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Bluetooth: Fix issues where sk_sleep() helper is needed now
[deliverable/linux.git] / drivers / net / gianfar.c
CommitLineData
0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
cc772ab7 85#include <linux/net_tstamp.h>
1da177e4
LT		 86
87#include <asm/io.h>
88#include <asm/irq.h>
89#include <asm/uaccess.h>
90#include <linux/module.h>
1da177e4
LT		 91#include <linux/dma-mapping.h>
92#include <linux/crc32.h>
bb40dcbb
AF		 93#include <linux/mii.h>
94#include <linux/phy.h>
b31a1d8b
AF		 95#include <linux/phy_fixed.h>
96#include <linux/of.h>
1da177e4
LT		 97
98#include "gianfar.h"
1577ecef 99#include "fsl_pq_mdio.h"
1da177e4
LT		 100
101#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 102#undef BRIEF_GFAR_ERRORS
103#undef VERBOSE_GFAR_ERRORS
104
1da177e4 105const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 106const char gfar_driver_version[] = "1.3";
1da177e4 107
1da177e4
LT		 108static int gfar_enet_open(struct net_device *dev);
109static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 110static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 111static void gfar_timeout(struct net_device *dev);
112static int gfar_close(struct net_device *dev);
815b97c6 113struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 114static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 115 struct sk_buff *skb);
1da177e4
LT		 116static int gfar_set_mac_address(struct net_device *dev);
117static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 118static irqreturn_t gfar_error(int irq, void *dev_id);
119static irqreturn_t gfar_transmit(int irq, void *dev_id);
120static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 121static void adjust_link(struct net_device *dev);
122static void init_registers(struct net_device *dev);
123static int init_phy(struct net_device *dev);
b31a1d8b
AF		 124static int gfar_probe(struct of_device *ofdev,
125 const struct of_device_id *match);
126static int gfar_remove(struct of_device *ofdev);
bb40dcbb 127static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 128static void gfar_set_multi(struct net_device *dev);
129static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 130static void gfar_configure_serdes(struct net_device *dev);
bea3348e 131static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 132#ifdef CONFIG_NET_POLL_CONTROLLER
133static void gfar_netpoll(struct net_device *dev);
134#endif
a12f801d
SG		 135int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
136static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 137static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
138 int amount_pull);
0bbaf069
KG		 139static void gfar_vlan_rx_register(struct net_device *netdev,
140 struct vlan_group *grp);
7f7f5316 141void gfar_halt(struct net_device *dev);
d87eb127 142static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 143void gfar_start(struct net_device *dev);
144static void gfar_clear_exact_match(struct net_device *dev);
145static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 146static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 147
1da177e4
LT		 148MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL");
151
a12f801d 152static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 153 dma_addr_t buf)
154{
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
fba4ed03 175 int i, j;
a12f801d 176
fba4ed03
SG		 177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
8728327e 193
fba4ed03
SG		 194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
8728327e
AV		 197 }
198
fba4ed03
SG		 199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
8728327e 204
fba4ed03
SG		 205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 207
fba4ed03
SG		 208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
214 pr_err("%s: Can't allocate RX buffers\n",
215 ndev->name);
216 goto err_rxalloc_fail;
217 }
218 rx_queue->rx_skbuff[j] = skb;
219
220 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 221 }
8728327e 222
fba4ed03 223 rxbdp++;
8728327e
AV		 224 }
225
8728327e
AV		 226 }
227
228 return 0;
fba4ed03
SG		 229
230err_rxalloc_fail:
231 free_skb_resources(priv);
232 return -ENOMEM;
8728327e
AV		 233}
234
235static int gfar_alloc_skb_resources(struct net_device *ndev)
236{
826aa4a0 237 void *vaddr;
fba4ed03
SG		 238 dma_addr_t addr;
239 int i, j, k;
826aa4a0
AV		 240 struct gfar_private *priv = netdev_priv(ndev);
241 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 242 struct gfar_priv_tx_q *tx_queue = NULL;
243 struct gfar_priv_rx_q *rx_queue = NULL;
244
fba4ed03
SG		 245 priv->total_tx_ring_size = 0;
246 for (i = 0; i < priv->num_tx_queues; i++)
247 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
248
249 priv->total_rx_ring_size = 0;
250 for (i = 0; i < priv->num_rx_queues; i++)
251 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 252
253 /* Allocate memory for the buffer descriptors */
8728327e 254 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 255 sizeof(struct txbd8) * priv->total_tx_ring_size +
256 sizeof(struct rxbd8) * priv->total_rx_ring_size,
257 &addr, GFP_KERNEL);
826aa4a0
AV		 258 if (!vaddr) {
259 if (netif_msg_ifup(priv))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
261 ndev->name);
262 return -ENOMEM;
263 }
264
fba4ed03
SG		 265 for (i = 0; i < priv->num_tx_queues; i++) {
266 tx_queue = priv->tx_queue[i];
267 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
268 tx_queue->tx_bd_dma_base = addr;
269 tx_queue->dev = ndev;
270 /* enet DMA only understands physical addresses */
271 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 }
826aa4a0 274
826aa4a0 275 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 276 for (i = 0; i < priv->num_rx_queues; i++) {
277 rx_queue = priv->rx_queue[i];
278 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
279 rx_queue->rx_bd_dma_base = addr;
280 rx_queue->dev = ndev;
281 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 }
826aa4a0
AV		 284
285 /* Setup the skbuff rings */
fba4ed03
SG		 286 for (i = 0; i < priv->num_tx_queues; i++) {
287 tx_queue = priv->tx_queue[i];
288 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 289 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 290 if (!tx_queue->tx_skbuff) {
291 if (netif_msg_ifup(priv))
292 pr_err("%s: Could not allocate tx_skbuff\n",
293 ndev->name);
294 goto cleanup;
295 }
826aa4a0 296
fba4ed03
SG		 297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
826aa4a0 300
fba4ed03
SG		 301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
303 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 304 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 305
fba4ed03
SG		 306 if (!rx_queue->rx_skbuff) {
307 if (netif_msg_ifup(priv))
308 pr_err("%s: Could not allocate rx_skbuff\n",
309 ndev->name);
310 goto cleanup;
311 }
312
313 for (j = 0; j < rx_queue->rx_ring_size; j++)
314 rx_queue->rx_skbuff[j] = NULL;
315 }
826aa4a0 316
8728327e
AV		 317 if (gfar_init_bds(ndev))
318 goto cleanup;
826aa4a0
AV		 319
320 return 0;
321
322cleanup:
323 free_skb_resources(priv);
324 return -ENOMEM;
325}
326
fba4ed03
SG		 327static void gfar_init_tx_rx_base(struct gfar_private *priv)
328{
46ceb60c 329 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 330 u32 __iomem *baddr;
fba4ed03
SG		 331 int i;
332
333 baddr = &regs->tbase0;
334 for(i = 0; i < priv->num_tx_queues; i++) {
335 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336 baddr += 2;
337 }
338
339 baddr = &regs->rbase0;
340 for(i = 0; i < priv->num_rx_queues; i++) {
341 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 baddr += 2;
343 }
344}
345
826aa4a0
AV		 346static void gfar_init_mac(struct net_device *ndev)
347{
348 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 349 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 350 u32 rctrl = 0;
351 u32 tctrl = 0;
352 u32 attrs = 0;
353
fba4ed03
SG		 354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv);
32c513bc 356
826aa4a0 357 /* Configure the coalescing support */
46ceb60c 358 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 359
1ccb8389 360 if (priv->rx_filer_enable) {
fba4ed03 361 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 362 /* Program the RIR0 reg with the required distribution */
363 gfar_write(&regs->rir0, DEFAULT_RIR0);
364 }
826aa4a0
AV		 365
366 if (priv->rx_csum_enable)
367 rctrl |= RCTRL_CHECKSUMMING;
368
369 if (priv->extended_hash) {
370 rctrl |= RCTRL_EXTHASH;
371
372 gfar_clear_exact_match(ndev);
373 rctrl |= RCTRL_EMEN;
374 }
375
376 if (priv->padding) {
377 rctrl &= ~RCTRL_PAL_MASK;
378 rctrl |= RCTRL_PADDING(priv->padding);
379 }
380
cc772ab7
MR		 381 /* Insert receive time stamps into padding alignment bytes */
382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
383 rctrl &= ~RCTRL_PAL_MASK;
384 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8);
385 priv->padding = 8;
386 }
387
826aa4a0
AV		 388 /* keep vlan related bits if it's enabled */
389 if (priv->vlgrp) {
390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
391 tctrl |= TCTRL_VLINS;
392 }
393
394 /* Init rctrl based on our settings */
395 gfar_write(&regs->rctrl, rctrl);
396
397 if (ndev->features & NETIF_F_IP_CSUM)
398 tctrl |= TCTRL_INIT_CSUM;
399
fba4ed03
SG		 400 tctrl |= TCTRL_TXSCHED_PRIO;
401
826aa4a0
AV		 402 gfar_write(&regs->tctrl, tctrl);
403
404 /* Set the extraction length and index */
405 attrs = ATTRELI_EL(priv->rx_stash_size) |
406 ATTRELI_EI(priv->rx_stash_index);
407
408 gfar_write(&regs->attreli, attrs);
409
410 /* Start with defaults, and add stashing or locking
411 * depending on the approprate variables */
412 attrs = ATTR_INIT_SETTINGS;
413
414 if (priv->bd_stash_en)
415 attrs |= ATTR_BDSTASH;
416
417 if (priv->rx_stash_size != 0)
418 attrs |= ATTR_BUFSTASH;
419
420 gfar_write(&regs->attr, attrs);
421
422 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
423 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
424 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
425}
426
a7f38041
SG		 427static struct net_device_stats *gfar_get_stats(struct net_device *dev)
428{
429 struct gfar_private *priv = netdev_priv(dev);
430 struct netdev_queue *txq;
431 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
432 unsigned long tx_packets = 0, tx_bytes = 0;
433 int i = 0;
434
435 for (i = 0; i < priv->num_rx_queues; i++) {
436 rx_packets += priv->rx_queue[i]->stats.rx_packets;
437 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
438 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
439 }
440
441 dev->stats.rx_packets = rx_packets;
442 dev->stats.rx_bytes = rx_bytes;
443 dev->stats.rx_dropped = rx_dropped;
444
445 for (i = 0; i < priv->num_tx_queues; i++) {
446 txq = netdev_get_tx_queue(dev, i);
447 tx_bytes += txq->tx_bytes;
448 tx_packets += txq->tx_packets;
449 }
450
451 dev->stats.tx_bytes = tx_bytes;
452 dev->stats.tx_packets = tx_packets;
453
454 return &dev->stats;
455}
456
26ccfc37
AF		 457static const struct net_device_ops gfar_netdev_ops = {
458 .ndo_open = gfar_enet_open,
459 .ndo_start_xmit = gfar_start_xmit,
460 .ndo_stop = gfar_close,
461 .ndo_change_mtu = gfar_change_mtu,
462 .ndo_set_multicast_list = gfar_set_multi,
463 .ndo_tx_timeout = gfar_timeout,
464 .ndo_do_ioctl = gfar_ioctl,
a7f38041 465 .ndo_get_stats = gfar_get_stats,
26ccfc37 466 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 467 .ndo_set_mac_address = eth_mac_addr,
468 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 469#ifdef CONFIG_NET_POLL_CONTROLLER
470 .ndo_poll_controller = gfar_netpoll,
471#endif
472};
473
7a8b3372
SG		 474unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
475unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
476
fba4ed03
SG		 477void lock_rx_qs(struct gfar_private *priv)
478{
479 int i = 0x0;
480
481 for (i = 0; i < priv->num_rx_queues; i++)
482 spin_lock(&priv->rx_queue[i]->rxlock);
483}
484
485void lock_tx_qs(struct gfar_private *priv)
486{
487 int i = 0x0;
488
489 for (i = 0; i < priv->num_tx_queues; i++)
490 spin_lock(&priv->tx_queue[i]->txlock);
491}
492
493void unlock_rx_qs(struct gfar_private *priv)
494{
495 int i = 0x0;
496
497 for (i = 0; i < priv->num_rx_queues; i++)
498 spin_unlock(&priv->rx_queue[i]->rxlock);
499}
500
501void unlock_tx_qs(struct gfar_private *priv)
502{
503 int i = 0x0;
504
505 for (i = 0; i < priv->num_tx_queues; i++)
506 spin_unlock(&priv->tx_queue[i]->txlock);
507}
508
7f7f5316
AF		 509/* Returns 1 if incoming frames use an FCB */
510static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 511{
cc772ab7
MR		 512 return priv->vlgrp || priv->rx_csum_enable ||
513 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 514}
bb40dcbb 515
fba4ed03
SG		 516static void free_tx_pointers(struct gfar_private *priv)
517{
518 int i = 0;
519
520 for (i = 0; i < priv->num_tx_queues; i++)
521 kfree(priv->tx_queue[i]);
522}
523
524static void free_rx_pointers(struct gfar_private *priv)
525{
526 int i = 0;
527
528 for (i = 0; i < priv->num_rx_queues; i++)
529 kfree(priv->rx_queue[i]);
530}
531
46ceb60c
SG		 532static void unmap_group_regs(struct gfar_private *priv)
533{
534 int i = 0;
535
536 for (i = 0; i < MAXGROUPS; i++)
537 if (priv->gfargrp[i].regs)
538 iounmap(priv->gfargrp[i].regs);
539}
540
541static void disable_napi(struct gfar_private *priv)
542{
543 int i = 0;
544
545 for (i = 0; i < priv->num_grps; i++)
546 napi_disable(&priv->gfargrp[i].napi);
547}
548
549static void enable_napi(struct gfar_private *priv)
550{
551 int i = 0;
552
553 for (i = 0; i < priv->num_grps; i++)
554 napi_enable(&priv->gfargrp[i].napi);
555}
556
557static int gfar_parse_group(struct device_node *np,
558 struct gfar_private *priv, const char *model)
559{
560 u32 *queue_mask;
46ceb60c 561
7ce97d4f 562 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 563 if (!priv->gfargrp[priv->num_grps].regs)
564 return -ENOMEM;
565
566 priv->gfargrp[priv->num_grps].interruptTransmit =
567 irq_of_parse_and_map(np, 0);
568
569 /* If we aren't the FEC we have multiple interrupts */
570 if (model && strcasecmp(model, "FEC")) {
571 priv->gfargrp[priv->num_grps].interruptReceive =
572 irq_of_parse_and_map(np, 1);
573 priv->gfargrp[priv->num_grps].interruptError =
574 irq_of_parse_and_map(np,2);
575 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
576 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
577 priv->gfargrp[priv->num_grps].interruptError < 0) {
578 return -EINVAL;
579 }
580 }
581
582 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
583 priv->gfargrp[priv->num_grps].priv = priv;
584 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
585 if(priv->mode == MQ_MG_MODE) {
586 queue_mask = (u32 *)of_get_property(np,
587 "fsl,rx-bit-map", NULL);
588 priv->gfargrp[priv->num_grps].rx_bit_map =
589 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
590 queue_mask = (u32 *)of_get_property(np,
591 "fsl,tx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].tx_bit_map =
593 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
594 } else {
595 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
596 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
597 }
598 priv->num_grps++;
599
600 return 0;
601}
602
fba4ed03 603static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
b31a1d8b 604{
b31a1d8b
AF		 605 const char *model;
606 const char *ctype;
607 const void *mac_addr;
fba4ed03
SG		 608 int err = 0, i;
609 struct net_device *dev = NULL;
610 struct gfar_private *priv = NULL;
611 struct device_node *np = ofdev->node;
46ceb60c 612 struct device_node *child = NULL;
4d7902f2
AF		 613 const u32 *stash;
614 const u32 *stash_len;
615 const u32 *stash_idx;
fba4ed03
SG		 616 unsigned int num_tx_qs, num_rx_qs;
617 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 618
619 if (!np || !of_device_is_available(np))
620 return -ENODEV;
621
fba4ed03
SG		 622 /* parse the num of tx and rx queues */
623 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
624 num_tx_qs = tx_queues ? *tx_queues : 1;
625
626 if (num_tx_qs > MAX_TX_QS) {
627 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
628 num_tx_qs, MAX_TX_QS);
629 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
630 return -EINVAL;
631 }
632
633 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
634 num_rx_qs = rx_queues ? *rx_queues : 1;
635
636 if (num_rx_qs > MAX_RX_QS) {
637 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
638 num_tx_qs, MAX_TX_QS);
639 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
640 return -EINVAL;
641 }
642
643 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
644 dev = *pdev;
645 if (NULL == dev)
646 return -ENOMEM;
647
648 priv = netdev_priv(dev);
649 priv->node = ofdev->node;
650 priv->ndev = dev;
651
652 dev->num_tx_queues = num_tx_qs;
653 dev->real_num_tx_queues = num_tx_qs;
654 priv->num_tx_queues = num_tx_qs;
655 priv->num_rx_queues = num_rx_qs;
46ceb60c 656 priv->num_grps = 0x0;
b31a1d8b
AF		 657
658 model = of_get_property(np, "model", NULL);
659
46ceb60c
SG		 660 for (i = 0; i < MAXGROUPS; i++)
661 priv->gfargrp[i].regs = NULL;
b31a1d8b 662
46ceb60c
SG		 663 /* Parse and initialize group specific information */
664 if (of_device_is_compatible(np, "fsl,etsec2")) {
665 priv->mode = MQ_MG_MODE;
666 for_each_child_of_node(np, child) {
667 err = gfar_parse_group(child, priv, model);
668 if (err)
669 goto err_grp_init;
b31a1d8b 670 }
46ceb60c
SG		 671 } else {
672 priv->mode = SQ_SG_MODE;
673 err = gfar_parse_group(np, priv, model);
674 if(err)
675 goto err_grp_init;
b31a1d8b
AF		 676 }
677
fba4ed03
SG		 678 for (i = 0; i < priv->num_tx_queues; i++)
679 priv->tx_queue[i] = NULL;
680 for (i = 0; i < priv->num_rx_queues; i++)
681 priv->rx_queue[i] = NULL;
682
683 for (i = 0; i < priv->num_tx_queues; i++) {
ed130589 684 priv->tx_queue[i] = (struct gfar_priv_tx_q *)kzalloc(
fba4ed03
SG		 685 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
686 if (!priv->tx_queue[i]) {
687 err = -ENOMEM;
688 goto tx_alloc_failed;
689 }
690 priv->tx_queue[i]->tx_skbuff = NULL;
691 priv->tx_queue[i]->qindex = i;
692 priv->tx_queue[i]->dev = dev;
693 spin_lock_init(&(priv->tx_queue[i]->txlock));
694 }
695
696 for (i = 0; i < priv->num_rx_queues; i++) {
ed130589 697 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
fba4ed03
SG		 698 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
699 if (!priv->rx_queue[i]) {
700 err = -ENOMEM;
701 goto rx_alloc_failed;
702 }
703 priv->rx_queue[i]->rx_skbuff = NULL;
704 priv->rx_queue[i]->qindex = i;
705 priv->rx_queue[i]->dev = dev;
706 spin_lock_init(&(priv->rx_queue[i]->rxlock));
707 }
708
709
4d7902f2
AF		 710 stash = of_get_property(np, "bd-stash", NULL);
711
a12f801d 712 if (stash) {
4d7902f2
AF		 713 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
714 priv->bd_stash_en = 1;
715 }
716
717 stash_len = of_get_property(np, "rx-stash-len", NULL);
718
719 if (stash_len)
720 priv->rx_stash_size = *stash_len;
721
722 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
723
724 if (stash_idx)
725 priv->rx_stash_index = *stash_idx;
726
727 if (stash_len || stash_idx)
728 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
729
b31a1d8b
AF		 730 mac_addr = of_get_mac_address(np);
731 if (mac_addr)
732 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
733
734 if (model && !strcasecmp(model, "TSEC"))
735 priv->device_flags =
736 FSL_GIANFAR_DEV_HAS_GIGABIT |
737 FSL_GIANFAR_DEV_HAS_COALESCE |
738 FSL_GIANFAR_DEV_HAS_RMON |
739 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
740 if (model && !strcasecmp(model, "eTSEC"))
741 priv->device_flags =
742 FSL_GIANFAR_DEV_HAS_GIGABIT |
743 FSL_GIANFAR_DEV_HAS_COALESCE |
744 FSL_GIANFAR_DEV_HAS_RMON |
745 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 746 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 747 FSL_GIANFAR_DEV_HAS_CSUM |
748 FSL_GIANFAR_DEV_HAS_VLAN |
749 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
cc772ab7
MR		 750 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
751 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 752
753 ctype = of_get_property(np, "phy-connection-type", NULL);
754
755 /* We only care about rgmii-id. The rest are autodetected */
756 if (ctype && !strcmp(ctype, "rgmii-id"))
757 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
758 else
759 priv->interface = PHY_INTERFACE_MODE_MII;
760
761 if (of_get_property(np, "fsl,magic-packet", NULL))
762 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
763
fe192a49 764 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 765
766 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 767 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 768
769 return 0;
770
fba4ed03
SG		 771rx_alloc_failed:
772 free_rx_pointers(priv);
773tx_alloc_failed:
774 free_tx_pointers(priv);
46ceb60c
SG		 775err_grp_init:
776 unmap_group_regs(priv);
fba4ed03 777 free_netdev(dev);
b31a1d8b
AF		 778 return err;
779}
780
cc772ab7
MR		 781static int gfar_hwtstamp_ioctl(struct net_device *netdev,
782 struct ifreq *ifr, int cmd)
783{
784 struct hwtstamp_config config;
785 struct gfar_private *priv = netdev_priv(netdev);
786
787 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
788 return -EFAULT;
789
790 /* reserved for future extensions */
791 if (config.flags)
792 return -EINVAL;
793
f0ee7acf
MR		 794 switch (config.tx_type) {
795 case HWTSTAMP_TX_OFF:
796 priv->hwts_tx_en = 0;
797 break;
798 case HWTSTAMP_TX_ON:
799 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
800 return -ERANGE;
801 priv->hwts_tx_en = 1;
802 break;
803 default:
cc772ab7 804 return -ERANGE;
f0ee7acf 805 }
cc772ab7
MR		 806
807 switch (config.rx_filter) {
808 case HWTSTAMP_FILTER_NONE:
809 priv->hwts_rx_en = 0;
810 break;
811 default:
812 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
813 return -ERANGE;
814 priv->hwts_rx_en = 1;
815 config.rx_filter = HWTSTAMP_FILTER_ALL;
816 break;
817 }
818
819 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
820 -EFAULT : 0;
821}
822
0faac9f7
CW		 823/* Ioctl MII Interface */
824static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
825{
826 struct gfar_private *priv = netdev_priv(dev);
827
828 if (!netif_running(dev))
829 return -EINVAL;
830
cc772ab7
MR		 831 if (cmd == SIOCSHWTSTAMP)
832 return gfar_hwtstamp_ioctl(dev, rq, cmd);
833
0faac9f7
CW		 834 if (!priv->phydev)
835 return -ENODEV;
836
837 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
838}
839
fba4ed03
SG		 840static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
841{
842 unsigned int new_bit_map = 0x0;
843 int mask = 0x1 << (max_qs - 1), i;
844 for (i = 0; i < max_qs; i++) {
845 if (bit_map & mask)
846 new_bit_map = new_bit_map + (1 << i);
847 mask = mask >> 0x1;
848 }
849 return new_bit_map;
850}
7a8b3372 851
18294ad1
AV		 852static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
853 u32 class)
7a8b3372
SG		 854{
855 u32 rqfpr = FPR_FILER_MASK;
856 u32 rqfcr = 0x0;
857
858 rqfar--;
859 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
860 ftp_rqfpr[rqfar] = rqfpr;
861 ftp_rqfcr[rqfar] = rqfcr;
862 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
863
864 rqfar--;
865 rqfcr = RQFCR_CMP_NOMATCH;
866 ftp_rqfpr[rqfar] = rqfpr;
867 ftp_rqfcr[rqfar] = rqfcr;
868 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
869
870 rqfar--;
871 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
872 rqfpr = class;
873 ftp_rqfcr[rqfar] = rqfcr;
874 ftp_rqfpr[rqfar] = rqfpr;
875 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
876
877 rqfar--;
878 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
879 rqfpr = class;
880 ftp_rqfcr[rqfar] = rqfcr;
881 ftp_rqfpr[rqfar] = rqfpr;
882 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
883
884 return rqfar;
885}
886
887static void gfar_init_filer_table(struct gfar_private *priv)
888{
889 int i = 0x0;
890 u32 rqfar = MAX_FILER_IDX;
891 u32 rqfcr = 0x0;
892 u32 rqfpr = FPR_FILER_MASK;
893
894 /* Default rule */
895 rqfcr = RQFCR_CMP_MATCH;
896 ftp_rqfcr[rqfar] = rqfcr;
897 ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899
900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
903 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
904 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
905 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
906
907 /* cur_filer_idx indicated the fisrt non-masked rule */
908 priv->cur_filer_idx = rqfar;
909
910 /* Rest are masked rules */
911 rqfcr = RQFCR_CMP_NOMATCH;
912 for (i = 0; i < rqfar; i++) {
913 ftp_rqfcr[i] = rqfcr;
914 ftp_rqfpr[i] = rqfpr;
915 gfar_write_filer(priv, i, rqfcr, rqfpr);
916 }
917}
918
bb40dcbb
AF		 919/* Set up the ethernet device structure, private data,
920 * and anything else we need before we start */
b31a1d8b
AF		 921static int gfar_probe(struct of_device *ofdev,
922 const struct of_device_id *match)
1da177e4
LT		 923{
924 u32 tempval;
925 struct net_device *dev = NULL;
926 struct gfar_private *priv = NULL;
f4983704 927 struct gfar __iomem *regs = NULL;
46ceb60c 928 int err = 0, i, grp_idx = 0;
c50a5d9a 929 int len_devname;
fba4ed03 930 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 931 u32 isrg = 0;
18294ad1 932 u32 __iomem *baddr;
1da177e4 933
fba4ed03 934 err = gfar_of_init(ofdev, &dev);
1da177e4 935
fba4ed03
SG		 936 if (err)
937 return err;
1da177e4
LT		 938
939 priv = netdev_priv(dev);
4826857f
KG		 940 priv->ndev = dev;
941 priv->ofdev = ofdev;
b31a1d8b 942 priv->node = ofdev->node;
4826857f 943 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 944
d87eb127 945 spin_lock_init(&priv->bflock);
ab939905 946 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 947
b31a1d8b 948 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 949 regs = priv->gfargrp[0].regs;
1da177e4
LT		 950
951 /* Stop the DMA engine now, in case it was running before */
952 /* (The firmware could have used it, and left it running). */
257d938a 953 gfar_halt(dev);
1da177e4
LT		 954
955 /* Reset MAC layer */
f4983704 956 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 957
b98ac702
AF		 958 /* We need to delay at least 3 TX clocks */
959 udelay(2);
960
1da177e4 961 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 962 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 963
964 /* Initialize MACCFG2. */
f4983704 965 gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
1da177e4
LT		 966
967 /* Initialize ECNTRL */
f4983704 968 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 969
1da177e4 970 /* Set the dev->base_addr to the gfar reg region */
f4983704 971 dev->base_addr = (unsigned long) regs;
1da177e4 972
b31a1d8b 973 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 974
975 /* Fill in the dev structure */
1da177e4 976 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 977 dev->mtu = 1500;
26ccfc37 978 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 979 dev->ethtool_ops = &gfar_ethtool_ops;
980
fba4ed03 981 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 982 for (i = 0; i < priv->num_grps; i++)
983 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 984
b31a1d8b 985 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 986 priv->rx_csum_enable = 1;
4669bc90 987 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 988 } else
989 priv->rx_csum_enable = 0;
990
991 priv->vlgrp = NULL;
1da177e4 992
26ccfc37 993 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 994 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 995
b31a1d8b 996 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 997 priv->extended_hash = 1;
998 priv->hash_width = 9;
999
f4983704
SG		 1000 priv->hash_regs[0] = &regs->igaddr0;
1001 priv->hash_regs[1] = &regs->igaddr1;
1002 priv->hash_regs[2] = &regs->igaddr2;
1003 priv->hash_regs[3] = &regs->igaddr3;
1004 priv->hash_regs[4] = &regs->igaddr4;
1005 priv->hash_regs[5] = &regs->igaddr5;
1006 priv->hash_regs[6] = &regs->igaddr6;
1007 priv->hash_regs[7] = &regs->igaddr7;
1008 priv->hash_regs[8] = &regs->gaddr0;
1009 priv->hash_regs[9] = &regs->gaddr1;
1010 priv->hash_regs[10] = &regs->gaddr2;
1011 priv->hash_regs[11] = &regs->gaddr3;
1012 priv->hash_regs[12] = &regs->gaddr4;
1013 priv->hash_regs[13] = &regs->gaddr5;
1014 priv->hash_regs[14] = &regs->gaddr6;
1015 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1016
1017 } else {
1018 priv->extended_hash = 0;
1019 priv->hash_width = 8;
1020
f4983704
SG		 1021 priv->hash_regs[0] = &regs->gaddr0;
1022 priv->hash_regs[1] = &regs->gaddr1;
1023 priv->hash_regs[2] = &regs->gaddr2;
1024 priv->hash_regs[3] = &regs->gaddr3;
1025 priv->hash_regs[4] = &regs->gaddr4;
1026 priv->hash_regs[5] = &regs->gaddr5;
1027 priv->hash_regs[6] = &regs->gaddr6;
1028 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1029 }
1030
b31a1d8b 1031 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1032 priv->padding = DEFAULT_PADDING;
1033 else
1034 priv->padding = 0;
1035
cc772ab7
MR		 1036 if (dev->features & NETIF_F_IP_CSUM ||
1037 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
0bbaf069 1038 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 1039
46ceb60c
SG		 1040 /* Program the isrg regs only if number of grps > 1 */
1041 if (priv->num_grps > 1) {
1042 baddr = &regs->isrg0;
1043 for (i = 0; i < priv->num_grps; i++) {
1044 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1045 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1046 gfar_write(baddr, isrg);
1047 baddr++;
1048 isrg = 0x0;
1049 }
1050 }
1051
fba4ed03 1052 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1053 * but, for_each_set_bit parses from right to left, which
fba4ed03 1054 * basically reverses the queue numbers */
46ceb60c
SG		 1055 for (i = 0; i< priv->num_grps; i++) {
1056 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1057 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1058 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1059 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1060 }
1061
1062 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1063 * also assign queues to groups */
1064 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1065 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1066 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1067 priv->num_rx_queues) {
1068 priv->gfargrp[grp_idx].num_rx_queues++;
1069 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1070 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1071 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1072 }
1073 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1074 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1075 priv->num_tx_queues) {
1076 priv->gfargrp[grp_idx].num_tx_queues++;
1077 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1078 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1079 tqueue = tqueue | (TQUEUE_EN0 >> i);
1080 }
1081 priv->gfargrp[grp_idx].rstat = rstat;
1082 priv->gfargrp[grp_idx].tstat = tstat;
1083 rstat = tstat =0;
fba4ed03 1084 }
fba4ed03
SG		 1085
1086 gfar_write(&regs->rqueue, rqueue);
1087 gfar_write(&regs->tqueue, tqueue);
1088
1da177e4 1089 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1090
a12f801d 1091 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1092 for (i = 0; i < priv->num_tx_queues; i++) {
1093 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1094 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1095 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1096 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1097 }
a12f801d 1098
fba4ed03
SG		 1099 for (i = 0; i < priv->num_rx_queues; i++) {
1100 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1101 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1102 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1103 }
1da177e4 1104
1ccb8389
SG		 1105 /* enable filer if using multiple RX queues*/
1106 if(priv->num_rx_queues > 1)
1107 priv->rx_filer_enable = 1;
0bbaf069
KG		 1108 /* Enable most messages by default */
1109 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1110
d3eab82b
TP		 1111 /* Carrier starts down, phylib will bring it up */
1112 netif_carrier_off(dev);
1113
1da177e4
LT		 1114 err = register_netdev(dev);
1115
1116 if (err) {
1117 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1118 dev->name);
1119 goto register_fail;
1120 }
1121
2884e5cc
AV		 1122 device_init_wakeup(&dev->dev,
1123 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1124
c50a5d9a
DH		 1125 /* fill out IRQ number and name fields */
1126 len_devname = strlen(dev->name);
46ceb60c
SG		 1127 for (i = 0; i < priv->num_grps; i++) {
1128 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1129 len_devname);
1130 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1131 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1132 "_g", sizeof("_g"));
1133 priv->gfargrp[i].int_name_tx[
1134 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1135 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1136 priv->gfargrp[i].int_name_tx)],
1137 "_tx", sizeof("_tx") + 1);
1138
1139 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1140 len_devname);
1141 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1142 "_g", sizeof("_g"));
1143 priv->gfargrp[i].int_name_rx[
1144 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1145 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1146 priv->gfargrp[i].int_name_rx)],
1147 "_rx", sizeof("_rx") + 1);
1148
1149 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1150 len_devname);
1151 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1152 "_g", sizeof("_g"));
1153 priv->gfargrp[i].int_name_er[strlen(
1154 priv->gfargrp[i].int_name_er)] = i+48;
1155 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1156 priv->gfargrp[i].int_name_er)],
1157 "_er", sizeof("_er") + 1);
1158 } else
1159 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1160 }
c50a5d9a 1161
7a8b3372
SG		 1162 /* Initialize the filer table */
1163 gfar_init_filer_table(priv);
1164
7f7f5316
AF		 1165 /* Create all the sysfs files */
1166 gfar_init_sysfs(dev);
1167
1da177e4 1168 /* Print out the device info */
e174961c 1169 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1170
1171 /* Even more device info helps when determining which kernel */
7f7f5316 1172 /* provided which set of benchmarks. */
1da177e4 1173 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03 1174 for (i = 0; i < priv->num_rx_queues; i++)
ddc01b3b 1175 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
fba4ed03
SG		 1176 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1177 for(i = 0; i < priv->num_tx_queues; i++)
ddc01b3b 1178 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
fba4ed03 1179 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1180
1181 return 0;
1182
1183register_fail:
46ceb60c 1184 unmap_group_regs(priv);
fba4ed03
SG		 1185 free_tx_pointers(priv);
1186 free_rx_pointers(priv);
fe192a49
GL		 1187 if (priv->phy_node)
1188 of_node_put(priv->phy_node);
1189 if (priv->tbi_node)
1190 of_node_put(priv->tbi_node);
1da177e4 1191 free_netdev(dev);
bb40dcbb 1192 return err;
1da177e4
LT		 1193}
1194
b31a1d8b 1195static int gfar_remove(struct of_device *ofdev)
1da177e4 1196{
b31a1d8b 1197 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1198
fe192a49
GL		 1199 if (priv->phy_node)
1200 of_node_put(priv->phy_node);
1201 if (priv->tbi_node)
1202 of_node_put(priv->tbi_node);
1203
b31a1d8b 1204 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1205
d9d8e041 1206 unregister_netdev(priv->ndev);
46ceb60c 1207 unmap_group_regs(priv);
4826857f 1208 free_netdev(priv->ndev);
1da177e4
LT		 1209
1210 return 0;
1211}
1212
d87eb127 1213#ifdef CONFIG_PM
be926fc4
AV		 1214
1215static int gfar_suspend(struct device *dev)
d87eb127 1216{
be926fc4
AV		 1217 struct gfar_private *priv = dev_get_drvdata(dev);
1218 struct net_device *ndev = priv->ndev;
46ceb60c 1219 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1220 unsigned long flags;
1221 u32 tempval;
1222
1223 int magic_packet = priv->wol_en &&
b31a1d8b 1224 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1225
be926fc4 1226 netif_device_detach(ndev);
d87eb127 1227
be926fc4 1228 if (netif_running(ndev)) {
fba4ed03
SG		 1229
1230 local_irq_save(flags);
1231 lock_tx_qs(priv);
1232 lock_rx_qs(priv);
d87eb127 1233
be926fc4 1234 gfar_halt_nodisable(ndev);
d87eb127
SW		 1235
1236 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1237 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1238
1239 tempval &= ~MACCFG1_TX_EN;
1240
1241 if (!magic_packet)
1242 tempval &= ~MACCFG1_RX_EN;
1243
f4983704 1244 gfar_write(&regs->maccfg1, tempval);
d87eb127 1245
fba4ed03
SG		 1246 unlock_rx_qs(priv);
1247 unlock_tx_qs(priv);
1248 local_irq_restore(flags);
d87eb127 1249
46ceb60c 1250 disable_napi(priv);
d87eb127
SW		 1251
1252 if (magic_packet) {
1253 /* Enable interrupt on Magic Packet */
f4983704 1254 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1255
1256 /* Enable Magic Packet mode */
f4983704 1257 tempval = gfar_read(&regs->maccfg2);
d87eb127 1258 tempval |= MACCFG2_MPEN;
f4983704 1259 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1260 } else {
1261 phy_stop(priv->phydev);
1262 }
1263 }
1264
1265 return 0;
1266}
1267
be926fc4 1268static int gfar_resume(struct device *dev)
d87eb127 1269{
be926fc4
AV		 1270 struct gfar_private *priv = dev_get_drvdata(dev);
1271 struct net_device *ndev = priv->ndev;
46ceb60c 1272 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1273 unsigned long flags;
1274 u32 tempval;
1275 int magic_packet = priv->wol_en &&
b31a1d8b 1276 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1277
be926fc4
AV		 1278 if (!netif_running(ndev)) {
1279 netif_device_attach(ndev);
d87eb127
SW		 1280 return 0;
1281 }
1282
1283 if (!magic_packet && priv->phydev)
1284 phy_start(priv->phydev);
1285
1286 /* Disable Magic Packet mode, in case something
1287 * else woke us up.
1288 */
fba4ed03
SG		 1289 local_irq_save(flags);
1290 lock_tx_qs(priv);
1291 lock_rx_qs(priv);
d87eb127 1292
f4983704 1293 tempval = gfar_read(&regs->maccfg2);
d87eb127 1294 tempval &= ~MACCFG2_MPEN;
f4983704 1295 gfar_write(&regs->maccfg2, tempval);
d87eb127 1296
be926fc4 1297 gfar_start(ndev);
d87eb127 1298
fba4ed03
SG		 1299 unlock_rx_qs(priv);
1300 unlock_tx_qs(priv);
1301 local_irq_restore(flags);
d87eb127 1302
be926fc4
AV		 1303 netif_device_attach(ndev);
1304
46ceb60c 1305 enable_napi(priv);
be926fc4
AV		 1306
1307 return 0;
1308}
1309
1310static int gfar_restore(struct device *dev)
1311{
1312 struct gfar_private *priv = dev_get_drvdata(dev);
1313 struct net_device *ndev = priv->ndev;
1314
1315 if (!netif_running(ndev))
1316 return 0;
1317
1318 gfar_init_bds(ndev);
1319 init_registers(ndev);
1320 gfar_set_mac_address(ndev);
1321 gfar_init_mac(ndev);
1322 gfar_start(ndev);
1323
1324 priv->oldlink = 0;
1325 priv->oldspeed = 0;
1326 priv->oldduplex = -1;
1327
1328 if (priv->phydev)
1329 phy_start(priv->phydev);
d87eb127 1330
be926fc4 1331 netif_device_attach(ndev);
5ea681d4 1332 enable_napi(priv);
d87eb127
SW		 1333
1334 return 0;
1335}
be926fc4
AV		 1336
1337static struct dev_pm_ops gfar_pm_ops = {
1338 .suspend = gfar_suspend,
1339 .resume = gfar_resume,
1340 .freeze = gfar_suspend,
1341 .thaw = gfar_resume,
1342 .restore = gfar_restore,
1343};
1344
1345#define GFAR_PM_OPS (&gfar_pm_ops)
1346
1347static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1348{
1349 return gfar_suspend(&ofdev->dev);
1350}
1351
1352static int gfar_legacy_resume(struct of_device *ofdev)
1353{
1354 return gfar_resume(&ofdev->dev);
1355}
1356
d87eb127 1357#else
be926fc4
AV		 1358
1359#define GFAR_PM_OPS NULL
1360#define gfar_legacy_suspend NULL
1361#define gfar_legacy_resume NULL
1362
d87eb127 1363#endif
1da177e4 1364
e8a2b6a4
AF		 1365/* Reads the controller's registers to determine what interface
1366 * connects it to the PHY.
1367 */
1368static phy_interface_t gfar_get_interface(struct net_device *dev)
1369{
1370 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1371 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1372 u32 ecntrl;
1373
f4983704 1374 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1375
1376 if (ecntrl & ECNTRL_SGMII_MODE)
1377 return PHY_INTERFACE_MODE_SGMII;
1378
1379 if (ecntrl & ECNTRL_TBI_MODE) {
1380 if (ecntrl & ECNTRL_REDUCED_MODE)
1381 return PHY_INTERFACE_MODE_RTBI;
1382 else
1383 return PHY_INTERFACE_MODE_TBI;
1384 }
1385
1386 if (ecntrl & ECNTRL_REDUCED_MODE) {
1387 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1388 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1389 else {
b31a1d8b 1390 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1391
1392 /*
1393 * This isn't autodetected right now, so it must
1394 * be set by the device tree or platform code.
1395 */
1396 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1397 return PHY_INTERFACE_MODE_RGMII_ID;
1398
e8a2b6a4 1399 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1400 }
e8a2b6a4
AF		 1401 }
1402
b31a1d8b 1403 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1404 return PHY_INTERFACE_MODE_GMII;
1405
1406 return PHY_INTERFACE_MODE_MII;
1407}
1408
1409
bb40dcbb
AF		 1410/* Initializes driver's PHY state, and attaches to the PHY.
1411 * Returns 0 on success.
1da177e4
LT		 1412 */
1413static int init_phy(struct net_device *dev)
1414{
1415 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1416 uint gigabit_support =
b31a1d8b 1417 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1418 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1419 phy_interface_t interface;
1da177e4
LT		 1420
1421 priv->oldlink = 0;
1422 priv->oldspeed = 0;
1423 priv->oldduplex = -1;
1424
e8a2b6a4
AF		 1425 interface = gfar_get_interface(dev);
1426
1db780f8
AV		 1427 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1428 interface);
1429 if (!priv->phydev)
1430 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1431 interface);
1432 if (!priv->phydev) {
1433 dev_err(&dev->dev, "could not attach to PHY\n");
1434 return -ENODEV;
fe192a49 1435 }
1da177e4 1436
d3c12873
KJ		 1437 if (interface == PHY_INTERFACE_MODE_SGMII)
1438 gfar_configure_serdes(dev);
1439
bb40dcbb 1440 /* Remove any features not supported by the controller */
fe192a49
GL		 1441 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1442 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1443
1444 return 0;
1da177e4
LT		 1445}
1446
d0313587
PG		 1447/*
1448 * Initialize TBI PHY interface for communicating with the
1449 * SERDES lynx PHY on the chip. We communicate with this PHY
1450 * through the MDIO bus on each controller, treating it as a
1451 * "normal" PHY at the address found in the TBIPA register. We assume
1452 * that the TBIPA register is valid. Either the MDIO bus code will set
1453 * it to a value that doesn't conflict with other PHYs on the bus, or the
1454 * value doesn't matter, as there are no other PHYs on the bus.
1455 */
d3c12873
KJ		 1456static void gfar_configure_serdes(struct net_device *dev)
1457{
1458 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1459 struct phy_device *tbiphy;
1460
1461 if (!priv->tbi_node) {
1462 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1463 "device tree specify a tbi-handle\n");
1464 return;
1465 }
c132419e 1466
fe192a49
GL		 1467 tbiphy = of_phy_find_device(priv->tbi_node);
1468 if (!tbiphy) {
1469 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1470 return;
1471 }
d3c12873 1472
b31a1d8b
AF		 1473 /*
1474 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1475 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1476 * everything for us? Resetting it takes the link down and requires
1477 * several seconds for it to come back.
1478 */
fe192a49 1479 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1480 return;
d3c12873 1481
d0313587 1482 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1483 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1484
fe192a49 1485 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1486 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1487 ADVERTISE_1000XPSE_ASYM);
1488
fe192a49 1489 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1490 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1491}
1492
1da177e4
LT		 1493static void init_registers(struct net_device *dev)
1494{
1495 struct gfar_private *priv = netdev_priv(dev);
f4983704 1496 struct gfar __iomem *regs = NULL;
46ceb60c 1497 int i = 0;
1da177e4 1498
46ceb60c
SG		 1499 for (i = 0; i < priv->num_grps; i++) {
1500 regs = priv->gfargrp[i].regs;
1501 /* Clear IEVENT */
1502 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1503
46ceb60c
SG		 1504 /* Initialize IMASK */
1505 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1506 }
1da177e4 1507
46ceb60c 1508 regs = priv->gfargrp[0].regs;
1da177e4 1509 /* Init hash registers to zero */
f4983704
SG		 1510 gfar_write(&regs->igaddr0, 0);
1511 gfar_write(&regs->igaddr1, 0);
1512 gfar_write(&regs->igaddr2, 0);
1513 gfar_write(&regs->igaddr3, 0);
1514 gfar_write(&regs->igaddr4, 0);
1515 gfar_write(&regs->igaddr5, 0);
1516 gfar_write(&regs->igaddr6, 0);
1517 gfar_write(&regs->igaddr7, 0);
1518
1519 gfar_write(&regs->gaddr0, 0);
1520 gfar_write(&regs->gaddr1, 0);
1521 gfar_write(&regs->gaddr2, 0);
1522 gfar_write(&regs->gaddr3, 0);
1523 gfar_write(&regs->gaddr4, 0);
1524 gfar_write(&regs->gaddr5, 0);
1525 gfar_write(&regs->gaddr6, 0);
1526 gfar_write(&regs->gaddr7, 0);
1da177e4 1527
1da177e4 1528 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1529 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1530 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1531
1532 /* Mask off the CAM interrupts */
f4983704
SG		 1533 gfar_write(&regs->rmon.cam1, 0xffffffff);
1534 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1535 }
1536
1537 /* Initialize the max receive buffer length */
f4983704 1538 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1539
1da177e4 1540 /* Initialize the Minimum Frame Length Register */
f4983704 1541 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1542}
1543
0bbaf069
KG		 1544
1545/* Halt the receive and transmit queues */
d87eb127 1546static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1547{
1548 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1549 struct gfar __iomem *regs = NULL;
1da177e4 1550 u32 tempval;
46ceb60c 1551 int i = 0;
1da177e4 1552
46ceb60c
SG		 1553 for (i = 0; i < priv->num_grps; i++) {
1554 regs = priv->gfargrp[i].regs;
1555 /* Mask all interrupts */
1556 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1557
46ceb60c
SG		 1558 /* Clear all interrupts */
1559 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1560 }
1da177e4 1561
46ceb60c 1562 regs = priv->gfargrp[0].regs;
1da177e4 1563 /* Stop the DMA, and wait for it to stop */
f4983704 1564 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1565 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1566 != (DMACTRL_GRS | DMACTRL_GTS)) {
1567 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1568 gfar_write(&regs->dmactrl, tempval);
1da177e4 1569
761ed01b
AF		 1570 spin_event_timeout(((gfar_read(&regs->ievent) &
1571 (IEVENT_GRSC | IEVENT_GTSC)) ==
1572 (IEVENT_GRSC | IEVENT_GTSC)), -1, 0);
1da177e4 1573 }
d87eb127 1574}
d87eb127
SW		 1575
1576/* Halt the receive and transmit queues */
1577void gfar_halt(struct net_device *dev)
1578{
1579 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1580 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1581 u32 tempval;
1da177e4 1582
2a54adc3
SW		 1583 gfar_halt_nodisable(dev);
1584
1da177e4
LT		 1585 /* Disable Rx and Tx */
1586 tempval = gfar_read(&regs->maccfg1);
1587 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1588 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1589}
1590
46ceb60c
SG		 1591static void free_grp_irqs(struct gfar_priv_grp *grp)
1592{
1593 free_irq(grp->interruptError, grp);
1594 free_irq(grp->interruptTransmit, grp);
1595 free_irq(grp->interruptReceive, grp);
1596}
1597
0bbaf069
KG		 1598void stop_gfar(struct net_device *dev)
1599{
1600 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1601 unsigned long flags;
46ceb60c 1602 int i;
0bbaf069 1603
bb40dcbb
AF		 1604 phy_stop(priv->phydev);
1605
a12f801d 1606
0bbaf069 1607 /* Lock it down */
fba4ed03
SG		 1608 local_irq_save(flags);
1609 lock_tx_qs(priv);
1610 lock_rx_qs(priv);
0bbaf069 1611
0bbaf069 1612 gfar_halt(dev);
1da177e4 1613
fba4ed03
SG		 1614 unlock_rx_qs(priv);
1615 unlock_tx_qs(priv);
1616 local_irq_restore(flags);
1da177e4
LT		 1617
1618 /* Free the IRQs */
b31a1d8b 1619 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1620 for (i = 0; i < priv->num_grps; i++)
1621 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1622 } else {
46ceb60c
SG		 1623 for (i = 0; i < priv->num_grps; i++)
1624 free_irq(priv->gfargrp[i].interruptTransmit,
1625 &priv->gfargrp[i]);
1da177e4
LT		 1626 }
1627
1628 free_skb_resources(priv);
1da177e4
LT		 1629}
1630
fba4ed03 1631static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1632{
1da177e4 1633 struct txbd8 *txbdp;
fba4ed03 1634 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1635 int i, j;
1da177e4 1636
a12f801d 1637 txbdp = tx_queue->tx_bd_base;
1da177e4 1638
a12f801d
SG		 1639 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1640 if (!tx_queue->tx_skbuff[i])
4669bc90 1641 continue;
1da177e4 1642
4826857f 1643 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1644 txbdp->length, DMA_TO_DEVICE);
1645 txbdp->lstatus = 0;
fba4ed03
SG		 1646 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1647 j++) {
4669bc90 1648 txbdp++;
4826857f 1649 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1650 txbdp->length, DMA_TO_DEVICE);
1da177e4 1651 }
ad5da7ab 1652 txbdp++;
a12f801d
SG		 1653 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1654 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1655 }
a12f801d 1656 kfree(tx_queue->tx_skbuff);
fba4ed03 1657}
1da177e4 1658
fba4ed03
SG		 1659static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1660{
1661 struct rxbd8 *rxbdp;
1662 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1663 int i;
1da177e4 1664
fba4ed03 1665 rxbdp = rx_queue->rx_bd_base;
1da177e4 1666
a12f801d
SG		 1667 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1668 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1669 dma_unmap_single(&priv->ofdev->dev,
1670 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1671 DMA_FROM_DEVICE);
a12f801d
SG		 1672 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1673 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1674 }
e69edd21
AV		 1675 rxbdp->lstatus = 0;
1676 rxbdp->bufPtr = 0;
1677 rxbdp++;
1da177e4 1678 }
a12f801d 1679 kfree(rx_queue->rx_skbuff);
fba4ed03 1680}
e69edd21 1681
fba4ed03
SG		 1682/* If there are any tx skbs or rx skbs still around, free them.
1683 * Then free tx_skbuff and rx_skbuff */
1684static void free_skb_resources(struct gfar_private *priv)
1685{
1686 struct gfar_priv_tx_q *tx_queue = NULL;
1687 struct gfar_priv_rx_q *rx_queue = NULL;
1688 int i;
1689
1690 /* Go through all the buffer descriptors and free their data buffers */
1691 for (i = 0; i < priv->num_tx_queues; i++) {
1692 tx_queue = priv->tx_queue[i];
7c0d10d3 1693 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1694 free_skb_tx_queue(tx_queue);
1695 }
1696
1697 for (i = 0; i < priv->num_rx_queues; i++) {
1698 rx_queue = priv->rx_queue[i];
7c0d10d3 1699 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1700 free_skb_rx_queue(rx_queue);
1701 }
1702
1703 dma_free_coherent(&priv->ofdev->dev,
1704 sizeof(struct txbd8) * priv->total_tx_ring_size +
1705 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1706 priv->tx_queue[0]->tx_bd_base,
1707 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1708}
1709
0bbaf069
KG		 1710void gfar_start(struct net_device *dev)
1711{
1712 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1713 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1714 u32 tempval;
46ceb60c 1715 int i = 0;
0bbaf069
KG		 1716
1717 /* Enable Rx and Tx in MACCFG1 */
1718 tempval = gfar_read(&regs->maccfg1);
1719 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1720 gfar_write(&regs->maccfg1, tempval);
1721
1722 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1723 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1724 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1725 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1726
0bbaf069 1727 /* Make sure we aren't stopped */
f4983704 1728 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1729 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1730 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1731
46ceb60c
SG		 1732 for (i = 0; i < priv->num_grps; i++) {
1733 regs = priv->gfargrp[i].regs;
1734 /* Clear THLT/RHLT, so that the DMA starts polling now */
1735 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1736 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1737 /* Unmask the interrupts we look for */
1738 gfar_write(&regs->imask, IMASK_DEFAULT);
1739 }
12dea57b
DH		 1740
1741 dev->trans_start = jiffies;
0bbaf069
KG		 1742}
1743
46ceb60c 1744void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1745 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1746{
46ceb60c 1747 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1748 u32 __iomem *baddr;
46ceb60c 1749 int i = 0;
1da177e4 1750
46ceb60c
SG		 1751 /* Backward compatible case ---- even if we enable
1752 * multiple queues, there's only single reg to program
1753 */
1754 gfar_write(&regs->txic, 0);
1755 if(likely(priv->tx_queue[0]->txcoalescing))
1756 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1757
46ceb60c
SG		 1758 gfar_write(&regs->rxic, 0);
1759 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1760 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1761
46ceb60c
SG		 1762 if (priv->mode == MQ_MG_MODE) {
1763 baddr = &regs->txic0;
984b3f57 1764 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1765 if (likely(priv->tx_queue[i]->txcoalescing)) {
1766 gfar_write(baddr + i, 0);
1767 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1768 }
1769 }
1770
1771 baddr = &regs->rxic0;
984b3f57 1772 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1773 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1774 gfar_write(baddr + i, 0);
1775 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1776 }
1777 }
1778 }
1779}
1780
1781static int register_grp_irqs(struct gfar_priv_grp *grp)
1782{
1783 struct gfar_private *priv = grp->priv;
1784 struct net_device *dev = priv->ndev;
1785 int err;
1da177e4 1786
1da177e4
LT		 1787 /* If the device has multiple interrupts, register for
1788 * them. Otherwise, only register for the one */
b31a1d8b 1789 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1790 /* Install our interrupt handlers for Error,
1da177e4 1791 * Transmit, and Receive */
46ceb60c
SG		 1792 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1793 grp->int_name_er,grp)) < 0) {
0bbaf069 1794 if (netif_msg_intr(priv))
46ceb60c
SG		 1795 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1796 dev->name, grp->interruptError);
1797
1798 goto err_irq_fail;
1da177e4
LT		 1799 }
1800
46ceb60c
SG		 1801 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1802 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1803 if (netif_msg_intr(priv))
46ceb60c
SG		 1804 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1805 dev->name, grp->interruptTransmit);
1da177e4
LT		 1806 goto tx_irq_fail;
1807 }
1808
46ceb60c
SG		 1809 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1810 grp->int_name_rx, grp)) < 0) {
0bbaf069 1811 if (netif_msg_intr(priv))
46ceb60c
SG		 1812 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1813 dev->name, grp->interruptReceive);
1da177e4
LT		 1814 goto rx_irq_fail;
1815 }
1816 } else {
46ceb60c
SG		 1817 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1818 grp->int_name_tx, grp)) < 0) {
0bbaf069 1819 if (netif_msg_intr(priv))
46ceb60c
SG		 1820 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1821 dev->name, grp->interruptTransmit);
1da177e4
LT		 1822 goto err_irq_fail;
1823 }
1824 }
1825
46ceb60c
SG		 1826 return 0;
1827
1828rx_irq_fail:
1829 free_irq(grp->interruptTransmit, grp);
1830tx_irq_fail:
1831 free_irq(grp->interruptError, grp);
1832err_irq_fail:
1833 return err;
1834
1835}
1836
1837/* Bring the controller up and running */
1838int startup_gfar(struct net_device *ndev)
1839{
1840 struct gfar_private *priv = netdev_priv(ndev);
1841 struct gfar __iomem *regs = NULL;
1842 int err, i, j;
1843
1844 for (i = 0; i < priv->num_grps; i++) {
1845 regs= priv->gfargrp[i].regs;
1846 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1847 }
1848
1849 regs= priv->gfargrp[0].regs;
1850 err = gfar_alloc_skb_resources(ndev);
1851 if (err)
1852 return err;
1853
1854 gfar_init_mac(ndev);
1855
1856 for (i = 0; i < priv->num_grps; i++) {
1857 err = register_grp_irqs(&priv->gfargrp[i]);
1858 if (err) {
1859 for (j = 0; j < i; j++)
1860 free_grp_irqs(&priv->gfargrp[j]);
1861 goto irq_fail;
1862 }
1863 }
1864
7f7f5316 1865 /* Start the controller */
ccc05c6e 1866 gfar_start(ndev);
1da177e4 1867
826aa4a0
AV		 1868 phy_start(priv->phydev);
1869
46ceb60c
SG		 1870 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1871
1da177e4
LT		 1872 return 0;
1873
46ceb60c 1874irq_fail:
e69edd21 1875 free_skb_resources(priv);
1da177e4
LT		 1876 return err;
1877}
1878
1879/* Called when something needs to use the ethernet device */
1880/* Returns 0 for success. */
1881static int gfar_enet_open(struct net_device *dev)
1882{
94e8cc35 1883 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1884 int err;
1885
46ceb60c 1886 enable_napi(priv);
bea3348e 1887
0fd56bb5
AF		 1888 skb_queue_head_init(&priv->rx_recycle);
1889
1da177e4
LT		 1890 /* Initialize a bunch of registers */
1891 init_registers(dev);
1892
1893 gfar_set_mac_address(dev);
1894
1895 err = init_phy(dev);
1896
a12f801d 1897 if (err) {
46ceb60c 1898 disable_napi(priv);
1da177e4 1899 return err;
bea3348e 1900 }
1da177e4
LT		 1901
1902 err = startup_gfar(dev);
db0e8e3f 1903 if (err) {
46ceb60c 1904 disable_napi(priv);
db0e8e3f
AV		 1905 return err;
1906 }
1da177e4 1907
fba4ed03 1908 netif_tx_start_all_queues(dev);
1da177e4 1909
2884e5cc
AV		 1910 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1911
1da177e4
LT		 1912 return err;
1913}
1914
54dc79fe 1915static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1916{
54dc79fe 1917 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1918
1919 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1920
0bbaf069
KG		 1921 return fcb;
1922}
1923
1924static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1925{
7f7f5316 1926 u8 flags = 0;
0bbaf069
KG		 1927
1928 /* If we're here, it's a IP packet with a TCP or UDP
1929 * payload. We set it to checksum, using a pseudo-header
1930 * we provide
1931 */
7f7f5316 1932 flags = TXFCB_DEFAULT;
0bbaf069 1933
7f7f5316
AF		 1934 /* Tell the controller what the protocol is */
1935 /* And provide the already calculated phcs */
eddc9ec5 1936 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1937 flags |= TXFCB_UDP;
4bedb452 1938 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1939 } else
8da32de5 1940 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1941
1942 /* l3os is the distance between the start of the
1943 * frame (skb->data) and the start of the IP hdr.
1944 * l4os is the distance between the start of the
1945 * l3 hdr and the l4 hdr */
bbe735e4 1946 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 1947 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1948
7f7f5316 1949 fcb->flags = flags;
0bbaf069
KG		 1950}
1951
7f7f5316 1952void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1953{
7f7f5316 1954 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1955 fcb->vlctl = vlan_tx_tag_get(skb);
1956}
1957
4669bc90
DH		 1958static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1959 struct txbd8 *base, int ring_size)
1960{
1961 struct txbd8 *new_bd = bdp + stride;
1962
1963 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1964}
1965
1966static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1967 int ring_size)
1968{
1969 return skip_txbd(bdp, 1, base, ring_size);
1970}
1971
1da177e4
LT		 1972/* This is called by the kernel when a frame is ready for transmission. */
1973/* It is pointed to by the dev->hard_start_xmit function pointer */
1974static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1975{
1976 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1977 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 1978 struct netdev_queue *txq;
f4983704 1979 struct gfar __iomem *regs = NULL;
0bbaf069 1980 struct txfcb *fcb = NULL;
f0ee7acf 1981 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 1982 u32 lstatus;
f0ee7acf 1983 int i, rq = 0, do_tstamp = 0;
4669bc90 1984 u32 bufaddr;
fef6108d 1985 unsigned long flags;
f0ee7acf
MR		 1986 unsigned int nr_frags, nr_txbds, length;
1987 union skb_shared_tx *shtx;
fba4ed03
SG		 1988
1989 rq = skb->queue_mapping;
1990 tx_queue = priv->tx_queue[rq];
1991 txq = netdev_get_tx_queue(dev, rq);
a12f801d 1992 base = tx_queue->tx_bd_base;
46ceb60c 1993 regs = tx_queue->grp->regs;
f0ee7acf
MR		 1994 shtx = skb_tx(skb);
1995
1996 /* check if time stamp should be generated */
1997 if (unlikely(shtx->hardware && priv->hwts_tx_en))
1998 do_tstamp = 1;
4669bc90 1999
5b28beaf
LY		 2000 /* make space for additional header when fcb is needed */
2001 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
f0ee7acf
MR		 2002 (priv->vlgrp && vlan_tx_tag_present(skb)) ||
2003 unlikely(do_tstamp)) &&
5b28beaf 2004 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 2005 struct sk_buff *skb_new;
2006
2007 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2008 if (!skb_new) {
2009 dev->stats.tx_errors++;
bd14ba84 2010 kfree_skb(skb);
54dc79fe
SH		 2011 return NETDEV_TX_OK;
2012 }
2013 kfree_skb(skb);
2014 skb = skb_new;
2015 }
2016
4669bc90
DH		 2017 /* total number of fragments in the SKB */
2018 nr_frags = skb_shinfo(skb)->nr_frags;
2019
f0ee7acf
MR		 2020 /* calculate the required number of TxBDs for this skb */
2021 if (unlikely(do_tstamp))
2022 nr_txbds = nr_frags + 2;
2023 else
2024 nr_txbds = nr_frags + 1;
2025
4669bc90 2026 /* check if there is space to queue this packet */
f0ee7acf 2027 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2028 /* no space, stop the queue */
fba4ed03 2029 netif_tx_stop_queue(txq);
4669bc90 2030 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2031 return NETDEV_TX_BUSY;
2032 }
1da177e4
LT		 2033
2034 /* Update transmit stats */
a7f38041
SG		 2035 txq->tx_bytes += skb->len;
2036 txq->tx_packets ++;
1da177e4 2037
a12f801d 2038 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2039 lstatus = txbdp->lstatus;
2040
2041 /* Time stamp insertion requires one additional TxBD */
2042 if (unlikely(do_tstamp))
2043 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2044 tx_queue->tx_ring_size);
1da177e4 2045
4669bc90 2046 if (nr_frags == 0) {
f0ee7acf
MR		 2047 if (unlikely(do_tstamp))
2048 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2049 TXBD_INTERRUPT);
2050 else
2051 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2052 } else {
2053 /* Place the fragment addresses and lengths into the TxBDs */
2054 for (i = 0; i < nr_frags; i++) {
2055 /* Point at the next BD, wrapping as needed */
a12f801d 2056 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2057
2058 length = skb_shinfo(skb)->frags[i].size;
2059
2060 lstatus = txbdp->lstatus | length |
2061 BD_LFLAG(TXBD_READY);
2062
2063 /* Handle the last BD specially */
2064 if (i == nr_frags - 1)
2065 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2066
4826857f 2067 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 2068 skb_shinfo(skb)->frags[i].page,
2069 skb_shinfo(skb)->frags[i].page_offset,
2070 length,
2071 DMA_TO_DEVICE);
2072
2073 /* set the TxBD length and buffer pointer */
2074 txbdp->bufPtr = bufaddr;
2075 txbdp->lstatus = lstatus;
2076 }
2077
2078 lstatus = txbdp_start->lstatus;
2079 }
1da177e4 2080
0bbaf069 2081 /* Set up checksumming */
12dea57b 2082 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 2083 fcb = gfar_add_fcb(skb);
2084 lstatus |= BD_LFLAG(TXBD_TOE);
2085 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 2086 }
2087
77ecaf2d 2088 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2089 if (unlikely(NULL == fcb)) {
2090 fcb = gfar_add_fcb(skb);
5a5efed4 2091 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2092 }
54dc79fe
SH		 2093
2094 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2095 }
2096
f0ee7acf
MR		 2097 /* Setup tx hardware time stamping if requested */
2098 if (unlikely(do_tstamp)) {
2099 shtx->in_progress = 1;
2100 if (fcb == NULL)
2101 fcb = gfar_add_fcb(skb);
2102 fcb->ptp = 1;
2103 lstatus |= BD_LFLAG(TXBD_TOE);
2104 }
2105
4826857f 2106 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2107 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2108
f0ee7acf
MR		 2109 /*
2110 * If time stamping is requested one additional TxBD must be set up. The
2111 * first TxBD points to the FCB and must have a data length of
2112 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2113 * the full frame length.
2114 */
2115 if (unlikely(do_tstamp)) {
2116 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2117 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2118 (skb_headlen(skb) - GMAC_FCB_LEN);
2119 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2120 } else {
2121 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2122 }
1da177e4 2123
a3bc1f11
AV		 2124 /*
2125 * We can work in parallel with gfar_clean_tx_ring(), except
2126 * when modifying num_txbdfree. Note that we didn't grab the lock
2127 * when we were reading the num_txbdfree and checking for available
2128 * space, that's because outside of this function it can only grow,
2129 * and once we've got needed space, it cannot suddenly disappear.
2130 *
2131 * The lock also protects us from gfar_error(), which can modify
2132 * regs->tstat and thus retrigger the transfers, which is why we
2133 * also must grab the lock before setting ready bit for the first
2134 * to be transmitted BD.
2135 */
2136 spin_lock_irqsave(&tx_queue->txlock, flags);
2137
4669bc90
DH		 2138 /*
2139 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2140 * semantics (it requires synchronization between cacheable and
2141 * uncacheable mappings, which eieio doesn't provide and which we
2142 * don't need), thus requiring a more expensive sync instruction. At
2143 * some point, the set of architecture-independent barrier functions
2144 * should be expanded to include weaker barriers.
2145 */
3b6330ce 2146 eieio();
7f7f5316 2147
4669bc90
DH		 2148 txbdp_start->lstatus = lstatus;
2149
0eddba52
AV		 2150 eieio(); /* force lstatus write before tx_skbuff */
2151
2152 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2153
4669bc90
DH		 2154 /* Update the current skb pointer to the next entry we will use
2155 * (wrapping if necessary) */
a12f801d
SG		 2156 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2157 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2158
a12f801d 2159 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2160
2161 /* reduce TxBD free count */
f0ee7acf 2162 tx_queue->num_txbdfree -= (nr_txbds);
4669bc90
DH		 2163
2164 dev->trans_start = jiffies;
1da177e4
LT		 2165
2166 /* If the next BD still needs to be cleaned up, then the bds
2167 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2168 if (!tx_queue->num_txbdfree) {
fba4ed03 2169 netif_tx_stop_queue(txq);
1da177e4 2170
09f75cd7 2171 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2172 }
2173
1da177e4 2174 /* Tell the DMA to go go go */
fba4ed03 2175 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2176
2177 /* Unlock priv */
a12f801d 2178 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2179
54dc79fe 2180 return NETDEV_TX_OK;
1da177e4
LT		 2181}
2182
2183/* Stops the kernel queue, and halts the controller */
2184static int gfar_close(struct net_device *dev)
2185{
2186 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2187
46ceb60c 2188 disable_napi(priv);
bea3348e 2189
0fd56bb5 2190 skb_queue_purge(&priv->rx_recycle);
ab939905 2191 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2192 stop_gfar(dev);
2193
bb40dcbb
AF		 2194 /* Disconnect from the PHY */
2195 phy_disconnect(priv->phydev);
2196 priv->phydev = NULL;
1da177e4 2197
fba4ed03 2198 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2199
2200 return 0;
2201}
2202
1da177e4 2203/* Changes the mac address if the controller is not running. */
f162b9d5 2204static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2205{
7f7f5316 2206 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2207
2208 return 0;
2209}
2210
2211
0bbaf069
KG		 2212/* Enables and disables VLAN insertion/extraction */
2213static void gfar_vlan_rx_register(struct net_device *dev,
2214 struct vlan_group *grp)
2215{
2216 struct gfar_private *priv = netdev_priv(dev);
f4983704 2217 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2218 unsigned long flags;
2219 u32 tempval;
2220
46ceb60c 2221 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2222 local_irq_save(flags);
2223 lock_rx_qs(priv);
0bbaf069 2224
cd1f55a5 2225 priv->vlgrp = grp;
0bbaf069
KG		 2226
2227 if (grp) {
2228 /* Enable VLAN tag insertion */
f4983704 2229 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2230 tempval |= TCTRL_VLINS;
2231
f4983704 2232 gfar_write(&regs->tctrl, tempval);
6aa20a22 2233
0bbaf069 2234 /* Enable VLAN tag extraction */
f4983704 2235 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2236 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2237 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2238 } else {
2239 /* Disable VLAN tag insertion */
f4983704 2240 tempval = gfar_read(&regs->tctrl);
0bbaf069 2241 tempval &= ~TCTRL_VLINS;
f4983704 2242 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2243
2244 /* Disable VLAN tag extraction */
f4983704 2245 tempval = gfar_read(&regs->rctrl);
0bbaf069 2246 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2247 /* If parse is no longer required, then disable parser */
2248 if (tempval & RCTRL_REQ_PARSER)
2249 tempval |= RCTRL_PRSDEP_INIT;
2250 else
2251 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2252 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2253 }
2254
77ecaf2d
DH		 2255 gfar_change_mtu(dev, dev->mtu);
2256
fba4ed03
SG		 2257 unlock_rx_qs(priv);
2258 local_irq_restore(flags);
0bbaf069
KG		 2259}
2260
1da177e4
LT		 2261static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2262{
2263 int tempsize, tempval;
2264 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2265 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2266 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2267 int frame_size = new_mtu + ETH_HLEN;
2268
77ecaf2d 2269 if (priv->vlgrp)
faa89577 2270 frame_size += VLAN_HLEN;
0bbaf069 2271
1da177e4 2272 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2273 if (netif_msg_drv(priv))
2274 printk(KERN_ERR "%s: Invalid MTU setting\n",
2275 dev->name);
1da177e4
LT		 2276 return -EINVAL;
2277 }
2278
77ecaf2d
DH		 2279 if (gfar_uses_fcb(priv))
2280 frame_size += GMAC_FCB_LEN;
2281
2282 frame_size += priv->padding;
2283
1da177e4
LT		 2284 tempsize =
2285 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2286 INCREMENTAL_BUFFER_SIZE;
2287
2288 /* Only stop and start the controller if it isn't already
7f7f5316 2289 * stopped, and we changed something */
1da177e4
LT		 2290 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2291 stop_gfar(dev);
2292
2293 priv->rx_buffer_size = tempsize;
2294
2295 dev->mtu = new_mtu;
2296
f4983704
SG		 2297 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2298 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2299
2300 /* If the mtu is larger than the max size for standard
2301 * ethernet frames (ie, a jumbo frame), then set maccfg2
2302 * to allow huge frames, and to check the length */
f4983704 2303 tempval = gfar_read(&regs->maccfg2);
1da177e4
LT		 2304
2305 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2306 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2307 else
2308 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2309
f4983704 2310 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2311
2312 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2313 startup_gfar(dev);
2314
2315 return 0;
2316}
2317
ab939905 2318/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2319 * transmitted after a set amount of time.
2320 * For now, assume that clearing out all the structures, and
ab939905
SS		 2321 * starting over will fix the problem.
2322 */
2323static void gfar_reset_task(struct work_struct *work)
1da177e4 2324{
ab939905
SS		 2325 struct gfar_private *priv = container_of(work, struct gfar_private,
2326 reset_task);
4826857f 2327 struct net_device *dev = priv->ndev;
1da177e4
LT		 2328
2329 if (dev->flags & IFF_UP) {
fba4ed03 2330 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2331 stop_gfar(dev);
2332 startup_gfar(dev);
fba4ed03 2333 netif_tx_start_all_queues(dev);
1da177e4
LT		 2334 }
2335
263ba320 2336 netif_tx_schedule_all(dev);
1da177e4
LT		 2337}
2338
ab939905
SS		 2339static void gfar_timeout(struct net_device *dev)
2340{
2341 struct gfar_private *priv = netdev_priv(dev);
2342
2343 dev->stats.tx_errors++;
2344 schedule_work(&priv->reset_task);
2345}
2346
1da177e4 2347/* Interrupt Handler for Transmit complete */
a12f801d 2348static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2349{
a12f801d 2350 struct net_device *dev = tx_queue->dev;
d080cd63 2351 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2352 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2353 struct txbd8 *bdp, *next = NULL;
4669bc90 2354 struct txbd8 *lbdp = NULL;
a12f801d 2355 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2356 struct sk_buff *skb;
2357 int skb_dirtytx;
a12f801d 2358 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2359 int frags = 0, nr_txbds = 0;
4669bc90 2360 int i;
d080cd63 2361 int howmany = 0;
4669bc90 2362 u32 lstatus;
f0ee7acf
MR		 2363 size_t buflen;
2364 union skb_shared_tx *shtx;
1da177e4 2365
fba4ed03 2366 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2367 bdp = tx_queue->dirty_tx;
2368 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2369
a12f801d 2370 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2371 unsigned long flags;
2372
4669bc90 2373 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2374
2375 /*
2376 * When time stamping, one additional TxBD must be freed.
2377 * Also, we need to dma_unmap_single() the TxPAL.
2378 */
2379 shtx = skb_tx(skb);
2380 if (unlikely(shtx->in_progress))
2381 nr_txbds = frags + 2;
2382 else
2383 nr_txbds = frags + 1;
2384
2385 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2386
4669bc90 2387 lstatus = lbdp->lstatus;
1da177e4 2388
4669bc90
DH		 2389 /* Only clean completed frames */
2390 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2391 (lstatus & BD_LENGTH_MASK))
2392 break;
2393
f0ee7acf
MR		 2394 if (unlikely(shtx->in_progress)) {
2395 next = next_txbd(bdp, base, tx_ring_size);
2396 buflen = next->length + GMAC_FCB_LEN;
2397 } else
2398 buflen = bdp->length;
2399
2400 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2401 buflen, DMA_TO_DEVICE);
2402
2403 if (unlikely(shtx->in_progress)) {
2404 struct skb_shared_hwtstamps shhwtstamps;
2405 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2406 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2407 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2408 skb_tstamp_tx(skb, &shhwtstamps);
2409 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2410 bdp = next;
2411 }
81183059 2412
4669bc90
DH		 2413 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2414 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2415
4669bc90 2416 for (i = 0; i < frags; i++) {
4826857f 2417 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2418 bdp->bufPtr,
2419 bdp->length,
2420 DMA_TO_DEVICE);
2421 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2422 bdp = next_txbd(bdp, base, tx_ring_size);
2423 }
1da177e4 2424
0fd56bb5
AF		 2425 /*
2426 * If there's room in the queue (limit it to rx_buffer_size)
2427 * we add this skb back into the pool, if it's the right size
2428 */
a12f801d 2429 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5
AF		 2430 skb_recycle_check(skb, priv->rx_buffer_size +
2431 RXBUF_ALIGNMENT))
2432 __skb_queue_head(&priv->rx_recycle, skb);
2433 else
2434 dev_kfree_skb_any(skb);
2435
a12f801d 2436 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2437
4669bc90
DH		 2438 skb_dirtytx = (skb_dirtytx + 1) &
2439 TX_RING_MOD_MASK(tx_ring_size);
2440
2441 howmany++;
a3bc1f11 2442 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2443 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2444 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2445 }
1da177e4 2446
4669bc90 2447 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2448 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2449 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2450
4669bc90 2451 /* Update dirty indicators */
a12f801d
SG		 2452 tx_queue->skb_dirtytx = skb_dirtytx;
2453 tx_queue->dirty_tx = bdp;
1da177e4 2454
d080cd63
DH		 2455 return howmany;
2456}
2457
f4983704 2458static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2459{
a6d0b91a
AV		 2460 unsigned long flags;
2461
fba4ed03
SG		 2462 spin_lock_irqsave(&gfargrp->grplock, flags);
2463 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2464 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2465 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2466 } else {
2467 /*
2468 * Clear IEVENT, so interrupts aren't called again
2469 * because of the packets that have already arrived.
2470 */
f4983704 2471 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2472 }
fba4ed03 2473 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2474
8c7396ae 2475}
1da177e4 2476
8c7396ae 2477/* Interrupt Handler for Transmit complete */
f4983704 2478static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2479{
f4983704 2480 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2481 return IRQ_HANDLED;
2482}
2483
a12f801d 2484static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2485 struct sk_buff *skb)
2486{
a12f801d 2487 struct net_device *dev = rx_queue->dev;
815b97c6 2488 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2489 dma_addr_t buf;
815b97c6 2490
8a102fe0
AV		 2491 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2492 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2493 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2494}
2495
2496
2497struct sk_buff * gfar_new_skb(struct net_device *dev)
1da177e4 2498{
7f7f5316 2499 unsigned int alignamount;
1da177e4
LT		 2500 struct gfar_private *priv = netdev_priv(dev);
2501 struct sk_buff *skb = NULL;
1da177e4 2502
0fd56bb5
AF		 2503 skb = __skb_dequeue(&priv->rx_recycle);
2504 if (!skb)
2505 skb = netdev_alloc_skb(dev,
2506 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1da177e4 2507
815b97c6 2508 if (!skb)
1da177e4
LT		 2509 return NULL;
2510
7f7f5316 2511 alignamount = RXBUF_ALIGNMENT -
bea3348e 2512 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
7f7f5316 2513
1da177e4
LT		 2514 /* We need the data buffer to be aligned properly. We will reserve
2515 * as many bytes as needed to align the data properly
2516 */
7f7f5316 2517 skb_reserve(skb, alignamount);
a6d36d56 2518 GFAR_CB(skb)->alignamount = alignamount;
1da177e4 2519
1da177e4
LT		 2520 return skb;
2521}
2522
298e1a9e 2523static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2524{
298e1a9e 2525 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2526 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2527 struct gfar_extra_stats *estats = &priv->extra_stats;
2528
2529 /* If the packet was truncated, none of the other errors
2530 * matter */
2531 if (status & RXBD_TRUNCATED) {
2532 stats->rx_length_errors++;
2533
2534 estats->rx_trunc++;
2535
2536 return;
2537 }
2538 /* Count the errors, if there were any */
2539 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2540 stats->rx_length_errors++;
2541
2542 if (status & RXBD_LARGE)
2543 estats->rx_large++;
2544 else
2545 estats->rx_short++;
2546 }
2547 if (status & RXBD_NONOCTET) {
2548 stats->rx_frame_errors++;
2549 estats->rx_nonoctet++;
2550 }
2551 if (status & RXBD_CRCERR) {
2552 estats->rx_crcerr++;
2553 stats->rx_crc_errors++;
2554 }
2555 if (status & RXBD_OVERRUN) {
2556 estats->rx_overrun++;
2557 stats->rx_crc_errors++;
2558 }
2559}
2560
f4983704 2561irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2562{
f4983704 2563 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2564 return IRQ_HANDLED;
2565}
2566
0bbaf069
KG		 2567static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2568{
2569 /* If valid headers were found, and valid sums
2570 * were verified, then we tell the kernel that no
2571 * checksumming is necessary. Otherwise, it is */
7f7f5316 2572 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2573 skb->ip_summed = CHECKSUM_UNNECESSARY;
2574 else
2575 skb->ip_summed = CHECKSUM_NONE;
2576}
2577
2578
1da177e4
LT		 2579/* gfar_process_frame() -- handle one incoming packet if skb
2580 * isn't NULL. */
2581static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2582 int amount_pull)
1da177e4
LT		 2583{
2584 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2585 struct rxfcb *fcb = NULL;
1da177e4 2586
2c2db48a 2587 int ret;
1da177e4 2588
2c2db48a
DH		 2589 /* fcb is at the beginning if exists */
2590 fcb = (struct rxfcb *)skb->data;
0bbaf069 2591
2c2db48a
DH		 2592 /* Remove the FCB from the skb */
2593 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2594 if (amount_pull) {
2595 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2596 skb_pull(skb, amount_pull);
f74dac08 2597 }
0bbaf069 2598
cc772ab7
MR		 2599 /* Get receive timestamp from the skb */
2600 if (priv->hwts_rx_en) {
2601 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2602 u64 *ns = (u64 *) skb->data;
2603 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2604 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2605 }
2606
2607 if (priv->padding)
2608 skb_pull(skb, priv->padding);
2609
2c2db48a
DH		 2610 if (priv->rx_csum_enable)
2611 gfar_rx_checksum(skb, fcb);
0bbaf069 2612
2c2db48a
DH		 2613 /* Tell the skb what kind of packet this is */
2614 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2615
2c2db48a
DH		 2616 /* Send the packet up the stack */
2617 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2618 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2619 else
2620 ret = netif_receive_skb(skb);
0bbaf069 2621
2c2db48a
DH		 2622 if (NET_RX_DROP == ret)
2623 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2624
2625 return 0;
2626}
2627
2628/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2629 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2630 * of frames handled
2631 */
a12f801d 2632int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2633{
a12f801d 2634 struct net_device *dev = rx_queue->dev;
31de198b 2635 struct rxbd8 *bdp, *base;
1da177e4 2636 struct sk_buff *skb;
2c2db48a
DH		 2637 int pkt_len;
2638 int amount_pull;
1da177e4
LT		 2639 int howmany = 0;
2640 struct gfar_private *priv = netdev_priv(dev);
2641
2642 /* Get the first full descriptor */
a12f801d
SG		 2643 bdp = rx_queue->cur_rx;
2644 base = rx_queue->rx_bd_base;
1da177e4 2645
cc772ab7 2646 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2647
1da177e4 2648 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2649 struct sk_buff *newskb;
3b6330ce 2650 rmb();
815b97c6
AF		 2651
2652 /* Add another skb for the future */
2653 newskb = gfar_new_skb(dev);
2654
a12f801d 2655 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2656
4826857f 2657 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2658 priv->rx_buffer_size, DMA_FROM_DEVICE);
2659
815b97c6
AF		 2660 /* We drop the frame if we failed to allocate a new buffer */
2661 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2662 bdp->status & RXBD_ERR)) {
2663 count_errors(bdp->status, dev);
2664
2665 if (unlikely(!newskb))
2666 newskb = skb;
4e2fd555
LB		 2667 else if (skb) {
2668 /*
a6d36d56 2669 * We need to un-reserve() the skb to what it
4e2fd555
LB		 2670 * was before gfar_new_skb() re-aligned
2671 * it to an RXBUF_ALIGNMENT boundary
2672 * before we put the skb back on the
2673 * recycle list.
2674 */
a6d36d56 2675 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
0fd56bb5 2676 __skb_queue_head(&priv->rx_recycle, skb);
4e2fd555 2677 }
815b97c6 2678 } else {
1da177e4 2679 /* Increment the number of packets */
a7f38041 2680 rx_queue->stats.rx_packets++;
1da177e4
LT		 2681 howmany++;
2682
2c2db48a
DH		 2683 if (likely(skb)) {
2684 pkt_len = bdp->length - ETH_FCS_LEN;
2685 /* Remove the FCS from the packet length */
2686 skb_put(skb, pkt_len);
a7f38041 2687 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2688 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2689 gfar_process_frame(dev, skb, amount_pull);
2690
2691 } else {
2692 if (netif_msg_rx_err(priv))
2693 printk(KERN_WARNING
2694 "%s: Missing skb!\n", dev->name);
a7f38041 2695 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2696 priv->extra_stats.rx_skbmissing++;
2697 }
1da177e4 2698
1da177e4
LT		 2699 }
2700
a12f801d 2701 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2702
815b97c6 2703 /* Setup the new bdp */
a12f801d 2704 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2705
2706 /* Update to the next pointer */
a12f801d 2707 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2708
2709 /* update to point at the next skb */
a12f801d
SG		 2710 rx_queue->skb_currx =
2711 (rx_queue->skb_currx + 1) &
2712 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2713 }
2714
2715 /* Update the current rxbd pointer to be the next one */
a12f801d 2716 rx_queue->cur_rx = bdp;
1da177e4 2717
1da177e4
LT		 2718 return howmany;
2719}
2720
bea3348e 2721static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2722{
fba4ed03
SG		 2723 struct gfar_priv_grp *gfargrp = container_of(napi,
2724 struct gfar_priv_grp, napi);
2725 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2726 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2727 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2728 struct gfar_priv_rx_q *rx_queue = NULL;
2729 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2730 int tx_cleaned = 0, i, left_over_budget = budget;
2731 unsigned long serviced_queues = 0;
fba4ed03 2732 int num_queues = 0;
d080cd63 2733
fba4ed03
SG		 2734 num_queues = gfargrp->num_rx_queues;
2735 budget_per_queue = budget/num_queues;
2736
8c7396ae
DH		 2737 /* Clear IEVENT, so interrupts aren't called again
2738 * because of the packets that have already arrived */
f4983704 2739 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2740
fba4ed03 2741 while (num_queues && left_over_budget) {
1da177e4 2742
fba4ed03
SG		 2743 budget_per_queue = left_over_budget/num_queues;
2744 left_over_budget = 0;
2745
984b3f57 2746 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2747 if (test_bit(i, &serviced_queues))
2748 continue;
2749 rx_queue = priv->rx_queue[i];
2750 tx_queue = priv->tx_queue[rx_queue->qindex];
2751
a3bc1f11 2752 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2753 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2754 budget_per_queue);
2755 rx_cleaned += rx_cleaned_per_queue;
2756 if(rx_cleaned_per_queue < budget_per_queue) {
2757 left_over_budget = left_over_budget +
2758 (budget_per_queue - rx_cleaned_per_queue);
2759 set_bit(i, &serviced_queues);
2760 num_queues--;
2761 }
2762 }
2763 }
1da177e4 2764
42199884
AF		 2765 if (tx_cleaned)
2766 return budget;
2767
2768 if (rx_cleaned < budget) {
288379f0 2769 napi_complete(napi);
1da177e4
LT		 2770
2771 /* Clear the halt bit in RSTAT */
fba4ed03 2772 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2773
f4983704 2774 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2775
2776 /* If we are coalescing interrupts, update the timer */
2777 /* Otherwise, clear it */
46ceb60c
SG		 2778 gfar_configure_coalescing(priv,
2779 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2780 }
2781
42199884 2782 return rx_cleaned;
1da177e4 2783}
1da177e4 2784
f2d71c2d
VW		 2785#ifdef CONFIG_NET_POLL_CONTROLLER
2786/*
2787 * Polling 'interrupt' - used by things like netconsole to send skbs
2788 * without having to re-enable interrupts. It's not called while
2789 * the interrupt routine is executing.
2790 */
2791static void gfar_netpoll(struct net_device *dev)
2792{
2793 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2794 int i = 0;
f2d71c2d
VW		 2795
2796 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2797 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2798 for (i = 0; i < priv->num_grps; i++) {
2799 disable_irq(priv->gfargrp[i].interruptTransmit);
2800 disable_irq(priv->gfargrp[i].interruptReceive);
2801 disable_irq(priv->gfargrp[i].interruptError);
2802 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2803 &priv->gfargrp[i]);
2804 enable_irq(priv->gfargrp[i].interruptError);
2805 enable_irq(priv->gfargrp[i].interruptReceive);
2806 enable_irq(priv->gfargrp[i].interruptTransmit);
2807 }
f2d71c2d 2808 } else {
46ceb60c
SG		 2809 for (i = 0; i < priv->num_grps; i++) {
2810 disable_irq(priv->gfargrp[i].interruptTransmit);
2811 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2812 &priv->gfargrp[i]);
2813 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2814 }
f2d71c2d
VW		 2815 }
2816}
2817#endif
2818
1da177e4 2819/* The interrupt handler for devices with one interrupt */
f4983704 2820static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2821{
f4983704 2822 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2823
2824 /* Save ievent for future reference */
f4983704 2825 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2826
1da177e4 2827 /* Check for reception */
538cc7ee 2828 if (events & IEVENT_RX_MASK)
f4983704 2829 gfar_receive(irq, grp_id);
1da177e4
LT		 2830
2831 /* Check for transmit completion */
538cc7ee 2832 if (events & IEVENT_TX_MASK)
f4983704 2833 gfar_transmit(irq, grp_id);
1da177e4 2834
538cc7ee
SS		 2835 /* Check for errors */
2836 if (events & IEVENT_ERR_MASK)
f4983704 2837 gfar_error(irq, grp_id);
1da177e4
LT		 2838
2839 return IRQ_HANDLED;
2840}
2841
1da177e4
LT		 2842/* Called every time the controller might need to be made
2843 * aware of new link state. The PHY code conveys this
bb40dcbb 2844 * information through variables in the phydev structure, and this
1da177e4
LT		 2845 * function converts those variables into the appropriate
2846 * register values, and can bring down the device if needed.
2847 */
2848static void adjust_link(struct net_device *dev)
2849{
2850 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2851 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2852 unsigned long flags;
2853 struct phy_device *phydev = priv->phydev;
2854 int new_state = 0;
2855
fba4ed03
SG		 2856 local_irq_save(flags);
2857 lock_tx_qs(priv);
2858
bb40dcbb
AF		 2859 if (phydev->link) {
2860 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2861 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2862
1da177e4
LT		 2863 /* Now we make sure that we can be in full duplex mode.
2864 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2865 if (phydev->duplex != priv->oldduplex) {
2866 new_state = 1;
2867 if (!(phydev->duplex))
1da177e4 2868 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2869 else
1da177e4 2870 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2871
bb40dcbb 2872 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2873 }
2874
bb40dcbb
AF		 2875 if (phydev->speed != priv->oldspeed) {
2876 new_state = 1;
2877 switch (phydev->speed) {
1da177e4 2878 case 1000:
1da177e4
LT		 2879 tempval =
2880 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2881
2882 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2883 break;
2884 case 100:
2885 case 10:
1da177e4
LT		 2886 tempval =
2887 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2888
2889 /* Reduced mode distinguishes
2890 * between 10 and 100 */
2891 if (phydev->speed == SPEED_100)
2892 ecntrl |= ECNTRL_R100;
2893 else
2894 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2895 break;
2896 default:
0bbaf069
KG		 2897 if (netif_msg_link(priv))
2898 printk(KERN_WARNING
bb40dcbb
AF		 2899 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2900 dev->name, phydev->speed);
1da177e4
LT		 2901 break;
2902 }
2903
bb40dcbb 2904 priv->oldspeed = phydev->speed;
1da177e4
LT		 2905 }
2906
bb40dcbb 2907 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2908 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2909
1da177e4 2910 if (!priv->oldlink) {
bb40dcbb 2911 new_state = 1;
1da177e4 2912 priv->oldlink = 1;
1da177e4 2913 }
bb40dcbb
AF		 2914 } else if (priv->oldlink) {
2915 new_state = 1;
2916 priv->oldlink = 0;
2917 priv->oldspeed = 0;
2918 priv->oldduplex = -1;
1da177e4 2919 }
1da177e4 2920
bb40dcbb
AF		 2921 if (new_state && netif_msg_link(priv))
2922 phy_print_status(phydev);
fba4ed03
SG		 2923 unlock_tx_qs(priv);
2924 local_irq_restore(flags);
bb40dcbb 2925}
1da177e4
LT		 2926
2927/* Update the hash table based on the current list of multicast
2928 * addresses we subscribe to. Also, change the promiscuity of
2929 * the device based on the flags (this function is called
2930 * whenever dev->flags is changed */
2931static void gfar_set_multi(struct net_device *dev)
2932{
22bedad3 2933 struct netdev_hw_addr *ha;
1da177e4 2934 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2935 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 2936 u32 tempval;
2937
a12f801d 2938 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 2939 /* Set RCTRL to PROM */
2940 tempval = gfar_read(&regs->rctrl);
2941 tempval |= RCTRL_PROM;
2942 gfar_write(&regs->rctrl, tempval);
2943 } else {
2944 /* Set RCTRL to not PROM */
2945 tempval = gfar_read(&regs->rctrl);
2946 tempval &= ~(RCTRL_PROM);
2947 gfar_write(&regs->rctrl, tempval);
2948 }
6aa20a22 2949
a12f801d 2950 if (dev->flags & IFF_ALLMULTI) {
1da177e4 2951 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 2952 gfar_write(&regs->igaddr0, 0xffffffff);
2953 gfar_write(&regs->igaddr1, 0xffffffff);
2954 gfar_write(&regs->igaddr2, 0xffffffff);
2955 gfar_write(&regs->igaddr3, 0xffffffff);
2956 gfar_write(&regs->igaddr4, 0xffffffff);
2957 gfar_write(&regs->igaddr5, 0xffffffff);
2958 gfar_write(&regs->igaddr6, 0xffffffff);
2959 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 2960 gfar_write(&regs->gaddr0, 0xffffffff);
2961 gfar_write(&regs->gaddr1, 0xffffffff);
2962 gfar_write(&regs->gaddr2, 0xffffffff);
2963 gfar_write(&regs->gaddr3, 0xffffffff);
2964 gfar_write(&regs->gaddr4, 0xffffffff);
2965 gfar_write(&regs->gaddr5, 0xffffffff);
2966 gfar_write(&regs->gaddr6, 0xffffffff);
2967 gfar_write(&regs->gaddr7, 0xffffffff);
2968 } else {
7f7f5316
AF		 2969 int em_num;
2970 int idx;
2971
1da177e4 2972 /* zero out the hash */
0bbaf069
KG		 2973 gfar_write(&regs->igaddr0, 0x0);
2974 gfar_write(&regs->igaddr1, 0x0);
2975 gfar_write(&regs->igaddr2, 0x0);
2976 gfar_write(&regs->igaddr3, 0x0);
2977 gfar_write(&regs->igaddr4, 0x0);
2978 gfar_write(&regs->igaddr5, 0x0);
2979 gfar_write(&regs->igaddr6, 0x0);
2980 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 2981 gfar_write(&regs->gaddr0, 0x0);
2982 gfar_write(&regs->gaddr1, 0x0);
2983 gfar_write(&regs->gaddr2, 0x0);
2984 gfar_write(&regs->gaddr3, 0x0);
2985 gfar_write(&regs->gaddr4, 0x0);
2986 gfar_write(&regs->gaddr5, 0x0);
2987 gfar_write(&regs->gaddr6, 0x0);
2988 gfar_write(&regs->gaddr7, 0x0);
2989
7f7f5316
AF		 2990 /* If we have extended hash tables, we need to
2991 * clear the exact match registers to prepare for
2992 * setting them */
2993 if (priv->extended_hash) {
2994 em_num = GFAR_EM_NUM + 1;
2995 gfar_clear_exact_match(dev);
2996 idx = 1;
2997 } else {
2998 idx = 0;
2999 em_num = 0;
3000 }
3001
4cd24eaf 3002 if (netdev_mc_empty(dev))
1da177e4
LT		 3003 return;
3004
3005 /* Parse the list, and set the appropriate bits */
22bedad3 3006 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3007 if (idx < em_num) {
22bedad3 3008 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3009 idx++;
3010 } else
22bedad3 3011 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3012 }
3013 }
3014
3015 return;
3016}
3017
7f7f5316
AF		 3018
3019/* Clears each of the exact match registers to zero, so they
3020 * don't interfere with normal reception */
3021static void gfar_clear_exact_match(struct net_device *dev)
3022{
3023 int idx;
3024 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3025
3026 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3027 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3028}
3029
1da177e4
LT		 3030/* Set the appropriate hash bit for the given addr */
3031/* The algorithm works like so:
3032 * 1) Take the Destination Address (ie the multicast address), and
3033 * do a CRC on it (little endian), and reverse the bits of the
3034 * result.
3035 * 2) Use the 8 most significant bits as a hash into a 256-entry
3036 * table. The table is controlled through 8 32-bit registers:
3037 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3038 * gaddr7. This means that the 3 most significant bits in the
3039 * hash index which gaddr register to use, and the 5 other bits
3040 * indicate which bit (assuming an IBM numbering scheme, which
3041 * for PowerPC (tm) is usually the case) in the register holds
3042 * the entry. */
3043static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3044{
3045 u32 tempval;
3046 struct gfar_private *priv = netdev_priv(dev);
1da177e4 3047 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 3048 int width = priv->hash_width;
3049 u8 whichbit = (result >> (32 - width)) & 0x1f;
3050 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3051 u32 value = (1 << (31-whichbit));
3052
0bbaf069 3053 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3054 tempval |= value;
0bbaf069 3055 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3056
3057 return;
3058}
3059
7f7f5316
AF		 3060
3061/* There are multiple MAC Address register pairs on some controllers
3062 * This function sets the numth pair to a given address
3063 */
3064static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3065{
3066 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3067 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 3068 int idx;
3069 char tmpbuf[MAC_ADDR_LEN];
3070 u32 tempval;
f4983704 3071 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3072
3073 macptr += num*2;
3074
3075 /* Now copy it into the mac registers backwards, cuz */
3076 /* little endian is silly */
3077 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3078 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3079
3080 gfar_write(macptr, *((u32 *) (tmpbuf)));
3081
3082 tempval = *((u32 *) (tmpbuf + 4));
3083
3084 gfar_write(macptr+1, tempval);
3085}
3086
1da177e4 3087/* GFAR error interrupt handler */
f4983704 3088static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3089{
f4983704
SG		 3090 struct gfar_priv_grp *gfargrp = grp_id;
3091 struct gfar __iomem *regs = gfargrp->regs;
3092 struct gfar_private *priv= gfargrp->priv;
3093 struct net_device *dev = priv->ndev;
1da177e4
LT		 3094
3095 /* Save ievent for future reference */
f4983704 3096 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3097
3098 /* Clear IEVENT */
f4983704 3099 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3100
3101 /* Magic Packet is not an error. */
b31a1d8b 3102 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3103 (events & IEVENT_MAG))
3104 events &= ~IEVENT_MAG;
1da177e4
LT		 3105
3106 /* Hmm... */
0bbaf069
KG		 3107 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3108 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 3109 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 3110
3111 /* Update the error counters */
3112 if (events & IEVENT_TXE) {
09f75cd7 3113 dev->stats.tx_errors++;
1da177e4
LT		 3114
3115 if (events & IEVENT_LC)
09f75cd7 3116 dev->stats.tx_window_errors++;
1da177e4 3117 if (events & IEVENT_CRL)
09f75cd7 3118 dev->stats.tx_aborted_errors++;
1da177e4 3119 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3120 unsigned long flags;
3121
0bbaf069 3122 if (netif_msg_tx_err(priv))
538cc7ee
SS		 3123 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3124 "packet dropped.\n", dev->name);
09f75cd7 3125 dev->stats.tx_dropped++;
1da177e4
LT		 3126 priv->extra_stats.tx_underrun++;
3127
836cf7fa
AV		 3128 local_irq_save(flags);
3129 lock_tx_qs(priv);
3130
1da177e4 3131 /* Reactivate the Tx Queues */
fba4ed03 3132 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3133
3134 unlock_tx_qs(priv);
3135 local_irq_restore(flags);
1da177e4 3136 }
0bbaf069
KG		 3137 if (netif_msg_tx_err(priv))
3138 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 3139 }
3140 if (events & IEVENT_BSY) {
09f75cd7 3141 dev->stats.rx_errors++;
1da177e4
LT		 3142 priv->extra_stats.rx_bsy++;
3143
f4983704 3144 gfar_receive(irq, grp_id);
1da177e4 3145
0bbaf069 3146 if (netif_msg_rx_err(priv))
538cc7ee 3147 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 3148 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 3149 }
3150 if (events & IEVENT_BABR) {
09f75cd7 3151 dev->stats.rx_errors++;
1da177e4
LT		 3152 priv->extra_stats.rx_babr++;
3153
0bbaf069 3154 if (netif_msg_rx_err(priv))
538cc7ee 3155 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 3156 }
3157 if (events & IEVENT_EBERR) {
3158 priv->extra_stats.eberr++;
0bbaf069 3159 if (netif_msg_rx_err(priv))
538cc7ee 3160 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 3161 }
0bbaf069 3162 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 3163 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 3164
3165 if (events & IEVENT_BABT) {
3166 priv->extra_stats.tx_babt++;
0bbaf069 3167 if (netif_msg_tx_err(priv))
538cc7ee 3168 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3169 }
3170 return IRQ_HANDLED;
3171}
3172
b31a1d8b
AF		 3173static struct of_device_id gfar_match[] =
3174{
3175 {
3176 .type = "network",
3177 .compatible = "gianfar",
3178 },
46ceb60c
SG		 3179 {
3180 .compatible = "fsl,etsec2",
3181 },
b31a1d8b
AF		 3182 {},
3183};
e72701ac 3184MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3185
1da177e4 3186/* Structure for a device driver */
b31a1d8b
AF		 3187static struct of_platform_driver gfar_driver = {
3188 .name = "fsl-gianfar",
3189 .match_table = gfar_match,
3190
1da177e4
LT		 3191 .probe = gfar_probe,
3192 .remove = gfar_remove,
be926fc4
AV		 3193 .suspend = gfar_legacy_suspend,
3194 .resume = gfar_legacy_resume,
3195 .driver.pm = GFAR_PM_OPS,
1da177e4
LT		 3196};
3197
3198static int __init gfar_init(void)
3199{
1577ecef 3200 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3201}
3202
3203static void __exit gfar_exit(void)
3204{
b31a1d8b 3205 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3206}
3207
3208module_init(gfar_init);
3209module_exit(gfar_exit);
3210
Linux kernel - Deliverables
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