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[PATCH] dscc4: fix dscc4_init_dummy_skb check
[deliverable/linux.git] / drivers / net / gianfar.c
CommitLineData
0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
1da177e4
LT		 11 *
12 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * Gianfar: AKA Lambda Draconis, "Dragon"
20 * RA 11 31 24.2
21 * Dec +69 19 52
22 * V 3.84
23 * B-V +1.62
24 *
25 * Theory of operation
0bbaf069 26 *
1da177e4
LT		 27 * The driver is initialized through platform_device. Structures which
28 * define the configuration needed by the board are defined in a
29 * board structure in arch/ppc/platforms (though I do not
30 * discount the possibility that other architectures could one
bb40dcbb 31 * day be supported.
1da177e4
LT		 32 *
33 * The Gianfar Ethernet Controller uses a ring of buffer
34 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 35 * pointing to the physical address of the start of the ring.
36 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 37 * last descriptor of the ring.
38 *
39 * When a packet is received, the RXF bit in the
0bbaf069 40 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 41 * corresponding bit in the IMASK register is also set (if
42 * interrupt coalescing is active, then the interrupt may not
43 * happen immediately, but will wait until either a set number
bb40dcbb 44 * of frames or amount of time have passed). In NAPI, the
1da177e4
LT		 45 * interrupt handler will signal there is work to be done, and
46 * exit. Without NAPI, the packet(s) will be handled
47 * immediately. Both methods will start at the last known empty
0bbaf069 48 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
55 * skb.
56 *
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
65 */
66
67#include <linux/config.h>
68#include <linux/kernel.h>
69#include <linux/sched.h>
70#include <linux/string.h>
71#include <linux/errno.h>
bb40dcbb 72#include <linux/unistd.h>
1da177e4
LT		 73#include <linux/slab.h>
74#include <linux/interrupt.h>
75#include <linux/init.h>
76#include <linux/delay.h>
77#include <linux/netdevice.h>
78#include <linux/etherdevice.h>
79#include <linux/skbuff.h>
0bbaf069 80#include <linux/if_vlan.h>
1da177e4
LT		 81#include <linux/spinlock.h>
82#include <linux/mm.h>
d052d1be 83#include <linux/platform_device.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
1da177e4
LT		 88
89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/uaccess.h>
92#include <linux/module.h>
1da177e4
LT		 93#include <linux/dma-mapping.h>
94#include <linux/crc32.h>
bb40dcbb
AF		 95#include <linux/mii.h>
96#include <linux/phy.h>
1da177e4
LT		 97
98#include "gianfar.h"
bb40dcbb 99#include "gianfar_mii.h"
1da177e4
LT		 100
101#define TX_TIMEOUT (1*HZ)
102#define SKB_ALLOC_TIMEOUT 1000000
103#undef BRIEF_GFAR_ERRORS
104#undef VERBOSE_GFAR_ERRORS
105
106#ifdef CONFIG_GFAR_NAPI
107#define RECEIVE(x) netif_receive_skb(x)
108#else
109#define RECEIVE(x) netif_rx(x)
110#endif
111
112const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 113const char gfar_driver_version[] = "1.3";
1da177e4 114
1da177e4
LT		 115static int gfar_enet_open(struct net_device *dev);
116static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
117static void gfar_timeout(struct net_device *dev);
118static int gfar_close(struct net_device *dev);
119struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
120static struct net_device_stats *gfar_get_stats(struct net_device *dev);
121static int gfar_set_mac_address(struct net_device *dev);
122static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
124static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
1da177e4 125static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1da177e4
LT		 126static void adjust_link(struct net_device *dev);
127static void init_registers(struct net_device *dev);
128static int init_phy(struct net_device *dev);
3ae5eaec
RK		 129static int gfar_probe(struct platform_device *pdev);
130static int gfar_remove(struct platform_device *pdev);
bb40dcbb 131static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 132static void gfar_set_multi(struct net_device *dev);
133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134#ifdef CONFIG_GFAR_NAPI
135static int gfar_poll(struct net_device *dev, int *budget);
136#endif
0bbaf069 137int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
1da177e4 138static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
0bbaf069
KG		 139static void gfar_vlan_rx_register(struct net_device *netdev,
140 struct vlan_group *grp);
141static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
7f7f5316
AF		 142void gfar_halt(struct net_device *dev);
143void gfar_start(struct net_device *dev);
144static void gfar_clear_exact_match(struct net_device *dev);
145static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
1da177e4
LT		 146
147extern struct ethtool_ops gfar_ethtool_ops;
148
149MODULE_AUTHOR("Freescale Semiconductor, Inc");
150MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151MODULE_LICENSE("GPL");
152
7f7f5316
AF		 153/* Returns 1 if incoming frames use an FCB */
154static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 155{
7f7f5316 156 return (priv->vlan_enable || priv->rx_csum_enable);
0bbaf069 157}
bb40dcbb
AF		 158
159/* Set up the ethernet device structure, private data,
160 * and anything else we need before we start */
3ae5eaec 161static int gfar_probe(struct platform_device *pdev)
1da177e4
LT		 162{
163 u32 tempval;
164 struct net_device *dev = NULL;
165 struct gfar_private *priv = NULL;
1da177e4
LT		 166 struct gianfar_platform_data *einfo;
167 struct resource *r;
168 int idx;
169 int err = 0;
1da177e4
LT		 170
171 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
172
bb40dcbb 173 if (NULL == einfo) {
1da177e4
LT		 174 printk(KERN_ERR "gfar %d: Missing additional data!\n",
175 pdev->id);
176
177 return -ENODEV;
178 }
179
180 /* Create an ethernet device instance */
181 dev = alloc_etherdev(sizeof (*priv));
182
bb40dcbb 183 if (NULL == dev)
1da177e4
LT		 184 return -ENOMEM;
185
186 priv = netdev_priv(dev);
187
188 /* Set the info in the priv to the current info */
189 priv->einfo = einfo;
190
191 /* fill out IRQ fields */
192 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
193 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
194 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
195 priv->interruptError = platform_get_irq_byname(pdev, "error");
196 } else {
197 priv->interruptTransmit = platform_get_irq(pdev, 0);
198 }
199
200 /* get a pointer to the register memory */
201 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 priv->regs = (struct gfar *)
203 ioremap(r->start, sizeof (struct gfar));
204
bb40dcbb 205 if (NULL == priv->regs) {
1da177e4
LT		 206 err = -ENOMEM;
207 goto regs_fail;
208 }
209
1da177e4
LT		 210 spin_lock_init(&priv->lock);
211
3ae5eaec 212 platform_set_drvdata(pdev, dev);
1da177e4
LT		 213
214 /* Stop the DMA engine now, in case it was running before */
215 /* (The firmware could have used it, and left it running). */
216 /* To do this, we write Graceful Receive Stop and Graceful */
217 /* Transmit Stop, and then wait until the corresponding bits */
218 /* in IEVENT indicate the stops have completed. */
219 tempval = gfar_read(&priv->regs->dmactrl);
220 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
221 gfar_write(&priv->regs->dmactrl, tempval);
222
223 tempval = gfar_read(&priv->regs->dmactrl);
224 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
225 gfar_write(&priv->regs->dmactrl, tempval);
226
227 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
228 cpu_relax();
229
230 /* Reset MAC layer */
231 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
232
233 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
234 gfar_write(&priv->regs->maccfg1, tempval);
235
236 /* Initialize MACCFG2. */
237 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
238
239 /* Initialize ECNTRL */
240 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
241
242 /* Copy the station address into the dev structure, */
243 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
244
245 /* Set the dev->base_addr to the gfar reg region */
246 dev->base_addr = (unsigned long) (priv->regs);
247
248 SET_MODULE_OWNER(dev);
3ae5eaec 249 SET_NETDEV_DEV(dev, &pdev->dev);
1da177e4
LT		 250
251 /* Fill in the dev structure */
252 dev->open = gfar_enet_open;
253 dev->hard_start_xmit = gfar_start_xmit;
254 dev->tx_timeout = gfar_timeout;
255 dev->watchdog_timeo = TX_TIMEOUT;
256#ifdef CONFIG_GFAR_NAPI
257 dev->poll = gfar_poll;
258 dev->weight = GFAR_DEV_WEIGHT;
259#endif
260 dev->stop = gfar_close;
261 dev->get_stats = gfar_get_stats;
262 dev->change_mtu = gfar_change_mtu;
263 dev->mtu = 1500;
264 dev->set_multicast_list = gfar_set_multi;
265
0bbaf069
KG		 266 dev->ethtool_ops = &gfar_ethtool_ops;
267
268 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
269 priv->rx_csum_enable = 1;
270 dev->features |= NETIF_F_IP_CSUM;
271 } else
272 priv->rx_csum_enable = 0;
273
274 priv->vlgrp = NULL;
1da177e4 275
0bbaf069
KG		 276 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
277 dev->vlan_rx_register = gfar_vlan_rx_register;
278 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
1da177e4 279
0bbaf069
KG		 280 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
281
282 priv->vlan_enable = 1;
283 }
284
285 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
286 priv->extended_hash = 1;
287 priv->hash_width = 9;
288
289 priv->hash_regs[0] = &priv->regs->igaddr0;
290 priv->hash_regs[1] = &priv->regs->igaddr1;
291 priv->hash_regs[2] = &priv->regs->igaddr2;
292 priv->hash_regs[3] = &priv->regs->igaddr3;
293 priv->hash_regs[4] = &priv->regs->igaddr4;
294 priv->hash_regs[5] = &priv->regs->igaddr5;
295 priv->hash_regs[6] = &priv->regs->igaddr6;
296 priv->hash_regs[7] = &priv->regs->igaddr7;
297 priv->hash_regs[8] = &priv->regs->gaddr0;
298 priv->hash_regs[9] = &priv->regs->gaddr1;
299 priv->hash_regs[10] = &priv->regs->gaddr2;
300 priv->hash_regs[11] = &priv->regs->gaddr3;
301 priv->hash_regs[12] = &priv->regs->gaddr4;
302 priv->hash_regs[13] = &priv->regs->gaddr5;
303 priv->hash_regs[14] = &priv->regs->gaddr6;
304 priv->hash_regs[15] = &priv->regs->gaddr7;
305
306 } else {
307 priv->extended_hash = 0;
308 priv->hash_width = 8;
309
310 priv->hash_regs[0] = &priv->regs->gaddr0;
311 priv->hash_regs[1] = &priv->regs->gaddr1;
312 priv->hash_regs[2] = &priv->regs->gaddr2;
313 priv->hash_regs[3] = &priv->regs->gaddr3;
314 priv->hash_regs[4] = &priv->regs->gaddr4;
315 priv->hash_regs[5] = &priv->regs->gaddr5;
316 priv->hash_regs[6] = &priv->regs->gaddr6;
317 priv->hash_regs[7] = &priv->regs->gaddr7;
318 }
319
320 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
321 priv->padding = DEFAULT_PADDING;
322 else
323 priv->padding = 0;
324
0bbaf069
KG		 325 if (dev->features & NETIF_F_IP_CSUM)
326 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4
LT		 327
328 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4
LT		 329 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
330 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
331
332 priv->txcoalescing = DEFAULT_TX_COALESCE;
333 priv->txcount = DEFAULT_TXCOUNT;
334 priv->txtime = DEFAULT_TXTIME;
335 priv->rxcoalescing = DEFAULT_RX_COALESCE;
336 priv->rxcount = DEFAULT_RXCOUNT;
337 priv->rxtime = DEFAULT_RXTIME;
338
0bbaf069
KG		 339 /* Enable most messages by default */
340 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
341
1da177e4
LT		 342 err = register_netdev(dev);
343
344 if (err) {
345 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
346 dev->name);
347 goto register_fail;
348 }
349
7f7f5316
AF		 350 /* Create all the sysfs files */
351 gfar_init_sysfs(dev);
352
1da177e4
LT		 353 /* Print out the device info */
354 printk(KERN_INFO DEVICE_NAME, dev->name);
355 for (idx = 0; idx < 6; idx++)
356 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
357 printk("\n");
358
359 /* Even more device info helps when determining which kernel */
7f7f5316 360 /* provided which set of benchmarks. */
1da177e4
LT		 361#ifdef CONFIG_GFAR_NAPI
362 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
363#else
364 printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
365#endif
366 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
367 dev->name, priv->rx_ring_size, priv->tx_ring_size);
368
369 return 0;
370
371register_fail:
1da177e4
LT		 372 iounmap((void *) priv->regs);
373regs_fail:
374 free_netdev(dev);
bb40dcbb 375 return err;
1da177e4
LT		 376}
377
3ae5eaec 378static int gfar_remove(struct platform_device *pdev)
1da177e4 379{
3ae5eaec 380 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 381 struct gfar_private *priv = netdev_priv(dev);
382
3ae5eaec 383 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 384
385 iounmap((void *) priv->regs);
1da177e4
LT		 386 free_netdev(dev);
387
388 return 0;
389}
390
391
bb40dcbb
AF		 392/* Initializes driver's PHY state, and attaches to the PHY.
393 * Returns 0 on success.
1da177e4
LT		 394 */
395static int init_phy(struct net_device *dev)
396{
397 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb
AF		 398 uint gigabit_support =
399 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
400 SUPPORTED_1000baseT_Full : 0;
401 struct phy_device *phydev;
4d3248a2 402 char phy_id[BUS_ID_SIZE];
1da177e4
LT		 403
404 priv->oldlink = 0;
405 priv->oldspeed = 0;
406 priv->oldduplex = -1;
407
4d3248a2
KG		 408 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
409
410 phydev = phy_connect(dev, phy_id, &adjust_link, 0);
1da177e4 411
bb40dcbb
AF		 412 if (IS_ERR(phydev)) {
413 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
414 return PTR_ERR(phydev);
1da177e4
LT		 415 }
416
bb40dcbb
AF		 417 /* Remove any features not supported by the controller */
418 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
419 phydev->advertising = phydev->supported;
1da177e4 420
bb40dcbb 421 priv->phydev = phydev;
1da177e4
LT		 422
423 return 0;
1da177e4
LT		 424}
425
426static void init_registers(struct net_device *dev)
427{
428 struct gfar_private *priv = netdev_priv(dev);
429
430 /* Clear IEVENT */
431 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
432
433 /* Initialize IMASK */
434 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
435
436 /* Init hash registers to zero */
0bbaf069
KG		 437 gfar_write(&priv->regs->igaddr0, 0);
438 gfar_write(&priv->regs->igaddr1, 0);
439 gfar_write(&priv->regs->igaddr2, 0);
440 gfar_write(&priv->regs->igaddr3, 0);
441 gfar_write(&priv->regs->igaddr4, 0);
442 gfar_write(&priv->regs->igaddr5, 0);
443 gfar_write(&priv->regs->igaddr6, 0);
444 gfar_write(&priv->regs->igaddr7, 0);
1da177e4
LT		 445
446 gfar_write(&priv->regs->gaddr0, 0);
447 gfar_write(&priv->regs->gaddr1, 0);
448 gfar_write(&priv->regs->gaddr2, 0);
449 gfar_write(&priv->regs->gaddr3, 0);
450 gfar_write(&priv->regs->gaddr4, 0);
451 gfar_write(&priv->regs->gaddr5, 0);
452 gfar_write(&priv->regs->gaddr6, 0);
453 gfar_write(&priv->regs->gaddr7, 0);
454
1da177e4
LT		 455 /* Zero out the rmon mib registers if it has them */
456 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
457 memset((void *) &(priv->regs->rmon), 0,
458 sizeof (struct rmon_mib));
459
460 /* Mask off the CAM interrupts */
461 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
462 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
463 }
464
465 /* Initialize the max receive buffer length */
466 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
467
1da177e4
LT		 468 /* Initialize the Minimum Frame Length Register */
469 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
470
1da177e4
LT		 471 /* Assign the TBI an address which won't conflict with the PHYs */
472 gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
473}
474
0bbaf069
KG		 475
476/* Halt the receive and transmit queues */
477void gfar_halt(struct net_device *dev)
1da177e4
LT		 478{
479 struct gfar_private *priv = netdev_priv(dev);
480 struct gfar *regs = priv->regs;
1da177e4
LT		 481 u32 tempval;
482
1da177e4
LT		 483 /* Mask all interrupts */
484 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
485
486 /* Clear all interrupts */
487 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
488
489 /* Stop the DMA, and wait for it to stop */
490 tempval = gfar_read(&priv->regs->dmactrl);
491 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
492 != (DMACTRL_GRS | DMACTRL_GTS)) {
493 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
494 gfar_write(&priv->regs->dmactrl, tempval);
495
496 while (!(gfar_read(&priv->regs->ievent) &
497 (IEVENT_GRSC | IEVENT_GTSC)))
498 cpu_relax();
499 }
500
501 /* Disable Rx and Tx */
502 tempval = gfar_read(&regs->maccfg1);
503 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
504 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 505}
506
507void stop_gfar(struct net_device *dev)
508{
509 struct gfar_private *priv = netdev_priv(dev);
510 struct gfar *regs = priv->regs;
511 unsigned long flags;
512
bb40dcbb
AF		 513 phy_stop(priv->phydev);
514
0bbaf069
KG		 515 /* Lock it down */
516 spin_lock_irqsave(&priv->lock, flags);
517
0bbaf069 518 gfar_halt(dev);
1da177e4 519
1da177e4
LT		 520 spin_unlock_irqrestore(&priv->lock, flags);
521
522 /* Free the IRQs */
523 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
524 free_irq(priv->interruptError, dev);
525 free_irq(priv->interruptTransmit, dev);
526 free_irq(priv->interruptReceive, dev);
527 } else {
bb40dcbb 528 free_irq(priv->interruptTransmit, dev);
1da177e4
LT		 529 }
530
531 free_skb_resources(priv);
532
533 dma_free_coherent(NULL,
534 sizeof(struct txbd8)*priv->tx_ring_size
535 + sizeof(struct rxbd8)*priv->rx_ring_size,
536 priv->tx_bd_base,
0bbaf069 537 gfar_read(&regs->tbase0));
1da177e4
LT		 538}
539
540/* If there are any tx skbs or rx skbs still around, free them.
541 * Then free tx_skbuff and rx_skbuff */
bb40dcbb 542static void free_skb_resources(struct gfar_private *priv)
1da177e4
LT		 543{
544 struct rxbd8 *rxbdp;
545 struct txbd8 *txbdp;
546 int i;
547
548 /* Go through all the buffer descriptors and free their data buffers */
549 txbdp = priv->tx_bd_base;
550
551 for (i = 0; i < priv->tx_ring_size; i++) {
552
553 if (priv->tx_skbuff[i]) {
554 dma_unmap_single(NULL, txbdp->bufPtr,
555 txbdp->length,
556 DMA_TO_DEVICE);
557 dev_kfree_skb_any(priv->tx_skbuff[i]);
558 priv->tx_skbuff[i] = NULL;
559 }
560 }
561
562 kfree(priv->tx_skbuff);
563
564 rxbdp = priv->rx_bd_base;
565
566 /* rx_skbuff is not guaranteed to be allocated, so only
567 * free it and its contents if it is allocated */
568 if(priv->rx_skbuff != NULL) {
569 for (i = 0; i < priv->rx_ring_size; i++) {
570 if (priv->rx_skbuff[i]) {
571 dma_unmap_single(NULL, rxbdp->bufPtr,
7f7f5316 572 priv->rx_buffer_size,
1da177e4
LT		 573 DMA_FROM_DEVICE);
574
575 dev_kfree_skb_any(priv->rx_skbuff[i]);
576 priv->rx_skbuff[i] = NULL;
577 }
578
579 rxbdp->status = 0;
580 rxbdp->length = 0;
581 rxbdp->bufPtr = 0;
582
583 rxbdp++;
584 }
585
586 kfree(priv->rx_skbuff);
587 }
588}
589
0bbaf069
KG		 590void gfar_start(struct net_device *dev)
591{
592 struct gfar_private *priv = netdev_priv(dev);
593 struct gfar *regs = priv->regs;
594 u32 tempval;
595
596 /* Enable Rx and Tx in MACCFG1 */
597 tempval = gfar_read(&regs->maccfg1);
598 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
599 gfar_write(&regs->maccfg1, tempval);
600
601 /* Initialize DMACTRL to have WWR and WOP */
602 tempval = gfar_read(&priv->regs->dmactrl);
603 tempval |= DMACTRL_INIT_SETTINGS;
604 gfar_write(&priv->regs->dmactrl, tempval);
605
606 /* Clear THLT, so that the DMA starts polling now */
607 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
608
609 /* Make sure we aren't stopped */
610 tempval = gfar_read(&priv->regs->dmactrl);
611 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
612 gfar_write(&priv->regs->dmactrl, tempval);
613
614 /* Unmask the interrupts we look for */
615 gfar_write(&regs->imask, IMASK_DEFAULT);
616}
617
1da177e4
LT		 618/* Bring the controller up and running */
619int startup_gfar(struct net_device *dev)
620{
621 struct txbd8 *txbdp;
622 struct rxbd8 *rxbdp;
623 dma_addr_t addr;
624 unsigned long vaddr;
625 int i;
626 struct gfar_private *priv = netdev_priv(dev);
627 struct gfar *regs = priv->regs;
1da177e4 628 int err = 0;
0bbaf069 629 u32 rctrl = 0;
7f7f5316 630 u32 attrs = 0;
1da177e4
LT		 631
632 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
633
634 /* Allocate memory for the buffer descriptors */
0bbaf069 635 vaddr = (unsigned long) dma_alloc_coherent(NULL,
1da177e4
LT		 636 sizeof (struct txbd8) * priv->tx_ring_size +
637 sizeof (struct rxbd8) * priv->rx_ring_size,
638 &addr, GFP_KERNEL);
639
640 if (vaddr == 0) {
0bbaf069
KG		 641 if (netif_msg_ifup(priv))
642 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
643 dev->name);
1da177e4
LT		 644 return -ENOMEM;
645 }
646
647 priv->tx_bd_base = (struct txbd8 *) vaddr;
648
649 /* enet DMA only understands physical addresses */
0bbaf069 650 gfar_write(&regs->tbase0, addr);
1da177e4
LT		 651
652 /* Start the rx descriptor ring where the tx ring leaves off */
653 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
654 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
655 priv->rx_bd_base = (struct rxbd8 *) vaddr;
0bbaf069 656 gfar_write(&regs->rbase0, addr);
1da177e4
LT		 657
658 /* Setup the skbuff rings */
659 priv->tx_skbuff =
660 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
661 priv->tx_ring_size, GFP_KERNEL);
662
bb40dcbb 663 if (NULL == priv->tx_skbuff) {
0bbaf069
KG		 664 if (netif_msg_ifup(priv))
665 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
666 dev->name);
1da177e4
LT		 667 err = -ENOMEM;
668 goto tx_skb_fail;
669 }
670
671 for (i = 0; i < priv->tx_ring_size; i++)
672 priv->tx_skbuff[i] = NULL;
673
674 priv->rx_skbuff =
675 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
676 priv->rx_ring_size, GFP_KERNEL);
677
bb40dcbb 678 if (NULL == priv->rx_skbuff) {
0bbaf069
KG		 679 if (netif_msg_ifup(priv))
680 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
681 dev->name);
1da177e4
LT		 682 err = -ENOMEM;
683 goto rx_skb_fail;
684 }
685
686 for (i = 0; i < priv->rx_ring_size; i++)
687 priv->rx_skbuff[i] = NULL;
688
689 /* Initialize some variables in our dev structure */
690 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
691 priv->cur_rx = priv->rx_bd_base;
692 priv->skb_curtx = priv->skb_dirtytx = 0;
693 priv->skb_currx = 0;
694
695 /* Initialize Transmit Descriptor Ring */
696 txbdp = priv->tx_bd_base;
697 for (i = 0; i < priv->tx_ring_size; i++) {
698 txbdp->status = 0;
699 txbdp->length = 0;
700 txbdp->bufPtr = 0;
701 txbdp++;
702 }
703
704 /* Set the last descriptor in the ring to indicate wrap */
705 txbdp--;
706 txbdp->status |= TXBD_WRAP;
707
708 rxbdp = priv->rx_bd_base;
709 for (i = 0; i < priv->rx_ring_size; i++) {
710 struct sk_buff *skb = NULL;
711
712 rxbdp->status = 0;
713
714 skb = gfar_new_skb(dev, rxbdp);
715
716 priv->rx_skbuff[i] = skb;
717
718 rxbdp++;
719 }
720
721 /* Set the last descriptor in the ring to wrap */
722 rxbdp--;
723 rxbdp->status |= RXBD_WRAP;
724
725 /* If the device has multiple interrupts, register for
726 * them. Otherwise, only register for the one */
727 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 728 /* Install our interrupt handlers for Error,
1da177e4
LT		 729 * Transmit, and Receive */
730 if (request_irq(priv->interruptError, gfar_error,
731 0, "enet_error", dev) < 0) {
0bbaf069
KG		 732 if (netif_msg_intr(priv))
733 printk(KERN_ERR "%s: Can't get IRQ %d\n",
734 dev->name, priv->interruptError);
1da177e4
LT		 735
736 err = -1;
737 goto err_irq_fail;
738 }
739
740 if (request_irq(priv->interruptTransmit, gfar_transmit,
741 0, "enet_tx", dev) < 0) {
0bbaf069
KG		 742 if (netif_msg_intr(priv))
743 printk(KERN_ERR "%s: Can't get IRQ %d\n",
744 dev->name, priv->interruptTransmit);
1da177e4
LT		 745
746 err = -1;
747
748 goto tx_irq_fail;
749 }
750
751 if (request_irq(priv->interruptReceive, gfar_receive,
752 0, "enet_rx", dev) < 0) {
0bbaf069
KG		 753 if (netif_msg_intr(priv))
754 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
755 dev->name, priv->interruptReceive);
1da177e4
LT		 756
757 err = -1;
758 goto rx_irq_fail;
759 }
760 } else {
761 if (request_irq(priv->interruptTransmit, gfar_interrupt,
762 0, "gfar_interrupt", dev) < 0) {
0bbaf069
KG		 763 if (netif_msg_intr(priv))
764 printk(KERN_ERR "%s: Can't get IRQ %d\n",
765 dev->name, priv->interruptError);
1da177e4
LT		 766
767 err = -1;
768 goto err_irq_fail;
769 }
770 }
771
bb40dcbb 772 phy_start(priv->phydev);
1da177e4
LT		 773
774 /* Configure the coalescing support */
775 if (priv->txcoalescing)
776 gfar_write(&regs->txic,
777 mk_ic_value(priv->txcount, priv->txtime));
778 else
779 gfar_write(&regs->txic, 0);
780
781 if (priv->rxcoalescing)
782 gfar_write(&regs->rxic,
783 mk_ic_value(priv->rxcount, priv->rxtime));
784 else
785 gfar_write(&regs->rxic, 0);
786
0bbaf069
KG		 787 if (priv->rx_csum_enable)
788 rctrl |= RCTRL_CHECKSUMMING;
1da177e4 789
7f7f5316 790 if (priv->extended_hash) {
0bbaf069 791 rctrl |= RCTRL_EXTHASH;
1da177e4 792
7f7f5316
AF		 793 gfar_clear_exact_match(dev);
794 rctrl |= RCTRL_EMEN;
795 }
796
0bbaf069
KG		 797 if (priv->vlan_enable)
798 rctrl |= RCTRL_VLAN;
1da177e4 799
7f7f5316
AF		 800 if (priv->padding) {
801 rctrl &= ~RCTRL_PAL_MASK;
802 rctrl |= RCTRL_PADDING(priv->padding);
803 }
804
0bbaf069
KG		 805 /* Init rctrl based on our settings */
806 gfar_write(&priv->regs->rctrl, rctrl);
1da177e4 807
0bbaf069
KG		 808 if (dev->features & NETIF_F_IP_CSUM)
809 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1da177e4 810
7f7f5316
AF		 811 /* Set the extraction length and index */
812 attrs = ATTRELI_EL(priv->rx_stash_size) |
813 ATTRELI_EI(priv->rx_stash_index);
814
815 gfar_write(&priv->regs->attreli, attrs);
816
817 /* Start with defaults, and add stashing or locking
818 * depending on the approprate variables */
819 attrs = ATTR_INIT_SETTINGS;
820
821 if (priv->bd_stash_en)
822 attrs |= ATTR_BDSTASH;
823
824 if (priv->rx_stash_size != 0)
825 attrs |= ATTR_BUFSTASH;
826
827 gfar_write(&priv->regs->attr, attrs);
828
829 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
830 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
831 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
832
833 /* Start the controller */
0bbaf069 834 gfar_start(dev);
1da177e4
LT		 835
836 return 0;
837
838rx_irq_fail:
839 free_irq(priv->interruptTransmit, dev);
840tx_irq_fail:
841 free_irq(priv->interruptError, dev);
842err_irq_fail:
843rx_skb_fail:
844 free_skb_resources(priv);
845tx_skb_fail:
846 dma_free_coherent(NULL,
847 sizeof(struct txbd8)*priv->tx_ring_size
848 + sizeof(struct rxbd8)*priv->rx_ring_size,
849 priv->tx_bd_base,
0bbaf069 850 gfar_read(&regs->tbase0));
1da177e4 851
1da177e4
LT		 852 return err;
853}
854
855/* Called when something needs to use the ethernet device */
856/* Returns 0 for success. */
857static int gfar_enet_open(struct net_device *dev)
858{
859 int err;
860
861 /* Initialize a bunch of registers */
862 init_registers(dev);
863
864 gfar_set_mac_address(dev);
865
866 err = init_phy(dev);
867
868 if(err)
869 return err;
870
871 err = startup_gfar(dev);
872
873 netif_start_queue(dev);
874
875 return err;
876}
877
7f7f5316 878static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
0bbaf069
KG		 879{
880 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
881
882 memset(fcb, 0, GMAC_FCB_LEN);
883
0bbaf069
KG		 884 return fcb;
885}
886
887static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
888{
7f7f5316 889 u8 flags = 0;
0bbaf069
KG		 890
891 /* If we're here, it's a IP packet with a TCP or UDP
892 * payload. We set it to checksum, using a pseudo-header
893 * we provide
894 */
7f7f5316 895 flags = TXFCB_DEFAULT;
0bbaf069 896
7f7f5316
AF		 897 /* Tell the controller what the protocol is */
898 /* And provide the already calculated phcs */
899 if (skb->nh.iph->protocol == IPPROTO_UDP) {
900 flags |= TXFCB_UDP;
901 fcb->phcs = skb->h.uh->check;
902 } else
903 fcb->phcs = skb->h.th->check;
0bbaf069
KG		 904
905 /* l3os is the distance between the start of the
906 * frame (skb->data) and the start of the IP hdr.
907 * l4os is the distance between the start of the
908 * l3 hdr and the l4 hdr */
909 fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
910 fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
911
7f7f5316 912 fcb->flags = flags;
0bbaf069
KG		 913}
914
7f7f5316 915void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 916{
7f7f5316 917 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 918 fcb->vlctl = vlan_tx_tag_get(skb);
919}
920
1da177e4
LT		 921/* This is called by the kernel when a frame is ready for transmission. */
922/* It is pointed to by the dev->hard_start_xmit function pointer */
923static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
924{
925 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 926 struct txfcb *fcb = NULL;
1da177e4 927 struct txbd8 *txbdp;
7f7f5316 928 u16 status;
1da177e4
LT		 929
930 /* Update transmit stats */
931 priv->stats.tx_bytes += skb->len;
932
933 /* Lock priv now */
934 spin_lock_irq(&priv->lock);
935
936 /* Point at the first free tx descriptor */
937 txbdp = priv->cur_tx;
938
939 /* Clear all but the WRAP status flags */
7f7f5316 940 status = txbdp->status & TXBD_WRAP;
1da177e4 941
0bbaf069 942 /* Set up checksumming */
7f7f5316
AF		 943 if (likely((dev->features & NETIF_F_IP_CSUM)
944 && (CHECKSUM_HW == skb->ip_summed))) {
0bbaf069 945 fcb = gfar_add_fcb(skb, txbdp);
7f7f5316 946 status |= TXBD_TOE;
0bbaf069
KG		 947 gfar_tx_checksum(skb, fcb);
948 }
949
950 if (priv->vlan_enable &&
951 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
7f7f5316 952 if (unlikely(NULL == fcb)) {
0bbaf069 953 fcb = gfar_add_fcb(skb, txbdp);
7f7f5316
AF		 954 status |= TXBD_TOE;
955 }
0bbaf069
KG		 956
957 gfar_tx_vlan(skb, fcb);
958 }
959
1da177e4
LT		 960 /* Set buffer length and pointer */
961 txbdp->length = skb->len;
0bbaf069 962 txbdp->bufPtr = dma_map_single(NULL, skb->data,
1da177e4
LT		 963 skb->len, DMA_TO_DEVICE);
964
965 /* Save the skb pointer so we can free it later */
966 priv->tx_skbuff[priv->skb_curtx] = skb;
967
968 /* Update the current skb pointer (wrapping if this was the last) */
969 priv->skb_curtx =
970 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
971
972 /* Flag the BD as interrupt-causing */
7f7f5316 973 status |= TXBD_INTERRUPT;
1da177e4
LT		 974
975 /* Flag the BD as ready to go, last in frame, and */
976 /* in need of CRC */
7f7f5316 977 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1da177e4
LT		 978
979 dev->trans_start = jiffies;
980
7f7f5316
AF		 981 txbdp->status = status;
982
1da177e4
LT		 983 /* If this was the last BD in the ring, the next one */
984 /* is at the beginning of the ring */
985 if (txbdp->status & TXBD_WRAP)
986 txbdp = priv->tx_bd_base;
987 else
988 txbdp++;
989
990 /* If the next BD still needs to be cleaned up, then the bds
991 are full. We need to tell the kernel to stop sending us stuff. */
992 if (txbdp == priv->dirty_tx) {
993 netif_stop_queue(dev);
994
995 priv->stats.tx_fifo_errors++;
996 }
997
998 /* Update the current txbd to the next one */
999 priv->cur_tx = txbdp;
1000
1001 /* Tell the DMA to go go go */
1002 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1003
1004 /* Unlock priv */
1005 spin_unlock_irq(&priv->lock);
1006
1007 return 0;
1008}
1009
1010/* Stops the kernel queue, and halts the controller */
1011static int gfar_close(struct net_device *dev)
1012{
1013 struct gfar_private *priv = netdev_priv(dev);
1014 stop_gfar(dev);
1015
bb40dcbb
AF		 1016 /* Disconnect from the PHY */
1017 phy_disconnect(priv->phydev);
1018 priv->phydev = NULL;
1da177e4
LT		 1019
1020 netif_stop_queue(dev);
1021
1022 return 0;
1023}
1024
1025/* returns a net_device_stats structure pointer */
1026static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1027{
1028 struct gfar_private *priv = netdev_priv(dev);
1029
1030 return &(priv->stats);
1031}
1032
1033/* Changes the mac address if the controller is not running. */
1034int gfar_set_mac_address(struct net_device *dev)
1035{
7f7f5316 1036 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 1037
1038 return 0;
1039}
1040
1041
0bbaf069
KG		 1042/* Enables and disables VLAN insertion/extraction */
1043static void gfar_vlan_rx_register(struct net_device *dev,
1044 struct vlan_group *grp)
1045{
1046 struct gfar_private *priv = netdev_priv(dev);
1047 unsigned long flags;
1048 u32 tempval;
1049
1050 spin_lock_irqsave(&priv->lock, flags);
1051
1052 priv->vlgrp = grp;
1053
1054 if (grp) {
1055 /* Enable VLAN tag insertion */
1056 tempval = gfar_read(&priv->regs->tctrl);
1057 tempval |= TCTRL_VLINS;
1058
1059 gfar_write(&priv->regs->tctrl, tempval);
1060
1061 /* Enable VLAN tag extraction */
1062 tempval = gfar_read(&priv->regs->rctrl);
1063 tempval |= RCTRL_VLEX;
1064 gfar_write(&priv->regs->rctrl, tempval);
1065 } else {
1066 /* Disable VLAN tag insertion */
1067 tempval = gfar_read(&priv->regs->tctrl);
1068 tempval &= ~TCTRL_VLINS;
1069 gfar_write(&priv->regs->tctrl, tempval);
1070
1071 /* Disable VLAN tag extraction */
1072 tempval = gfar_read(&priv->regs->rctrl);
1073 tempval &= ~RCTRL_VLEX;
1074 gfar_write(&priv->regs->rctrl, tempval);
1075 }
1076
1077 spin_unlock_irqrestore(&priv->lock, flags);
1078}
1079
1080
1081static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1082{
1083 struct gfar_private *priv = netdev_priv(dev);
1084 unsigned long flags;
1085
1086 spin_lock_irqsave(&priv->lock, flags);
1087
1088 if (priv->vlgrp)
1089 priv->vlgrp->vlan_devices[vid] = NULL;
1090
1091 spin_unlock_irqrestore(&priv->lock, flags);
1092}
1093
1094
1da177e4
LT		 1095static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1096{
1097 int tempsize, tempval;
1098 struct gfar_private *priv = netdev_priv(dev);
1099 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 1100 int frame_size = new_mtu + ETH_HLEN;
1101
1102 if (priv->vlan_enable)
1103 frame_size += VLAN_ETH_HLEN;
1104
1105 if (gfar_uses_fcb(priv))
1106 frame_size += GMAC_FCB_LEN;
1107
1108 frame_size += priv->padding;
1da177e4
LT		 1109
1110 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 1111 if (netif_msg_drv(priv))
1112 printk(KERN_ERR "%s: Invalid MTU setting\n",
1113 dev->name);
1da177e4
LT		 1114 return -EINVAL;
1115 }
1116
1117 tempsize =
1118 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1119 INCREMENTAL_BUFFER_SIZE;
1120
1121 /* Only stop and start the controller if it isn't already
7f7f5316 1122 * stopped, and we changed something */
1da177e4
LT		 1123 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1124 stop_gfar(dev);
1125
1126 priv->rx_buffer_size = tempsize;
1127
1128 dev->mtu = new_mtu;
1129
1130 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1131 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1132
1133 /* If the mtu is larger than the max size for standard
1134 * ethernet frames (ie, a jumbo frame), then set maccfg2
1135 * to allow huge frames, and to check the length */
1136 tempval = gfar_read(&priv->regs->maccfg2);
1137
1138 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1139 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1140 else
1141 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1142
1143 gfar_write(&priv->regs->maccfg2, tempval);
1144
1145 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1146 startup_gfar(dev);
1147
1148 return 0;
1149}
1150
1151/* gfar_timeout gets called when a packet has not been
1152 * transmitted after a set amount of time.
1153 * For now, assume that clearing out all the structures, and
1154 * starting over will fix the problem. */
1155static void gfar_timeout(struct net_device *dev)
1156{
1157 struct gfar_private *priv = netdev_priv(dev);
1158
1159 priv->stats.tx_errors++;
1160
1161 if (dev->flags & IFF_UP) {
1162 stop_gfar(dev);
1163 startup_gfar(dev);
1164 }
1165
1166 netif_schedule(dev);
1167}
1168
1169/* Interrupt Handler for Transmit complete */
1170static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs)
1171{
1172 struct net_device *dev = (struct net_device *) dev_id;
1173 struct gfar_private *priv = netdev_priv(dev);
1174 struct txbd8 *bdp;
1175
1176 /* Clear IEVENT */
1177 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1178
1179 /* Lock priv */
1180 spin_lock(&priv->lock);
1181 bdp = priv->dirty_tx;
1182 while ((bdp->status & TXBD_READY) == 0) {
1183 /* If dirty_tx and cur_tx are the same, then either the */
1184 /* ring is empty or full now (it could only be full in the beginning, */
1185 /* obviously). If it is empty, we are done. */
1186 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1187 break;
1188
1189 priv->stats.tx_packets++;
1190
1191 /* Deferred means some collisions occurred during transmit, */
1192 /* but we eventually sent the packet. */
1193 if (bdp->status & TXBD_DEF)
1194 priv->stats.collisions++;
1195
1196 /* Free the sk buffer associated with this TxBD */
1197 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1198 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1199 priv->skb_dirtytx =
1200 (priv->skb_dirtytx +
1201 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1202
1203 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1204 if (bdp->status & TXBD_WRAP)
1205 bdp = priv->tx_bd_base;
1206 else
1207 bdp++;
1208
1209 /* Move dirty_tx to be the next bd */
1210 priv->dirty_tx = bdp;
1211
1212 /* We freed a buffer, so now we can restart transmission */
1213 if (netif_queue_stopped(dev))
1214 netif_wake_queue(dev);
1215 } /* while ((bdp->status & TXBD_READY) == 0) */
1216
1217 /* If we are coalescing the interrupts, reset the timer */
1218 /* Otherwise, clear it */
1219 if (priv->txcoalescing)
1220 gfar_write(&priv->regs->txic,
1221 mk_ic_value(priv->txcount, priv->txtime));
1222 else
1223 gfar_write(&priv->regs->txic, 0);
1224
1225 spin_unlock(&priv->lock);
1226
1227 return IRQ_HANDLED;
1228}
1229
1230struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1231{
7f7f5316 1232 unsigned int alignamount;
1da177e4
LT		 1233 struct gfar_private *priv = netdev_priv(dev);
1234 struct sk_buff *skb = NULL;
1235 unsigned int timeout = SKB_ALLOC_TIMEOUT;
1236
1237 /* We have to allocate the skb, so keep trying till we succeed */
1238 while ((!skb) && timeout--)
1239 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1240
bb40dcbb 1241 if (NULL == skb)
1da177e4
LT		 1242 return NULL;
1243
7f7f5316
AF		 1244 alignamount = RXBUF_ALIGNMENT -
1245 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1246
1da177e4
LT		 1247 /* We need the data buffer to be aligned properly. We will reserve
1248 * as many bytes as needed to align the data properly
1249 */
7f7f5316 1250 skb_reserve(skb, alignamount);
1da177e4
LT		 1251
1252 skb->dev = dev;
1253
1254 bdp->bufPtr = dma_map_single(NULL, skb->data,
7f7f5316 1255 priv->rx_buffer_size, DMA_FROM_DEVICE);
1da177e4
LT		 1256
1257 bdp->length = 0;
1258
1259 /* Mark the buffer empty */
1260 bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1261
1262 return skb;
1263}
1264
1265static inline void count_errors(unsigned short status, struct gfar_private *priv)
1266{
1267 struct net_device_stats *stats = &priv->stats;
1268 struct gfar_extra_stats *estats = &priv->extra_stats;
1269
1270 /* If the packet was truncated, none of the other errors
1271 * matter */
1272 if (status & RXBD_TRUNCATED) {
1273 stats->rx_length_errors++;
1274
1275 estats->rx_trunc++;
1276
1277 return;
1278 }
1279 /* Count the errors, if there were any */
1280 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1281 stats->rx_length_errors++;
1282
1283 if (status & RXBD_LARGE)
1284 estats->rx_large++;
1285 else
1286 estats->rx_short++;
1287 }
1288 if (status & RXBD_NONOCTET) {
1289 stats->rx_frame_errors++;
1290 estats->rx_nonoctet++;
1291 }
1292 if (status & RXBD_CRCERR) {
1293 estats->rx_crcerr++;
1294 stats->rx_crc_errors++;
1295 }
1296 if (status & RXBD_OVERRUN) {
1297 estats->rx_overrun++;
1298 stats->rx_crc_errors++;
1299 }
1300}
1301
1302irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1303{
1304 struct net_device *dev = (struct net_device *) dev_id;
1305 struct gfar_private *priv = netdev_priv(dev);
1306
1307#ifdef CONFIG_GFAR_NAPI
1308 u32 tempval;
1309#endif
1310
1311 /* Clear IEVENT, so rx interrupt isn't called again
1312 * because of this interrupt */
1313 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1314
1315 /* support NAPI */
1316#ifdef CONFIG_GFAR_NAPI
1317 if (netif_rx_schedule_prep(dev)) {
1318 tempval = gfar_read(&priv->regs->imask);
1319 tempval &= IMASK_RX_DISABLED;
1320 gfar_write(&priv->regs->imask, tempval);
1321
1322 __netif_rx_schedule(dev);
1323 } else {
0bbaf069
KG		 1324 if (netif_msg_rx_err(priv))
1325 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1326 dev->name, gfar_read(&priv->regs->ievent),
1327 gfar_read(&priv->regs->imask));
1da177e4
LT		 1328 }
1329#else
1330
1331 spin_lock(&priv->lock);
1332 gfar_clean_rx_ring(dev, priv->rx_ring_size);
1333
1334 /* If we are coalescing interrupts, update the timer */
1335 /* Otherwise, clear it */
1336 if (priv->rxcoalescing)
1337 gfar_write(&priv->regs->rxic,
1338 mk_ic_value(priv->rxcount, priv->rxtime));
1339 else
1340 gfar_write(&priv->regs->rxic, 0);
1341
1da177e4
LT		 1342 spin_unlock(&priv->lock);
1343#endif
1344
1345 return IRQ_HANDLED;
1346}
1347
0bbaf069
KG		 1348static inline int gfar_rx_vlan(struct sk_buff *skb,
1349 struct vlan_group *vlgrp, unsigned short vlctl)
1350{
1351#ifdef CONFIG_GFAR_NAPI
1352 return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1353#else
1354 return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1355#endif
1356}
1357
1358static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1359{
1360 /* If valid headers were found, and valid sums
1361 * were verified, then we tell the kernel that no
1362 * checksumming is necessary. Otherwise, it is */
7f7f5316 1363 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 1364 skb->ip_summed = CHECKSUM_UNNECESSARY;
1365 else
1366 skb->ip_summed = CHECKSUM_NONE;
1367}
1368
1369
1370static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1371{
1372 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1373
1374 /* Remove the FCB from the skb */
1375 skb_pull(skb, GMAC_FCB_LEN);
1376
1377 return fcb;
1378}
1da177e4
LT		 1379
1380/* gfar_process_frame() -- handle one incoming packet if skb
1381 * isn't NULL. */
1382static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1383 int length)
1384{
1385 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1386 struct rxfcb *fcb = NULL;
1da177e4 1387
bb40dcbb 1388 if (NULL == skb) {
0bbaf069
KG		 1389 if (netif_msg_rx_err(priv))
1390 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1da177e4
LT		 1391 priv->stats.rx_dropped++;
1392 priv->extra_stats.rx_skbmissing++;
1393 } else {
0bbaf069
KG		 1394 int ret;
1395
1da177e4
LT		 1396 /* Prep the skb for the packet */
1397 skb_put(skb, length);
1398
0bbaf069
KG		 1399 /* Grab the FCB if there is one */
1400 if (gfar_uses_fcb(priv))
1401 fcb = gfar_get_fcb(skb);
1402
1403 /* Remove the padded bytes, if there are any */
1404 if (priv->padding)
1405 skb_pull(skb, priv->padding);
1406
1407 if (priv->rx_csum_enable)
1408 gfar_rx_checksum(skb, fcb);
1409
1da177e4
LT		 1410 /* Tell the skb what kind of packet this is */
1411 skb->protocol = eth_type_trans(skb, dev);
1412
1413 /* Send the packet up the stack */
7f7f5316 1414 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
0bbaf069
KG		 1415 ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1416 else
1417 ret = RECEIVE(skb);
1418
1419 if (NET_RX_DROP == ret)
1da177e4 1420 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 1421 }
1422
1423 return 0;
1424}
1425
1426/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 1427 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 1428 * of frames handled
1429 */
0bbaf069 1430int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1da177e4
LT		 1431{
1432 struct rxbd8 *bdp;
1433 struct sk_buff *skb;
1434 u16 pkt_len;
1435 int howmany = 0;
1436 struct gfar_private *priv = netdev_priv(dev);
1437
1438 /* Get the first full descriptor */
1439 bdp = priv->cur_rx;
1440
1441 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1442 skb = priv->rx_skbuff[priv->skb_currx];
1443
1444 if (!(bdp->status &
1445 (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1446 | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1447 /* Increment the number of packets */
1448 priv->stats.rx_packets++;
1449 howmany++;
1450
1451 /* Remove the FCS from the packet length */
1452 pkt_len = bdp->length - 4;
1453
1454 gfar_process_frame(dev, skb, pkt_len);
1455
1456 priv->stats.rx_bytes += pkt_len;
1457 } else {
1458 count_errors(bdp->status, priv);
1459
1460 if (skb)
1461 dev_kfree_skb_any(skb);
1462
1463 priv->rx_skbuff[priv->skb_currx] = NULL;
1464 }
1465
1466 dev->last_rx = jiffies;
1467
1468 /* Clear the status flags for this buffer */
1469 bdp->status &= ~RXBD_STATS;
1470
1471 /* Add another skb for the future */
1472 skb = gfar_new_skb(dev, bdp);
1473 priv->rx_skbuff[priv->skb_currx] = skb;
1474
1475 /* Update to the next pointer */
1476 if (bdp->status & RXBD_WRAP)
1477 bdp = priv->rx_bd_base;
1478 else
1479 bdp++;
1480
1481 /* update to point at the next skb */
1482 priv->skb_currx =
1483 (priv->skb_currx +
1484 1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1485
1486 }
1487
1488 /* Update the current rxbd pointer to be the next one */
1489 priv->cur_rx = bdp;
1490
1491 /* If no packets have arrived since the
1492 * last one we processed, clear the IEVENT RX and
1493 * BSY bits so that another interrupt won't be
1494 * generated when we set IMASK */
1495 if (bdp->status & RXBD_EMPTY)
1496 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1497
1498 return howmany;
1499}
1500
1501#ifdef CONFIG_GFAR_NAPI
1502static int gfar_poll(struct net_device *dev, int *budget)
1503{
1504 int howmany;
1505 struct gfar_private *priv = netdev_priv(dev);
1506 int rx_work_limit = *budget;
1507
1508 if (rx_work_limit > dev->quota)
1509 rx_work_limit = dev->quota;
1510
1511 howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1512
1513 dev->quota -= howmany;
1514 rx_work_limit -= howmany;
1515 *budget -= howmany;
1516
1517 if (rx_work_limit >= 0) {
1518 netif_rx_complete(dev);
1519
1520 /* Clear the halt bit in RSTAT */
1521 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1522
1523 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1524
1525 /* If we are coalescing interrupts, update the timer */
1526 /* Otherwise, clear it */
1527 if (priv->rxcoalescing)
1528 gfar_write(&priv->regs->rxic,
1529 mk_ic_value(priv->rxcount, priv->rxtime));
1530 else
1531 gfar_write(&priv->regs->rxic, 0);
1da177e4
LT		 1532 }
1533
1534 return (rx_work_limit < 0) ? 1 : 0;
1535}
1536#endif
1537
1538/* The interrupt handler for devices with one interrupt */
1539static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1540{
1541 struct net_device *dev = dev_id;
1542 struct gfar_private *priv = netdev_priv(dev);
1543
1544 /* Save ievent for future reference */
1545 u32 events = gfar_read(&priv->regs->ievent);
1546
1547 /* Clear IEVENT */
1548 gfar_write(&priv->regs->ievent, events);
1549
1550 /* Check for reception */
1551 if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1552 gfar_receive(irq, dev_id, regs);
1553
1554 /* Check for transmit completion */
1555 if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1556 gfar_transmit(irq, dev_id, regs);
1557
1558 /* Update error statistics */
1559 if (events & IEVENT_TXE) {
1560 priv->stats.tx_errors++;
1561
1562 if (events & IEVENT_LC)
1563 priv->stats.tx_window_errors++;
1564 if (events & IEVENT_CRL)
1565 priv->stats.tx_aborted_errors++;
1566 if (events & IEVENT_XFUN) {
0bbaf069
KG		 1567 if (netif_msg_tx_err(priv))
1568 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1da177e4
LT		 1569 priv->stats.tx_dropped++;
1570 priv->extra_stats.tx_underrun++;
1571
1572 /* Reactivate the Tx Queues */
1573 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1574 }
1575 }
1576 if (events & IEVENT_BSY) {
1577 priv->stats.rx_errors++;
1578 priv->extra_stats.rx_bsy++;
1579
1580 gfar_receive(irq, dev_id, regs);
1581
1582#ifndef CONFIG_GFAR_NAPI
1583 /* Clear the halt bit in RSTAT */
1584 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1585#endif
1586
0bbaf069
KG		 1587 if (netif_msg_rx_err(priv))
1588 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1589 dev->name,
1590 gfar_read(&priv->regs->rstat));
1da177e4
LT		 1591 }
1592 if (events & IEVENT_BABR) {
1593 priv->stats.rx_errors++;
1594 priv->extra_stats.rx_babr++;
1595
0bbaf069
KG		 1596 if (netif_msg_rx_err(priv))
1597 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1da177e4
LT		 1598 }
1599 if (events & IEVENT_EBERR) {
1600 priv->extra_stats.eberr++;
0bbaf069
KG		 1601 if (netif_msg_rx_err(priv))
1602 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1da177e4 1603 }
0bbaf069
KG		 1604 if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1605 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 1606
1607 if (events & IEVENT_BABT) {
1608 priv->extra_stats.tx_babt++;
0bbaf069
KG		 1609 if (netif_msg_rx_err(priv))
1610 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1da177e4
LT		 1611 }
1612
1613 return IRQ_HANDLED;
1614}
1615
1da177e4
LT		 1616/* Called every time the controller might need to be made
1617 * aware of new link state. The PHY code conveys this
bb40dcbb 1618 * information through variables in the phydev structure, and this
1da177e4
LT		 1619 * function converts those variables into the appropriate
1620 * register values, and can bring down the device if needed.
1621 */
1622static void adjust_link(struct net_device *dev)
1623{
1624 struct gfar_private *priv = netdev_priv(dev);
1625 struct gfar *regs = priv->regs;
bb40dcbb
AF		 1626 unsigned long flags;
1627 struct phy_device *phydev = priv->phydev;
1628 int new_state = 0;
1629
1630 spin_lock_irqsave(&priv->lock, flags);
1631 if (phydev->link) {
1632 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 1633 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 1634
1da177e4
LT		 1635 /* Now we make sure that we can be in full duplex mode.
1636 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 1637 if (phydev->duplex != priv->oldduplex) {
1638 new_state = 1;
1639 if (!(phydev->duplex))
1da177e4 1640 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 1641 else
1da177e4 1642 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 1643
bb40dcbb 1644 priv->oldduplex = phydev->duplex;
1da177e4
LT		 1645 }
1646
bb40dcbb
AF		 1647 if (phydev->speed != priv->oldspeed) {
1648 new_state = 1;
1649 switch (phydev->speed) {
1da177e4 1650 case 1000:
1da177e4
LT		 1651 tempval =
1652 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1da177e4
LT		 1653 break;
1654 case 100:
1655 case 10:
1da177e4
LT		 1656 tempval =
1657 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 1658
1659 /* Reduced mode distinguishes
1660 * between 10 and 100 */
1661 if (phydev->speed == SPEED_100)
1662 ecntrl |= ECNTRL_R100;
1663 else
1664 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 1665 break;
1666 default:
0bbaf069
KG		 1667 if (netif_msg_link(priv))
1668 printk(KERN_WARNING
bb40dcbb
AF		 1669 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1670 dev->name, phydev->speed);
1da177e4
LT		 1671 break;
1672 }
1673
bb40dcbb 1674 priv->oldspeed = phydev->speed;
1da177e4
LT		 1675 }
1676
bb40dcbb 1677 gfar_write(&regs->maccfg2, tempval);
7f7f5316 1678 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 1679
1da177e4 1680 if (!priv->oldlink) {
bb40dcbb 1681 new_state = 1;
1da177e4 1682 priv->oldlink = 1;
1da177e4
LT		 1683 netif_schedule(dev);
1684 }
bb40dcbb
AF		 1685 } else if (priv->oldlink) {
1686 new_state = 1;
1687 priv->oldlink = 0;
1688 priv->oldspeed = 0;
1689 priv->oldduplex = -1;
1da177e4 1690 }
1da177e4 1691
bb40dcbb
AF		 1692 if (new_state && netif_msg_link(priv))
1693 phy_print_status(phydev);
1694
1695 spin_unlock_irqrestore(&priv->lock, flags);
1696}
1da177e4
LT		 1697
1698/* Update the hash table based on the current list of multicast
1699 * addresses we subscribe to. Also, change the promiscuity of
1700 * the device based on the flags (this function is called
1701 * whenever dev->flags is changed */
1702static void gfar_set_multi(struct net_device *dev)
1703{
1704 struct dev_mc_list *mc_ptr;
1705 struct gfar_private *priv = netdev_priv(dev);
1706 struct gfar *regs = priv->regs;
1707 u32 tempval;
1708
1709 if(dev->flags & IFF_PROMISC) {
0bbaf069
KG		 1710 if (netif_msg_drv(priv))
1711 printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1712 dev->name);
1da177e4
LT		 1713 /* Set RCTRL to PROM */
1714 tempval = gfar_read(&regs->rctrl);
1715 tempval |= RCTRL_PROM;
1716 gfar_write(&regs->rctrl, tempval);
1717 } else {
1718 /* Set RCTRL to not PROM */
1719 tempval = gfar_read(&regs->rctrl);
1720 tempval &= ~(RCTRL_PROM);
1721 gfar_write(&regs->rctrl, tempval);
1722 }
1723
1724 if(dev->flags & IFF_ALLMULTI) {
1725 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 1726 gfar_write(&regs->igaddr0, 0xffffffff);
1727 gfar_write(&regs->igaddr1, 0xffffffff);
1728 gfar_write(&regs->igaddr2, 0xffffffff);
1729 gfar_write(&regs->igaddr3, 0xffffffff);
1730 gfar_write(&regs->igaddr4, 0xffffffff);
1731 gfar_write(&regs->igaddr5, 0xffffffff);
1732 gfar_write(&regs->igaddr6, 0xffffffff);
1733 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 1734 gfar_write(&regs->gaddr0, 0xffffffff);
1735 gfar_write(&regs->gaddr1, 0xffffffff);
1736 gfar_write(&regs->gaddr2, 0xffffffff);
1737 gfar_write(&regs->gaddr3, 0xffffffff);
1738 gfar_write(&regs->gaddr4, 0xffffffff);
1739 gfar_write(&regs->gaddr5, 0xffffffff);
1740 gfar_write(&regs->gaddr6, 0xffffffff);
1741 gfar_write(&regs->gaddr7, 0xffffffff);
1742 } else {
7f7f5316
AF		 1743 int em_num;
1744 int idx;
1745
1da177e4 1746 /* zero out the hash */
0bbaf069
KG		 1747 gfar_write(&regs->igaddr0, 0x0);
1748 gfar_write(&regs->igaddr1, 0x0);
1749 gfar_write(&regs->igaddr2, 0x0);
1750 gfar_write(&regs->igaddr3, 0x0);
1751 gfar_write(&regs->igaddr4, 0x0);
1752 gfar_write(&regs->igaddr5, 0x0);
1753 gfar_write(&regs->igaddr6, 0x0);
1754 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 1755 gfar_write(&regs->gaddr0, 0x0);
1756 gfar_write(&regs->gaddr1, 0x0);
1757 gfar_write(&regs->gaddr2, 0x0);
1758 gfar_write(&regs->gaddr3, 0x0);
1759 gfar_write(&regs->gaddr4, 0x0);
1760 gfar_write(&regs->gaddr5, 0x0);
1761 gfar_write(&regs->gaddr6, 0x0);
1762 gfar_write(&regs->gaddr7, 0x0);
1763
7f7f5316
AF		 1764 /* If we have extended hash tables, we need to
1765 * clear the exact match registers to prepare for
1766 * setting them */
1767 if (priv->extended_hash) {
1768 em_num = GFAR_EM_NUM + 1;
1769 gfar_clear_exact_match(dev);
1770 idx = 1;
1771 } else {
1772 idx = 0;
1773 em_num = 0;
1774 }
1775
1da177e4
LT		 1776 if(dev->mc_count == 0)
1777 return;
1778
1779 /* Parse the list, and set the appropriate bits */
1780 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
7f7f5316
AF		 1781 if (idx < em_num) {
1782 gfar_set_mac_for_addr(dev, idx,
1783 mc_ptr->dmi_addr);
1784 idx++;
1785 } else
1786 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1da177e4
LT		 1787 }
1788 }
1789
1790 return;
1791}
1792
7f7f5316
AF		 1793
1794/* Clears each of the exact match registers to zero, so they
1795 * don't interfere with normal reception */
1796static void gfar_clear_exact_match(struct net_device *dev)
1797{
1798 int idx;
1799 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1800
1801 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1802 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1803}
1804
1da177e4
LT		 1805/* Set the appropriate hash bit for the given addr */
1806/* The algorithm works like so:
1807 * 1) Take the Destination Address (ie the multicast address), and
1808 * do a CRC on it (little endian), and reverse the bits of the
1809 * result.
1810 * 2) Use the 8 most significant bits as a hash into a 256-entry
1811 * table. The table is controlled through 8 32-bit registers:
1812 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1813 * gaddr7. This means that the 3 most significant bits in the
1814 * hash index which gaddr register to use, and the 5 other bits
1815 * indicate which bit (assuming an IBM numbering scheme, which
1816 * for PowerPC (tm) is usually the case) in the register holds
1817 * the entry. */
1818static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1819{
1820 u32 tempval;
1821 struct gfar_private *priv = netdev_priv(dev);
1da177e4 1822 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 1823 int width = priv->hash_width;
1824 u8 whichbit = (result >> (32 - width)) & 0x1f;
1825 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 1826 u32 value = (1 << (31-whichbit));
1827
0bbaf069 1828 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 1829 tempval |= value;
0bbaf069 1830 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 1831
1832 return;
1833}
1834
7f7f5316
AF		 1835
1836/* There are multiple MAC Address register pairs on some controllers
1837 * This function sets the numth pair to a given address
1838 */
1839static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1840{
1841 struct gfar_private *priv = netdev_priv(dev);
1842 int idx;
1843 char tmpbuf[MAC_ADDR_LEN];
1844 u32 tempval;
1845 u32 *macptr = &priv->regs->macstnaddr1;
1846
1847 macptr += num*2;
1848
1849 /* Now copy it into the mac registers backwards, cuz */
1850 /* little endian is silly */
1851 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1852 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1853
1854 gfar_write(macptr, *((u32 *) (tmpbuf)));
1855
1856 tempval = *((u32 *) (tmpbuf + 4));
1857
1858 gfar_write(macptr+1, tempval);
1859}
1860
1da177e4
LT		 1861/* GFAR error interrupt handler */
1862static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1863{
1864 struct net_device *dev = dev_id;
1865 struct gfar_private *priv = netdev_priv(dev);
1866
1867 /* Save ievent for future reference */
1868 u32 events = gfar_read(&priv->regs->ievent);
1869
1870 /* Clear IEVENT */
1871 gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1872
1873 /* Hmm... */
0bbaf069
KG		 1874 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1875 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1876 dev->name, events, gfar_read(&priv->regs->imask));
1da177e4
LT		 1877
1878 /* Update the error counters */
1879 if (events & IEVENT_TXE) {
1880 priv->stats.tx_errors++;
1881
1882 if (events & IEVENT_LC)
1883 priv->stats.tx_window_errors++;
1884 if (events & IEVENT_CRL)
1885 priv->stats.tx_aborted_errors++;
1886 if (events & IEVENT_XFUN) {
0bbaf069
KG		 1887 if (netif_msg_tx_err(priv))
1888 printk(KERN_DEBUG "%s: underrun. packet dropped.\n",
1889 dev->name);
1da177e4
LT		 1890 priv->stats.tx_dropped++;
1891 priv->extra_stats.tx_underrun++;
1892
1893 /* Reactivate the Tx Queues */
1894 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1895 }
0bbaf069
KG		 1896 if (netif_msg_tx_err(priv))
1897 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 1898 }
1899 if (events & IEVENT_BSY) {
1900 priv->stats.rx_errors++;
1901 priv->extra_stats.rx_bsy++;
1902
1903 gfar_receive(irq, dev_id, regs);
1904
1905#ifndef CONFIG_GFAR_NAPI
1906 /* Clear the halt bit in RSTAT */
1907 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1908#endif
1909
0bbaf069
KG		 1910 if (netif_msg_rx_err(priv))
1911 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1912 dev->name,
1913 gfar_read(&priv->regs->rstat));
1da177e4
LT		 1914 }
1915 if (events & IEVENT_BABR) {
1916 priv->stats.rx_errors++;
1917 priv->extra_stats.rx_babr++;
1918
0bbaf069
KG		 1919 if (netif_msg_rx_err(priv))
1920 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1da177e4
LT		 1921 }
1922 if (events & IEVENT_EBERR) {
1923 priv->extra_stats.eberr++;
0bbaf069
KG		 1924 if (netif_msg_rx_err(priv))
1925 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1da177e4 1926 }
0bbaf069
KG		 1927 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1928 if (netif_msg_rx_status(priv))
1929 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 1930
1931 if (events & IEVENT_BABT) {
1932 priv->extra_stats.tx_babt++;
0bbaf069
KG		 1933 if (netif_msg_tx_err(priv))
1934 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1da177e4
LT		 1935 }
1936 return IRQ_HANDLED;
1937}
1938
1939/* Structure for a device driver */
3ae5eaec 1940static struct platform_driver gfar_driver = {
1da177e4
LT		 1941 .probe = gfar_probe,
1942 .remove = gfar_remove,
3ae5eaec
RK		 1943 .driver = {
1944 .name = "fsl-gianfar",
1945 },
1da177e4
LT		 1946};
1947
1948static int __init gfar_init(void)
1949{
bb40dcbb
AF		 1950 int err = gfar_mdio_init();
1951
1952 if (err)
1953 return err;
1954
3ae5eaec 1955 err = platform_driver_register(&gfar_driver);
bb40dcbb
AF		 1956
1957 if (err)
1958 gfar_mdio_exit();
1959
1960 return err;
1da177e4
LT		 1961}
1962
1963static void __exit gfar_exit(void)
1964{
3ae5eaec 1965 platform_driver_unregister(&gfar_driver);
bb40dcbb 1966 gfar_mdio_exit();
1da177e4
LT		 1967}
1968
1969module_init(gfar_init);
1970module_exit(gfar_exit);
1971
Linux kernel - Deliverables
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