Commit | Line | Data |
---|---|---|
6aa20a22 | 1 | /* |
bb40dcbb AF |
2 | * drivers/net/gianfar_mii.c |
3 | * | |
4 | * Gianfar Ethernet Driver -- MIIM bus implementation | |
5 | * Provides Bus interface for MIIM regs | |
6 | * | |
7 | * Author: Andy Fleming | |
4c8d3d99 | 8 | * Maintainer: Kumar Gala |
bb40dcbb AF |
9 | * |
10 | * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | * | |
17 | */ | |
18 | ||
bb40dcbb | 19 | #include <linux/kernel.h> |
bb40dcbb AF |
20 | #include <linux/string.h> |
21 | #include <linux/errno.h> | |
22 | #include <linux/unistd.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/skbuff.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
bb40dcbb AF |
34 | #include <linux/crc32.h> |
35 | #include <linux/mii.h> | |
36 | #include <linux/phy.h> | |
b31a1d8b AF |
37 | #include <linux/of.h> |
38 | #include <linux/of_platform.h> | |
bb40dcbb AF |
39 | |
40 | #include <asm/io.h> | |
41 | #include <asm/irq.h> | |
42 | #include <asm/uaccess.h> | |
43 | ||
44 | #include "gianfar.h" | |
45 | #include "gianfar_mii.h" | |
46 | ||
d3c12873 KJ |
47 | /* |
48 | * Write value to the PHY at mii_id at register regnum, | |
49 | * on the bus attached to the local interface, which may be different from the | |
50 | * generic mdio bus (tied to a single interface), waiting until the write is | |
51 | * done before returning. This is helpful in programming interfaces like | |
52 | * the TBI which control interfaces like onchip SERDES and are always tied to | |
53 | * the local mdio pins, which may not be the same as system mdio bus, used for | |
54 | * controlling the external PHYs, for example. | |
55 | */ | |
fdb26629 | 56 | int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id, |
d3c12873 | 57 | int regnum, u16 value) |
bb40dcbb | 58 | { |
bb40dcbb AF |
59 | /* Set the PHY address and the register address we want to write */ |
60 | gfar_write(®s->miimadd, (mii_id << 8) | regnum); | |
61 | ||
62 | /* Write out the value we want */ | |
63 | gfar_write(®s->miimcon, value); | |
64 | ||
65 | /* Wait for the transaction to finish */ | |
66 | while (gfar_read(®s->miimind) & MIIMIND_BUSY) | |
67 | cpu_relax(); | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
d3c12873 KJ |
72 | /* |
73 | * Read the bus for PHY at addr mii_id, register regnum, and | |
74 | * return the value. Clears miimcom first. All PHY operation | |
75 | * done on the bus attached to the local interface, | |
76 | * which may be different from the generic mdio bus | |
77 | * This is helpful in programming interfaces like | |
78 | * the TBI which, inturn, control interfaces like onchip SERDES | |
79 | * and are always tied to the local mdio pins, which may not be the | |
80 | * same as system mdio bus, used for controlling the external PHYs, for eg. | |
81 | */ | |
fdb26629 | 82 | int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum) |
bb40dcbb | 83 | { |
bb40dcbb AF |
84 | u16 value; |
85 | ||
86 | /* Set the PHY address and the register address we want to read */ | |
87 | gfar_write(®s->miimadd, (mii_id << 8) | regnum); | |
88 | ||
89 | /* Clear miimcom, and then initiate a read */ | |
90 | gfar_write(®s->miimcom, 0); | |
91 | gfar_write(®s->miimcom, MII_READ_COMMAND); | |
92 | ||
93 | /* Wait for the transaction to finish */ | |
94 | while (gfar_read(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)) | |
95 | cpu_relax(); | |
96 | ||
97 | /* Grab the value of the register from miimstat */ | |
98 | value = gfar_read(®s->miimstat); | |
99 | ||
100 | return value; | |
101 | } | |
102 | ||
d3c12873 KJ |
103 | /* Write value to the PHY at mii_id at register regnum, |
104 | * on the bus, waiting until the write is done before returning. | |
105 | * All PHY configuration is done through the TSEC1 MIIM regs */ | |
106 | int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) | |
107 | { | |
b2f66d18 | 108 | struct gfar_mii __iomem *regs = (void __force __iomem *)bus->priv; |
d3c12873 KJ |
109 | |
110 | /* Write to the local MII regs */ | |
111 | return(gfar_local_mdio_write(regs, mii_id, regnum, value)); | |
112 | } | |
113 | ||
114 | /* Read the bus for PHY at addr mii_id, register regnum, and | |
115 | * return the value. Clears miimcom first. All PHY | |
116 | * configuration has to be done through the TSEC1 MIIM regs */ | |
117 | int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | |
118 | { | |
b2f66d18 | 119 | struct gfar_mii __iomem *regs = (void __force __iomem *)bus->priv; |
d3c12873 KJ |
120 | |
121 | /* Read the local MII regs */ | |
122 | return(gfar_local_mdio_read(regs, mii_id, regnum)); | |
123 | } | |
bb40dcbb AF |
124 | |
125 | /* Reset the MIIM registers, and wait for the bus to free */ | |
d0313587 | 126 | static int gfar_mdio_reset(struct mii_bus *bus) |
bb40dcbb | 127 | { |
b2f66d18 | 128 | struct gfar_mii __iomem *regs = (void __force __iomem *)bus->priv; |
bb40dcbb AF |
129 | unsigned int timeout = PHY_INIT_TIMEOUT; |
130 | ||
15cf6dde | 131 | mutex_lock(&bus->mdio_lock); |
bb40dcbb AF |
132 | |
133 | /* Reset the management interface */ | |
134 | gfar_write(®s->miimcfg, MIIMCFG_RESET); | |
135 | ||
136 | /* Setup the MII Mgmt clock speed */ | |
137 | gfar_write(®s->miimcfg, MIIMCFG_INIT_VALUE); | |
138 | ||
139 | /* Wait until the bus is free */ | |
140 | while ((gfar_read(®s->miimind) & MIIMIND_BUSY) && | |
baac03d9 | 141 | --timeout) |
bb40dcbb AF |
142 | cpu_relax(); |
143 | ||
15cf6dde | 144 | mutex_unlock(&bus->mdio_lock); |
bb40dcbb | 145 | |
baac03d9 | 146 | if(timeout == 0) { |
bb40dcbb AF |
147 | printk(KERN_ERR "%s: The MII Bus is stuck!\n", |
148 | bus->name); | |
149 | return -EBUSY; | |
150 | } | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
b31a1d8b AF |
155 | /* Allocate an array which provides irq #s for each PHY on the given bus */ |
156 | static int *create_irq_map(struct device_node *np) | |
157 | { | |
158 | int *irqs; | |
159 | int i; | |
160 | struct device_node *child = NULL; | |
161 | ||
162 | irqs = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); | |
163 | ||
164 | if (!irqs) | |
165 | return NULL; | |
166 | ||
167 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
168 | irqs[i] = PHY_POLL; | |
169 | ||
170 | while ((child = of_get_next_child(np, child)) != NULL) { | |
171 | int irq = irq_of_parse_and_map(child, 0); | |
172 | const u32 *id; | |
173 | ||
174 | if (irq == NO_IRQ) | |
175 | continue; | |
176 | ||
177 | id = of_get_property(child, "reg", NULL); | |
178 | ||
179 | if (!id) | |
180 | continue; | |
181 | ||
182 | if (*id < PHY_MAX_ADDR && *id >= 0) | |
183 | irqs[*id] = irq; | |
184 | else | |
185 | printk(KERN_WARNING "%s: " | |
186 | "%d is not a valid PHY address\n", | |
187 | np->full_name, *id); | |
188 | } | |
189 | ||
190 | return irqs; | |
191 | } | |
192 | ||
193 | ||
194 | void gfar_mdio_bus_name(char *name, struct device_node *np) | |
195 | { | |
196 | const u32 *reg; | |
197 | ||
198 | reg = of_get_property(np, "reg", NULL); | |
bb40dcbb | 199 | |
b31a1d8b AF |
200 | snprintf(name, MII_BUS_ID_SIZE, "%s@%x", np->name, reg ? *reg : 0); |
201 | } | |
202 | ||
203 | /* Scan the bus in reverse, looking for an empty spot */ | |
204 | static int gfar_mdio_find_free(struct mii_bus *new_bus) | |
205 | { | |
206 | int i; | |
207 | ||
208 | for (i = PHY_MAX_ADDR; i > 0; i--) { | |
209 | u32 phy_id; | |
210 | ||
211 | if (get_phy_id(new_bus, i, &phy_id)) | |
212 | return -1; | |
213 | ||
214 | if (phy_id == 0xffffffff) | |
215 | break; | |
216 | } | |
217 | ||
218 | return i; | |
219 | } | |
220 | ||
221 | static int gfar_mdio_probe(struct of_device *ofdev, | |
222 | const struct of_device_id *match) | |
bb40dcbb | 223 | { |
cc8c6e37 | 224 | struct gfar_mii __iomem *regs; |
d0313587 | 225 | struct gfar __iomem *enet_regs; |
bb40dcbb | 226 | struct mii_bus *new_bus; |
b31a1d8b AF |
227 | int err = 0; |
228 | u64 addr, size; | |
229 | struct device_node *np = ofdev->node; | |
230 | struct device_node *tbi; | |
231 | int tbiaddr = -1; | |
bb40dcbb | 232 | |
298cf9be | 233 | new_bus = mdiobus_alloc(); |
bb40dcbb AF |
234 | if (NULL == new_bus) |
235 | return -ENOMEM; | |
236 | ||
e5664bb2 AV |
237 | device_init_wakeup(&ofdev->dev, 1); |
238 | ||
bb40dcbb AF |
239 | new_bus->name = "Gianfar MII Bus", |
240 | new_bus->read = &gfar_mdio_read, | |
241 | new_bus->write = &gfar_mdio_write, | |
242 | new_bus->reset = &gfar_mdio_reset, | |
b31a1d8b | 243 | gfar_mdio_bus_name(new_bus->id, np); |
1d532677 | 244 | |
bb40dcbb | 245 | /* Set the PHY base address */ |
b31a1d8b AF |
246 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); |
247 | regs = ioremap(addr, size); | |
bb40dcbb AF |
248 | |
249 | if (NULL == regs) { | |
250 | err = -ENOMEM; | |
b31a1d8b | 251 | goto err_free_bus; |
bb40dcbb AF |
252 | } |
253 | ||
cc8c6e37 | 254 | new_bus->priv = (void __force *)regs; |
bb40dcbb | 255 | |
b31a1d8b AF |
256 | new_bus->irq = create_irq_map(np); |
257 | ||
258 | if (new_bus->irq == NULL) { | |
259 | err = -ENOMEM; | |
260 | goto err_unmap_regs; | |
261 | } | |
bb40dcbb | 262 | |
b31a1d8b AF |
263 | new_bus->parent = &ofdev->dev; |
264 | dev_set_drvdata(&ofdev->dev, new_bus); | |
bb40dcbb | 265 | |
d0313587 PG |
266 | /* |
267 | * This is mildly evil, but so is our hardware for doing this. | |
268 | * Also, we have to cast back to struct gfar_mii because of | |
269 | * definition weirdness done in gianfar.h. | |
270 | */ | |
b2f66d18 AV |
271 | enet_regs = (struct gfar __force __iomem *) |
272 | ((char __force *)regs - offsetof(struct gfar, gfar_mii_regs)); | |
d0313587 | 273 | |
b31a1d8b AF |
274 | for_each_child_of_node(np, tbi) { |
275 | if (!strncmp(tbi->type, "tbi-phy", 8)) | |
276 | break; | |
277 | } | |
d0313587 | 278 | |
b31a1d8b AF |
279 | if (tbi) { |
280 | const u32 *prop = of_get_property(tbi, "reg", NULL); | |
d0313587 | 281 | |
b31a1d8b AF |
282 | if (prop) |
283 | tbiaddr = *prop; | |
d0313587 PG |
284 | } |
285 | ||
b31a1d8b AF |
286 | if (tbiaddr == -1) { |
287 | gfar_write(&enet_regs->tbipa, 0); | |
288 | ||
289 | tbiaddr = gfar_mdio_find_free(new_bus); | |
290 | } | |
291 | ||
292 | /* | |
293 | * We define TBIPA at 0 to be illegal, opting to fail for boards that | |
294 | * have PHYs at 1-31, rather than change tbipa and rescan. | |
295 | */ | |
296 | if (tbiaddr == 0) { | |
ac7198bb AF |
297 | err = -EBUSY; |
298 | ||
b31a1d8b | 299 | goto err_free_irqs; |
ac7198bb | 300 | } |
d0313587 | 301 | |
b31a1d8b AF |
302 | gfar_write(&enet_regs->tbipa, tbiaddr); |
303 | ||
304 | /* | |
305 | * The TBIPHY-only buses will find PHYs at every address, | |
306 | * so we mask them all but the TBI | |
307 | */ | |
308 | if (!of_device_is_compatible(np, "fsl,gianfar-mdio")) | |
309 | new_bus->phy_mask = ~(1 << tbiaddr); | |
d0313587 | 310 | |
bb40dcbb AF |
311 | err = mdiobus_register(new_bus); |
312 | ||
b31a1d8b | 313 | if (err != 0) { |
6aa20a22 | 314 | printk (KERN_ERR "%s: Cannot register as MDIO bus\n", |
bb40dcbb | 315 | new_bus->name); |
b31a1d8b | 316 | goto err_free_irqs; |
bb40dcbb AF |
317 | } |
318 | ||
319 | return 0; | |
320 | ||
b31a1d8b AF |
321 | err_free_irqs: |
322 | kfree(new_bus->irq); | |
323 | err_unmap_regs: | |
cc8c6e37 | 324 | iounmap(regs); |
b31a1d8b | 325 | err_free_bus: |
298cf9be | 326 | mdiobus_free(new_bus); |
bb40dcbb AF |
327 | |
328 | return err; | |
329 | } | |
330 | ||
331 | ||
b31a1d8b | 332 | static int gfar_mdio_remove(struct of_device *ofdev) |
bb40dcbb | 333 | { |
b31a1d8b | 334 | struct mii_bus *bus = dev_get_drvdata(&ofdev->dev); |
bb40dcbb AF |
335 | |
336 | mdiobus_unregister(bus); | |
337 | ||
b31a1d8b | 338 | dev_set_drvdata(&ofdev->dev, NULL); |
bb40dcbb | 339 | |
b2f66d18 | 340 | iounmap((void __force __iomem *)bus->priv); |
bb40dcbb | 341 | bus->priv = NULL; |
b31a1d8b | 342 | kfree(bus->irq); |
298cf9be | 343 | mdiobus_free(bus); |
bb40dcbb AF |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
b31a1d8b AF |
348 | static struct of_device_id gfar_mdio_match[] = |
349 | { | |
350 | { | |
351 | .compatible = "fsl,gianfar-mdio", | |
352 | }, | |
353 | { | |
354 | .compatible = "fsl,gianfar-tbi", | |
355 | }, | |
356 | { | |
357 | .type = "mdio", | |
358 | .compatible = "gianfar", | |
359 | }, | |
360 | {}, | |
361 | }; | |
362 | ||
363 | static struct of_platform_driver gianfar_mdio_driver = { | |
bb40dcbb | 364 | .name = "fsl-gianfar_mdio", |
b31a1d8b AF |
365 | .match_table = gfar_mdio_match, |
366 | ||
bb40dcbb AF |
367 | .probe = gfar_mdio_probe, |
368 | .remove = gfar_mdio_remove, | |
369 | }; | |
370 | ||
371 | int __init gfar_mdio_init(void) | |
372 | { | |
b31a1d8b | 373 | return of_register_platform_driver(&gianfar_mdio_driver); |
bb40dcbb AF |
374 | } |
375 | ||
b9daf6c0 | 376 | void gfar_mdio_exit(void) |
bb40dcbb | 377 | { |
b31a1d8b | 378 | of_unregister_platform_driver(&gianfar_mdio_driver); |
bb40dcbb | 379 | } |