[deliverable/linux.git] / drivers / net / ibm_newemac / core.h

/*
 * drivers/net/ibm_newemac/core.h
 *
 * Driver for PowerPC 4xx on-chip ethernet controller.
 *
 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
 *                <benh@kernel.crashing.org>
 *
 * Based on the arch/ppc version of the driver:
 *
 * Copyright (c) 2004, 2005 Zultys Technologies.
 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
 *
 * Based on original work by
 *      Armin Kuster <akuster@mvista.com>
 * 	Johnnie Peters <jpeters@mvista.com>
 *      Copyright 2000, 2001 MontaVista Softare Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#ifndef __IBM_NEWEMAC_CORE_H
#define __IBM_NEWEMAC_CORE_H

#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/dma-mapping.h>
#include <linux/spinlock.h>
#include <linux/of_platform.h>

#include <asm/io.h>
#include <asm/dcr.h>

#include "emac.h"
#include "phy.h"
#include "zmii.h"
#include "rgmii.h"
#include "mal.h"
#include "tah.h"
#include "debug.h"

#define NUM_TX_BUFF			CONFIG_IBM_NEW_EMAC_TXB
#define NUM_RX_BUFF			CONFIG_IBM_NEW_EMAC_RXB

/* Simple sanity check */
#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
#error Invalid number of buffer descriptors (greater than 256)
#endif

#define EMAC_MIN_MTU			46

/* Maximum L2 header length (VLAN tagged, no FCS) */
#define EMAC_MTU_OVERHEAD		(6 * 2 + 2 + 4)

/* RX BD size for the given MTU */
static inline int emac_rx_size(int mtu)
{
	if (mtu > ETH_DATA_LEN)
		return MAL_MAX_RX_SIZE;
	else
		return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
}

#define EMAC_DMA_ALIGN(x)		ALIGN((x), dma_get_cache_alignment())

#define EMAC_RX_SKB_HEADROOM		\
	EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM)

/* Size of RX skb for the given MTU */
static inline int emac_rx_skb_size(int mtu)
{
	int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
	return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
}

/* RX DMA sync size */
static inline int emac_rx_sync_size(int mtu)
{
	return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
}

/* Driver statistcs is split into two parts to make it more cache friendly:
 *   - normal statistics (packet count, etc)
 *   - error statistics
 *
 * When statistics is requested by ethtool, these parts are concatenated,
 * normal one goes first.
 *
 * Please, keep these structures in sync with emac_stats_keys.
 */

/* Normal TX/RX Statistics */
struct emac_stats {
	u64 rx_packets;
	u64 rx_bytes;
	u64 tx_packets;
	u64 tx_bytes;
	u64 rx_packets_csum;
	u64 tx_packets_csum;
};

/* Error statistics */
struct emac_error_stats {
	u64 tx_undo;

	/* Software RX Errors */
	u64 rx_dropped_stack;
	u64 rx_dropped_oom;
	u64 rx_dropped_error;
	u64 rx_dropped_resize;
	u64 rx_dropped_mtu;
	u64 rx_stopped;
	/* BD reported RX errors */
	u64 rx_bd_errors;
	u64 rx_bd_overrun;
	u64 rx_bd_bad_packet;
	u64 rx_bd_runt_packet;
	u64 rx_bd_short_event;
	u64 rx_bd_alignment_error;
	u64 rx_bd_bad_fcs;
	u64 rx_bd_packet_too_long;
	u64 rx_bd_out_of_range;
	u64 rx_bd_in_range;
	/* EMAC IRQ reported RX errors */
	u64 rx_parity;
	u64 rx_fifo_overrun;
	u64 rx_overrun;
	u64 rx_bad_packet;
	u64 rx_runt_packet;
	u64 rx_short_event;
	u64 rx_alignment_error;
	u64 rx_bad_fcs;
	u64 rx_packet_too_long;
	u64 rx_out_of_range;
	u64 rx_in_range;

	/* Software TX Errors */
	u64 tx_dropped;
	/* BD reported TX errors */
	u64 tx_bd_errors;
	u64 tx_bd_bad_fcs;
	u64 tx_bd_carrier_loss;
	u64 tx_bd_excessive_deferral;
	u64 tx_bd_excessive_collisions;
	u64 tx_bd_late_collision;
	u64 tx_bd_multple_collisions;
	u64 tx_bd_single_collision;
	u64 tx_bd_underrun;
	u64 tx_bd_sqe;
	/* EMAC IRQ reported TX errors */
	u64 tx_parity;
	u64 tx_underrun;
	u64 tx_sqe;
	u64 tx_errors;
};

#define EMAC_ETHTOOL_STATS_COUNT	((sizeof(struct emac_stats) + \
					  sizeof(struct emac_error_stats)) \
					 / sizeof(u64))

struct emac_instance {
	struct net_device		*ndev;
	struct resource			rsrc_regs;
	struct emac_regs		__iomem *emacp;
	struct of_device		*ofdev;
	struct device_node		**blist; /* bootlist entry */

	/* MAL linkage */
	u32				mal_ph;
	struct of_device		*mal_dev;
	u32				mal_rx_chan;
	u32				mal_tx_chan;
	struct mal_instance		*mal;
	struct mal_commac		commac;

	/* PHY infos */
	u32				phy_mode;
	u32				phy_map;
	u32				phy_address;
	u32				phy_feat_exc;
	struct mii_phy			phy;
	struct mutex			link_lock;
	struct delayed_work		link_work;
	int				link_polling;

	/* Shared MDIO if any */
	u32				mdio_ph;
	struct of_device		*mdio_dev;
	struct emac_instance		*mdio_instance;
	struct mutex			mdio_lock;

	/* ZMII infos if any */
	u32				zmii_ph;
	u32				zmii_port;
	struct of_device		*zmii_dev;

	/* RGMII infos if any */
	u32				rgmii_ph;
	u32				rgmii_port;
	struct of_device		*rgmii_dev;

	/* TAH infos if any */
	u32				tah_ph;
	u32				tah_port;
	struct of_device		*tah_dev;

	/* IRQs */
	int				wol_irq;
	int				emac_irq;

	/* OPB bus frequency in Mhz */
	u32				opb_bus_freq;

	/* Cell index within an ASIC (for clk mgmnt) */
	u32				cell_index;

	/* Max supported MTU */
	u32				max_mtu;

	/* Feature bits (from probe table) */
	unsigned int			features;

	/* Tx and Rx fifo sizes & other infos in bytes */
	u32				tx_fifo_size;
	u32				tx_fifo_size_gige;
	u32				rx_fifo_size;
	u32				rx_fifo_size_gige;
	u32				fifo_entry_size;
	u32				mal_burst_size; /* move to MAL ? */

	/* IAHT and GAHT filter parameterization */
	u32				xaht_slots_shift;
	u32				xaht_width_shift;

	/* Descriptor management
	 */
	struct mal_descriptor		*tx_desc;
	int				tx_cnt;
	int				tx_slot;
	int				ack_slot;

	struct mal_descriptor		*rx_desc;
	int				rx_slot;
	struct sk_buff			*rx_sg_skb;	/* 1 */
	int 				rx_skb_size;
	int				rx_sync_size;

	struct sk_buff			*tx_skb[NUM_TX_BUFF];
	struct sk_buff			*rx_skb[NUM_RX_BUFF];

	/* Stats
	 */
	struct emac_error_stats		estats;
	struct net_device_stats		nstats;
	struct emac_stats 		stats;

	/* Misc
	 */
	int				reset_failed;
	int				stop_timeout;	/* in us */
	int				no_mcast;
	int				mcast_pending;
	int				opened;
	struct work_struct		reset_work;
	spinlock_t			lock;
};

/*
 * Features of various EMAC implementations
 */

/*
 * No flow control on 40x according to the original driver
 */
#define EMAC_FTR_NO_FLOW_CONTROL_40x	0x00000001
/*
 * Cell is an EMAC4
 */
#define EMAC_FTR_EMAC4			0x00000002
/*
 * For the 440SPe, AMCC inexplicably changed the polarity of
 * the "operation complete" bit in the MII control register.
 */
#define EMAC_FTR_STACR_OC_INVERT	0x00000004
/*
 * Set if we have a TAH.
 */
#define EMAC_FTR_HAS_TAH		0x00000008
/*
 * Set if we have a ZMII.
 */
#define EMAC_FTR_HAS_ZMII		0x00000010
/*
 * Set if we have a RGMII.
 */
#define EMAC_FTR_HAS_RGMII		0x00000020
/*
 * Set if we have new type STACR with STAOPC
 */
#define EMAC_FTR_HAS_NEW_STACR		0x00000040
/*
 * Set if we need phy clock workaround for 440gx
 */
#define EMAC_FTR_440GX_PHY_CLK_FIX	0x00000080
/*
 * Set if we need phy clock workaround for 440ep or 440gr
 */
#define EMAC_FTR_440EP_PHY_CLK_FIX	0x00000100
/*
 * The 405EX and 460EX contain the EMAC4SYNC core
 */
#define EMAC_FTR_EMAC4SYNC		0x00000200


/* Right now, we don't quite handle the always/possible masks on the
 * most optimal way as we don't have a way to say something like
 * always EMAC4. Patches welcome.
 */
enum {
	EMAC_FTRS_ALWAYS	= 0,

	EMAC_FTRS_POSSIBLE	=
#ifdef CONFIG_IBM_NEW_EMAC_EMAC4
	    EMAC_FTR_EMAC4	| EMAC_FTR_EMAC4SYNC	|
	    EMAC_FTR_HAS_NEW_STACR	|
	    EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
#endif
#ifdef CONFIG_IBM_NEW_EMAC_TAH
	    EMAC_FTR_HAS_TAH	|
#endif
#ifdef CONFIG_IBM_NEW_EMAC_ZMII
	    EMAC_FTR_HAS_ZMII	|
#endif
#ifdef CONFIG_IBM_NEW_EMAC_RGMII
	    EMAC_FTR_HAS_RGMII	|
#endif
	EMAC_FTR_440EP_PHY_CLK_FIX,
};

static inline int emac_has_feature(struct emac_instance *dev,
				   unsigned long feature)
{
	return (EMAC_FTRS_ALWAYS & feature) ||
	       (EMAC_FTRS_POSSIBLE & dev->features & feature);
}

/*
 * Various instances of the EMAC core have varying 1) number of
 * address match slots, 2) width of the registers for handling address
 * match slots, 3) number of registers for handling address match
 * slots and 4) base offset for those registers.
 *
 * These macros and inlines handle these differences based on
 * parameters supplied by the device structure which are, in turn,
 * initialized based on the "compatible" entry in the device tree.
 */

#define	EMAC4_XAHT_SLOTS_SHIFT		6
#define	EMAC4_XAHT_WIDTH_SHIFT		4

#define	EMAC4SYNC_XAHT_SLOTS_SHIFT	8
#define	EMAC4SYNC_XAHT_WIDTH_SHIFT	5

#define	EMAC_XAHT_SLOTS(dev)         	(1 << (dev)->xaht_slots_shift)
#define	EMAC_XAHT_WIDTH(dev)         	(1 << (dev)->xaht_width_shift)
#define	EMAC_XAHT_REGS(dev)          	(1 << ((dev)->xaht_slots_shift - \
					       (dev)->xaht_width_shift))

#define	EMAC_XAHT_CRC_TO_SLOT(dev, crc)			\
	((EMAC_XAHT_SLOTS(dev) - 1) -			\
	 ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) -	\
		    (dev)->xaht_slots_shift)))

#define	EMAC_XAHT_SLOT_TO_REG(dev, slot)		\
	((slot) >> (dev)->xaht_width_shift)

#define	EMAC_XAHT_SLOT_TO_MASK(dev, slot)		\
	((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >>	\
	 ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))

static inline u32 *emac_xaht_base(struct emac_instance *dev)
{
	struct emac_regs __iomem *p = dev->emacp;
	int offset;

	/* The first IAHT entry always is the base of the block of
	 * IAHT and GAHT registers.
	 */
	if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
		offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
	else
		offset = offsetof(struct emac_regs, u0.emac4.iaht1);

	return ((u32 *)((ptrdiff_t)p + offset));
}

static inline u32 *emac_gaht_base(struct emac_instance *dev)
{
	/* GAHT registers always come after an identical number of
	 * IAHT registers.
	 */
	return (emac_xaht_base(dev) + EMAC_XAHT_REGS(dev));
}

static inline u32 *emac_iaht_base(struct emac_instance *dev)
{
	/* IAHT registers always come before an identical number of
	 * GAHT registers.
	 */
	return (emac_xaht_base(dev));
}

/* Ethtool get_regs complex data.
 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
 * when available.
 *
 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
 * Each register component is preceded with emac_ethtool_regs_subhdr.
 * Order of the optional headers follows their relative bit posititions
 * in emac_ethtool_regs_hdr.components
 */
#define EMAC_ETHTOOL_REGS_ZMII		0x00000001
#define EMAC_ETHTOOL_REGS_RGMII		0x00000002
#define EMAC_ETHTOOL_REGS_TAH		0x00000004

struct emac_ethtool_regs_hdr {
	u32 components;
};

struct emac_ethtool_regs_subhdr {
	u32 version;
	u32 index;
};

#define EMAC_ETHTOOL_REGS_VER		0
#define EMAC_ETHTOOL_REGS_SIZE(dev) 	((dev)->rsrc_regs.end - \
					 (dev)->rsrc_regs.start + 1)
#define EMAC4_ETHTOOL_REGS_VER      	1
#define EMAC4_ETHTOOL_REGS_SIZE(dev)	((dev)->rsrc_regs.end -	\
					 (dev)->rsrc_regs.start + 1)

#endif /* __IBM_NEWEMAC_CORE_H */
Commit	Line	Data
1d3bb996 DG	1	/*
	2	* drivers/net/ibm_newemac/core.h
	3	*
	4	* Driver for PowerPC 4xx on-chip ethernet controller.
	5	*
17cf803a BH	6	* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
	7	* <benh@kernel.crashing.org>
	8	*
	9	* Based on the arch/ppc version of the driver:
	10	*
1d3bb996 DG	11	* Copyright (c) 2004, 2005 Zultys Technologies.
	12	* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
	13	*
	14	* Based on original work by
	15	* Armin Kuster <akuster@mvista.com>
	16	* Johnnie Peters <jpeters@mvista.com>
	17	* Copyright 2000, 2001 MontaVista Softare Inc.
	18	*
	19	* This program is free software; you can redistribute it and/or modify it
	20	* under the terms of the GNU General Public License as published by the
	21	* Free Software Foundation; either version 2 of the License, or (at your
	22	* option) any later version.
	23	*
	24	*/
	25	#ifndef __IBM_NEWEMAC_CORE_H
	26	#define __IBM_NEWEMAC_CORE_H
	27
	28	#include <linux/module.h>
	29	#include <linux/init.h>
	30	#include <linux/list.h>
	31	#include <linux/kernel.h>
	32	#include <linux/interrupt.h>
	33	#include <linux/netdevice.h>
	34	#include <linux/dma-mapping.h>
	35	#include <linux/spinlock.h>
55b6c8e9	36	#include <linux/of_platform.h>
1d3bb996	37
1d3bb996 DG	38	#include <asm/io.h>
	39	#include <asm/dcr.h>
	40
	41	#include "emac.h"
	42	#include "phy.h"
	43	#include "zmii.h"
	44	#include "rgmii.h"
	45	#include "mal.h"
	46	#include "tah.h"
	47	#include "debug.h"
	48
	49	#define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB
	50	#define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB
	51
	52	/* Simple sanity check */
	53	#if NUM_TX_BUFF > 256 \|\| NUM_RX_BUFF > 256
	54	#error Invalid number of buffer descriptors (greater than 256)
	55	#endif
	56
	57	#define EMAC_MIN_MTU 46
	58
	59	/* Maximum L2 header length (VLAN tagged, no FCS) */
	60	#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
	61
	62	/* RX BD size for the given MTU */
	63	static inline int emac_rx_size(int mtu)
	64	{
	65	if (mtu > ETH_DATA_LEN)
	66	return MAL_MAX_RX_SIZE;
	67	else
	68	return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
	69	}
	70
	71	#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
	72
	73	#define EMAC_RX_SKB_HEADROOM \
	74	EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM)
	75
	76	/* Size of RX skb for the given MTU */
	77	static inline int emac_rx_skb_size(int mtu)
	78	{
	79	int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
	80	return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
	81	}
	82
	83	/* RX DMA sync size */
	84	static inline int emac_rx_sync_size(int mtu)
	85	{
	86	return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
	87	}
	88
	89	/* Driver statistcs is split into two parts to make it more cache friendly:
	90	* - normal statistics (packet count, etc)
	91	* - error statistics
	92	*
	93	* When statistics is requested by ethtool, these parts are concatenated,
	94	* normal one goes first.
	95	*
	96	* Please, keep these structures in sync with emac_stats_keys.
	97	*/
	98
	99	/* Normal TX/RX Statistics */
	100	struct emac_stats {
	101	u64 rx_packets;
102	u64 rx_bytes;
103	u64 tx_packets;
104	u64 tx_bytes;
105	u64 rx_packets_csum;
106	u64 tx_packets_csum;
107	};
108
109	/* Error statistics */
110	struct emac_error_stats {
111	u64 tx_undo;
112
113	/* Software RX Errors */
114	u64 rx_dropped_stack;
115	u64 rx_dropped_oom;
116	u64 rx_dropped_error;
117	u64 rx_dropped_resize;
118	u64 rx_dropped_mtu;
119	u64 rx_stopped;
120	/* BD reported RX errors */
121	u64 rx_bd_errors;
122	u64 rx_bd_overrun;
123	u64 rx_bd_bad_packet;
124	u64 rx_bd_runt_packet;
125	u64 rx_bd_short_event;
126	u64 rx_bd_alignment_error;
127	u64 rx_bd_bad_fcs;
128	u64 rx_bd_packet_too_long;
129	u64 rx_bd_out_of_range;
130	u64 rx_bd_in_range;
131	/* EMAC IRQ reported RX errors */
132	u64 rx_parity;
133	u64 rx_fifo_overrun;
134	u64 rx_overrun;
135	u64 rx_bad_packet;
136	u64 rx_runt_packet;
137	u64 rx_short_event;
138	u64 rx_alignment_error;
139	u64 rx_bad_fcs;
140	u64 rx_packet_too_long;
141	u64 rx_out_of_range;
142	u64 rx_in_range;
143
144	/* Software TX Errors */
145	u64 tx_dropped;
146	/* BD reported TX errors */
147	u64 tx_bd_errors;
148	u64 tx_bd_bad_fcs;
149	u64 tx_bd_carrier_loss;
150	u64 tx_bd_excessive_deferral;
151	u64 tx_bd_excessive_collisions;
152	u64 tx_bd_late_collision;
153	u64 tx_bd_multple_collisions;
154	u64 tx_bd_single_collision;
155	u64 tx_bd_underrun;
156	u64 tx_bd_sqe;
157	/* EMAC IRQ reported TX errors */
158	u64 tx_parity;
159	u64 tx_underrun;
160	u64 tx_sqe;
161	u64 tx_errors;
162	};
163
164	#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \
165	sizeof(struct emac_error_stats)) \
166	/ sizeof(u64))
167
168	struct emac_instance {
169	struct net_device *ndev;
170	struct resource rsrc_regs;
171	struct emac_regs __iomem *emacp;
172	struct of_device *ofdev;
173	struct device_node *blist; / bootlist entry */
174
175	/* MAL linkage */
176	u32 mal_ph;
177	struct of_device *mal_dev;
178	u32 mal_rx_chan;
179	u32 mal_tx_chan;
180	struct mal_instance *mal;
181	struct mal_commac commac;
182
183	/* PHY infos */
184	u32 phy_mode;
185	u32 phy_map;
186	u32 phy_address;
187	u32 phy_feat_exc;
188	struct mii_phy phy;
189	struct mutex link_lock;
190	struct delayed_work link_work;
191	int link_polling;
192
193	/* Shared MDIO if any */
194	u32 mdio_ph;
195	struct of_device *mdio_dev;
196	struct emac_instance *mdio_instance;
197	struct mutex mdio_lock;
198
199	/* ZMII infos if any */
200	u32 zmii_ph;
201	u32 zmii_port;
202	struct of_device *zmii_dev;
203
204	/* RGMII infos if any */
205	u32 rgmii_ph;
206	u32 rgmii_port;
207	struct of_device *rgmii_dev;
208
209	/* TAH infos if any */
210	u32 tah_ph;
211	u32 tah_port;
212	struct of_device *tah_dev;
213
214	/* IRQs */
215	int wol_irq;
216	int emac_irq;
217
218	/* OPB bus frequency in Mhz */
219	u32 opb_bus_freq;
220
221	/* Cell index within an ASIC (for clk mgmnt) */
222	u32 cell_index;
223
224	/* Max supported MTU */
225	u32 max_mtu;
226
227	/* Feature bits (from probe table) */
228	unsigned int features;
229
230	/* Tx and Rx fifo sizes & other infos in bytes */
231	u32 tx_fifo_size;
232	u32 tx_fifo_size_gige;
233	u32 rx_fifo_size;
234	u32 rx_fifo_size_gige;
235	u32 fifo_entry_size;
236	u32 mal_burst_size; /* move to MAL ? */
237
05781ccd GE	238	/* IAHT and GAHT filter parameterization */
	239	u32 xaht_slots_shift;
	240	u32 xaht_width_shift;
	241
1d3bb996 DG	242	/* Descriptor management
	243	*/
	244	struct mal_descriptor *tx_desc;
	245	int tx_cnt;
	246	int tx_slot;
	247	int ack_slot;
	248
	249	struct mal_descriptor *rx_desc;
	250	int rx_slot;
	251	struct sk_buff rx_sg_skb; / 1 */
	252	int rx_skb_size;
	253	int rx_sync_size;
	254
	255	struct sk_buff *tx_skb[NUM_TX_BUFF];
	256	struct sk_buff *rx_skb[NUM_RX_BUFF];
	257
	258	/* Stats
	259	*/
	260	struct emac_error_stats estats;
	261	struct net_device_stats nstats;
	262	struct emac_stats stats;
	263
	264	/* Misc
	265	*/
	266	int reset_failed;
	267	int stop_timeout; /* in us */
	268	int no_mcast;
	269	int mcast_pending;
61dbcece	270	int opened;
1d3bb996 DG	271	struct work_struct reset_work;
	272	spinlock_t lock;
	273	};
	274
	275	/*
	276	* Features of various EMAC implementations
	277	*/
	278
	279	/*
	280	* No flow control on 40x according to the original driver
	281	*/
	282	#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001
	283	/*
	284	* Cell is an EMAC4
	285	*/
	286	#define EMAC_FTR_EMAC4 0x00000002
	287	/*
	288	* For the 440SPe, AMCC inexplicably changed the polarity of
	289	* the "operation complete" bit in the MII control register.
	290	*/
	291	#define EMAC_FTR_STACR_OC_INVERT 0x00000004
	292	/*
	293	* Set if we have a TAH.
	294	*/
	295	#define EMAC_FTR_HAS_TAH 0x00000008
	296	/*
	297	* Set if we have a ZMII.
	298	*/
	299	#define EMAC_FTR_HAS_ZMII 0x00000010
	300	/*
	301	* Set if we have a RGMII.
	302	*/
	303	#define EMAC_FTR_HAS_RGMII 0x00000020
	304	/*
bff713b5	305	* Set if we have new type STACR with STAOPC
1d3bb996	306	*/
bff713b5	307	#define EMAC_FTR_HAS_NEW_STACR 0x00000040
0925ab5d VB	308	/*
	309	* Set if we need phy clock workaround for 440gx
	310	*/
	311	#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
11121e30 VB	312	/*
	313	* Set if we need phy clock workaround for 440ep or 440gr
	314	*/
	315	#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100
05781ccd GE	316	/*
	317	* The 405EX and 460EX contain the EMAC4SYNC core
	318	*/
	319	#define EMAC_FTR_EMAC4SYNC 0x00000200
1d3bb996 DG	320
	321
	322	/* Right now, we don't quite handle the always/possible masks on the
	323	* most optimal way as we don't have a way to say something like
	324	* always EMAC4. Patches welcome.
	325	*/
	326	enum {
	327	EMAC_FTRS_ALWAYS = 0,
	328
	329	EMAC_FTRS_POSSIBLE =
	330	#ifdef CONFIG_IBM_NEW_EMAC_EMAC4
05781ccd GE	331	EMAC_FTR_EMAC4 \| EMAC_FTR_EMAC4SYNC \|
05781ccd GE	332	EMAC_FTR_HAS_NEW_STACR \|
0925ab5d	333	EMAC_FTR_STACR_OC_INVERT \| EMAC_FTR_440GX_PHY_CLK_FIX \|
1d3bb996 DG	334	#endif
	335	#ifdef CONFIG_IBM_NEW_EMAC_TAH
	336	EMAC_FTR_HAS_TAH \|
	337	#endif
	338	#ifdef CONFIG_IBM_NEW_EMAC_ZMII
	339	EMAC_FTR_HAS_ZMII \|
	340	#endif
	341	#ifdef CONFIG_IBM_NEW_EMAC_RGMII
	342	EMAC_FTR_HAS_RGMII \|
	343	#endif
11121e30	344	EMAC_FTR_440EP_PHY_CLK_FIX,
1d3bb996 DG	345	};
	346
	347	static inline int emac_has_feature(struct emac_instance *dev,
	348	unsigned long feature)
	349	{
	350	return (EMAC_FTRS_ALWAYS & feature) \|\|
	351	(EMAC_FTRS_POSSIBLE & dev->features & feature);
	352	}
	353
05781ccd GE	354	/*
	355	* Various instances of the EMAC core have varying 1) number of
	356	* address match slots, 2) width of the registers for handling address
	357	* match slots, 3) number of registers for handling address match
	358	* slots and 4) base offset for those registers.
	359	*
	360	* These macros and inlines handle these differences based on
	361	* parameters supplied by the device structure which are, in turn,
	362	* initialized based on the "compatible" entry in the device tree.
	363	*/
	364
	365	#define EMAC4_XAHT_SLOTS_SHIFT 6
	366	#define EMAC4_XAHT_WIDTH_SHIFT 4
	367
	368	#define EMAC4SYNC_XAHT_SLOTS_SHIFT 8
	369	#define EMAC4SYNC_XAHT_WIDTH_SHIFT 5
	370
	371	#define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift)
	372	#define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift)
	373	#define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \
	374	(dev)->xaht_width_shift))
	375
	376	#define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \
	377	((EMAC_XAHT_SLOTS(dev) - 1) - \
	378	((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \
	379	(dev)->xaht_slots_shift)))
	380
	381	#define EMAC_XAHT_SLOT_TO_REG(dev, slot) \
	382	((slot) >> (dev)->xaht_width_shift)
	383
	384	#define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \
	385	((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \
	386	((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
	387
	388	static inline u32 emac_xaht_base(struct emac_instance dev)
	389	{
	390	struct emac_regs __iomem *p = dev->emacp;
	391	int offset;
	392
	393	/* The first IAHT entry always is the base of the block of
	394	* IAHT and GAHT registers.
	395	*/
	396	if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
	397	offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
	398	else
	399	offset = offsetof(struct emac_regs, u0.emac4.iaht1);
	400
	401	return ((u32 *)((ptrdiff_t)p + offset));
	402	}
	403
	404	static inline u32 emac_gaht_base(struct emac_instance dev)
	405	{
	406	/* GAHT registers always come after an identical number of
	407	* IAHT registers.
	408	*/
	409	return (emac_xaht_base(dev) + EMAC_XAHT_REGS(dev));
	410	}
	411
	412	static inline u32 emac_iaht_base(struct emac_instance dev)
	413	{
	414	/* IAHT registers always come before an identical number of
	415	* GAHT registers.
	416	*/
	417	return (emac_xaht_base(dev));
418	}
1d3bb996 DG	419
	420	/* Ethtool get_regs complex data.
	421	* We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
	422	* when available.
	423	*
	424	* Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
	425	* MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
	426	* Each register component is preceded with emac_ethtool_regs_subhdr.
	427	* Order of the optional headers follows their relative bit posititions
	428	* in emac_ethtool_regs_hdr.components
	429	*/
	430	#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
	431	#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
	432	#define EMAC_ETHTOOL_REGS_TAH 0x00000004
	433
	434	struct emac_ethtool_regs_hdr {
	435	u32 components;
	436	};
	437
	438	struct emac_ethtool_regs_subhdr {
	439	u32 version;
	440	u32 index;
	441	};
	442
05781ccd GE	443	#define EMAC_ETHTOOL_REGS_VER 0
	444	#define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \
	445	(dev)->rsrc_regs.start + 1)
	446	#define EMAC4_ETHTOOL_REGS_VER 1
	447	#define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \
	448	(dev)->rsrc_regs.start + 1)
	449
1d3bb996	450	#endif /* __IBM_NEWEMAC_CORE_H */