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Add dcr_host_t.base in dcr_read()/dcr_write()
[deliverable/linux.git] / drivers / net / ibm_newemac / mal.c
CommitLineData
1d3bb996
DG		 1/*
2 * drivers/net/ibm_newemac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
12 *
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 */
22
23#include <linux/delay.h>
24
25#include "core.h"
26
27static int mal_count;
28
29int __devinit mal_register_commac(struct mal_instance *mal,
30 struct mal_commac *commac)
31{
32 unsigned long flags;
33
34 spin_lock_irqsave(&mal->lock, flags);
35
36 MAL_DBG(mal, "reg(%08x, %08x)" NL,
37 commac->tx_chan_mask, commac->rx_chan_mask);
38
39 /* Don't let multiple commacs claim the same channel(s) */
40 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
41 (mal->rx_chan_mask & commac->rx_chan_mask)) {
42 spin_unlock_irqrestore(&mal->lock, flags);
43 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
44 mal->index);
45 return -EBUSY;
46 }
47
48 mal->tx_chan_mask |= commac->tx_chan_mask;
49 mal->rx_chan_mask |= commac->rx_chan_mask;
50 list_add(&commac->list, &mal->list);
51
52 spin_unlock_irqrestore(&mal->lock, flags);
53
54 return 0;
55}
56
57void __devexit mal_unregister_commac(struct mal_instance *mal,
58 struct mal_commac *commac)
59{
60 unsigned long flags;
61
62 spin_lock_irqsave(&mal->lock, flags);
63
64 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
65 commac->tx_chan_mask, commac->rx_chan_mask);
66
67 mal->tx_chan_mask &= ~commac->tx_chan_mask;
68 mal->rx_chan_mask &= ~commac->rx_chan_mask;
69 list_del_init(&commac->list);
70
71 spin_unlock_irqrestore(&mal->lock, flags);
72}
73
74int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
75{
76 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
77 size > MAL_MAX_RX_SIZE);
78
79 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
80
81 if (size & 0xf) {
82 printk(KERN_WARNING
83 "mal%d: incorrect RX size %lu for the channel %d\n",
84 mal->index, size, channel);
85 return -EINVAL;
86 }
87
88 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
89 return 0;
90}
91
92int mal_tx_bd_offset(struct mal_instance *mal, int channel)
93{
94 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
95
96 return channel * NUM_TX_BUFF;
97}
98
99int mal_rx_bd_offset(struct mal_instance *mal, int channel)
100{
101 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
102 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
103}
104
105void mal_enable_tx_channel(struct mal_instance *mal, int channel)
106{
107 unsigned long flags;
108
109 spin_lock_irqsave(&mal->lock, flags);
110
111 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
112
113 set_mal_dcrn(mal, MAL_TXCASR,
114 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
115
116 spin_unlock_irqrestore(&mal->lock, flags);
117}
118
119void mal_disable_tx_channel(struct mal_instance *mal, int channel)
120{
121 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
122
123 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
124}
125
126void mal_enable_rx_channel(struct mal_instance *mal, int channel)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&mal->lock, flags);
131
132 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
133
134 set_mal_dcrn(mal, MAL_RXCASR,
135 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
136
137 spin_unlock_irqrestore(&mal->lock, flags);
138}
139
140void mal_disable_rx_channel(struct mal_instance *mal, int channel)
141{
142 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
143
144 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
145}
146
147void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&mal->lock, flags);
152
153 MAL_DBG(mal, "poll_add(%p)" NL, commac);
154
155 /* starts disabled */
156 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
157
158 list_add_tail(&commac->poll_list, &mal->poll_list);
159
160 spin_unlock_irqrestore(&mal->lock, flags);
161}
162
163void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&mal->lock, flags);
168
169 MAL_DBG(mal, "poll_del(%p)" NL, commac);
170
171 list_del(&commac->poll_list);
172
173 spin_unlock_irqrestore(&mal->lock, flags);
174}
175
176/* synchronized by mal_poll() */
177static inline void mal_enable_eob_irq(struct mal_instance *mal)
178{
179 MAL_DBG2(mal, "enable_irq" NL);
180
181 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
182 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
183}
184
185/* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
186static inline void mal_disable_eob_irq(struct mal_instance *mal)
187{
188 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
189 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
190
191 MAL_DBG2(mal, "disable_irq" NL);
192}
193
194static irqreturn_t mal_serr(int irq, void *dev_instance)
195{
196 struct mal_instance *mal = dev_instance;
197
198 u32 esr = get_mal_dcrn(mal, MAL_ESR);
199
200 /* Clear the error status register */
201 set_mal_dcrn(mal, MAL_ESR, esr);
202
203 MAL_DBG(mal, "SERR %08x" NL, esr);
204
205 if (esr & MAL_ESR_EVB) {
206 if (esr & MAL_ESR_DE) {
207 /* We ignore Descriptor error,
208 * TXDE or RXDE interrupt will be generated anyway.
209 */
210 return IRQ_HANDLED;
211 }
212
213 if (esr & MAL_ESR_PEIN) {
214 /* PLB error, it's probably buggy hardware or
215 * incorrect physical address in BD (i.e. bug)
216 */
217 if (net_ratelimit())
218 printk(KERN_ERR
219 "mal%d: system error, "
220 "PLB (ESR = 0x%08x)\n",
221 mal->index, esr);
222 return IRQ_HANDLED;
223 }
224
225 /* OPB error, it's probably buggy hardware or incorrect
226 * EBC setup
227 */
228 if (net_ratelimit())
229 printk(KERN_ERR
230 "mal%d: system error, OPB (ESR = 0x%08x)\n",
231 mal->index, esr);
232 }
233 return IRQ_HANDLED;
234}
235
236static inline void mal_schedule_poll(struct mal_instance *mal)
237{
59e90b2d 238 if (likely(napi_schedule_prep(&mal->napi))) {
1d3bb996
DG		 239 MAL_DBG2(mal, "schedule_poll" NL);
240 mal_disable_eob_irq(mal);
59e90b2d 241 __napi_schedule(&mal->napi);
1d3bb996
DG		 242 } else
243 MAL_DBG2(mal, "already in poll" NL);
244}
245
246static irqreturn_t mal_txeob(int irq, void *dev_instance)
247{
248 struct mal_instance *mal = dev_instance;
249
250 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
251
252 MAL_DBG2(mal, "txeob %08x" NL, r);
253
254 mal_schedule_poll(mal);
255 set_mal_dcrn(mal, MAL_TXEOBISR, r);
256
257 return IRQ_HANDLED;
258}
259
260static irqreturn_t mal_rxeob(int irq, void *dev_instance)
261{
262 struct mal_instance *mal = dev_instance;
263
264 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
265
266 MAL_DBG2(mal, "rxeob %08x" NL, r);
267
268 mal_schedule_poll(mal);
269 set_mal_dcrn(mal, MAL_RXEOBISR, r);
270
271 return IRQ_HANDLED;
272}
273
274static irqreturn_t mal_txde(int irq, void *dev_instance)
275{
276 struct mal_instance *mal = dev_instance;
277
278 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
279 set_mal_dcrn(mal, MAL_TXDEIR, deir);
280
281 MAL_DBG(mal, "txde %08x" NL, deir);
282
283 if (net_ratelimit())
284 printk(KERN_ERR
285 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
286 mal->index, deir);
287
288 return IRQ_HANDLED;
289}
290
291static irqreturn_t mal_rxde(int irq, void *dev_instance)
292{
293 struct mal_instance *mal = dev_instance;
294 struct list_head *l;
295
296 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
297
298 MAL_DBG(mal, "rxde %08x" NL, deir);
299
300 list_for_each(l, &mal->list) {
301 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
302 if (deir & mc->rx_chan_mask) {
303 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
304 mc->ops->rxde(mc->dev);
305 }
306 }
307
308 mal_schedule_poll(mal);
309 set_mal_dcrn(mal, MAL_RXDEIR, deir);
310
311 return IRQ_HANDLED;
312}
313
314void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
315{
316 /* Spinlock-type semantics: only one caller disable poll at a time */
317 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
318 msleep(1);
319
320 /* Synchronize with the MAL NAPI poller. */
59e90b2d 321 napi_disable(&mal->napi);
1d3bb996
DG		 322}
323
324void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
325{
326 smp_wmb();
327 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
328
329 // XXX might want to kick a poll now...
330}
331
59e90b2d 332static int mal_poll(struct napi_struct *napi, int budget)
1d3bb996 333{
59e90b2d 334 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
1d3bb996 335 struct list_head *l;
59e90b2d 336 int received = 0;
1d3bb996
DG		 337 unsigned long flags;
338
339 MAL_DBG2(mal, "poll(%d) %d ->" NL, *budget,
340 rx_work_limit);
341 again:
342 /* Process TX skbs */
343 list_for_each(l, &mal->poll_list) {
344 struct mal_commac *mc =
345 list_entry(l, struct mal_commac, poll_list);
346 mc->ops->poll_tx(mc->dev);
347 }
348
349 /* Process RX skbs.
350 *
351 * We _might_ need something more smart here to enforce polling
352 * fairness.
353 */
354 list_for_each(l, &mal->poll_list) {
355 struct mal_commac *mc =
356 list_entry(l, struct mal_commac, poll_list);
357 int n;
358 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
359 continue;
59e90b2d 360 n = mc->ops->poll_rx(mc->dev, budget);
1d3bb996
DG		 361 if (n) {
362 received += n;
59e90b2d
RD		 363 budget -= n;
364 if (budget <= 0)
365 goto more_work; // XXX What if this is the last one ?
1d3bb996
DG		 366 }
367 }
368
369 /* We need to disable IRQs to protect from RXDE IRQ here */
370 spin_lock_irqsave(&mal->lock, flags);
59e90b2d 371 __napi_complete(napi);
1d3bb996
DG		 372 mal_enable_eob_irq(mal);
373 spin_unlock_irqrestore(&mal->lock, flags);
374
1d3bb996
DG		 375 /* Check for "rotting" packet(s) */
376 list_for_each(l, &mal->poll_list) {
377 struct mal_commac *mc =
378 list_entry(l, struct mal_commac, poll_list);
379 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
380 continue;
381 if (unlikely(mc->ops->peek_rx(mc->dev) ||
382 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
383 MAL_DBG2(mal, "rotting packet" NL);
59e90b2d 384 if (napi_reschedule(napi))
1d3bb996
DG		 385 mal_disable_eob_irq(mal);
386 else
387 MAL_DBG2(mal, "already in poll list" NL);
388
59e90b2d 389 if (budget > 0)
1d3bb996
DG		 390 goto again;
391 else
392 goto more_work;
393 }
394 mc->ops->poll_tx(mc->dev);
395 }
396
397 more_work:
59e90b2d
RD		 398 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
399 return received;
1d3bb996
DG		 400}
401
402static void mal_reset(struct mal_instance *mal)
403{
404 int n = 10;
405
406 MAL_DBG(mal, "reset" NL);
407
408 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
409
410 /* Wait for reset to complete (1 system clock) */
411 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
412 --n;
413
414 if (unlikely(!n))
415 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
416}
417
418int mal_get_regs_len(struct mal_instance *mal)
419{
420 return sizeof(struct emac_ethtool_regs_subhdr) +
421 sizeof(struct mal_regs);
422}
423
424void *mal_dump_regs(struct mal_instance *mal, void *buf)
425{
426 struct emac_ethtool_regs_subhdr *hdr = buf;
427 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
428 int i;
429
430 hdr->version = mal->version;
431 hdr->index = mal->index;
432
433 regs->tx_count = mal->num_tx_chans;
434 regs->rx_count = mal->num_rx_chans;
435
436 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
437 regs->esr = get_mal_dcrn(mal, MAL_ESR);
438 regs->ier = get_mal_dcrn(mal, MAL_IER);
439 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
440 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
441 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
442 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
443 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
444 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
445 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
446 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
447
448 for (i = 0; i < regs->tx_count; ++i)
449 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
450
451 for (i = 0; i < regs->rx_count; ++i) {
452 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
453 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
454 }
455 return regs + 1;
456}
457
458static int __devinit mal_probe(struct of_device *ofdev,
459 const struct of_device_id *match)
460{
461 struct mal_instance *mal;
462 int err = 0, i, bd_size;
463 int index = mal_count++;
79203695 464 unsigned int dcr_base;
1d3bb996
DG		 465 const u32 *prop;
466 u32 cfg;
467
468 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
469 if (!mal) {
470 printk(KERN_ERR
471 "mal%d: out of memory allocating MAL structure!\n",
472 index);
473 return -ENOMEM;
474 }
475 mal->index = index;
476 mal->ofdev = ofdev;
477 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
478
479 MAL_DBG(mal, "probe" NL);
480
481 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
482 if (prop == NULL) {
483 printk(KERN_ERR
484 "mal%d: can't find MAL num-tx-chans property!\n",
485 index);
486 err = -ENODEV;
487 goto fail;
488 }
489 mal->num_tx_chans = prop[0];
490
491 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
492 if (prop == NULL) {
493 printk(KERN_ERR
494 "mal%d: can't find MAL num-rx-chans property!\n",
495 index);
496 err = -ENODEV;
497 goto fail;
498 }
499 mal->num_rx_chans = prop[0];
500
79203695
ME		 501 dcr_base = dcr_resource_start(ofdev->node, 0);
502 if (dcr_base == 0) {
1d3bb996
DG		 503 printk(KERN_ERR
504 "mal%d: can't find DCR resource!\n", index);
505 err = -ENODEV;
506 goto fail;
507 }
79203695 508 mal->dcr_host = dcr_map(ofdev->node, dcr_base, 0x100);
1d3bb996
DG		 509 if (!DCR_MAP_OK(mal->dcr_host)) {
510 printk(KERN_ERR
511 "mal%d: failed to map DCRs !\n", index);
512 err = -ENODEV;
513 goto fail;
514 }
515
516 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
517 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
518 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
519 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
520 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
521 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
522 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
523 mal->rxde_irq == NO_IRQ) {
524 printk(KERN_ERR
525 "mal%d: failed to map interrupts !\n", index);
526 err = -ENODEV;
527 goto fail_unmap;
528 }
529
530 INIT_LIST_HEAD(&mal->poll_list);
59e90b2d
RD		 531 mal->napi.weight = CONFIG_IBM_NEW_EMAC_POLL_WEIGHT;
532 mal->napi.poll = mal_poll;
1d3bb996
DG		 533 INIT_LIST_HEAD(&mal->list);
534 spin_lock_init(&mal->lock);
535
536 /* Load power-on reset defaults */
537 mal_reset(mal);
538
539 /* Set the MAL configuration register */
540 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
541 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
542
543 /* Current Axon is not happy with priority being non-0, it can
544 * deadlock, fix it up here
545 */
546 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
547 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
548
549 /* Apply configuration */
550 set_mal_dcrn(mal, MAL_CFG, cfg);
551
552 /* Allocate space for BD rings */
553 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
554 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
555
556 bd_size = sizeof(struct mal_descriptor) *
557 (NUM_TX_BUFF * mal->num_tx_chans +
558 NUM_RX_BUFF * mal->num_rx_chans);
559 mal->bd_virt =
560 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
561 GFP_KERNEL);
562 if (mal->bd_virt == NULL) {
563 printk(KERN_ERR
564 "mal%d: out of memory allocating RX/TX descriptors!\n",
565 index);
566 err = -ENOMEM;
567 goto fail_unmap;
568 }
569 memset(mal->bd_virt, 0, bd_size);
570
571 for (i = 0; i < mal->num_tx_chans; ++i)
572 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
573 sizeof(struct mal_descriptor) *
574 mal_tx_bd_offset(mal, i));
575
576 for (i = 0; i < mal->num_rx_chans; ++i)
577 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
578 sizeof(struct mal_descriptor) *
579 mal_rx_bd_offset(mal, i));
580
581 err = request_irq(mal->serr_irq, mal_serr, 0, "MAL SERR", mal);
582 if (err)
583 goto fail2;
584 err = request_irq(mal->txde_irq, mal_txde, 0, "MAL TX DE", mal);
585 if (err)
586 goto fail3;
587 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
588 if (err)
589 goto fail4;
590 err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
591 if (err)
592 goto fail5;
593 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
594 if (err)
595 goto fail6;
596
597 /* Enable all MAL SERR interrupt sources */
598 if (mal->version == 2)
599 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
600 else
601 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
602
603 /* Enable EOB interrupt */
604 mal_enable_eob_irq(mal);
605
606 printk(KERN_INFO
607 "MAL v%d %s, %d TX channels, %d RX channels\n",
608 mal->version, ofdev->node->full_name,
609 mal->num_tx_chans, mal->num_rx_chans);
610
611 /* Advertise this instance to the rest of the world */
612 wmb();
613 dev_set_drvdata(&ofdev->dev, mal);
614
615 mal_dbg_register(mal);
616
617 return 0;
618
619 fail6:
620 free_irq(mal->rxde_irq, mal);
621 fail5:
622 free_irq(mal->txeob_irq, mal);
623 fail4:
624 free_irq(mal->txde_irq, mal);
625 fail3:
626 free_irq(mal->serr_irq, mal);
627 fail2:
628 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
629 fail_unmap:
79203695 630 dcr_unmap(mal->dcr_host, dcr_base, 0x100);
1d3bb996
DG		 631 fail:
632 kfree(mal);
633
634 return err;
635}
636
637static int __devexit mal_remove(struct of_device *ofdev)
638{
639 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
640
641 MAL_DBG(mal, "remove" NL);
642
59e90b2d
RD		 643 /* Synchronize with scheduled polling */
644 napi_disable(&mal->napi);
1d3bb996
DG		 645
646 if (!list_empty(&mal->list)) {
647 /* This is *very* bad */
648 printk(KERN_EMERG
649 "mal%d: commac list is not empty on remove!\n",
650 mal->index);
651 WARN_ON(1);
652 }
653
654 dev_set_drvdata(&ofdev->dev, NULL);
655
656 free_irq(mal->serr_irq, mal);
657 free_irq(mal->txde_irq, mal);
658 free_irq(mal->txeob_irq, mal);
659 free_irq(mal->rxde_irq, mal);
660 free_irq(mal->rxeob_irq, mal);
661
662 mal_reset(mal);
663
664 mal_dbg_unregister(mal);
665
666 dma_free_coherent(&ofdev->dev,
667 sizeof(struct mal_descriptor) *
668 (NUM_TX_BUFF * mal->num_tx_chans +
669 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
670 mal->bd_dma);
671 kfree(mal);
672
673 return 0;
674}
675
676static struct of_device_id mal_platform_match[] =
677{
678 {
679 .compatible = "ibm,mcmal",
680 },
681 {
682 .compatible = "ibm,mcmal2",
683 },
684 /* Backward compat */
685 {
686 .type = "mcmal-dma",
687 .compatible = "ibm,mcmal",
688 },
689 {
690 .type = "mcmal-dma",
691 .compatible = "ibm,mcmal2",
692 },
693 {},
694};
695
696static struct of_platform_driver mal_of_driver = {
697 .name = "mcmal",
698 .match_table = mal_platform_match,
699
700 .probe = mal_probe,
701 .remove = mal_remove,
702};
703
704int __init mal_init(void)
705{
706 return of_register_platform_driver(&mal_of_driver);
707}
708
709void mal_exit(void)
710{
711 of_unregister_platform_driver(&mal_of_driver);
712}
Linux kernel - Deliverables
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