Merge branch 'kconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / drivers / net / ieee802154 / at86rf230.c
CommitLineData
7b8e19b6 1/*
2 * AT86RF230/RF231 driver
3 *
4 * Copyright (C) 2009-2012 Siemens AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
7b8e19b6 15 * Written by:
16 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
17 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
01ebd60b 18 * Alexander Aring <aar@pengutronix.de>
7b8e19b6 19 */
20#include <linux/kernel.h>
21#include <linux/module.h>
eb3b435e 22#include <linux/hrtimer.h>
dce481e6 23#include <linux/jiffies.h>
7b8e19b6 24#include <linux/interrupt.h>
4af619ae 25#include <linux/irq.h>
7b8e19b6 26#include <linux/gpio.h>
27#include <linux/delay.h>
7b8e19b6 28#include <linux/spi/spi.h>
29#include <linux/spi/at86rf230.h>
f76014f7 30#include <linux/regmap.h>
7b8e19b6 31#include <linux/skbuff.h>
fa2d3e94 32#include <linux/of_gpio.h>
4ca24aca 33#include <linux/ieee802154.h>
493bc90a 34#include <linux/debugfs.h>
7b8e19b6 35
36#include <net/mac802154.h>
5ad60d36 37#include <net/cfg802154.h>
7b8e19b6 38
7490b008
AA
39#include "at86rf230.h"
40
a53d1f7c
AA
41struct at86rf230_local;
42/* at86rf2xx chip depend data.
43 * All timings are in us.
44 */
45struct at86rf2xx_chip_data {
7a4ef918 46 u16 t_sleep_cycle;
984e0c68 47 u16 t_channel_switch;
09e536cd 48 u16 t_reset_to_off;
2e0571c0
AA
49 u16 t_off_to_aack;
50 u16 t_off_to_tx_on;
e6f7ed9d
AA
51 u16 t_off_to_sleep;
52 u16 t_sleep_to_off;
1d15d6b5
AA
53 u16 t_frame;
54 u16 t_p_ack;
a53d1f7c
AA
55 int rssi_base_val;
56
e37d2ec8 57 int (*set_channel)(struct at86rf230_local *, u8, u8);
6f4da3f8 58 int (*set_txpower)(struct at86rf230_local *, s32);
a53d1f7c
AA
59};
60
ba6d2239
AA
61#define AT86RF2XX_MAX_BUF (127 + 3)
62/* tx retries to access the TX_ON state
63 * if it's above then force change will be started.
64 *
65 * We assume the max_frame_retries (7) value of 802.15.4 here.
66 */
67#define AT86RF2XX_MAX_TX_RETRIES 7
dce481e6
AA
68/* We use the recommended 5 minutes timeout to recalibrate */
69#define AT86RF2XX_CAL_LOOP_TIMEOUT (5 * 60 * HZ)
7b8e19b6 70
1d15d6b5
AA
71struct at86rf230_state_change {
72 struct at86rf230_local *lp;
cca990c8 73 int irq;
7b8e19b6 74
eb3b435e 75 struct hrtimer timer;
1d15d6b5
AA
76 struct spi_message msg;
77 struct spi_transfer trx;
78 u8 buf[AT86RF2XX_MAX_BUF];
79
80 void (*complete)(void *context);
81 u8 from_state;
82 u8 to_state;
97fed795 83
57c1bc7e 84 bool free;
1d15d6b5
AA
85};
86
493bc90a
AA
87struct at86rf230_trac {
88 u64 success;
89 u64 success_data_pending;
90 u64 success_wait_for_ack;
91 u64 channel_access_failure;
92 u64 no_ack;
93 u64 invalid;
94};
95
1d15d6b5
AA
96struct at86rf230_local {
97 struct spi_device *spi;
7b8e19b6 98
5a504397 99 struct ieee802154_hw *hw;
1d15d6b5 100 struct at86rf2xx_chip_data *data;
f76014f7 101 struct regmap *regmap;
d2c8bf51 102 int slp_tr;
cbe62346 103 bool sleep;
7b8e19b6 104
2e0571c0
AA
105 struct completion state_complete;
106 struct at86rf230_state_change state;
107
dce481e6 108 unsigned long cal_timeout;
1d15d6b5 109 bool is_tx;
85009203 110 bool is_tx_from_off;
ba6d2239 111 u8 tx_retry;
1d15d6b5
AA
112 struct sk_buff *tx_skb;
113 struct at86rf230_state_change tx;
493bc90a
AA
114
115 struct at86rf230_trac trac;
7b8e19b6 116};
117
f76014f7
AA
118#define AT86RF2XX_NUMREGS 0x3F
119
97fed795 120static void
1d15d6b5
AA
121at86rf230_async_state_change(struct at86rf230_local *lp,
122 struct at86rf230_state_change *ctx,
57c1bc7e 123 const u8 state, void (*complete)(void *context));
1d15d6b5 124
cbe62346
AA
125static inline void
126at86rf230_sleep(struct at86rf230_local *lp)
127{
128 if (gpio_is_valid(lp->slp_tr)) {
129 gpio_set_value(lp->slp_tr, 1);
130 usleep_range(lp->data->t_off_to_sleep,
131 lp->data->t_off_to_sleep + 10);
132 lp->sleep = true;
133 }
134}
135
136static inline void
137at86rf230_awake(struct at86rf230_local *lp)
138{
139 if (gpio_is_valid(lp->slp_tr)) {
140 gpio_set_value(lp->slp_tr, 0);
141 usleep_range(lp->data->t_sleep_to_off,
142 lp->data->t_sleep_to_off + 100);
143 lp->sleep = false;
144 }
145}
146
f76014f7
AA
147static inline int
148__at86rf230_write(struct at86rf230_local *lp,
149 unsigned int addr, unsigned int data)
150{
cbe62346
AA
151 bool sleep = lp->sleep;
152 int ret;
153
154 /* awake for register setting if sleep */
155 if (sleep)
156 at86rf230_awake(lp);
157
158 ret = regmap_write(lp->regmap, addr, data);
159
160 /* sleep again if was sleeping */
161 if (sleep)
162 at86rf230_sleep(lp);
163
164 return ret;
f76014f7
AA
165}
166
167static inline int
168__at86rf230_read(struct at86rf230_local *lp,
169 unsigned int addr, unsigned int *data)
170{
cbe62346
AA
171 bool sleep = lp->sleep;
172 int ret;
173
174 /* awake for register setting if sleep */
175 if (sleep)
176 at86rf230_awake(lp);
177
178 ret = regmap_read(lp->regmap, addr, data);
179
180 /* sleep again if was sleeping */
181 if (sleep)
182 at86rf230_sleep(lp);
183
184 return ret;
f76014f7
AA
185}
186
187static inline int
188at86rf230_read_subreg(struct at86rf230_local *lp,
189 unsigned int addr, unsigned int mask,
190 unsigned int shift, unsigned int *data)
191{
192 int rc;
193
194 rc = __at86rf230_read(lp, addr, data);
d907c4f0 195 if (!rc)
f76014f7
AA
196 *data = (*data & mask) >> shift;
197
198 return rc;
199}
200
201static inline int
202at86rf230_write_subreg(struct at86rf230_local *lp,
203 unsigned int addr, unsigned int mask,
204 unsigned int shift, unsigned int data)
205{
cbe62346
AA
206 bool sleep = lp->sleep;
207 int ret;
208
209 /* awake for register setting if sleep */
210 if (sleep)
211 at86rf230_awake(lp);
212
213 ret = regmap_update_bits(lp->regmap, addr, mask, data << shift);
214
215 /* sleep again if was sleeping */
216 if (sleep)
217 at86rf230_sleep(lp);
218
219 return ret;
f76014f7
AA
220}
221
d2c8bf51
AA
222static inline void
223at86rf230_slp_tr_rising_edge(struct at86rf230_local *lp)
224{
225 gpio_set_value(lp->slp_tr, 1);
226 udelay(1);
227 gpio_set_value(lp->slp_tr, 0);
228}
229
f76014f7
AA
230static bool
231at86rf230_reg_writeable(struct device *dev, unsigned int reg)
232{
233 switch (reg) {
234 case RG_TRX_STATE:
235 case RG_TRX_CTRL_0:
236 case RG_TRX_CTRL_1:
237 case RG_PHY_TX_PWR:
238 case RG_PHY_ED_LEVEL:
239 case RG_PHY_CC_CCA:
240 case RG_CCA_THRES:
241 case RG_RX_CTRL:
242 case RG_SFD_VALUE:
243 case RG_TRX_CTRL_2:
244 case RG_ANT_DIV:
245 case RG_IRQ_MASK:
246 case RG_VREG_CTRL:
247 case RG_BATMON:
248 case RG_XOSC_CTRL:
249 case RG_RX_SYN:
250 case RG_XAH_CTRL_1:
251 case RG_FTN_CTRL:
252 case RG_PLL_CF:
253 case RG_PLL_DCU:
254 case RG_SHORT_ADDR_0:
255 case RG_SHORT_ADDR_1:
256 case RG_PAN_ID_0:
257 case RG_PAN_ID_1:
258 case RG_IEEE_ADDR_0:
259 case RG_IEEE_ADDR_1:
260 case RG_IEEE_ADDR_2:
261 case RG_IEEE_ADDR_3:
262 case RG_IEEE_ADDR_4:
263 case RG_IEEE_ADDR_5:
264 case RG_IEEE_ADDR_6:
265 case RG_IEEE_ADDR_7:
266 case RG_XAH_CTRL_0:
267 case RG_CSMA_SEED_0:
268 case RG_CSMA_SEED_1:
269 case RG_CSMA_BE:
270 return true;
271 default:
272 return false;
273 }
274}
275
276static bool
277at86rf230_reg_readable(struct device *dev, unsigned int reg)
278{
279 bool rc;
280
281 /* all writeable are also readable */
282 rc = at86rf230_reg_writeable(dev, reg);
283 if (rc)
284 return rc;
285
286 /* readonly regs */
287 switch (reg) {
288 case RG_TRX_STATUS:
289 case RG_PHY_RSSI:
290 case RG_IRQ_STATUS:
291 case RG_PART_NUM:
292 case RG_VERSION_NUM:
293 case RG_MAN_ID_1:
294 case RG_MAN_ID_0:
295 return true;
296 default:
297 return false;
298 }
299}
300
301static bool
302at86rf230_reg_volatile(struct device *dev, unsigned int reg)
303{
304 /* can be changed during runtime */
305 switch (reg) {
306 case RG_TRX_STATUS:
307 case RG_TRX_STATE:
308 case RG_PHY_RSSI:
309 case RG_PHY_ED_LEVEL:
310 case RG_IRQ_STATUS:
311 case RG_VREG_CTRL:
51b3b2cf
AA
312 case RG_PLL_CF:
313 case RG_PLL_DCU:
f76014f7
AA
314 return true;
315 default:
316 return false;
317 }
318}
319
320static bool
321at86rf230_reg_precious(struct device *dev, unsigned int reg)
322{
323 /* don't clear irq line on read */
324 switch (reg) {
325 case RG_IRQ_STATUS:
326 return true;
327 default:
328 return false;
329 }
330}
331
889ee2c7 332static const struct regmap_config at86rf230_regmap_spi_config = {
f76014f7
AA
333 .reg_bits = 8,
334 .val_bits = 8,
335 .write_flag_mask = CMD_REG | CMD_WRITE,
336 .read_flag_mask = CMD_REG,
337 .cache_type = REGCACHE_RBTREE,
338 .max_register = AT86RF2XX_NUMREGS,
339 .writeable_reg = at86rf230_reg_writeable,
340 .readable_reg = at86rf230_reg_readable,
341 .volatile_reg = at86rf230_reg_volatile,
342 .precious_reg = at86rf230_reg_precious,
343};
344
1d15d6b5
AA
345static void
346at86rf230_async_error_recover(void *context)
347{
348 struct at86rf230_state_change *ctx = context;
349 struct at86rf230_local *lp = ctx->lp;
350
a7a484bf 351 lp->is_tx = 0;
57c1bc7e 352 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL);
955aee8b 353 ieee802154_wake_queue(lp->hw);
57c1bc7e
AA
354 if (ctx->free)
355 kfree(ctx);
1d15d6b5
AA
356}
357
fc50c6e3 358static inline void
1d15d6b5
AA
359at86rf230_async_error(struct at86rf230_local *lp,
360 struct at86rf230_state_change *ctx, int rc)
361{
362 dev_err(&lp->spi->dev, "spi_async error %d\n", rc);
363
364 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
57c1bc7e 365 at86rf230_async_error_recover);
1d15d6b5
AA
366}
367
368/* Generic function to get some register value in async mode */
97fed795 369static void
57c1bc7e 370at86rf230_async_read_reg(struct at86rf230_local *lp, u8 reg,
1d15d6b5 371 struct at86rf230_state_change *ctx,
57c1bc7e 372 void (*complete)(void *context))
7b8e19b6 373{
97fed795
AA
374 int rc;
375
1d15d6b5
AA
376 u8 *tx_buf = ctx->buf;
377
378 tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
1d15d6b5 379 ctx->msg.complete = complete;
97fed795 380 rc = spi_async(lp->spi, &ctx->msg);
57c1bc7e
AA
381 if (rc)
382 at86rf230_async_error(lp, ctx, rc);
383}
97fed795 384
57c1bc7e
AA
385static void
386at86rf230_async_write_reg(struct at86rf230_local *lp, u8 reg, u8 val,
387 struct at86rf230_state_change *ctx,
388 void (*complete)(void *context))
389{
390 int rc;
391
392 ctx->buf[0] = (reg & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
393 ctx->buf[1] = val;
394 ctx->msg.complete = complete;
395 rc = spi_async(lp->spi, &ctx->msg);
396 if (rc)
97fed795 397 at86rf230_async_error(lp, ctx, rc);
1d15d6b5
AA
398}
399
400static void
401at86rf230_async_state_assert(void *context)
402{
403 struct at86rf230_state_change *ctx = context;
404 struct at86rf230_local *lp = ctx->lp;
405 const u8 *buf = ctx->buf;
4748e86e 406 const u8 trx_state = buf[1] & TRX_STATE_MASK;
1d15d6b5
AA
407
408 /* Assert state change */
409 if (trx_state != ctx->to_state) {
410 /* Special handling if transceiver state is in
411 * STATE_BUSY_RX_AACK and a SHR was detected.
412 */
413 if (trx_state == STATE_BUSY_RX_AACK) {
414 /* Undocumented race condition. If we send a state
415 * change to STATE_RX_AACK_ON the transceiver could
416 * change his state automatically to STATE_BUSY_RX_AACK
417 * if a SHR was detected. This is not an error, but we
418 * can't assert this.
419 */
420 if (ctx->to_state == STATE_RX_AACK_ON)
421 goto done;
422
423 /* If we change to STATE_TX_ON without forcing and
424 * transceiver state is STATE_BUSY_RX_AACK, we wait
425 * 'tFrame + tPAck' receiving time. In this time the
426 * PDU should be received. If the transceiver is still
427 * in STATE_BUSY_RX_AACK, we run a force state change
428 * to STATE_TX_ON. This is a timeout handling, if the
429 * transceiver stucks in STATE_BUSY_RX_AACK.
ba6d2239
AA
430 *
431 * Additional we do several retries to try to get into
432 * TX_ON state without forcing. If the retries are
433 * higher or equal than AT86RF2XX_MAX_TX_RETRIES we
434 * will do a force change.
1d15d6b5 435 */
dce481e6
AA
436 if (ctx->to_state == STATE_TX_ON ||
437 ctx->to_state == STATE_TRX_OFF) {
438 u8 state = ctx->to_state;
ba6d2239
AA
439
440 if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES)
ed4a26b0 441 state = STATE_FORCE_TRX_OFF;
ba6d2239
AA
442 lp->tx_retry++;
443
444 at86rf230_async_state_change(lp, ctx, state,
57c1bc7e 445 ctx->complete);
1d15d6b5
AA
446 return;
447 }
448 }
449
1d15d6b5
AA
450 dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n",
451 ctx->from_state, ctx->to_state, trx_state);
452 }
453
454done:
455 if (ctx->complete)
456 ctx->complete(context);
457}
458
eb3b435e
AA
459static enum hrtimer_restart at86rf230_async_state_timer(struct hrtimer *timer)
460{
461 struct at86rf230_state_change *ctx =
462 container_of(timer, struct at86rf230_state_change, timer);
463 struct at86rf230_local *lp = ctx->lp;
464
465 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
57c1bc7e 466 at86rf230_async_state_assert);
eb3b435e
AA
467
468 return HRTIMER_NORESTART;
469}
470
1d15d6b5
AA
471/* Do state change timing delay. */
472static void
473at86rf230_async_state_delay(void *context)
474{
475 struct at86rf230_state_change *ctx = context;
476 struct at86rf230_local *lp = ctx->lp;
477 struct at86rf2xx_chip_data *c = lp->data;
478 bool force = false;
eb3b435e 479 ktime_t tim;
1d15d6b5
AA
480
481 /* The force state changes are will show as normal states in the
482 * state status subregister. We change the to_state to the
483 * corresponding one and remember if it was a force change, this
484 * differs if we do a state change from STATE_BUSY_RX_AACK.
485 */
486 switch (ctx->to_state) {
487 case STATE_FORCE_TX_ON:
488 ctx->to_state = STATE_TX_ON;
489 force = true;
490 break;
491 case STATE_FORCE_TRX_OFF:
492 ctx->to_state = STATE_TRX_OFF;
493 force = true;
494 break;
495 default:
496 break;
497 }
498
499 switch (ctx->from_state) {
2e0571c0
AA
500 case STATE_TRX_OFF:
501 switch (ctx->to_state) {
502 case STATE_RX_AACK_ON:
eb3b435e 503 tim = ktime_set(0, c->t_off_to_aack * NSEC_PER_USEC);
2ad33244
AA
504 /* state change from TRX_OFF to RX_AACK_ON to do a
505 * calibration, we need to reset the timeout for the
506 * next one.
507 */
508 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
2e0571c0 509 goto change;
3b951ca7 510 case STATE_TX_ARET_ON:
2e0571c0 511 case STATE_TX_ON:
eb3b435e 512 tim = ktime_set(0, c->t_off_to_tx_on * NSEC_PER_USEC);
3b951ca7
AA
513 /* state change from TRX_OFF to TX_ON or ARET_ON to do
514 * a calibration, we need to reset the timeout for the
dce481e6
AA
515 * next one.
516 */
517 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
2e0571c0
AA
518 goto change;
519 default:
520 break;
521 }
522 break;
1d15d6b5
AA
523 case STATE_BUSY_RX_AACK:
524 switch (ctx->to_state) {
dce481e6 525 case STATE_TRX_OFF:
1d15d6b5
AA
526 case STATE_TX_ON:
527 /* Wait for worst case receiving time if we
528 * didn't make a force change from BUSY_RX_AACK
dce481e6 529 * to TX_ON or TRX_OFF.
1d15d6b5
AA
530 */
531 if (!force) {
eb3b435e
AA
532 tim = ktime_set(0, (c->t_frame + c->t_p_ack) *
533 NSEC_PER_USEC);
1d15d6b5
AA
534 goto change;
535 }
536 break;
537 default:
538 break;
539 }
540 break;
09e536cd
AA
541 /* Default value, means RESET state */
542 case STATE_P_ON:
543 switch (ctx->to_state) {
544 case STATE_TRX_OFF:
eb3b435e 545 tim = ktime_set(0, c->t_reset_to_off * NSEC_PER_USEC);
09e536cd
AA
546 goto change;
547 default:
548 break;
549 }
550 break;
1d15d6b5
AA
551 default:
552 break;
553 }
554
555 /* Default delay is 1us in the most cases */
8b44f0dd
AA
556 udelay(1);
557 at86rf230_async_state_timer(&ctx->timer);
558 return;
1d15d6b5
AA
559
560change:
eb3b435e 561 hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
1d15d6b5
AA
562}
563
564static void
565at86rf230_async_state_change_start(void *context)
566{
567 struct at86rf230_state_change *ctx = context;
568 struct at86rf230_local *lp = ctx->lp;
569 u8 *buf = ctx->buf;
4748e86e 570 const u8 trx_state = buf[1] & TRX_STATE_MASK;
1d15d6b5
AA
571
572 /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */
573 if (trx_state == STATE_TRANSITION_IN_PROGRESS) {
574 udelay(1);
97fed795 575 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
57c1bc7e 576 at86rf230_async_state_change_start);
1d15d6b5
AA
577 return;
578 }
579
580 /* Check if we already are in the state which we change in */
581 if (trx_state == ctx->to_state) {
582 if (ctx->complete)
583 ctx->complete(context);
584 return;
585 }
586
587 /* Set current state to the context of state change */
588 ctx->from_state = trx_state;
589
590 /* Going into the next step for a state change which do a timing
591 * relevant delay.
592 */
57c1bc7e
AA
593 at86rf230_async_write_reg(lp, RG_TRX_STATE, ctx->to_state, ctx,
594 at86rf230_async_state_delay);
7b8e19b6 595}
596
97fed795 597static void
1d15d6b5
AA
598at86rf230_async_state_change(struct at86rf230_local *lp,
599 struct at86rf230_state_change *ctx,
57c1bc7e 600 const u8 state, void (*complete)(void *context))
7b8e19b6 601{
1d15d6b5
AA
602 /* Initialization for the state change context */
603 ctx->to_state = state;
604 ctx->complete = complete;
97fed795 605 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
57c1bc7e 606 at86rf230_async_state_change_start);
1d15d6b5 607}
7b8e19b6 608
2e0571c0
AA
609static void
610at86rf230_sync_state_change_complete(void *context)
611{
612 struct at86rf230_state_change *ctx = context;
613 struct at86rf230_local *lp = ctx->lp;
614
615 complete(&lp->state_complete);
616}
617
618/* This function do a sync framework above the async state change.
619 * Some callbacks of the IEEE 802.15.4 driver interface need to be
620 * handled synchronously.
621 */
622static int
623at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state)
624{
3e544ef9 625 unsigned long rc;
2e0571c0 626
97fed795 627 at86rf230_async_state_change(lp, &lp->state, state,
57c1bc7e 628 at86rf230_sync_state_change_complete);
2e0571c0
AA
629
630 rc = wait_for_completion_timeout(&lp->state_complete,
631 msecs_to_jiffies(100));
d06c2199
AA
632 if (!rc) {
633 at86rf230_async_error(lp, &lp->state, -ETIMEDOUT);
2e0571c0 634 return -ETIMEDOUT;
d06c2199 635 }
2e0571c0
AA
636
637 return 0;
638}
639
1d15d6b5
AA
640static void
641at86rf230_tx_complete(void *context)
642{
643 struct at86rf230_state_change *ctx = context;
644 struct at86rf230_local *lp = ctx->lp;
645
fc0719e6 646 ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);
57c1bc7e 647 kfree(ctx);
1d15d6b5
AA
648}
649
650static void
651at86rf230_tx_on(void *context)
652{
653 struct at86rf230_state_change *ctx = context;
654 struct at86rf230_local *lp = ctx->lp;
1d15d6b5 655
31fa7434 656 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
57c1bc7e 657 at86rf230_tx_complete);
1d15d6b5
AA
658}
659
1d15d6b5
AA
660static void
661at86rf230_tx_trac_check(void *context)
662{
663 struct at86rf230_state_change *ctx = context;
664 struct at86rf230_local *lp = ctx->lp;
1d15d6b5 665
493bc90a
AA
666 if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS)) {
667 u8 trac = TRAC_MASK(ctx->buf[1]);
668
669 switch (trac) {
670 case TRAC_SUCCESS:
671 lp->trac.success++;
672 break;
673 case TRAC_SUCCESS_DATA_PENDING:
674 lp->trac.success_data_pending++;
675 break;
676 case TRAC_CHANNEL_ACCESS_FAILURE:
677 lp->trac.channel_access_failure++;
678 break;
679 case TRAC_NO_ACK:
680 lp->trac.no_ack++;
681 break;
682 case TRAC_INVALID:
683 lp->trac.invalid++;
684 break;
685 default:
686 WARN_ONCE(1, "received tx trac status %d\n", trac);
687 break;
688 }
689 }
690
57c1bc7e 691 at86rf230_async_state_change(lp, ctx, STATE_TX_ON, at86rf230_tx_on);
1d15d6b5
AA
692}
693
694static void
74de4c80 695at86rf230_rx_read_frame_complete(void *context)
1d15d6b5 696{
74de4c80
AA
697 struct at86rf230_state_change *ctx = context;
698 struct at86rf230_local *lp = ctx->lp;
31fa7434 699 const u8 *buf = ctx->buf;
74de4c80
AA
700 struct sk_buff *skb;
701 u8 len, lqi;
1d15d6b5 702
74de4c80
AA
703 len = buf[1];
704 if (!ieee802154_is_valid_psdu_len(len)) {
705 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
706 len = IEEE802154_MTU;
707 }
708 lqi = buf[2 + len];
709
61a22814 710 skb = dev_alloc_skb(IEEE802154_MTU);
1d15d6b5
AA
711 if (!skb) {
712 dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n");
57c1bc7e 713 kfree(ctx);
1d15d6b5
AA
714 return;
715 }
716
57c1bc7e 717 memcpy(skb_put(skb, len), buf + 2, len);
b89c3341 718 ieee802154_rx_irqsafe(lp->hw, skb, lqi);
57c1bc7e 719 kfree(ctx);
1d15d6b5 720}
7b8e19b6 721
97fed795 722static void
493bc90a 723at86rf230_rx_trac_check(void *context)
1d15d6b5 724{
cca990c8
AA
725 struct at86rf230_state_change *ctx = context;
726 struct at86rf230_local *lp = ctx->lp;
31fa7434 727 u8 *buf = ctx->buf;
97fed795
AA
728 int rc;
729
493bc90a
AA
730 if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS)) {
731 u8 trac = TRAC_MASK(buf[1]);
732
733 switch (trac) {
734 case TRAC_SUCCESS:
735 lp->trac.success++;
736 break;
737 case TRAC_SUCCESS_WAIT_FOR_ACK:
738 lp->trac.success_wait_for_ack++;
739 break;
740 case TRAC_INVALID:
741 lp->trac.invalid++;
742 break;
743 default:
744 WARN_ONCE(1, "received rx trac status %d\n", trac);
745 break;
746 }
747 }
748
7b8e19b6 749 buf[0] = CMD_FB;
31fa7434
AA
750 ctx->trx.len = AT86RF2XX_MAX_BUF;
751 ctx->msg.complete = at86rf230_rx_read_frame_complete;
752 rc = spi_async(lp->spi, &ctx->msg);
97fed795 753 if (rc) {
263be332 754 ctx->trx.len = 2;
31fa7434 755 at86rf230_async_error(lp, ctx, rc);
97fed795 756 }
1d15d6b5
AA
757}
758
97fed795 759static void
57c1bc7e 760at86rf230_irq_trx_end(void *context)
1d15d6b5 761{
57c1bc7e
AA
762 struct at86rf230_state_change *ctx = context;
763 struct at86rf230_local *lp = ctx->lp;
764
1d15d6b5
AA
765 if (lp->is_tx) {
766 lp->is_tx = 0;
57c1bc7e
AA
767 at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
768 at86rf230_tx_trac_check);
1d15d6b5 769 } else {
57c1bc7e
AA
770 at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
771 at86rf230_rx_trac_check);
1d15d6b5
AA
772 }
773}
774
775static void
776at86rf230_irq_status(void *context)
777{
778 struct at86rf230_state_change *ctx = context;
779 struct at86rf230_local *lp = ctx->lp;
31fa7434 780 const u8 *buf = ctx->buf;
57c1bc7e
AA
781 u8 irq = buf[1];
782
783 enable_irq(lp->spi->irq);
1d15d6b5
AA
784
785 if (irq & IRQ_TRX_END) {
57c1bc7e 786 at86rf230_irq_trx_end(ctx);
1d15d6b5 787 } else {
1d15d6b5
AA
788 dev_err(&lp->spi->dev, "not supported irq %02x received\n",
789 irq);
57c1bc7e 790 kfree(ctx);
1d15d6b5
AA
791 }
792}
793
57c1bc7e
AA
794static void
795at86rf230_setup_spi_messages(struct at86rf230_local *lp,
796 struct at86rf230_state_change *state)
797{
798 state->lp = lp;
799 state->irq = lp->spi->irq;
800 spi_message_init(&state->msg);
801 state->msg.context = state;
802 state->trx.len = 2;
803 state->trx.tx_buf = state->buf;
804 state->trx.rx_buf = state->buf;
805 spi_message_add_tail(&state->trx, &state->msg);
806 hrtimer_init(&state->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
807 state->timer.function = at86rf230_async_state_timer;
808}
809
1d15d6b5
AA
810static irqreturn_t at86rf230_isr(int irq, void *data)
811{
812 struct at86rf230_local *lp = data;
57c1bc7e 813 struct at86rf230_state_change *ctx;
1d15d6b5
AA
814 int rc;
815
90566363 816 disable_irq_nosync(irq);
1d15d6b5 817
57c1bc7e
AA
818 ctx = kzalloc(sizeof(*ctx), GFP_ATOMIC);
819 if (!ctx) {
820 enable_irq(irq);
821 return IRQ_NONE;
822 }
823
824 at86rf230_setup_spi_messages(lp, ctx);
825 /* tell on error handling to free ctx */
826 ctx->free = true;
827
828 ctx->buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
1d15d6b5
AA
829 ctx->msg.complete = at86rf230_irq_status;
830 rc = spi_async(lp->spi, &ctx->msg);
831 if (rc) {
832 at86rf230_async_error(lp, ctx, rc);
57c1bc7e 833 enable_irq(irq);
1d15d6b5
AA
834 return IRQ_NONE;
835 }
836
837 return IRQ_HANDLED;
838}
839
840static void
841at86rf230_write_frame_complete(void *context)
842{
843 struct at86rf230_state_change *ctx = context;
844 struct at86rf230_local *lp = ctx->lp;
1d15d6b5 845
1d15d6b5 846 ctx->trx.len = 2;
d2c8bf51 847
57c1bc7e 848 if (gpio_is_valid(lp->slp_tr))
d2c8bf51 849 at86rf230_slp_tr_rising_edge(lp);
57c1bc7e
AA
850 else
851 at86rf230_async_write_reg(lp, RG_TRX_STATE, STATE_BUSY_TX, ctx,
852 NULL);
1d15d6b5
AA
853}
854
855static void
856at86rf230_write_frame(void *context)
857{
858 struct at86rf230_state_change *ctx = context;
859 struct at86rf230_local *lp = ctx->lp;
860 struct sk_buff *skb = lp->tx_skb;
31fa7434 861 u8 *buf = ctx->buf;
1d15d6b5
AA
862 int rc;
863
1d15d6b5 864 lp->is_tx = 1;
1d15d6b5
AA
865
866 buf[0] = CMD_FB | CMD_WRITE;
867 buf[1] = skb->len + 2;
868 memcpy(buf + 2, skb->data, skb->len);
31fa7434
AA
869 ctx->trx.len = skb->len + 2;
870 ctx->msg.complete = at86rf230_write_frame_complete;
871 rc = spi_async(lp->spi, &ctx->msg);
263be332
AA
872 if (rc) {
873 ctx->trx.len = 2;
1d15d6b5 874 at86rf230_async_error(lp, ctx, rc);
263be332 875 }
1d15d6b5
AA
876}
877
878static void
879at86rf230_xmit_tx_on(void *context)
880{
881 struct at86rf230_state_change *ctx = context;
882 struct at86rf230_local *lp = ctx->lp;
7b8e19b6 883
97fed795 884 at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
57c1bc7e 885 at86rf230_write_frame);
1d15d6b5
AA
886}
887
dce481e6
AA
888static void
889at86rf230_xmit_start(void *context)
1d15d6b5 890{
dce481e6
AA
891 struct at86rf230_state_change *ctx = context;
892 struct at86rf230_local *lp = ctx->lp;
7b8e19b6 893
fc0719e6
AA
894 /* check if we change from off state */
895 if (lp->is_tx_from_off) {
896 lp->is_tx_from_off = false;
897 at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
57c1bc7e 898 at86rf230_write_frame);
85009203 899 } else {
dce481e6 900 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
57c1bc7e 901 at86rf230_xmit_tx_on);
85009203 902 }
dce481e6
AA
903}
904
905static int
906at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
907{
908 struct at86rf230_local *lp = hw->priv;
909 struct at86rf230_state_change *ctx = &lp->tx;
7b8e19b6 910
dce481e6 911 lp->tx_skb = skb;
ba6d2239 912 lp->tx_retry = 0;
dce481e6
AA
913
914 /* After 5 minutes in PLL and the same frequency we run again the
915 * calibration loops which is recommended by at86rf2xx datasheets.
916 *
917 * The calibration is initiate by a state change from TRX_OFF
918 * to TX_ON, the lp->cal_timeout should be reinit by state_delay
919 * function then to start in the next 5 minutes.
920 */
85009203
AA
921 if (time_is_before_jiffies(lp->cal_timeout)) {
922 lp->is_tx_from_off = true;
dce481e6 923 at86rf230_async_state_change(lp, ctx, STATE_TRX_OFF,
57c1bc7e 924 at86rf230_xmit_start);
85009203 925 } else {
dce481e6 926 at86rf230_xmit_start(ctx);
85009203 927 }
97fed795 928
1d15d6b5 929 return 0;
7b8e19b6 930}
931
932static int
5a504397 933at86rf230_ed(struct ieee802154_hw *hw, u8 *level)
7b8e19b6 934{
7b8e19b6 935 BUG_ON(!level);
936 *level = 0xbe;
937 return 0;
938}
939
7b8e19b6 940static int
5a504397 941at86rf230_start(struct ieee802154_hw *hw)
7b8e19b6 942{
e6f7ed9d
AA
943 struct at86rf230_local *lp = hw->priv;
944
493bc90a
AA
945 /* reset trac stats on start */
946 if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS))
947 memset(&lp->trac, 0, sizeof(struct at86rf230_trac));
948
cbe62346 949 at86rf230_awake(lp);
e6f7ed9d
AA
950 enable_irq(lp->spi->irq);
951
30811fa6 952 return at86rf230_sync_state_change(lp, STATE_RX_AACK_ON);
7b8e19b6 953}
954
955static void
5a504397 956at86rf230_stop(struct ieee802154_hw *hw)
7b8e19b6 957{
e6f7ed9d 958 struct at86rf230_local *lp = hw->priv;
74ed9d98 959 u8 csma_seed[2];
e6f7ed9d 960
30811fa6 961 at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
e6f7ed9d
AA
962
963 disable_irq(lp->spi->irq);
74ed9d98
AA
964
965 /* It's recommended to set random new csma_seeds before sleep state.
966 * Makes only sense in the stop callback, not doing this inside of
967 * at86rf230_sleep, this is also used when we don't transmit afterwards
968 * when calling start callback again.
969 */
970 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
971 at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
972 at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
973
cbe62346 974 at86rf230_sleep(lp);
7b8e19b6 975}
976
8fad346f 977static int
e37d2ec8 978at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
8fad346f
PB
979{
980 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
981}
982
2d9fe7ab
AA
983#define AT86RF2XX_MAX_ED_LEVELS 0xF
984static const s32 at86rf23x_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
985 -9100, -8900, -8700, -8500, -8300, -8100, -7900, -7700, -7500, -7300,
986 -7100, -6900, -6700, -6500, -6300, -6100,
987};
988
989static const s32 at86rf212_ed_levels_100[AT86RF2XX_MAX_ED_LEVELS + 1] = {
990 -10000, -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200,
179655fc 991 -8000, -7800, -7600, -7400, -7200, -7000,
2d9fe7ab
AA
992};
993
994static const s32 at86rf212_ed_levels_98[AT86RF2XX_MAX_ED_LEVELS + 1] = {
995 -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000,
179655fc 996 -7800, -7600, -7400, -7200, -7000, -6800,
2d9fe7ab
AA
997};
998
999static inline int
1000at86rf212_update_cca_ed_level(struct at86rf230_local *lp, int rssi_base_val)
1001{
1002 unsigned int cca_ed_thres;
1003 int rc;
1004
1005 rc = at86rf230_read_subreg(lp, SR_CCA_ED_THRES, &cca_ed_thres);
1006 if (rc < 0)
1007 return rc;
1008
1009 switch (rssi_base_val) {
1010 case -98:
1011 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_98;
1012 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_98);
1013 lp->hw->phy->cca_ed_level = at86rf212_ed_levels_98[cca_ed_thres];
1014 break;
1015 case -100:
1016 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
1017 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
1018 lp->hw->phy->cca_ed_level = at86rf212_ed_levels_100[cca_ed_thres];
1019 break;
1020 default:
1021 WARN_ON(1);
1022 }
1023
1024 return 0;
1025}
1026
8fad346f 1027static int
e37d2ec8 1028at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
8fad346f
PB
1029{
1030 int rc;
1031
1032 if (channel == 0)
1033 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
1034 else
1035 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
1036 if (rc < 0)
1037 return rc;
1038
6ca00197 1039 if (page == 0) {
643e53c2 1040 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
a53d1f7c 1041 lp->data->rssi_base_val = -100;
6ca00197 1042 } else {
643e53c2 1043 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
a53d1f7c 1044 lp->data->rssi_base_val = -98;
6ca00197 1045 }
643e53c2
PB
1046 if (rc < 0)
1047 return rc;
1048
2d9fe7ab
AA
1049 rc = at86rf212_update_cca_ed_level(lp, lp->data->rssi_base_val);
1050 if (rc < 0)
1051 return rc;
1052
24ccb9f4
AA
1053 /* This sets the symbol_duration according frequency on the 212.
1054 * TODO move this handling while set channel and page in cfg802154.
1055 * We can do that, this timings are according 802.15.4 standard.
1056 * If we do that in cfg802154, this is a more generic calculation.
1057 *
1058 * This should also protected from ifs_timer. Means cancel timer and
1059 * init with a new value. For now, this is okay.
1060 */
1061 if (channel == 0) {
1062 if (page == 0) {
1063 /* SUB:0 and BPSK:0 -> BPSK-20 */
1064 lp->hw->phy->symbol_duration = 50;
1065 } else {
1066 /* SUB:1 and BPSK:0 -> BPSK-40 */
1067 lp->hw->phy->symbol_duration = 25;
1068 }
1069 } else {
1070 if (page == 0)
2d6dde29 1071 /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */
24ccb9f4
AA
1072 lp->hw->phy->symbol_duration = 40;
1073 else
2d6dde29 1074 /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */
24ccb9f4
AA
1075 lp->hw->phy->symbol_duration = 16;
1076 }
1077
1078 lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD *
1079 lp->hw->phy->symbol_duration;
1080 lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD *
1081 lp->hw->phy->symbol_duration;
1082
8fad346f
PB
1083 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1084}
1085
7b8e19b6 1086static int
e37d2ec8 1087at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
7b8e19b6 1088{
5a504397 1089 struct at86rf230_local *lp = hw->priv;
7b8e19b6 1090 int rc;
1091
a53d1f7c 1092 rc = lp->data->set_channel(lp, page, channel);
984e0c68
AA
1093 /* Wait for PLL */
1094 usleep_range(lp->data->t_channel_switch,
1095 lp->data->t_channel_switch + 10);
dce481e6
AA
1096
1097 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
820bd66f 1098 return rc;
7b8e19b6 1099}
1100
1486774d 1101static int
5a504397 1102at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
1486774d 1103 struct ieee802154_hw_addr_filt *filt,
1104 unsigned long changed)
1105{
5a504397 1106 struct at86rf230_local *lp = hw->priv;
1486774d 1107
57205c14 1108 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
b70ab2e8
PB
1109 u16 addr = le16_to_cpu(filt->short_addr);
1110
1486774d 1111 dev_vdbg(&lp->spi->dev,
e80fb5ee 1112 "at86rf230_set_hw_addr_filt called for saddr\n");
b70ab2e8
PB
1113 __at86rf230_write(lp, RG_SHORT_ADDR_0, addr);
1114 __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8);
1486774d 1115 }
1116
57205c14 1117 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
b70ab2e8
PB
1118 u16 pan = le16_to_cpu(filt->pan_id);
1119
1486774d 1120 dev_vdbg(&lp->spi->dev,
e80fb5ee 1121 "at86rf230_set_hw_addr_filt called for pan id\n");
b70ab2e8
PB
1122 __at86rf230_write(lp, RG_PAN_ID_0, pan);
1123 __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8);
1486774d 1124 }
1125
57205c14 1126 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
b70ab2e8
PB
1127 u8 i, addr[8];
1128
1129 memcpy(addr, &filt->ieee_addr, 8);
1486774d 1130 dev_vdbg(&lp->spi->dev,
e80fb5ee 1131 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
b70ab2e8
PB
1132 for (i = 0; i < 8; i++)
1133 __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]);
1486774d 1134 }
1135
57205c14 1136 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
1486774d 1137 dev_vdbg(&lp->spi->dev,
e80fb5ee 1138 "at86rf230_set_hw_addr_filt called for panc change\n");
1486774d 1139 if (filt->pan_coord)
1140 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
1141 else
1142 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
1143 }
1144
1145 return 0;
1146}
1147
6f4da3f8
AA
1148#define AT86RF23X_MAX_TX_POWERS 0xF
1149static const s32 at86rf233_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
1150 400, 370, 340, 300, 250, 200, 100, 0, -100, -200, -300, -400, -600,
1151 -800, -1200, -1700,
1152};
1153
1154static const s32 at86rf231_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
1155 300, 280, 230, 180, 130, 70, 0, -100, -200, -300, -400, -500, -700,
1156 -900, -1200, -1700,
1157};
1158
1159#define AT86RF212_MAX_TX_POWERS 0x1F
1160static const s32 at86rf212_powers[AT86RF212_MAX_TX_POWERS + 1] = {
1161 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
1162 -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
1163 -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
1164};
1165
9b2777d6 1166static int
6f4da3f8 1167at86rf23x_set_txpower(struct at86rf230_local *lp, s32 mbm)
9b2777d6 1168{
6f4da3f8 1169 u32 i;
9b2777d6 1170
6f4da3f8
AA
1171 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
1172 if (lp->hw->phy->supported.tx_powers[i] == mbm)
1173 return at86rf230_write_subreg(lp, SR_TX_PWR_23X, i);
1174 }
1175
1176 return -EINVAL;
1177}
1178
1179static int
1180at86rf212_set_txpower(struct at86rf230_local *lp, s32 mbm)
1181{
1182 u32 i;
1183
1184 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
1185 if (lp->hw->phy->supported.tx_powers[i] == mbm)
1186 return at86rf230_write_subreg(lp, SR_TX_PWR_212, i);
1187 }
9b2777d6 1188
6f4da3f8
AA
1189 return -EINVAL;
1190}
1191
1192static int
1193at86rf230_set_txpower(struct ieee802154_hw *hw, s32 mbm)
1194{
1195 struct at86rf230_local *lp = hw->priv;
9b2777d6 1196
6f4da3f8 1197 return lp->data->set_txpower(lp, mbm);
9b2777d6
PB
1198}
1199
84dda3c6 1200static int
5a504397 1201at86rf230_set_lbt(struct ieee802154_hw *hw, bool on)
84dda3c6 1202{
5a504397 1203 struct at86rf230_local *lp = hw->priv;
84dda3c6
PB
1204
1205 return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
1206}
1207
ba08fea5 1208static int
7fe9a388
AA
1209at86rf230_set_cca_mode(struct ieee802154_hw *hw,
1210 const struct wpan_phy_cca *cca)
ba08fea5 1211{
5a504397 1212 struct at86rf230_local *lp = hw->priv;
7fe9a388 1213 u8 val;
ba08fea5 1214
7fe9a388
AA
1215 /* mapping 802.15.4 to driver spec */
1216 switch (cca->mode) {
1217 case NL802154_CCA_ENERGY:
1218 val = 1;
1219 break;
1220 case NL802154_CCA_CARRIER:
1221 val = 2;
1222 break;
1223 case NL802154_CCA_ENERGY_CARRIER:
1224 switch (cca->opt) {
1225 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
1226 val = 3;
1227 break;
1228 case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
1229 val = 0;
1230 break;
1231 default:
1232 return -EINVAL;
1233 }
1234 break;
1235 default:
1236 return -EINVAL;
1237 }
1238
1239 return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
ba08fea5
PB
1240}
1241
a7d7eda9 1242
6ca00197 1243static int
32b23550 1244at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
6ca00197 1245{
5a504397 1246 struct at86rf230_local *lp = hw->priv;
2d9fe7ab 1247 u32 i;
6ca00197 1248
2d9fe7ab
AA
1249 for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
1250 if (hw->phy->supported.cca_ed_levels[i] == mbm)
1251 return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, i);
1252 }
6ca00197 1253
2d9fe7ab 1254 return -EINVAL;
6ca00197
PB
1255}
1256
f2fdd67c 1257static int
5a504397 1258at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
f2fdd67c
PB
1259 u8 retries)
1260{
5a504397 1261 struct at86rf230_local *lp = hw->priv;
f2fdd67c
PB
1262 int rc;
1263
f2fdd67c
PB
1264 rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
1265 if (rc)
1266 return rc;
1267
1268 rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
1269 if (rc)
1270 return rc;
1271
39d7f320 1272 return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries);
f2fdd67c
PB
1273}
1274
1275static int
5a504397 1276at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
f2fdd67c 1277{
5a504397 1278 struct at86rf230_local *lp = hw->priv;
f2fdd67c 1279
fc0719e6 1280 return at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
f2fdd67c
PB
1281}
1282
92f45f54
AA
1283static int
1284at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
1285{
1286 struct at86rf230_local *lp = hw->priv;
1287 int rc;
1288
1289 if (on) {
1290 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1);
1291 if (rc < 0)
1292 return rc;
1293
1294 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1);
1295 if (rc < 0)
1296 return rc;
1297 } else {
1298 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0);
1299 if (rc < 0)
1300 return rc;
1301
1302 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0);
1303 if (rc < 0)
1304 return rc;
1305 }
1306
1307 return 0;
1308}
1309
16301861 1310static const struct ieee802154_ops at86rf230_ops = {
7b8e19b6 1311 .owner = THIS_MODULE,
955aee8b 1312 .xmit_async = at86rf230_xmit,
7b8e19b6 1313 .ed = at86rf230_ed,
1314 .set_channel = at86rf230_channel,
1315 .start = at86rf230_start,
1316 .stop = at86rf230_stop,
1486774d 1317 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
640985ec
AA
1318 .set_txpower = at86rf230_set_txpower,
1319 .set_lbt = at86rf230_set_lbt,
1320 .set_cca_mode = at86rf230_set_cca_mode,
1321 .set_cca_ed_level = at86rf230_set_cca_ed_level,
1322 .set_csma_params = at86rf230_set_csma_params,
1323 .set_frame_retries = at86rf230_set_frame_retries,
92f45f54 1324 .set_promiscuous_mode = at86rf230_set_promiscuous_mode,
8fad346f
PB
1325};
1326
a53d1f7c 1327static struct at86rf2xx_chip_data at86rf233_data = {
7a4ef918 1328 .t_sleep_cycle = 330,
984e0c68 1329 .t_channel_switch = 11,
09e536cd 1330 .t_reset_to_off = 26,
2e0571c0
AA
1331 .t_off_to_aack = 80,
1332 .t_off_to_tx_on = 80,
e6f7ed9d
AA
1333 .t_off_to_sleep = 35,
1334 .t_sleep_to_off = 210,
1d15d6b5
AA
1335 .t_frame = 4096,
1336 .t_p_ack = 545,
a53d1f7c
AA
1337 .rssi_base_val = -91,
1338 .set_channel = at86rf23x_set_channel,
6f4da3f8 1339 .set_txpower = at86rf23x_set_txpower,
a53d1f7c
AA
1340};
1341
1342static struct at86rf2xx_chip_data at86rf231_data = {
7a4ef918 1343 .t_sleep_cycle = 330,
984e0c68 1344 .t_channel_switch = 24,
09e536cd 1345 .t_reset_to_off = 37,
2e0571c0
AA
1346 .t_off_to_aack = 110,
1347 .t_off_to_tx_on = 110,
e6f7ed9d
AA
1348 .t_off_to_sleep = 35,
1349 .t_sleep_to_off = 380,
1d15d6b5
AA
1350 .t_frame = 4096,
1351 .t_p_ack = 545,
a53d1f7c
AA
1352 .rssi_base_val = -91,
1353 .set_channel = at86rf23x_set_channel,
6f4da3f8 1354 .set_txpower = at86rf23x_set_txpower,
a53d1f7c
AA
1355};
1356
1357static struct at86rf2xx_chip_data at86rf212_data = {
7a4ef918 1358 .t_sleep_cycle = 330,
984e0c68 1359 .t_channel_switch = 11,
09e536cd 1360 .t_reset_to_off = 26,
2e0571c0
AA
1361 .t_off_to_aack = 200,
1362 .t_off_to_tx_on = 200,
e6f7ed9d
AA
1363 .t_off_to_sleep = 35,
1364 .t_sleep_to_off = 380,
1d15d6b5
AA
1365 .t_frame = 4096,
1366 .t_p_ack = 545,
a53d1f7c
AA
1367 .rssi_base_val = -100,
1368 .set_channel = at86rf212_set_channel,
6f4da3f8 1369 .set_txpower = at86rf212_set_txpower,
a53d1f7c
AA
1370};
1371
ccdaeb2b 1372static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
7b8e19b6 1373{
1db0558e 1374 int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH;
f76014f7 1375 unsigned int dvdd;
f2fdd67c 1376 u8 csma_seed[2];
7b8e19b6 1377
09e536cd 1378 rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
7dcbd22a
PB
1379 if (rc)
1380 return rc;
7b8e19b6 1381
4af619ae 1382 irq_type = irq_get_trigger_type(lp->spi->irq);
702d211c
AA
1383 if (irq_type == IRQ_TYPE_EDGE_FALLING ||
1384 irq_type == IRQ_TYPE_LEVEL_LOW)
43b5abe0 1385 irq_pol = IRQ_ACTIVE_LOW;
43b5abe0 1386
18c65049 1387 rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol);
43b5abe0
SH
1388 if (rc)
1389 return rc;
1390
6bd2b132
AA
1391 rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
1392 if (rc)
1393 return rc;
1394
057dad6f 1395 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
7b8e19b6 1396 if (rc)
1397 return rc;
1398
be64f076
AA
1399 /* reset values differs in at86rf231 and at86rf233 */
1400 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0);
1401 if (rc)
1402 return rc;
1403
f2fdd67c
PB
1404 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
1405 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
1406 if (rc)
1407 return rc;
1408 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
1409 if (rc)
1410 return rc;
1411
7b8e19b6 1412 /* CLKM changes are applied immediately */
1413 rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
1414 if (rc)
1415 return rc;
1416
1417 /* Turn CLKM Off */
1418 rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
1419 if (rc)
1420 return rc;
1421 /* Wait the next SLEEP cycle */
7a4ef918
AA
1422 usleep_range(lp->data->t_sleep_cycle,
1423 lp->data->t_sleep_cycle + 100);
7b8e19b6 1424
ccdaeb2b
AA
1425 /* xtal_trim value is calculated by:
1426 * CL = 0.5 * (CX + CTRIM + CPAR)
1427 *
1428 * whereas:
1429 * CL = capacitor of used crystal
1430 * CX = connected capacitors at xtal pins
1431 * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF,
1432 * but this is different on each board setup. You need to fine
1433 * tuning this value via CTRIM.
1434 * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is
1435 * 0 pF upto 4.5 pF.
1436 *
1437 * Examples:
1438 * atben transceiver:
1439 *
1440 * CL = 8 pF
1441 * CX = 12 pF
1442 * CPAR = 3 pF (We assume the magic constant from datasheet)
1443 * CTRIM = 0.9 pF
1444 *
1445 * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF
1446 *
1447 * xtal_trim = 0x3
1448 *
1449 * openlabs transceiver:
1450 *
1451 * CL = 16 pF
1452 * CX = 22 pF
1453 * CPAR = 3 pF (We assume the magic constant from datasheet)
1454 * CTRIM = 4.5 pF
1455 *
1456 * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF
1457 *
1458 * xtal_trim = 0xf
1459 */
1460 rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim);
1461 if (rc)
1462 return rc;
1463
1cc9fc53 1464 rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd);
7b8e19b6 1465 if (rc)
1466 return rc;
1cc9fc53 1467 if (!dvdd) {
7b8e19b6 1468 dev_err(&lp->spi->dev, "DVDD error\n");
1469 return -EINVAL;
1470 }
1471
05e3f2f3
AA
1472 /* Force setting slotted operation bit to 0. Sometimes the atben
1473 * sets this bit and I don't know why. We set this always force
1474 * to zero while probing.
1475 */
6cc6399c 1476 return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0);
7b8e19b6 1477}
1478
aaa1c4d2 1479static int
ccdaeb2b
AA
1480at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr,
1481 u8 *xtal_trim)
fa2d3e94 1482{
aaa1c4d2 1483 struct at86rf230_platform_data *pdata = spi->dev.platform_data;
ccdaeb2b 1484 int ret;
fa2d3e94 1485
aaa1c4d2
AA
1486 if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) {
1487 if (!pdata)
1488 return -ENOENT;
fa2d3e94 1489
aaa1c4d2
AA
1490 *rstn = pdata->rstn;
1491 *slp_tr = pdata->slp_tr;
ccdaeb2b 1492 *xtal_trim = pdata->xtal_trim;
aaa1c4d2
AA
1493 return 0;
1494 }
fa2d3e94 1495
aaa1c4d2
AA
1496 *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0);
1497 *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0);
ccdaeb2b
AA
1498 ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim);
1499 if (ret < 0 && ret != -EINVAL)
1500 return ret;
fa2d3e94 1501
aaa1c4d2 1502 return 0;
fa2d3e94
AA
1503}
1504
c8ee0f56
AA
1505static int
1506at86rf230_detect_device(struct at86rf230_local *lp)
1507{
1508 unsigned int part, version, val;
1509 u16 man_id = 0;
1510 const char *chip;
1511 int rc;
1512
1513 rc = __at86rf230_read(lp, RG_MAN_ID_0, &val);
1514 if (rc)
1515 return rc;
1516 man_id |= val;
1517
1518 rc = __at86rf230_read(lp, RG_MAN_ID_1, &val);
1519 if (rc)
1520 return rc;
1521 man_id |= (val << 8);
1522
1523 rc = __at86rf230_read(lp, RG_PART_NUM, &part);
1524 if (rc)
1525 return rc;
1526
7598968d 1527 rc = __at86rf230_read(lp, RG_VERSION_NUM, &version);
c8ee0f56
AA
1528 if (rc)
1529 return rc;
1530
1531 if (man_id != 0x001f) {
1532 dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1533 man_id >> 8, man_id & 0xFF);
1534 return -EINVAL;
1535 }
1536
f265be3d 1537 lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM |
edea8f7c
AA
1538 IEEE802154_HW_CSMA_PARAMS |
1539 IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
1540 IEEE802154_HW_PROMISCUOUS;
1541
1542 lp->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
1543 WPAN_PHY_FLAG_CCA_ED_LEVEL |
1544 WPAN_PHY_FLAG_CCA_MODE;
c8ee0f56 1545
8377d22c
AA
1546 lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1547 BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
1548 lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
1549 BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
1550
2d9fe7ab
AA
1551 lp->hw->phy->supported.cca_ed_levels = at86rf23x_ed_levels;
1552 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf23x_ed_levels);
1553
b48a7c18
AA
1554 lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
1555
c8ee0f56
AA
1556 switch (part) {
1557 case 2:
1558 chip = "at86rf230";
1559 rc = -ENOTSUPP;
cc643496 1560 goto not_supp;
c8ee0f56
AA
1561 case 3:
1562 chip = "at86rf231";
a53d1f7c 1563 lp->data = &at86rf231_data;
72f655e4 1564 lp->hw->phy->supported.channels[0] = 0x7FFF800;
fe58d016 1565 lp->hw->phy->current_channel = 11;
24ccb9f4 1566 lp->hw->phy->symbol_duration = 16;
6f4da3f8
AA
1567 lp->hw->phy->supported.tx_powers = at86rf231_powers;
1568 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf231_powers);
c8ee0f56
AA
1569 break;
1570 case 7:
1571 chip = "at86rf212";
4ecc8a55
AY
1572 lp->data = &at86rf212_data;
1573 lp->hw->flags |= IEEE802154_HW_LBT;
72f655e4
AA
1574 lp->hw->phy->supported.channels[0] = 0x00007FF;
1575 lp->hw->phy->supported.channels[2] = 0x00007FF;
4ecc8a55
AY
1576 lp->hw->phy->current_channel = 5;
1577 lp->hw->phy->symbol_duration = 25;
8377d22c 1578 lp->hw->phy->supported.lbt = NL802154_SUPPORTED_BOOL_BOTH;
6f4da3f8
AA
1579 lp->hw->phy->supported.tx_powers = at86rf212_powers;
1580 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf212_powers);
2d9fe7ab
AA
1581 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
1582 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
c8ee0f56
AA
1583 break;
1584 case 11:
1585 chip = "at86rf233";
a53d1f7c 1586 lp->data = &at86rf233_data;
72f655e4 1587 lp->hw->phy->supported.channels[0] = 0x7FFF800;
fe58d016 1588 lp->hw->phy->current_channel = 13;
24ccb9f4 1589 lp->hw->phy->symbol_duration = 16;
6f4da3f8
AA
1590 lp->hw->phy->supported.tx_powers = at86rf233_powers;
1591 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf233_powers);
c8ee0f56
AA
1592 break;
1593 default:
2b8b7e29 1594 chip = "unknown";
c8ee0f56 1595 rc = -ENOTSUPP;
cc643496 1596 goto not_supp;
c8ee0f56
AA
1597 }
1598
cc643496 1599 lp->hw->phy->cca_ed_level = lp->hw->phy->supported.cca_ed_levels[7];
392f4e67 1600 lp->hw->phy->transmit_power = lp->hw->phy->supported.tx_powers[0];
cc643496
AA
1601
1602not_supp:
c8ee0f56
AA
1603 dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
1604
1605 return rc;
1606}
1607
493bc90a
AA
1608#ifdef CONFIG_IEEE802154_AT86RF230_DEBUGFS
1609static struct dentry *at86rf230_debugfs_root;
1610
1611static int at86rf230_stats_show(struct seq_file *file, void *offset)
1612{
1613 struct at86rf230_local *lp = file->private;
493bc90a 1614
97170ea1
SR
1615 seq_printf(file, "SUCCESS:\t\t%8llu\n", lp->trac.success);
1616 seq_printf(file, "SUCCESS_DATA_PENDING:\t%8llu\n",
1617 lp->trac.success_data_pending);
1618 seq_printf(file, "SUCCESS_WAIT_FOR_ACK:\t%8llu\n",
1619 lp->trac.success_wait_for_ack);
1620 seq_printf(file, "CHANNEL_ACCESS_FAILURE:\t%8llu\n",
1621 lp->trac.channel_access_failure);
1622 seq_printf(file, "NO_ACK:\t\t\t%8llu\n", lp->trac.no_ack);
1623 seq_printf(file, "INVALID:\t\t%8llu\n", lp->trac.invalid);
1624 return 0;
493bc90a
AA
1625}
1626
1627static int at86rf230_stats_open(struct inode *inode, struct file *file)
1628{
1629 return single_open(file, at86rf230_stats_show, inode->i_private);
1630}
1631
1632static const struct file_operations at86rf230_stats_fops = {
1633 .open = at86rf230_stats_open,
1634 .read = seq_read,
1635 .llseek = seq_lseek,
1636 .release = single_release,
1637};
1638
1639static int at86rf230_debugfs_init(struct at86rf230_local *lp)
1640{
1641 char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "at86rf230-";
1642 struct dentry *stats;
1643
1644 strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN);
1645
1646 at86rf230_debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1647 if (!at86rf230_debugfs_root)
1648 return -ENOMEM;
1649
1650 stats = debugfs_create_file("trac_stats", S_IRUGO,
1651 at86rf230_debugfs_root, lp,
1652 &at86rf230_stats_fops);
1653 if (!stats)
1654 return -ENOMEM;
1655
1656 return 0;
1657}
1658
1659static void at86rf230_debugfs_remove(void)
1660{
1661 debugfs_remove_recursive(at86rf230_debugfs_root);
1662}
1663#else
1664static int at86rf230_debugfs_init(struct at86rf230_local *lp) { return 0; }
1665static void at86rf230_debugfs_remove(void) { }
1666#endif
1667
bb1f4606 1668static int at86rf230_probe(struct spi_device *spi)
7b8e19b6 1669{
5a504397 1670 struct ieee802154_hw *hw;
7b8e19b6 1671 struct at86rf230_local *lp;
f76014f7 1672 unsigned int status;
aaa1c4d2 1673 int rc, irq_type, rstn, slp_tr;
e3721749 1674 u8 xtal_trim = 0;
7b8e19b6 1675
1676 if (!spi->irq) {
1677 dev_err(&spi->dev, "no IRQ specified\n");
1678 return -EINVAL;
1679 }
1680
ccdaeb2b 1681 rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim);
aaa1c4d2
AA
1682 if (rc < 0) {
1683 dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc);
1684 return rc;
43b5abe0
SH
1685 }
1686
aaa1c4d2
AA
1687 if (gpio_is_valid(rstn)) {
1688 rc = devm_gpio_request_one(&spi->dev, rstn,
0679e29b 1689 GPIOF_OUT_INIT_HIGH, "rstn");
3fa27571
AA
1690 if (rc)
1691 return rc;
1692 }
7b8e19b6 1693
aaa1c4d2
AA
1694 if (gpio_is_valid(slp_tr)) {
1695 rc = devm_gpio_request_one(&spi->dev, slp_tr,
0679e29b 1696 GPIOF_OUT_INIT_LOW, "slp_tr");
7b8e19b6 1697 if (rc)
0679e29b 1698 return rc;
7b8e19b6 1699 }
1700
1701 /* Reset */
aaa1c4d2 1702 if (gpio_is_valid(rstn)) {
3fa27571 1703 udelay(1);
aaa1c4d2 1704 gpio_set_value(rstn, 0);
3fa27571 1705 udelay(1);
aaa1c4d2 1706 gpio_set_value(rstn, 1);
3fa27571
AA
1707 usleep_range(120, 240);
1708 }
7b8e19b6 1709
5a504397
AA
1710 hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops);
1711 if (!hw)
640985ec
AA
1712 return -ENOMEM;
1713
5a504397
AA
1714 lp = hw->priv;
1715 lp->hw = hw;
640985ec 1716 lp->spi = spi;
d2c8bf51 1717 lp->slp_tr = slp_tr;
5a504397 1718 hw->parent = &spi->dev;
f6f4e86a 1719 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
8fad346f 1720
f76014f7
AA
1721 lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config);
1722 if (IS_ERR(lp->regmap)) {
1723 rc = PTR_ERR(lp->regmap);
1724 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1725 rc);
1726 goto free_dev;
1727 }
1728
57c1bc7e
AA
1729 at86rf230_setup_spi_messages(lp, &lp->state);
1730 at86rf230_setup_spi_messages(lp, &lp->tx);
1d15d6b5 1731
c8ee0f56
AA
1732 rc = at86rf230_detect_device(lp);
1733 if (rc < 0)
1734 goto free_dev;
1735
2e0571c0 1736 init_completion(&lp->state_complete);
8fad346f
PB
1737
1738 spi_set_drvdata(spi, lp);
1739
ccdaeb2b 1740 rc = at86rf230_hw_init(lp, xtal_trim);
7b8e19b6 1741 if (rc)
1d15d6b5 1742 goto free_dev;
7b8e19b6 1743
19626946
AA
1744 /* Read irq status register to reset irq line */
1745 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
7b8e19b6 1746 if (rc)
1d15d6b5 1747 goto free_dev;
7b8e19b6 1748
1d15d6b5
AA
1749 irq_type = irq_get_trigger_type(spi->irq);
1750 if (!irq_type)
9ff19e6f 1751 irq_type = IRQF_TRIGGER_HIGH;
1d15d6b5
AA
1752
1753 rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr,
1754 IRQF_SHARED | irq_type, dev_name(&spi->dev), lp);
057dad6f 1755 if (rc)
1d15d6b5 1756 goto free_dev;
057dad6f 1757
e6f7ed9d
AA
1758 /* disable_irq by default and wait for starting hardware */
1759 disable_irq(spi->irq);
1760
1761 /* going into sleep by default */
cbe62346 1762 at86rf230_sleep(lp);
e6f7ed9d 1763
493bc90a 1764 rc = at86rf230_debugfs_init(lp);
7b8e19b6 1765 if (rc)
1d15d6b5 1766 goto free_dev;
7b8e19b6 1767
493bc90a
AA
1768 rc = ieee802154_register_hw(lp->hw);
1769 if (rc)
1770 goto free_debugfs;
1771
7b8e19b6 1772 return rc;
1773
493bc90a
AA
1774free_debugfs:
1775 at86rf230_debugfs_remove();
640985ec 1776free_dev:
5a504397 1777 ieee802154_free_hw(lp->hw);
8fad346f 1778
7b8e19b6 1779 return rc;
1780}
1781
bb1f4606 1782static int at86rf230_remove(struct spi_device *spi)
7b8e19b6 1783{
1784 struct at86rf230_local *lp = spi_get_drvdata(spi);
1785
17e84a92
AA
1786 /* mask all at86rf230 irq's */
1787 at86rf230_write_subreg(lp, SR_IRQ_MASK, 0);
5a504397
AA
1788 ieee802154_unregister_hw(lp->hw);
1789 ieee802154_free_hw(lp->hw);
493bc90a 1790 at86rf230_debugfs_remove();
7b8e19b6 1791 dev_dbg(&spi->dev, "unregistered at86rf230\n");
0679e29b 1792
7b8e19b6 1793 return 0;
1794}
1795
1086b4f6 1796static const struct of_device_id at86rf230_of_match[] = {
fa2d3e94
AA
1797 { .compatible = "atmel,at86rf230", },
1798 { .compatible = "atmel,at86rf231", },
1799 { .compatible = "atmel,at86rf233", },
1800 { .compatible = "atmel,at86rf212", },
1801 { },
1802};
835cb7d2 1803MODULE_DEVICE_TABLE(of, at86rf230_of_match);
fa2d3e94 1804
90b15520
AA
1805static const struct spi_device_id at86rf230_device_id[] = {
1806 { .name = "at86rf230", },
1807 { .name = "at86rf231", },
1808 { .name = "at86rf233", },
1809 { .name = "at86rf212", },
1810 { },
1811};
1812MODULE_DEVICE_TABLE(spi, at86rf230_device_id);
1813
7b8e19b6 1814static struct spi_driver at86rf230_driver = {
90b15520 1815 .id_table = at86rf230_device_id,
7b8e19b6 1816 .driver = {
fa2d3e94 1817 .of_match_table = of_match_ptr(at86rf230_of_match),
7b8e19b6 1818 .name = "at86rf230",
7b8e19b6 1819 },
1820 .probe = at86rf230_probe,
bb1f4606 1821 .remove = at86rf230_remove,
7b8e19b6 1822};
1823
395a5738 1824module_spi_driver(at86rf230_driver);
7b8e19b6 1825
1826MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1827MODULE_LICENSE("GPL v2");
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