Commit | Line | Data |
---|---|---|
7b8e19b6 | 1 | /* |
2 | * AT86RF230/RF231 driver | |
3 | * | |
4 | * Copyright (C) 2009-2012 Siemens AG | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | * | |
19 | * Written by: | |
20 | * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> | |
21 | * Alexander Smirnov <alex.bluesman.smirnov@gmail.com> | |
01ebd60b | 22 | * Alexander Aring <aar@pengutronix.de> |
7b8e19b6 | 23 | */ |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/interrupt.h> | |
4af619ae | 27 | #include <linux/irq.h> |
7b8e19b6 | 28 | #include <linux/gpio.h> |
29 | #include <linux/delay.h> | |
7b8e19b6 | 30 | #include <linux/spinlock.h> |
31 | #include <linux/spi/spi.h> | |
32 | #include <linux/spi/at86rf230.h> | |
f76014f7 | 33 | #include <linux/regmap.h> |
7b8e19b6 | 34 | #include <linux/skbuff.h> |
fa2d3e94 | 35 | #include <linux/of_gpio.h> |
7b8e19b6 | 36 | |
1d15d6b5 | 37 | #include <net/ieee802154.h> |
7b8e19b6 | 38 | #include <net/mac802154.h> |
39 | #include <net/wpan-phy.h> | |
40 | ||
a53d1f7c AA |
41 | struct at86rf230_local; |
42 | /* at86rf2xx chip depend data. | |
43 | * All timings are in us. | |
44 | */ | |
45 | struct at86rf2xx_chip_data { | |
7a4ef918 | 46 | u16 t_sleep_cycle; |
984e0c68 | 47 | u16 t_channel_switch; |
09e536cd | 48 | u16 t_reset_to_off; |
2e0571c0 AA |
49 | u16 t_off_to_aack; |
50 | u16 t_off_to_tx_on; | |
1d15d6b5 AA |
51 | u16 t_frame; |
52 | u16 t_p_ack; | |
53 | /* short interframe spacing time */ | |
54 | u16 t_sifs; | |
55 | /* long interframe spacing time */ | |
56 | u16 t_lifs; | |
57 | /* completion timeout for tx in msecs */ | |
58 | u16 t_tx_timeout; | |
a53d1f7c AA |
59 | int rssi_base_val; |
60 | ||
61 | int (*set_channel)(struct at86rf230_local *, int, int); | |
a7d7eda9 | 62 | int (*get_desense_steps)(struct at86rf230_local *, s32); |
a53d1f7c AA |
63 | }; |
64 | ||
1d15d6b5 | 65 | #define AT86RF2XX_MAX_BUF (127 + 3) |
7b8e19b6 | 66 | |
1d15d6b5 AA |
67 | struct at86rf230_state_change { |
68 | struct at86rf230_local *lp; | |
7b8e19b6 | 69 | |
1d15d6b5 AA |
70 | struct spi_message msg; |
71 | struct spi_transfer trx; | |
72 | u8 buf[AT86RF2XX_MAX_BUF]; | |
73 | ||
74 | void (*complete)(void *context); | |
75 | u8 from_state; | |
76 | u8 to_state; | |
77 | }; | |
78 | ||
79 | struct at86rf230_local { | |
80 | struct spi_device *spi; | |
7b8e19b6 | 81 | |
82 | struct ieee802154_dev *dev; | |
1d15d6b5 | 83 | struct at86rf2xx_chip_data *data; |
f76014f7 | 84 | struct regmap *regmap; |
7b8e19b6 | 85 | |
2e0571c0 AA |
86 | struct completion state_complete; |
87 | struct at86rf230_state_change state; | |
88 | ||
1d15d6b5 | 89 | struct at86rf230_state_change irq; |
6ca00197 | 90 | |
a53d1f7c | 91 | bool tx_aret; |
850f43ac | 92 | s8 max_frame_retries; |
1d15d6b5 AA |
93 | bool is_tx; |
94 | /* spinlock for is_tx protection */ | |
95 | spinlock_t lock; | |
96 | struct completion tx_complete; | |
97 | struct sk_buff *tx_skb; | |
98 | struct at86rf230_state_change tx; | |
7b8e19b6 | 99 | }; |
100 | ||
101 | #define RG_TRX_STATUS (0x01) | |
102 | #define SR_TRX_STATUS 0x01, 0x1f, 0 | |
103 | #define SR_RESERVED_01_3 0x01, 0x20, 5 | |
104 | #define SR_CCA_STATUS 0x01, 0x40, 6 | |
105 | #define SR_CCA_DONE 0x01, 0x80, 7 | |
106 | #define RG_TRX_STATE (0x02) | |
107 | #define SR_TRX_CMD 0x02, 0x1f, 0 | |
108 | #define SR_TRAC_STATUS 0x02, 0xe0, 5 | |
109 | #define RG_TRX_CTRL_0 (0x03) | |
110 | #define SR_CLKM_CTRL 0x03, 0x07, 0 | |
111 | #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 | |
112 | #define SR_PAD_IO_CLKM 0x03, 0x30, 4 | |
113 | #define SR_PAD_IO 0x03, 0xc0, 6 | |
114 | #define RG_TRX_CTRL_1 (0x04) | |
115 | #define SR_IRQ_POLARITY 0x04, 0x01, 0 | |
116 | #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 | |
117 | #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 | |
118 | #define SR_RX_BL_CTRL 0x04, 0x10, 4 | |
119 | #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 | |
120 | #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 | |
121 | #define SR_PA_EXT_EN 0x04, 0x80, 7 | |
122 | #define RG_PHY_TX_PWR (0x05) | |
123 | #define SR_TX_PWR 0x05, 0x0f, 0 | |
124 | #define SR_PA_LT 0x05, 0x30, 4 | |
125 | #define SR_PA_BUF_LT 0x05, 0xc0, 6 | |
126 | #define RG_PHY_RSSI (0x06) | |
127 | #define SR_RSSI 0x06, 0x1f, 0 | |
128 | #define SR_RND_VALUE 0x06, 0x60, 5 | |
129 | #define SR_RX_CRC_VALID 0x06, 0x80, 7 | |
130 | #define RG_PHY_ED_LEVEL (0x07) | |
131 | #define SR_ED_LEVEL 0x07, 0xff, 0 | |
132 | #define RG_PHY_CC_CCA (0x08) | |
133 | #define SR_CHANNEL 0x08, 0x1f, 0 | |
134 | #define SR_CCA_MODE 0x08, 0x60, 5 | |
135 | #define SR_CCA_REQUEST 0x08, 0x80, 7 | |
136 | #define RG_CCA_THRES (0x09) | |
137 | #define SR_CCA_ED_THRES 0x09, 0x0f, 0 | |
138 | #define SR_RESERVED_09_1 0x09, 0xf0, 4 | |
139 | #define RG_RX_CTRL (0x0a) | |
140 | #define SR_PDT_THRES 0x0a, 0x0f, 0 | |
141 | #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 | |
142 | #define RG_SFD_VALUE (0x0b) | |
143 | #define SR_SFD_VALUE 0x0b, 0xff, 0 | |
144 | #define RG_TRX_CTRL_2 (0x0c) | |
145 | #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 | |
8fad346f PB |
146 | #define SR_SUB_MODE 0x0c, 0x04, 2 |
147 | #define SR_BPSK_QPSK 0x0c, 0x08, 3 | |
643e53c2 PB |
148 | #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 |
149 | #define SR_RESERVED_0c_5 0x0c, 0x60, 5 | |
7b8e19b6 | 150 | #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 |
151 | #define RG_ANT_DIV (0x0d) | |
152 | #define SR_ANT_CTRL 0x0d, 0x03, 0 | |
153 | #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 | |
154 | #define SR_ANT_DIV_EN 0x0d, 0x08, 3 | |
155 | #define SR_RESERVED_0d_2 0x0d, 0x70, 4 | |
156 | #define SR_ANT_SEL 0x0d, 0x80, 7 | |
157 | #define RG_IRQ_MASK (0x0e) | |
158 | #define SR_IRQ_MASK 0x0e, 0xff, 0 | |
159 | #define RG_IRQ_STATUS (0x0f) | |
160 | #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 | |
161 | #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 | |
162 | #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 | |
163 | #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 | |
164 | #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 | |
165 | #define SR_IRQ_5_AMI 0x0f, 0x20, 5 | |
166 | #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 | |
167 | #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 | |
168 | #define RG_VREG_CTRL (0x10) | |
169 | #define SR_RESERVED_10_6 0x10, 0x03, 0 | |
170 | #define SR_DVDD_OK 0x10, 0x04, 2 | |
171 | #define SR_DVREG_EXT 0x10, 0x08, 3 | |
172 | #define SR_RESERVED_10_3 0x10, 0x30, 4 | |
173 | #define SR_AVDD_OK 0x10, 0x40, 6 | |
174 | #define SR_AVREG_EXT 0x10, 0x80, 7 | |
175 | #define RG_BATMON (0x11) | |
176 | #define SR_BATMON_VTH 0x11, 0x0f, 0 | |
177 | #define SR_BATMON_HR 0x11, 0x10, 4 | |
178 | #define SR_BATMON_OK 0x11, 0x20, 5 | |
179 | #define SR_RESERVED_11_1 0x11, 0xc0, 6 | |
180 | #define RG_XOSC_CTRL (0x12) | |
181 | #define SR_XTAL_TRIM 0x12, 0x0f, 0 | |
182 | #define SR_XTAL_MODE 0x12, 0xf0, 4 | |
183 | #define RG_RX_SYN (0x15) | |
184 | #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 | |
185 | #define SR_RESERVED_15_2 0x15, 0x70, 4 | |
186 | #define SR_RX_PDT_DIS 0x15, 0x80, 7 | |
187 | #define RG_XAH_CTRL_1 (0x17) | |
188 | #define SR_RESERVED_17_8 0x17, 0x01, 0 | |
189 | #define SR_AACK_PROM_MODE 0x17, 0x02, 1 | |
190 | #define SR_AACK_ACK_TIME 0x17, 0x04, 2 | |
191 | #define SR_RESERVED_17_5 0x17, 0x08, 3 | |
192 | #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 | |
193 | #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 | |
84dda3c6 | 194 | #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
7b8e19b6 | 195 | #define SR_RESERVED_17_1 0x17, 0x80, 7 |
196 | #define RG_FTN_CTRL (0x18) | |
197 | #define SR_RESERVED_18_2 0x18, 0x7f, 0 | |
198 | #define SR_FTN_START 0x18, 0x80, 7 | |
199 | #define RG_PLL_CF (0x1a) | |
200 | #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 | |
201 | #define SR_PLL_CF_START 0x1a, 0x80, 7 | |
202 | #define RG_PLL_DCU (0x1b) | |
203 | #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 | |
204 | #define SR_RESERVED_1b_2 0x1b, 0x40, 6 | |
205 | #define SR_PLL_DCU_START 0x1b, 0x80, 7 | |
206 | #define RG_PART_NUM (0x1c) | |
207 | #define SR_PART_NUM 0x1c, 0xff, 0 | |
208 | #define RG_VERSION_NUM (0x1d) | |
209 | #define SR_VERSION_NUM 0x1d, 0xff, 0 | |
210 | #define RG_MAN_ID_0 (0x1e) | |
211 | #define SR_MAN_ID_0 0x1e, 0xff, 0 | |
212 | #define RG_MAN_ID_1 (0x1f) | |
213 | #define SR_MAN_ID_1 0x1f, 0xff, 0 | |
214 | #define RG_SHORT_ADDR_0 (0x20) | |
215 | #define SR_SHORT_ADDR_0 0x20, 0xff, 0 | |
216 | #define RG_SHORT_ADDR_1 (0x21) | |
217 | #define SR_SHORT_ADDR_1 0x21, 0xff, 0 | |
218 | #define RG_PAN_ID_0 (0x22) | |
219 | #define SR_PAN_ID_0 0x22, 0xff, 0 | |
220 | #define RG_PAN_ID_1 (0x23) | |
221 | #define SR_PAN_ID_1 0x23, 0xff, 0 | |
222 | #define RG_IEEE_ADDR_0 (0x24) | |
223 | #define SR_IEEE_ADDR_0 0x24, 0xff, 0 | |
224 | #define RG_IEEE_ADDR_1 (0x25) | |
225 | #define SR_IEEE_ADDR_1 0x25, 0xff, 0 | |
226 | #define RG_IEEE_ADDR_2 (0x26) | |
227 | #define SR_IEEE_ADDR_2 0x26, 0xff, 0 | |
228 | #define RG_IEEE_ADDR_3 (0x27) | |
229 | #define SR_IEEE_ADDR_3 0x27, 0xff, 0 | |
230 | #define RG_IEEE_ADDR_4 (0x28) | |
231 | #define SR_IEEE_ADDR_4 0x28, 0xff, 0 | |
232 | #define RG_IEEE_ADDR_5 (0x29) | |
233 | #define SR_IEEE_ADDR_5 0x29, 0xff, 0 | |
234 | #define RG_IEEE_ADDR_6 (0x2a) | |
235 | #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 | |
236 | #define RG_IEEE_ADDR_7 (0x2b) | |
237 | #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 | |
238 | #define RG_XAH_CTRL_0 (0x2c) | |
239 | #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 | |
240 | #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 | |
241 | #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 | |
242 | #define RG_CSMA_SEED_0 (0x2d) | |
243 | #define SR_CSMA_SEED_0 0x2d, 0xff, 0 | |
244 | #define RG_CSMA_SEED_1 (0x2e) | |
245 | #define SR_CSMA_SEED_1 0x2e, 0x07, 0 | |
246 | #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 | |
247 | #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 | |
248 | #define SR_AACK_SET_PD 0x2e, 0x20, 5 | |
249 | #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 | |
250 | #define RG_CSMA_BE (0x2f) | |
251 | #define SR_MIN_BE 0x2f, 0x0f, 0 | |
252 | #define SR_MAX_BE 0x2f, 0xf0, 4 | |
253 | ||
254 | #define CMD_REG 0x80 | |
255 | #define CMD_REG_MASK 0x3f | |
256 | #define CMD_WRITE 0x40 | |
257 | #define CMD_FB 0x20 | |
258 | ||
259 | #define IRQ_BAT_LOW (1 << 7) | |
260 | #define IRQ_TRX_UR (1 << 6) | |
261 | #define IRQ_AMI (1 << 5) | |
262 | #define IRQ_CCA_ED (1 << 4) | |
263 | #define IRQ_TRX_END (1 << 3) | |
264 | #define IRQ_RX_START (1 << 2) | |
265 | #define IRQ_PLL_UNL (1 << 1) | |
266 | #define IRQ_PLL_LOCK (1 << 0) | |
267 | ||
43b5abe0 SH |
268 | #define IRQ_ACTIVE_HIGH 0 |
269 | #define IRQ_ACTIVE_LOW 1 | |
270 | ||
7b8e19b6 | 271 | #define STATE_P_ON 0x00 /* BUSY */ |
272 | #define STATE_BUSY_RX 0x01 | |
273 | #define STATE_BUSY_TX 0x02 | |
274 | #define STATE_FORCE_TRX_OFF 0x03 | |
275 | #define STATE_FORCE_TX_ON 0x04 /* IDLE */ | |
276 | /* 0x05 */ /* INVALID_PARAMETER */ | |
277 | #define STATE_RX_ON 0x06 | |
278 | /* 0x07 */ /* SUCCESS */ | |
279 | #define STATE_TRX_OFF 0x08 | |
280 | #define STATE_TX_ON 0x09 | |
281 | /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */ | |
282 | #define STATE_SLEEP 0x0F | |
48d5dbaf | 283 | #define STATE_PREP_DEEP_SLEEP 0x10 |
7b8e19b6 | 284 | #define STATE_BUSY_RX_AACK 0x11 |
285 | #define STATE_BUSY_TX_ARET 0x12 | |
028889b0 | 286 | #define STATE_RX_AACK_ON 0x16 |
287 | #define STATE_TX_ARET_ON 0x19 | |
7b8e19b6 | 288 | #define STATE_RX_ON_NOCLK 0x1C |
289 | #define STATE_RX_AACK_ON_NOCLK 0x1D | |
290 | #define STATE_BUSY_RX_AACK_NOCLK 0x1E | |
291 | #define STATE_TRANSITION_IN_PROGRESS 0x1F | |
292 | ||
f76014f7 AA |
293 | #define AT86RF2XX_NUMREGS 0x3F |
294 | ||
1d15d6b5 AA |
295 | static int |
296 | at86rf230_async_state_change(struct at86rf230_local *lp, | |
297 | struct at86rf230_state_change *ctx, | |
298 | const u8 state, void (*complete)(void *context)); | |
299 | ||
f76014f7 AA |
300 | static inline int |
301 | __at86rf230_write(struct at86rf230_local *lp, | |
302 | unsigned int addr, unsigned int data) | |
303 | { | |
304 | return regmap_write(lp->regmap, addr, data); | |
305 | } | |
306 | ||
307 | static inline int | |
308 | __at86rf230_read(struct at86rf230_local *lp, | |
309 | unsigned int addr, unsigned int *data) | |
310 | { | |
311 | return regmap_read(lp->regmap, addr, data); | |
312 | } | |
313 | ||
314 | static inline int | |
315 | at86rf230_read_subreg(struct at86rf230_local *lp, | |
316 | unsigned int addr, unsigned int mask, | |
317 | unsigned int shift, unsigned int *data) | |
318 | { | |
319 | int rc; | |
320 | ||
321 | rc = __at86rf230_read(lp, addr, data); | |
322 | if (rc > 0) | |
323 | *data = (*data & mask) >> shift; | |
324 | ||
325 | return rc; | |
326 | } | |
327 | ||
328 | static inline int | |
329 | at86rf230_write_subreg(struct at86rf230_local *lp, | |
330 | unsigned int addr, unsigned int mask, | |
331 | unsigned int shift, unsigned int data) | |
332 | { | |
333 | return regmap_update_bits(lp->regmap, addr, mask, data << shift); | |
334 | } | |
335 | ||
336 | static bool | |
337 | at86rf230_reg_writeable(struct device *dev, unsigned int reg) | |
338 | { | |
339 | switch (reg) { | |
340 | case RG_TRX_STATE: | |
341 | case RG_TRX_CTRL_0: | |
342 | case RG_TRX_CTRL_1: | |
343 | case RG_PHY_TX_PWR: | |
344 | case RG_PHY_ED_LEVEL: | |
345 | case RG_PHY_CC_CCA: | |
346 | case RG_CCA_THRES: | |
347 | case RG_RX_CTRL: | |
348 | case RG_SFD_VALUE: | |
349 | case RG_TRX_CTRL_2: | |
350 | case RG_ANT_DIV: | |
351 | case RG_IRQ_MASK: | |
352 | case RG_VREG_CTRL: | |
353 | case RG_BATMON: | |
354 | case RG_XOSC_CTRL: | |
355 | case RG_RX_SYN: | |
356 | case RG_XAH_CTRL_1: | |
357 | case RG_FTN_CTRL: | |
358 | case RG_PLL_CF: | |
359 | case RG_PLL_DCU: | |
360 | case RG_SHORT_ADDR_0: | |
361 | case RG_SHORT_ADDR_1: | |
362 | case RG_PAN_ID_0: | |
363 | case RG_PAN_ID_1: | |
364 | case RG_IEEE_ADDR_0: | |
365 | case RG_IEEE_ADDR_1: | |
366 | case RG_IEEE_ADDR_2: | |
367 | case RG_IEEE_ADDR_3: | |
368 | case RG_IEEE_ADDR_4: | |
369 | case RG_IEEE_ADDR_5: | |
370 | case RG_IEEE_ADDR_6: | |
371 | case RG_IEEE_ADDR_7: | |
372 | case RG_XAH_CTRL_0: | |
373 | case RG_CSMA_SEED_0: | |
374 | case RG_CSMA_SEED_1: | |
375 | case RG_CSMA_BE: | |
376 | return true; | |
377 | default: | |
378 | return false; | |
379 | } | |
380 | } | |
381 | ||
382 | static bool | |
383 | at86rf230_reg_readable(struct device *dev, unsigned int reg) | |
384 | { | |
385 | bool rc; | |
386 | ||
387 | /* all writeable are also readable */ | |
388 | rc = at86rf230_reg_writeable(dev, reg); | |
389 | if (rc) | |
390 | return rc; | |
391 | ||
392 | /* readonly regs */ | |
393 | switch (reg) { | |
394 | case RG_TRX_STATUS: | |
395 | case RG_PHY_RSSI: | |
396 | case RG_IRQ_STATUS: | |
397 | case RG_PART_NUM: | |
398 | case RG_VERSION_NUM: | |
399 | case RG_MAN_ID_1: | |
400 | case RG_MAN_ID_0: | |
401 | return true; | |
402 | default: | |
403 | return false; | |
404 | } | |
405 | } | |
406 | ||
407 | static bool | |
408 | at86rf230_reg_volatile(struct device *dev, unsigned int reg) | |
409 | { | |
410 | /* can be changed during runtime */ | |
411 | switch (reg) { | |
412 | case RG_TRX_STATUS: | |
413 | case RG_TRX_STATE: | |
414 | case RG_PHY_RSSI: | |
415 | case RG_PHY_ED_LEVEL: | |
416 | case RG_IRQ_STATUS: | |
417 | case RG_VREG_CTRL: | |
418 | return true; | |
419 | default: | |
420 | return false; | |
421 | } | |
422 | } | |
423 | ||
424 | static bool | |
425 | at86rf230_reg_precious(struct device *dev, unsigned int reg) | |
426 | { | |
427 | /* don't clear irq line on read */ | |
428 | switch (reg) { | |
429 | case RG_IRQ_STATUS: | |
430 | return true; | |
431 | default: | |
432 | return false; | |
433 | } | |
434 | } | |
435 | ||
436 | static struct regmap_config at86rf230_regmap_spi_config = { | |
437 | .reg_bits = 8, | |
438 | .val_bits = 8, | |
439 | .write_flag_mask = CMD_REG | CMD_WRITE, | |
440 | .read_flag_mask = CMD_REG, | |
441 | .cache_type = REGCACHE_RBTREE, | |
442 | .max_register = AT86RF2XX_NUMREGS, | |
443 | .writeable_reg = at86rf230_reg_writeable, | |
444 | .readable_reg = at86rf230_reg_readable, | |
445 | .volatile_reg = at86rf230_reg_volatile, | |
446 | .precious_reg = at86rf230_reg_precious, | |
447 | }; | |
448 | ||
1d15d6b5 AA |
449 | static void |
450 | at86rf230_async_error_recover(void *context) | |
451 | { | |
452 | struct at86rf230_state_change *ctx = context; | |
453 | struct at86rf230_local *lp = ctx->lp; | |
454 | ||
455 | at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL); | |
456 | } | |
457 | ||
458 | static void | |
459 | at86rf230_async_error(struct at86rf230_local *lp, | |
460 | struct at86rf230_state_change *ctx, int rc) | |
461 | { | |
462 | dev_err(&lp->spi->dev, "spi_async error %d\n", rc); | |
463 | ||
464 | at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF, | |
465 | at86rf230_async_error_recover); | |
466 | } | |
467 | ||
468 | /* Generic function to get some register value in async mode */ | |
7b8e19b6 | 469 | static int |
1d15d6b5 AA |
470 | at86rf230_async_read_reg(struct at86rf230_local *lp, const u8 reg, |
471 | struct at86rf230_state_change *ctx, | |
472 | void (*complete)(void *context)) | |
7b8e19b6 | 473 | { |
1d15d6b5 AA |
474 | u8 *tx_buf = ctx->buf; |
475 | ||
476 | tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG; | |
477 | ctx->trx.len = 2; | |
478 | ctx->msg.complete = complete; | |
479 | return spi_async(lp->spi, &ctx->msg); | |
480 | } | |
481 | ||
482 | static void | |
483 | at86rf230_async_state_assert(void *context) | |
484 | { | |
485 | struct at86rf230_state_change *ctx = context; | |
486 | struct at86rf230_local *lp = ctx->lp; | |
487 | const u8 *buf = ctx->buf; | |
488 | const u8 trx_state = buf[1] & 0x1f; | |
489 | ||
490 | /* Assert state change */ | |
491 | if (trx_state != ctx->to_state) { | |
492 | /* Special handling if transceiver state is in | |
493 | * STATE_BUSY_RX_AACK and a SHR was detected. | |
494 | */ | |
495 | if (trx_state == STATE_BUSY_RX_AACK) { | |
496 | /* Undocumented race condition. If we send a state | |
497 | * change to STATE_RX_AACK_ON the transceiver could | |
498 | * change his state automatically to STATE_BUSY_RX_AACK | |
499 | * if a SHR was detected. This is not an error, but we | |
500 | * can't assert this. | |
501 | */ | |
502 | if (ctx->to_state == STATE_RX_AACK_ON) | |
503 | goto done; | |
504 | ||
505 | /* If we change to STATE_TX_ON without forcing and | |
506 | * transceiver state is STATE_BUSY_RX_AACK, we wait | |
507 | * 'tFrame + tPAck' receiving time. In this time the | |
508 | * PDU should be received. If the transceiver is still | |
509 | * in STATE_BUSY_RX_AACK, we run a force state change | |
510 | * to STATE_TX_ON. This is a timeout handling, if the | |
511 | * transceiver stucks in STATE_BUSY_RX_AACK. | |
512 | */ | |
513 | if (ctx->to_state == STATE_TX_ON) { | |
514 | at86rf230_async_state_change(lp, ctx, | |
515 | STATE_FORCE_TX_ON, | |
516 | ctx->complete); | |
517 | return; | |
518 | } | |
519 | } | |
520 | ||
521 | ||
522 | dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n", | |
523 | ctx->from_state, ctx->to_state, trx_state); | |
524 | } | |
525 | ||
526 | done: | |
527 | if (ctx->complete) | |
528 | ctx->complete(context); | |
529 | } | |
530 | ||
531 | /* Do state change timing delay. */ | |
532 | static void | |
533 | at86rf230_async_state_delay(void *context) | |
534 | { | |
535 | struct at86rf230_state_change *ctx = context; | |
536 | struct at86rf230_local *lp = ctx->lp; | |
537 | struct at86rf2xx_chip_data *c = lp->data; | |
538 | bool force = false; | |
539 | int rc; | |
540 | ||
541 | /* The force state changes are will show as normal states in the | |
542 | * state status subregister. We change the to_state to the | |
543 | * corresponding one and remember if it was a force change, this | |
544 | * differs if we do a state change from STATE_BUSY_RX_AACK. | |
545 | */ | |
546 | switch (ctx->to_state) { | |
547 | case STATE_FORCE_TX_ON: | |
548 | ctx->to_state = STATE_TX_ON; | |
549 | force = true; | |
550 | break; | |
551 | case STATE_FORCE_TRX_OFF: | |
552 | ctx->to_state = STATE_TRX_OFF; | |
553 | force = true; | |
554 | break; | |
555 | default: | |
556 | break; | |
557 | } | |
558 | ||
559 | switch (ctx->from_state) { | |
2e0571c0 AA |
560 | case STATE_TRX_OFF: |
561 | switch (ctx->to_state) { | |
562 | case STATE_RX_AACK_ON: | |
563 | usleep_range(c->t_off_to_aack, c->t_off_to_aack + 10); | |
564 | goto change; | |
565 | case STATE_TX_ON: | |
566 | usleep_range(c->t_off_to_tx_on, | |
567 | c->t_off_to_tx_on + 10); | |
568 | goto change; | |
569 | default: | |
570 | break; | |
571 | } | |
572 | break; | |
1d15d6b5 AA |
573 | case STATE_BUSY_RX_AACK: |
574 | switch (ctx->to_state) { | |
575 | case STATE_TX_ON: | |
576 | /* Wait for worst case receiving time if we | |
577 | * didn't make a force change from BUSY_RX_AACK | |
578 | * to TX_ON. | |
579 | */ | |
580 | if (!force) { | |
581 | usleep_range(c->t_frame + c->t_p_ack, | |
582 | c->t_frame + c->t_p_ack + 1000); | |
583 | goto change; | |
584 | } | |
585 | break; | |
586 | default: | |
587 | break; | |
588 | } | |
589 | break; | |
09e536cd AA |
590 | /* Default value, means RESET state */ |
591 | case STATE_P_ON: | |
592 | switch (ctx->to_state) { | |
593 | case STATE_TRX_OFF: | |
594 | usleep_range(c->t_reset_to_off, c->t_reset_to_off + 10); | |
595 | goto change; | |
596 | default: | |
597 | break; | |
598 | } | |
599 | break; | |
1d15d6b5 AA |
600 | default: |
601 | break; | |
602 | } | |
603 | ||
604 | /* Default delay is 1us in the most cases */ | |
605 | udelay(1); | |
606 | ||
607 | change: | |
608 | rc = at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, | |
609 | at86rf230_async_state_assert); | |
610 | if (rc) | |
611 | dev_err(&lp->spi->dev, "spi_async error %d\n", rc); | |
612 | } | |
613 | ||
614 | static void | |
615 | at86rf230_async_state_change_start(void *context) | |
616 | { | |
617 | struct at86rf230_state_change *ctx = context; | |
618 | struct at86rf230_local *lp = ctx->lp; | |
619 | u8 *buf = ctx->buf; | |
620 | const u8 trx_state = buf[1] & 0x1f; | |
621 | int rc; | |
622 | ||
623 | /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */ | |
624 | if (trx_state == STATE_TRANSITION_IN_PROGRESS) { | |
625 | udelay(1); | |
626 | rc = at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, | |
627 | at86rf230_async_state_change_start); | |
628 | if (rc) | |
629 | dev_err(&lp->spi->dev, "spi_async error %d\n", rc); | |
630 | return; | |
631 | } | |
632 | ||
633 | /* Check if we already are in the state which we change in */ | |
634 | if (trx_state == ctx->to_state) { | |
635 | if (ctx->complete) | |
636 | ctx->complete(context); | |
637 | return; | |
638 | } | |
639 | ||
640 | /* Set current state to the context of state change */ | |
641 | ctx->from_state = trx_state; | |
642 | ||
643 | /* Going into the next step for a state change which do a timing | |
644 | * relevant delay. | |
645 | */ | |
646 | buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE; | |
647 | buf[1] = ctx->to_state; | |
648 | ctx->trx.len = 2; | |
649 | ctx->msg.complete = at86rf230_async_state_delay; | |
650 | rc = spi_async(lp->spi, &ctx->msg); | |
651 | if (rc) | |
652 | dev_err(&lp->spi->dev, "spi_async error %d\n", rc); | |
7b8e19b6 | 653 | } |
654 | ||
655 | static int | |
1d15d6b5 AA |
656 | at86rf230_async_state_change(struct at86rf230_local *lp, |
657 | struct at86rf230_state_change *ctx, | |
658 | const u8 state, void (*complete)(void *context)) | |
7b8e19b6 | 659 | { |
1d15d6b5 AA |
660 | /* Initialization for the state change context */ |
661 | ctx->to_state = state; | |
662 | ctx->complete = complete; | |
663 | return at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, | |
664 | at86rf230_async_state_change_start); | |
665 | } | |
7b8e19b6 | 666 | |
2e0571c0 AA |
667 | static void |
668 | at86rf230_sync_state_change_complete(void *context) | |
669 | { | |
670 | struct at86rf230_state_change *ctx = context; | |
671 | struct at86rf230_local *lp = ctx->lp; | |
672 | ||
673 | complete(&lp->state_complete); | |
674 | } | |
675 | ||
676 | /* This function do a sync framework above the async state change. | |
677 | * Some callbacks of the IEEE 802.15.4 driver interface need to be | |
678 | * handled synchronously. | |
679 | */ | |
680 | static int | |
681 | at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state) | |
682 | { | |
683 | int rc; | |
684 | ||
685 | rc = at86rf230_async_state_change(lp, &lp->state, state, | |
686 | at86rf230_sync_state_change_complete); | |
687 | if (rc) { | |
688 | at86rf230_async_error(lp, &lp->state, rc); | |
689 | return rc; | |
690 | } | |
691 | ||
692 | rc = wait_for_completion_timeout(&lp->state_complete, | |
693 | msecs_to_jiffies(100)); | |
d06c2199 AA |
694 | if (!rc) { |
695 | at86rf230_async_error(lp, &lp->state, -ETIMEDOUT); | |
2e0571c0 | 696 | return -ETIMEDOUT; |
d06c2199 | 697 | } |
2e0571c0 AA |
698 | |
699 | return 0; | |
700 | } | |
701 | ||
1d15d6b5 AA |
702 | static void |
703 | at86rf230_tx_complete(void *context) | |
704 | { | |
705 | struct at86rf230_state_change *ctx = context; | |
706 | struct at86rf230_local *lp = ctx->lp; | |
707 | ||
35e92a8e | 708 | enable_irq(lp->spi->irq); |
1d15d6b5 AA |
709 | complete(&lp->tx_complete); |
710 | } | |
711 | ||
712 | static void | |
713 | at86rf230_tx_on(void *context) | |
714 | { | |
715 | struct at86rf230_state_change *ctx = context; | |
716 | struct at86rf230_local *lp = ctx->lp; | |
717 | int rc; | |
718 | ||
719 | rc = at86rf230_async_state_change(lp, &lp->irq, STATE_RX_AACK_ON, | |
720 | at86rf230_tx_complete); | |
721 | if (rc) | |
722 | at86rf230_async_error(lp, ctx, rc); | |
723 | } | |
724 | ||
725 | static void | |
726 | at86rf230_tx_trac_error(void *context) | |
727 | { | |
728 | struct at86rf230_state_change *ctx = context; | |
729 | struct at86rf230_local *lp = ctx->lp; | |
730 | int rc; | |
731 | ||
732 | rc = at86rf230_async_state_change(lp, ctx, STATE_TX_ON, | |
733 | at86rf230_tx_on); | |
734 | if (rc) | |
735 | at86rf230_async_error(lp, ctx, rc); | |
736 | } | |
737 | ||
738 | static void | |
739 | at86rf230_tx_trac_check(void *context) | |
740 | { | |
741 | struct at86rf230_state_change *ctx = context; | |
742 | struct at86rf230_local *lp = ctx->lp; | |
743 | const u8 *buf = ctx->buf; | |
744 | const u8 trac = (buf[1] & 0xe0) >> 5; | |
745 | int rc; | |
746 | ||
747 | /* If trac status is different than zero we need to do a state change | |
748 | * to STATE_FORCE_TRX_OFF then STATE_TX_ON to recover the transceiver | |
749 | * state to TX_ON. | |
750 | */ | |
751 | if (trac) { | |
752 | rc = at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF, | |
753 | at86rf230_tx_trac_error); | |
754 | if (rc) | |
755 | at86rf230_async_error(lp, ctx, rc); | |
756 | return; | |
757 | } | |
758 | ||
759 | at86rf230_tx_on(context); | |
760 | } | |
761 | ||
762 | ||
763 | static void | |
764 | at86rf230_tx_trac_status(void *context) | |
765 | { | |
766 | struct at86rf230_state_change *ctx = context; | |
767 | struct at86rf230_local *lp = ctx->lp; | |
768 | int rc; | |
769 | ||
770 | rc = at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx, | |
771 | at86rf230_tx_trac_check); | |
772 | if (rc) | |
773 | at86rf230_async_error(lp, ctx, rc); | |
774 | } | |
775 | ||
776 | static void | |
777 | at86rf230_rx(struct at86rf230_local *lp, | |
778 | const u8 *data, u8 len) | |
779 | { | |
780 | u8 lqi; | |
781 | struct sk_buff *skb; | |
782 | u8 rx_local_buf[AT86RF2XX_MAX_BUF]; | |
783 | ||
784 | if (len < 2) | |
785 | return; | |
786 | ||
787 | /* read full frame buffer and invalid lqi value to lowest | |
788 | * indicator if frame was is in a corrupted state. | |
789 | */ | |
790 | if (len > IEEE802154_MTU) { | |
791 | lqi = 0; | |
792 | len = IEEE802154_MTU; | |
793 | dev_vdbg(&lp->spi->dev, "corrupted frame received\n"); | |
794 | } else { | |
795 | lqi = data[len]; | |
796 | } | |
797 | ||
798 | memcpy(rx_local_buf, data, len); | |
799 | enable_irq(lp->spi->irq); | |
800 | ||
801 | skb = alloc_skb(IEEE802154_MTU, GFP_ATOMIC); | |
802 | if (!skb) { | |
803 | dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n"); | |
804 | return; | |
805 | } | |
806 | ||
807 | memcpy(skb_put(skb, len), rx_local_buf, len); | |
808 | ||
809 | /* We do not put CRC into the frame */ | |
810 | skb_trim(skb, len - 2); | |
7b8e19b6 | 811 | |
1d15d6b5 AA |
812 | ieee802154_rx_irqsafe(lp->dev, skb, lqi); |
813 | } | |
7b8e19b6 | 814 | |
1d15d6b5 AA |
815 | static void |
816 | at86rf230_rx_read_frame_complete(void *context) | |
817 | { | |
818 | struct at86rf230_state_change *ctx = context; | |
819 | struct at86rf230_local *lp = ctx->lp; | |
820 | const u8 *buf = lp->irq.buf; | |
821 | const u8 len = buf[1]; | |
7b8e19b6 | 822 | |
1d15d6b5 AA |
823 | at86rf230_rx(lp, buf + 2, len); |
824 | } | |
825 | ||
826 | static int | |
827 | at86rf230_rx_read_frame(struct at86rf230_local *lp) | |
828 | { | |
829 | u8 *buf = lp->irq.buf; | |
7b8e19b6 | 830 | |
831 | buf[0] = CMD_FB; | |
1d15d6b5 AA |
832 | lp->irq.trx.len = AT86RF2XX_MAX_BUF; |
833 | lp->irq.msg.complete = at86rf230_rx_read_frame_complete; | |
834 | return spi_async(lp->spi, &lp->irq.msg); | |
835 | } | |
836 | ||
837 | static void | |
838 | at86rf230_rx_trac_check(void *context) | |
839 | { | |
840 | struct at86rf230_state_change *ctx = context; | |
841 | struct at86rf230_local *lp = ctx->lp; | |
842 | int rc; | |
843 | ||
844 | /* Possible check on trac status here. This could be useful to make | |
845 | * some stats why receive is failed. Not used at the moment, but it's | |
846 | * maybe timing relevant. Datasheet doesn't say anything about this. | |
847 | * The programming guide say do it so. | |
848 | */ | |
849 | ||
850 | rc = at86rf230_rx_read_frame(lp); | |
851 | if (rc) { | |
852 | enable_irq(lp->spi->irq); | |
853 | at86rf230_async_error(lp, ctx, rc); | |
854 | } | |
855 | } | |
856 | ||
857 | static int | |
858 | at86rf230_irq_trx_end(struct at86rf230_local *lp) | |
859 | { | |
860 | spin_lock(&lp->lock); | |
861 | if (lp->is_tx) { | |
862 | lp->is_tx = 0; | |
863 | spin_unlock(&lp->lock); | |
1d15d6b5 AA |
864 | |
865 | if (lp->tx_aret) | |
866 | return at86rf230_async_state_change(lp, &lp->irq, | |
867 | STATE_FORCE_TX_ON, | |
868 | at86rf230_tx_trac_status); | |
869 | else | |
870 | return at86rf230_async_state_change(lp, &lp->irq, | |
871 | STATE_RX_AACK_ON, | |
872 | at86rf230_tx_complete); | |
873 | } else { | |
874 | spin_unlock(&lp->lock); | |
875 | return at86rf230_async_read_reg(lp, RG_TRX_STATE, &lp->irq, | |
876 | at86rf230_rx_trac_check); | |
877 | } | |
878 | } | |
879 | ||
880 | static void | |
881 | at86rf230_irq_status(void *context) | |
882 | { | |
883 | struct at86rf230_state_change *ctx = context; | |
884 | struct at86rf230_local *lp = ctx->lp; | |
885 | const u8 *buf = lp->irq.buf; | |
886 | const u8 irq = buf[1]; | |
887 | int rc; | |
888 | ||
889 | if (irq & IRQ_TRX_END) { | |
890 | rc = at86rf230_irq_trx_end(lp); | |
891 | if (rc) | |
892 | at86rf230_async_error(lp, ctx, rc); | |
893 | } else { | |
894 | enable_irq(lp->spi->irq); | |
895 | dev_err(&lp->spi->dev, "not supported irq %02x received\n", | |
896 | irq); | |
897 | } | |
898 | } | |
899 | ||
900 | static irqreturn_t at86rf230_isr(int irq, void *data) | |
901 | { | |
902 | struct at86rf230_local *lp = data; | |
903 | struct at86rf230_state_change *ctx = &lp->irq; | |
904 | u8 *buf = ctx->buf; | |
905 | int rc; | |
906 | ||
90566363 | 907 | disable_irq_nosync(irq); |
1d15d6b5 AA |
908 | |
909 | buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG; | |
910 | ctx->trx.len = 2; | |
911 | ctx->msg.complete = at86rf230_irq_status; | |
912 | rc = spi_async(lp->spi, &ctx->msg); | |
913 | if (rc) { | |
e9310211 | 914 | enable_irq(irq); |
1d15d6b5 AA |
915 | at86rf230_async_error(lp, ctx, rc); |
916 | return IRQ_NONE; | |
917 | } | |
918 | ||
919 | return IRQ_HANDLED; | |
920 | } | |
921 | ||
922 | static void | |
923 | at86rf230_write_frame_complete(void *context) | |
924 | { | |
925 | struct at86rf230_state_change *ctx = context; | |
926 | struct at86rf230_local *lp = ctx->lp; | |
927 | u8 *buf = ctx->buf; | |
928 | int rc; | |
929 | ||
930 | buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE; | |
931 | buf[1] = STATE_BUSY_TX; | |
932 | ctx->trx.len = 2; | |
933 | ctx->msg.complete = NULL; | |
934 | rc = spi_async(lp->spi, &ctx->msg); | |
935 | if (rc) | |
936 | at86rf230_async_error(lp, ctx, rc); | |
937 | } | |
938 | ||
939 | static void | |
940 | at86rf230_write_frame(void *context) | |
941 | { | |
942 | struct at86rf230_state_change *ctx = context; | |
943 | struct at86rf230_local *lp = ctx->lp; | |
944 | struct sk_buff *skb = lp->tx_skb; | |
945 | u8 *buf = lp->tx.buf; | |
946 | int rc; | |
947 | ||
948 | spin_lock(&lp->lock); | |
949 | lp->is_tx = 1; | |
950 | spin_unlock(&lp->lock); | |
951 | ||
952 | buf[0] = CMD_FB | CMD_WRITE; | |
953 | buf[1] = skb->len + 2; | |
954 | memcpy(buf + 2, skb->data, skb->len); | |
955 | lp->tx.trx.len = skb->len + 2; | |
956 | lp->tx.msg.complete = at86rf230_write_frame_complete; | |
957 | rc = spi_async(lp->spi, &lp->tx.msg); | |
958 | if (rc) | |
959 | at86rf230_async_error(lp, ctx, rc); | |
960 | } | |
961 | ||
962 | static void | |
963 | at86rf230_xmit_tx_on(void *context) | |
964 | { | |
965 | struct at86rf230_state_change *ctx = context; | |
966 | struct at86rf230_local *lp = ctx->lp; | |
967 | int rc; | |
7b8e19b6 | 968 | |
1d15d6b5 AA |
969 | rc = at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON, |
970 | at86rf230_write_frame); | |
971 | if (rc) | |
972 | at86rf230_async_error(lp, ctx, rc); | |
973 | } | |
974 | ||
975 | static int | |
976 | at86rf230_xmit(struct ieee802154_dev *dev, struct sk_buff *skb) | |
977 | { | |
978 | struct at86rf230_local *lp = dev->priv; | |
979 | struct at86rf230_state_change *ctx = &lp->tx; | |
7b8e19b6 | 980 | |
1d15d6b5 AA |
981 | void (*tx_complete)(void *context) = at86rf230_write_frame; |
982 | int rc; | |
7b8e19b6 | 983 | |
1d15d6b5 | 984 | lp->tx_skb = skb; |
7b8e19b6 | 985 | |
1d15d6b5 AA |
986 | /* In ARET mode we need to go into STATE_TX_ARET_ON after we |
987 | * are in STATE_TX_ON. The pfad differs here, so we change | |
988 | * the complete handler. | |
989 | */ | |
990 | if (lp->tx_aret) | |
991 | tx_complete = at86rf230_xmit_tx_on; | |
7b8e19b6 | 992 | |
1d15d6b5 AA |
993 | rc = at86rf230_async_state_change(lp, ctx, STATE_TX_ON, |
994 | tx_complete); | |
995 | if (rc) { | |
996 | at86rf230_async_error(lp, ctx, rc); | |
997 | return rc; | |
998 | } | |
999 | rc = wait_for_completion_interruptible_timeout(&lp->tx_complete, | |
1000 | msecs_to_jiffies(lp->data->t_tx_timeout)); | |
1001 | if (!rc) { | |
464f0299 | 1002 | at86rf230_async_error(lp, ctx, -ETIMEDOUT); |
1d15d6b5 | 1003 | return -ETIMEDOUT; |
7b8e19b6 | 1004 | } |
7b8e19b6 | 1005 | |
850f43ac AA |
1006 | if (lp->max_frame_retries > 0) |
1007 | return 0; | |
1008 | ||
1d15d6b5 AA |
1009 | /* Interfame spacing time, which is phy depend. |
1010 | * TODO | |
1011 | * Move this handling in MAC 802.15.4 layer. | |
1012 | * This is currently a workaround to avoid fragmenation issues. | |
1013 | */ | |
1014 | if (skb->len > 18) | |
1015 | usleep_range(lp->data->t_lifs, lp->data->t_lifs + 10); | |
1016 | else | |
1017 | usleep_range(lp->data->t_sifs, lp->data->t_sifs + 10); | |
1018 | ||
1019 | return 0; | |
7b8e19b6 | 1020 | } |
1021 | ||
1022 | static int | |
1023 | at86rf230_ed(struct ieee802154_dev *dev, u8 *level) | |
1024 | { | |
1025 | might_sleep(); | |
1026 | BUG_ON(!level); | |
1027 | *level = 0xbe; | |
1028 | return 0; | |
1029 | } | |
1030 | ||
7b8e19b6 | 1031 | static int |
1032 | at86rf230_start(struct ieee802154_dev *dev) | |
1033 | { | |
2e0571c0 | 1034 | return at86rf230_sync_state_change(dev->priv, STATE_RX_AACK_ON); |
7b8e19b6 | 1035 | } |
1036 | ||
1037 | static void | |
1038 | at86rf230_stop(struct ieee802154_dev *dev) | |
1039 | { | |
2e0571c0 | 1040 | at86rf230_sync_state_change(dev->priv, STATE_FORCE_TRX_OFF); |
7b8e19b6 | 1041 | } |
1042 | ||
8fad346f | 1043 | static int |
a53d1f7c | 1044 | at86rf23x_set_channel(struct at86rf230_local *lp, int page, int channel) |
8fad346f PB |
1045 | { |
1046 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); | |
1047 | } | |
1048 | ||
1049 | static int | |
1050 | at86rf212_set_channel(struct at86rf230_local *lp, int page, int channel) | |
1051 | { | |
1052 | int rc; | |
1053 | ||
1054 | if (channel == 0) | |
1055 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0); | |
1056 | else | |
1057 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1); | |
1058 | if (rc < 0) | |
1059 | return rc; | |
1060 | ||
6ca00197 | 1061 | if (page == 0) { |
643e53c2 | 1062 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0); |
a53d1f7c | 1063 | lp->data->rssi_base_val = -100; |
6ca00197 | 1064 | } else { |
643e53c2 | 1065 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1); |
a53d1f7c | 1066 | lp->data->rssi_base_val = -98; |
6ca00197 | 1067 | } |
643e53c2 PB |
1068 | if (rc < 0) |
1069 | return rc; | |
1070 | ||
8fad346f PB |
1071 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); |
1072 | } | |
1073 | ||
7b8e19b6 | 1074 | static int |
1075 | at86rf230_channel(struct ieee802154_dev *dev, int page, int channel) | |
1076 | { | |
1077 | struct at86rf230_local *lp = dev->priv; | |
1078 | int rc; | |
1079 | ||
1080 | might_sleep(); | |
1081 | ||
8fad346f PB |
1082 | if (page < 0 || page > 31 || |
1083 | !(lp->dev->phy->channels_supported[page] & BIT(channel))) { | |
7b8e19b6 | 1084 | WARN_ON(1); |
1085 | return -EINVAL; | |
1086 | } | |
1087 | ||
a53d1f7c | 1088 | rc = lp->data->set_channel(lp, page, channel); |
8fad346f PB |
1089 | if (rc < 0) |
1090 | return rc; | |
1091 | ||
984e0c68 AA |
1092 | /* Wait for PLL */ |
1093 | usleep_range(lp->data->t_channel_switch, | |
1094 | lp->data->t_channel_switch + 10); | |
7b8e19b6 | 1095 | dev->phy->current_channel = channel; |
643e53c2 | 1096 | dev->phy->current_page = page; |
7b8e19b6 | 1097 | |
1098 | return 0; | |
1099 | } | |
1100 | ||
1486774d | 1101 | static int |
1102 | at86rf230_set_hw_addr_filt(struct ieee802154_dev *dev, | |
1103 | struct ieee802154_hw_addr_filt *filt, | |
1104 | unsigned long changed) | |
1105 | { | |
1106 | struct at86rf230_local *lp = dev->priv; | |
1107 | ||
1108 | if (changed & IEEE802515_AFILT_SADDR_CHANGED) { | |
b70ab2e8 PB |
1109 | u16 addr = le16_to_cpu(filt->short_addr); |
1110 | ||
1486774d | 1111 | dev_vdbg(&lp->spi->dev, |
1112 | "at86rf230_set_hw_addr_filt called for saddr\n"); | |
b70ab2e8 PB |
1113 | __at86rf230_write(lp, RG_SHORT_ADDR_0, addr); |
1114 | __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8); | |
1486774d | 1115 | } |
1116 | ||
1117 | if (changed & IEEE802515_AFILT_PANID_CHANGED) { | |
b70ab2e8 PB |
1118 | u16 pan = le16_to_cpu(filt->pan_id); |
1119 | ||
1486774d | 1120 | dev_vdbg(&lp->spi->dev, |
1121 | "at86rf230_set_hw_addr_filt called for pan id\n"); | |
b70ab2e8 PB |
1122 | __at86rf230_write(lp, RG_PAN_ID_0, pan); |
1123 | __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8); | |
1486774d | 1124 | } |
1125 | ||
1126 | if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) { | |
b70ab2e8 PB |
1127 | u8 i, addr[8]; |
1128 | ||
1129 | memcpy(addr, &filt->ieee_addr, 8); | |
1486774d | 1130 | dev_vdbg(&lp->spi->dev, |
1131 | "at86rf230_set_hw_addr_filt called for IEEE addr\n"); | |
b70ab2e8 PB |
1132 | for (i = 0; i < 8; i++) |
1133 | __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]); | |
1486774d | 1134 | } |
1135 | ||
1136 | if (changed & IEEE802515_AFILT_PANC_CHANGED) { | |
1137 | dev_vdbg(&lp->spi->dev, | |
1138 | "at86rf230_set_hw_addr_filt called for panc change\n"); | |
1139 | if (filt->pan_coord) | |
1140 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1); | |
1141 | else | |
1142 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0); | |
1143 | } | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
9b2777d6 | 1148 | static int |
640985ec | 1149 | at86rf230_set_txpower(struct ieee802154_dev *dev, int db) |
9b2777d6 PB |
1150 | { |
1151 | struct at86rf230_local *lp = dev->priv; | |
9b2777d6 PB |
1152 | |
1153 | /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five | |
1154 | * bits decrease power in 1dB steps. 0x60 represents extra PA gain of | |
1155 | * 0dB. | |
1156 | * thus, supported values for db range from -26 to 5, for 31dB of | |
1157 | * reduction to 0dB of reduction. | |
1158 | */ | |
1159 | if (db > 5 || db < -26) | |
1160 | return -EINVAL; | |
1161 | ||
1162 | db = -(db - 5); | |
1163 | ||
677676cd | 1164 | return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db); |
9b2777d6 PB |
1165 | } |
1166 | ||
84dda3c6 | 1167 | static int |
640985ec | 1168 | at86rf230_set_lbt(struct ieee802154_dev *dev, bool on) |
84dda3c6 PB |
1169 | { |
1170 | struct at86rf230_local *lp = dev->priv; | |
1171 | ||
1172 | return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on); | |
1173 | } | |
1174 | ||
ba08fea5 | 1175 | static int |
640985ec | 1176 | at86rf230_set_cca_mode(struct ieee802154_dev *dev, u8 mode) |
ba08fea5 PB |
1177 | { |
1178 | struct at86rf230_local *lp = dev->priv; | |
1179 | ||
1180 | return at86rf230_write_subreg(lp, SR_CCA_MODE, mode); | |
1181 | } | |
1182 | ||
a7d7eda9 AA |
1183 | static int |
1184 | at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level) | |
1185 | { | |
1186 | return (level - lp->data->rssi_base_val) * 100 / 207; | |
1187 | } | |
1188 | ||
1189 | static int | |
1190 | at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level) | |
1191 | { | |
1192 | return (level - lp->data->rssi_base_val) / 2; | |
1193 | } | |
1194 | ||
6ca00197 | 1195 | static int |
640985ec | 1196 | at86rf230_set_cca_ed_level(struct ieee802154_dev *dev, s32 level) |
6ca00197 PB |
1197 | { |
1198 | struct at86rf230_local *lp = dev->priv; | |
6ca00197 | 1199 | |
a53d1f7c | 1200 | if (level < lp->data->rssi_base_val || level > 30) |
6ca00197 PB |
1201 | return -EINVAL; |
1202 | ||
a7d7eda9 AA |
1203 | return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, |
1204 | lp->data->get_desense_steps(lp, level)); | |
6ca00197 PB |
1205 | } |
1206 | ||
f2fdd67c | 1207 | static int |
640985ec | 1208 | at86rf230_set_csma_params(struct ieee802154_dev *dev, u8 min_be, u8 max_be, |
f2fdd67c PB |
1209 | u8 retries) |
1210 | { | |
1211 | struct at86rf230_local *lp = dev->priv; | |
1212 | int rc; | |
1213 | ||
1214 | if (min_be > max_be || max_be > 8 || retries > 5) | |
1215 | return -EINVAL; | |
1216 | ||
1217 | rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be); | |
1218 | if (rc) | |
1219 | return rc; | |
1220 | ||
1221 | rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be); | |
1222 | if (rc) | |
1223 | return rc; | |
1224 | ||
39d7f320 | 1225 | return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries); |
f2fdd67c PB |
1226 | } |
1227 | ||
1228 | static int | |
640985ec | 1229 | at86rf230_set_frame_retries(struct ieee802154_dev *dev, s8 retries) |
f2fdd67c PB |
1230 | { |
1231 | struct at86rf230_local *lp = dev->priv; | |
1232 | int rc = 0; | |
1233 | ||
1234 | if (retries < -1 || retries > 15) | |
1235 | return -EINVAL; | |
1236 | ||
1237 | lp->tx_aret = retries >= 0; | |
850f43ac | 1238 | lp->max_frame_retries = retries; |
f2fdd67c PB |
1239 | |
1240 | if (retries >= 0) | |
1241 | rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries); | |
1242 | ||
1243 | return rc; | |
1244 | } | |
1245 | ||
7b8e19b6 | 1246 | static struct ieee802154_ops at86rf230_ops = { |
1247 | .owner = THIS_MODULE, | |
1248 | .xmit = at86rf230_xmit, | |
1249 | .ed = at86rf230_ed, | |
1250 | .set_channel = at86rf230_channel, | |
1251 | .start = at86rf230_start, | |
1252 | .stop = at86rf230_stop, | |
1486774d | 1253 | .set_hw_addr_filt = at86rf230_set_hw_addr_filt, |
640985ec AA |
1254 | .set_txpower = at86rf230_set_txpower, |
1255 | .set_lbt = at86rf230_set_lbt, | |
1256 | .set_cca_mode = at86rf230_set_cca_mode, | |
1257 | .set_cca_ed_level = at86rf230_set_cca_ed_level, | |
1258 | .set_csma_params = at86rf230_set_csma_params, | |
1259 | .set_frame_retries = at86rf230_set_frame_retries, | |
8fad346f PB |
1260 | }; |
1261 | ||
a53d1f7c | 1262 | static struct at86rf2xx_chip_data at86rf233_data = { |
7a4ef918 | 1263 | .t_sleep_cycle = 330, |
984e0c68 | 1264 | .t_channel_switch = 11, |
09e536cd | 1265 | .t_reset_to_off = 26, |
2e0571c0 AA |
1266 | .t_off_to_aack = 80, |
1267 | .t_off_to_tx_on = 80, | |
1d15d6b5 AA |
1268 | .t_frame = 4096, |
1269 | .t_p_ack = 545, | |
1270 | .t_sifs = 192, | |
7ad38b8f | 1271 | .t_lifs = 640, |
1d15d6b5 | 1272 | .t_tx_timeout = 2000, |
a53d1f7c AA |
1273 | .rssi_base_val = -91, |
1274 | .set_channel = at86rf23x_set_channel, | |
a7d7eda9 | 1275 | .get_desense_steps = at86rf23x_get_desens_steps |
a53d1f7c AA |
1276 | }; |
1277 | ||
1278 | static struct at86rf2xx_chip_data at86rf231_data = { | |
7a4ef918 | 1279 | .t_sleep_cycle = 330, |
984e0c68 | 1280 | .t_channel_switch = 24, |
09e536cd | 1281 | .t_reset_to_off = 37, |
2e0571c0 AA |
1282 | .t_off_to_aack = 110, |
1283 | .t_off_to_tx_on = 110, | |
1d15d6b5 AA |
1284 | .t_frame = 4096, |
1285 | .t_p_ack = 545, | |
1286 | .t_sifs = 192, | |
7ad38b8f | 1287 | .t_lifs = 640, |
1d15d6b5 | 1288 | .t_tx_timeout = 2000, |
a53d1f7c AA |
1289 | .rssi_base_val = -91, |
1290 | .set_channel = at86rf23x_set_channel, | |
a7d7eda9 | 1291 | .get_desense_steps = at86rf23x_get_desens_steps |
a53d1f7c AA |
1292 | }; |
1293 | ||
1294 | static struct at86rf2xx_chip_data at86rf212_data = { | |
7a4ef918 | 1295 | .t_sleep_cycle = 330, |
984e0c68 | 1296 | .t_channel_switch = 11, |
09e536cd | 1297 | .t_reset_to_off = 26, |
2e0571c0 AA |
1298 | .t_off_to_aack = 200, |
1299 | .t_off_to_tx_on = 200, | |
1d15d6b5 AA |
1300 | .t_frame = 4096, |
1301 | .t_p_ack = 545, | |
1302 | .t_sifs = 192, | |
7ad38b8f | 1303 | .t_lifs = 640, |
1d15d6b5 | 1304 | .t_tx_timeout = 2000, |
a53d1f7c AA |
1305 | .rssi_base_val = -100, |
1306 | .set_channel = at86rf212_set_channel, | |
a7d7eda9 | 1307 | .get_desense_steps = at86rf212_get_desens_steps |
a53d1f7c AA |
1308 | }; |
1309 | ||
7b8e19b6 | 1310 | static int at86rf230_hw_init(struct at86rf230_local *lp) |
1311 | { | |
1db0558e | 1312 | int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH; |
f76014f7 | 1313 | unsigned int dvdd; |
f2fdd67c | 1314 | u8 csma_seed[2]; |
7b8e19b6 | 1315 | |
09e536cd | 1316 | rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF); |
7dcbd22a PB |
1317 | if (rc) |
1318 | return rc; | |
7b8e19b6 | 1319 | |
4af619ae | 1320 | irq_type = irq_get_trigger_type(lp->spi->irq); |
1db0558e | 1321 | if (irq_type == IRQ_TYPE_EDGE_FALLING) |
43b5abe0 | 1322 | irq_pol = IRQ_ACTIVE_LOW; |
43b5abe0 | 1323 | |
18c65049 | 1324 | rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol); |
43b5abe0 SH |
1325 | if (rc) |
1326 | return rc; | |
1327 | ||
6bd2b132 AA |
1328 | rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1); |
1329 | if (rc) | |
1330 | return rc; | |
1331 | ||
057dad6f | 1332 | rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END); |
7b8e19b6 | 1333 | if (rc) |
1334 | return rc; | |
1335 | ||
f2fdd67c PB |
1336 | get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed)); |
1337 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]); | |
1338 | if (rc) | |
1339 | return rc; | |
1340 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]); | |
1341 | if (rc) | |
1342 | return rc; | |
1343 | ||
7b8e19b6 | 1344 | /* CLKM changes are applied immediately */ |
1345 | rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00); | |
1346 | if (rc) | |
1347 | return rc; | |
1348 | ||
1349 | /* Turn CLKM Off */ | |
1350 | rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00); | |
1351 | if (rc) | |
1352 | return rc; | |
1353 | /* Wait the next SLEEP cycle */ | |
7a4ef918 AA |
1354 | usleep_range(lp->data->t_sleep_cycle, |
1355 | lp->data->t_sleep_cycle + 100); | |
7b8e19b6 | 1356 | |
1cc9fc53 | 1357 | rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd); |
7b8e19b6 | 1358 | if (rc) |
1359 | return rc; | |
1cc9fc53 | 1360 | if (!dvdd) { |
7b8e19b6 | 1361 | dev_err(&lp->spi->dev, "DVDD error\n"); |
1362 | return -EINVAL; | |
1363 | } | |
1364 | ||
7b8e19b6 | 1365 | return 0; |
1366 | } | |
1367 | ||
fa2d3e94 AA |
1368 | static struct at86rf230_platform_data * |
1369 | at86rf230_get_pdata(struct spi_device *spi) | |
1370 | { | |
1371 | struct at86rf230_platform_data *pdata; | |
fa2d3e94 AA |
1372 | |
1373 | if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) | |
1374 | return spi->dev.platform_data; | |
1375 | ||
1376 | pdata = devm_kzalloc(&spi->dev, sizeof(*pdata), GFP_KERNEL); | |
1377 | if (!pdata) | |
1378 | goto done; | |
1379 | ||
1380 | pdata->rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0); | |
1381 | pdata->slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0); | |
1382 | ||
fa2d3e94 AA |
1383 | spi->dev.platform_data = pdata; |
1384 | done: | |
1385 | return pdata; | |
1386 | } | |
1387 | ||
c8ee0f56 AA |
1388 | static int |
1389 | at86rf230_detect_device(struct at86rf230_local *lp) | |
1390 | { | |
1391 | unsigned int part, version, val; | |
1392 | u16 man_id = 0; | |
1393 | const char *chip; | |
1394 | int rc; | |
1395 | ||
1396 | rc = __at86rf230_read(lp, RG_MAN_ID_0, &val); | |
1397 | if (rc) | |
1398 | return rc; | |
1399 | man_id |= val; | |
1400 | ||
1401 | rc = __at86rf230_read(lp, RG_MAN_ID_1, &val); | |
1402 | if (rc) | |
1403 | return rc; | |
1404 | man_id |= (val << 8); | |
1405 | ||
1406 | rc = __at86rf230_read(lp, RG_PART_NUM, &part); | |
1407 | if (rc) | |
1408 | return rc; | |
1409 | ||
1410 | rc = __at86rf230_read(lp, RG_PART_NUM, &version); | |
1411 | if (rc) | |
1412 | return rc; | |
1413 | ||
1414 | if (man_id != 0x001f) { | |
1415 | dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n", | |
1416 | man_id >> 8, man_id & 0xFF); | |
1417 | return -EINVAL; | |
1418 | } | |
1419 | ||
c8ee0f56 AA |
1420 | lp->dev->extra_tx_headroom = 0; |
1421 | lp->dev->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK | | |
1422 | IEEE802154_HW_TXPOWER | IEEE802154_HW_CSMA; | |
1423 | ||
1424 | switch (part) { | |
1425 | case 2: | |
1426 | chip = "at86rf230"; | |
1427 | rc = -ENOTSUPP; | |
1428 | break; | |
1429 | case 3: | |
1430 | chip = "at86rf231"; | |
a53d1f7c | 1431 | lp->data = &at86rf231_data; |
c8ee0f56 AA |
1432 | lp->dev->phy->channels_supported[0] = 0x7FFF800; |
1433 | break; | |
1434 | case 7: | |
1435 | chip = "at86rf212"; | |
1436 | if (version == 1) { | |
a53d1f7c | 1437 | lp->data = &at86rf212_data; |
c8ee0f56 AA |
1438 | lp->dev->flags |= IEEE802154_HW_LBT; |
1439 | lp->dev->phy->channels_supported[0] = 0x00007FF; | |
1440 | lp->dev->phy->channels_supported[2] = 0x00007FF; | |
1441 | } else { | |
1442 | rc = -ENOTSUPP; | |
1443 | } | |
1444 | break; | |
1445 | case 11: | |
1446 | chip = "at86rf233"; | |
a53d1f7c | 1447 | lp->data = &at86rf233_data; |
c8ee0f56 AA |
1448 | lp->dev->phy->channels_supported[0] = 0x7FFF800; |
1449 | break; | |
1450 | default: | |
1451 | chip = "unkown"; | |
1452 | rc = -ENOTSUPP; | |
1453 | break; | |
1454 | } | |
1455 | ||
1456 | dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version); | |
1457 | ||
1458 | return rc; | |
1459 | } | |
1460 | ||
1d15d6b5 AA |
1461 | static void |
1462 | at86rf230_setup_spi_messages(struct at86rf230_local *lp) | |
1463 | { | |
2e0571c0 AA |
1464 | lp->state.lp = lp; |
1465 | spi_message_init(&lp->state.msg); | |
1466 | lp->state.msg.context = &lp->state; | |
1467 | lp->state.trx.tx_buf = lp->state.buf; | |
1468 | lp->state.trx.rx_buf = lp->state.buf; | |
1469 | spi_message_add_tail(&lp->state.trx, &lp->state.msg); | |
1470 | ||
1d15d6b5 AA |
1471 | lp->irq.lp = lp; |
1472 | spi_message_init(&lp->irq.msg); | |
1473 | lp->irq.msg.context = &lp->irq; | |
1474 | lp->irq.trx.tx_buf = lp->irq.buf; | |
1475 | lp->irq.trx.rx_buf = lp->irq.buf; | |
1476 | spi_message_add_tail(&lp->irq.trx, &lp->irq.msg); | |
1477 | ||
1478 | lp->tx.lp = lp; | |
1479 | spi_message_init(&lp->tx.msg); | |
1480 | lp->tx.msg.context = &lp->tx; | |
1481 | lp->tx.trx.tx_buf = lp->tx.buf; | |
1482 | lp->tx.trx.rx_buf = lp->tx.buf; | |
1483 | spi_message_add_tail(&lp->tx.trx, &lp->tx.msg); | |
1484 | } | |
1485 | ||
bb1f4606 | 1486 | static int at86rf230_probe(struct spi_device *spi) |
7b8e19b6 | 1487 | { |
43b5abe0 | 1488 | struct at86rf230_platform_data *pdata; |
7b8e19b6 | 1489 | struct ieee802154_dev *dev; |
1490 | struct at86rf230_local *lp; | |
f76014f7 | 1491 | unsigned int status; |
4af619ae | 1492 | int rc, irq_type; |
7b8e19b6 | 1493 | |
1494 | if (!spi->irq) { | |
1495 | dev_err(&spi->dev, "no IRQ specified\n"); | |
1496 | return -EINVAL; | |
1497 | } | |
1498 | ||
fa2d3e94 | 1499 | pdata = at86rf230_get_pdata(spi); |
43b5abe0 SH |
1500 | if (!pdata) { |
1501 | dev_err(&spi->dev, "no platform_data\n"); | |
1502 | return -EINVAL; | |
1503 | } | |
1504 | ||
3fa27571 | 1505 | if (gpio_is_valid(pdata->rstn)) { |
0679e29b AA |
1506 | rc = devm_gpio_request_one(&spi->dev, pdata->rstn, |
1507 | GPIOF_OUT_INIT_HIGH, "rstn"); | |
3fa27571 AA |
1508 | if (rc) |
1509 | return rc; | |
1510 | } | |
7b8e19b6 | 1511 | |
8fad346f | 1512 | if (gpio_is_valid(pdata->slp_tr)) { |
0679e29b AA |
1513 | rc = devm_gpio_request_one(&spi->dev, pdata->slp_tr, |
1514 | GPIOF_OUT_INIT_LOW, "slp_tr"); | |
7b8e19b6 | 1515 | if (rc) |
0679e29b | 1516 | return rc; |
7b8e19b6 | 1517 | } |
1518 | ||
1519 | /* Reset */ | |
3fa27571 AA |
1520 | if (gpio_is_valid(pdata->rstn)) { |
1521 | udelay(1); | |
1522 | gpio_set_value(pdata->rstn, 0); | |
1523 | udelay(1); | |
1524 | gpio_set_value(pdata->rstn, 1); | |
1525 | usleep_range(120, 240); | |
1526 | } | |
7b8e19b6 | 1527 | |
640985ec AA |
1528 | dev = ieee802154_alloc_device(sizeof(*lp), &at86rf230_ops); |
1529 | if (!dev) | |
1530 | return -ENOMEM; | |
1531 | ||
1532 | lp = dev->priv; | |
1533 | lp->dev = dev; | |
640985ec | 1534 | lp->spi = spi; |
640985ec | 1535 | dev->parent = &spi->dev; |
8fad346f | 1536 | |
f76014f7 AA |
1537 | lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config); |
1538 | if (IS_ERR(lp->regmap)) { | |
1539 | rc = PTR_ERR(lp->regmap); | |
1540 | dev_err(&spi->dev, "Failed to allocate register map: %d\n", | |
1541 | rc); | |
1542 | goto free_dev; | |
1543 | } | |
1544 | ||
1d15d6b5 AA |
1545 | at86rf230_setup_spi_messages(lp); |
1546 | ||
c8ee0f56 AA |
1547 | rc = at86rf230_detect_device(lp); |
1548 | if (rc < 0) | |
1549 | goto free_dev; | |
1550 | ||
8fad346f PB |
1551 | spin_lock_init(&lp->lock); |
1552 | init_completion(&lp->tx_complete); | |
2e0571c0 | 1553 | init_completion(&lp->state_complete); |
8fad346f PB |
1554 | |
1555 | spi_set_drvdata(spi, lp); | |
1556 | ||
7b8e19b6 | 1557 | rc = at86rf230_hw_init(lp); |
1558 | if (rc) | |
1d15d6b5 | 1559 | goto free_dev; |
7b8e19b6 | 1560 | |
19626946 AA |
1561 | /* Read irq status register to reset irq line */ |
1562 | rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status); | |
7b8e19b6 | 1563 | if (rc) |
1d15d6b5 | 1564 | goto free_dev; |
7b8e19b6 | 1565 | |
1d15d6b5 AA |
1566 | irq_type = irq_get_trigger_type(spi->irq); |
1567 | if (!irq_type) | |
1568 | irq_type = IRQF_TRIGGER_RISING; | |
1569 | ||
1570 | rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr, | |
1571 | IRQF_SHARED | irq_type, dev_name(&spi->dev), lp); | |
057dad6f | 1572 | if (rc) |
1d15d6b5 | 1573 | goto free_dev; |
057dad6f | 1574 | |
7b8e19b6 | 1575 | rc = ieee802154_register_device(lp->dev); |
1576 | if (rc) | |
1d15d6b5 | 1577 | goto free_dev; |
7b8e19b6 | 1578 | |
1579 | return rc; | |
1580 | ||
640985ec | 1581 | free_dev: |
7b8e19b6 | 1582 | ieee802154_free_device(lp->dev); |
8fad346f | 1583 | |
7b8e19b6 | 1584 | return rc; |
1585 | } | |
1586 | ||
bb1f4606 | 1587 | static int at86rf230_remove(struct spi_device *spi) |
7b8e19b6 | 1588 | { |
1589 | struct at86rf230_local *lp = spi_get_drvdata(spi); | |
1590 | ||
17e84a92 AA |
1591 | /* mask all at86rf230 irq's */ |
1592 | at86rf230_write_subreg(lp, SR_IRQ_MASK, 0); | |
7b8e19b6 | 1593 | ieee802154_unregister_device(lp->dev); |
7b8e19b6 | 1594 | ieee802154_free_device(lp->dev); |
7b8e19b6 | 1595 | dev_dbg(&spi->dev, "unregistered at86rf230\n"); |
0679e29b | 1596 | |
7b8e19b6 | 1597 | return 0; |
1598 | } | |
1599 | ||
1086b4f6 | 1600 | static const struct of_device_id at86rf230_of_match[] = { |
fa2d3e94 AA |
1601 | { .compatible = "atmel,at86rf230", }, |
1602 | { .compatible = "atmel,at86rf231", }, | |
1603 | { .compatible = "atmel,at86rf233", }, | |
1604 | { .compatible = "atmel,at86rf212", }, | |
1605 | { }, | |
1606 | }; | |
835cb7d2 | 1607 | MODULE_DEVICE_TABLE(of, at86rf230_of_match); |
fa2d3e94 | 1608 | |
90b15520 AA |
1609 | static const struct spi_device_id at86rf230_device_id[] = { |
1610 | { .name = "at86rf230", }, | |
1611 | { .name = "at86rf231", }, | |
1612 | { .name = "at86rf233", }, | |
1613 | { .name = "at86rf212", }, | |
1614 | { }, | |
1615 | }; | |
1616 | MODULE_DEVICE_TABLE(spi, at86rf230_device_id); | |
1617 | ||
7b8e19b6 | 1618 | static struct spi_driver at86rf230_driver = { |
90b15520 | 1619 | .id_table = at86rf230_device_id, |
7b8e19b6 | 1620 | .driver = { |
fa2d3e94 | 1621 | .of_match_table = of_match_ptr(at86rf230_of_match), |
7b8e19b6 | 1622 | .name = "at86rf230", |
1623 | .owner = THIS_MODULE, | |
1624 | }, | |
1625 | .probe = at86rf230_probe, | |
bb1f4606 | 1626 | .remove = at86rf230_remove, |
7b8e19b6 | 1627 | }; |
1628 | ||
395a5738 | 1629 | module_spi_driver(at86rf230_driver); |
7b8e19b6 | 1630 | |
1631 | MODULE_DESCRIPTION("AT86RF230 Transceiver Driver"); | |
1632 | MODULE_LICENSE("GPL v2"); |