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Merge branch 'pkt_sched_cond_resched'
[deliverable/linux.git] / drivers / net / ieee802154 / at86rf230.c
CommitLineData
7b8e19b6 1/*
2 * AT86RF230/RF231 driver
3 *
4 * Copyright (C) 2009-2012 Siemens AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Written by:
20 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
21 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
22 */
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/interrupt.h>
26#include <linux/gpio.h>
27#include <linux/delay.h>
28#include <linux/mutex.h>
29#include <linux/workqueue.h>
30#include <linux/spinlock.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/at86rf230.h>
33#include <linux/skbuff.h>
34
35#include <net/mac802154.h>
36#include <net/wpan-phy.h>
37
38struct at86rf230_local {
39 struct spi_device *spi;
7b8e19b6 40
41 u8 part;
42 u8 vers;
43
44 u8 buf[2];
45 struct mutex bmux;
46
47 struct work_struct irqwork;
48 struct completion tx_complete;
49
50 struct ieee802154_dev *dev;
51
52 spinlock_t lock;
057dad6f 53 bool irq_busy;
7b8e19b6 54 bool is_tx;
f2fdd67c 55 bool tx_aret;
6ca00197
PB		 56
57 int rssi_base_val;
7b8e19b6 58};
59
44a6bd86 60static bool is_rf212(struct at86rf230_local *local)
8fad346f
PB		 61{
62 return local->part == 7;
63}
64
7b8e19b6 65#define RG_TRX_STATUS (0x01)
66#define SR_TRX_STATUS 0x01, 0x1f, 0
67#define SR_RESERVED_01_3 0x01, 0x20, 5
68#define SR_CCA_STATUS 0x01, 0x40, 6
69#define SR_CCA_DONE 0x01, 0x80, 7
70#define RG_TRX_STATE (0x02)
71#define SR_TRX_CMD 0x02, 0x1f, 0
72#define SR_TRAC_STATUS 0x02, 0xe0, 5
73#define RG_TRX_CTRL_0 (0x03)
74#define SR_CLKM_CTRL 0x03, 0x07, 0
75#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
76#define SR_PAD_IO_CLKM 0x03, 0x30, 4
77#define SR_PAD_IO 0x03, 0xc0, 6
78#define RG_TRX_CTRL_1 (0x04)
79#define SR_IRQ_POLARITY 0x04, 0x01, 0
80#define SR_IRQ_MASK_MODE 0x04, 0x02, 1
81#define SR_SPI_CMD_MODE 0x04, 0x0c, 2
82#define SR_RX_BL_CTRL 0x04, 0x10, 4
83#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
84#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
85#define SR_PA_EXT_EN 0x04, 0x80, 7
86#define RG_PHY_TX_PWR (0x05)
87#define SR_TX_PWR 0x05, 0x0f, 0
88#define SR_PA_LT 0x05, 0x30, 4
89#define SR_PA_BUF_LT 0x05, 0xc0, 6
90#define RG_PHY_RSSI (0x06)
91#define SR_RSSI 0x06, 0x1f, 0
92#define SR_RND_VALUE 0x06, 0x60, 5
93#define SR_RX_CRC_VALID 0x06, 0x80, 7
94#define RG_PHY_ED_LEVEL (0x07)
95#define SR_ED_LEVEL 0x07, 0xff, 0
96#define RG_PHY_CC_CCA (0x08)
97#define SR_CHANNEL 0x08, 0x1f, 0
98#define SR_CCA_MODE 0x08, 0x60, 5
99#define SR_CCA_REQUEST 0x08, 0x80, 7
100#define RG_CCA_THRES (0x09)
101#define SR_CCA_ED_THRES 0x09, 0x0f, 0
102#define SR_RESERVED_09_1 0x09, 0xf0, 4
103#define RG_RX_CTRL (0x0a)
104#define SR_PDT_THRES 0x0a, 0x0f, 0
105#define SR_RESERVED_0a_1 0x0a, 0xf0, 4
106#define RG_SFD_VALUE (0x0b)
107#define SR_SFD_VALUE 0x0b, 0xff, 0
108#define RG_TRX_CTRL_2 (0x0c)
109#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
8fad346f
PB		 110#define SR_SUB_MODE 0x0c, 0x04, 2
111#define SR_BPSK_QPSK 0x0c, 0x08, 3
643e53c2
PB		 112#define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
113#define SR_RESERVED_0c_5 0x0c, 0x60, 5
7b8e19b6 114#define SR_RX_SAFE_MODE 0x0c, 0x80, 7
115#define RG_ANT_DIV (0x0d)
116#define SR_ANT_CTRL 0x0d, 0x03, 0
117#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
118#define SR_ANT_DIV_EN 0x0d, 0x08, 3
119#define SR_RESERVED_0d_2 0x0d, 0x70, 4
120#define SR_ANT_SEL 0x0d, 0x80, 7
121#define RG_IRQ_MASK (0x0e)
122#define SR_IRQ_MASK 0x0e, 0xff, 0
123#define RG_IRQ_STATUS (0x0f)
124#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
125#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
126#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
127#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
128#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
129#define SR_IRQ_5_AMI 0x0f, 0x20, 5
130#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
131#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
132#define RG_VREG_CTRL (0x10)
133#define SR_RESERVED_10_6 0x10, 0x03, 0
134#define SR_DVDD_OK 0x10, 0x04, 2
135#define SR_DVREG_EXT 0x10, 0x08, 3
136#define SR_RESERVED_10_3 0x10, 0x30, 4
137#define SR_AVDD_OK 0x10, 0x40, 6
138#define SR_AVREG_EXT 0x10, 0x80, 7
139#define RG_BATMON (0x11)
140#define SR_BATMON_VTH 0x11, 0x0f, 0
141#define SR_BATMON_HR 0x11, 0x10, 4
142#define SR_BATMON_OK 0x11, 0x20, 5
143#define SR_RESERVED_11_1 0x11, 0xc0, 6
144#define RG_XOSC_CTRL (0x12)
145#define SR_XTAL_TRIM 0x12, 0x0f, 0
146#define SR_XTAL_MODE 0x12, 0xf0, 4
147#define RG_RX_SYN (0x15)
148#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
149#define SR_RESERVED_15_2 0x15, 0x70, 4
150#define SR_RX_PDT_DIS 0x15, 0x80, 7
151#define RG_XAH_CTRL_1 (0x17)
152#define SR_RESERVED_17_8 0x17, 0x01, 0
153#define SR_AACK_PROM_MODE 0x17, 0x02, 1
154#define SR_AACK_ACK_TIME 0x17, 0x04, 2
155#define SR_RESERVED_17_5 0x17, 0x08, 3
156#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
157#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
84dda3c6 158#define SR_CSMA_LBT_MODE 0x17, 0x40, 6
7b8e19b6 159#define SR_RESERVED_17_1 0x17, 0x80, 7
160#define RG_FTN_CTRL (0x18)
161#define SR_RESERVED_18_2 0x18, 0x7f, 0
162#define SR_FTN_START 0x18, 0x80, 7
163#define RG_PLL_CF (0x1a)
164#define SR_RESERVED_1a_2 0x1a, 0x7f, 0
165#define SR_PLL_CF_START 0x1a, 0x80, 7
166#define RG_PLL_DCU (0x1b)
167#define SR_RESERVED_1b_3 0x1b, 0x3f, 0
168#define SR_RESERVED_1b_2 0x1b, 0x40, 6
169#define SR_PLL_DCU_START 0x1b, 0x80, 7
170#define RG_PART_NUM (0x1c)
171#define SR_PART_NUM 0x1c, 0xff, 0
172#define RG_VERSION_NUM (0x1d)
173#define SR_VERSION_NUM 0x1d, 0xff, 0
174#define RG_MAN_ID_0 (0x1e)
175#define SR_MAN_ID_0 0x1e, 0xff, 0
176#define RG_MAN_ID_1 (0x1f)
177#define SR_MAN_ID_1 0x1f, 0xff, 0
178#define RG_SHORT_ADDR_0 (0x20)
179#define SR_SHORT_ADDR_0 0x20, 0xff, 0
180#define RG_SHORT_ADDR_1 (0x21)
181#define SR_SHORT_ADDR_1 0x21, 0xff, 0
182#define RG_PAN_ID_0 (0x22)
183#define SR_PAN_ID_0 0x22, 0xff, 0
184#define RG_PAN_ID_1 (0x23)
185#define SR_PAN_ID_1 0x23, 0xff, 0
186#define RG_IEEE_ADDR_0 (0x24)
187#define SR_IEEE_ADDR_0 0x24, 0xff, 0
188#define RG_IEEE_ADDR_1 (0x25)
189#define SR_IEEE_ADDR_1 0x25, 0xff, 0
190#define RG_IEEE_ADDR_2 (0x26)
191#define SR_IEEE_ADDR_2 0x26, 0xff, 0
192#define RG_IEEE_ADDR_3 (0x27)
193#define SR_IEEE_ADDR_3 0x27, 0xff, 0
194#define RG_IEEE_ADDR_4 (0x28)
195#define SR_IEEE_ADDR_4 0x28, 0xff, 0
196#define RG_IEEE_ADDR_5 (0x29)
197#define SR_IEEE_ADDR_5 0x29, 0xff, 0
198#define RG_IEEE_ADDR_6 (0x2a)
199#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
200#define RG_IEEE_ADDR_7 (0x2b)
201#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
202#define RG_XAH_CTRL_0 (0x2c)
203#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
204#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
205#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
206#define RG_CSMA_SEED_0 (0x2d)
207#define SR_CSMA_SEED_0 0x2d, 0xff, 0
208#define RG_CSMA_SEED_1 (0x2e)
209#define SR_CSMA_SEED_1 0x2e, 0x07, 0
210#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
211#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
212#define SR_AACK_SET_PD 0x2e, 0x20, 5
213#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
214#define RG_CSMA_BE (0x2f)
215#define SR_MIN_BE 0x2f, 0x0f, 0
216#define SR_MAX_BE 0x2f, 0xf0, 4
217
218#define CMD_REG 0x80
219#define CMD_REG_MASK 0x3f
220#define CMD_WRITE 0x40
221#define CMD_FB 0x20
222
223#define IRQ_BAT_LOW (1 << 7)
224#define IRQ_TRX_UR (1 << 6)
225#define IRQ_AMI (1 << 5)
226#define IRQ_CCA_ED (1 << 4)
227#define IRQ_TRX_END (1 << 3)
228#define IRQ_RX_START (1 << 2)
229#define IRQ_PLL_UNL (1 << 1)
230#define IRQ_PLL_LOCK (1 << 0)
231
43b5abe0
SH		 232#define IRQ_ACTIVE_HIGH 0
233#define IRQ_ACTIVE_LOW 1
234
7b8e19b6 235#define STATE_P_ON 0x00 /* BUSY */
236#define STATE_BUSY_RX 0x01
237#define STATE_BUSY_TX 0x02
238#define STATE_FORCE_TRX_OFF 0x03
239#define STATE_FORCE_TX_ON 0x04 /* IDLE */
240/* 0x05 */ /* INVALID_PARAMETER */
241#define STATE_RX_ON 0x06
242/* 0x07 */ /* SUCCESS */
243#define STATE_TRX_OFF 0x08
244#define STATE_TX_ON 0x09
245/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
246#define STATE_SLEEP 0x0F
247#define STATE_BUSY_RX_AACK 0x11
248#define STATE_BUSY_TX_ARET 0x12
028889b0 249#define STATE_RX_AACK_ON 0x16
250#define STATE_TX_ARET_ON 0x19
7b8e19b6 251#define STATE_RX_ON_NOCLK 0x1C
252#define STATE_RX_AACK_ON_NOCLK 0x1D
253#define STATE_BUSY_RX_AACK_NOCLK 0x1E
254#define STATE_TRANSITION_IN_PROGRESS 0x1F
255
8fad346f
PB		 256static int
257__at86rf230_detect_device(struct spi_device *spi, u16 *man_id, u8 *part,
258 u8 *version)
259{
260 u8 data[4];
261 u8 *buf = kmalloc(2, GFP_KERNEL);
262 int status;
263 struct spi_message msg;
264 struct spi_transfer xfer = {
265 .len = 2,
266 .tx_buf = buf,
267 .rx_buf = buf,
268 };
269 u8 reg;
270
271 if (!buf)
272 return -ENOMEM;
273
274 for (reg = RG_PART_NUM; reg <= RG_MAN_ID_1; reg++) {
275 buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
276 buf[1] = 0xff;
277 dev_vdbg(&spi->dev, "buf[0] = %02x\n", buf[0]);
278 spi_message_init(&msg);
279 spi_message_add_tail(&xfer, &msg);
280
281 status = spi_sync(spi, &msg);
282 dev_vdbg(&spi->dev, "status = %d\n", status);
283 if (msg.status)
284 status = msg.status;
285
286 dev_vdbg(&spi->dev, "status = %d\n", status);
287 dev_vdbg(&spi->dev, "buf[0] = %02x\n", buf[0]);
288 dev_vdbg(&spi->dev, "buf[1] = %02x\n", buf[1]);
289
290 if (status == 0)
291 data[reg - RG_PART_NUM] = buf[1];
292 else
293 break;
294 }
295
296 if (status == 0) {
297 *part = data[0];
298 *version = data[1];
299 *man_id = (data[3] << 8) | data[2];
300 }
301
302 kfree(buf);
303
304 return status;
305}
306
7b8e19b6 307static int
308__at86rf230_write(struct at86rf230_local *lp, u8 addr, u8 data)
309{
310 u8 *buf = lp->buf;
311 int status;
312 struct spi_message msg;
313 struct spi_transfer xfer = {
314 .len = 2,
315 .tx_buf = buf,
316 };
317
318 buf[0] = (addr & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
319 buf[1] = data;
320 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
321 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
322 spi_message_init(&msg);
323 spi_message_add_tail(&xfer, &msg);
324
325 status = spi_sync(lp->spi, &msg);
326 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
327 if (msg.status)
328 status = msg.status;
329
330 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
331 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
332 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
333
334 return status;
335}
336
337static int
338__at86rf230_read_subreg(struct at86rf230_local *lp,
339 u8 addr, u8 mask, int shift, u8 *data)
340{
341 u8 *buf = lp->buf;
342 int status;
343 struct spi_message msg;
344 struct spi_transfer xfer = {
345 .len = 2,
346 .tx_buf = buf,
347 .rx_buf = buf,
348 };
349
350 buf[0] = (addr & CMD_REG_MASK) | CMD_REG;
351 buf[1] = 0xff;
352 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
353 spi_message_init(&msg);
354 spi_message_add_tail(&xfer, &msg);
355
356 status = spi_sync(lp->spi, &msg);
357 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
358 if (msg.status)
359 status = msg.status;
360
361 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
362 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
363 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
364
365 if (status == 0)
366 *data = buf[1];
367
368 return status;
369}
370
371static int
372at86rf230_read_subreg(struct at86rf230_local *lp,
373 u8 addr, u8 mask, int shift, u8 *data)
374{
375 int status;
376
377 mutex_lock(&lp->bmux);
378 status = __at86rf230_read_subreg(lp, addr, mask, shift, data);
379 mutex_unlock(&lp->bmux);
380
381 return status;
382}
383
384static int
385at86rf230_write_subreg(struct at86rf230_local *lp,
386 u8 addr, u8 mask, int shift, u8 data)
387{
388 int status;
389 u8 val;
390
391 mutex_lock(&lp->bmux);
392 status = __at86rf230_read_subreg(lp, addr, 0xff, 0, &val);
393 if (status)
394 goto out;
395
396 val &= ~mask;
397 val |= (data << shift) & mask;
398
399 status = __at86rf230_write(lp, addr, val);
400out:
401 mutex_unlock(&lp->bmux);
402
403 return status;
404}
405
406static int
407at86rf230_write_fbuf(struct at86rf230_local *lp, u8 *data, u8 len)
408{
409 u8 *buf = lp->buf;
410 int status;
411 struct spi_message msg;
412 struct spi_transfer xfer_head = {
413 .len = 2,
414 .tx_buf = buf,
415
416 };
417 struct spi_transfer xfer_buf = {
418 .len = len,
419 .tx_buf = data,
420 };
421
422 mutex_lock(&lp->bmux);
423 buf[0] = CMD_WRITE | CMD_FB;
424 buf[1] = len + 2; /* 2 bytes for CRC that isn't written */
425
426 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
427 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
428
429 spi_message_init(&msg);
430 spi_message_add_tail(&xfer_head, &msg);
431 spi_message_add_tail(&xfer_buf, &msg);
432
433 status = spi_sync(lp->spi, &msg);
434 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
435 if (msg.status)
436 status = msg.status;
437
438 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
439 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
440 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
441
442 mutex_unlock(&lp->bmux);
443 return status;
444}
445
446static int
447at86rf230_read_fbuf(struct at86rf230_local *lp, u8 *data, u8 *len, u8 *lqi)
448{
449 u8 *buf = lp->buf;
450 int status;
451 struct spi_message msg;
452 struct spi_transfer xfer_head = {
453 .len = 2,
454 .tx_buf = buf,
455 .rx_buf = buf,
456 };
457 struct spi_transfer xfer_head1 = {
458 .len = 2,
459 .tx_buf = buf,
460 .rx_buf = buf,
461 };
462 struct spi_transfer xfer_buf = {
463 .len = 0,
464 .rx_buf = data,
465 };
466
467 mutex_lock(&lp->bmux);
468
469 buf[0] = CMD_FB;
470 buf[1] = 0x00;
471
472 spi_message_init(&msg);
473 spi_message_add_tail(&xfer_head, &msg);
474
475 status = spi_sync(lp->spi, &msg);
476 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
477
478 xfer_buf.len = *(buf + 1) + 1;
479 *len = buf[1];
480
481 buf[0] = CMD_FB;
482 buf[1] = 0x00;
483
484 spi_message_init(&msg);
485 spi_message_add_tail(&xfer_head1, &msg);
486 spi_message_add_tail(&xfer_buf, &msg);
487
488 status = spi_sync(lp->spi, &msg);
489
490 if (msg.status)
491 status = msg.status;
492
493 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
494 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
495 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
496
497 if (status) {
498 if (lqi && (*len > lp->buf[1]))
499 *lqi = data[lp->buf[1]];
500 }
501 mutex_unlock(&lp->bmux);
502
503 return status;
504}
505
506static int
507at86rf230_ed(struct ieee802154_dev *dev, u8 *level)
508{
509 might_sleep();
510 BUG_ON(!level);
511 *level = 0xbe;
512 return 0;
513}
514
515static int
516at86rf230_state(struct ieee802154_dev *dev, int state)
517{
518 struct at86rf230_local *lp = dev->priv;
519 int rc;
520 u8 val;
521 u8 desired_status;
522
523 might_sleep();
524
525 if (state == STATE_FORCE_TX_ON)
526 desired_status = STATE_TX_ON;
527 else if (state == STATE_FORCE_TRX_OFF)
528 desired_status = STATE_TRX_OFF;
529 else
530 desired_status = state;
531
532 do {
533 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val);
534 if (rc)
535 goto err;
536 } while (val == STATE_TRANSITION_IN_PROGRESS);
537
538 if (val == desired_status)
539 return 0;
540
541 /* state is equal to phy states */
542 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, state);
543 if (rc)
544 goto err;
545
546 do {
547 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val);
548 if (rc)
549 goto err;
550 } while (val == STATE_TRANSITION_IN_PROGRESS);
551
552
f2fdd67c
PB		 553 if (val == desired_status ||
554 (desired_status == STATE_RX_ON && val == STATE_BUSY_RX) ||
555 (desired_status == STATE_RX_AACK_ON && val == STATE_BUSY_RX_AACK))
7b8e19b6 556 return 0;
557
558 pr_err("unexpected state change: %d, asked for %d\n", val, state);
559 return -EBUSY;
560
561err:
562 pr_err("error: %d\n", rc);
563 return rc;
564}
565
566static int
567at86rf230_start(struct ieee802154_dev *dev)
568{
569 struct at86rf230_local *lp = dev->priv;
570 u8 rc;
571
572 rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
573 if (rc)
574 return rc;
575
f2fdd67c
PB		 576 rc = at86rf230_state(dev, STATE_FORCE_TX_ON);
577 if (rc)
578 return rc;
579
5b520bbb 580 return at86rf230_state(dev, STATE_RX_AACK_ON);
7b8e19b6 581}
582
583static void
584at86rf230_stop(struct ieee802154_dev *dev)
585{
586 at86rf230_state(dev, STATE_FORCE_TRX_OFF);
587}
588
8fad346f
PB		 589static int
590at86rf230_set_channel(struct at86rf230_local *lp, int page, int channel)
591{
6ca00197
PB		 592 lp->rssi_base_val = -91;
593
8fad346f
PB		 594 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
595}
596
597static int
598at86rf212_set_channel(struct at86rf230_local *lp, int page, int channel)
599{
600 int rc;
601
602 if (channel == 0)
603 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
604 else
605 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
606 if (rc < 0)
607 return rc;
608
6ca00197 609 if (page == 0) {
643e53c2 610 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
6ca00197
PB		 611 lp->rssi_base_val = -100;
612 } else {
643e53c2 613 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
6ca00197
PB		 614 lp->rssi_base_val = -98;
615 }
643e53c2
PB		 616 if (rc < 0)
617 return rc;
618
8fad346f
PB		 619 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
620}
621
7b8e19b6 622static int
623at86rf230_channel(struct ieee802154_dev *dev, int page, int channel)
624{
625 struct at86rf230_local *lp = dev->priv;
626 int rc;
627
628 might_sleep();
629
8fad346f
PB		 630 if (page < 0 || page > 31 ||
631 !(lp->dev->phy->channels_supported[page] & BIT(channel))) {
7b8e19b6 632 WARN_ON(1);
633 return -EINVAL;
634 }
635
8fad346f
PB		 636 if (is_rf212(lp))
637 rc = at86rf212_set_channel(lp, page, channel);
638 else
639 rc = at86rf230_set_channel(lp, page, channel);
640 if (rc < 0)
641 return rc;
642
7b8e19b6 643 msleep(1); /* Wait for PLL */
644 dev->phy->current_channel = channel;
643e53c2 645 dev->phy->current_page = page;
7b8e19b6 646
647 return 0;
648}
649
650static int
651at86rf230_xmit(struct ieee802154_dev *dev, struct sk_buff *skb)
652{
653 struct at86rf230_local *lp = dev->priv;
654 int rc;
655 unsigned long flags;
656
5b00f2ee 657 spin_lock(&lp->lock);
057dad6f 658 if (lp->irq_busy) {
5b00f2ee 659 spin_unlock(&lp->lock);
660 return -EBUSY;
661 }
662 spin_unlock(&lp->lock);
663
7b8e19b6 664 might_sleep();
665
666 rc = at86rf230_state(dev, STATE_FORCE_TX_ON);
667 if (rc)
668 goto err;
669
670 spin_lock_irqsave(&lp->lock, flags);
671 lp->is_tx = 1;
16735d02 672 reinit_completion(&lp->tx_complete);
7b8e19b6 673 spin_unlock_irqrestore(&lp->lock, flags);
674
675 rc = at86rf230_write_fbuf(lp, skb->data, skb->len);
676 if (rc)
677 goto err_rx;
678
f2fdd67c
PB		 679 if (lp->tx_aret) {
680 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_TX_ARET_ON);
681 if (rc)
682 goto err_rx;
683 }
684
7b8e19b6 685 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_BUSY_TX);
686 if (rc)
687 goto err_rx;
688
689 rc = wait_for_completion_interruptible(&lp->tx_complete);
690 if (rc < 0)
691 goto err_rx;
692
693 rc = at86rf230_start(dev);
694
695 return rc;
696
697err_rx:
698 at86rf230_start(dev);
699err:
700 pr_err("error: %d\n", rc);
701
702 spin_lock_irqsave(&lp->lock, flags);
703 lp->is_tx = 0;
704 spin_unlock_irqrestore(&lp->lock, flags);
705
706 return rc;
707}
708
709static int at86rf230_rx(struct at86rf230_local *lp)
710{
711 u8 len = 128, lqi = 0;
7b8e19b6 712 struct sk_buff *skb;
713
714 skb = alloc_skb(len, GFP_KERNEL);
715
716 if (!skb)
717 return -ENOMEM;
718
5b00f2ee 719 if (at86rf230_read_fbuf(lp, skb_put(skb, len), &len, &lqi))
7b8e19b6 720 goto err;
7b8e19b6 721
722 if (len < 2)
723 goto err;
724
725 skb_trim(skb, len - 2); /* We do not put CRC into the frame */
726
727 ieee802154_rx_irqsafe(lp->dev, skb, lqi);
728
23c34215 729 dev_dbg(&lp->spi->dev, "READ_FBUF: %d %x\n", len, lqi);
7b8e19b6 730
731 return 0;
732err:
733 pr_debug("received frame is too small\n");
734
735 kfree_skb(skb);
736 return -EINVAL;
737}
738
1486774d 739static int
740at86rf230_set_hw_addr_filt(struct ieee802154_dev *dev,
741 struct ieee802154_hw_addr_filt *filt,
742 unsigned long changed)
743{
744 struct at86rf230_local *lp = dev->priv;
745
746 if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
747 dev_vdbg(&lp->spi->dev,
748 "at86rf230_set_hw_addr_filt called for saddr\n");
749 __at86rf230_write(lp, RG_SHORT_ADDR_0, filt->short_addr);
750 __at86rf230_write(lp, RG_SHORT_ADDR_1, filt->short_addr >> 8);
751 }
752
753 if (changed & IEEE802515_AFILT_PANID_CHANGED) {
754 dev_vdbg(&lp->spi->dev,
755 "at86rf230_set_hw_addr_filt called for pan id\n");
756 __at86rf230_write(lp, RG_PAN_ID_0, filt->pan_id);
757 __at86rf230_write(lp, RG_PAN_ID_1, filt->pan_id >> 8);
758 }
759
760 if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
761 dev_vdbg(&lp->spi->dev,
762 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
763 at86rf230_write_subreg(lp, SR_IEEE_ADDR_0, filt->ieee_addr[7]);
764 at86rf230_write_subreg(lp, SR_IEEE_ADDR_1, filt->ieee_addr[6]);
765 at86rf230_write_subreg(lp, SR_IEEE_ADDR_2, filt->ieee_addr[5]);
766 at86rf230_write_subreg(lp, SR_IEEE_ADDR_3, filt->ieee_addr[4]);
767 at86rf230_write_subreg(lp, SR_IEEE_ADDR_4, filt->ieee_addr[3]);
768 at86rf230_write_subreg(lp, SR_IEEE_ADDR_5, filt->ieee_addr[2]);
769 at86rf230_write_subreg(lp, SR_IEEE_ADDR_6, filt->ieee_addr[1]);
770 at86rf230_write_subreg(lp, SR_IEEE_ADDR_7, filt->ieee_addr[0]);
771 }
772
773 if (changed & IEEE802515_AFILT_PANC_CHANGED) {
774 dev_vdbg(&lp->spi->dev,
775 "at86rf230_set_hw_addr_filt called for panc change\n");
776 if (filt->pan_coord)
777 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
778 else
779 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
780 }
781
782 return 0;
783}
784
9b2777d6
PB		 785static int
786at86rf212_set_txpower(struct ieee802154_dev *dev, int db)
787{
788 struct at86rf230_local *lp = dev->priv;
9b2777d6
PB		 789
790 /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
791 * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
792 * 0dB.
793 * thus, supported values for db range from -26 to 5, for 31dB of
794 * reduction to 0dB of reduction.
795 */
796 if (db > 5 || db < -26)
797 return -EINVAL;
798
799 db = -(db - 5);
800
677676cd 801 return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db);
9b2777d6
PB		 802}
803
84dda3c6
PB		 804static int
805at86rf212_set_lbt(struct ieee802154_dev *dev, bool on)
806{
807 struct at86rf230_local *lp = dev->priv;
808
809 return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
810}
811
ba08fea5
PB		 812static int
813at86rf212_set_cca_mode(struct ieee802154_dev *dev, u8 mode)
814{
815 struct at86rf230_local *lp = dev->priv;
816
817 return at86rf230_write_subreg(lp, SR_CCA_MODE, mode);
818}
819
6ca00197
PB		 820static int
821at86rf212_set_cca_ed_level(struct ieee802154_dev *dev, s32 level)
822{
823 struct at86rf230_local *lp = dev->priv;
824 int desens_steps;
825
826 if (level < lp->rssi_base_val || level > 30)
827 return -EINVAL;
828
829 desens_steps = (level - lp->rssi_base_val) * 100 / 207;
830
831 return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, desens_steps);
832}
833
f2fdd67c
PB		 834static int
835at86rf212_set_csma_params(struct ieee802154_dev *dev, u8 min_be, u8 max_be,
836 u8 retries)
837{
838 struct at86rf230_local *lp = dev->priv;
839 int rc;
840
841 if (min_be > max_be || max_be > 8 || retries > 5)
842 return -EINVAL;
843
844 rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
845 if (rc)
846 return rc;
847
848 rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
849 if (rc)
850 return rc;
851
852 return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, max_be);
853}
854
855static int
856at86rf212_set_frame_retries(struct ieee802154_dev *dev, s8 retries)
857{
858 struct at86rf230_local *lp = dev->priv;
859 int rc = 0;
860
861 if (retries < -1 || retries > 15)
862 return -EINVAL;
863
864 lp->tx_aret = retries >= 0;
865
866 if (retries >= 0)
867 rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
868
869 return rc;
870}
871
7b8e19b6 872static struct ieee802154_ops at86rf230_ops = {
873 .owner = THIS_MODULE,
874 .xmit = at86rf230_xmit,
875 .ed = at86rf230_ed,
876 .set_channel = at86rf230_channel,
877 .start = at86rf230_start,
878 .stop = at86rf230_stop,
1486774d 879 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
7b8e19b6 880};
881
8fad346f
PB		 882static struct ieee802154_ops at86rf212_ops = {
883 .owner = THIS_MODULE,
884 .xmit = at86rf230_xmit,
885 .ed = at86rf230_ed,
886 .set_channel = at86rf230_channel,
887 .start = at86rf230_start,
888 .stop = at86rf230_stop,
889 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
9b2777d6 890 .set_txpower = at86rf212_set_txpower,
84dda3c6 891 .set_lbt = at86rf212_set_lbt,
ba08fea5 892 .set_cca_mode = at86rf212_set_cca_mode,
6ca00197 893 .set_cca_ed_level = at86rf212_set_cca_ed_level,
f2fdd67c
PB		 894 .set_csma_params = at86rf212_set_csma_params,
895 .set_frame_retries = at86rf212_set_frame_retries,
8fad346f
PB		 896};
897
7b8e19b6 898static void at86rf230_irqwork(struct work_struct *work)
899{
900 struct at86rf230_local *lp =
901 container_of(work, struct at86rf230_local, irqwork);
902 u8 status = 0, val;
903 int rc;
904 unsigned long flags;
905
7b8e19b6 906 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &val);
907 status |= val;
908
909 status &= ~IRQ_PLL_LOCK; /* ignore */
910 status &= ~IRQ_RX_START; /* ignore */
911 status &= ~IRQ_AMI; /* ignore */
912 status &= ~IRQ_TRX_UR; /* FIXME: possibly handle ???*/
913
914 if (status & IRQ_TRX_END) {
5b00f2ee 915 spin_lock_irqsave(&lp->lock, flags);
7b8e19b6 916 status &= ~IRQ_TRX_END;
917 if (lp->is_tx) {
918 lp->is_tx = 0;
5b00f2ee 919 spin_unlock_irqrestore(&lp->lock, flags);
7b8e19b6 920 complete(&lp->tx_complete);
921 } else {
5b00f2ee 922 spin_unlock_irqrestore(&lp->lock, flags);
7b8e19b6 923 at86rf230_rx(lp);
924 }
925 }
926
5b00f2ee 927 spin_lock_irqsave(&lp->lock, flags);
057dad6f 928 lp->irq_busy = 0;
7b8e19b6 929 spin_unlock_irqrestore(&lp->lock, flags);
057dad6f
SH		 930}
931
932static void at86rf230_irqwork_level(struct work_struct *work)
933{
934 struct at86rf230_local *lp =
935 container_of(work, struct at86rf230_local, irqwork);
936
937 at86rf230_irqwork(work);
5b00f2ee 938
939 enable_irq(lp->spi->irq);
7b8e19b6 940}
941
942static irqreturn_t at86rf230_isr(int irq, void *data)
943{
944 struct at86rf230_local *lp = data;
945
946 spin_lock(&lp->lock);
057dad6f 947 lp->irq_busy = 1;
7b8e19b6 948 spin_unlock(&lp->lock);
949
950 schedule_work(&lp->irqwork);
951
952 return IRQ_HANDLED;
953}
954
057dad6f
SH		 955static irqreturn_t at86rf230_isr_level(int irq, void *data)
956{
957 disable_irq_nosync(irq);
958
959 return at86rf230_isr(irq, data);
960}
961
43b5abe0
SH		 962static int at86rf230_irq_polarity(struct at86rf230_local *lp, int pol)
963{
964 return at86rf230_write_subreg(lp, SR_IRQ_POLARITY, pol);
965}
7b8e19b6 966
967static int at86rf230_hw_init(struct at86rf230_local *lp)
968{
43b5abe0
SH		 969 struct at86rf230_platform_data *pdata = lp->spi->dev.platform_data;
970 int rc, irq_pol;
7b8e19b6 971 u8 status;
f2fdd67c 972 u8 csma_seed[2];
7b8e19b6 973
974 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
975 if (rc)
976 return rc;
977
7dcbd22a
PB		 978 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_FORCE_TRX_OFF);
979 if (rc)
980 return rc;
7b8e19b6 981
43b5abe0
SH		 982 /* configure irq polarity, defaults to high active */
983 if (pdata->irq_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
984 irq_pol = IRQ_ACTIVE_LOW;
985 else
986 irq_pol = IRQ_ACTIVE_HIGH;
987
988 rc = at86rf230_irq_polarity(lp, irq_pol);
989 if (rc)
990 return rc;
991
057dad6f 992 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
7b8e19b6 993 if (rc)
994 return rc;
995
f2fdd67c
PB		 996 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
997 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
998 if (rc)
999 return rc;
1000 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
1001 if (rc)
1002 return rc;
1003
7b8e19b6 1004 /* CLKM changes are applied immediately */
1005 rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
1006 if (rc)
1007 return rc;
1008
1009 /* Turn CLKM Off */
1010 rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
1011 if (rc)
1012 return rc;
1013 /* Wait the next SLEEP cycle */
1014 msleep(100);
1015
7b8e19b6 1016 rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &status);
1017 if (rc)
1018 return rc;
1019 if (!status) {
1020 dev_err(&lp->spi->dev, "DVDD error\n");
1021 return -EINVAL;
1022 }
1023
1024 rc = at86rf230_read_subreg(lp, SR_AVDD_OK, &status);
1025 if (rc)
1026 return rc;
1027 if (!status) {
1028 dev_err(&lp->spi->dev, "AVDD error\n");
1029 return -EINVAL;
1030 }
1031
1032 return 0;
1033}
1034
bb1f4606 1035static int at86rf230_probe(struct spi_device *spi)
7b8e19b6 1036{
43b5abe0 1037 struct at86rf230_platform_data *pdata;
7b8e19b6 1038 struct ieee802154_dev *dev;
1039 struct at86rf230_local *lp;
8fad346f
PB		 1040 u16 man_id = 0;
1041 u8 part = 0, version = 0, status;
057dad6f
SH		 1042 irq_handler_t irq_handler;
1043 work_func_t irq_worker;
8fad346f 1044 int rc;
7b8e19b6 1045 const char *chip;
8fad346f 1046 struct ieee802154_ops *ops = NULL;
7b8e19b6 1047
1048 if (!spi->irq) {
1049 dev_err(&spi->dev, "no IRQ specified\n");
1050 return -EINVAL;
1051 }
1052
43b5abe0
SH		 1053 pdata = spi->dev.platform_data;
1054 if (!pdata) {
1055 dev_err(&spi->dev, "no platform_data\n");
1056 return -EINVAL;
1057 }
1058
8fad346f 1059 rc = gpio_request(pdata->rstn, "rstn");
7b8e19b6 1060 if (rc)
8fad346f 1061 return rc;
7b8e19b6 1062
8fad346f
PB		 1063 if (gpio_is_valid(pdata->slp_tr)) {
1064 rc = gpio_request(pdata->slp_tr, "slp_tr");
7b8e19b6 1065 if (rc)
1066 goto err_slp_tr;
1067 }
1068
8fad346f 1069 rc = gpio_direction_output(pdata->rstn, 1);
7b8e19b6 1070 if (rc)
1071 goto err_gpio_dir;
1072
8fad346f
PB		 1073 if (gpio_is_valid(pdata->slp_tr)) {
1074 rc = gpio_direction_output(pdata->slp_tr, 0);
7b8e19b6 1075 if (rc)
1076 goto err_gpio_dir;
1077 }
1078
1079 /* Reset */
1080 msleep(1);
8fad346f 1081 gpio_set_value(pdata->rstn, 0);
7b8e19b6 1082 msleep(1);
8fad346f 1083 gpio_set_value(pdata->rstn, 1);
7b8e19b6 1084 msleep(1);
1085
8fad346f
PB		 1086 rc = __at86rf230_detect_device(spi, &man_id, &part, &version);
1087 if (rc < 0)
7b8e19b6 1088 goto err_gpio_dir;
1089
8fad346f 1090 if (man_id != 0x001f) {
7b8e19b6 1091 dev_err(&spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
8fad346f 1092 man_id >> 8, man_id & 0xFF);
7b8e19b6 1093 rc = -EINVAL;
1094 goto err_gpio_dir;
1095 }
1096
8fad346f 1097 switch (part) {
7b8e19b6 1098 case 2:
1099 chip = "at86rf230";
8fad346f 1100 /* FIXME: should be easy to support; */
7b8e19b6 1101 break;
1102 case 3:
1103 chip = "at86rf231";
8fad346f
PB		 1104 ops = &at86rf230_ops;
1105 break;
1106 case 7:
1107 chip = "at86rf212";
1108 if (version == 1)
1109 ops = &at86rf212_ops;
7b8e19b6 1110 break;
1111 default:
1112 chip = "UNKNOWN";
1113 break;
1114 }
1115
8fad346f
PB		 1116 dev_info(&spi->dev, "Detected %s chip version %d\n", chip, version);
1117 if (!ops) {
7b8e19b6 1118 rc = -ENOTSUPP;
1119 goto err_gpio_dir;
1120 }
1121
8fad346f
PB		 1122 dev = ieee802154_alloc_device(sizeof(*lp), ops);
1123 if (!dev) {
1124 rc = -ENOMEM;
1125 goto err_gpio_dir;
1126 }
1127
1128 lp = dev->priv;
1129 lp->dev = dev;
1130 lp->part = part;
1131 lp->vers = version;
1132
1133 lp->spi = spi;
1134
1135 dev->parent = &spi->dev;
1136 dev->extra_tx_headroom = 0;
1137 dev->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK;
1138
1139 if (pdata->irq_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
1140 irq_worker = at86rf230_irqwork;
1141 irq_handler = at86rf230_isr;
1142 } else {
1143 irq_worker = at86rf230_irqwork_level;
1144 irq_handler = at86rf230_isr_level;
1145 }
1146
1147 mutex_init(&lp->bmux);
1148 INIT_WORK(&lp->irqwork, irq_worker);
1149 spin_lock_init(&lp->lock);
1150 init_completion(&lp->tx_complete);
1151
1152 spi_set_drvdata(spi, lp);
1153
643e53c2 1154 if (is_rf212(lp)) {
8fad346f 1155 dev->phy->channels_supported[0] = 0x00007FF;
643e53c2
PB		 1156 dev->phy->channels_supported[2] = 0x00007FF;
1157 } else {
8fad346f 1158 dev->phy->channels_supported[0] = 0x7FFF800;
643e53c2 1159 }
8fad346f 1160
7b8e19b6 1161 rc = at86rf230_hw_init(lp);
1162 if (rc)
8fad346f 1163 goto err_hw_init;
7b8e19b6 1164
057dad6f 1165 rc = request_irq(spi->irq, irq_handler,
43b5abe0 1166 IRQF_SHARED | pdata->irq_type,
7b8e19b6 1167 dev_name(&spi->dev), lp);
1168 if (rc)
8fad346f 1169 goto err_hw_init;
7b8e19b6 1170
057dad6f
SH		 1171 /* Read irq status register to reset irq line */
1172 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
1173 if (rc)
1174 goto err_irq;
1175
7b8e19b6 1176 rc = ieee802154_register_device(lp->dev);
1177 if (rc)
1178 goto err_irq;
1179
1180 return rc;
1181
7b8e19b6 1182err_irq:
1183 free_irq(spi->irq, lp);
8fad346f 1184err_hw_init:
7b8e19b6 1185 flush_work(&lp->irqwork);
8fad346f 1186 spi_set_drvdata(spi, NULL);
7b8e19b6 1187 mutex_destroy(&lp->bmux);
1188 ieee802154_free_device(lp->dev);
8fad346f
PB		 1189
1190err_gpio_dir:
1191 if (gpio_is_valid(pdata->slp_tr))
1192 gpio_free(pdata->slp_tr);
1193err_slp_tr:
1194 gpio_free(pdata->rstn);
7b8e19b6 1195 return rc;
1196}
1197
bb1f4606 1198static int at86rf230_remove(struct spi_device *spi)
7b8e19b6 1199{
1200 struct at86rf230_local *lp = spi_get_drvdata(spi);
8fad346f 1201 struct at86rf230_platform_data *pdata = spi->dev.platform_data;
7b8e19b6 1202
1203 ieee802154_unregister_device(lp->dev);
1204
1205 free_irq(spi->irq, lp);
1206 flush_work(&lp->irqwork);
1207
8fad346f
PB		 1208 if (gpio_is_valid(pdata->slp_tr))
1209 gpio_free(pdata->slp_tr);
1210 gpio_free(pdata->rstn);
7b8e19b6 1211
7b8e19b6 1212 mutex_destroy(&lp->bmux);
1213 ieee802154_free_device(lp->dev);
1214
1215 dev_dbg(&spi->dev, "unregistered at86rf230\n");
1216 return 0;
1217}
1218
1219static struct spi_driver at86rf230_driver = {
1220 .driver = {
1221 .name = "at86rf230",
1222 .owner = THIS_MODULE,
1223 },
1224 .probe = at86rf230_probe,
bb1f4606 1225 .remove = at86rf230_remove,
7b8e19b6 1226};
1227
395a5738 1228module_spi_driver(at86rf230_driver);
7b8e19b6 1229
1230MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1231MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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