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7b8e19b6 | 1 | /* |
2 | * AT86RF230/RF231 driver | |
3 | * | |
4 | * Copyright (C) 2009-2012 Siemens AG | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
7b8e19b6 | 15 | * Written by: |
16 | * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> | |
17 | * Alexander Smirnov <alex.bluesman.smirnov@gmail.com> | |
01ebd60b | 18 | * Alexander Aring <aar@pengutronix.de> |
7b8e19b6 | 19 | */ |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
4af619ae | 23 | #include <linux/irq.h> |
7b8e19b6 | 24 | #include <linux/gpio.h> |
25 | #include <linux/delay.h> | |
7b8e19b6 | 26 | #include <linux/spinlock.h> |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/spi/at86rf230.h> | |
f76014f7 | 29 | #include <linux/regmap.h> |
7b8e19b6 | 30 | #include <linux/skbuff.h> |
fa2d3e94 | 31 | #include <linux/of_gpio.h> |
4ca24aca | 32 | #include <linux/ieee802154.h> |
7b8e19b6 | 33 | |
34 | #include <net/mac802154.h> | |
5ad60d36 | 35 | #include <net/cfg802154.h> |
7b8e19b6 | 36 | |
a53d1f7c AA |
37 | struct at86rf230_local; |
38 | /* at86rf2xx chip depend data. | |
39 | * All timings are in us. | |
40 | */ | |
41 | struct at86rf2xx_chip_data { | |
7a4ef918 | 42 | u16 t_sleep_cycle; |
984e0c68 | 43 | u16 t_channel_switch; |
09e536cd | 44 | u16 t_reset_to_off; |
2e0571c0 AA |
45 | u16 t_off_to_aack; |
46 | u16 t_off_to_tx_on; | |
1d15d6b5 AA |
47 | u16 t_frame; |
48 | u16 t_p_ack; | |
1d15d6b5 AA |
49 | /* completion timeout for tx in msecs */ |
50 | u16 t_tx_timeout; | |
a53d1f7c AA |
51 | int rssi_base_val; |
52 | ||
e37d2ec8 | 53 | int (*set_channel)(struct at86rf230_local *, u8, u8); |
a7d7eda9 | 54 | int (*get_desense_steps)(struct at86rf230_local *, s32); |
a53d1f7c AA |
55 | }; |
56 | ||
1d15d6b5 | 57 | #define AT86RF2XX_MAX_BUF (127 + 3) |
7b8e19b6 | 58 | |
1d15d6b5 AA |
59 | struct at86rf230_state_change { |
60 | struct at86rf230_local *lp; | |
7b8e19b6 | 61 | |
1d15d6b5 AA |
62 | struct spi_message msg; |
63 | struct spi_transfer trx; | |
64 | u8 buf[AT86RF2XX_MAX_BUF]; | |
65 | ||
66 | void (*complete)(void *context); | |
67 | u8 from_state; | |
68 | u8 to_state; | |
97fed795 AA |
69 | |
70 | bool irq_enable; | |
1d15d6b5 AA |
71 | }; |
72 | ||
73 | struct at86rf230_local { | |
74 | struct spi_device *spi; | |
7b8e19b6 | 75 | |
5a504397 | 76 | struct ieee802154_hw *hw; |
1d15d6b5 | 77 | struct at86rf2xx_chip_data *data; |
f76014f7 | 78 | struct regmap *regmap; |
7b8e19b6 | 79 | |
2e0571c0 AA |
80 | struct completion state_complete; |
81 | struct at86rf230_state_change state; | |
82 | ||
1d15d6b5 | 83 | struct at86rf230_state_change irq; |
6ca00197 | 84 | |
a53d1f7c | 85 | bool tx_aret; |
850f43ac | 86 | s8 max_frame_retries; |
1d15d6b5 AA |
87 | bool is_tx; |
88 | /* spinlock for is_tx protection */ | |
89 | spinlock_t lock; | |
1d15d6b5 AA |
90 | struct sk_buff *tx_skb; |
91 | struct at86rf230_state_change tx; | |
7b8e19b6 | 92 | }; |
93 | ||
94 | #define RG_TRX_STATUS (0x01) | |
95 | #define SR_TRX_STATUS 0x01, 0x1f, 0 | |
96 | #define SR_RESERVED_01_3 0x01, 0x20, 5 | |
97 | #define SR_CCA_STATUS 0x01, 0x40, 6 | |
98 | #define SR_CCA_DONE 0x01, 0x80, 7 | |
99 | #define RG_TRX_STATE (0x02) | |
100 | #define SR_TRX_CMD 0x02, 0x1f, 0 | |
101 | #define SR_TRAC_STATUS 0x02, 0xe0, 5 | |
102 | #define RG_TRX_CTRL_0 (0x03) | |
103 | #define SR_CLKM_CTRL 0x03, 0x07, 0 | |
104 | #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 | |
105 | #define SR_PAD_IO_CLKM 0x03, 0x30, 4 | |
106 | #define SR_PAD_IO 0x03, 0xc0, 6 | |
107 | #define RG_TRX_CTRL_1 (0x04) | |
108 | #define SR_IRQ_POLARITY 0x04, 0x01, 0 | |
109 | #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 | |
110 | #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 | |
111 | #define SR_RX_BL_CTRL 0x04, 0x10, 4 | |
112 | #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 | |
113 | #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 | |
114 | #define SR_PA_EXT_EN 0x04, 0x80, 7 | |
115 | #define RG_PHY_TX_PWR (0x05) | |
116 | #define SR_TX_PWR 0x05, 0x0f, 0 | |
117 | #define SR_PA_LT 0x05, 0x30, 4 | |
118 | #define SR_PA_BUF_LT 0x05, 0xc0, 6 | |
119 | #define RG_PHY_RSSI (0x06) | |
120 | #define SR_RSSI 0x06, 0x1f, 0 | |
121 | #define SR_RND_VALUE 0x06, 0x60, 5 | |
122 | #define SR_RX_CRC_VALID 0x06, 0x80, 7 | |
123 | #define RG_PHY_ED_LEVEL (0x07) | |
124 | #define SR_ED_LEVEL 0x07, 0xff, 0 | |
125 | #define RG_PHY_CC_CCA (0x08) | |
126 | #define SR_CHANNEL 0x08, 0x1f, 0 | |
127 | #define SR_CCA_MODE 0x08, 0x60, 5 | |
128 | #define SR_CCA_REQUEST 0x08, 0x80, 7 | |
129 | #define RG_CCA_THRES (0x09) | |
130 | #define SR_CCA_ED_THRES 0x09, 0x0f, 0 | |
131 | #define SR_RESERVED_09_1 0x09, 0xf0, 4 | |
132 | #define RG_RX_CTRL (0x0a) | |
133 | #define SR_PDT_THRES 0x0a, 0x0f, 0 | |
134 | #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 | |
135 | #define RG_SFD_VALUE (0x0b) | |
136 | #define SR_SFD_VALUE 0x0b, 0xff, 0 | |
137 | #define RG_TRX_CTRL_2 (0x0c) | |
138 | #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 | |
8fad346f PB |
139 | #define SR_SUB_MODE 0x0c, 0x04, 2 |
140 | #define SR_BPSK_QPSK 0x0c, 0x08, 3 | |
643e53c2 PB |
141 | #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 |
142 | #define SR_RESERVED_0c_5 0x0c, 0x60, 5 | |
7b8e19b6 | 143 | #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 |
144 | #define RG_ANT_DIV (0x0d) | |
145 | #define SR_ANT_CTRL 0x0d, 0x03, 0 | |
146 | #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 | |
147 | #define SR_ANT_DIV_EN 0x0d, 0x08, 3 | |
148 | #define SR_RESERVED_0d_2 0x0d, 0x70, 4 | |
149 | #define SR_ANT_SEL 0x0d, 0x80, 7 | |
150 | #define RG_IRQ_MASK (0x0e) | |
151 | #define SR_IRQ_MASK 0x0e, 0xff, 0 | |
152 | #define RG_IRQ_STATUS (0x0f) | |
153 | #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 | |
154 | #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 | |
155 | #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 | |
156 | #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 | |
157 | #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 | |
158 | #define SR_IRQ_5_AMI 0x0f, 0x20, 5 | |
159 | #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 | |
160 | #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 | |
161 | #define RG_VREG_CTRL (0x10) | |
162 | #define SR_RESERVED_10_6 0x10, 0x03, 0 | |
163 | #define SR_DVDD_OK 0x10, 0x04, 2 | |
164 | #define SR_DVREG_EXT 0x10, 0x08, 3 | |
165 | #define SR_RESERVED_10_3 0x10, 0x30, 4 | |
166 | #define SR_AVDD_OK 0x10, 0x40, 6 | |
167 | #define SR_AVREG_EXT 0x10, 0x80, 7 | |
168 | #define RG_BATMON (0x11) | |
169 | #define SR_BATMON_VTH 0x11, 0x0f, 0 | |
170 | #define SR_BATMON_HR 0x11, 0x10, 4 | |
171 | #define SR_BATMON_OK 0x11, 0x20, 5 | |
172 | #define SR_RESERVED_11_1 0x11, 0xc0, 6 | |
173 | #define RG_XOSC_CTRL (0x12) | |
174 | #define SR_XTAL_TRIM 0x12, 0x0f, 0 | |
175 | #define SR_XTAL_MODE 0x12, 0xf0, 4 | |
176 | #define RG_RX_SYN (0x15) | |
177 | #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 | |
178 | #define SR_RESERVED_15_2 0x15, 0x70, 4 | |
179 | #define SR_RX_PDT_DIS 0x15, 0x80, 7 | |
180 | #define RG_XAH_CTRL_1 (0x17) | |
181 | #define SR_RESERVED_17_8 0x17, 0x01, 0 | |
182 | #define SR_AACK_PROM_MODE 0x17, 0x02, 1 | |
183 | #define SR_AACK_ACK_TIME 0x17, 0x04, 2 | |
184 | #define SR_RESERVED_17_5 0x17, 0x08, 3 | |
185 | #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 | |
186 | #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 | |
84dda3c6 | 187 | #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
7b8e19b6 | 188 | #define SR_RESERVED_17_1 0x17, 0x80, 7 |
189 | #define RG_FTN_CTRL (0x18) | |
190 | #define SR_RESERVED_18_2 0x18, 0x7f, 0 | |
191 | #define SR_FTN_START 0x18, 0x80, 7 | |
192 | #define RG_PLL_CF (0x1a) | |
193 | #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 | |
194 | #define SR_PLL_CF_START 0x1a, 0x80, 7 | |
195 | #define RG_PLL_DCU (0x1b) | |
196 | #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 | |
197 | #define SR_RESERVED_1b_2 0x1b, 0x40, 6 | |
198 | #define SR_PLL_DCU_START 0x1b, 0x80, 7 | |
199 | #define RG_PART_NUM (0x1c) | |
200 | #define SR_PART_NUM 0x1c, 0xff, 0 | |
201 | #define RG_VERSION_NUM (0x1d) | |
202 | #define SR_VERSION_NUM 0x1d, 0xff, 0 | |
203 | #define RG_MAN_ID_0 (0x1e) | |
204 | #define SR_MAN_ID_0 0x1e, 0xff, 0 | |
205 | #define RG_MAN_ID_1 (0x1f) | |
206 | #define SR_MAN_ID_1 0x1f, 0xff, 0 | |
207 | #define RG_SHORT_ADDR_0 (0x20) | |
208 | #define SR_SHORT_ADDR_0 0x20, 0xff, 0 | |
209 | #define RG_SHORT_ADDR_1 (0x21) | |
210 | #define SR_SHORT_ADDR_1 0x21, 0xff, 0 | |
211 | #define RG_PAN_ID_0 (0x22) | |
212 | #define SR_PAN_ID_0 0x22, 0xff, 0 | |
213 | #define RG_PAN_ID_1 (0x23) | |
214 | #define SR_PAN_ID_1 0x23, 0xff, 0 | |
215 | #define RG_IEEE_ADDR_0 (0x24) | |
216 | #define SR_IEEE_ADDR_0 0x24, 0xff, 0 | |
217 | #define RG_IEEE_ADDR_1 (0x25) | |
218 | #define SR_IEEE_ADDR_1 0x25, 0xff, 0 | |
219 | #define RG_IEEE_ADDR_2 (0x26) | |
220 | #define SR_IEEE_ADDR_2 0x26, 0xff, 0 | |
221 | #define RG_IEEE_ADDR_3 (0x27) | |
222 | #define SR_IEEE_ADDR_3 0x27, 0xff, 0 | |
223 | #define RG_IEEE_ADDR_4 (0x28) | |
224 | #define SR_IEEE_ADDR_4 0x28, 0xff, 0 | |
225 | #define RG_IEEE_ADDR_5 (0x29) | |
226 | #define SR_IEEE_ADDR_5 0x29, 0xff, 0 | |
227 | #define RG_IEEE_ADDR_6 (0x2a) | |
228 | #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 | |
229 | #define RG_IEEE_ADDR_7 (0x2b) | |
230 | #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 | |
231 | #define RG_XAH_CTRL_0 (0x2c) | |
232 | #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 | |
233 | #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 | |
234 | #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 | |
235 | #define RG_CSMA_SEED_0 (0x2d) | |
236 | #define SR_CSMA_SEED_0 0x2d, 0xff, 0 | |
237 | #define RG_CSMA_SEED_1 (0x2e) | |
238 | #define SR_CSMA_SEED_1 0x2e, 0x07, 0 | |
239 | #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 | |
240 | #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 | |
241 | #define SR_AACK_SET_PD 0x2e, 0x20, 5 | |
242 | #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 | |
243 | #define RG_CSMA_BE (0x2f) | |
244 | #define SR_MIN_BE 0x2f, 0x0f, 0 | |
245 | #define SR_MAX_BE 0x2f, 0xf0, 4 | |
246 | ||
247 | #define CMD_REG 0x80 | |
248 | #define CMD_REG_MASK 0x3f | |
249 | #define CMD_WRITE 0x40 | |
250 | #define CMD_FB 0x20 | |
251 | ||
252 | #define IRQ_BAT_LOW (1 << 7) | |
253 | #define IRQ_TRX_UR (1 << 6) | |
254 | #define IRQ_AMI (1 << 5) | |
255 | #define IRQ_CCA_ED (1 << 4) | |
256 | #define IRQ_TRX_END (1 << 3) | |
257 | #define IRQ_RX_START (1 << 2) | |
258 | #define IRQ_PLL_UNL (1 << 1) | |
259 | #define IRQ_PLL_LOCK (1 << 0) | |
260 | ||
43b5abe0 SH |
261 | #define IRQ_ACTIVE_HIGH 0 |
262 | #define IRQ_ACTIVE_LOW 1 | |
263 | ||
7b8e19b6 | 264 | #define STATE_P_ON 0x00 /* BUSY */ |
265 | #define STATE_BUSY_RX 0x01 | |
266 | #define STATE_BUSY_TX 0x02 | |
267 | #define STATE_FORCE_TRX_OFF 0x03 | |
268 | #define STATE_FORCE_TX_ON 0x04 /* IDLE */ | |
269 | /* 0x05 */ /* INVALID_PARAMETER */ | |
270 | #define STATE_RX_ON 0x06 | |
271 | /* 0x07 */ /* SUCCESS */ | |
272 | #define STATE_TRX_OFF 0x08 | |
273 | #define STATE_TX_ON 0x09 | |
274 | /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */ | |
275 | #define STATE_SLEEP 0x0F | |
48d5dbaf | 276 | #define STATE_PREP_DEEP_SLEEP 0x10 |
7b8e19b6 | 277 | #define STATE_BUSY_RX_AACK 0x11 |
278 | #define STATE_BUSY_TX_ARET 0x12 | |
028889b0 | 279 | #define STATE_RX_AACK_ON 0x16 |
280 | #define STATE_TX_ARET_ON 0x19 | |
7b8e19b6 | 281 | #define STATE_RX_ON_NOCLK 0x1C |
282 | #define STATE_RX_AACK_ON_NOCLK 0x1D | |
283 | #define STATE_BUSY_RX_AACK_NOCLK 0x1E | |
284 | #define STATE_TRANSITION_IN_PROGRESS 0x1F | |
285 | ||
f76014f7 AA |
286 | #define AT86RF2XX_NUMREGS 0x3F |
287 | ||
97fed795 | 288 | static void |
1d15d6b5 AA |
289 | at86rf230_async_state_change(struct at86rf230_local *lp, |
290 | struct at86rf230_state_change *ctx, | |
97fed795 AA |
291 | const u8 state, void (*complete)(void *context), |
292 | const bool irq_enable); | |
1d15d6b5 | 293 | |
f76014f7 AA |
294 | static inline int |
295 | __at86rf230_write(struct at86rf230_local *lp, | |
296 | unsigned int addr, unsigned int data) | |
297 | { | |
298 | return regmap_write(lp->regmap, addr, data); | |
299 | } | |
300 | ||
301 | static inline int | |
302 | __at86rf230_read(struct at86rf230_local *lp, | |
303 | unsigned int addr, unsigned int *data) | |
304 | { | |
305 | return regmap_read(lp->regmap, addr, data); | |
306 | } | |
307 | ||
308 | static inline int | |
309 | at86rf230_read_subreg(struct at86rf230_local *lp, | |
310 | unsigned int addr, unsigned int mask, | |
311 | unsigned int shift, unsigned int *data) | |
312 | { | |
313 | int rc; | |
314 | ||
315 | rc = __at86rf230_read(lp, addr, data); | |
316 | if (rc > 0) | |
317 | *data = (*data & mask) >> shift; | |
318 | ||
319 | return rc; | |
320 | } | |
321 | ||
322 | static inline int | |
323 | at86rf230_write_subreg(struct at86rf230_local *lp, | |
324 | unsigned int addr, unsigned int mask, | |
325 | unsigned int shift, unsigned int data) | |
326 | { | |
327 | return regmap_update_bits(lp->regmap, addr, mask, data << shift); | |
328 | } | |
329 | ||
330 | static bool | |
331 | at86rf230_reg_writeable(struct device *dev, unsigned int reg) | |
332 | { | |
333 | switch (reg) { | |
334 | case RG_TRX_STATE: | |
335 | case RG_TRX_CTRL_0: | |
336 | case RG_TRX_CTRL_1: | |
337 | case RG_PHY_TX_PWR: | |
338 | case RG_PHY_ED_LEVEL: | |
339 | case RG_PHY_CC_CCA: | |
340 | case RG_CCA_THRES: | |
341 | case RG_RX_CTRL: | |
342 | case RG_SFD_VALUE: | |
343 | case RG_TRX_CTRL_2: | |
344 | case RG_ANT_DIV: | |
345 | case RG_IRQ_MASK: | |
346 | case RG_VREG_CTRL: | |
347 | case RG_BATMON: | |
348 | case RG_XOSC_CTRL: | |
349 | case RG_RX_SYN: | |
350 | case RG_XAH_CTRL_1: | |
351 | case RG_FTN_CTRL: | |
352 | case RG_PLL_CF: | |
353 | case RG_PLL_DCU: | |
354 | case RG_SHORT_ADDR_0: | |
355 | case RG_SHORT_ADDR_1: | |
356 | case RG_PAN_ID_0: | |
357 | case RG_PAN_ID_1: | |
358 | case RG_IEEE_ADDR_0: | |
359 | case RG_IEEE_ADDR_1: | |
360 | case RG_IEEE_ADDR_2: | |
361 | case RG_IEEE_ADDR_3: | |
362 | case RG_IEEE_ADDR_4: | |
363 | case RG_IEEE_ADDR_5: | |
364 | case RG_IEEE_ADDR_6: | |
365 | case RG_IEEE_ADDR_7: | |
366 | case RG_XAH_CTRL_0: | |
367 | case RG_CSMA_SEED_0: | |
368 | case RG_CSMA_SEED_1: | |
369 | case RG_CSMA_BE: | |
370 | return true; | |
371 | default: | |
372 | return false; | |
373 | } | |
374 | } | |
375 | ||
376 | static bool | |
377 | at86rf230_reg_readable(struct device *dev, unsigned int reg) | |
378 | { | |
379 | bool rc; | |
380 | ||
381 | /* all writeable are also readable */ | |
382 | rc = at86rf230_reg_writeable(dev, reg); | |
383 | if (rc) | |
384 | return rc; | |
385 | ||
386 | /* readonly regs */ | |
387 | switch (reg) { | |
388 | case RG_TRX_STATUS: | |
389 | case RG_PHY_RSSI: | |
390 | case RG_IRQ_STATUS: | |
391 | case RG_PART_NUM: | |
392 | case RG_VERSION_NUM: | |
393 | case RG_MAN_ID_1: | |
394 | case RG_MAN_ID_0: | |
395 | return true; | |
396 | default: | |
397 | return false; | |
398 | } | |
399 | } | |
400 | ||
401 | static bool | |
402 | at86rf230_reg_volatile(struct device *dev, unsigned int reg) | |
403 | { | |
404 | /* can be changed during runtime */ | |
405 | switch (reg) { | |
406 | case RG_TRX_STATUS: | |
407 | case RG_TRX_STATE: | |
408 | case RG_PHY_RSSI: | |
409 | case RG_PHY_ED_LEVEL: | |
410 | case RG_IRQ_STATUS: | |
411 | case RG_VREG_CTRL: | |
412 | return true; | |
413 | default: | |
414 | return false; | |
415 | } | |
416 | } | |
417 | ||
418 | static bool | |
419 | at86rf230_reg_precious(struct device *dev, unsigned int reg) | |
420 | { | |
421 | /* don't clear irq line on read */ | |
422 | switch (reg) { | |
423 | case RG_IRQ_STATUS: | |
424 | return true; | |
425 | default: | |
426 | return false; | |
427 | } | |
428 | } | |
429 | ||
430 | static struct regmap_config at86rf230_regmap_spi_config = { | |
431 | .reg_bits = 8, | |
432 | .val_bits = 8, | |
433 | .write_flag_mask = CMD_REG | CMD_WRITE, | |
434 | .read_flag_mask = CMD_REG, | |
435 | .cache_type = REGCACHE_RBTREE, | |
436 | .max_register = AT86RF2XX_NUMREGS, | |
437 | .writeable_reg = at86rf230_reg_writeable, | |
438 | .readable_reg = at86rf230_reg_readable, | |
439 | .volatile_reg = at86rf230_reg_volatile, | |
440 | .precious_reg = at86rf230_reg_precious, | |
441 | }; | |
442 | ||
1d15d6b5 AA |
443 | static void |
444 | at86rf230_async_error_recover(void *context) | |
445 | { | |
446 | struct at86rf230_state_change *ctx = context; | |
447 | struct at86rf230_local *lp = ctx->lp; | |
448 | ||
97fed795 | 449 | at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL, false); |
955aee8b | 450 | ieee802154_wake_queue(lp->hw); |
1d15d6b5 AA |
451 | } |
452 | ||
fc50c6e3 | 453 | static inline void |
1d15d6b5 AA |
454 | at86rf230_async_error(struct at86rf230_local *lp, |
455 | struct at86rf230_state_change *ctx, int rc) | |
456 | { | |
457 | dev_err(&lp->spi->dev, "spi_async error %d\n", rc); | |
458 | ||
459 | at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF, | |
97fed795 | 460 | at86rf230_async_error_recover, false); |
1d15d6b5 AA |
461 | } |
462 | ||
463 | /* Generic function to get some register value in async mode */ | |
97fed795 | 464 | static void |
1d15d6b5 AA |
465 | at86rf230_async_read_reg(struct at86rf230_local *lp, const u8 reg, |
466 | struct at86rf230_state_change *ctx, | |
97fed795 AA |
467 | void (*complete)(void *context), |
468 | const bool irq_enable) | |
7b8e19b6 | 469 | { |
97fed795 AA |
470 | int rc; |
471 | ||
1d15d6b5 AA |
472 | u8 *tx_buf = ctx->buf; |
473 | ||
474 | tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG; | |
475 | ctx->trx.len = 2; | |
476 | ctx->msg.complete = complete; | |
97fed795 AA |
477 | ctx->irq_enable = irq_enable; |
478 | rc = spi_async(lp->spi, &ctx->msg); | |
479 | if (rc) { | |
480 | if (irq_enable) | |
481 | enable_irq(lp->spi->irq); | |
482 | ||
483 | at86rf230_async_error(lp, ctx, rc); | |
484 | } | |
1d15d6b5 AA |
485 | } |
486 | ||
487 | static void | |
488 | at86rf230_async_state_assert(void *context) | |
489 | { | |
490 | struct at86rf230_state_change *ctx = context; | |
491 | struct at86rf230_local *lp = ctx->lp; | |
492 | const u8 *buf = ctx->buf; | |
493 | const u8 trx_state = buf[1] & 0x1f; | |
494 | ||
495 | /* Assert state change */ | |
496 | if (trx_state != ctx->to_state) { | |
497 | /* Special handling if transceiver state is in | |
498 | * STATE_BUSY_RX_AACK and a SHR was detected. | |
499 | */ | |
500 | if (trx_state == STATE_BUSY_RX_AACK) { | |
501 | /* Undocumented race condition. If we send a state | |
502 | * change to STATE_RX_AACK_ON the transceiver could | |
503 | * change his state automatically to STATE_BUSY_RX_AACK | |
504 | * if a SHR was detected. This is not an error, but we | |
505 | * can't assert this. | |
506 | */ | |
507 | if (ctx->to_state == STATE_RX_AACK_ON) | |
508 | goto done; | |
509 | ||
510 | /* If we change to STATE_TX_ON without forcing and | |
511 | * transceiver state is STATE_BUSY_RX_AACK, we wait | |
512 | * 'tFrame + tPAck' receiving time. In this time the | |
513 | * PDU should be received. If the transceiver is still | |
514 | * in STATE_BUSY_RX_AACK, we run a force state change | |
515 | * to STATE_TX_ON. This is a timeout handling, if the | |
516 | * transceiver stucks in STATE_BUSY_RX_AACK. | |
517 | */ | |
518 | if (ctx->to_state == STATE_TX_ON) { | |
519 | at86rf230_async_state_change(lp, ctx, | |
520 | STATE_FORCE_TX_ON, | |
97fed795 AA |
521 | ctx->complete, |
522 | ctx->irq_enable); | |
1d15d6b5 AA |
523 | return; |
524 | } | |
525 | } | |
526 | ||
1d15d6b5 AA |
527 | dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n", |
528 | ctx->from_state, ctx->to_state, trx_state); | |
529 | } | |
530 | ||
531 | done: | |
532 | if (ctx->complete) | |
533 | ctx->complete(context); | |
534 | } | |
535 | ||
536 | /* Do state change timing delay. */ | |
537 | static void | |
538 | at86rf230_async_state_delay(void *context) | |
539 | { | |
540 | struct at86rf230_state_change *ctx = context; | |
541 | struct at86rf230_local *lp = ctx->lp; | |
542 | struct at86rf2xx_chip_data *c = lp->data; | |
543 | bool force = false; | |
1d15d6b5 AA |
544 | |
545 | /* The force state changes are will show as normal states in the | |
546 | * state status subregister. We change the to_state to the | |
547 | * corresponding one and remember if it was a force change, this | |
548 | * differs if we do a state change from STATE_BUSY_RX_AACK. | |
549 | */ | |
550 | switch (ctx->to_state) { | |
551 | case STATE_FORCE_TX_ON: | |
552 | ctx->to_state = STATE_TX_ON; | |
553 | force = true; | |
554 | break; | |
555 | case STATE_FORCE_TRX_OFF: | |
556 | ctx->to_state = STATE_TRX_OFF; | |
557 | force = true; | |
558 | break; | |
559 | default: | |
560 | break; | |
561 | } | |
562 | ||
563 | switch (ctx->from_state) { | |
2e0571c0 AA |
564 | case STATE_TRX_OFF: |
565 | switch (ctx->to_state) { | |
566 | case STATE_RX_AACK_ON: | |
567 | usleep_range(c->t_off_to_aack, c->t_off_to_aack + 10); | |
568 | goto change; | |
569 | case STATE_TX_ON: | |
570 | usleep_range(c->t_off_to_tx_on, | |
571 | c->t_off_to_tx_on + 10); | |
572 | goto change; | |
573 | default: | |
574 | break; | |
575 | } | |
576 | break; | |
1d15d6b5 AA |
577 | case STATE_BUSY_RX_AACK: |
578 | switch (ctx->to_state) { | |
579 | case STATE_TX_ON: | |
580 | /* Wait for worst case receiving time if we | |
581 | * didn't make a force change from BUSY_RX_AACK | |
582 | * to TX_ON. | |
583 | */ | |
584 | if (!force) { | |
585 | usleep_range(c->t_frame + c->t_p_ack, | |
586 | c->t_frame + c->t_p_ack + 1000); | |
587 | goto change; | |
588 | } | |
589 | break; | |
590 | default: | |
591 | break; | |
592 | } | |
593 | break; | |
09e536cd AA |
594 | /* Default value, means RESET state */ |
595 | case STATE_P_ON: | |
596 | switch (ctx->to_state) { | |
597 | case STATE_TRX_OFF: | |
598 | usleep_range(c->t_reset_to_off, c->t_reset_to_off + 10); | |
599 | goto change; | |
600 | default: | |
601 | break; | |
602 | } | |
603 | break; | |
1d15d6b5 AA |
604 | default: |
605 | break; | |
606 | } | |
607 | ||
608 | /* Default delay is 1us in the most cases */ | |
609 | udelay(1); | |
610 | ||
611 | change: | |
97fed795 AA |
612 | at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, |
613 | at86rf230_async_state_assert, | |
614 | ctx->irq_enable); | |
1d15d6b5 AA |
615 | } |
616 | ||
617 | static void | |
618 | at86rf230_async_state_change_start(void *context) | |
619 | { | |
620 | struct at86rf230_state_change *ctx = context; | |
621 | struct at86rf230_local *lp = ctx->lp; | |
622 | u8 *buf = ctx->buf; | |
623 | const u8 trx_state = buf[1] & 0x1f; | |
624 | int rc; | |
625 | ||
626 | /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */ | |
627 | if (trx_state == STATE_TRANSITION_IN_PROGRESS) { | |
628 | udelay(1); | |
97fed795 AA |
629 | at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, |
630 | at86rf230_async_state_change_start, | |
631 | ctx->irq_enable); | |
1d15d6b5 AA |
632 | return; |
633 | } | |
634 | ||
635 | /* Check if we already are in the state which we change in */ | |
636 | if (trx_state == ctx->to_state) { | |
637 | if (ctx->complete) | |
638 | ctx->complete(context); | |
639 | return; | |
640 | } | |
641 | ||
642 | /* Set current state to the context of state change */ | |
643 | ctx->from_state = trx_state; | |
644 | ||
645 | /* Going into the next step for a state change which do a timing | |
646 | * relevant delay. | |
647 | */ | |
648 | buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE; | |
649 | buf[1] = ctx->to_state; | |
650 | ctx->trx.len = 2; | |
651 | ctx->msg.complete = at86rf230_async_state_delay; | |
652 | rc = spi_async(lp->spi, &ctx->msg); | |
97fed795 AA |
653 | if (rc) { |
654 | if (ctx->irq_enable) | |
655 | enable_irq(lp->spi->irq); | |
656 | ||
4fef7d3b | 657 | at86rf230_async_error(lp, ctx, rc); |
97fed795 | 658 | } |
7b8e19b6 | 659 | } |
660 | ||
97fed795 | 661 | static void |
1d15d6b5 AA |
662 | at86rf230_async_state_change(struct at86rf230_local *lp, |
663 | struct at86rf230_state_change *ctx, | |
97fed795 AA |
664 | const u8 state, void (*complete)(void *context), |
665 | const bool irq_enable) | |
7b8e19b6 | 666 | { |
1d15d6b5 AA |
667 | /* Initialization for the state change context */ |
668 | ctx->to_state = state; | |
669 | ctx->complete = complete; | |
97fed795 AA |
670 | ctx->irq_enable = irq_enable; |
671 | at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, | |
672 | at86rf230_async_state_change_start, | |
673 | irq_enable); | |
1d15d6b5 | 674 | } |
7b8e19b6 | 675 | |
2e0571c0 AA |
676 | static void |
677 | at86rf230_sync_state_change_complete(void *context) | |
678 | { | |
679 | struct at86rf230_state_change *ctx = context; | |
680 | struct at86rf230_local *lp = ctx->lp; | |
681 | ||
682 | complete(&lp->state_complete); | |
683 | } | |
684 | ||
685 | /* This function do a sync framework above the async state change. | |
686 | * Some callbacks of the IEEE 802.15.4 driver interface need to be | |
687 | * handled synchronously. | |
688 | */ | |
689 | static int | |
690 | at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state) | |
691 | { | |
692 | int rc; | |
693 | ||
97fed795 AA |
694 | at86rf230_async_state_change(lp, &lp->state, state, |
695 | at86rf230_sync_state_change_complete, | |
696 | false); | |
2e0571c0 AA |
697 | |
698 | rc = wait_for_completion_timeout(&lp->state_complete, | |
699 | msecs_to_jiffies(100)); | |
d06c2199 AA |
700 | if (!rc) { |
701 | at86rf230_async_error(lp, &lp->state, -ETIMEDOUT); | |
2e0571c0 | 702 | return -ETIMEDOUT; |
d06c2199 | 703 | } |
2e0571c0 AA |
704 | |
705 | return 0; | |
706 | } | |
707 | ||
1d15d6b5 AA |
708 | static void |
709 | at86rf230_tx_complete(void *context) | |
710 | { | |
711 | struct at86rf230_state_change *ctx = context; | |
712 | struct at86rf230_local *lp = ctx->lp; | |
955aee8b | 713 | struct sk_buff *skb = lp->tx_skb; |
1d15d6b5 | 714 | |
35e92a8e | 715 | enable_irq(lp->spi->irq); |
955aee8b | 716 | |
5f5c5c23 | 717 | ieee802154_xmit_complete(lp->hw, skb, !lp->tx_aret); |
1d15d6b5 AA |
718 | } |
719 | ||
720 | static void | |
721 | at86rf230_tx_on(void *context) | |
722 | { | |
723 | struct at86rf230_state_change *ctx = context; | |
724 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 725 | |
97fed795 AA |
726 | at86rf230_async_state_change(lp, &lp->irq, STATE_RX_AACK_ON, |
727 | at86rf230_tx_complete, true); | |
1d15d6b5 AA |
728 | } |
729 | ||
730 | static void | |
731 | at86rf230_tx_trac_error(void *context) | |
732 | { | |
733 | struct at86rf230_state_change *ctx = context; | |
734 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 735 | |
97fed795 AA |
736 | at86rf230_async_state_change(lp, ctx, STATE_TX_ON, |
737 | at86rf230_tx_on, true); | |
1d15d6b5 AA |
738 | } |
739 | ||
740 | static void | |
741 | at86rf230_tx_trac_check(void *context) | |
742 | { | |
743 | struct at86rf230_state_change *ctx = context; | |
744 | struct at86rf230_local *lp = ctx->lp; | |
745 | const u8 *buf = ctx->buf; | |
746 | const u8 trac = (buf[1] & 0xe0) >> 5; | |
1d15d6b5 AA |
747 | |
748 | /* If trac status is different than zero we need to do a state change | |
749 | * to STATE_FORCE_TRX_OFF then STATE_TX_ON to recover the transceiver | |
750 | * state to TX_ON. | |
751 | */ | |
752 | if (trac) { | |
97fed795 AA |
753 | at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF, |
754 | at86rf230_tx_trac_error, true); | |
1d15d6b5 AA |
755 | return; |
756 | } | |
757 | ||
758 | at86rf230_tx_on(context); | |
759 | } | |
760 | ||
1d15d6b5 AA |
761 | static void |
762 | at86rf230_tx_trac_status(void *context) | |
763 | { | |
764 | struct at86rf230_state_change *ctx = context; | |
765 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 766 | |
97fed795 AA |
767 | at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx, |
768 | at86rf230_tx_trac_check, true); | |
1d15d6b5 AA |
769 | } |
770 | ||
771 | static void | |
772 | at86rf230_rx(struct at86rf230_local *lp, | |
b89c3341 | 773 | const u8 *data, const u8 len, const u8 lqi) |
1d15d6b5 | 774 | { |
1d15d6b5 AA |
775 | struct sk_buff *skb; |
776 | u8 rx_local_buf[AT86RF2XX_MAX_BUF]; | |
777 | ||
1d15d6b5 AA |
778 | memcpy(rx_local_buf, data, len); |
779 | enable_irq(lp->spi->irq); | |
780 | ||
61a22814 | 781 | skb = dev_alloc_skb(IEEE802154_MTU); |
1d15d6b5 AA |
782 | if (!skb) { |
783 | dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n"); | |
784 | return; | |
785 | } | |
786 | ||
787 | memcpy(skb_put(skb, len), rx_local_buf, len); | |
b89c3341 | 788 | ieee802154_rx_irqsafe(lp->hw, skb, lqi); |
1d15d6b5 | 789 | } |
7b8e19b6 | 790 | |
1d15d6b5 AA |
791 | static void |
792 | at86rf230_rx_read_frame_complete(void *context) | |
793 | { | |
794 | struct at86rf230_state_change *ctx = context; | |
795 | struct at86rf230_local *lp = ctx->lp; | |
796 | const u8 *buf = lp->irq.buf; | |
d0e73c47 AA |
797 | u8 len = buf[1]; |
798 | ||
799 | if (!ieee802154_is_valid_psdu_len(len)) { | |
800 | dev_vdbg(&lp->spi->dev, "corrupted frame received\n"); | |
801 | len = IEEE802154_MTU; | |
802 | } | |
7b8e19b6 | 803 | |
2ac0f3a3 | 804 | at86rf230_rx(lp, buf + 2, len, buf[2 + len]); |
1d15d6b5 AA |
805 | } |
806 | ||
97fed795 | 807 | static void |
1d15d6b5 AA |
808 | at86rf230_rx_read_frame(struct at86rf230_local *lp) |
809 | { | |
97fed795 AA |
810 | int rc; |
811 | ||
1d15d6b5 | 812 | u8 *buf = lp->irq.buf; |
7b8e19b6 | 813 | |
814 | buf[0] = CMD_FB; | |
1d15d6b5 AA |
815 | lp->irq.trx.len = AT86RF2XX_MAX_BUF; |
816 | lp->irq.msg.complete = at86rf230_rx_read_frame_complete; | |
97fed795 AA |
817 | rc = spi_async(lp->spi, &lp->irq.msg); |
818 | if (rc) { | |
819 | enable_irq(lp->spi->irq); | |
820 | at86rf230_async_error(lp, &lp->irq, rc); | |
821 | } | |
1d15d6b5 AA |
822 | } |
823 | ||
824 | static void | |
825 | at86rf230_rx_trac_check(void *context) | |
826 | { | |
827 | struct at86rf230_state_change *ctx = context; | |
828 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 AA |
829 | |
830 | /* Possible check on trac status here. This could be useful to make | |
831 | * some stats why receive is failed. Not used at the moment, but it's | |
832 | * maybe timing relevant. Datasheet doesn't say anything about this. | |
833 | * The programming guide say do it so. | |
834 | */ | |
835 | ||
97fed795 | 836 | at86rf230_rx_read_frame(lp); |
1d15d6b5 AA |
837 | } |
838 | ||
97fed795 | 839 | static void |
1d15d6b5 AA |
840 | at86rf230_irq_trx_end(struct at86rf230_local *lp) |
841 | { | |
842 | spin_lock(&lp->lock); | |
843 | if (lp->is_tx) { | |
844 | lp->is_tx = 0; | |
845 | spin_unlock(&lp->lock); | |
1d15d6b5 AA |
846 | |
847 | if (lp->tx_aret) | |
97fed795 AA |
848 | at86rf230_async_state_change(lp, &lp->irq, |
849 | STATE_FORCE_TX_ON, | |
850 | at86rf230_tx_trac_status, | |
851 | true); | |
1d15d6b5 | 852 | else |
97fed795 AA |
853 | at86rf230_async_state_change(lp, &lp->irq, |
854 | STATE_RX_AACK_ON, | |
855 | at86rf230_tx_complete, | |
856 | true); | |
1d15d6b5 AA |
857 | } else { |
858 | spin_unlock(&lp->lock); | |
97fed795 AA |
859 | at86rf230_async_read_reg(lp, RG_TRX_STATE, &lp->irq, |
860 | at86rf230_rx_trac_check, true); | |
1d15d6b5 AA |
861 | } |
862 | } | |
863 | ||
864 | static void | |
865 | at86rf230_irq_status(void *context) | |
866 | { | |
867 | struct at86rf230_state_change *ctx = context; | |
868 | struct at86rf230_local *lp = ctx->lp; | |
869 | const u8 *buf = lp->irq.buf; | |
870 | const u8 irq = buf[1]; | |
1d15d6b5 AA |
871 | |
872 | if (irq & IRQ_TRX_END) { | |
97fed795 | 873 | at86rf230_irq_trx_end(lp); |
1d15d6b5 AA |
874 | } else { |
875 | enable_irq(lp->spi->irq); | |
876 | dev_err(&lp->spi->dev, "not supported irq %02x received\n", | |
877 | irq); | |
878 | } | |
879 | } | |
880 | ||
881 | static irqreturn_t at86rf230_isr(int irq, void *data) | |
882 | { | |
883 | struct at86rf230_local *lp = data; | |
884 | struct at86rf230_state_change *ctx = &lp->irq; | |
885 | u8 *buf = ctx->buf; | |
886 | int rc; | |
887 | ||
90566363 | 888 | disable_irq_nosync(irq); |
1d15d6b5 AA |
889 | |
890 | buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG; | |
891 | ctx->trx.len = 2; | |
892 | ctx->msg.complete = at86rf230_irq_status; | |
893 | rc = spi_async(lp->spi, &ctx->msg); | |
894 | if (rc) { | |
e9310211 | 895 | enable_irq(irq); |
1d15d6b5 AA |
896 | at86rf230_async_error(lp, ctx, rc); |
897 | return IRQ_NONE; | |
898 | } | |
899 | ||
900 | return IRQ_HANDLED; | |
901 | } | |
902 | ||
903 | static void | |
904 | at86rf230_write_frame_complete(void *context) | |
905 | { | |
906 | struct at86rf230_state_change *ctx = context; | |
907 | struct at86rf230_local *lp = ctx->lp; | |
908 | u8 *buf = ctx->buf; | |
909 | int rc; | |
910 | ||
911 | buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE; | |
912 | buf[1] = STATE_BUSY_TX; | |
913 | ctx->trx.len = 2; | |
914 | ctx->msg.complete = NULL; | |
915 | rc = spi_async(lp->spi, &ctx->msg); | |
916 | if (rc) | |
917 | at86rf230_async_error(lp, ctx, rc); | |
918 | } | |
919 | ||
920 | static void | |
921 | at86rf230_write_frame(void *context) | |
922 | { | |
923 | struct at86rf230_state_change *ctx = context; | |
924 | struct at86rf230_local *lp = ctx->lp; | |
925 | struct sk_buff *skb = lp->tx_skb; | |
926 | u8 *buf = lp->tx.buf; | |
927 | int rc; | |
928 | ||
929 | spin_lock(&lp->lock); | |
930 | lp->is_tx = 1; | |
931 | spin_unlock(&lp->lock); | |
932 | ||
933 | buf[0] = CMD_FB | CMD_WRITE; | |
934 | buf[1] = skb->len + 2; | |
935 | memcpy(buf + 2, skb->data, skb->len); | |
936 | lp->tx.trx.len = skb->len + 2; | |
937 | lp->tx.msg.complete = at86rf230_write_frame_complete; | |
938 | rc = spi_async(lp->spi, &lp->tx.msg); | |
939 | if (rc) | |
940 | at86rf230_async_error(lp, ctx, rc); | |
941 | } | |
942 | ||
943 | static void | |
944 | at86rf230_xmit_tx_on(void *context) | |
945 | { | |
946 | struct at86rf230_state_change *ctx = context; | |
947 | struct at86rf230_local *lp = ctx->lp; | |
7b8e19b6 | 948 | |
97fed795 AA |
949 | at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON, |
950 | at86rf230_write_frame, false); | |
1d15d6b5 AA |
951 | } |
952 | ||
953 | static int | |
5a504397 | 954 | at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) |
1d15d6b5 | 955 | { |
5a504397 | 956 | struct at86rf230_local *lp = hw->priv; |
1d15d6b5 | 957 | struct at86rf230_state_change *ctx = &lp->tx; |
7b8e19b6 | 958 | |
1d15d6b5 | 959 | void (*tx_complete)(void *context) = at86rf230_write_frame; |
7b8e19b6 | 960 | |
1d15d6b5 | 961 | lp->tx_skb = skb; |
7b8e19b6 | 962 | |
1d15d6b5 AA |
963 | /* In ARET mode we need to go into STATE_TX_ARET_ON after we |
964 | * are in STATE_TX_ON. The pfad differs here, so we change | |
965 | * the complete handler. | |
966 | */ | |
967 | if (lp->tx_aret) | |
968 | tx_complete = at86rf230_xmit_tx_on; | |
7b8e19b6 | 969 | |
97fed795 AA |
970 | at86rf230_async_state_change(lp, ctx, STATE_TX_ON, tx_complete, false); |
971 | ||
1d15d6b5 | 972 | return 0; |
7b8e19b6 | 973 | } |
974 | ||
975 | static int | |
5a504397 | 976 | at86rf230_ed(struct ieee802154_hw *hw, u8 *level) |
7b8e19b6 | 977 | { |
7b8e19b6 | 978 | BUG_ON(!level); |
979 | *level = 0xbe; | |
980 | return 0; | |
981 | } | |
982 | ||
7b8e19b6 | 983 | static int |
5a504397 | 984 | at86rf230_start(struct ieee802154_hw *hw) |
7b8e19b6 | 985 | { |
5a504397 | 986 | return at86rf230_sync_state_change(hw->priv, STATE_RX_AACK_ON); |
7b8e19b6 | 987 | } |
988 | ||
989 | static void | |
5a504397 | 990 | at86rf230_stop(struct ieee802154_hw *hw) |
7b8e19b6 | 991 | { |
5a504397 | 992 | at86rf230_sync_state_change(hw->priv, STATE_FORCE_TRX_OFF); |
7b8e19b6 | 993 | } |
994 | ||
8fad346f | 995 | static int |
e37d2ec8 | 996 | at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel) |
8fad346f PB |
997 | { |
998 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); | |
999 | } | |
1000 | ||
1001 | static int | |
e37d2ec8 | 1002 | at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel) |
8fad346f PB |
1003 | { |
1004 | int rc; | |
1005 | ||
1006 | if (channel == 0) | |
1007 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0); | |
1008 | else | |
1009 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1); | |
1010 | if (rc < 0) | |
1011 | return rc; | |
1012 | ||
6ca00197 | 1013 | if (page == 0) { |
643e53c2 | 1014 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0); |
a53d1f7c | 1015 | lp->data->rssi_base_val = -100; |
6ca00197 | 1016 | } else { |
643e53c2 | 1017 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1); |
a53d1f7c | 1018 | lp->data->rssi_base_val = -98; |
6ca00197 | 1019 | } |
643e53c2 PB |
1020 | if (rc < 0) |
1021 | return rc; | |
1022 | ||
24ccb9f4 AA |
1023 | /* This sets the symbol_duration according frequency on the 212. |
1024 | * TODO move this handling while set channel and page in cfg802154. | |
1025 | * We can do that, this timings are according 802.15.4 standard. | |
1026 | * If we do that in cfg802154, this is a more generic calculation. | |
1027 | * | |
1028 | * This should also protected from ifs_timer. Means cancel timer and | |
1029 | * init with a new value. For now, this is okay. | |
1030 | */ | |
1031 | if (channel == 0) { | |
1032 | if (page == 0) { | |
1033 | /* SUB:0 and BPSK:0 -> BPSK-20 */ | |
1034 | lp->hw->phy->symbol_duration = 50; | |
1035 | } else { | |
1036 | /* SUB:1 and BPSK:0 -> BPSK-40 */ | |
1037 | lp->hw->phy->symbol_duration = 25; | |
1038 | } | |
1039 | } else { | |
1040 | if (page == 0) | |
2d6dde29 | 1041 | /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */ |
24ccb9f4 AA |
1042 | lp->hw->phy->symbol_duration = 40; |
1043 | else | |
2d6dde29 | 1044 | /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */ |
24ccb9f4 AA |
1045 | lp->hw->phy->symbol_duration = 16; |
1046 | } | |
1047 | ||
1048 | lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD * | |
1049 | lp->hw->phy->symbol_duration; | |
1050 | lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD * | |
1051 | lp->hw->phy->symbol_duration; | |
1052 | ||
8fad346f PB |
1053 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); |
1054 | } | |
1055 | ||
7b8e19b6 | 1056 | static int |
e37d2ec8 | 1057 | at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel) |
7b8e19b6 | 1058 | { |
5a504397 | 1059 | struct at86rf230_local *lp = hw->priv; |
7b8e19b6 | 1060 | int rc; |
1061 | ||
a53d1f7c | 1062 | rc = lp->data->set_channel(lp, page, channel); |
984e0c68 AA |
1063 | /* Wait for PLL */ |
1064 | usleep_range(lp->data->t_channel_switch, | |
1065 | lp->data->t_channel_switch + 10); | |
820bd66f | 1066 | return rc; |
7b8e19b6 | 1067 | } |
1068 | ||
1486774d | 1069 | static int |
5a504397 | 1070 | at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw, |
1486774d | 1071 | struct ieee802154_hw_addr_filt *filt, |
1072 | unsigned long changed) | |
1073 | { | |
5a504397 | 1074 | struct at86rf230_local *lp = hw->priv; |
1486774d | 1075 | |
57205c14 | 1076 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { |
b70ab2e8 PB |
1077 | u16 addr = le16_to_cpu(filt->short_addr); |
1078 | ||
1486774d | 1079 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1080 | "at86rf230_set_hw_addr_filt called for saddr\n"); |
b70ab2e8 PB |
1081 | __at86rf230_write(lp, RG_SHORT_ADDR_0, addr); |
1082 | __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8); | |
1486774d | 1083 | } |
1084 | ||
57205c14 | 1085 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { |
b70ab2e8 PB |
1086 | u16 pan = le16_to_cpu(filt->pan_id); |
1087 | ||
1486774d | 1088 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1089 | "at86rf230_set_hw_addr_filt called for pan id\n"); |
b70ab2e8 PB |
1090 | __at86rf230_write(lp, RG_PAN_ID_0, pan); |
1091 | __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8); | |
1486774d | 1092 | } |
1093 | ||
57205c14 | 1094 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { |
b70ab2e8 PB |
1095 | u8 i, addr[8]; |
1096 | ||
1097 | memcpy(addr, &filt->ieee_addr, 8); | |
1486774d | 1098 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1099 | "at86rf230_set_hw_addr_filt called for IEEE addr\n"); |
b70ab2e8 PB |
1100 | for (i = 0; i < 8; i++) |
1101 | __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]); | |
1486774d | 1102 | } |
1103 | ||
57205c14 | 1104 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { |
1486774d | 1105 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1106 | "at86rf230_set_hw_addr_filt called for panc change\n"); |
1486774d | 1107 | if (filt->pan_coord) |
1108 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1); | |
1109 | else | |
1110 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0); | |
1111 | } | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
9b2777d6 | 1116 | static int |
5a504397 | 1117 | at86rf230_set_txpower(struct ieee802154_hw *hw, int db) |
9b2777d6 | 1118 | { |
5a504397 | 1119 | struct at86rf230_local *lp = hw->priv; |
9b2777d6 PB |
1120 | |
1121 | /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five | |
1122 | * bits decrease power in 1dB steps. 0x60 represents extra PA gain of | |
1123 | * 0dB. | |
1124 | * thus, supported values for db range from -26 to 5, for 31dB of | |
1125 | * reduction to 0dB of reduction. | |
1126 | */ | |
1127 | if (db > 5 || db < -26) | |
1128 | return -EINVAL; | |
1129 | ||
1130 | db = -(db - 5); | |
1131 | ||
677676cd | 1132 | return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db); |
9b2777d6 PB |
1133 | } |
1134 | ||
84dda3c6 | 1135 | static int |
5a504397 | 1136 | at86rf230_set_lbt(struct ieee802154_hw *hw, bool on) |
84dda3c6 | 1137 | { |
5a504397 | 1138 | struct at86rf230_local *lp = hw->priv; |
84dda3c6 PB |
1139 | |
1140 | return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on); | |
1141 | } | |
1142 | ||
ba08fea5 | 1143 | static int |
7fe9a388 AA |
1144 | at86rf230_set_cca_mode(struct ieee802154_hw *hw, |
1145 | const struct wpan_phy_cca *cca) | |
ba08fea5 | 1146 | { |
5a504397 | 1147 | struct at86rf230_local *lp = hw->priv; |
7fe9a388 | 1148 | u8 val; |
ba08fea5 | 1149 | |
7fe9a388 AA |
1150 | /* mapping 802.15.4 to driver spec */ |
1151 | switch (cca->mode) { | |
1152 | case NL802154_CCA_ENERGY: | |
1153 | val = 1; | |
1154 | break; | |
1155 | case NL802154_CCA_CARRIER: | |
1156 | val = 2; | |
1157 | break; | |
1158 | case NL802154_CCA_ENERGY_CARRIER: | |
1159 | switch (cca->opt) { | |
1160 | case NL802154_CCA_OPT_ENERGY_CARRIER_AND: | |
1161 | val = 3; | |
1162 | break; | |
1163 | case NL802154_CCA_OPT_ENERGY_CARRIER_OR: | |
1164 | val = 0; | |
1165 | break; | |
1166 | default: | |
1167 | return -EINVAL; | |
1168 | } | |
1169 | break; | |
1170 | default: | |
1171 | return -EINVAL; | |
1172 | } | |
1173 | ||
1174 | return at86rf230_write_subreg(lp, SR_CCA_MODE, val); | |
ba08fea5 PB |
1175 | } |
1176 | ||
a7d7eda9 AA |
1177 | static int |
1178 | at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level) | |
1179 | { | |
1180 | return (level - lp->data->rssi_base_val) * 100 / 207; | |
1181 | } | |
1182 | ||
1183 | static int | |
1184 | at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level) | |
1185 | { | |
1186 | return (level - lp->data->rssi_base_val) / 2; | |
1187 | } | |
1188 | ||
6ca00197 | 1189 | static int |
5a504397 | 1190 | at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 level) |
6ca00197 | 1191 | { |
5a504397 | 1192 | struct at86rf230_local *lp = hw->priv; |
6ca00197 | 1193 | |
a53d1f7c | 1194 | if (level < lp->data->rssi_base_val || level > 30) |
6ca00197 PB |
1195 | return -EINVAL; |
1196 | ||
a7d7eda9 AA |
1197 | return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, |
1198 | lp->data->get_desense_steps(lp, level)); | |
6ca00197 PB |
1199 | } |
1200 | ||
f2fdd67c | 1201 | static int |
5a504397 | 1202 | at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be, |
f2fdd67c PB |
1203 | u8 retries) |
1204 | { | |
5a504397 | 1205 | struct at86rf230_local *lp = hw->priv; |
f2fdd67c PB |
1206 | int rc; |
1207 | ||
f2fdd67c PB |
1208 | rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be); |
1209 | if (rc) | |
1210 | return rc; | |
1211 | ||
1212 | rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be); | |
1213 | if (rc) | |
1214 | return rc; | |
1215 | ||
39d7f320 | 1216 | return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries); |
f2fdd67c PB |
1217 | } |
1218 | ||
1219 | static int | |
5a504397 | 1220 | at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries) |
f2fdd67c | 1221 | { |
5a504397 | 1222 | struct at86rf230_local *lp = hw->priv; |
f2fdd67c PB |
1223 | int rc = 0; |
1224 | ||
f2fdd67c | 1225 | lp->tx_aret = retries >= 0; |
850f43ac | 1226 | lp->max_frame_retries = retries; |
f2fdd67c PB |
1227 | |
1228 | if (retries >= 0) | |
1229 | rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries); | |
1230 | ||
1231 | return rc; | |
1232 | } | |
1233 | ||
92f45f54 AA |
1234 | static int |
1235 | at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on) | |
1236 | { | |
1237 | struct at86rf230_local *lp = hw->priv; | |
1238 | int rc; | |
1239 | ||
1240 | if (on) { | |
1241 | rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1); | |
1242 | if (rc < 0) | |
1243 | return rc; | |
1244 | ||
1245 | rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1); | |
1246 | if (rc < 0) | |
1247 | return rc; | |
1248 | } else { | |
1249 | rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0); | |
1250 | if (rc < 0) | |
1251 | return rc; | |
1252 | ||
1253 | rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0); | |
1254 | if (rc < 0) | |
1255 | return rc; | |
1256 | } | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
16301861 | 1261 | static const struct ieee802154_ops at86rf230_ops = { |
7b8e19b6 | 1262 | .owner = THIS_MODULE, |
955aee8b | 1263 | .xmit_async = at86rf230_xmit, |
7b8e19b6 | 1264 | .ed = at86rf230_ed, |
1265 | .set_channel = at86rf230_channel, | |
1266 | .start = at86rf230_start, | |
1267 | .stop = at86rf230_stop, | |
1486774d | 1268 | .set_hw_addr_filt = at86rf230_set_hw_addr_filt, |
640985ec AA |
1269 | .set_txpower = at86rf230_set_txpower, |
1270 | .set_lbt = at86rf230_set_lbt, | |
1271 | .set_cca_mode = at86rf230_set_cca_mode, | |
1272 | .set_cca_ed_level = at86rf230_set_cca_ed_level, | |
1273 | .set_csma_params = at86rf230_set_csma_params, | |
1274 | .set_frame_retries = at86rf230_set_frame_retries, | |
92f45f54 | 1275 | .set_promiscuous_mode = at86rf230_set_promiscuous_mode, |
8fad346f PB |
1276 | }; |
1277 | ||
a53d1f7c | 1278 | static struct at86rf2xx_chip_data at86rf233_data = { |
7a4ef918 | 1279 | .t_sleep_cycle = 330, |
984e0c68 | 1280 | .t_channel_switch = 11, |
09e536cd | 1281 | .t_reset_to_off = 26, |
2e0571c0 AA |
1282 | .t_off_to_aack = 80, |
1283 | .t_off_to_tx_on = 80, | |
1d15d6b5 AA |
1284 | .t_frame = 4096, |
1285 | .t_p_ack = 545, | |
1d15d6b5 | 1286 | .t_tx_timeout = 2000, |
a53d1f7c AA |
1287 | .rssi_base_val = -91, |
1288 | .set_channel = at86rf23x_set_channel, | |
a7d7eda9 | 1289 | .get_desense_steps = at86rf23x_get_desens_steps |
a53d1f7c AA |
1290 | }; |
1291 | ||
1292 | static struct at86rf2xx_chip_data at86rf231_data = { | |
7a4ef918 | 1293 | .t_sleep_cycle = 330, |
984e0c68 | 1294 | .t_channel_switch = 24, |
09e536cd | 1295 | .t_reset_to_off = 37, |
2e0571c0 AA |
1296 | .t_off_to_aack = 110, |
1297 | .t_off_to_tx_on = 110, | |
1d15d6b5 AA |
1298 | .t_frame = 4096, |
1299 | .t_p_ack = 545, | |
1d15d6b5 | 1300 | .t_tx_timeout = 2000, |
a53d1f7c AA |
1301 | .rssi_base_val = -91, |
1302 | .set_channel = at86rf23x_set_channel, | |
a7d7eda9 | 1303 | .get_desense_steps = at86rf23x_get_desens_steps |
a53d1f7c AA |
1304 | }; |
1305 | ||
1306 | static struct at86rf2xx_chip_data at86rf212_data = { | |
7a4ef918 | 1307 | .t_sleep_cycle = 330, |
984e0c68 | 1308 | .t_channel_switch = 11, |
09e536cd | 1309 | .t_reset_to_off = 26, |
2e0571c0 AA |
1310 | .t_off_to_aack = 200, |
1311 | .t_off_to_tx_on = 200, | |
1d15d6b5 AA |
1312 | .t_frame = 4096, |
1313 | .t_p_ack = 545, | |
1d15d6b5 | 1314 | .t_tx_timeout = 2000, |
a53d1f7c AA |
1315 | .rssi_base_val = -100, |
1316 | .set_channel = at86rf212_set_channel, | |
a7d7eda9 | 1317 | .get_desense_steps = at86rf212_get_desens_steps |
a53d1f7c AA |
1318 | }; |
1319 | ||
7b8e19b6 | 1320 | static int at86rf230_hw_init(struct at86rf230_local *lp) |
1321 | { | |
1db0558e | 1322 | int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH; |
f76014f7 | 1323 | unsigned int dvdd; |
f2fdd67c | 1324 | u8 csma_seed[2]; |
7b8e19b6 | 1325 | |
09e536cd | 1326 | rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF); |
7dcbd22a PB |
1327 | if (rc) |
1328 | return rc; | |
7b8e19b6 | 1329 | |
4af619ae | 1330 | irq_type = irq_get_trigger_type(lp->spi->irq); |
1db0558e | 1331 | if (irq_type == IRQ_TYPE_EDGE_FALLING) |
43b5abe0 | 1332 | irq_pol = IRQ_ACTIVE_LOW; |
43b5abe0 | 1333 | |
18c65049 | 1334 | rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol); |
43b5abe0 SH |
1335 | if (rc) |
1336 | return rc; | |
1337 | ||
6bd2b132 AA |
1338 | rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1); |
1339 | if (rc) | |
1340 | return rc; | |
1341 | ||
057dad6f | 1342 | rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END); |
7b8e19b6 | 1343 | if (rc) |
1344 | return rc; | |
1345 | ||
f2fdd67c PB |
1346 | get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed)); |
1347 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]); | |
1348 | if (rc) | |
1349 | return rc; | |
1350 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]); | |
1351 | if (rc) | |
1352 | return rc; | |
1353 | ||
7b8e19b6 | 1354 | /* CLKM changes are applied immediately */ |
1355 | rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00); | |
1356 | if (rc) | |
1357 | return rc; | |
1358 | ||
1359 | /* Turn CLKM Off */ | |
1360 | rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00); | |
1361 | if (rc) | |
1362 | return rc; | |
1363 | /* Wait the next SLEEP cycle */ | |
7a4ef918 AA |
1364 | usleep_range(lp->data->t_sleep_cycle, |
1365 | lp->data->t_sleep_cycle + 100); | |
7b8e19b6 | 1366 | |
1cc9fc53 | 1367 | rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd); |
7b8e19b6 | 1368 | if (rc) |
1369 | return rc; | |
1cc9fc53 | 1370 | if (!dvdd) { |
7b8e19b6 | 1371 | dev_err(&lp->spi->dev, "DVDD error\n"); |
1372 | return -EINVAL; | |
1373 | } | |
1374 | ||
05e3f2f3 AA |
1375 | /* Force setting slotted operation bit to 0. Sometimes the atben |
1376 | * sets this bit and I don't know why. We set this always force | |
1377 | * to zero while probing. | |
1378 | */ | |
6cc6399c | 1379 | return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0); |
7b8e19b6 | 1380 | } |
1381 | ||
fa2d3e94 AA |
1382 | static struct at86rf230_platform_data * |
1383 | at86rf230_get_pdata(struct spi_device *spi) | |
1384 | { | |
1385 | struct at86rf230_platform_data *pdata; | |
fa2d3e94 AA |
1386 | |
1387 | if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) | |
1388 | return spi->dev.platform_data; | |
1389 | ||
1390 | pdata = devm_kzalloc(&spi->dev, sizeof(*pdata), GFP_KERNEL); | |
1391 | if (!pdata) | |
1392 | goto done; | |
1393 | ||
1394 | pdata->rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0); | |
1395 | pdata->slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0); | |
1396 | ||
fa2d3e94 AA |
1397 | spi->dev.platform_data = pdata; |
1398 | done: | |
1399 | return pdata; | |
1400 | } | |
1401 | ||
c8ee0f56 AA |
1402 | static int |
1403 | at86rf230_detect_device(struct at86rf230_local *lp) | |
1404 | { | |
1405 | unsigned int part, version, val; | |
1406 | u16 man_id = 0; | |
1407 | const char *chip; | |
1408 | int rc; | |
1409 | ||
1410 | rc = __at86rf230_read(lp, RG_MAN_ID_0, &val); | |
1411 | if (rc) | |
1412 | return rc; | |
1413 | man_id |= val; | |
1414 | ||
1415 | rc = __at86rf230_read(lp, RG_MAN_ID_1, &val); | |
1416 | if (rc) | |
1417 | return rc; | |
1418 | man_id |= (val << 8); | |
1419 | ||
1420 | rc = __at86rf230_read(lp, RG_PART_NUM, &part); | |
1421 | if (rc) | |
1422 | return rc; | |
1423 | ||
7598968d | 1424 | rc = __at86rf230_read(lp, RG_VERSION_NUM, &version); |
c8ee0f56 AA |
1425 | if (rc) |
1426 | return rc; | |
1427 | ||
1428 | if (man_id != 0x001f) { | |
1429 | dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n", | |
1430 | man_id >> 8, man_id & 0xFF); | |
1431 | return -EINVAL; | |
1432 | } | |
1433 | ||
2ac0f3a3 | 1434 | lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK | |
c8fc84ed | 1435 | IEEE802154_HW_TXPOWER | IEEE802154_HW_ARET | |
92f45f54 | 1436 | IEEE802154_HW_AFILT | IEEE802154_HW_PROMISCUOUS; |
c8ee0f56 | 1437 | |
b48a7c18 AA |
1438 | lp->hw->phy->cca.mode = NL802154_CCA_ENERGY; |
1439 | ||
c8ee0f56 AA |
1440 | switch (part) { |
1441 | case 2: | |
1442 | chip = "at86rf230"; | |
1443 | rc = -ENOTSUPP; | |
1444 | break; | |
1445 | case 3: | |
1446 | chip = "at86rf231"; | |
a53d1f7c | 1447 | lp->data = &at86rf231_data; |
5a504397 | 1448 | lp->hw->phy->channels_supported[0] = 0x7FFF800; |
fe58d016 | 1449 | lp->hw->phy->current_channel = 11; |
24ccb9f4 | 1450 | lp->hw->phy->symbol_duration = 16; |
c8ee0f56 AA |
1451 | break; |
1452 | case 7: | |
1453 | chip = "at86rf212"; | |
4ecc8a55 AY |
1454 | lp->data = &at86rf212_data; |
1455 | lp->hw->flags |= IEEE802154_HW_LBT; | |
1456 | lp->hw->phy->channels_supported[0] = 0x00007FF; | |
1457 | lp->hw->phy->channels_supported[2] = 0x00007FF; | |
1458 | lp->hw->phy->current_channel = 5; | |
1459 | lp->hw->phy->symbol_duration = 25; | |
c8ee0f56 AA |
1460 | break; |
1461 | case 11: | |
1462 | chip = "at86rf233"; | |
a53d1f7c | 1463 | lp->data = &at86rf233_data; |
5a504397 | 1464 | lp->hw->phy->channels_supported[0] = 0x7FFF800; |
fe58d016 | 1465 | lp->hw->phy->current_channel = 13; |
24ccb9f4 | 1466 | lp->hw->phy->symbol_duration = 16; |
c8ee0f56 AA |
1467 | break; |
1468 | default: | |
2b8b7e29 | 1469 | chip = "unknown"; |
c8ee0f56 AA |
1470 | rc = -ENOTSUPP; |
1471 | break; | |
1472 | } | |
1473 | ||
1474 | dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version); | |
1475 | ||
1476 | return rc; | |
1477 | } | |
1478 | ||
1d15d6b5 AA |
1479 | static void |
1480 | at86rf230_setup_spi_messages(struct at86rf230_local *lp) | |
1481 | { | |
2e0571c0 AA |
1482 | lp->state.lp = lp; |
1483 | spi_message_init(&lp->state.msg); | |
1484 | lp->state.msg.context = &lp->state; | |
1485 | lp->state.trx.tx_buf = lp->state.buf; | |
1486 | lp->state.trx.rx_buf = lp->state.buf; | |
1487 | spi_message_add_tail(&lp->state.trx, &lp->state.msg); | |
1488 | ||
1d15d6b5 AA |
1489 | lp->irq.lp = lp; |
1490 | spi_message_init(&lp->irq.msg); | |
1491 | lp->irq.msg.context = &lp->irq; | |
1492 | lp->irq.trx.tx_buf = lp->irq.buf; | |
1493 | lp->irq.trx.rx_buf = lp->irq.buf; | |
1494 | spi_message_add_tail(&lp->irq.trx, &lp->irq.msg); | |
1495 | ||
1496 | lp->tx.lp = lp; | |
1497 | spi_message_init(&lp->tx.msg); | |
1498 | lp->tx.msg.context = &lp->tx; | |
1499 | lp->tx.trx.tx_buf = lp->tx.buf; | |
1500 | lp->tx.trx.rx_buf = lp->tx.buf; | |
1501 | spi_message_add_tail(&lp->tx.trx, &lp->tx.msg); | |
1502 | } | |
1503 | ||
bb1f4606 | 1504 | static int at86rf230_probe(struct spi_device *spi) |
7b8e19b6 | 1505 | { |
43b5abe0 | 1506 | struct at86rf230_platform_data *pdata; |
5a504397 | 1507 | struct ieee802154_hw *hw; |
7b8e19b6 | 1508 | struct at86rf230_local *lp; |
f76014f7 | 1509 | unsigned int status; |
4af619ae | 1510 | int rc, irq_type; |
7b8e19b6 | 1511 | |
1512 | if (!spi->irq) { | |
1513 | dev_err(&spi->dev, "no IRQ specified\n"); | |
1514 | return -EINVAL; | |
1515 | } | |
1516 | ||
fa2d3e94 | 1517 | pdata = at86rf230_get_pdata(spi); |
43b5abe0 SH |
1518 | if (!pdata) { |
1519 | dev_err(&spi->dev, "no platform_data\n"); | |
1520 | return -EINVAL; | |
1521 | } | |
1522 | ||
3fa27571 | 1523 | if (gpio_is_valid(pdata->rstn)) { |
0679e29b AA |
1524 | rc = devm_gpio_request_one(&spi->dev, pdata->rstn, |
1525 | GPIOF_OUT_INIT_HIGH, "rstn"); | |
3fa27571 AA |
1526 | if (rc) |
1527 | return rc; | |
1528 | } | |
7b8e19b6 | 1529 | |
8fad346f | 1530 | if (gpio_is_valid(pdata->slp_tr)) { |
0679e29b AA |
1531 | rc = devm_gpio_request_one(&spi->dev, pdata->slp_tr, |
1532 | GPIOF_OUT_INIT_LOW, "slp_tr"); | |
7b8e19b6 | 1533 | if (rc) |
0679e29b | 1534 | return rc; |
7b8e19b6 | 1535 | } |
1536 | ||
1537 | /* Reset */ | |
3fa27571 AA |
1538 | if (gpio_is_valid(pdata->rstn)) { |
1539 | udelay(1); | |
1540 | gpio_set_value(pdata->rstn, 0); | |
1541 | udelay(1); | |
1542 | gpio_set_value(pdata->rstn, 1); | |
1543 | usleep_range(120, 240); | |
1544 | } | |
7b8e19b6 | 1545 | |
5a504397 AA |
1546 | hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops); |
1547 | if (!hw) | |
640985ec AA |
1548 | return -ENOMEM; |
1549 | ||
5a504397 AA |
1550 | lp = hw->priv; |
1551 | lp->hw = hw; | |
640985ec | 1552 | lp->spi = spi; |
5a504397 | 1553 | hw->parent = &spi->dev; |
7c118c1a | 1554 | hw->vif_data_size = sizeof(*lp); |
f6f4e86a | 1555 | ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); |
8fad346f | 1556 | |
f76014f7 AA |
1557 | lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config); |
1558 | if (IS_ERR(lp->regmap)) { | |
1559 | rc = PTR_ERR(lp->regmap); | |
1560 | dev_err(&spi->dev, "Failed to allocate register map: %d\n", | |
1561 | rc); | |
1562 | goto free_dev; | |
1563 | } | |
1564 | ||
1d15d6b5 AA |
1565 | at86rf230_setup_spi_messages(lp); |
1566 | ||
c8ee0f56 AA |
1567 | rc = at86rf230_detect_device(lp); |
1568 | if (rc < 0) | |
1569 | goto free_dev; | |
1570 | ||
8fad346f | 1571 | spin_lock_init(&lp->lock); |
2e0571c0 | 1572 | init_completion(&lp->state_complete); |
8fad346f PB |
1573 | |
1574 | spi_set_drvdata(spi, lp); | |
1575 | ||
7b8e19b6 | 1576 | rc = at86rf230_hw_init(lp); |
1577 | if (rc) | |
1d15d6b5 | 1578 | goto free_dev; |
7b8e19b6 | 1579 | |
19626946 AA |
1580 | /* Read irq status register to reset irq line */ |
1581 | rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status); | |
7b8e19b6 | 1582 | if (rc) |
1d15d6b5 | 1583 | goto free_dev; |
7b8e19b6 | 1584 | |
1d15d6b5 AA |
1585 | irq_type = irq_get_trigger_type(spi->irq); |
1586 | if (!irq_type) | |
1587 | irq_type = IRQF_TRIGGER_RISING; | |
1588 | ||
1589 | rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr, | |
1590 | IRQF_SHARED | irq_type, dev_name(&spi->dev), lp); | |
057dad6f | 1591 | if (rc) |
1d15d6b5 | 1592 | goto free_dev; |
057dad6f | 1593 | |
5a504397 | 1594 | rc = ieee802154_register_hw(lp->hw); |
7b8e19b6 | 1595 | if (rc) |
1d15d6b5 | 1596 | goto free_dev; |
7b8e19b6 | 1597 | |
1598 | return rc; | |
1599 | ||
640985ec | 1600 | free_dev: |
5a504397 | 1601 | ieee802154_free_hw(lp->hw); |
8fad346f | 1602 | |
7b8e19b6 | 1603 | return rc; |
1604 | } | |
1605 | ||
bb1f4606 | 1606 | static int at86rf230_remove(struct spi_device *spi) |
7b8e19b6 | 1607 | { |
1608 | struct at86rf230_local *lp = spi_get_drvdata(spi); | |
1609 | ||
17e84a92 AA |
1610 | /* mask all at86rf230 irq's */ |
1611 | at86rf230_write_subreg(lp, SR_IRQ_MASK, 0); | |
5a504397 AA |
1612 | ieee802154_unregister_hw(lp->hw); |
1613 | ieee802154_free_hw(lp->hw); | |
7b8e19b6 | 1614 | dev_dbg(&spi->dev, "unregistered at86rf230\n"); |
0679e29b | 1615 | |
7b8e19b6 | 1616 | return 0; |
1617 | } | |
1618 | ||
1086b4f6 | 1619 | static const struct of_device_id at86rf230_of_match[] = { |
fa2d3e94 AA |
1620 | { .compatible = "atmel,at86rf230", }, |
1621 | { .compatible = "atmel,at86rf231", }, | |
1622 | { .compatible = "atmel,at86rf233", }, | |
1623 | { .compatible = "atmel,at86rf212", }, | |
1624 | { }, | |
1625 | }; | |
835cb7d2 | 1626 | MODULE_DEVICE_TABLE(of, at86rf230_of_match); |
fa2d3e94 | 1627 | |
90b15520 AA |
1628 | static const struct spi_device_id at86rf230_device_id[] = { |
1629 | { .name = "at86rf230", }, | |
1630 | { .name = "at86rf231", }, | |
1631 | { .name = "at86rf233", }, | |
1632 | { .name = "at86rf212", }, | |
1633 | { }, | |
1634 | }; | |
1635 | MODULE_DEVICE_TABLE(spi, at86rf230_device_id); | |
1636 | ||
7b8e19b6 | 1637 | static struct spi_driver at86rf230_driver = { |
90b15520 | 1638 | .id_table = at86rf230_device_id, |
7b8e19b6 | 1639 | .driver = { |
fa2d3e94 | 1640 | .of_match_table = of_match_ptr(at86rf230_of_match), |
7b8e19b6 | 1641 | .name = "at86rf230", |
1642 | .owner = THIS_MODULE, | |
1643 | }, | |
1644 | .probe = at86rf230_probe, | |
bb1f4606 | 1645 | .remove = at86rf230_remove, |
7b8e19b6 | 1646 | }; |
1647 | ||
395a5738 | 1648 | module_spi_driver(at86rf230_driver); |
7b8e19b6 | 1649 | |
1650 | MODULE_DESCRIPTION("AT86RF230 Transceiver Driver"); | |
1651 | MODULE_LICENSE("GPL v2"); |