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7b8e19b6 | 1 | /* |
2 | * AT86RF230/RF231 driver | |
3 | * | |
4 | * Copyright (C) 2009-2012 Siemens AG | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | * | |
19 | * Written by: | |
20 | * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> | |
21 | * Alexander Smirnov <alex.bluesman.smirnov@gmail.com> | |
22 | */ | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/interrupt.h> | |
4af619ae | 26 | #include <linux/irq.h> |
7b8e19b6 | 27 | #include <linux/gpio.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/workqueue.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/spi/spi.h> | |
33 | #include <linux/spi/at86rf230.h> | |
f76014f7 | 34 | #include <linux/regmap.h> |
7b8e19b6 | 35 | #include <linux/skbuff.h> |
fa2d3e94 | 36 | #include <linux/of_gpio.h> |
7b8e19b6 | 37 | |
38 | #include <net/mac802154.h> | |
39 | #include <net/wpan-phy.h> | |
40 | ||
41 | struct at86rf230_local { | |
42 | struct spi_device *spi; | |
7b8e19b6 | 43 | |
44 | u8 part; | |
45 | u8 vers; | |
46 | ||
47 | u8 buf[2]; | |
48 | struct mutex bmux; | |
49 | ||
50 | struct work_struct irqwork; | |
51 | struct completion tx_complete; | |
52 | ||
53 | struct ieee802154_dev *dev; | |
f76014f7 | 54 | struct regmap *regmap; |
7b8e19b6 | 55 | |
56 | spinlock_t lock; | |
057dad6f | 57 | bool irq_busy; |
7b8e19b6 | 58 | bool is_tx; |
f2fdd67c | 59 | bool tx_aret; |
6ca00197 PB |
60 | |
61 | int rssi_base_val; | |
7b8e19b6 | 62 | }; |
63 | ||
44a6bd86 | 64 | static bool is_rf212(struct at86rf230_local *local) |
8fad346f PB |
65 | { |
66 | return local->part == 7; | |
67 | } | |
68 | ||
7b8e19b6 | 69 | #define RG_TRX_STATUS (0x01) |
70 | #define SR_TRX_STATUS 0x01, 0x1f, 0 | |
71 | #define SR_RESERVED_01_3 0x01, 0x20, 5 | |
72 | #define SR_CCA_STATUS 0x01, 0x40, 6 | |
73 | #define SR_CCA_DONE 0x01, 0x80, 7 | |
74 | #define RG_TRX_STATE (0x02) | |
75 | #define SR_TRX_CMD 0x02, 0x1f, 0 | |
76 | #define SR_TRAC_STATUS 0x02, 0xe0, 5 | |
77 | #define RG_TRX_CTRL_0 (0x03) | |
78 | #define SR_CLKM_CTRL 0x03, 0x07, 0 | |
79 | #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 | |
80 | #define SR_PAD_IO_CLKM 0x03, 0x30, 4 | |
81 | #define SR_PAD_IO 0x03, 0xc0, 6 | |
82 | #define RG_TRX_CTRL_1 (0x04) | |
83 | #define SR_IRQ_POLARITY 0x04, 0x01, 0 | |
84 | #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 | |
85 | #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 | |
86 | #define SR_RX_BL_CTRL 0x04, 0x10, 4 | |
87 | #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 | |
88 | #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 | |
89 | #define SR_PA_EXT_EN 0x04, 0x80, 7 | |
90 | #define RG_PHY_TX_PWR (0x05) | |
91 | #define SR_TX_PWR 0x05, 0x0f, 0 | |
92 | #define SR_PA_LT 0x05, 0x30, 4 | |
93 | #define SR_PA_BUF_LT 0x05, 0xc0, 6 | |
94 | #define RG_PHY_RSSI (0x06) | |
95 | #define SR_RSSI 0x06, 0x1f, 0 | |
96 | #define SR_RND_VALUE 0x06, 0x60, 5 | |
97 | #define SR_RX_CRC_VALID 0x06, 0x80, 7 | |
98 | #define RG_PHY_ED_LEVEL (0x07) | |
99 | #define SR_ED_LEVEL 0x07, 0xff, 0 | |
100 | #define RG_PHY_CC_CCA (0x08) | |
101 | #define SR_CHANNEL 0x08, 0x1f, 0 | |
102 | #define SR_CCA_MODE 0x08, 0x60, 5 | |
103 | #define SR_CCA_REQUEST 0x08, 0x80, 7 | |
104 | #define RG_CCA_THRES (0x09) | |
105 | #define SR_CCA_ED_THRES 0x09, 0x0f, 0 | |
106 | #define SR_RESERVED_09_1 0x09, 0xf0, 4 | |
107 | #define RG_RX_CTRL (0x0a) | |
108 | #define SR_PDT_THRES 0x0a, 0x0f, 0 | |
109 | #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 | |
110 | #define RG_SFD_VALUE (0x0b) | |
111 | #define SR_SFD_VALUE 0x0b, 0xff, 0 | |
112 | #define RG_TRX_CTRL_2 (0x0c) | |
113 | #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 | |
8fad346f PB |
114 | #define SR_SUB_MODE 0x0c, 0x04, 2 |
115 | #define SR_BPSK_QPSK 0x0c, 0x08, 3 | |
643e53c2 PB |
116 | #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 |
117 | #define SR_RESERVED_0c_5 0x0c, 0x60, 5 | |
7b8e19b6 | 118 | #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 |
119 | #define RG_ANT_DIV (0x0d) | |
120 | #define SR_ANT_CTRL 0x0d, 0x03, 0 | |
121 | #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 | |
122 | #define SR_ANT_DIV_EN 0x0d, 0x08, 3 | |
123 | #define SR_RESERVED_0d_2 0x0d, 0x70, 4 | |
124 | #define SR_ANT_SEL 0x0d, 0x80, 7 | |
125 | #define RG_IRQ_MASK (0x0e) | |
126 | #define SR_IRQ_MASK 0x0e, 0xff, 0 | |
127 | #define RG_IRQ_STATUS (0x0f) | |
128 | #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 | |
129 | #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 | |
130 | #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 | |
131 | #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 | |
132 | #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 | |
133 | #define SR_IRQ_5_AMI 0x0f, 0x20, 5 | |
134 | #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 | |
135 | #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 | |
136 | #define RG_VREG_CTRL (0x10) | |
137 | #define SR_RESERVED_10_6 0x10, 0x03, 0 | |
138 | #define SR_DVDD_OK 0x10, 0x04, 2 | |
139 | #define SR_DVREG_EXT 0x10, 0x08, 3 | |
140 | #define SR_RESERVED_10_3 0x10, 0x30, 4 | |
141 | #define SR_AVDD_OK 0x10, 0x40, 6 | |
142 | #define SR_AVREG_EXT 0x10, 0x80, 7 | |
143 | #define RG_BATMON (0x11) | |
144 | #define SR_BATMON_VTH 0x11, 0x0f, 0 | |
145 | #define SR_BATMON_HR 0x11, 0x10, 4 | |
146 | #define SR_BATMON_OK 0x11, 0x20, 5 | |
147 | #define SR_RESERVED_11_1 0x11, 0xc0, 6 | |
148 | #define RG_XOSC_CTRL (0x12) | |
149 | #define SR_XTAL_TRIM 0x12, 0x0f, 0 | |
150 | #define SR_XTAL_MODE 0x12, 0xf0, 4 | |
151 | #define RG_RX_SYN (0x15) | |
152 | #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 | |
153 | #define SR_RESERVED_15_2 0x15, 0x70, 4 | |
154 | #define SR_RX_PDT_DIS 0x15, 0x80, 7 | |
155 | #define RG_XAH_CTRL_1 (0x17) | |
156 | #define SR_RESERVED_17_8 0x17, 0x01, 0 | |
157 | #define SR_AACK_PROM_MODE 0x17, 0x02, 1 | |
158 | #define SR_AACK_ACK_TIME 0x17, 0x04, 2 | |
159 | #define SR_RESERVED_17_5 0x17, 0x08, 3 | |
160 | #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 | |
161 | #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 | |
84dda3c6 | 162 | #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
7b8e19b6 | 163 | #define SR_RESERVED_17_1 0x17, 0x80, 7 |
164 | #define RG_FTN_CTRL (0x18) | |
165 | #define SR_RESERVED_18_2 0x18, 0x7f, 0 | |
166 | #define SR_FTN_START 0x18, 0x80, 7 | |
167 | #define RG_PLL_CF (0x1a) | |
168 | #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 | |
169 | #define SR_PLL_CF_START 0x1a, 0x80, 7 | |
170 | #define RG_PLL_DCU (0x1b) | |
171 | #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 | |
172 | #define SR_RESERVED_1b_2 0x1b, 0x40, 6 | |
173 | #define SR_PLL_DCU_START 0x1b, 0x80, 7 | |
174 | #define RG_PART_NUM (0x1c) | |
175 | #define SR_PART_NUM 0x1c, 0xff, 0 | |
176 | #define RG_VERSION_NUM (0x1d) | |
177 | #define SR_VERSION_NUM 0x1d, 0xff, 0 | |
178 | #define RG_MAN_ID_0 (0x1e) | |
179 | #define SR_MAN_ID_0 0x1e, 0xff, 0 | |
180 | #define RG_MAN_ID_1 (0x1f) | |
181 | #define SR_MAN_ID_1 0x1f, 0xff, 0 | |
182 | #define RG_SHORT_ADDR_0 (0x20) | |
183 | #define SR_SHORT_ADDR_0 0x20, 0xff, 0 | |
184 | #define RG_SHORT_ADDR_1 (0x21) | |
185 | #define SR_SHORT_ADDR_1 0x21, 0xff, 0 | |
186 | #define RG_PAN_ID_0 (0x22) | |
187 | #define SR_PAN_ID_0 0x22, 0xff, 0 | |
188 | #define RG_PAN_ID_1 (0x23) | |
189 | #define SR_PAN_ID_1 0x23, 0xff, 0 | |
190 | #define RG_IEEE_ADDR_0 (0x24) | |
191 | #define SR_IEEE_ADDR_0 0x24, 0xff, 0 | |
192 | #define RG_IEEE_ADDR_1 (0x25) | |
193 | #define SR_IEEE_ADDR_1 0x25, 0xff, 0 | |
194 | #define RG_IEEE_ADDR_2 (0x26) | |
195 | #define SR_IEEE_ADDR_2 0x26, 0xff, 0 | |
196 | #define RG_IEEE_ADDR_3 (0x27) | |
197 | #define SR_IEEE_ADDR_3 0x27, 0xff, 0 | |
198 | #define RG_IEEE_ADDR_4 (0x28) | |
199 | #define SR_IEEE_ADDR_4 0x28, 0xff, 0 | |
200 | #define RG_IEEE_ADDR_5 (0x29) | |
201 | #define SR_IEEE_ADDR_5 0x29, 0xff, 0 | |
202 | #define RG_IEEE_ADDR_6 (0x2a) | |
203 | #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 | |
204 | #define RG_IEEE_ADDR_7 (0x2b) | |
205 | #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 | |
206 | #define RG_XAH_CTRL_0 (0x2c) | |
207 | #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 | |
208 | #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 | |
209 | #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 | |
210 | #define RG_CSMA_SEED_0 (0x2d) | |
211 | #define SR_CSMA_SEED_0 0x2d, 0xff, 0 | |
212 | #define RG_CSMA_SEED_1 (0x2e) | |
213 | #define SR_CSMA_SEED_1 0x2e, 0x07, 0 | |
214 | #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 | |
215 | #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 | |
216 | #define SR_AACK_SET_PD 0x2e, 0x20, 5 | |
217 | #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 | |
218 | #define RG_CSMA_BE (0x2f) | |
219 | #define SR_MIN_BE 0x2f, 0x0f, 0 | |
220 | #define SR_MAX_BE 0x2f, 0xf0, 4 | |
221 | ||
222 | #define CMD_REG 0x80 | |
223 | #define CMD_REG_MASK 0x3f | |
224 | #define CMD_WRITE 0x40 | |
225 | #define CMD_FB 0x20 | |
226 | ||
227 | #define IRQ_BAT_LOW (1 << 7) | |
228 | #define IRQ_TRX_UR (1 << 6) | |
229 | #define IRQ_AMI (1 << 5) | |
230 | #define IRQ_CCA_ED (1 << 4) | |
231 | #define IRQ_TRX_END (1 << 3) | |
232 | #define IRQ_RX_START (1 << 2) | |
233 | #define IRQ_PLL_UNL (1 << 1) | |
234 | #define IRQ_PLL_LOCK (1 << 0) | |
235 | ||
43b5abe0 SH |
236 | #define IRQ_ACTIVE_HIGH 0 |
237 | #define IRQ_ACTIVE_LOW 1 | |
238 | ||
7b8e19b6 | 239 | #define STATE_P_ON 0x00 /* BUSY */ |
240 | #define STATE_BUSY_RX 0x01 | |
241 | #define STATE_BUSY_TX 0x02 | |
242 | #define STATE_FORCE_TRX_OFF 0x03 | |
243 | #define STATE_FORCE_TX_ON 0x04 /* IDLE */ | |
244 | /* 0x05 */ /* INVALID_PARAMETER */ | |
245 | #define STATE_RX_ON 0x06 | |
246 | /* 0x07 */ /* SUCCESS */ | |
247 | #define STATE_TRX_OFF 0x08 | |
248 | #define STATE_TX_ON 0x09 | |
249 | /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */ | |
250 | #define STATE_SLEEP 0x0F | |
48d5dbaf | 251 | #define STATE_PREP_DEEP_SLEEP 0x10 |
7b8e19b6 | 252 | #define STATE_BUSY_RX_AACK 0x11 |
253 | #define STATE_BUSY_TX_ARET 0x12 | |
028889b0 | 254 | #define STATE_RX_AACK_ON 0x16 |
255 | #define STATE_TX_ARET_ON 0x19 | |
7b8e19b6 | 256 | #define STATE_RX_ON_NOCLK 0x1C |
257 | #define STATE_RX_AACK_ON_NOCLK 0x1D | |
258 | #define STATE_BUSY_RX_AACK_NOCLK 0x1E | |
259 | #define STATE_TRANSITION_IN_PROGRESS 0x1F | |
260 | ||
f76014f7 AA |
261 | #define AT86RF2XX_NUMREGS 0x3F |
262 | ||
263 | static inline int | |
264 | __at86rf230_write(struct at86rf230_local *lp, | |
265 | unsigned int addr, unsigned int data) | |
266 | { | |
267 | return regmap_write(lp->regmap, addr, data); | |
268 | } | |
269 | ||
270 | static inline int | |
271 | __at86rf230_read(struct at86rf230_local *lp, | |
272 | unsigned int addr, unsigned int *data) | |
273 | { | |
274 | return regmap_read(lp->regmap, addr, data); | |
275 | } | |
276 | ||
277 | static inline int | |
278 | at86rf230_read_subreg(struct at86rf230_local *lp, | |
279 | unsigned int addr, unsigned int mask, | |
280 | unsigned int shift, unsigned int *data) | |
281 | { | |
282 | int rc; | |
283 | ||
284 | rc = __at86rf230_read(lp, addr, data); | |
285 | if (rc > 0) | |
286 | *data = (*data & mask) >> shift; | |
287 | ||
288 | return rc; | |
289 | } | |
290 | ||
291 | static inline int | |
292 | at86rf230_write_subreg(struct at86rf230_local *lp, | |
293 | unsigned int addr, unsigned int mask, | |
294 | unsigned int shift, unsigned int data) | |
295 | { | |
296 | return regmap_update_bits(lp->regmap, addr, mask, data << shift); | |
297 | } | |
298 | ||
299 | static bool | |
300 | at86rf230_reg_writeable(struct device *dev, unsigned int reg) | |
301 | { | |
302 | switch (reg) { | |
303 | case RG_TRX_STATE: | |
304 | case RG_TRX_CTRL_0: | |
305 | case RG_TRX_CTRL_1: | |
306 | case RG_PHY_TX_PWR: | |
307 | case RG_PHY_ED_LEVEL: | |
308 | case RG_PHY_CC_CCA: | |
309 | case RG_CCA_THRES: | |
310 | case RG_RX_CTRL: | |
311 | case RG_SFD_VALUE: | |
312 | case RG_TRX_CTRL_2: | |
313 | case RG_ANT_DIV: | |
314 | case RG_IRQ_MASK: | |
315 | case RG_VREG_CTRL: | |
316 | case RG_BATMON: | |
317 | case RG_XOSC_CTRL: | |
318 | case RG_RX_SYN: | |
319 | case RG_XAH_CTRL_1: | |
320 | case RG_FTN_CTRL: | |
321 | case RG_PLL_CF: | |
322 | case RG_PLL_DCU: | |
323 | case RG_SHORT_ADDR_0: | |
324 | case RG_SHORT_ADDR_1: | |
325 | case RG_PAN_ID_0: | |
326 | case RG_PAN_ID_1: | |
327 | case RG_IEEE_ADDR_0: | |
328 | case RG_IEEE_ADDR_1: | |
329 | case RG_IEEE_ADDR_2: | |
330 | case RG_IEEE_ADDR_3: | |
331 | case RG_IEEE_ADDR_4: | |
332 | case RG_IEEE_ADDR_5: | |
333 | case RG_IEEE_ADDR_6: | |
334 | case RG_IEEE_ADDR_7: | |
335 | case RG_XAH_CTRL_0: | |
336 | case RG_CSMA_SEED_0: | |
337 | case RG_CSMA_SEED_1: | |
338 | case RG_CSMA_BE: | |
339 | return true; | |
340 | default: | |
341 | return false; | |
342 | } | |
343 | } | |
344 | ||
345 | static bool | |
346 | at86rf230_reg_readable(struct device *dev, unsigned int reg) | |
347 | { | |
348 | bool rc; | |
349 | ||
350 | /* all writeable are also readable */ | |
351 | rc = at86rf230_reg_writeable(dev, reg); | |
352 | if (rc) | |
353 | return rc; | |
354 | ||
355 | /* readonly regs */ | |
356 | switch (reg) { | |
357 | case RG_TRX_STATUS: | |
358 | case RG_PHY_RSSI: | |
359 | case RG_IRQ_STATUS: | |
360 | case RG_PART_NUM: | |
361 | case RG_VERSION_NUM: | |
362 | case RG_MAN_ID_1: | |
363 | case RG_MAN_ID_0: | |
364 | return true; | |
365 | default: | |
366 | return false; | |
367 | } | |
368 | } | |
369 | ||
370 | static bool | |
371 | at86rf230_reg_volatile(struct device *dev, unsigned int reg) | |
372 | { | |
373 | /* can be changed during runtime */ | |
374 | switch (reg) { | |
375 | case RG_TRX_STATUS: | |
376 | case RG_TRX_STATE: | |
377 | case RG_PHY_RSSI: | |
378 | case RG_PHY_ED_LEVEL: | |
379 | case RG_IRQ_STATUS: | |
380 | case RG_VREG_CTRL: | |
381 | return true; | |
382 | default: | |
383 | return false; | |
384 | } | |
385 | } | |
386 | ||
387 | static bool | |
388 | at86rf230_reg_precious(struct device *dev, unsigned int reg) | |
389 | { | |
390 | /* don't clear irq line on read */ | |
391 | switch (reg) { | |
392 | case RG_IRQ_STATUS: | |
393 | return true; | |
394 | default: | |
395 | return false; | |
396 | } | |
397 | } | |
398 | ||
399 | static struct regmap_config at86rf230_regmap_spi_config = { | |
400 | .reg_bits = 8, | |
401 | .val_bits = 8, | |
402 | .write_flag_mask = CMD_REG | CMD_WRITE, | |
403 | .read_flag_mask = CMD_REG, | |
404 | .cache_type = REGCACHE_RBTREE, | |
405 | .max_register = AT86RF2XX_NUMREGS, | |
406 | .writeable_reg = at86rf230_reg_writeable, | |
407 | .readable_reg = at86rf230_reg_readable, | |
408 | .volatile_reg = at86rf230_reg_volatile, | |
409 | .precious_reg = at86rf230_reg_precious, | |
410 | }; | |
411 | ||
8fad346f PB |
412 | static int |
413 | __at86rf230_detect_device(struct spi_device *spi, u16 *man_id, u8 *part, | |
414 | u8 *version) | |
415 | { | |
416 | u8 data[4]; | |
417 | u8 *buf = kmalloc(2, GFP_KERNEL); | |
418 | int status; | |
419 | struct spi_message msg; | |
420 | struct spi_transfer xfer = { | |
421 | .len = 2, | |
422 | .tx_buf = buf, | |
423 | .rx_buf = buf, | |
424 | }; | |
425 | u8 reg; | |
426 | ||
427 | if (!buf) | |
428 | return -ENOMEM; | |
429 | ||
430 | for (reg = RG_PART_NUM; reg <= RG_MAN_ID_1; reg++) { | |
431 | buf[0] = (reg & CMD_REG_MASK) | CMD_REG; | |
432 | buf[1] = 0xff; | |
433 | dev_vdbg(&spi->dev, "buf[0] = %02x\n", buf[0]); | |
434 | spi_message_init(&msg); | |
435 | spi_message_add_tail(&xfer, &msg); | |
436 | ||
437 | status = spi_sync(spi, &msg); | |
438 | dev_vdbg(&spi->dev, "status = %d\n", status); | |
439 | if (msg.status) | |
440 | status = msg.status; | |
441 | ||
442 | dev_vdbg(&spi->dev, "status = %d\n", status); | |
443 | dev_vdbg(&spi->dev, "buf[0] = %02x\n", buf[0]); | |
444 | dev_vdbg(&spi->dev, "buf[1] = %02x\n", buf[1]); | |
445 | ||
446 | if (status == 0) | |
447 | data[reg - RG_PART_NUM] = buf[1]; | |
448 | else | |
449 | break; | |
450 | } | |
451 | ||
452 | if (status == 0) { | |
453 | *part = data[0]; | |
454 | *version = data[1]; | |
455 | *man_id = (data[3] << 8) | data[2]; | |
456 | } | |
457 | ||
458 | kfree(buf); | |
459 | ||
460 | return status; | |
461 | } | |
462 | ||
7b8e19b6 | 463 | static int |
464 | at86rf230_write_fbuf(struct at86rf230_local *lp, u8 *data, u8 len) | |
465 | { | |
466 | u8 *buf = lp->buf; | |
467 | int status; | |
468 | struct spi_message msg; | |
469 | struct spi_transfer xfer_head = { | |
470 | .len = 2, | |
471 | .tx_buf = buf, | |
472 | ||
473 | }; | |
474 | struct spi_transfer xfer_buf = { | |
475 | .len = len, | |
476 | .tx_buf = data, | |
477 | }; | |
478 | ||
479 | mutex_lock(&lp->bmux); | |
480 | buf[0] = CMD_WRITE | CMD_FB; | |
481 | buf[1] = len + 2; /* 2 bytes for CRC that isn't written */ | |
482 | ||
483 | dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]); | |
484 | dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]); | |
485 | ||
486 | spi_message_init(&msg); | |
487 | spi_message_add_tail(&xfer_head, &msg); | |
488 | spi_message_add_tail(&xfer_buf, &msg); | |
489 | ||
490 | status = spi_sync(lp->spi, &msg); | |
491 | dev_vdbg(&lp->spi->dev, "status = %d\n", status); | |
492 | if (msg.status) | |
493 | status = msg.status; | |
494 | ||
495 | dev_vdbg(&lp->spi->dev, "status = %d\n", status); | |
496 | dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]); | |
497 | dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]); | |
498 | ||
499 | mutex_unlock(&lp->bmux); | |
500 | return status; | |
501 | } | |
502 | ||
503 | static int | |
504 | at86rf230_read_fbuf(struct at86rf230_local *lp, u8 *data, u8 *len, u8 *lqi) | |
505 | { | |
506 | u8 *buf = lp->buf; | |
507 | int status; | |
508 | struct spi_message msg; | |
509 | struct spi_transfer xfer_head = { | |
510 | .len = 2, | |
511 | .tx_buf = buf, | |
512 | .rx_buf = buf, | |
513 | }; | |
514 | struct spi_transfer xfer_head1 = { | |
515 | .len = 2, | |
516 | .tx_buf = buf, | |
517 | .rx_buf = buf, | |
518 | }; | |
519 | struct spi_transfer xfer_buf = { | |
520 | .len = 0, | |
521 | .rx_buf = data, | |
522 | }; | |
523 | ||
524 | mutex_lock(&lp->bmux); | |
525 | ||
526 | buf[0] = CMD_FB; | |
527 | buf[1] = 0x00; | |
528 | ||
529 | spi_message_init(&msg); | |
530 | spi_message_add_tail(&xfer_head, &msg); | |
531 | ||
532 | status = spi_sync(lp->spi, &msg); | |
533 | dev_vdbg(&lp->spi->dev, "status = %d\n", status); | |
534 | ||
535 | xfer_buf.len = *(buf + 1) + 1; | |
536 | *len = buf[1]; | |
537 | ||
538 | buf[0] = CMD_FB; | |
539 | buf[1] = 0x00; | |
540 | ||
541 | spi_message_init(&msg); | |
542 | spi_message_add_tail(&xfer_head1, &msg); | |
543 | spi_message_add_tail(&xfer_buf, &msg); | |
544 | ||
545 | status = spi_sync(lp->spi, &msg); | |
546 | ||
547 | if (msg.status) | |
548 | status = msg.status; | |
549 | ||
550 | dev_vdbg(&lp->spi->dev, "status = %d\n", status); | |
551 | dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]); | |
552 | dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]); | |
553 | ||
554 | if (status) { | |
555 | if (lqi && (*len > lp->buf[1])) | |
556 | *lqi = data[lp->buf[1]]; | |
557 | } | |
558 | mutex_unlock(&lp->bmux); | |
559 | ||
560 | return status; | |
561 | } | |
562 | ||
563 | static int | |
564 | at86rf230_ed(struct ieee802154_dev *dev, u8 *level) | |
565 | { | |
566 | might_sleep(); | |
567 | BUG_ON(!level); | |
568 | *level = 0xbe; | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static int | |
573 | at86rf230_state(struct ieee802154_dev *dev, int state) | |
574 | { | |
575 | struct at86rf230_local *lp = dev->priv; | |
576 | int rc; | |
f76014f7 | 577 | unsigned int val; |
7b8e19b6 | 578 | u8 desired_status; |
579 | ||
580 | might_sleep(); | |
581 | ||
582 | if (state == STATE_FORCE_TX_ON) | |
583 | desired_status = STATE_TX_ON; | |
584 | else if (state == STATE_FORCE_TRX_OFF) | |
585 | desired_status = STATE_TRX_OFF; | |
586 | else | |
587 | desired_status = state; | |
588 | ||
589 | do { | |
590 | rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val); | |
591 | if (rc) | |
592 | goto err; | |
593 | } while (val == STATE_TRANSITION_IN_PROGRESS); | |
594 | ||
595 | if (val == desired_status) | |
596 | return 0; | |
597 | ||
598 | /* state is equal to phy states */ | |
599 | rc = at86rf230_write_subreg(lp, SR_TRX_CMD, state); | |
600 | if (rc) | |
601 | goto err; | |
602 | ||
603 | do { | |
604 | rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val); | |
605 | if (rc) | |
606 | goto err; | |
607 | } while (val == STATE_TRANSITION_IN_PROGRESS); | |
608 | ||
609 | ||
f2fdd67c PB |
610 | if (val == desired_status || |
611 | (desired_status == STATE_RX_ON && val == STATE_BUSY_RX) || | |
612 | (desired_status == STATE_RX_AACK_ON && val == STATE_BUSY_RX_AACK)) | |
7b8e19b6 | 613 | return 0; |
614 | ||
615 | pr_err("unexpected state change: %d, asked for %d\n", val, state); | |
616 | return -EBUSY; | |
617 | ||
618 | err: | |
619 | pr_err("error: %d\n", rc); | |
620 | return rc; | |
621 | } | |
622 | ||
623 | static int | |
624 | at86rf230_start(struct ieee802154_dev *dev) | |
625 | { | |
626 | struct at86rf230_local *lp = dev->priv; | |
627 | u8 rc; | |
628 | ||
629 | rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1); | |
630 | if (rc) | |
631 | return rc; | |
632 | ||
7332fcb8 | 633 | rc = at86rf230_state(dev, STATE_TX_ON); |
f2fdd67c PB |
634 | if (rc) |
635 | return rc; | |
636 | ||
5b520bbb | 637 | return at86rf230_state(dev, STATE_RX_AACK_ON); |
7b8e19b6 | 638 | } |
639 | ||
640 | static void | |
641 | at86rf230_stop(struct ieee802154_dev *dev) | |
642 | { | |
643 | at86rf230_state(dev, STATE_FORCE_TRX_OFF); | |
644 | } | |
645 | ||
8fad346f PB |
646 | static int |
647 | at86rf230_set_channel(struct at86rf230_local *lp, int page, int channel) | |
648 | { | |
6ca00197 PB |
649 | lp->rssi_base_val = -91; |
650 | ||
8fad346f PB |
651 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); |
652 | } | |
653 | ||
654 | static int | |
655 | at86rf212_set_channel(struct at86rf230_local *lp, int page, int channel) | |
656 | { | |
657 | int rc; | |
658 | ||
659 | if (channel == 0) | |
660 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0); | |
661 | else | |
662 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1); | |
663 | if (rc < 0) | |
664 | return rc; | |
665 | ||
6ca00197 | 666 | if (page == 0) { |
643e53c2 | 667 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0); |
6ca00197 PB |
668 | lp->rssi_base_val = -100; |
669 | } else { | |
643e53c2 | 670 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1); |
6ca00197 PB |
671 | lp->rssi_base_val = -98; |
672 | } | |
643e53c2 PB |
673 | if (rc < 0) |
674 | return rc; | |
675 | ||
8fad346f PB |
676 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); |
677 | } | |
678 | ||
7b8e19b6 | 679 | static int |
680 | at86rf230_channel(struct ieee802154_dev *dev, int page, int channel) | |
681 | { | |
682 | struct at86rf230_local *lp = dev->priv; | |
683 | int rc; | |
684 | ||
685 | might_sleep(); | |
686 | ||
8fad346f PB |
687 | if (page < 0 || page > 31 || |
688 | !(lp->dev->phy->channels_supported[page] & BIT(channel))) { | |
7b8e19b6 | 689 | WARN_ON(1); |
690 | return -EINVAL; | |
691 | } | |
692 | ||
8fad346f PB |
693 | if (is_rf212(lp)) |
694 | rc = at86rf212_set_channel(lp, page, channel); | |
695 | else | |
696 | rc = at86rf230_set_channel(lp, page, channel); | |
697 | if (rc < 0) | |
698 | return rc; | |
699 | ||
7b8e19b6 | 700 | msleep(1); /* Wait for PLL */ |
701 | dev->phy->current_channel = channel; | |
643e53c2 | 702 | dev->phy->current_page = page; |
7b8e19b6 | 703 | |
704 | return 0; | |
705 | } | |
706 | ||
707 | static int | |
708 | at86rf230_xmit(struct ieee802154_dev *dev, struct sk_buff *skb) | |
709 | { | |
710 | struct at86rf230_local *lp = dev->priv; | |
711 | int rc; | |
712 | unsigned long flags; | |
713 | ||
6e07a1e0 | 714 | spin_lock_irqsave(&lp->lock, flags); |
057dad6f | 715 | if (lp->irq_busy) { |
6e07a1e0 | 716 | spin_unlock_irqrestore(&lp->lock, flags); |
5b00f2ee | 717 | return -EBUSY; |
718 | } | |
6e07a1e0 | 719 | spin_unlock_irqrestore(&lp->lock, flags); |
5b00f2ee | 720 | |
7b8e19b6 | 721 | might_sleep(); |
722 | ||
723 | rc = at86rf230_state(dev, STATE_FORCE_TX_ON); | |
724 | if (rc) | |
725 | goto err; | |
726 | ||
727 | spin_lock_irqsave(&lp->lock, flags); | |
728 | lp->is_tx = 1; | |
16735d02 | 729 | reinit_completion(&lp->tx_complete); |
7b8e19b6 | 730 | spin_unlock_irqrestore(&lp->lock, flags); |
731 | ||
732 | rc = at86rf230_write_fbuf(lp, skb->data, skb->len); | |
733 | if (rc) | |
734 | goto err_rx; | |
735 | ||
f2fdd67c PB |
736 | if (lp->tx_aret) { |
737 | rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_TX_ARET_ON); | |
738 | if (rc) | |
739 | goto err_rx; | |
740 | } | |
741 | ||
7b8e19b6 | 742 | rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_BUSY_TX); |
743 | if (rc) | |
744 | goto err_rx; | |
745 | ||
746 | rc = wait_for_completion_interruptible(&lp->tx_complete); | |
747 | if (rc < 0) | |
748 | goto err_rx; | |
749 | ||
ee69559b | 750 | return at86rf230_start(dev); |
7b8e19b6 | 751 | err_rx: |
752 | at86rf230_start(dev); | |
753 | err: | |
754 | pr_err("error: %d\n", rc); | |
755 | ||
756 | spin_lock_irqsave(&lp->lock, flags); | |
757 | lp->is_tx = 0; | |
758 | spin_unlock_irqrestore(&lp->lock, flags); | |
759 | ||
760 | return rc; | |
761 | } | |
762 | ||
763 | static int at86rf230_rx(struct at86rf230_local *lp) | |
764 | { | |
765 | u8 len = 128, lqi = 0; | |
7b8e19b6 | 766 | struct sk_buff *skb; |
767 | ||
768 | skb = alloc_skb(len, GFP_KERNEL); | |
769 | ||
770 | if (!skb) | |
771 | return -ENOMEM; | |
772 | ||
5b00f2ee | 773 | if (at86rf230_read_fbuf(lp, skb_put(skb, len), &len, &lqi)) |
7b8e19b6 | 774 | goto err; |
7b8e19b6 | 775 | |
776 | if (len < 2) | |
777 | goto err; | |
778 | ||
779 | skb_trim(skb, len - 2); /* We do not put CRC into the frame */ | |
780 | ||
781 | ieee802154_rx_irqsafe(lp->dev, skb, lqi); | |
782 | ||
23c34215 | 783 | dev_dbg(&lp->spi->dev, "READ_FBUF: %d %x\n", len, lqi); |
7b8e19b6 | 784 | |
785 | return 0; | |
786 | err: | |
787 | pr_debug("received frame is too small\n"); | |
788 | ||
789 | kfree_skb(skb); | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
1486774d | 793 | static int |
794 | at86rf230_set_hw_addr_filt(struct ieee802154_dev *dev, | |
795 | struct ieee802154_hw_addr_filt *filt, | |
796 | unsigned long changed) | |
797 | { | |
798 | struct at86rf230_local *lp = dev->priv; | |
799 | ||
800 | if (changed & IEEE802515_AFILT_SADDR_CHANGED) { | |
b70ab2e8 PB |
801 | u16 addr = le16_to_cpu(filt->short_addr); |
802 | ||
1486774d | 803 | dev_vdbg(&lp->spi->dev, |
804 | "at86rf230_set_hw_addr_filt called for saddr\n"); | |
b70ab2e8 PB |
805 | __at86rf230_write(lp, RG_SHORT_ADDR_0, addr); |
806 | __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8); | |
1486774d | 807 | } |
808 | ||
809 | if (changed & IEEE802515_AFILT_PANID_CHANGED) { | |
b70ab2e8 PB |
810 | u16 pan = le16_to_cpu(filt->pan_id); |
811 | ||
1486774d | 812 | dev_vdbg(&lp->spi->dev, |
813 | "at86rf230_set_hw_addr_filt called for pan id\n"); | |
b70ab2e8 PB |
814 | __at86rf230_write(lp, RG_PAN_ID_0, pan); |
815 | __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8); | |
1486774d | 816 | } |
817 | ||
818 | if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) { | |
b70ab2e8 PB |
819 | u8 i, addr[8]; |
820 | ||
821 | memcpy(addr, &filt->ieee_addr, 8); | |
1486774d | 822 | dev_vdbg(&lp->spi->dev, |
823 | "at86rf230_set_hw_addr_filt called for IEEE addr\n"); | |
b70ab2e8 PB |
824 | for (i = 0; i < 8; i++) |
825 | __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]); | |
1486774d | 826 | } |
827 | ||
828 | if (changed & IEEE802515_AFILT_PANC_CHANGED) { | |
829 | dev_vdbg(&lp->spi->dev, | |
830 | "at86rf230_set_hw_addr_filt called for panc change\n"); | |
831 | if (filt->pan_coord) | |
832 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1); | |
833 | else | |
834 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0); | |
835 | } | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
9b2777d6 | 840 | static int |
640985ec | 841 | at86rf230_set_txpower(struct ieee802154_dev *dev, int db) |
9b2777d6 PB |
842 | { |
843 | struct at86rf230_local *lp = dev->priv; | |
9b2777d6 PB |
844 | |
845 | /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five | |
846 | * bits decrease power in 1dB steps. 0x60 represents extra PA gain of | |
847 | * 0dB. | |
848 | * thus, supported values for db range from -26 to 5, for 31dB of | |
849 | * reduction to 0dB of reduction. | |
850 | */ | |
851 | if (db > 5 || db < -26) | |
852 | return -EINVAL; | |
853 | ||
854 | db = -(db - 5); | |
855 | ||
677676cd | 856 | return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db); |
9b2777d6 PB |
857 | } |
858 | ||
84dda3c6 | 859 | static int |
640985ec | 860 | at86rf230_set_lbt(struct ieee802154_dev *dev, bool on) |
84dda3c6 PB |
861 | { |
862 | struct at86rf230_local *lp = dev->priv; | |
863 | ||
864 | return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on); | |
865 | } | |
866 | ||
ba08fea5 | 867 | static int |
640985ec | 868 | at86rf230_set_cca_mode(struct ieee802154_dev *dev, u8 mode) |
ba08fea5 PB |
869 | { |
870 | struct at86rf230_local *lp = dev->priv; | |
871 | ||
872 | return at86rf230_write_subreg(lp, SR_CCA_MODE, mode); | |
873 | } | |
874 | ||
6ca00197 | 875 | static int |
640985ec | 876 | at86rf230_set_cca_ed_level(struct ieee802154_dev *dev, s32 level) |
6ca00197 PB |
877 | { |
878 | struct at86rf230_local *lp = dev->priv; | |
879 | int desens_steps; | |
880 | ||
881 | if (level < lp->rssi_base_val || level > 30) | |
882 | return -EINVAL; | |
883 | ||
884 | desens_steps = (level - lp->rssi_base_val) * 100 / 207; | |
885 | ||
886 | return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, desens_steps); | |
887 | } | |
888 | ||
f2fdd67c | 889 | static int |
640985ec | 890 | at86rf230_set_csma_params(struct ieee802154_dev *dev, u8 min_be, u8 max_be, |
f2fdd67c PB |
891 | u8 retries) |
892 | { | |
893 | struct at86rf230_local *lp = dev->priv; | |
894 | int rc; | |
895 | ||
896 | if (min_be > max_be || max_be > 8 || retries > 5) | |
897 | return -EINVAL; | |
898 | ||
899 | rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be); | |
900 | if (rc) | |
901 | return rc; | |
902 | ||
903 | rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be); | |
904 | if (rc) | |
905 | return rc; | |
906 | ||
39d7f320 | 907 | return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries); |
f2fdd67c PB |
908 | } |
909 | ||
910 | static int | |
640985ec | 911 | at86rf230_set_frame_retries(struct ieee802154_dev *dev, s8 retries) |
f2fdd67c PB |
912 | { |
913 | struct at86rf230_local *lp = dev->priv; | |
914 | int rc = 0; | |
915 | ||
916 | if (retries < -1 || retries > 15) | |
917 | return -EINVAL; | |
918 | ||
919 | lp->tx_aret = retries >= 0; | |
920 | ||
921 | if (retries >= 0) | |
922 | rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries); | |
923 | ||
924 | return rc; | |
925 | } | |
926 | ||
7b8e19b6 | 927 | static struct ieee802154_ops at86rf230_ops = { |
928 | .owner = THIS_MODULE, | |
929 | .xmit = at86rf230_xmit, | |
930 | .ed = at86rf230_ed, | |
931 | .set_channel = at86rf230_channel, | |
932 | .start = at86rf230_start, | |
933 | .stop = at86rf230_stop, | |
1486774d | 934 | .set_hw_addr_filt = at86rf230_set_hw_addr_filt, |
640985ec AA |
935 | .set_txpower = at86rf230_set_txpower, |
936 | .set_lbt = at86rf230_set_lbt, | |
937 | .set_cca_mode = at86rf230_set_cca_mode, | |
938 | .set_cca_ed_level = at86rf230_set_cca_ed_level, | |
939 | .set_csma_params = at86rf230_set_csma_params, | |
940 | .set_frame_retries = at86rf230_set_frame_retries, | |
8fad346f PB |
941 | }; |
942 | ||
7b8e19b6 | 943 | static void at86rf230_irqwork(struct work_struct *work) |
944 | { | |
945 | struct at86rf230_local *lp = | |
946 | container_of(work, struct at86rf230_local, irqwork); | |
f76014f7 | 947 | unsigned int status; |
7b8e19b6 | 948 | int rc; |
949 | unsigned long flags; | |
950 | ||
f76014f7 | 951 | rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status); |
7b8e19b6 | 952 | |
953 | status &= ~IRQ_PLL_LOCK; /* ignore */ | |
954 | status &= ~IRQ_RX_START; /* ignore */ | |
955 | status &= ~IRQ_AMI; /* ignore */ | |
956 | status &= ~IRQ_TRX_UR; /* FIXME: possibly handle ???*/ | |
957 | ||
958 | if (status & IRQ_TRX_END) { | |
959 | status &= ~IRQ_TRX_END; | |
7e814618 | 960 | spin_lock_irqsave(&lp->lock, flags); |
7b8e19b6 | 961 | if (lp->is_tx) { |
962 | lp->is_tx = 0; | |
5b00f2ee | 963 | spin_unlock_irqrestore(&lp->lock, flags); |
7b8e19b6 | 964 | complete(&lp->tx_complete); |
965 | } else { | |
5b00f2ee | 966 | spin_unlock_irqrestore(&lp->lock, flags); |
7b8e19b6 | 967 | at86rf230_rx(lp); |
968 | } | |
969 | } | |
970 | ||
5b00f2ee | 971 | spin_lock_irqsave(&lp->lock, flags); |
057dad6f | 972 | lp->irq_busy = 0; |
7b8e19b6 | 973 | spin_unlock_irqrestore(&lp->lock, flags); |
057dad6f SH |
974 | } |
975 | ||
976 | static void at86rf230_irqwork_level(struct work_struct *work) | |
977 | { | |
978 | struct at86rf230_local *lp = | |
979 | container_of(work, struct at86rf230_local, irqwork); | |
980 | ||
981 | at86rf230_irqwork(work); | |
5b00f2ee | 982 | |
983 | enable_irq(lp->spi->irq); | |
7b8e19b6 | 984 | } |
985 | ||
986 | static irqreturn_t at86rf230_isr(int irq, void *data) | |
987 | { | |
988 | struct at86rf230_local *lp = data; | |
6e07a1e0 | 989 | unsigned long flags; |
7b8e19b6 | 990 | |
6e07a1e0 | 991 | spin_lock_irqsave(&lp->lock, flags); |
057dad6f | 992 | lp->irq_busy = 1; |
6e07a1e0 | 993 | spin_unlock_irqrestore(&lp->lock, flags); |
7b8e19b6 | 994 | |
995 | schedule_work(&lp->irqwork); | |
996 | ||
997 | return IRQ_HANDLED; | |
998 | } | |
999 | ||
057dad6f SH |
1000 | static irqreturn_t at86rf230_isr_level(int irq, void *data) |
1001 | { | |
1002 | disable_irq_nosync(irq); | |
1003 | ||
1004 | return at86rf230_isr(irq, data); | |
1005 | } | |
1006 | ||
7b8e19b6 | 1007 | static int at86rf230_hw_init(struct at86rf230_local *lp) |
1008 | { | |
4af619ae | 1009 | int rc, irq_pol, irq_type; |
f76014f7 | 1010 | unsigned int dvdd; |
f2fdd67c | 1011 | u8 csma_seed[2]; |
7b8e19b6 | 1012 | |
7dcbd22a PB |
1013 | rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_FORCE_TRX_OFF); |
1014 | if (rc) | |
1015 | return rc; | |
7b8e19b6 | 1016 | |
4af619ae | 1017 | irq_type = irq_get_trigger_type(lp->spi->irq); |
43b5abe0 | 1018 | /* configure irq polarity, defaults to high active */ |
4af619ae | 1019 | if (irq_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) |
43b5abe0 SH |
1020 | irq_pol = IRQ_ACTIVE_LOW; |
1021 | else | |
1022 | irq_pol = IRQ_ACTIVE_HIGH; | |
1023 | ||
18c65049 | 1024 | rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol); |
43b5abe0 SH |
1025 | if (rc) |
1026 | return rc; | |
1027 | ||
057dad6f | 1028 | rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END); |
7b8e19b6 | 1029 | if (rc) |
1030 | return rc; | |
1031 | ||
f2fdd67c PB |
1032 | get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed)); |
1033 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]); | |
1034 | if (rc) | |
1035 | return rc; | |
1036 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]); | |
1037 | if (rc) | |
1038 | return rc; | |
1039 | ||
7b8e19b6 | 1040 | /* CLKM changes are applied immediately */ |
1041 | rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00); | |
1042 | if (rc) | |
1043 | return rc; | |
1044 | ||
1045 | /* Turn CLKM Off */ | |
1046 | rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00); | |
1047 | if (rc) | |
1048 | return rc; | |
1049 | /* Wait the next SLEEP cycle */ | |
1050 | msleep(100); | |
1051 | ||
1cc9fc53 | 1052 | rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd); |
7b8e19b6 | 1053 | if (rc) |
1054 | return rc; | |
1cc9fc53 | 1055 | if (!dvdd) { |
7b8e19b6 | 1056 | dev_err(&lp->spi->dev, "DVDD error\n"); |
1057 | return -EINVAL; | |
1058 | } | |
1059 | ||
7b8e19b6 | 1060 | return 0; |
1061 | } | |
1062 | ||
fa2d3e94 AA |
1063 | static struct at86rf230_platform_data * |
1064 | at86rf230_get_pdata(struct spi_device *spi) | |
1065 | { | |
1066 | struct at86rf230_platform_data *pdata; | |
fa2d3e94 AA |
1067 | |
1068 | if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) | |
1069 | return spi->dev.platform_data; | |
1070 | ||
1071 | pdata = devm_kzalloc(&spi->dev, sizeof(*pdata), GFP_KERNEL); | |
1072 | if (!pdata) | |
1073 | goto done; | |
1074 | ||
1075 | pdata->rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0); | |
1076 | pdata->slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0); | |
1077 | ||
fa2d3e94 AA |
1078 | spi->dev.platform_data = pdata; |
1079 | done: | |
1080 | return pdata; | |
1081 | } | |
1082 | ||
bb1f4606 | 1083 | static int at86rf230_probe(struct spi_device *spi) |
7b8e19b6 | 1084 | { |
43b5abe0 | 1085 | struct at86rf230_platform_data *pdata; |
7b8e19b6 | 1086 | struct ieee802154_dev *dev; |
1087 | struct at86rf230_local *lp; | |
8fad346f | 1088 | u16 man_id = 0; |
f76014f7 AA |
1089 | u8 part = 0, version = 0; |
1090 | unsigned int status; | |
057dad6f SH |
1091 | irq_handler_t irq_handler; |
1092 | work_func_t irq_worker; | |
4af619ae | 1093 | int rc, irq_type; |
7b8e19b6 | 1094 | const char *chip; |
7b8e19b6 | 1095 | |
1096 | if (!spi->irq) { | |
1097 | dev_err(&spi->dev, "no IRQ specified\n"); | |
1098 | return -EINVAL; | |
1099 | } | |
1100 | ||
fa2d3e94 | 1101 | pdata = at86rf230_get_pdata(spi); |
43b5abe0 SH |
1102 | if (!pdata) { |
1103 | dev_err(&spi->dev, "no platform_data\n"); | |
1104 | return -EINVAL; | |
1105 | } | |
1106 | ||
3fa27571 | 1107 | if (gpio_is_valid(pdata->rstn)) { |
0679e29b AA |
1108 | rc = devm_gpio_request_one(&spi->dev, pdata->rstn, |
1109 | GPIOF_OUT_INIT_HIGH, "rstn"); | |
3fa27571 AA |
1110 | if (rc) |
1111 | return rc; | |
1112 | } | |
7b8e19b6 | 1113 | |
8fad346f | 1114 | if (gpio_is_valid(pdata->slp_tr)) { |
0679e29b AA |
1115 | rc = devm_gpio_request_one(&spi->dev, pdata->slp_tr, |
1116 | GPIOF_OUT_INIT_LOW, "slp_tr"); | |
7b8e19b6 | 1117 | if (rc) |
0679e29b | 1118 | return rc; |
7b8e19b6 | 1119 | } |
1120 | ||
1121 | /* Reset */ | |
3fa27571 AA |
1122 | if (gpio_is_valid(pdata->rstn)) { |
1123 | udelay(1); | |
1124 | gpio_set_value(pdata->rstn, 0); | |
1125 | udelay(1); | |
1126 | gpio_set_value(pdata->rstn, 1); | |
1127 | usleep_range(120, 240); | |
1128 | } | |
7b8e19b6 | 1129 | |
640985ec AA |
1130 | dev = ieee802154_alloc_device(sizeof(*lp), &at86rf230_ops); |
1131 | if (!dev) | |
1132 | return -ENOMEM; | |
1133 | ||
1134 | lp = dev->priv; | |
1135 | lp->dev = dev; | |
1136 | lp->part = part; | |
1137 | lp->vers = version; | |
1138 | ||
1139 | lp->spi = spi; | |
1140 | ||
1141 | dev->parent = &spi->dev; | |
1142 | dev->extra_tx_headroom = 0; | |
1143 | dev->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK | | |
1144 | IEEE802154_HW_TXPOWER | IEEE802154_HW_CSMA; | |
1145 | ||
8fad346f PB |
1146 | rc = __at86rf230_detect_device(spi, &man_id, &part, &version); |
1147 | if (rc < 0) | |
640985ec | 1148 | goto free_dev; |
7b8e19b6 | 1149 | |
8fad346f | 1150 | if (man_id != 0x001f) { |
7b8e19b6 | 1151 | dev_err(&spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n", |
8fad346f | 1152 | man_id >> 8, man_id & 0xFF); |
0679e29b | 1153 | return -EINVAL; |
7b8e19b6 | 1154 | } |
1155 | ||
8fad346f | 1156 | switch (part) { |
7b8e19b6 | 1157 | case 2: |
1158 | chip = "at86rf230"; | |
640985ec | 1159 | rc = -ENOTSUPP; |
8fad346f | 1160 | /* FIXME: should be easy to support; */ |
7b8e19b6 | 1161 | break; |
1162 | case 3: | |
1163 | chip = "at86rf231"; | |
8fad346f PB |
1164 | break; |
1165 | case 7: | |
1166 | chip = "at86rf212"; | |
1167 | if (version == 1) | |
640985ec AA |
1168 | dev->flags |= IEEE802154_HW_LBT; |
1169 | else | |
1170 | rc = -ENOTSUPP; | |
7b8e19b6 | 1171 | break; |
48d5dbaf TS |
1172 | case 11: |
1173 | chip = "at86rf233"; | |
48d5dbaf | 1174 | break; |
7b8e19b6 | 1175 | default: |
1176 | chip = "UNKNOWN"; | |
640985ec | 1177 | rc = -ENOTSUPP; |
7b8e19b6 | 1178 | break; |
1179 | } | |
1180 | ||
8fad346f | 1181 | dev_info(&spi->dev, "Detected %s chip version %d\n", chip, version); |
640985ec AA |
1182 | if (rc < 0) |
1183 | goto free_dev; | |
8fad346f | 1184 | |
f76014f7 AA |
1185 | lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config); |
1186 | if (IS_ERR(lp->regmap)) { | |
1187 | rc = PTR_ERR(lp->regmap); | |
1188 | dev_err(&spi->dev, "Failed to allocate register map: %d\n", | |
1189 | rc); | |
1190 | goto free_dev; | |
1191 | } | |
1192 | ||
4af619ae | 1193 | irq_type = irq_get_trigger_type(spi->irq); |
363c2cd6 PB |
1194 | if (!irq_type) |
1195 | irq_type = IRQF_TRIGGER_RISING; | |
4af619ae | 1196 | if (irq_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { |
8fad346f PB |
1197 | irq_worker = at86rf230_irqwork; |
1198 | irq_handler = at86rf230_isr; | |
1199 | } else { | |
1200 | irq_worker = at86rf230_irqwork_level; | |
1201 | irq_handler = at86rf230_isr_level; | |
1202 | } | |
1203 | ||
1204 | mutex_init(&lp->bmux); | |
1205 | INIT_WORK(&lp->irqwork, irq_worker); | |
1206 | spin_lock_init(&lp->lock); | |
1207 | init_completion(&lp->tx_complete); | |
1208 | ||
1209 | spi_set_drvdata(spi, lp); | |
1210 | ||
643e53c2 | 1211 | if (is_rf212(lp)) { |
8fad346f | 1212 | dev->phy->channels_supported[0] = 0x00007FF; |
643e53c2 PB |
1213 | dev->phy->channels_supported[2] = 0x00007FF; |
1214 | } else { | |
8fad346f | 1215 | dev->phy->channels_supported[0] = 0x7FFF800; |
643e53c2 | 1216 | } |
8fad346f | 1217 | |
7b8e19b6 | 1218 | rc = at86rf230_hw_init(lp); |
1219 | if (rc) | |
8fad346f | 1220 | goto err_hw_init; |
7b8e19b6 | 1221 | |
19626946 AA |
1222 | /* Read irq status register to reset irq line */ |
1223 | rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status); | |
7b8e19b6 | 1224 | if (rc) |
8fad346f | 1225 | goto err_hw_init; |
7b8e19b6 | 1226 | |
363c2cd6 PB |
1227 | rc = devm_request_irq(&spi->dev, spi->irq, irq_handler, |
1228 | IRQF_SHARED | irq_type, | |
19626946 | 1229 | dev_name(&spi->dev), lp); |
057dad6f | 1230 | if (rc) |
652355c5 | 1231 | goto err_hw_init; |
057dad6f | 1232 | |
7b8e19b6 | 1233 | rc = ieee802154_register_device(lp->dev); |
1234 | if (rc) | |
652355c5 | 1235 | goto err_hw_init; |
7b8e19b6 | 1236 | |
1237 | return rc; | |
1238 | ||
8fad346f | 1239 | err_hw_init: |
7b8e19b6 | 1240 | flush_work(&lp->irqwork); |
7b8e19b6 | 1241 | mutex_destroy(&lp->bmux); |
640985ec | 1242 | free_dev: |
7b8e19b6 | 1243 | ieee802154_free_device(lp->dev); |
8fad346f | 1244 | |
7b8e19b6 | 1245 | return rc; |
1246 | } | |
1247 | ||
bb1f4606 | 1248 | static int at86rf230_remove(struct spi_device *spi) |
7b8e19b6 | 1249 | { |
1250 | struct at86rf230_local *lp = spi_get_drvdata(spi); | |
1251 | ||
17e84a92 AA |
1252 | /* mask all at86rf230 irq's */ |
1253 | at86rf230_write_subreg(lp, SR_IRQ_MASK, 0); | |
7b8e19b6 | 1254 | ieee802154_unregister_device(lp->dev); |
7b8e19b6 | 1255 | flush_work(&lp->irqwork); |
7b8e19b6 | 1256 | mutex_destroy(&lp->bmux); |
1257 | ieee802154_free_device(lp->dev); | |
7b8e19b6 | 1258 | dev_dbg(&spi->dev, "unregistered at86rf230\n"); |
0679e29b | 1259 | |
7b8e19b6 | 1260 | return 0; |
1261 | } | |
1262 | ||
1086b4f6 | 1263 | static const struct of_device_id at86rf230_of_match[] = { |
fa2d3e94 AA |
1264 | { .compatible = "atmel,at86rf230", }, |
1265 | { .compatible = "atmel,at86rf231", }, | |
1266 | { .compatible = "atmel,at86rf233", }, | |
1267 | { .compatible = "atmel,at86rf212", }, | |
1268 | { }, | |
1269 | }; | |
835cb7d2 | 1270 | MODULE_DEVICE_TABLE(of, at86rf230_of_match); |
fa2d3e94 | 1271 | |
90b15520 AA |
1272 | static const struct spi_device_id at86rf230_device_id[] = { |
1273 | { .name = "at86rf230", }, | |
1274 | { .name = "at86rf231", }, | |
1275 | { .name = "at86rf233", }, | |
1276 | { .name = "at86rf212", }, | |
1277 | { }, | |
1278 | }; | |
1279 | MODULE_DEVICE_TABLE(spi, at86rf230_device_id); | |
1280 | ||
7b8e19b6 | 1281 | static struct spi_driver at86rf230_driver = { |
90b15520 | 1282 | .id_table = at86rf230_device_id, |
7b8e19b6 | 1283 | .driver = { |
fa2d3e94 | 1284 | .of_match_table = of_match_ptr(at86rf230_of_match), |
7b8e19b6 | 1285 | .name = "at86rf230", |
1286 | .owner = THIS_MODULE, | |
1287 | }, | |
1288 | .probe = at86rf230_probe, | |
bb1f4606 | 1289 | .remove = at86rf230_remove, |
7b8e19b6 | 1290 | }; |
1291 | ||
395a5738 | 1292 | module_spi_driver(at86rf230_driver); |
7b8e19b6 | 1293 | |
1294 | MODULE_DESCRIPTION("AT86RF230 Transceiver Driver"); | |
1295 | MODULE_LICENSE("GPL v2"); |