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igb: add support for SGMII-based MDIO PHYs
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
2d064c06 33#include <linux/if_ether.h>
9d5c8243
AK		 34
35#include "e1000_mac.h"
36#include "e1000_82575.h"
37
38static s32 igb_get_invariants_82575(struct e1000_hw *);
39static s32 igb_acquire_phy_82575(struct e1000_hw *);
40static void igb_release_phy_82575(struct e1000_hw *);
41static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42static void igb_release_nvm_82575(struct e1000_hw *);
43static s32 igb_check_for_link_82575(struct e1000_hw *);
44static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 48static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 50static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 51static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243
AK		 52static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 54static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 55static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 58static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60static s32 igb_get_phy_id_82575(struct e1000_hw *);
61static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62static bool igb_sgmii_active_82575(struct e1000_hw *);
63static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
9d5c8243 66
bb2ac47b
AD		 67static const u16 e1000_82580_rxpbs_table[] =
68 { 36, 72, 144, 1, 2, 4, 8, 16,
69 35, 70, 140 };
70#define E1000_82580_RXPBS_TABLE_SIZE \
71 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
72
4085f746
NN		 73/**
74 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
75 * @hw: pointer to the HW structure
76 *
77 * Called to determine if the I2C pins are being used for I2C or as an
78 * external MDIO interface since the two options are mutually exclusive.
79 **/
80static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
81{
82 u32 reg = 0;
83 bool ext_mdio = false;
84
85 switch (hw->mac.type) {
86 case e1000_82575:
87 case e1000_82576:
88 reg = rd32(E1000_MDIC);
89 ext_mdio = !!(reg & E1000_MDIC_DEST);
90 break;
91 case e1000_82580:
92 case e1000_i350:
93 reg = rd32(E1000_MDICNFG);
94 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
95 break;
96 default:
97 break;
98 }
99 return ext_mdio;
100}
101
9d5c8243
AK		 102static s32 igb_get_invariants_82575(struct e1000_hw *hw)
103{
104 struct e1000_phy_info *phy = &hw->phy;
105 struct e1000_nvm_info *nvm = &hw->nvm;
106 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 107 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243
AK		 108 u32 eecd;
109 s32 ret_val;
110 u16 size;
111 u32 ctrl_ext = 0;
112
113 switch (hw->device_id) {
114 case E1000_DEV_ID_82575EB_COPPER:
115 case E1000_DEV_ID_82575EB_FIBER_SERDES:
116 case E1000_DEV_ID_82575GB_QUAD_COPPER:
117 mac->type = e1000_82575;
118 break;
2d064c06 119 case E1000_DEV_ID_82576:
9eb2341d 120 case E1000_DEV_ID_82576_NS:
747d49ba 121 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 122 case E1000_DEV_ID_82576_FIBER:
123 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 124 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 125 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 126 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 127 mac->type = e1000_82576;
128 break;
bb2ac47b
AD		 129 case E1000_DEV_ID_82580_COPPER:
130 case E1000_DEV_ID_82580_FIBER:
131 case E1000_DEV_ID_82580_SERDES:
132 case E1000_DEV_ID_82580_SGMII:
133 case E1000_DEV_ID_82580_COPPER_DUAL:
134 mac->type = e1000_82580;
135 break;
d2ba2ed8
AD		 136 case E1000_DEV_ID_I350_COPPER:
137 case E1000_DEV_ID_I350_FIBER:
138 case E1000_DEV_ID_I350_SERDES:
139 case E1000_DEV_ID_I350_SGMII:
140 mac->type = e1000_i350;
141 break;
9d5c8243
AK		 142 default:
143 return -E1000_ERR_MAC_INIT;
144 break;
145 }
146
9d5c8243
AK		 147 /* Set media type */
148 /*
149 * The 82575 uses bits 22:23 for link mode. The mode can be changed
150 * based on the EEPROM. We cannot rely upon device ID. There
151 * is no distinguishable difference between fiber and internal
152 * SerDes mode on the 82575. There can be an external PHY attached
153 * on the SGMII interface. For this, we'll set sgmii_active to true.
154 */
155 phy->media_type = e1000_media_type_copper;
156 dev_spec->sgmii_active = false;
157
158 ctrl_ext = rd32(E1000_CTRL_EXT);
2fb02a26
AD		 159 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
160 case E1000_CTRL_EXT_LINK_MODE_SGMII:
9d5c8243
AK		 161 dev_spec->sgmii_active = true;
162 ctrl_ext |= E1000_CTRL_I2C_ENA;
2fb02a26 163 break;
bb2ac47b 164 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26
AD		 165 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
166 hw->phy.media_type = e1000_media_type_internal_serdes;
167 ctrl_ext |= E1000_CTRL_I2C_ENA;
168 break;
169 default:
9d5c8243 170 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
2fb02a26 171 break;
9d5c8243 172 }
2fb02a26 173
9d5c8243
AK		 174 wr32(E1000_CTRL_EXT, ctrl_ext);
175
176 /* Set mta register count */
177 mac->mta_reg_count = 128;
178 /* Set rar entry count */
179 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
2d064c06
AD		 180 if (mac->type == e1000_82576)
181 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
bb2ac47b
AD		 182 if (mac->type == e1000_82580)
183 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
d2ba2ed8
AD		 184 if (mac->type == e1000_i350)
185 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
bb2ac47b 186 /* reset */
d2ba2ed8 187 if (mac->type >= e1000_82580)
bb2ac47b
AD		 188 mac->ops.reset_hw = igb_reset_hw_82580;
189 else
190 mac->ops.reset_hw = igb_reset_hw_82575;
9d5c8243
AK		 191 /* Set if part includes ASF firmware */
192 mac->asf_firmware_present = true;
193 /* Set if manageability features are enabled. */
194 mac->arc_subsystem_valid =
195 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
196 ? true : false;
197
198 /* physical interface link setup */
199 mac->ops.setup_physical_interface =
200 (hw->phy.media_type == e1000_media_type_copper)
201 ? igb_setup_copper_link_82575
2fb02a26 202 : igb_setup_serdes_link_82575;
9d5c8243
AK		 203
204 /* NVM initialization */
205 eecd = rd32(E1000_EECD);
206
207 nvm->opcode_bits = 8;
208 nvm->delay_usec = 1;
209 switch (nvm->override) {
210 case e1000_nvm_override_spi_large:
211 nvm->page_size = 32;
212 nvm->address_bits = 16;
213 break;
214 case e1000_nvm_override_spi_small:
215 nvm->page_size = 8;
216 nvm->address_bits = 8;
217 break;
218 default:
219 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
220 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
221 break;
222 }
223
224 nvm->type = e1000_nvm_eeprom_spi;
225
226 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
227 E1000_EECD_SIZE_EX_SHIFT);
228
229 /*
230 * Added to a constant, "size" becomes the left-shift value
231 * for setting word_size.
232 */
233 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75
JK		 234
235 /* EEPROM access above 16k is unsupported */
236 if (size > 14)
237 size = 14;
9d5c8243
AK		 238 nvm->word_size = 1 << size;
239
a0c98605
AD		 240 /* if 82576 then initialize mailbox parameters */
241 if (mac->type == e1000_82576)
242 igb_init_mbx_params_pf(hw);
243
9d5c8243
AK		 244 /* setup PHY parameters */
245 if (phy->media_type != e1000_media_type_copper) {
246 phy->type = e1000_phy_none;
247 return 0;
248 }
249
250 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
251 phy->reset_delay_us = 100;
252
253 /* PHY function pointers */
4085f746
NN		 254 if (igb_sgmii_active_82575(hw))
255 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
256 else
257 phy->ops.reset = igb_phy_hw_reset;
258
259 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
260 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
261 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
d2ba2ed8 262 } else if (hw->mac.type >= e1000_82580) {
4085f746
NN		 263 phy->ops.read_reg = igb_read_phy_reg_82580;
264 phy->ops.write_reg = igb_write_phy_reg_82580;
9d5c8243 265 } else {
4085f746
NN		 266 phy->ops.read_reg = igb_read_phy_reg_igp;
267 phy->ops.write_reg = igb_write_phy_reg_igp;
9d5c8243
AK		 268 }
269
19e588e7
AD		 270 /* set lan id */
271 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
272 E1000_STATUS_FUNC_SHIFT;
273
9d5c8243
AK		 274 /* Set phy->phy_addr and phy->id. */
275 ret_val = igb_get_phy_id_82575(hw);
276 if (ret_val)
277 return ret_val;
278
279 /* Verify phy id and set remaining function pointers */
280 switch (phy->id) {
281 case M88E1111_I_PHY_ID:
282 phy->type = e1000_phy_m88;
283 phy->ops.get_phy_info = igb_get_phy_info_m88;
284 phy->ops.get_cable_length = igb_get_cable_length_m88;
285 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
286 break;
287 case IGP03E1000_E_PHY_ID:
288 phy->type = e1000_phy_igp_3;
289 phy->ops.get_phy_info = igb_get_phy_info_igp;
290 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
291 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
292 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
293 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
294 break;
bb2ac47b 295 case I82580_I_PHY_ID:
d2ba2ed8 296 case I350_I_PHY_ID:
bb2ac47b
AD		 297 phy->type = e1000_phy_82580;
298 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
299 phy->ops.get_cable_length = igb_get_cable_length_82580;
300 phy->ops.get_phy_info = igb_get_phy_info_82580;
301 break;
9d5c8243
AK		 302 default:
303 return -E1000_ERR_PHY;
304 }
305
306 return 0;
307}
308
309/**
733596be 310 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 311 * @hw: pointer to the HW structure
312 *
313 * Acquire access rights to the correct PHY. This is a
314 * function pointer entry point called by the api module.
315 **/
316static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
317{
008c3422 318 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 319
008c3422
AD		 320 if (hw->bus.func == E1000_FUNC_1)
321 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 322 else if (hw->bus.func == E1000_FUNC_2)
323 mask = E1000_SWFW_PHY2_SM;
324 else if (hw->bus.func == E1000_FUNC_3)
325 mask = E1000_SWFW_PHY3_SM;
9d5c8243
AK		 326
327 return igb_acquire_swfw_sync_82575(hw, mask);
328}
329
330/**
733596be 331 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 332 * @hw: pointer to the HW structure
333 *
334 * A wrapper to release access rights to the correct PHY. This is a
335 * function pointer entry point called by the api module.
336 **/
337static void igb_release_phy_82575(struct e1000_hw *hw)
338{
008c3422
AD		 339 u16 mask = E1000_SWFW_PHY0_SM;
340
341 if (hw->bus.func == E1000_FUNC_1)
342 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 343 else if (hw->bus.func == E1000_FUNC_2)
344 mask = E1000_SWFW_PHY2_SM;
345 else if (hw->bus.func == E1000_FUNC_3)
346 mask = E1000_SWFW_PHY3_SM;
9d5c8243 347
9d5c8243
AK		 348 igb_release_swfw_sync_82575(hw, mask);
349}
350
351/**
733596be 352 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 353 * @hw: pointer to the HW structure
354 * @offset: register offset to be read
355 * @data: pointer to the read data
356 *
357 * Reads the PHY register at offset using the serial gigabit media independent
358 * interface and stores the retrieved information in data.
359 **/
360static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
361 u16 *data)
362{
bf6f7a92 363 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 364
365 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 366 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 367 goto out;
9d5c8243
AK		 368 }
369
bf6f7a92
AD		 370 ret_val = hw->phy.ops.acquire(hw);
371 if (ret_val)
372 goto out;
9d5c8243 373
bf6f7a92 374 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 375
bf6f7a92
AD		 376 hw->phy.ops.release(hw);
377
378out:
379 return ret_val;
9d5c8243
AK		 380}
381
382/**
733596be 383 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 384 * @hw: pointer to the HW structure
385 * @offset: register offset to write to
386 * @data: data to write at register offset
387 *
388 * Writes the data to PHY register at the offset using the serial gigabit
389 * media independent interface.
390 **/
391static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
392 u16 data)
393{
bf6f7a92
AD		 394 s32 ret_val = -E1000_ERR_PARAM;
395
9d5c8243
AK		 396
397 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 398 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 399 goto out;
9d5c8243
AK		 400 }
401
bf6f7a92
AD		 402 ret_val = hw->phy.ops.acquire(hw);
403 if (ret_val)
404 goto out;
9d5c8243 405
bf6f7a92 406 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 407
bf6f7a92
AD		 408 hw->phy.ops.release(hw);
409
410out:
411 return ret_val;
9d5c8243
AK		 412}
413
414/**
733596be 415 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 416 * @hw: pointer to the HW structure
417 *
652fff32 418 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 419 * sgmi interface.
420 **/
421static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
422{
423 struct e1000_phy_info *phy = &hw->phy;
424 s32 ret_val = 0;
425 u16 phy_id;
2fb02a26 426 u32 ctrl_ext;
4085f746 427 u32 mdic;
9d5c8243
AK		 428
429 /*
430 * For SGMII PHYs, we try the list of possible addresses until
431 * we find one that works. For non-SGMII PHYs
432 * (e.g. integrated copper PHYs), an address of 1 should
433 * work. The result of this function should mean phy->phy_addr
434 * and phy->id are set correctly.
435 */
436 if (!(igb_sgmii_active_82575(hw))) {
437 phy->addr = 1;
438 ret_val = igb_get_phy_id(hw);
439 goto out;
440 }
441
4085f746
NN		 442 if (igb_sgmii_uses_mdio_82575(hw)) {
443 switch (hw->mac.type) {
444 case e1000_82575:
445 case e1000_82576:
446 mdic = rd32(E1000_MDIC);
447 mdic &= E1000_MDIC_PHY_MASK;
448 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
449 break;
450 case e1000_82580:
451 case e1000_i350:
452 mdic = rd32(E1000_MDICNFG);
453 mdic &= E1000_MDICNFG_PHY_MASK;
454 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
455 break;
456 default:
457 ret_val = -E1000_ERR_PHY;
458 goto out;
459 break;
460 }
461 ret_val = igb_get_phy_id(hw);
462 goto out;
463 }
464
2fb02a26
AD		 465 /* Power on sgmii phy if it is disabled */
466 ctrl_ext = rd32(E1000_CTRL_EXT);
467 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
468 wrfl();
469 msleep(300);
470
9d5c8243
AK		 471 /*
472 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
473 * Therefore, we need to test 1-7
474 */
475 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
476 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
477 if (ret_val == 0) {
652fff32
AK		 478 hw_dbg("Vendor ID 0x%08X read at address %u\n",
479 phy_id, phy->addr);
9d5c8243
AK		 480 /*
481 * At the time of this writing, The M88 part is
482 * the only supported SGMII PHY product.
483 */
484 if (phy_id == M88_VENDOR)
485 break;
486 } else {
652fff32 487 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 488 }
489 }
490
491 /* A valid PHY type couldn't be found. */
492 if (phy->addr == 8) {
493 phy->addr = 0;
494 ret_val = -E1000_ERR_PHY;
495 goto out;
2fb02a26
AD		 496 } else {
497 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 498 }
499
2fb02a26
AD		 500 /* restore previous sfp cage power state */
501 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 502
503out:
504 return ret_val;
505}
506
507/**
733596be 508 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 509 * @hw: pointer to the HW structure
510 *
511 * Resets the PHY using the serial gigabit media independent interface.
512 **/
513static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
514{
515 s32 ret_val;
516
517 /*
518 * This isn't a true "hard" reset, but is the only reset
519 * available to us at this time.
520 */
521
652fff32 522 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 523
524 /*
525 * SFP documentation requires the following to configure the SPF module
526 * to work on SGMII. No further documentation is given.
527 */
a8d2a0c2 528 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 529 if (ret_val)
530 goto out;
531
532 ret_val = igb_phy_sw_reset(hw);
533
534out:
535 return ret_val;
536}
537
538/**
733596be 539 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 540 * @hw: pointer to the HW structure
541 * @active: true to enable LPLU, false to disable
542 *
543 * Sets the LPLU D0 state according to the active flag. When
544 * activating LPLU this function also disables smart speed
545 * and vice versa. LPLU will not be activated unless the
546 * device autonegotiation advertisement meets standards of
547 * either 10 or 10/100 or 10/100/1000 at all duplexes.
548 * This is a function pointer entry point only called by
549 * PHY setup routines.
550 **/
551static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
552{
553 struct e1000_phy_info *phy = &hw->phy;
554 s32 ret_val;
555 u16 data;
556
a8d2a0c2 557 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 558 if (ret_val)
559 goto out;
560
561 if (active) {
562 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 563 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 564 data);
9d5c8243
AK		 565 if (ret_val)
566 goto out;
567
568 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 569 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 570 &data);
9d5c8243 571 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 572 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 573 data);
9d5c8243
AK		 574 if (ret_val)
575 goto out;
576 } else {
577 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 578 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 579 data);
9d5c8243
AK		 580 /*
581 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
582 * during Dx states where the power conservation is most
583 * important. During driver activity we should enable
584 * SmartSpeed, so performance is maintained.
585 */
586 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 587 ret_val = phy->ops.read_reg(hw,
652fff32 588 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 589 if (ret_val)
590 goto out;
591
592 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 593 ret_val = phy->ops.write_reg(hw,
652fff32 594 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 595 if (ret_val)
596 goto out;
597 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 598 ret_val = phy->ops.read_reg(hw,
652fff32 599 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 600 if (ret_val)
601 goto out;
602
603 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 604 ret_val = phy->ops.write_reg(hw,
652fff32 605 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 606 if (ret_val)
607 goto out;
608 }
609 }
610
611out:
612 return ret_val;
613}
614
615/**
733596be 616 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 617 * @hw: pointer to the HW structure
618 *
652fff32 619 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 620 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
621 * Return successful if access grant bit set, else clear the request for
622 * EEPROM access and return -E1000_ERR_NVM (-1).
623 **/
624static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
625{
626 s32 ret_val;
627
628 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
629 if (ret_val)
630 goto out;
631
632 ret_val = igb_acquire_nvm(hw);
633
634 if (ret_val)
635 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
636
637out:
638 return ret_val;
639}
640
641/**
733596be 642 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 643 * @hw: pointer to the HW structure
644 *
645 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
646 * then release the semaphores acquired.
647 **/
648static void igb_release_nvm_82575(struct e1000_hw *hw)
649{
650 igb_release_nvm(hw);
651 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
652}
653
654/**
733596be 655 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 656 * @hw: pointer to the HW structure
657 * @mask: specifies which semaphore to acquire
658 *
659 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
660 * will also specify which port we're acquiring the lock for.
661 **/
662static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
663{
664 u32 swfw_sync;
665 u32 swmask = mask;
666 u32 fwmask = mask << 16;
667 s32 ret_val = 0;
668 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
669
670 while (i < timeout) {
671 if (igb_get_hw_semaphore(hw)) {
672 ret_val = -E1000_ERR_SWFW_SYNC;
673 goto out;
674 }
675
676 swfw_sync = rd32(E1000_SW_FW_SYNC);
677 if (!(swfw_sync & (fwmask | swmask)))
678 break;
679
680 /*
681 * Firmware currently using resource (fwmask)
682 * or other software thread using resource (swmask)
683 */
684 igb_put_hw_semaphore(hw);
685 mdelay(5);
686 i++;
687 }
688
689 if (i == timeout) {
652fff32 690 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 691 ret_val = -E1000_ERR_SWFW_SYNC;
692 goto out;
693 }
694
695 swfw_sync |= swmask;
696 wr32(E1000_SW_FW_SYNC, swfw_sync);
697
698 igb_put_hw_semaphore(hw);
699
700out:
701 return ret_val;
702}
703
704/**
733596be 705 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 706 * @hw: pointer to the HW structure
707 * @mask: specifies which semaphore to acquire
708 *
709 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
710 * will also specify which port we're releasing the lock for.
711 **/
712static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
713{
714 u32 swfw_sync;
715
716 while (igb_get_hw_semaphore(hw) != 0);
717 /* Empty */
718
719 swfw_sync = rd32(E1000_SW_FW_SYNC);
720 swfw_sync &= ~mask;
721 wr32(E1000_SW_FW_SYNC, swfw_sync);
722
723 igb_put_hw_semaphore(hw);
724}
725
726/**
733596be 727 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 728 * @hw: pointer to the HW structure
729 *
730 * Read the management control register for the config done bit for
731 * completion status. NOTE: silicon which is EEPROM-less will fail trying
732 * to read the config done bit, so an error is *ONLY* logged and returns
733 * 0. If we were to return with error, EEPROM-less silicon
734 * would not be able to be reset or change link.
735 **/
736static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
737{
738 s32 timeout = PHY_CFG_TIMEOUT;
739 s32 ret_val = 0;
740 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
741
742 if (hw->bus.func == 1)
743 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 744 else if (hw->bus.func == E1000_FUNC_2)
745 mask = E1000_NVM_CFG_DONE_PORT_2;
746 else if (hw->bus.func == E1000_FUNC_3)
747 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 748
749 while (timeout) {
750 if (rd32(E1000_EEMNGCTL) & mask)
751 break;
752 msleep(1);
753 timeout--;
754 }
755 if (!timeout)
652fff32 756 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 757
758 /* If EEPROM is not marked present, init the PHY manually */
759 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
760 (hw->phy.type == e1000_phy_igp_3))
761 igb_phy_init_script_igp3(hw);
762
763 return ret_val;
764}
765
766/**
733596be 767 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 768 * @hw: pointer to the HW structure
769 *
770 * If sgmii is enabled, then use the pcs register to determine link, otherwise
771 * use the generic interface for determining link.
772 **/
773static s32 igb_check_for_link_82575(struct e1000_hw *hw)
774{
775 s32 ret_val;
776 u16 speed, duplex;
777
70d92f86 778 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 779 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 780 &duplex);
5d0932a5
AD		 781 /*
782 * Use this flag to determine if link needs to be checked or
783 * not. If we have link clear the flag so that we do not
784 * continue to check for link.
785 */
786 hw->mac.get_link_status = !hw->mac.serdes_has_link;
787 } else {
9d5c8243 788 ret_val = igb_check_for_copper_link(hw);
5d0932a5 789 }
9d5c8243
AK		 790
791 return ret_val;
792}
70d92f86 793
88a268c1
NN		 794/**
795 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
796 * @hw: pointer to the HW structure
797 **/
798void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
799{
800 u32 reg;
801
802
803 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
804 !igb_sgmii_active_82575(hw))
805 return;
806
807 /* Enable PCS to turn on link */
808 reg = rd32(E1000_PCS_CFG0);
809 reg |= E1000_PCS_CFG_PCS_EN;
810 wr32(E1000_PCS_CFG0, reg);
811
812 /* Power up the laser */
813 reg = rd32(E1000_CTRL_EXT);
814 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
815 wr32(E1000_CTRL_EXT, reg);
816
817 /* flush the write to verify completion */
818 wrfl();
819 msleep(1);
820}
821
9d5c8243 822/**
733596be 823 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 824 * @hw: pointer to the HW structure
825 * @speed: stores the current speed
826 * @duplex: stores the current duplex
827 *
652fff32 828 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 829 * duplex, then store the values in the pointers provided.
830 **/
831static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
832 u16 *duplex)
833{
834 struct e1000_mac_info *mac = &hw->mac;
835 u32 pcs;
836
837 /* Set up defaults for the return values of this function */
838 mac->serdes_has_link = false;
839 *speed = 0;
840 *duplex = 0;
841
842 /*
843 * Read the PCS Status register for link state. For non-copper mode,
844 * the status register is not accurate. The PCS status register is
845 * used instead.
846 */
847 pcs = rd32(E1000_PCS_LSTAT);
848
849 /*
850 * The link up bit determines when link is up on autoneg. The sync ok
851 * gets set once both sides sync up and agree upon link. Stable link
852 * can be determined by checking for both link up and link sync ok
853 */
854 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
855 mac->serdes_has_link = true;
856
857 /* Detect and store PCS speed */
858 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
859 *speed = SPEED_1000;
860 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
861 *speed = SPEED_100;
862 } else {
863 *speed = SPEED_10;
864 }
865
866 /* Detect and store PCS duplex */
867 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
868 *duplex = FULL_DUPLEX;
869 } else {
870 *duplex = HALF_DUPLEX;
871 }
872 }
873
874 return 0;
875}
876
2d064c06 877/**
2fb02a26 878 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 879 * @hw: pointer to the HW structure
9d5c8243 880 *
2d064c06
AD		 881 * In the case of fiber serdes, shut down optics and PCS on driver unload
882 * when management pass thru is not enabled.
9d5c8243 883 **/
2fb02a26 884void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 885{
2d064c06
AD		 886 u32 reg;
887
53c992fa 888 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 889 igb_sgmii_active_82575(hw))
2d064c06
AD		 890 return;
891
53c992fa 892 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 893 /* Disable PCS to turn off link */
894 reg = rd32(E1000_PCS_CFG0);
895 reg &= ~E1000_PCS_CFG_PCS_EN;
896 wr32(E1000_PCS_CFG0, reg);
897
898 /* shutdown the laser */
899 reg = rd32(E1000_CTRL_EXT);
2fb02a26 900 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 901 wr32(E1000_CTRL_EXT, reg);
902
903 /* flush the write to verify completion */
904 wrfl();
905 msleep(1);
906 }
9d5c8243
AK		 907}
908
909/**
733596be 910 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 911 * @hw: pointer to the HW structure
912 *
913 * This resets the hardware into a known state. This is a
914 * function pointer entry point called by the api module.
915 **/
916static s32 igb_reset_hw_82575(struct e1000_hw *hw)
917{
918 u32 ctrl, icr;
919 s32 ret_val;
920
921 /*
922 * Prevent the PCI-E bus from sticking if there is no TLP connection
923 * on the last TLP read/write transaction when MAC is reset.
924 */
925 ret_val = igb_disable_pcie_master(hw);
926 if (ret_val)
652fff32 927 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 928
009bc06e
AD		 929 /* set the completion timeout for interface */
930 ret_val = igb_set_pcie_completion_timeout(hw);
931 if (ret_val) {
932 hw_dbg("PCI-E Set completion timeout has failed.\n");
933 }
934
652fff32 935 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 936 wr32(E1000_IMC, 0xffffffff);
937
938 wr32(E1000_RCTL, 0);
939 wr32(E1000_TCTL, E1000_TCTL_PSP);
940 wrfl();
941
942 msleep(10);
943
944 ctrl = rd32(E1000_CTRL);
945
652fff32 946 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 947 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
948
949 ret_val = igb_get_auto_rd_done(hw);
950 if (ret_val) {
951 /*
952 * When auto config read does not complete, do not
953 * return with an error. This can happen in situations
954 * where there is no eeprom and prevents getting link.
955 */
652fff32 956 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 957 }
958
959 /* If EEPROM is not present, run manual init scripts */
960 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
961 igb_reset_init_script_82575(hw);
962
963 /* Clear any pending interrupt events. */
964 wr32(E1000_IMC, 0xffffffff);
965 icr = rd32(E1000_ICR);
966
5ac16659
AD		 967 /* Install any alternate MAC address into RAR0 */
968 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 969
970 return ret_val;
971}
972
973/**
733596be 974 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 975 * @hw: pointer to the HW structure
976 *
977 * This inits the hardware readying it for operation.
978 **/
979static s32 igb_init_hw_82575(struct e1000_hw *hw)
980{
981 struct e1000_mac_info *mac = &hw->mac;
982 s32 ret_val;
983 u16 i, rar_count = mac->rar_entry_count;
984
985 /* Initialize identification LED */
986 ret_val = igb_id_led_init(hw);
987 if (ret_val) {
652fff32 988 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 989 /* This is not fatal and we should not stop init due to this */
990 }
991
992 /* Disabling VLAN filtering */
652fff32 993 hw_dbg("Initializing the IEEE VLAN\n");
9d5c8243
AK		 994 igb_clear_vfta(hw);
995
996 /* Setup the receive address */
5ac16659
AD		 997 igb_init_rx_addrs(hw, rar_count);
998
9d5c8243 999 /* Zero out the Multicast HASH table */
652fff32 1000 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1001 for (i = 0; i < mac->mta_reg_count; i++)
1002 array_wr32(E1000_MTA, i, 0);
1003
68d480c4
AD		 1004 /* Zero out the Unicast HASH table */
1005 hw_dbg("Zeroing the UTA\n");
1006 for (i = 0; i < mac->uta_reg_count; i++)
1007 array_wr32(E1000_UTA, i, 0);
1008
9d5c8243
AK		 1009 /* Setup link and flow control */
1010 ret_val = igb_setup_link(hw);
1011
1012 /*
1013 * Clear all of the statistics registers (clear on read). It is
1014 * important that we do this after we have tried to establish link
1015 * because the symbol error count will increment wildly if there
1016 * is no link.
1017 */
1018 igb_clear_hw_cntrs_82575(hw);
1019
1020 return ret_val;
1021}
1022
1023/**
733596be 1024 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1025 * @hw: pointer to the HW structure
1026 *
1027 * Configures the link for auto-neg or forced speed and duplex. Then we check
1028 * for link, once link is established calls to configure collision distance
1029 * and flow control are called.
1030 **/
1031static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1032{
12645a19 1033 u32 ctrl;
9d5c8243 1034 s32 ret_val;
9d5c8243
AK		 1035
1036 ctrl = rd32(E1000_CTRL);
1037 ctrl |= E1000_CTRL_SLU;
1038 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1039 wr32(E1000_CTRL, ctrl);
1040
2fb02a26
AD		 1041 ret_val = igb_setup_serdes_link_82575(hw);
1042 if (ret_val)
1043 goto out;
1044
1045 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1046 /* allow time for SFP cage time to power up phy */
1047 msleep(300);
1048
2fb02a26
AD		 1049 ret_val = hw->phy.ops.reset(hw);
1050 if (ret_val) {
1051 hw_dbg("Error resetting the PHY.\n");
1052 goto out;
1053 }
1054 }
9d5c8243
AK		 1055 switch (hw->phy.type) {
1056 case e1000_phy_m88:
1057 ret_val = igb_copper_link_setup_m88(hw);
1058 break;
1059 case e1000_phy_igp_3:
1060 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1061 break;
bb2ac47b
AD		 1062 case e1000_phy_82580:
1063 ret_val = igb_copper_link_setup_82580(hw);
1064 break;
9d5c8243
AK		 1065 default:
1066 ret_val = -E1000_ERR_PHY;
1067 break;
1068 }
1069
1070 if (ret_val)
1071 goto out;
1072
81fadd81 1073 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1074out:
1075 return ret_val;
1076}
1077
1078/**
70d92f86 1079 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1080 * @hw: pointer to the HW structure
1081 *
70d92f86
AD		 1082 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1083 * used on copper connections where the serialized gigabit media independent
1084 * interface (sgmii), or serdes fiber is being used. Configures the link
1085 * for auto-negotiation or forces speed/duplex.
9d5c8243 1086 **/
2fb02a26 1087static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1088{
bb2ac47b
AD		 1089 u32 ctrl_ext, ctrl_reg, reg;
1090 bool pcs_autoneg;
2fb02a26
AD		 1091
1092 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1093 !igb_sgmii_active_82575(hw))
1094 return 0;
9d5c8243
AK		 1095
1096 /*
1097 * On the 82575, SerDes loopback mode persists until it is
1098 * explicitly turned off or a power cycle is performed. A read to
1099 * the register does not indicate its status. Therefore, we ensure
1100 * loopback mode is disabled during initialization.
1101 */
1102 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1103
2fb02a26 1104 /* power on the sfp cage if present */
bb2ac47b
AD		 1105 ctrl_ext = rd32(E1000_CTRL_EXT);
1106 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1107 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1108
1109 ctrl_reg = rd32(E1000_CTRL);
1110 ctrl_reg |= E1000_CTRL_SLU;
1111
1112 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1113 /* set both sw defined pins */
1114 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1115
1116 /* Set switch control to serdes energy detect */
1117 reg = rd32(E1000_CONNSW);
1118 reg |= E1000_CONNSW_ENRGSRC;
1119 wr32(E1000_CONNSW, reg);
1120 }
1121
1122 reg = rd32(E1000_PCS_LCTL);
1123
bb2ac47b
AD		 1124 /* default pcs_autoneg to the same setting as mac autoneg */
1125 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1126
bb2ac47b
AD		 1127 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1128 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1129 /* sgmii mode lets the phy handle forcing speed/duplex */
1130 pcs_autoneg = true;
1131 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1132 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1133 break;
1134 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1135 /* disable PCS autoneg and support parallel detect only */
1136 pcs_autoneg = false;
1137 default:
1138 /*
1139 * non-SGMII modes only supports a speed of 1000/Full for the
1140 * link so it is best to just force the MAC and let the pcs
1141 * link either autoneg or be forced to 1000/Full
1142 */
2fb02a26
AD		 1143 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1144 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1145
1146 /* set speed of 1000/Full if speed/duplex is forced */
1147 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1148 break;
921aa749
AD		 1149 }
1150
2fb02a26 1151 wr32(E1000_CTRL, ctrl_reg);
9d5c8243
AK		 1152
1153 /*
1154 * New SerDes mode allows for forcing speed or autonegotiating speed
1155 * at 1gb. Autoneg should be default set by most drivers. This is the
1156 * mode that will be compatible with older link partners and switches.
1157 * However, both are supported by the hardware and some drivers/tools.
1158 */
9d5c8243
AK		 1159 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1160 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1161
2fb02a26
AD		 1162 /*
1163 * We force flow control to prevent the CTRL register values from being
1164 * overwritten by the autonegotiated flow control values
1165 */
1166 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1167
bb2ac47b 1168 if (pcs_autoneg) {
9d5c8243 1169 /* Set PCS register for autoneg */
bb2ac47b 1170 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1171 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
bb2ac47b 1172 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1173 } else {
bb2ac47b 1174 /* Set PCS register for forced link */
d68caec6 1175 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b
AD		 1176
1177 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1178 }
726c09e7 1179
9d5c8243
AK		 1180 wr32(E1000_PCS_LCTL, reg);
1181
2fb02a26
AD		 1182 if (!igb_sgmii_active_82575(hw))
1183 igb_force_mac_fc(hw);
9d5c8243 1184
2fb02a26 1185 return 0;
9d5c8243
AK		 1186}
1187
1188/**
733596be 1189 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1190 * @hw: pointer to the HW structure
1191 *
1192 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1193 * which can be enabled for use in the embedded applications. Simply
1194 * return the current state of the sgmii interface.
1195 **/
1196static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1197{
c1889bfe 1198 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1199 return dev_spec->sgmii_active;
9d5c8243
AK		 1200}
1201
1202/**
733596be 1203 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1204 * @hw: pointer to the HW structure
1205 *
1206 * Inits recommended HW defaults after a reset when there is no EEPROM
1207 * detected. This is only for the 82575.
1208 **/
1209static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1210{
1211 if (hw->mac.type == e1000_82575) {
652fff32 1212 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1213 /* SerDes configuration via SERDESCTRL */
1214 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1215 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1216 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1217 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1218
1219 /* CCM configuration via CCMCTL register */
1220 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1221 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1222
1223 /* PCIe lanes configuration */
1224 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1225 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1226 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1227 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1228
1229 /* PCIe PLL Configuration */
1230 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1231 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1232 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1233 }
1234
1235 return 0;
1236}
1237
1238/**
733596be 1239 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1240 * @hw: pointer to the HW structure
1241 **/
1242static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1243{
1244 s32 ret_val = 0;
1245
22896639
AD		 1246 /*
1247 * If there's an alternate MAC address place it in RAR0
1248 * so that it will override the Si installed default perm
1249 * address.
1250 */
1251 ret_val = igb_check_alt_mac_addr(hw);
1252 if (ret_val)
1253 goto out;
1254
1255 ret_val = igb_read_mac_addr(hw);
9d5c8243 1256
22896639 1257out:
9d5c8243
AK		 1258 return ret_val;
1259}
1260
88a268c1
NN		 1261/**
1262 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1263 * @hw: pointer to the HW structure
1264 *
1265 * In the case of a PHY power down to save power, or to turn off link during a
1266 * driver unload, or wake on lan is not enabled, remove the link.
1267 **/
1268void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1269{
1270 /* If the management interface is not enabled, then power down */
1271 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1272 igb_power_down_phy_copper(hw);
88a268c1
NN		 1273}
1274
9d5c8243 1275/**
733596be 1276 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1277 * @hw: pointer to the HW structure
1278 *
1279 * Clears the hardware counters by reading the counter registers.
1280 **/
1281static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1282{
9d5c8243
AK		 1283 igb_clear_hw_cntrs_base(hw);
1284
cc9073bb
AD		 1285 rd32(E1000_PRC64);
1286 rd32(E1000_PRC127);
1287 rd32(E1000_PRC255);
1288 rd32(E1000_PRC511);
1289 rd32(E1000_PRC1023);
1290 rd32(E1000_PRC1522);
1291 rd32(E1000_PTC64);
1292 rd32(E1000_PTC127);
1293 rd32(E1000_PTC255);
1294 rd32(E1000_PTC511);
1295 rd32(E1000_PTC1023);
1296 rd32(E1000_PTC1522);
1297
1298 rd32(E1000_ALGNERRC);
1299 rd32(E1000_RXERRC);
1300 rd32(E1000_TNCRS);
1301 rd32(E1000_CEXTERR);
1302 rd32(E1000_TSCTC);
1303 rd32(E1000_TSCTFC);
1304
1305 rd32(E1000_MGTPRC);
1306 rd32(E1000_MGTPDC);
1307 rd32(E1000_MGTPTC);
1308
1309 rd32(E1000_IAC);
1310 rd32(E1000_ICRXOC);
1311
1312 rd32(E1000_ICRXPTC);
1313 rd32(E1000_ICRXATC);
1314 rd32(E1000_ICTXPTC);
1315 rd32(E1000_ICTXATC);
1316 rd32(E1000_ICTXQEC);
1317 rd32(E1000_ICTXQMTC);
1318 rd32(E1000_ICRXDMTC);
1319
1320 rd32(E1000_CBTMPC);
1321 rd32(E1000_HTDPMC);
1322 rd32(E1000_CBRMPC);
1323 rd32(E1000_RPTHC);
1324 rd32(E1000_HGPTC);
1325 rd32(E1000_HTCBDPC);
1326 rd32(E1000_HGORCL);
1327 rd32(E1000_HGORCH);
1328 rd32(E1000_HGOTCL);
1329 rd32(E1000_HGOTCH);
1330 rd32(E1000_LENERRS);
9d5c8243
AK		 1331
1332 /* This register should not be read in copper configurations */
2fb02a26
AD		 1333 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1334 igb_sgmii_active_82575(hw))
cc9073bb 1335 rd32(E1000_SCVPC);
9d5c8243
AK		 1336}
1337
662d7205
AD		 1338/**
1339 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1340 * @hw: pointer to the HW structure
1341 *
1342 * After rx enable if managability is enabled then there is likely some
1343 * bad data at the start of the fifo and possibly in the DMA fifo. This
1344 * function clears the fifos and flushes any packets that came in as rx was
1345 * being enabled.
1346 **/
1347void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1348{
1349 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1350 int i, ms_wait;
1351
1352 if (hw->mac.type != e1000_82575 ||
1353 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1354 return;
1355
1356 /* Disable all RX queues */
1357 for (i = 0; i < 4; i++) {
1358 rxdctl[i] = rd32(E1000_RXDCTL(i));
1359 wr32(E1000_RXDCTL(i),
1360 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1361 }
1362 /* Poll all queues to verify they have shut down */
1363 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1364 msleep(1);
1365 rx_enabled = 0;
1366 for (i = 0; i < 4; i++)
1367 rx_enabled |= rd32(E1000_RXDCTL(i));
1368 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1369 break;
1370 }
1371
1372 if (ms_wait == 10)
1373 hw_dbg("Queue disable timed out after 10ms\n");
1374
1375 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1376 * incoming packets are rejected. Set enable and wait 2ms so that
1377 * any packet that was coming in as RCTL.EN was set is flushed
1378 */
1379 rfctl = rd32(E1000_RFCTL);
1380 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1381
1382 rlpml = rd32(E1000_RLPML);
1383 wr32(E1000_RLPML, 0);
1384
1385 rctl = rd32(E1000_RCTL);
1386 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1387 temp_rctl |= E1000_RCTL_LPE;
1388
1389 wr32(E1000_RCTL, temp_rctl);
1390 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1391 wrfl();
1392 msleep(2);
1393
1394 /* Enable RX queues that were previously enabled and restore our
1395 * previous state
1396 */
1397 for (i = 0; i < 4; i++)
1398 wr32(E1000_RXDCTL(i), rxdctl[i]);
1399 wr32(E1000_RCTL, rctl);
1400 wrfl();
1401
1402 wr32(E1000_RLPML, rlpml);
1403 wr32(E1000_RFCTL, rfctl);
1404
1405 /* Flush receive errors generated by workaround */
1406 rd32(E1000_ROC);
1407 rd32(E1000_RNBC);
1408 rd32(E1000_MPC);
1409}
1410
009bc06e
AD		 1411/**
1412 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1413 * @hw: pointer to the HW structure
1414 *
1415 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1416 * however the hardware default for these parts is 500us to 1ms which is less
1417 * than the 10ms recommended by the pci-e spec. To address this we need to
1418 * increase the value to either 10ms to 200ms for capability version 1 config,
1419 * or 16ms to 55ms for version 2.
1420 **/
1421static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1422{
1423 u32 gcr = rd32(E1000_GCR);
1424 s32 ret_val = 0;
1425 u16 pcie_devctl2;
1426
1427 /* only take action if timeout value is defaulted to 0 */
1428 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1429 goto out;
1430
1431 /*
1432 * if capababilities version is type 1 we can write the
1433 * timeout of 10ms to 200ms through the GCR register
1434 */
1435 if (!(gcr & E1000_GCR_CAP_VER2)) {
1436 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1437 goto out;
1438 }
1439
1440 /*
1441 * for version 2 capabilities we need to write the config space
1442 * directly in order to set the completion timeout value for
1443 * 16ms to 55ms
1444 */
1445 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1446 &pcie_devctl2);
1447 if (ret_val)
1448 goto out;
1449
1450 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1451
1452 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1453 &pcie_devctl2);
1454out:
1455 /* disable completion timeout resend */
1456 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1457
1458 wr32(E1000_GCR, gcr);
1459 return ret_val;
1460}
1461
4ae196df
AD		 1462/**
1463 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1464 * @hw: pointer to the hardware struct
1465 * @enable: state to enter, either enabled or disabled
1466 *
1467 * enables/disables L2 switch loopback functionality.
1468 **/
1469void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1470{
1471 u32 dtxswc = rd32(E1000_DTXSWC);
1472
1473 if (enable)
1474 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1475 else
1476 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1477
1478 wr32(E1000_DTXSWC, dtxswc);
1479}
1480
1481/**
1482 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1483 * @hw: pointer to the hardware struct
1484 * @enable: state to enter, either enabled or disabled
1485 *
1486 * enables/disables replication of packets across multiple pools.
1487 **/
1488void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1489{
1490 u32 vt_ctl = rd32(E1000_VT_CTL);
1491
1492 if (enable)
1493 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1494 else
1495 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1496
1497 wr32(E1000_VT_CTL, vt_ctl);
1498}
1499
bb2ac47b
AD		 1500/**
1501 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1502 * @hw: pointer to the HW structure
1503 * @offset: register offset to be read
1504 * @data: pointer to the read data
1505 *
1506 * Reads the MDI control register in the PHY at offset and stores the
1507 * information read to data.
1508 **/
1509static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1510{
bb2ac47b
AD		 1511 s32 ret_val;
1512
1513
1514 ret_val = hw->phy.ops.acquire(hw);
1515 if (ret_val)
1516 goto out;
1517
bb2ac47b
AD		 1518 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1519
1520 hw->phy.ops.release(hw);
1521
1522out:
1523 return ret_val;
1524}
1525
1526/**
1527 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1528 * @hw: pointer to the HW structure
1529 * @offset: register offset to write to
1530 * @data: data to write to register at offset
1531 *
1532 * Writes data to MDI control register in the PHY at offset.
1533 **/
1534static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1535{
bb2ac47b
AD		 1536 s32 ret_val;
1537
1538
1539 ret_val = hw->phy.ops.acquire(hw);
1540 if (ret_val)
1541 goto out;
1542
bb2ac47b
AD		 1543 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1544
1545 hw->phy.ops.release(hw);
1546
1547out:
1548 return ret_val;
1549}
1550
1551/**
1552 * igb_reset_hw_82580 - Reset hardware
1553 * @hw: pointer to the HW structure
1554 *
1555 * This resets function or entire device (all ports, etc.)
1556 * to a known state.
1557 **/
1558static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1559{
1560 s32 ret_val = 0;
1561 /* BH SW mailbox bit in SW_FW_SYNC */
1562 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1563 u32 ctrl, icr;
1564 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1565
1566
1567 hw->dev_spec._82575.global_device_reset = false;
1568
1569 /* Get current control state. */
1570 ctrl = rd32(E1000_CTRL);
1571
1572 /*
1573 * Prevent the PCI-E bus from sticking if there is no TLP connection
1574 * on the last TLP read/write transaction when MAC is reset.
1575 */
1576 ret_val = igb_disable_pcie_master(hw);
1577 if (ret_val)
1578 hw_dbg("PCI-E Master disable polling has failed.\n");
1579
1580 hw_dbg("Masking off all interrupts\n");
1581 wr32(E1000_IMC, 0xffffffff);
1582 wr32(E1000_RCTL, 0);
1583 wr32(E1000_TCTL, E1000_TCTL_PSP);
1584 wrfl();
1585
1586 msleep(10);
1587
1588 /* Determine whether or not a global dev reset is requested */
1589 if (global_device_reset &&
1590 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1591 global_device_reset = false;
1592
1593 if (global_device_reset &&
1594 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1595 ctrl |= E1000_CTRL_DEV_RST;
1596 else
1597 ctrl |= E1000_CTRL_RST;
1598
1599 wr32(E1000_CTRL, ctrl);
1600
1601 /* Add delay to insure DEV_RST has time to complete */
1602 if (global_device_reset)
1603 msleep(5);
1604
1605 ret_val = igb_get_auto_rd_done(hw);
1606 if (ret_val) {
1607 /*
1608 * When auto config read does not complete, do not
1609 * return with an error. This can happen in situations
1610 * where there is no eeprom and prevents getting link.
1611 */
1612 hw_dbg("Auto Read Done did not complete\n");
1613 }
1614
1615 /* If EEPROM is not present, run manual init scripts */
1616 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1617 igb_reset_init_script_82575(hw);
1618
1619 /* clear global device reset status bit */
1620 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1621
1622 /* Clear any pending interrupt events. */
1623 wr32(E1000_IMC, 0xffffffff);
1624 icr = rd32(E1000_ICR);
1625
1626 /* Install any alternate MAC address into RAR0 */
1627 ret_val = igb_check_alt_mac_addr(hw);
1628
1629 /* Release semaphore */
1630 if (global_device_reset)
1631 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1632
1633 return ret_val;
1634}
1635
1636/**
1637 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1638 * @data: data received by reading RXPBS register
1639 *
1640 * The 82580 uses a table based approach for packet buffer allocation sizes.
1641 * This function converts the retrieved value into the correct table value
1642 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1643 * 0x0 36 72 144 1 2 4 8 16
1644 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1645 */
1646u16 igb_rxpbs_adjust_82580(u32 data)
1647{
1648 u16 ret_val = 0;
1649
1650 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1651 ret_val = e1000_82580_rxpbs_table[data];
1652
1653 return ret_val;
1654}
1655
9d5c8243 1656static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 1657 .init_hw = igb_init_hw_82575,
1658 .check_for_link = igb_check_for_link_82575,
2d064c06 1659 .rar_set = igb_rar_set,
9d5c8243
AK		 1660 .read_mac_addr = igb_read_mac_addr_82575,
1661 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1662};
1663
1664static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 1665 .acquire = igb_acquire_phy_82575,
9d5c8243 1666 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 1667 .release = igb_release_phy_82575,
9d5c8243
AK		 1668};
1669
1670static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 1671 .acquire = igb_acquire_nvm_82575,
1672 .read = igb_read_nvm_eerd,
1673 .release = igb_release_nvm_82575,
1674 .write = igb_write_nvm_spi,
9d5c8243
AK		 1675};
1676
1677const struct e1000_info e1000_82575_info = {
1678 .get_invariants = igb_get_invariants_82575,
1679 .mac_ops = &e1000_mac_ops_82575,
1680 .phy_ops = &e1000_phy_ops_82575,
1681 .nvm_ops = &e1000_nvm_ops_82575,
1682};
1683
Linux kernel - Deliverables
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