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ixgbe: fix unmap length bug
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
33#include <linux/slab.h>
2d064c06 34#include <linux/if_ether.h>
9d5c8243
AK		 35
36#include "e1000_mac.h"
37#include "e1000_82575.h"
38
39static s32 igb_get_invariants_82575(struct e1000_hw *);
40static s32 igb_acquire_phy_82575(struct e1000_hw *);
41static void igb_release_phy_82575(struct e1000_hw *);
42static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43static void igb_release_nvm_82575(struct e1000_hw *);
44static s32 igb_check_for_link_82575(struct e1000_hw *);
45static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46static s32 igb_init_hw_82575(struct e1000_hw *);
47static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
9d5c8243
AK		 49static s32 igb_reset_hw_82575(struct e1000_hw *);
50static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51static s32 igb_setup_copper_link_82575(struct e1000_hw *);
52static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
53static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56static s32 igb_configure_pcs_link_82575(struct e1000_hw *);
57static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
58 u16 *);
59static s32 igb_get_phy_id_82575(struct e1000_hw *);
60static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
61static bool igb_sgmii_active_82575(struct e1000_hw *);
62static s32 igb_reset_init_script_82575(struct e1000_hw *);
63static s32 igb_read_mac_addr_82575(struct e1000_hw *);
64
9d5c8243
AK		 65static s32 igb_get_invariants_82575(struct e1000_hw *hw)
66{
67 struct e1000_phy_info *phy = &hw->phy;
68 struct e1000_nvm_info *nvm = &hw->nvm;
69 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 70 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243
AK		 71 u32 eecd;
72 s32 ret_val;
73 u16 size;
74 u32 ctrl_ext = 0;
75
76 switch (hw->device_id) {
77 case E1000_DEV_ID_82575EB_COPPER:
78 case E1000_DEV_ID_82575EB_FIBER_SERDES:
79 case E1000_DEV_ID_82575GB_QUAD_COPPER:
80 mac->type = e1000_82575;
81 break;
2d064c06 82 case E1000_DEV_ID_82576:
9eb2341d 83 case E1000_DEV_ID_82576_NS:
2d064c06
AD		 84 case E1000_DEV_ID_82576_FIBER:
85 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 86 case E1000_DEV_ID_82576_QUAD_COPPER:
2d064c06
AD		 87 mac->type = e1000_82576;
88 break;
9d5c8243
AK		 89 default:
90 return -E1000_ERR_MAC_INIT;
91 break;
92 }
93
9d5c8243
AK		 94 /* Set media type */
95 /*
96 * The 82575 uses bits 22:23 for link mode. The mode can be changed
97 * based on the EEPROM. We cannot rely upon device ID. There
98 * is no distinguishable difference between fiber and internal
99 * SerDes mode on the 82575. There can be an external PHY attached
100 * on the SGMII interface. For this, we'll set sgmii_active to true.
101 */
102 phy->media_type = e1000_media_type_copper;
103 dev_spec->sgmii_active = false;
104
105 ctrl_ext = rd32(E1000_CTRL_EXT);
106 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
107 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
108 hw->phy.media_type = e1000_media_type_internal_serdes;
109 ctrl_ext |= E1000_CTRL_I2C_ENA;
110 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
111 dev_spec->sgmii_active = true;
112 ctrl_ext |= E1000_CTRL_I2C_ENA;
113 } else {
114 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
115 }
116 wr32(E1000_CTRL_EXT, ctrl_ext);
117
118 /* Set mta register count */
119 mac->mta_reg_count = 128;
120 /* Set rar entry count */
121 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
2d064c06
AD		 122 if (mac->type == e1000_82576)
123 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
9d5c8243
AK		 124 /* Set if part includes ASF firmware */
125 mac->asf_firmware_present = true;
126 /* Set if manageability features are enabled. */
127 mac->arc_subsystem_valid =
128 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
129 ? true : false;
130
131 /* physical interface link setup */
132 mac->ops.setup_physical_interface =
133 (hw->phy.media_type == e1000_media_type_copper)
134 ? igb_setup_copper_link_82575
135 : igb_setup_fiber_serdes_link_82575;
136
137 /* NVM initialization */
138 eecd = rd32(E1000_EECD);
139
140 nvm->opcode_bits = 8;
141 nvm->delay_usec = 1;
142 switch (nvm->override) {
143 case e1000_nvm_override_spi_large:
144 nvm->page_size = 32;
145 nvm->address_bits = 16;
146 break;
147 case e1000_nvm_override_spi_small:
148 nvm->page_size = 8;
149 nvm->address_bits = 8;
150 break;
151 default:
152 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
153 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
154 break;
155 }
156
157 nvm->type = e1000_nvm_eeprom_spi;
158
159 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
160 E1000_EECD_SIZE_EX_SHIFT);
161
162 /*
163 * Added to a constant, "size" becomes the left-shift value
164 * for setting word_size.
165 */
166 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75
JK		 167
168 /* EEPROM access above 16k is unsupported */
169 if (size > 14)
170 size = 14;
9d5c8243
AK		 171 nvm->word_size = 1 << size;
172
173 /* setup PHY parameters */
174 if (phy->media_type != e1000_media_type_copper) {
175 phy->type = e1000_phy_none;
176 return 0;
177 }
178
179 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
180 phy->reset_delay_us = 100;
181
182 /* PHY function pointers */
183 if (igb_sgmii_active_82575(hw)) {
a8d2a0c2
AD		 184 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
185 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
186 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
9d5c8243 187 } else {
a8d2a0c2
AD		 188 phy->ops.reset = igb_phy_hw_reset;
189 phy->ops.read_reg = igb_read_phy_reg_igp;
190 phy->ops.write_reg = igb_write_phy_reg_igp;
9d5c8243
AK		 191 }
192
193 /* Set phy->phy_addr and phy->id. */
194 ret_val = igb_get_phy_id_82575(hw);
195 if (ret_val)
196 return ret_val;
197
198 /* Verify phy id and set remaining function pointers */
199 switch (phy->id) {
200 case M88E1111_I_PHY_ID:
201 phy->type = e1000_phy_m88;
202 phy->ops.get_phy_info = igb_get_phy_info_m88;
203 phy->ops.get_cable_length = igb_get_cable_length_m88;
204 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
205 break;
206 case IGP03E1000_E_PHY_ID:
207 phy->type = e1000_phy_igp_3;
208 phy->ops.get_phy_info = igb_get_phy_info_igp;
209 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
210 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
211 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
212 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
213 break;
214 default:
215 return -E1000_ERR_PHY;
216 }
217
4ae196df
AD		 218 /* if 82576 then initialize mailbox parameters */
219 if (mac->type == e1000_82576)
220 igb_init_mbx_params_pf(hw);
221
9d5c8243
AK		 222 return 0;
223}
224
225/**
733596be 226 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 227 * @hw: pointer to the HW structure
228 *
229 * Acquire access rights to the correct PHY. This is a
230 * function pointer entry point called by the api module.
231 **/
232static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
233{
234 u16 mask;
235
236 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
237
238 return igb_acquire_swfw_sync_82575(hw, mask);
239}
240
241/**
733596be 242 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 243 * @hw: pointer to the HW structure
244 *
245 * A wrapper to release access rights to the correct PHY. This is a
246 * function pointer entry point called by the api module.
247 **/
248static void igb_release_phy_82575(struct e1000_hw *hw)
249{
250 u16 mask;
251
252 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
253 igb_release_swfw_sync_82575(hw, mask);
254}
255
256/**
733596be 257 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 258 * @hw: pointer to the HW structure
259 * @offset: register offset to be read
260 * @data: pointer to the read data
261 *
262 * Reads the PHY register at offset using the serial gigabit media independent
263 * interface and stores the retrieved information in data.
264 **/
265static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
266 u16 *data)
267{
268 struct e1000_phy_info *phy = &hw->phy;
269 u32 i, i2ccmd = 0;
270
271 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 272 hw_dbg("PHY Address %u is out of range\n", offset);
9d5c8243
AK		 273 return -E1000_ERR_PARAM;
274 }
275
276 /*
277 * Set up Op-code, Phy Address, and register address in the I2CCMD
278 * register. The MAC will take care of interfacing with the
279 * PHY to retrieve the desired data.
280 */
281 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
282 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
283 (E1000_I2CCMD_OPCODE_READ));
284
285 wr32(E1000_I2CCMD, i2ccmd);
286
287 /* Poll the ready bit to see if the I2C read completed */
288 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
289 udelay(50);
290 i2ccmd = rd32(E1000_I2CCMD);
291 if (i2ccmd & E1000_I2CCMD_READY)
292 break;
293 }
294 if (!(i2ccmd & E1000_I2CCMD_READY)) {
652fff32 295 hw_dbg("I2CCMD Read did not complete\n");
9d5c8243
AK		 296 return -E1000_ERR_PHY;
297 }
298 if (i2ccmd & E1000_I2CCMD_ERROR) {
652fff32 299 hw_dbg("I2CCMD Error bit set\n");
9d5c8243
AK		 300 return -E1000_ERR_PHY;
301 }
302
303 /* Need to byte-swap the 16-bit value. */
304 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
305
306 return 0;
307}
308
309/**
733596be 310 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 311 * @hw: pointer to the HW structure
312 * @offset: register offset to write to
313 * @data: data to write at register offset
314 *
315 * Writes the data to PHY register at the offset using the serial gigabit
316 * media independent interface.
317 **/
318static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
319 u16 data)
320{
321 struct e1000_phy_info *phy = &hw->phy;
322 u32 i, i2ccmd = 0;
323 u16 phy_data_swapped;
324
325 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 326 hw_dbg("PHY Address %d is out of range\n", offset);
9d5c8243
AK		 327 return -E1000_ERR_PARAM;
328 }
329
330 /* Swap the data bytes for the I2C interface */
331 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
332
333 /*
334 * Set up Op-code, Phy Address, and register address in the I2CCMD
335 * register. The MAC will take care of interfacing with the
336 * PHY to retrieve the desired data.
337 */
338 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
339 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
340 E1000_I2CCMD_OPCODE_WRITE |
341 phy_data_swapped);
342
343 wr32(E1000_I2CCMD, i2ccmd);
344
345 /* Poll the ready bit to see if the I2C read completed */
346 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
347 udelay(50);
348 i2ccmd = rd32(E1000_I2CCMD);
349 if (i2ccmd & E1000_I2CCMD_READY)
350 break;
351 }
352 if (!(i2ccmd & E1000_I2CCMD_READY)) {
652fff32 353 hw_dbg("I2CCMD Write did not complete\n");
9d5c8243
AK		 354 return -E1000_ERR_PHY;
355 }
356 if (i2ccmd & E1000_I2CCMD_ERROR) {
652fff32 357 hw_dbg("I2CCMD Error bit set\n");
9d5c8243
AK		 358 return -E1000_ERR_PHY;
359 }
360
361 return 0;
362}
363
364/**
733596be 365 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 366 * @hw: pointer to the HW structure
367 *
652fff32 368 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 369 * sgmi interface.
370 **/
371static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
372{
373 struct e1000_phy_info *phy = &hw->phy;
374 s32 ret_val = 0;
375 u16 phy_id;
376
377 /*
378 * For SGMII PHYs, we try the list of possible addresses until
379 * we find one that works. For non-SGMII PHYs
380 * (e.g. integrated copper PHYs), an address of 1 should
381 * work. The result of this function should mean phy->phy_addr
382 * and phy->id are set correctly.
383 */
384 if (!(igb_sgmii_active_82575(hw))) {
385 phy->addr = 1;
386 ret_val = igb_get_phy_id(hw);
387 goto out;
388 }
389
390 /*
391 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
392 * Therefore, we need to test 1-7
393 */
394 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
395 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
396 if (ret_val == 0) {
652fff32
AK		 397 hw_dbg("Vendor ID 0x%08X read at address %u\n",
398 phy_id, phy->addr);
9d5c8243
AK		 399 /*
400 * At the time of this writing, The M88 part is
401 * the only supported SGMII PHY product.
402 */
403 if (phy_id == M88_VENDOR)
404 break;
405 } else {
652fff32 406 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 407 }
408 }
409
410 /* A valid PHY type couldn't be found. */
411 if (phy->addr == 8) {
412 phy->addr = 0;
413 ret_val = -E1000_ERR_PHY;
414 goto out;
415 }
416
417 ret_val = igb_get_phy_id(hw);
418
419out:
420 return ret_val;
421}
422
423/**
733596be 424 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 425 * @hw: pointer to the HW structure
426 *
427 * Resets the PHY using the serial gigabit media independent interface.
428 **/
429static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
430{
431 s32 ret_val;
432
433 /*
434 * This isn't a true "hard" reset, but is the only reset
435 * available to us at this time.
436 */
437
652fff32 438 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 439
440 /*
441 * SFP documentation requires the following to configure the SPF module
442 * to work on SGMII. No further documentation is given.
443 */
a8d2a0c2 444 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 445 if (ret_val)
446 goto out;
447
448 ret_val = igb_phy_sw_reset(hw);
449
450out:
451 return ret_val;
452}
453
454/**
733596be 455 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 456 * @hw: pointer to the HW structure
457 * @active: true to enable LPLU, false to disable
458 *
459 * Sets the LPLU D0 state according to the active flag. When
460 * activating LPLU this function also disables smart speed
461 * and vice versa. LPLU will not be activated unless the
462 * device autonegotiation advertisement meets standards of
463 * either 10 or 10/100 or 10/100/1000 at all duplexes.
464 * This is a function pointer entry point only called by
465 * PHY setup routines.
466 **/
467static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
468{
469 struct e1000_phy_info *phy = &hw->phy;
470 s32 ret_val;
471 u16 data;
472
a8d2a0c2 473 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 474 if (ret_val)
475 goto out;
476
477 if (active) {
478 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 479 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 480 data);
9d5c8243
AK		 481 if (ret_val)
482 goto out;
483
484 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 485 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 486 &data);
9d5c8243 487 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 488 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 489 data);
9d5c8243
AK		 490 if (ret_val)
491 goto out;
492 } else {
493 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 494 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 495 data);
9d5c8243
AK		 496 /*
497 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
498 * during Dx states where the power conservation is most
499 * important. During driver activity we should enable
500 * SmartSpeed, so performance is maintained.
501 */
502 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 503 ret_val = phy->ops.read_reg(hw,
652fff32 504 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 505 if (ret_val)
506 goto out;
507
508 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 509 ret_val = phy->ops.write_reg(hw,
652fff32 510 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 511 if (ret_val)
512 goto out;
513 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 514 ret_val = phy->ops.read_reg(hw,
652fff32 515 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 516 if (ret_val)
517 goto out;
518
519 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 520 ret_val = phy->ops.write_reg(hw,
652fff32 521 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 522 if (ret_val)
523 goto out;
524 }
525 }
526
527out:
528 return ret_val;
529}
530
531/**
733596be 532 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 533 * @hw: pointer to the HW structure
534 *
652fff32 535 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 536 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
537 * Return successful if access grant bit set, else clear the request for
538 * EEPROM access and return -E1000_ERR_NVM (-1).
539 **/
540static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
541{
542 s32 ret_val;
543
544 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
545 if (ret_val)
546 goto out;
547
548 ret_val = igb_acquire_nvm(hw);
549
550 if (ret_val)
551 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
552
553out:
554 return ret_val;
555}
556
557/**
733596be 558 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 559 * @hw: pointer to the HW structure
560 *
561 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
562 * then release the semaphores acquired.
563 **/
564static void igb_release_nvm_82575(struct e1000_hw *hw)
565{
566 igb_release_nvm(hw);
567 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
568}
569
570/**
733596be 571 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 572 * @hw: pointer to the HW structure
573 * @mask: specifies which semaphore to acquire
574 *
575 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
576 * will also specify which port we're acquiring the lock for.
577 **/
578static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
579{
580 u32 swfw_sync;
581 u32 swmask = mask;
582 u32 fwmask = mask << 16;
583 s32 ret_val = 0;
584 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
585
586 while (i < timeout) {
587 if (igb_get_hw_semaphore(hw)) {
588 ret_val = -E1000_ERR_SWFW_SYNC;
589 goto out;
590 }
591
592 swfw_sync = rd32(E1000_SW_FW_SYNC);
593 if (!(swfw_sync & (fwmask | swmask)))
594 break;
595
596 /*
597 * Firmware currently using resource (fwmask)
598 * or other software thread using resource (swmask)
599 */
600 igb_put_hw_semaphore(hw);
601 mdelay(5);
602 i++;
603 }
604
605 if (i == timeout) {
652fff32 606 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 607 ret_val = -E1000_ERR_SWFW_SYNC;
608 goto out;
609 }
610
611 swfw_sync |= swmask;
612 wr32(E1000_SW_FW_SYNC, swfw_sync);
613
614 igb_put_hw_semaphore(hw);
615
616out:
617 return ret_val;
618}
619
620/**
733596be 621 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 622 * @hw: pointer to the HW structure
623 * @mask: specifies which semaphore to acquire
624 *
625 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
626 * will also specify which port we're releasing the lock for.
627 **/
628static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
629{
630 u32 swfw_sync;
631
632 while (igb_get_hw_semaphore(hw) != 0);
633 /* Empty */
634
635 swfw_sync = rd32(E1000_SW_FW_SYNC);
636 swfw_sync &= ~mask;
637 wr32(E1000_SW_FW_SYNC, swfw_sync);
638
639 igb_put_hw_semaphore(hw);
640}
641
642/**
733596be 643 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 644 * @hw: pointer to the HW structure
645 *
646 * Read the management control register for the config done bit for
647 * completion status. NOTE: silicon which is EEPROM-less will fail trying
648 * to read the config done bit, so an error is *ONLY* logged and returns
649 * 0. If we were to return with error, EEPROM-less silicon
650 * would not be able to be reset or change link.
651 **/
652static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
653{
654 s32 timeout = PHY_CFG_TIMEOUT;
655 s32 ret_val = 0;
656 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
657
658 if (hw->bus.func == 1)
659 mask = E1000_NVM_CFG_DONE_PORT_1;
660
661 while (timeout) {
662 if (rd32(E1000_EEMNGCTL) & mask)
663 break;
664 msleep(1);
665 timeout--;
666 }
667 if (!timeout)
652fff32 668 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 669
670 /* If EEPROM is not marked present, init the PHY manually */
671 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
672 (hw->phy.type == e1000_phy_igp_3))
673 igb_phy_init_script_igp3(hw);
674
675 return ret_val;
676}
677
678/**
733596be 679 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 680 * @hw: pointer to the HW structure
681 *
682 * If sgmii is enabled, then use the pcs register to determine link, otherwise
683 * use the generic interface for determining link.
684 **/
685static s32 igb_check_for_link_82575(struct e1000_hw *hw)
686{
687 s32 ret_val;
688 u16 speed, duplex;
689
690 /* SGMII link check is done through the PCS register. */
691 if ((hw->phy.media_type != e1000_media_type_copper) ||
5d0932a5 692 (igb_sgmii_active_82575(hw))) {
9d5c8243 693 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 694 &duplex);
5d0932a5
AD		 695 /*
696 * Use this flag to determine if link needs to be checked or
697 * not. If we have link clear the flag so that we do not
698 * continue to check for link.
699 */
700 hw->mac.get_link_status = !hw->mac.serdes_has_link;
701 } else {
9d5c8243 702 ret_val = igb_check_for_copper_link(hw);
5d0932a5 703 }
9d5c8243
AK		 704
705 return ret_val;
706}
9d5c8243 707/**
733596be 708 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 709 * @hw: pointer to the HW structure
710 * @speed: stores the current speed
711 * @duplex: stores the current duplex
712 *
652fff32 713 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 714 * duplex, then store the values in the pointers provided.
715 **/
716static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
717 u16 *duplex)
718{
719 struct e1000_mac_info *mac = &hw->mac;
720 u32 pcs;
721
722 /* Set up defaults for the return values of this function */
723 mac->serdes_has_link = false;
724 *speed = 0;
725 *duplex = 0;
726
727 /*
728 * Read the PCS Status register for link state. For non-copper mode,
729 * the status register is not accurate. The PCS status register is
730 * used instead.
731 */
732 pcs = rd32(E1000_PCS_LSTAT);
733
734 /*
735 * The link up bit determines when link is up on autoneg. The sync ok
736 * gets set once both sides sync up and agree upon link. Stable link
737 * can be determined by checking for both link up and link sync ok
738 */
739 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
740 mac->serdes_has_link = true;
741
742 /* Detect and store PCS speed */
743 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
744 *speed = SPEED_1000;
745 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
746 *speed = SPEED_100;
747 } else {
748 *speed = SPEED_10;
749 }
750
751 /* Detect and store PCS duplex */
752 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
753 *duplex = FULL_DUPLEX;
754 } else {
755 *duplex = HALF_DUPLEX;
756 }
757 }
758
759 return 0;
760}
761
762/**
2d064c06
AD		 763 * igb_init_rx_addrs_82575 - Initialize receive address's
764 * @hw: pointer to the HW structure
765 * @rar_count: receive address registers
766 *
767 * Setups the receive address registers by setting the base receive address
768 * register to the devices MAC address and clearing all the other receive
769 * address registers to 0.
770 **/
771static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
772{
773 u32 i;
774 u8 addr[6] = {0,0,0,0,0,0};
775 /*
776 * This function is essentially the same as that of
777 * e1000_init_rx_addrs_generic. However it also takes care
778 * of the special case where the register offset of the
779 * second set of RARs begins elsewhere. This is implicitly taken care by
780 * function e1000_rar_set_generic.
781 */
782
783 hw_dbg("e1000_init_rx_addrs_82575");
784
785 /* Setup the receive address */
786 hw_dbg("Programming MAC Address into RAR[0]\n");
787 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
788
789 /* Zero out the other (rar_entry_count - 1) receive addresses */
790 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
791 for (i = 1; i < rar_count; i++)
792 hw->mac.ops.rar_set(hw, addr, i);
793}
794
795/**
8a900862 796 * igb_update_mc_addr_list - Update Multicast addresses
2d064c06
AD		 797 * @hw: pointer to the HW structure
798 * @mc_addr_list: array of multicast addresses to program
799 * @mc_addr_count: number of multicast addresses to program
800 * @rar_used_count: the first RAR register free to program
801 * @rar_count: total number of supported Receive Address Registers
802 *
803 * Updates the Receive Address Registers and Multicast Table Array.
804 * The caller must have a packed mc_addr_list of multicast addresses.
805 * The parameter rar_count will usually be hw->mac.rar_entry_count
806 * unless there are workarounds that change this.
807 **/
8a900862
AD		 808void igb_update_mc_addr_list(struct e1000_hw *hw,
809 u8 *mc_addr_list, u32 mc_addr_count,
810 u32 rar_used_count, u32 rar_count)
2d064c06
AD		 811{
812 u32 hash_value;
813 u32 i;
814 u8 addr[6] = {0,0,0,0,0,0};
815 /*
816 * This function is essentially the same as that of
817 * igb_update_mc_addr_list_generic. However it also takes care
818 * of the special case where the register offset of the
819 * second set of RARs begins elsewhere. This is implicitly taken care by
820 * function e1000_rar_set_generic.
821 */
822
823 /*
824 * Load the first set of multicast addresses into the exact
825 * filters (RAR). If there are not enough to fill the RAR
826 * array, clear the filters.
827 */
828 for (i = rar_used_count; i < rar_count; i++) {
829 if (mc_addr_count) {
830 igb_rar_set(hw, mc_addr_list, i);
831 mc_addr_count--;
832 mc_addr_list += ETH_ALEN;
833 } else {
834 igb_rar_set(hw, addr, i);
835 }
836 }
837
838 /* Clear the old settings from the MTA */
839 hw_dbg("Clearing MTA\n");
840 for (i = 0; i < hw->mac.mta_reg_count; i++) {
841 array_wr32(E1000_MTA, i, 0);
842 wrfl();
843 }
844
845 /* Load any remaining multicast addresses into the hash table. */
846 for (; mc_addr_count > 0; mc_addr_count--) {
847 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
848 hw_dbg("Hash value = 0x%03X\n", hash_value);
549bdd84 849 igb_mta_set(hw, hash_value);
2d064c06
AD		 850 mc_addr_list += ETH_ALEN;
851 }
852}
853
854/**
855 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
9d5c8243 856 * @hw: pointer to the HW structure
9d5c8243 857 *
2d064c06
AD		 858 * In the case of fiber serdes, shut down optics and PCS on driver unload
859 * when management pass thru is not enabled.
9d5c8243 860 **/
2d064c06 861void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 862{
2d064c06
AD		 863 u32 reg;
864
865 if (hw->mac.type != e1000_82576 ||
866 (hw->phy.media_type != e1000_media_type_fiber &&
867 hw->phy.media_type != e1000_media_type_internal_serdes))
868 return;
869
870 /* if the management interface is not enabled, then power down */
871 if (!igb_enable_mng_pass_thru(hw)) {
872 /* Disable PCS to turn off link */
873 reg = rd32(E1000_PCS_CFG0);
874 reg &= ~E1000_PCS_CFG_PCS_EN;
875 wr32(E1000_PCS_CFG0, reg);
876
877 /* shutdown the laser */
878 reg = rd32(E1000_CTRL_EXT);
879 reg |= E1000_CTRL_EXT_SDP7_DATA;
880 wr32(E1000_CTRL_EXT, reg);
881
882 /* flush the write to verify completion */
883 wrfl();
884 msleep(1);
885 }
9d5c8243
AK		 886
887 return;
888}
889
890/**
733596be 891 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 892 * @hw: pointer to the HW structure
893 *
894 * This resets the hardware into a known state. This is a
895 * function pointer entry point called by the api module.
896 **/
897static s32 igb_reset_hw_82575(struct e1000_hw *hw)
898{
899 u32 ctrl, icr;
900 s32 ret_val;
901
902 /*
903 * Prevent the PCI-E bus from sticking if there is no TLP connection
904 * on the last TLP read/write transaction when MAC is reset.
905 */
906 ret_val = igb_disable_pcie_master(hw);
907 if (ret_val)
652fff32 908 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 909
652fff32 910 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 911 wr32(E1000_IMC, 0xffffffff);
912
913 wr32(E1000_RCTL, 0);
914 wr32(E1000_TCTL, E1000_TCTL_PSP);
915 wrfl();
916
917 msleep(10);
918
919 ctrl = rd32(E1000_CTRL);
920
652fff32 921 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 922 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
923
924 ret_val = igb_get_auto_rd_done(hw);
925 if (ret_val) {
926 /*
927 * When auto config read does not complete, do not
928 * return with an error. This can happen in situations
929 * where there is no eeprom and prevents getting link.
930 */
652fff32 931 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 932 }
933
934 /* If EEPROM is not present, run manual init scripts */
935 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
936 igb_reset_init_script_82575(hw);
937
938 /* Clear any pending interrupt events. */
939 wr32(E1000_IMC, 0xffffffff);
940 icr = rd32(E1000_ICR);
941
942 igb_check_alt_mac_addr(hw);
943
944 return ret_val;
945}
946
947/**
733596be 948 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 949 * @hw: pointer to the HW structure
950 *
951 * This inits the hardware readying it for operation.
952 **/
953static s32 igb_init_hw_82575(struct e1000_hw *hw)
954{
955 struct e1000_mac_info *mac = &hw->mac;
956 s32 ret_val;
957 u16 i, rar_count = mac->rar_entry_count;
958
959 /* Initialize identification LED */
960 ret_val = igb_id_led_init(hw);
961 if (ret_val) {
652fff32 962 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 963 /* This is not fatal and we should not stop init due to this */
964 }
965
966 /* Disabling VLAN filtering */
652fff32 967 hw_dbg("Initializing the IEEE VLAN\n");
9d5c8243
AK		 968 igb_clear_vfta(hw);
969
970 /* Setup the receive address */
2d064c06 971 igb_init_rx_addrs_82575(hw, rar_count);
9d5c8243 972 /* Zero out the Multicast HASH table */
652fff32 973 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 974 for (i = 0; i < mac->mta_reg_count; i++)
975 array_wr32(E1000_MTA, i, 0);
976
977 /* Setup link and flow control */
978 ret_val = igb_setup_link(hw);
979
980 /*
981 * Clear all of the statistics registers (clear on read). It is
982 * important that we do this after we have tried to establish link
983 * because the symbol error count will increment wildly if there
984 * is no link.
985 */
986 igb_clear_hw_cntrs_82575(hw);
987
988 return ret_val;
989}
990
991/**
733596be 992 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 993 * @hw: pointer to the HW structure
994 *
995 * Configures the link for auto-neg or forced speed and duplex. Then we check
996 * for link, once link is established calls to configure collision distance
997 * and flow control are called.
998 **/
999static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1000{
1001 u32 ctrl, led_ctrl;
1002 s32 ret_val;
1003 bool link;
1004
1005 ctrl = rd32(E1000_CTRL);
1006 ctrl |= E1000_CTRL_SLU;
1007 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1008 wr32(E1000_CTRL, ctrl);
1009
1010 switch (hw->phy.type) {
1011 case e1000_phy_m88:
1012 ret_val = igb_copper_link_setup_m88(hw);
1013 break;
1014 case e1000_phy_igp_3:
1015 ret_val = igb_copper_link_setup_igp(hw);
1016 /* Setup activity LED */
1017 led_ctrl = rd32(E1000_LEDCTL);
1018 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1019 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1020 wr32(E1000_LEDCTL, led_ctrl);
1021 break;
1022 default:
1023 ret_val = -E1000_ERR_PHY;
1024 break;
1025 }
1026
1027 if (ret_val)
1028 goto out;
1029
1030 if (hw->mac.autoneg) {
1031 /*
1032 * Setup autoneg and flow control advertisement
1033 * and perform autonegotiation.
1034 */
1035 ret_val = igb_copper_link_autoneg(hw);
1036 if (ret_val)
1037 goto out;
1038 } else {
1039 /*
1040 * PHY will be set to 10H, 10F, 100H or 100F
1041 * depending on user settings.
1042 */
652fff32 1043 hw_dbg("Forcing Speed and Duplex\n");
a8d2a0c2 1044 ret_val = hw->phy.ops.force_speed_duplex(hw);
9d5c8243 1045 if (ret_val) {
652fff32 1046 hw_dbg("Error Forcing Speed and Duplex\n");
9d5c8243
AK		 1047 goto out;
1048 }
1049 }
1050
1051 ret_val = igb_configure_pcs_link_82575(hw);
1052 if (ret_val)
1053 goto out;
1054
1055 /*
1056 * Check link status. Wait up to 100 microseconds for link to become
1057 * valid.
1058 */
652fff32 1059 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
9d5c8243
AK		 1060 if (ret_val)
1061 goto out;
1062
1063 if (link) {
652fff32 1064 hw_dbg("Valid link established!!!\n");
9d5c8243
AK		 1065 /* Config the MAC and PHY after link is up */
1066 igb_config_collision_dist(hw);
1067 ret_val = igb_config_fc_after_link_up(hw);
1068 } else {
652fff32 1069 hw_dbg("Unable to establish link!!!\n");
9d5c8243
AK		 1070 }
1071
1072out:
1073 return ret_val;
1074}
1075
1076/**
733596be 1077 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
9d5c8243
AK		 1078 * @hw: pointer to the HW structure
1079 *
1080 * Configures speed and duplex for fiber and serdes links.
1081 **/
1082static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1083{
1084 u32 reg;
1085
1086 /*
1087 * On the 82575, SerDes loopback mode persists until it is
1088 * explicitly turned off or a power cycle is performed. A read to
1089 * the register does not indicate its status. Therefore, we ensure
1090 * loopback mode is disabled during initialization.
1091 */
1092 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1093
1094 /* Force link up, set 1gb, set both sw defined pins */
1095 reg = rd32(E1000_CTRL);
1096 reg |= E1000_CTRL_SLU |
1097 E1000_CTRL_SPD_1000 |
1098 E1000_CTRL_FRCSPD |
1099 E1000_CTRL_SWDPIN0 |
1100 E1000_CTRL_SWDPIN1;
1101 wr32(E1000_CTRL, reg);
1102
921aa749
AD		 1103 /* Power on phy for 82576 fiber adapters */
1104 if (hw->mac.type == e1000_82576) {
1105 reg = rd32(E1000_CTRL_EXT);
1106 reg &= ~E1000_CTRL_EXT_SDP7_DATA;
1107 wr32(E1000_CTRL_EXT, reg);
1108 }
1109
9d5c8243
AK		 1110 /* Set switch control to serdes energy detect */
1111 reg = rd32(E1000_CONNSW);
1112 reg |= E1000_CONNSW_ENRGSRC;
1113 wr32(E1000_CONNSW, reg);
1114
1115 /*
1116 * New SerDes mode allows for forcing speed or autonegotiating speed
1117 * at 1gb. Autoneg should be default set by most drivers. This is the
1118 * mode that will be compatible with older link partners and switches.
1119 * However, both are supported by the hardware and some drivers/tools.
1120 */
1121 reg = rd32(E1000_PCS_LCTL);
1122
1123 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1124 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1125
1126 if (hw->mac.autoneg) {
1127 /* Set PCS register for autoneg */
1128 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1129 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1130 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1131 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
652fff32 1132 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
9d5c8243
AK		 1133 } else {
1134 /* Set PCS register for forced speed */
1135 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1136 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1137 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1138 E1000_PCS_LCTL_FSD | /* Force Speed */
1139 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
652fff32 1140 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
9d5c8243 1141 }
726c09e7
AD		 1142
1143 if (hw->mac.type == e1000_82576) {
1144 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1145 igb_force_mac_fc(hw);
1146 }
1147
9d5c8243
AK		 1148 wr32(E1000_PCS_LCTL, reg);
1149
1150 return 0;
1151}
1152
1153/**
733596be 1154 * igb_configure_pcs_link_82575 - Configure PCS link
9d5c8243
AK		 1155 * @hw: pointer to the HW structure
1156 *
1157 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1158 * only used on copper connections where the serialized gigabit media
1159 * independent interface (sgmii) is being used. Configures the link
1160 * for auto-negotiation or forces speed/duplex.
1161 **/
1162static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1163{
1164 struct e1000_mac_info *mac = &hw->mac;
1165 u32 reg = 0;
1166
1167 if (hw->phy.media_type != e1000_media_type_copper ||
1168 !(igb_sgmii_active_82575(hw)))
1169 goto out;
1170
1171 /* For SGMII, we need to issue a PCS autoneg restart */
1172 reg = rd32(E1000_PCS_LCTL);
1173
1174 /* AN time out should be disabled for SGMII mode */
1175 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1176
1177 if (mac->autoneg) {
1178 /* Make sure forced speed and force link are not set */
1179 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1180
1181 /*
1182 * The PHY should be setup prior to calling this function.
1183 * All we need to do is restart autoneg and enable autoneg.
1184 */
1185 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1186 } else {
652fff32 1187 /* Set PCS register for forced speed */
9d5c8243
AK		 1188
1189 /* Turn off bits for full duplex, speed, and autoneg */
1190 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1191 E1000_PCS_LCTL_FSV_100 |
1192 E1000_PCS_LCTL_FDV_FULL |
1193 E1000_PCS_LCTL_AN_ENABLE);
1194
1195 /* Check for duplex first */
1196 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1197 reg |= E1000_PCS_LCTL_FDV_FULL;
1198
1199 /* Now set speed */
1200 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1201 reg |= E1000_PCS_LCTL_FSV_100;
1202
1203 /* Force speed and force link */
1204 reg |= E1000_PCS_LCTL_FSD |
1205 E1000_PCS_LCTL_FORCE_LINK |
1206 E1000_PCS_LCTL_FLV_LINK_UP;
1207
652fff32 1208 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
9d5c8243
AK		 1209 reg);
1210 }
1211 wr32(E1000_PCS_LCTL, reg);
1212
1213out:
1214 return 0;
1215}
1216
1217/**
733596be 1218 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1219 * @hw: pointer to the HW structure
1220 *
1221 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1222 * which can be enabled for use in the embedded applications. Simply
1223 * return the current state of the sgmii interface.
1224 **/
1225static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1226{
c1889bfe 1227 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
9d5c8243 1228
c1889bfe
AD		 1229 if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576)
1230 return false;
9d5c8243 1231
c1889bfe 1232 return dev_spec->sgmii_active;
9d5c8243
AK		 1233}
1234
1235/**
733596be 1236 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1237 * @hw: pointer to the HW structure
1238 *
1239 * Inits recommended HW defaults after a reset when there is no EEPROM
1240 * detected. This is only for the 82575.
1241 **/
1242static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1243{
1244 if (hw->mac.type == e1000_82575) {
652fff32 1245 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1246 /* SerDes configuration via SERDESCTRL */
1247 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1248 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1249 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1250 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1251
1252 /* CCM configuration via CCMCTL register */
1253 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1254 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1255
1256 /* PCIe lanes configuration */
1257 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1258 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1259 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1260 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1261
1262 /* PCIe PLL Configuration */
1263 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1264 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1265 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1266 }
1267
1268 return 0;
1269}
1270
1271/**
733596be 1272 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1273 * @hw: pointer to the HW structure
1274 **/
1275static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1276{
1277 s32 ret_val = 0;
1278
1279 if (igb_check_alt_mac_addr(hw))
1280 ret_val = igb_read_mac_addr(hw);
1281
1282 return ret_val;
1283}
1284
1285/**
733596be 1286 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1287 * @hw: pointer to the HW structure
1288 *
1289 * Clears the hardware counters by reading the counter registers.
1290 **/
1291static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1292{
1293 u32 temp;
1294
1295 igb_clear_hw_cntrs_base(hw);
1296
1297 temp = rd32(E1000_PRC64);
1298 temp = rd32(E1000_PRC127);
1299 temp = rd32(E1000_PRC255);
1300 temp = rd32(E1000_PRC511);
1301 temp = rd32(E1000_PRC1023);
1302 temp = rd32(E1000_PRC1522);
1303 temp = rd32(E1000_PTC64);
1304 temp = rd32(E1000_PTC127);
1305 temp = rd32(E1000_PTC255);
1306 temp = rd32(E1000_PTC511);
1307 temp = rd32(E1000_PTC1023);
1308 temp = rd32(E1000_PTC1522);
1309
1310 temp = rd32(E1000_ALGNERRC);
1311 temp = rd32(E1000_RXERRC);
1312 temp = rd32(E1000_TNCRS);
1313 temp = rd32(E1000_CEXTERR);
1314 temp = rd32(E1000_TSCTC);
1315 temp = rd32(E1000_TSCTFC);
1316
1317 temp = rd32(E1000_MGTPRC);
1318 temp = rd32(E1000_MGTPDC);
1319 temp = rd32(E1000_MGTPTC);
1320
1321 temp = rd32(E1000_IAC);
1322 temp = rd32(E1000_ICRXOC);
1323
1324 temp = rd32(E1000_ICRXPTC);
1325 temp = rd32(E1000_ICRXATC);
1326 temp = rd32(E1000_ICTXPTC);
1327 temp = rd32(E1000_ICTXATC);
1328 temp = rd32(E1000_ICTXQEC);
1329 temp = rd32(E1000_ICTXQMTC);
1330 temp = rd32(E1000_ICRXDMTC);
1331
1332 temp = rd32(E1000_CBTMPC);
1333 temp = rd32(E1000_HTDPMC);
1334 temp = rd32(E1000_CBRMPC);
1335 temp = rd32(E1000_RPTHC);
1336 temp = rd32(E1000_HGPTC);
1337 temp = rd32(E1000_HTCBDPC);
1338 temp = rd32(E1000_HGORCL);
1339 temp = rd32(E1000_HGORCH);
1340 temp = rd32(E1000_HGOTCL);
1341 temp = rd32(E1000_HGOTCH);
1342 temp = rd32(E1000_LENERRS);
1343
1344 /* This register should not be read in copper configurations */
1345 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1346 temp = rd32(E1000_SCVPC);
1347}
1348
662d7205
AD		 1349/**
1350 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1351 * @hw: pointer to the HW structure
1352 *
1353 * After rx enable if managability is enabled then there is likely some
1354 * bad data at the start of the fifo and possibly in the DMA fifo. This
1355 * function clears the fifos and flushes any packets that came in as rx was
1356 * being enabled.
1357 **/
1358void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1359{
1360 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1361 int i, ms_wait;
1362
1363 if (hw->mac.type != e1000_82575 ||
1364 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1365 return;
1366
1367 /* Disable all RX queues */
1368 for (i = 0; i < 4; i++) {
1369 rxdctl[i] = rd32(E1000_RXDCTL(i));
1370 wr32(E1000_RXDCTL(i),
1371 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1372 }
1373 /* Poll all queues to verify they have shut down */
1374 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1375 msleep(1);
1376 rx_enabled = 0;
1377 for (i = 0; i < 4; i++)
1378 rx_enabled |= rd32(E1000_RXDCTL(i));
1379 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1380 break;
1381 }
1382
1383 if (ms_wait == 10)
1384 hw_dbg("Queue disable timed out after 10ms\n");
1385
1386 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1387 * incoming packets are rejected. Set enable and wait 2ms so that
1388 * any packet that was coming in as RCTL.EN was set is flushed
1389 */
1390 rfctl = rd32(E1000_RFCTL);
1391 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1392
1393 rlpml = rd32(E1000_RLPML);
1394 wr32(E1000_RLPML, 0);
1395
1396 rctl = rd32(E1000_RCTL);
1397 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1398 temp_rctl |= E1000_RCTL_LPE;
1399
1400 wr32(E1000_RCTL, temp_rctl);
1401 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1402 wrfl();
1403 msleep(2);
1404
1405 /* Enable RX queues that were previously enabled and restore our
1406 * previous state
1407 */
1408 for (i = 0; i < 4; i++)
1409 wr32(E1000_RXDCTL(i), rxdctl[i]);
1410 wr32(E1000_RCTL, rctl);
1411 wrfl();
1412
1413 wr32(E1000_RLPML, rlpml);
1414 wr32(E1000_RFCTL, rfctl);
1415
1416 /* Flush receive errors generated by workaround */
1417 rd32(E1000_ROC);
1418 rd32(E1000_RNBC);
1419 rd32(E1000_MPC);
1420}
1421
4ae196df
AD		 1422/**
1423 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1424 * @hw: pointer to the hardware struct
1425 * @enable: state to enter, either enabled or disabled
1426 *
1427 * enables/disables L2 switch loopback functionality.
1428 **/
1429void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1430{
1431 u32 dtxswc = rd32(E1000_DTXSWC);
1432
1433 if (enable)
1434 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1435 else
1436 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1437
1438 wr32(E1000_DTXSWC, dtxswc);
1439}
1440
1441/**
1442 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1443 * @hw: pointer to the hardware struct
1444 * @enable: state to enter, either enabled or disabled
1445 *
1446 * enables/disables replication of packets across multiple pools.
1447 **/
1448void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1449{
1450 u32 vt_ctl = rd32(E1000_VT_CTL);
1451
1452 if (enable)
1453 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1454 else
1455 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1456
1457 wr32(E1000_VT_CTL, vt_ctl);
1458}
1459
9d5c8243
AK		 1460static struct e1000_mac_operations e1000_mac_ops_82575 = {
1461 .reset_hw = igb_reset_hw_82575,
1462 .init_hw = igb_init_hw_82575,
1463 .check_for_link = igb_check_for_link_82575,
2d064c06 1464 .rar_set = igb_rar_set,
9d5c8243
AK		 1465 .read_mac_addr = igb_read_mac_addr_82575,
1466 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1467};
1468
1469static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 1470 .acquire = igb_acquire_phy_82575,
9d5c8243 1471 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 1472 .release = igb_release_phy_82575,
9d5c8243
AK		 1473};
1474
1475static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 1476 .acquire = igb_acquire_nvm_82575,
1477 .read = igb_read_nvm_eerd,
1478 .release = igb_release_nvm_82575,
1479 .write = igb_write_nvm_spi,
9d5c8243
AK		 1480};
1481
1482const struct e1000_info e1000_82575_info = {
1483 .get_invariants = igb_get_invariants_82575,
1484 .mac_ops = &e1000_mac_ops_82575,
1485 .phy_ops = &e1000_phy_ops_82575,
1486 .nvm_ops = &e1000_nvm_ops_82575,
1487};
1488
Linux kernel - Deliverables
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