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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* e1000_82575 | |
29 | * e1000_82576 | |
30 | */ | |
31 | ||
32 | #include <linux/types.h> | |
2d064c06 | 33 | #include <linux/if_ether.h> |
9d5c8243 AK |
34 | |
35 | #include "e1000_mac.h" | |
36 | #include "e1000_82575.h" | |
37 | ||
38 | static s32 igb_get_invariants_82575(struct e1000_hw *); | |
39 | static s32 igb_acquire_phy_82575(struct e1000_hw *); | |
40 | static void igb_release_phy_82575(struct e1000_hw *); | |
41 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); | |
42 | static void igb_release_nvm_82575(struct e1000_hw *); | |
43 | static s32 igb_check_for_link_82575(struct e1000_hw *); | |
44 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |
45 | static s32 igb_init_hw_82575(struct e1000_hw *); | |
46 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | |
47 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | |
bb2ac47b AD |
48 | static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); |
49 | static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); | |
9d5c8243 | 50 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
bb2ac47b | 51 | static s32 igb_reset_hw_82580(struct e1000_hw *); |
9d5c8243 AK |
52 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
53 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | |
2fb02a26 | 54 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *); |
9d5c8243 AK |
55 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
56 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); | |
57 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); | |
9d5c8243 AK |
58 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
59 | u16 *); | |
60 | static s32 igb_get_phy_id_82575(struct e1000_hw *); | |
61 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); | |
62 | static bool igb_sgmii_active_82575(struct e1000_hw *); | |
63 | static s32 igb_reset_init_script_82575(struct e1000_hw *); | |
64 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); | |
009bc06e | 65 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
99870a73 | 66 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); |
9d5c8243 | 67 | |
bb2ac47b AD |
68 | static const u16 e1000_82580_rxpbs_table[] = |
69 | { 36, 72, 144, 1, 2, 4, 8, 16, | |
70 | 35, 70, 140 }; | |
71 | #define E1000_82580_RXPBS_TABLE_SIZE \ | |
72 | (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) | |
73 | ||
4085f746 NN |
74 | /** |
75 | * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO | |
76 | * @hw: pointer to the HW structure | |
77 | * | |
78 | * Called to determine if the I2C pins are being used for I2C or as an | |
79 | * external MDIO interface since the two options are mutually exclusive. | |
80 | **/ | |
81 | static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) | |
82 | { | |
83 | u32 reg = 0; | |
84 | bool ext_mdio = false; | |
85 | ||
86 | switch (hw->mac.type) { | |
87 | case e1000_82575: | |
88 | case e1000_82576: | |
89 | reg = rd32(E1000_MDIC); | |
90 | ext_mdio = !!(reg & E1000_MDIC_DEST); | |
91 | break; | |
92 | case e1000_82580: | |
93 | case e1000_i350: | |
94 | reg = rd32(E1000_MDICNFG); | |
95 | ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); | |
96 | break; | |
97 | default: | |
98 | break; | |
99 | } | |
100 | return ext_mdio; | |
101 | } | |
102 | ||
9d5c8243 AK |
103 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
104 | { | |
105 | struct e1000_phy_info *phy = &hw->phy; | |
106 | struct e1000_nvm_info *nvm = &hw->nvm; | |
107 | struct e1000_mac_info *mac = &hw->mac; | |
c1889bfe | 108 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
9d5c8243 AK |
109 | u32 eecd; |
110 | s32 ret_val; | |
111 | u16 size; | |
112 | u32 ctrl_ext = 0; | |
113 | ||
114 | switch (hw->device_id) { | |
115 | case E1000_DEV_ID_82575EB_COPPER: | |
116 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
117 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
118 | mac->type = e1000_82575; | |
119 | break; | |
2d064c06 | 120 | case E1000_DEV_ID_82576: |
9eb2341d | 121 | case E1000_DEV_ID_82576_NS: |
747d49ba | 122 | case E1000_DEV_ID_82576_NS_SERDES: |
2d064c06 AD |
123 | case E1000_DEV_ID_82576_FIBER: |
124 | case E1000_DEV_ID_82576_SERDES: | |
c8ea5ea9 | 125 | case E1000_DEV_ID_82576_QUAD_COPPER: |
b894fa26 | 126 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
4703bf73 | 127 | case E1000_DEV_ID_82576_SERDES_QUAD: |
2d064c06 AD |
128 | mac->type = e1000_82576; |
129 | break; | |
bb2ac47b AD |
130 | case E1000_DEV_ID_82580_COPPER: |
131 | case E1000_DEV_ID_82580_FIBER: | |
132 | case E1000_DEV_ID_82580_SERDES: | |
133 | case E1000_DEV_ID_82580_SGMII: | |
134 | case E1000_DEV_ID_82580_COPPER_DUAL: | |
308fb39a JG |
135 | case E1000_DEV_ID_DH89XXCC_SGMII: |
136 | case E1000_DEV_ID_DH89XXCC_SERDES: | |
1b5dda33 GJ |
137 | case E1000_DEV_ID_DH89XXCC_BACKPLANE: |
138 | case E1000_DEV_ID_DH89XXCC_SFP: | |
bb2ac47b AD |
139 | mac->type = e1000_82580; |
140 | break; | |
d2ba2ed8 AD |
141 | case E1000_DEV_ID_I350_COPPER: |
142 | case E1000_DEV_ID_I350_FIBER: | |
143 | case E1000_DEV_ID_I350_SERDES: | |
144 | case E1000_DEV_ID_I350_SGMII: | |
145 | mac->type = e1000_i350; | |
146 | break; | |
9d5c8243 AK |
147 | default: |
148 | return -E1000_ERR_MAC_INIT; | |
149 | break; | |
150 | } | |
151 | ||
9d5c8243 AK |
152 | /* Set media type */ |
153 | /* | |
154 | * The 82575 uses bits 22:23 for link mode. The mode can be changed | |
155 | * based on the EEPROM. We cannot rely upon device ID. There | |
156 | * is no distinguishable difference between fiber and internal | |
157 | * SerDes mode on the 82575. There can be an external PHY attached | |
158 | * on the SGMII interface. For this, we'll set sgmii_active to true. | |
159 | */ | |
160 | phy->media_type = e1000_media_type_copper; | |
161 | dev_spec->sgmii_active = false; | |
162 | ||
163 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
2fb02a26 AD |
164 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
165 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
9d5c8243 | 166 | dev_spec->sgmii_active = true; |
2fb02a26 | 167 | break; |
bb2ac47b | 168 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
2fb02a26 AD |
169 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: |
170 | hw->phy.media_type = e1000_media_type_internal_serdes; | |
2fb02a26 AD |
171 | break; |
172 | default: | |
2fb02a26 | 173 | break; |
9d5c8243 | 174 | } |
2fb02a26 | 175 | |
9d5c8243 AK |
176 | /* Set mta register count */ |
177 | mac->mta_reg_count = 128; | |
178 | /* Set rar entry count */ | |
179 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | |
2d064c06 AD |
180 | if (mac->type == e1000_82576) |
181 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | |
bb2ac47b AD |
182 | if (mac->type == e1000_82580) |
183 | mac->rar_entry_count = E1000_RAR_ENTRIES_82580; | |
d2ba2ed8 AD |
184 | if (mac->type == e1000_i350) |
185 | mac->rar_entry_count = E1000_RAR_ENTRIES_I350; | |
bb2ac47b | 186 | /* reset */ |
d2ba2ed8 | 187 | if (mac->type >= e1000_82580) |
bb2ac47b AD |
188 | mac->ops.reset_hw = igb_reset_hw_82580; |
189 | else | |
190 | mac->ops.reset_hw = igb_reset_hw_82575; | |
9d5c8243 AK |
191 | /* Set if part includes ASF firmware */ |
192 | mac->asf_firmware_present = true; | |
193 | /* Set if manageability features are enabled. */ | |
194 | mac->arc_subsystem_valid = | |
195 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) | |
196 | ? true : false; | |
197 | ||
198 | /* physical interface link setup */ | |
199 | mac->ops.setup_physical_interface = | |
200 | (hw->phy.media_type == e1000_media_type_copper) | |
201 | ? igb_setup_copper_link_82575 | |
2fb02a26 | 202 | : igb_setup_serdes_link_82575; |
9d5c8243 AK |
203 | |
204 | /* NVM initialization */ | |
205 | eecd = rd32(E1000_EECD); | |
206 | ||
207 | nvm->opcode_bits = 8; | |
208 | nvm->delay_usec = 1; | |
209 | switch (nvm->override) { | |
210 | case e1000_nvm_override_spi_large: | |
211 | nvm->page_size = 32; | |
212 | nvm->address_bits = 16; | |
213 | break; | |
214 | case e1000_nvm_override_spi_small: | |
215 | nvm->page_size = 8; | |
216 | nvm->address_bits = 8; | |
217 | break; | |
218 | default: | |
219 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
220 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
221 | break; | |
222 | } | |
223 | ||
224 | nvm->type = e1000_nvm_eeprom_spi; | |
225 | ||
226 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
227 | E1000_EECD_SIZE_EX_SHIFT); | |
228 | ||
229 | /* | |
230 | * Added to a constant, "size" becomes the left-shift value | |
231 | * for setting word_size. | |
232 | */ | |
233 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
5c3cad75 JK |
234 | |
235 | /* EEPROM access above 16k is unsupported */ | |
236 | if (size > 14) | |
237 | size = 14; | |
9d5c8243 AK |
238 | nvm->word_size = 1 << size; |
239 | ||
a0c98605 AD |
240 | /* if 82576 then initialize mailbox parameters */ |
241 | if (mac->type == e1000_82576) | |
242 | igb_init_mbx_params_pf(hw); | |
243 | ||
9d5c8243 AK |
244 | /* setup PHY parameters */ |
245 | if (phy->media_type != e1000_media_type_copper) { | |
246 | phy->type = e1000_phy_none; | |
247 | return 0; | |
248 | } | |
249 | ||
250 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
251 | phy->reset_delay_us = 100; | |
252 | ||
99870a73 AD |
253 | ctrl_ext = rd32(E1000_CTRL_EXT); |
254 | ||
9d5c8243 | 255 | /* PHY function pointers */ |
99870a73 | 256 | if (igb_sgmii_active_82575(hw)) { |
4085f746 | 257 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
99870a73 AD |
258 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
259 | } else { | |
4085f746 | 260 | phy->ops.reset = igb_phy_hw_reset; |
99870a73 AD |
261 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
262 | } | |
263 | ||
264 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
265 | igb_reset_mdicnfg_82580(hw); | |
4085f746 NN |
266 | |
267 | if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { | |
268 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; | |
269 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; | |
d2ba2ed8 | 270 | } else if (hw->mac.type >= e1000_82580) { |
4085f746 NN |
271 | phy->ops.read_reg = igb_read_phy_reg_82580; |
272 | phy->ops.write_reg = igb_write_phy_reg_82580; | |
9d5c8243 | 273 | } else { |
4085f746 NN |
274 | phy->ops.read_reg = igb_read_phy_reg_igp; |
275 | phy->ops.write_reg = igb_write_phy_reg_igp; | |
9d5c8243 AK |
276 | } |
277 | ||
19e588e7 AD |
278 | /* set lan id */ |
279 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> | |
280 | E1000_STATUS_FUNC_SHIFT; | |
281 | ||
9d5c8243 AK |
282 | /* Set phy->phy_addr and phy->id. */ |
283 | ret_val = igb_get_phy_id_82575(hw); | |
284 | if (ret_val) | |
285 | return ret_val; | |
286 | ||
287 | /* Verify phy id and set remaining function pointers */ | |
288 | switch (phy->id) { | |
308fb39a JG |
289 | case I347AT4_E_PHY_ID: |
290 | case M88E1112_E_PHY_ID: | |
9d5c8243 AK |
291 | case M88E1111_I_PHY_ID: |
292 | phy->type = e1000_phy_m88; | |
293 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
308fb39a JG |
294 | |
295 | if (phy->id == I347AT4_E_PHY_ID || | |
296 | phy->id == M88E1112_E_PHY_ID) | |
297 | phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; | |
298 | else | |
299 | phy->ops.get_cable_length = igb_get_cable_length_m88; | |
300 | ||
9d5c8243 AK |
301 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
302 | break; | |
303 | case IGP03E1000_E_PHY_ID: | |
304 | phy->type = e1000_phy_igp_3; | |
305 | phy->ops.get_phy_info = igb_get_phy_info_igp; | |
306 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; | |
307 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; | |
308 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; | |
309 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; | |
310 | break; | |
bb2ac47b | 311 | case I82580_I_PHY_ID: |
d2ba2ed8 | 312 | case I350_I_PHY_ID: |
bb2ac47b AD |
313 | phy->type = e1000_phy_82580; |
314 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580; | |
315 | phy->ops.get_cable_length = igb_get_cable_length_82580; | |
316 | phy->ops.get_phy_info = igb_get_phy_info_82580; | |
317 | break; | |
9d5c8243 AK |
318 | default: |
319 | return -E1000_ERR_PHY; | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /** | |
733596be | 326 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
9d5c8243 AK |
327 | * @hw: pointer to the HW structure |
328 | * | |
329 | * Acquire access rights to the correct PHY. This is a | |
330 | * function pointer entry point called by the api module. | |
331 | **/ | |
332 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) | |
333 | { | |
008c3422 | 334 | u16 mask = E1000_SWFW_PHY0_SM; |
9d5c8243 | 335 | |
008c3422 AD |
336 | if (hw->bus.func == E1000_FUNC_1) |
337 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
338 | else if (hw->bus.func == E1000_FUNC_2) |
339 | mask = E1000_SWFW_PHY2_SM; | |
340 | else if (hw->bus.func == E1000_FUNC_3) | |
341 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 AK |
342 | |
343 | return igb_acquire_swfw_sync_82575(hw, mask); | |
344 | } | |
345 | ||
346 | /** | |
733596be | 347 | * igb_release_phy_82575 - Release rights to access PHY |
9d5c8243 AK |
348 | * @hw: pointer to the HW structure |
349 | * | |
350 | * A wrapper to release access rights to the correct PHY. This is a | |
351 | * function pointer entry point called by the api module. | |
352 | **/ | |
353 | static void igb_release_phy_82575(struct e1000_hw *hw) | |
354 | { | |
008c3422 AD |
355 | u16 mask = E1000_SWFW_PHY0_SM; |
356 | ||
357 | if (hw->bus.func == E1000_FUNC_1) | |
358 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
359 | else if (hw->bus.func == E1000_FUNC_2) |
360 | mask = E1000_SWFW_PHY2_SM; | |
361 | else if (hw->bus.func == E1000_FUNC_3) | |
362 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 | 363 | |
9d5c8243 AK |
364 | igb_release_swfw_sync_82575(hw, mask); |
365 | } | |
366 | ||
367 | /** | |
733596be | 368 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
9d5c8243 AK |
369 | * @hw: pointer to the HW structure |
370 | * @offset: register offset to be read | |
371 | * @data: pointer to the read data | |
372 | * | |
373 | * Reads the PHY register at offset using the serial gigabit media independent | |
374 | * interface and stores the retrieved information in data. | |
375 | **/ | |
376 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
377 | u16 *data) | |
378 | { | |
bf6f7a92 | 379 | s32 ret_val = -E1000_ERR_PARAM; |
9d5c8243 AK |
380 | |
381 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 382 | hw_dbg("PHY Address %u is out of range\n", offset); |
bf6f7a92 | 383 | goto out; |
9d5c8243 AK |
384 | } |
385 | ||
bf6f7a92 AD |
386 | ret_val = hw->phy.ops.acquire(hw); |
387 | if (ret_val) | |
388 | goto out; | |
9d5c8243 | 389 | |
bf6f7a92 | 390 | ret_val = igb_read_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 391 | |
bf6f7a92 AD |
392 | hw->phy.ops.release(hw); |
393 | ||
394 | out: | |
395 | return ret_val; | |
9d5c8243 AK |
396 | } |
397 | ||
398 | /** | |
733596be | 399 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
9d5c8243 AK |
400 | * @hw: pointer to the HW structure |
401 | * @offset: register offset to write to | |
402 | * @data: data to write at register offset | |
403 | * | |
404 | * Writes the data to PHY register at the offset using the serial gigabit | |
405 | * media independent interface. | |
406 | **/ | |
407 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
408 | u16 data) | |
409 | { | |
bf6f7a92 AD |
410 | s32 ret_val = -E1000_ERR_PARAM; |
411 | ||
9d5c8243 AK |
412 | |
413 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 414 | hw_dbg("PHY Address %d is out of range\n", offset); |
bf6f7a92 | 415 | goto out; |
9d5c8243 AK |
416 | } |
417 | ||
bf6f7a92 AD |
418 | ret_val = hw->phy.ops.acquire(hw); |
419 | if (ret_val) | |
420 | goto out; | |
9d5c8243 | 421 | |
bf6f7a92 | 422 | ret_val = igb_write_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 423 | |
bf6f7a92 AD |
424 | hw->phy.ops.release(hw); |
425 | ||
426 | out: | |
427 | return ret_val; | |
9d5c8243 AK |
428 | } |
429 | ||
430 | /** | |
733596be | 431 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
9d5c8243 AK |
432 | * @hw: pointer to the HW structure |
433 | * | |
652fff32 | 434 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
9d5c8243 AK |
435 | * sgmi interface. |
436 | **/ | |
437 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) | |
438 | { | |
439 | struct e1000_phy_info *phy = &hw->phy; | |
440 | s32 ret_val = 0; | |
441 | u16 phy_id; | |
2fb02a26 | 442 | u32 ctrl_ext; |
4085f746 | 443 | u32 mdic; |
9d5c8243 AK |
444 | |
445 | /* | |
446 | * For SGMII PHYs, we try the list of possible addresses until | |
447 | * we find one that works. For non-SGMII PHYs | |
448 | * (e.g. integrated copper PHYs), an address of 1 should | |
449 | * work. The result of this function should mean phy->phy_addr | |
450 | * and phy->id are set correctly. | |
451 | */ | |
452 | if (!(igb_sgmii_active_82575(hw))) { | |
453 | phy->addr = 1; | |
454 | ret_val = igb_get_phy_id(hw); | |
455 | goto out; | |
456 | } | |
457 | ||
4085f746 NN |
458 | if (igb_sgmii_uses_mdio_82575(hw)) { |
459 | switch (hw->mac.type) { | |
460 | case e1000_82575: | |
461 | case e1000_82576: | |
462 | mdic = rd32(E1000_MDIC); | |
463 | mdic &= E1000_MDIC_PHY_MASK; | |
464 | phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; | |
465 | break; | |
466 | case e1000_82580: | |
467 | case e1000_i350: | |
468 | mdic = rd32(E1000_MDICNFG); | |
469 | mdic &= E1000_MDICNFG_PHY_MASK; | |
470 | phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; | |
471 | break; | |
472 | default: | |
473 | ret_val = -E1000_ERR_PHY; | |
474 | goto out; | |
475 | break; | |
476 | } | |
477 | ret_val = igb_get_phy_id(hw); | |
478 | goto out; | |
479 | } | |
480 | ||
2fb02a26 AD |
481 | /* Power on sgmii phy if it is disabled */ |
482 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
483 | wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); | |
484 | wrfl(); | |
485 | msleep(300); | |
486 | ||
9d5c8243 AK |
487 | /* |
488 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. | |
489 | * Therefore, we need to test 1-7 | |
490 | */ | |
491 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { | |
492 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); | |
493 | if (ret_val == 0) { | |
652fff32 AK |
494 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
495 | phy_id, phy->addr); | |
9d5c8243 AK |
496 | /* |
497 | * At the time of this writing, The M88 part is | |
498 | * the only supported SGMII PHY product. | |
499 | */ | |
500 | if (phy_id == M88_VENDOR) | |
501 | break; | |
502 | } else { | |
652fff32 | 503 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
9d5c8243 AK |
504 | } |
505 | } | |
506 | ||
507 | /* A valid PHY type couldn't be found. */ | |
508 | if (phy->addr == 8) { | |
509 | phy->addr = 0; | |
510 | ret_val = -E1000_ERR_PHY; | |
511 | goto out; | |
2fb02a26 AD |
512 | } else { |
513 | ret_val = igb_get_phy_id(hw); | |
9d5c8243 AK |
514 | } |
515 | ||
2fb02a26 AD |
516 | /* restore previous sfp cage power state */ |
517 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
9d5c8243 AK |
518 | |
519 | out: | |
520 | return ret_val; | |
521 | } | |
522 | ||
523 | /** | |
733596be | 524 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
9d5c8243 AK |
525 | * @hw: pointer to the HW structure |
526 | * | |
527 | * Resets the PHY using the serial gigabit media independent interface. | |
528 | **/ | |
529 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) | |
530 | { | |
531 | s32 ret_val; | |
532 | ||
533 | /* | |
534 | * This isn't a true "hard" reset, but is the only reset | |
535 | * available to us at this time. | |
536 | */ | |
537 | ||
652fff32 | 538 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
9d5c8243 AK |
539 | |
540 | /* | |
541 | * SFP documentation requires the following to configure the SPF module | |
542 | * to work on SGMII. No further documentation is given. | |
543 | */ | |
a8d2a0c2 | 544 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
9d5c8243 AK |
545 | if (ret_val) |
546 | goto out; | |
547 | ||
548 | ret_val = igb_phy_sw_reset(hw); | |
549 | ||
550 | out: | |
551 | return ret_val; | |
552 | } | |
553 | ||
554 | /** | |
733596be | 555 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
9d5c8243 AK |
556 | * @hw: pointer to the HW structure |
557 | * @active: true to enable LPLU, false to disable | |
558 | * | |
559 | * Sets the LPLU D0 state according to the active flag. When | |
560 | * activating LPLU this function also disables smart speed | |
561 | * and vice versa. LPLU will not be activated unless the | |
562 | * device autonegotiation advertisement meets standards of | |
563 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
564 | * This is a function pointer entry point only called by | |
565 | * PHY setup routines. | |
566 | **/ | |
567 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) | |
568 | { | |
569 | struct e1000_phy_info *phy = &hw->phy; | |
570 | s32 ret_val; | |
571 | u16 data; | |
572 | ||
a8d2a0c2 | 573 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
574 | if (ret_val) |
575 | goto out; | |
576 | ||
577 | if (active) { | |
578 | data |= IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 579 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 580 | data); |
9d5c8243 AK |
581 | if (ret_val) |
582 | goto out; | |
583 | ||
584 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 585 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 586 | &data); |
9d5c8243 | 587 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
a8d2a0c2 | 588 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 589 | data); |
9d5c8243 AK |
590 | if (ret_val) |
591 | goto out; | |
592 | } else { | |
593 | data &= ~IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 594 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 595 | data); |
9d5c8243 AK |
596 | /* |
597 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
598 | * during Dx states where the power conservation is most | |
599 | * important. During driver activity we should enable | |
600 | * SmartSpeed, so performance is maintained. | |
601 | */ | |
602 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 603 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 604 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
605 | if (ret_val) |
606 | goto out; | |
607 | ||
608 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 609 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 610 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
611 | if (ret_val) |
612 | goto out; | |
613 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 614 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 615 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
616 | if (ret_val) |
617 | goto out; | |
618 | ||
619 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 620 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 621 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
622 | if (ret_val) |
623 | goto out; | |
624 | } | |
625 | } | |
626 | ||
627 | out: | |
628 | return ret_val; | |
629 | } | |
630 | ||
631 | /** | |
733596be | 632 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
9d5c8243 AK |
633 | * @hw: pointer to the HW structure |
634 | * | |
652fff32 | 635 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
9d5c8243 AK |
636 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
637 | * Return successful if access grant bit set, else clear the request for | |
638 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
639 | **/ | |
640 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) | |
641 | { | |
642 | s32 ret_val; | |
643 | ||
644 | ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
645 | if (ret_val) | |
646 | goto out; | |
647 | ||
648 | ret_val = igb_acquire_nvm(hw); | |
649 | ||
650 | if (ret_val) | |
651 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
652 | ||
653 | out: | |
654 | return ret_val; | |
655 | } | |
656 | ||
657 | /** | |
733596be | 658 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
9d5c8243 AK |
659 | * @hw: pointer to the HW structure |
660 | * | |
661 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, | |
662 | * then release the semaphores acquired. | |
663 | **/ | |
664 | static void igb_release_nvm_82575(struct e1000_hw *hw) | |
665 | { | |
666 | igb_release_nvm(hw); | |
667 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
668 | } | |
669 | ||
670 | /** | |
733596be | 671 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
9d5c8243 AK |
672 | * @hw: pointer to the HW structure |
673 | * @mask: specifies which semaphore to acquire | |
674 | * | |
675 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
676 | * will also specify which port we're acquiring the lock for. | |
677 | **/ | |
678 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
679 | { | |
680 | u32 swfw_sync; | |
681 | u32 swmask = mask; | |
682 | u32 fwmask = mask << 16; | |
683 | s32 ret_val = 0; | |
684 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | |
685 | ||
686 | while (i < timeout) { | |
687 | if (igb_get_hw_semaphore(hw)) { | |
688 | ret_val = -E1000_ERR_SWFW_SYNC; | |
689 | goto out; | |
690 | } | |
691 | ||
692 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
693 | if (!(swfw_sync & (fwmask | swmask))) | |
694 | break; | |
695 | ||
696 | /* | |
697 | * Firmware currently using resource (fwmask) | |
698 | * or other software thread using resource (swmask) | |
699 | */ | |
700 | igb_put_hw_semaphore(hw); | |
701 | mdelay(5); | |
702 | i++; | |
703 | } | |
704 | ||
705 | if (i == timeout) { | |
652fff32 | 706 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
9d5c8243 AK |
707 | ret_val = -E1000_ERR_SWFW_SYNC; |
708 | goto out; | |
709 | } | |
710 | ||
711 | swfw_sync |= swmask; | |
712 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
713 | ||
714 | igb_put_hw_semaphore(hw); | |
715 | ||
716 | out: | |
717 | return ret_val; | |
718 | } | |
719 | ||
720 | /** | |
733596be | 721 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
9d5c8243 AK |
722 | * @hw: pointer to the HW structure |
723 | * @mask: specifies which semaphore to acquire | |
724 | * | |
725 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
726 | * will also specify which port we're releasing the lock for. | |
727 | **/ | |
728 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
729 | { | |
730 | u32 swfw_sync; | |
731 | ||
732 | while (igb_get_hw_semaphore(hw) != 0); | |
733 | /* Empty */ | |
734 | ||
735 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
736 | swfw_sync &= ~mask; | |
737 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
738 | ||
739 | igb_put_hw_semaphore(hw); | |
740 | } | |
741 | ||
742 | /** | |
733596be | 743 | * igb_get_cfg_done_82575 - Read config done bit |
9d5c8243 AK |
744 | * @hw: pointer to the HW structure |
745 | * | |
746 | * Read the management control register for the config done bit for | |
747 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
748 | * to read the config done bit, so an error is *ONLY* logged and returns | |
749 | * 0. If we were to return with error, EEPROM-less silicon | |
750 | * would not be able to be reset or change link. | |
751 | **/ | |
752 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) | |
753 | { | |
754 | s32 timeout = PHY_CFG_TIMEOUT; | |
755 | s32 ret_val = 0; | |
756 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
757 | ||
758 | if (hw->bus.func == 1) | |
759 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
bb2ac47b AD |
760 | else if (hw->bus.func == E1000_FUNC_2) |
761 | mask = E1000_NVM_CFG_DONE_PORT_2; | |
762 | else if (hw->bus.func == E1000_FUNC_3) | |
763 | mask = E1000_NVM_CFG_DONE_PORT_3; | |
9d5c8243 AK |
764 | |
765 | while (timeout) { | |
766 | if (rd32(E1000_EEMNGCTL) & mask) | |
767 | break; | |
768 | msleep(1); | |
769 | timeout--; | |
770 | } | |
771 | if (!timeout) | |
652fff32 | 772 | hw_dbg("MNG configuration cycle has not completed.\n"); |
9d5c8243 AK |
773 | |
774 | /* If EEPROM is not marked present, init the PHY manually */ | |
775 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && | |
776 | (hw->phy.type == e1000_phy_igp_3)) | |
777 | igb_phy_init_script_igp3(hw); | |
778 | ||
779 | return ret_val; | |
780 | } | |
781 | ||
782 | /** | |
733596be | 783 | * igb_check_for_link_82575 - Check for link |
9d5c8243 AK |
784 | * @hw: pointer to the HW structure |
785 | * | |
786 | * If sgmii is enabled, then use the pcs register to determine link, otherwise | |
787 | * use the generic interface for determining link. | |
788 | **/ | |
789 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |
790 | { | |
791 | s32 ret_val; | |
792 | u16 speed, duplex; | |
793 | ||
70d92f86 | 794 | if (hw->phy.media_type != e1000_media_type_copper) { |
9d5c8243 | 795 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
2d064c06 | 796 | &duplex); |
5d0932a5 AD |
797 | /* |
798 | * Use this flag to determine if link needs to be checked or | |
799 | * not. If we have link clear the flag so that we do not | |
800 | * continue to check for link. | |
801 | */ | |
802 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | |
803 | } else { | |
9d5c8243 | 804 | ret_val = igb_check_for_copper_link(hw); |
5d0932a5 | 805 | } |
9d5c8243 AK |
806 | |
807 | return ret_val; | |
808 | } | |
70d92f86 | 809 | |
88a268c1 NN |
810 | /** |
811 | * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown | |
812 | * @hw: pointer to the HW structure | |
813 | **/ | |
814 | void igb_power_up_serdes_link_82575(struct e1000_hw *hw) | |
815 | { | |
816 | u32 reg; | |
817 | ||
818 | ||
819 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
820 | !igb_sgmii_active_82575(hw)) | |
821 | return; | |
822 | ||
823 | /* Enable PCS to turn on link */ | |
824 | reg = rd32(E1000_PCS_CFG0); | |
825 | reg |= E1000_PCS_CFG_PCS_EN; | |
826 | wr32(E1000_PCS_CFG0, reg); | |
827 | ||
828 | /* Power up the laser */ | |
829 | reg = rd32(E1000_CTRL_EXT); | |
830 | reg &= ~E1000_CTRL_EXT_SDP3_DATA; | |
831 | wr32(E1000_CTRL_EXT, reg); | |
832 | ||
833 | /* flush the write to verify completion */ | |
834 | wrfl(); | |
835 | msleep(1); | |
836 | } | |
837 | ||
9d5c8243 | 838 | /** |
733596be | 839 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
9d5c8243 AK |
840 | * @hw: pointer to the HW structure |
841 | * @speed: stores the current speed | |
842 | * @duplex: stores the current duplex | |
843 | * | |
652fff32 | 844 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
9d5c8243 AK |
845 | * duplex, then store the values in the pointers provided. |
846 | **/ | |
847 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |
848 | u16 *duplex) | |
849 | { | |
850 | struct e1000_mac_info *mac = &hw->mac; | |
851 | u32 pcs; | |
852 | ||
853 | /* Set up defaults for the return values of this function */ | |
854 | mac->serdes_has_link = false; | |
855 | *speed = 0; | |
856 | *duplex = 0; | |
857 | ||
858 | /* | |
859 | * Read the PCS Status register for link state. For non-copper mode, | |
860 | * the status register is not accurate. The PCS status register is | |
861 | * used instead. | |
862 | */ | |
863 | pcs = rd32(E1000_PCS_LSTAT); | |
864 | ||
865 | /* | |
866 | * The link up bit determines when link is up on autoneg. The sync ok | |
867 | * gets set once both sides sync up and agree upon link. Stable link | |
868 | * can be determined by checking for both link up and link sync ok | |
869 | */ | |
870 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { | |
871 | mac->serdes_has_link = true; | |
872 | ||
873 | /* Detect and store PCS speed */ | |
874 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { | |
875 | *speed = SPEED_1000; | |
876 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { | |
877 | *speed = SPEED_100; | |
878 | } else { | |
879 | *speed = SPEED_10; | |
880 | } | |
881 | ||
882 | /* Detect and store PCS duplex */ | |
883 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { | |
884 | *duplex = FULL_DUPLEX; | |
885 | } else { | |
886 | *duplex = HALF_DUPLEX; | |
887 | } | |
888 | } | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
2d064c06 | 893 | /** |
2fb02a26 | 894 | * igb_shutdown_serdes_link_82575 - Remove link during power down |
9d5c8243 | 895 | * @hw: pointer to the HW structure |
9d5c8243 | 896 | * |
2d064c06 AD |
897 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
898 | * when management pass thru is not enabled. | |
9d5c8243 | 899 | **/ |
2fb02a26 | 900 | void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 901 | { |
2d064c06 AD |
902 | u32 reg; |
903 | ||
53c992fa | 904 | if (hw->phy.media_type != e1000_media_type_internal_serdes && |
2fb02a26 | 905 | igb_sgmii_active_82575(hw)) |
2d064c06 AD |
906 | return; |
907 | ||
53c992fa | 908 | if (!igb_enable_mng_pass_thru(hw)) { |
2d064c06 AD |
909 | /* Disable PCS to turn off link */ |
910 | reg = rd32(E1000_PCS_CFG0); | |
911 | reg &= ~E1000_PCS_CFG_PCS_EN; | |
912 | wr32(E1000_PCS_CFG0, reg); | |
913 | ||
914 | /* shutdown the laser */ | |
915 | reg = rd32(E1000_CTRL_EXT); | |
2fb02a26 | 916 | reg |= E1000_CTRL_EXT_SDP3_DATA; |
2d064c06 AD |
917 | wr32(E1000_CTRL_EXT, reg); |
918 | ||
919 | /* flush the write to verify completion */ | |
920 | wrfl(); | |
921 | msleep(1); | |
922 | } | |
9d5c8243 AK |
923 | } |
924 | ||
925 | /** | |
733596be | 926 | * igb_reset_hw_82575 - Reset hardware |
9d5c8243 AK |
927 | * @hw: pointer to the HW structure |
928 | * | |
929 | * This resets the hardware into a known state. This is a | |
930 | * function pointer entry point called by the api module. | |
931 | **/ | |
932 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) | |
933 | { | |
934 | u32 ctrl, icr; | |
935 | s32 ret_val; | |
936 | ||
937 | /* | |
938 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
939 | * on the last TLP read/write transaction when MAC is reset. | |
940 | */ | |
941 | ret_val = igb_disable_pcie_master(hw); | |
942 | if (ret_val) | |
652fff32 | 943 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
9d5c8243 | 944 | |
009bc06e AD |
945 | /* set the completion timeout for interface */ |
946 | ret_val = igb_set_pcie_completion_timeout(hw); | |
947 | if (ret_val) { | |
948 | hw_dbg("PCI-E Set completion timeout has failed.\n"); | |
949 | } | |
950 | ||
652fff32 | 951 | hw_dbg("Masking off all interrupts\n"); |
9d5c8243 AK |
952 | wr32(E1000_IMC, 0xffffffff); |
953 | ||
954 | wr32(E1000_RCTL, 0); | |
955 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
956 | wrfl(); | |
957 | ||
958 | msleep(10); | |
959 | ||
960 | ctrl = rd32(E1000_CTRL); | |
961 | ||
652fff32 | 962 | hw_dbg("Issuing a global reset to MAC\n"); |
9d5c8243 AK |
963 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
964 | ||
965 | ret_val = igb_get_auto_rd_done(hw); | |
966 | if (ret_val) { | |
967 | /* | |
968 | * When auto config read does not complete, do not | |
969 | * return with an error. This can happen in situations | |
970 | * where there is no eeprom and prevents getting link. | |
971 | */ | |
652fff32 | 972 | hw_dbg("Auto Read Done did not complete\n"); |
9d5c8243 AK |
973 | } |
974 | ||
975 | /* If EEPROM is not present, run manual init scripts */ | |
976 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
977 | igb_reset_init_script_82575(hw); | |
978 | ||
979 | /* Clear any pending interrupt events. */ | |
980 | wr32(E1000_IMC, 0xffffffff); | |
981 | icr = rd32(E1000_ICR); | |
982 | ||
5ac16659 AD |
983 | /* Install any alternate MAC address into RAR0 */ |
984 | ret_val = igb_check_alt_mac_addr(hw); | |
9d5c8243 AK |
985 | |
986 | return ret_val; | |
987 | } | |
988 | ||
989 | /** | |
733596be | 990 | * igb_init_hw_82575 - Initialize hardware |
9d5c8243 AK |
991 | * @hw: pointer to the HW structure |
992 | * | |
993 | * This inits the hardware readying it for operation. | |
994 | **/ | |
995 | static s32 igb_init_hw_82575(struct e1000_hw *hw) | |
996 | { | |
997 | struct e1000_mac_info *mac = &hw->mac; | |
998 | s32 ret_val; | |
999 | u16 i, rar_count = mac->rar_entry_count; | |
1000 | ||
1001 | /* Initialize identification LED */ | |
1002 | ret_val = igb_id_led_init(hw); | |
1003 | if (ret_val) { | |
652fff32 | 1004 | hw_dbg("Error initializing identification LED\n"); |
9d5c8243 AK |
1005 | /* This is not fatal and we should not stop init due to this */ |
1006 | } | |
1007 | ||
1008 | /* Disabling VLAN filtering */ | |
652fff32 | 1009 | hw_dbg("Initializing the IEEE VLAN\n"); |
9d5c8243 AK |
1010 | igb_clear_vfta(hw); |
1011 | ||
1012 | /* Setup the receive address */ | |
5ac16659 AD |
1013 | igb_init_rx_addrs(hw, rar_count); |
1014 | ||
9d5c8243 | 1015 | /* Zero out the Multicast HASH table */ |
652fff32 | 1016 | hw_dbg("Zeroing the MTA\n"); |
9d5c8243 AK |
1017 | for (i = 0; i < mac->mta_reg_count; i++) |
1018 | array_wr32(E1000_MTA, i, 0); | |
1019 | ||
68d480c4 AD |
1020 | /* Zero out the Unicast HASH table */ |
1021 | hw_dbg("Zeroing the UTA\n"); | |
1022 | for (i = 0; i < mac->uta_reg_count; i++) | |
1023 | array_wr32(E1000_UTA, i, 0); | |
1024 | ||
9d5c8243 AK |
1025 | /* Setup link and flow control */ |
1026 | ret_val = igb_setup_link(hw); | |
1027 | ||
1028 | /* | |
1029 | * Clear all of the statistics registers (clear on read). It is | |
1030 | * important that we do this after we have tried to establish link | |
1031 | * because the symbol error count will increment wildly if there | |
1032 | * is no link. | |
1033 | */ | |
1034 | igb_clear_hw_cntrs_82575(hw); | |
1035 | ||
1036 | return ret_val; | |
1037 | } | |
1038 | ||
1039 | /** | |
733596be | 1040 | * igb_setup_copper_link_82575 - Configure copper link settings |
9d5c8243 AK |
1041 | * @hw: pointer to the HW structure |
1042 | * | |
1043 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1044 | * for link, once link is established calls to configure collision distance | |
1045 | * and flow control are called. | |
1046 | **/ | |
1047 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) | |
1048 | { | |
12645a19 | 1049 | u32 ctrl; |
9d5c8243 | 1050 | s32 ret_val; |
9d5c8243 AK |
1051 | |
1052 | ctrl = rd32(E1000_CTRL); | |
1053 | ctrl |= E1000_CTRL_SLU; | |
1054 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1055 | wr32(E1000_CTRL, ctrl); | |
1056 | ||
2fb02a26 AD |
1057 | ret_val = igb_setup_serdes_link_82575(hw); |
1058 | if (ret_val) | |
1059 | goto out; | |
1060 | ||
1061 | if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { | |
bb2ac47b AD |
1062 | /* allow time for SFP cage time to power up phy */ |
1063 | msleep(300); | |
1064 | ||
2fb02a26 AD |
1065 | ret_val = hw->phy.ops.reset(hw); |
1066 | if (ret_val) { | |
1067 | hw_dbg("Error resetting the PHY.\n"); | |
1068 | goto out; | |
1069 | } | |
1070 | } | |
9d5c8243 AK |
1071 | switch (hw->phy.type) { |
1072 | case e1000_phy_m88: | |
308fb39a JG |
1073 | if (hw->phy.id == I347AT4_E_PHY_ID || |
1074 | hw->phy.id == M88E1112_E_PHY_ID) | |
1075 | ret_val = igb_copper_link_setup_m88_gen2(hw); | |
1076 | else | |
1077 | ret_val = igb_copper_link_setup_m88(hw); | |
9d5c8243 AK |
1078 | break; |
1079 | case e1000_phy_igp_3: | |
1080 | ret_val = igb_copper_link_setup_igp(hw); | |
9d5c8243 | 1081 | break; |
bb2ac47b AD |
1082 | case e1000_phy_82580: |
1083 | ret_val = igb_copper_link_setup_82580(hw); | |
1084 | break; | |
9d5c8243 AK |
1085 | default: |
1086 | ret_val = -E1000_ERR_PHY; | |
1087 | break; | |
1088 | } | |
1089 | ||
1090 | if (ret_val) | |
1091 | goto out; | |
1092 | ||
81fadd81 | 1093 | ret_val = igb_setup_copper_link(hw); |
9d5c8243 AK |
1094 | out: |
1095 | return ret_val; | |
1096 | } | |
1097 | ||
1098 | /** | |
70d92f86 | 1099 | * igb_setup_serdes_link_82575 - Setup link for serdes |
9d5c8243 AK |
1100 | * @hw: pointer to the HW structure |
1101 | * | |
70d92f86 AD |
1102 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
1103 | * used on copper connections where the serialized gigabit media independent | |
1104 | * interface (sgmii), or serdes fiber is being used. Configures the link | |
1105 | * for auto-negotiation or forces speed/duplex. | |
9d5c8243 | 1106 | **/ |
2fb02a26 | 1107 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 1108 | { |
bb2ac47b AD |
1109 | u32 ctrl_ext, ctrl_reg, reg; |
1110 | bool pcs_autoneg; | |
2fb02a26 AD |
1111 | |
1112 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1113 | !igb_sgmii_active_82575(hw)) | |
1114 | return 0; | |
9d5c8243 AK |
1115 | |
1116 | /* | |
1117 | * On the 82575, SerDes loopback mode persists until it is | |
1118 | * explicitly turned off or a power cycle is performed. A read to | |
1119 | * the register does not indicate its status. Therefore, we ensure | |
1120 | * loopback mode is disabled during initialization. | |
1121 | */ | |
1122 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1123 | ||
2fb02a26 | 1124 | /* power on the sfp cage if present */ |
bb2ac47b AD |
1125 | ctrl_ext = rd32(E1000_CTRL_EXT); |
1126 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1127 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
2fb02a26 AD |
1128 | |
1129 | ctrl_reg = rd32(E1000_CTRL); | |
1130 | ctrl_reg |= E1000_CTRL_SLU; | |
1131 | ||
1132 | if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { | |
1133 | /* set both sw defined pins */ | |
1134 | ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; | |
1135 | ||
1136 | /* Set switch control to serdes energy detect */ | |
1137 | reg = rd32(E1000_CONNSW); | |
1138 | reg |= E1000_CONNSW_ENRGSRC; | |
1139 | wr32(E1000_CONNSW, reg); | |
1140 | } | |
1141 | ||
1142 | reg = rd32(E1000_PCS_LCTL); | |
1143 | ||
bb2ac47b AD |
1144 | /* default pcs_autoneg to the same setting as mac autoneg */ |
1145 | pcs_autoneg = hw->mac.autoneg; | |
2fb02a26 | 1146 | |
bb2ac47b AD |
1147 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
1148 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
1149 | /* sgmii mode lets the phy handle forcing speed/duplex */ | |
1150 | pcs_autoneg = true; | |
1151 | /* autoneg time out should be disabled for SGMII mode */ | |
2fb02a26 | 1152 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
bb2ac47b AD |
1153 | break; |
1154 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: | |
1155 | /* disable PCS autoneg and support parallel detect only */ | |
1156 | pcs_autoneg = false; | |
1157 | default: | |
1158 | /* | |
1159 | * non-SGMII modes only supports a speed of 1000/Full for the | |
1160 | * link so it is best to just force the MAC and let the pcs | |
1161 | * link either autoneg or be forced to 1000/Full | |
1162 | */ | |
2fb02a26 AD |
1163 | ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | |
1164 | E1000_CTRL_FD | E1000_CTRL_FRCDPX; | |
bb2ac47b AD |
1165 | |
1166 | /* set speed of 1000/Full if speed/duplex is forced */ | |
1167 | reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; | |
1168 | break; | |
921aa749 AD |
1169 | } |
1170 | ||
2fb02a26 | 1171 | wr32(E1000_CTRL, ctrl_reg); |
9d5c8243 AK |
1172 | |
1173 | /* | |
1174 | * New SerDes mode allows for forcing speed or autonegotiating speed | |
1175 | * at 1gb. Autoneg should be default set by most drivers. This is the | |
1176 | * mode that will be compatible with older link partners and switches. | |
1177 | * However, both are supported by the hardware and some drivers/tools. | |
1178 | */ | |
9d5c8243 AK |
1179 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1180 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1181 | ||
2fb02a26 AD |
1182 | /* |
1183 | * We force flow control to prevent the CTRL register values from being | |
1184 | * overwritten by the autonegotiated flow control values | |
1185 | */ | |
1186 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1187 | ||
bb2ac47b | 1188 | if (pcs_autoneg) { |
9d5c8243 | 1189 | /* Set PCS register for autoneg */ |
bb2ac47b | 1190 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
70d92f86 | 1191 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
bb2ac47b | 1192 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
9d5c8243 | 1193 | } else { |
bb2ac47b | 1194 | /* Set PCS register for forced link */ |
d68caec6 | 1195 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
bb2ac47b AD |
1196 | |
1197 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); | |
9d5c8243 | 1198 | } |
726c09e7 | 1199 | |
9d5c8243 AK |
1200 | wr32(E1000_PCS_LCTL, reg); |
1201 | ||
2fb02a26 AD |
1202 | if (!igb_sgmii_active_82575(hw)) |
1203 | igb_force_mac_fc(hw); | |
9d5c8243 | 1204 | |
2fb02a26 | 1205 | return 0; |
9d5c8243 AK |
1206 | } |
1207 | ||
1208 | /** | |
733596be | 1209 | * igb_sgmii_active_82575 - Return sgmii state |
9d5c8243 AK |
1210 | * @hw: pointer to the HW structure |
1211 | * | |
1212 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) | |
1213 | * which can be enabled for use in the embedded applications. Simply | |
1214 | * return the current state of the sgmii interface. | |
1215 | **/ | |
1216 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) | |
1217 | { | |
c1889bfe | 1218 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
c1889bfe | 1219 | return dev_spec->sgmii_active; |
9d5c8243 AK |
1220 | } |
1221 | ||
1222 | /** | |
733596be | 1223 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
9d5c8243 AK |
1224 | * @hw: pointer to the HW structure |
1225 | * | |
1226 | * Inits recommended HW defaults after a reset when there is no EEPROM | |
1227 | * detected. This is only for the 82575. | |
1228 | **/ | |
1229 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) | |
1230 | { | |
1231 | if (hw->mac.type == e1000_82575) { | |
652fff32 | 1232 | hw_dbg("Running reset init script for 82575\n"); |
9d5c8243 AK |
1233 | /* SerDes configuration via SERDESCTRL */ |
1234 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); | |
1235 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); | |
1236 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); | |
1237 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); | |
1238 | ||
1239 | /* CCM configuration via CCMCTL register */ | |
1240 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); | |
1241 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); | |
1242 | ||
1243 | /* PCIe lanes configuration */ | |
1244 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); | |
1245 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); | |
1246 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); | |
1247 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); | |
1248 | ||
1249 | /* PCIe PLL Configuration */ | |
1250 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); | |
1251 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); | |
1252 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); | |
1253 | } | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | /** | |
733596be | 1259 | * igb_read_mac_addr_82575 - Read device MAC address |
9d5c8243 AK |
1260 | * @hw: pointer to the HW structure |
1261 | **/ | |
1262 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) | |
1263 | { | |
1264 | s32 ret_val = 0; | |
1265 | ||
22896639 AD |
1266 | /* |
1267 | * If there's an alternate MAC address place it in RAR0 | |
1268 | * so that it will override the Si installed default perm | |
1269 | * address. | |
1270 | */ | |
1271 | ret_val = igb_check_alt_mac_addr(hw); | |
1272 | if (ret_val) | |
1273 | goto out; | |
1274 | ||
1275 | ret_val = igb_read_mac_addr(hw); | |
9d5c8243 | 1276 | |
22896639 | 1277 | out: |
9d5c8243 AK |
1278 | return ret_val; |
1279 | } | |
1280 | ||
88a268c1 NN |
1281 | /** |
1282 | * igb_power_down_phy_copper_82575 - Remove link during PHY power down | |
1283 | * @hw: pointer to the HW structure | |
1284 | * | |
1285 | * In the case of a PHY power down to save power, or to turn off link during a | |
1286 | * driver unload, or wake on lan is not enabled, remove the link. | |
1287 | **/ | |
1288 | void igb_power_down_phy_copper_82575(struct e1000_hw *hw) | |
1289 | { | |
1290 | /* If the management interface is not enabled, then power down */ | |
1291 | if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) | |
1292 | igb_power_down_phy_copper(hw); | |
88a268c1 NN |
1293 | } |
1294 | ||
9d5c8243 | 1295 | /** |
733596be | 1296 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
9d5c8243 AK |
1297 | * @hw: pointer to the HW structure |
1298 | * | |
1299 | * Clears the hardware counters by reading the counter registers. | |
1300 | **/ | |
1301 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) | |
1302 | { | |
9d5c8243 AK |
1303 | igb_clear_hw_cntrs_base(hw); |
1304 | ||
cc9073bb AD |
1305 | rd32(E1000_PRC64); |
1306 | rd32(E1000_PRC127); | |
1307 | rd32(E1000_PRC255); | |
1308 | rd32(E1000_PRC511); | |
1309 | rd32(E1000_PRC1023); | |
1310 | rd32(E1000_PRC1522); | |
1311 | rd32(E1000_PTC64); | |
1312 | rd32(E1000_PTC127); | |
1313 | rd32(E1000_PTC255); | |
1314 | rd32(E1000_PTC511); | |
1315 | rd32(E1000_PTC1023); | |
1316 | rd32(E1000_PTC1522); | |
1317 | ||
1318 | rd32(E1000_ALGNERRC); | |
1319 | rd32(E1000_RXERRC); | |
1320 | rd32(E1000_TNCRS); | |
1321 | rd32(E1000_CEXTERR); | |
1322 | rd32(E1000_TSCTC); | |
1323 | rd32(E1000_TSCTFC); | |
1324 | ||
1325 | rd32(E1000_MGTPRC); | |
1326 | rd32(E1000_MGTPDC); | |
1327 | rd32(E1000_MGTPTC); | |
1328 | ||
1329 | rd32(E1000_IAC); | |
1330 | rd32(E1000_ICRXOC); | |
1331 | ||
1332 | rd32(E1000_ICRXPTC); | |
1333 | rd32(E1000_ICRXATC); | |
1334 | rd32(E1000_ICTXPTC); | |
1335 | rd32(E1000_ICTXATC); | |
1336 | rd32(E1000_ICTXQEC); | |
1337 | rd32(E1000_ICTXQMTC); | |
1338 | rd32(E1000_ICRXDMTC); | |
1339 | ||
1340 | rd32(E1000_CBTMPC); | |
1341 | rd32(E1000_HTDPMC); | |
1342 | rd32(E1000_CBRMPC); | |
1343 | rd32(E1000_RPTHC); | |
1344 | rd32(E1000_HGPTC); | |
1345 | rd32(E1000_HTCBDPC); | |
1346 | rd32(E1000_HGORCL); | |
1347 | rd32(E1000_HGORCH); | |
1348 | rd32(E1000_HGOTCL); | |
1349 | rd32(E1000_HGOTCH); | |
1350 | rd32(E1000_LENERRS); | |
9d5c8243 AK |
1351 | |
1352 | /* This register should not be read in copper configurations */ | |
2fb02a26 AD |
1353 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
1354 | igb_sgmii_active_82575(hw)) | |
cc9073bb | 1355 | rd32(E1000_SCVPC); |
9d5c8243 AK |
1356 | } |
1357 | ||
662d7205 AD |
1358 | /** |
1359 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable | |
1360 | * @hw: pointer to the HW structure | |
1361 | * | |
1362 | * After rx enable if managability is enabled then there is likely some | |
1363 | * bad data at the start of the fifo and possibly in the DMA fifo. This | |
1364 | * function clears the fifos and flushes any packets that came in as rx was | |
1365 | * being enabled. | |
1366 | **/ | |
1367 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) | |
1368 | { | |
1369 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; | |
1370 | int i, ms_wait; | |
1371 | ||
1372 | if (hw->mac.type != e1000_82575 || | |
1373 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) | |
1374 | return; | |
1375 | ||
1376 | /* Disable all RX queues */ | |
1377 | for (i = 0; i < 4; i++) { | |
1378 | rxdctl[i] = rd32(E1000_RXDCTL(i)); | |
1379 | wr32(E1000_RXDCTL(i), | |
1380 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); | |
1381 | } | |
1382 | /* Poll all queues to verify they have shut down */ | |
1383 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { | |
1384 | msleep(1); | |
1385 | rx_enabled = 0; | |
1386 | for (i = 0; i < 4; i++) | |
1387 | rx_enabled |= rd32(E1000_RXDCTL(i)); | |
1388 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) | |
1389 | break; | |
1390 | } | |
1391 | ||
1392 | if (ms_wait == 10) | |
1393 | hw_dbg("Queue disable timed out after 10ms\n"); | |
1394 | ||
1395 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all | |
1396 | * incoming packets are rejected. Set enable and wait 2ms so that | |
1397 | * any packet that was coming in as RCTL.EN was set is flushed | |
1398 | */ | |
1399 | rfctl = rd32(E1000_RFCTL); | |
1400 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); | |
1401 | ||
1402 | rlpml = rd32(E1000_RLPML); | |
1403 | wr32(E1000_RLPML, 0); | |
1404 | ||
1405 | rctl = rd32(E1000_RCTL); | |
1406 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); | |
1407 | temp_rctl |= E1000_RCTL_LPE; | |
1408 | ||
1409 | wr32(E1000_RCTL, temp_rctl); | |
1410 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); | |
1411 | wrfl(); | |
1412 | msleep(2); | |
1413 | ||
1414 | /* Enable RX queues that were previously enabled and restore our | |
1415 | * previous state | |
1416 | */ | |
1417 | for (i = 0; i < 4; i++) | |
1418 | wr32(E1000_RXDCTL(i), rxdctl[i]); | |
1419 | wr32(E1000_RCTL, rctl); | |
1420 | wrfl(); | |
1421 | ||
1422 | wr32(E1000_RLPML, rlpml); | |
1423 | wr32(E1000_RFCTL, rfctl); | |
1424 | ||
1425 | /* Flush receive errors generated by workaround */ | |
1426 | rd32(E1000_ROC); | |
1427 | rd32(E1000_RNBC); | |
1428 | rd32(E1000_MPC); | |
1429 | } | |
1430 | ||
009bc06e AD |
1431 | /** |
1432 | * igb_set_pcie_completion_timeout - set pci-e completion timeout | |
1433 | * @hw: pointer to the HW structure | |
1434 | * | |
1435 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, | |
1436 | * however the hardware default for these parts is 500us to 1ms which is less | |
1437 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
1438 | * increase the value to either 10ms to 200ms for capability version 1 config, | |
1439 | * or 16ms to 55ms for version 2. | |
1440 | **/ | |
1441 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) | |
1442 | { | |
1443 | u32 gcr = rd32(E1000_GCR); | |
1444 | s32 ret_val = 0; | |
1445 | u16 pcie_devctl2; | |
1446 | ||
1447 | /* only take action if timeout value is defaulted to 0 */ | |
1448 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) | |
1449 | goto out; | |
1450 | ||
1451 | /* | |
1452 | * if capababilities version is type 1 we can write the | |
1453 | * timeout of 10ms to 200ms through the GCR register | |
1454 | */ | |
1455 | if (!(gcr & E1000_GCR_CAP_VER2)) { | |
1456 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; | |
1457 | goto out; | |
1458 | } | |
1459 | ||
1460 | /* | |
1461 | * for version 2 capabilities we need to write the config space | |
1462 | * directly in order to set the completion timeout value for | |
1463 | * 16ms to 55ms | |
1464 | */ | |
1465 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1466 | &pcie_devctl2); | |
1467 | if (ret_val) | |
1468 | goto out; | |
1469 | ||
1470 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; | |
1471 | ||
1472 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1473 | &pcie_devctl2); | |
1474 | out: | |
1475 | /* disable completion timeout resend */ | |
1476 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; | |
1477 | ||
1478 | wr32(E1000_GCR, gcr); | |
1479 | return ret_val; | |
1480 | } | |
1481 | ||
13800469 GR |
1482 | /** |
1483 | * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing | |
1484 | * @hw: pointer to the hardware struct | |
1485 | * @enable: state to enter, either enabled or disabled | |
1486 | * @pf: Physical Function pool - do not set anti-spoofing for the PF | |
1487 | * | |
1488 | * enables/disables L2 switch anti-spoofing functionality. | |
1489 | **/ | |
1490 | void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) | |
1491 | { | |
1492 | u32 dtxswc; | |
1493 | ||
1494 | switch (hw->mac.type) { | |
1495 | case e1000_82576: | |
1496 | case e1000_i350: | |
1497 | dtxswc = rd32(E1000_DTXSWC); | |
1498 | if (enable) { | |
1499 | dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | | |
1500 | E1000_DTXSWC_VLAN_SPOOF_MASK); | |
1501 | /* The PF can spoof - it has to in order to | |
1502 | * support emulation mode NICs */ | |
1503 | dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); | |
1504 | } else { | |
1505 | dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | | |
1506 | E1000_DTXSWC_VLAN_SPOOF_MASK); | |
1507 | } | |
1508 | wr32(E1000_DTXSWC, dtxswc); | |
1509 | break; | |
1510 | default: | |
1511 | break; | |
1512 | } | |
1513 | } | |
1514 | ||
4ae196df AD |
1515 | /** |
1516 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback | |
1517 | * @hw: pointer to the hardware struct | |
1518 | * @enable: state to enter, either enabled or disabled | |
1519 | * | |
1520 | * enables/disables L2 switch loopback functionality. | |
1521 | **/ | |
1522 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) | |
1523 | { | |
1524 | u32 dtxswc = rd32(E1000_DTXSWC); | |
1525 | ||
1526 | if (enable) | |
1527 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1528 | else | |
1529 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1530 | ||
1531 | wr32(E1000_DTXSWC, dtxswc); | |
1532 | } | |
1533 | ||
1534 | /** | |
1535 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication | |
1536 | * @hw: pointer to the hardware struct | |
1537 | * @enable: state to enter, either enabled or disabled | |
1538 | * | |
1539 | * enables/disables replication of packets across multiple pools. | |
1540 | **/ | |
1541 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) | |
1542 | { | |
1543 | u32 vt_ctl = rd32(E1000_VT_CTL); | |
1544 | ||
1545 | if (enable) | |
1546 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; | |
1547 | else | |
1548 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; | |
1549 | ||
1550 | wr32(E1000_VT_CTL, vt_ctl); | |
1551 | } | |
1552 | ||
bb2ac47b AD |
1553 | /** |
1554 | * igb_read_phy_reg_82580 - Read 82580 MDI control register | |
1555 | * @hw: pointer to the HW structure | |
1556 | * @offset: register offset to be read | |
1557 | * @data: pointer to the read data | |
1558 | * | |
1559 | * Reads the MDI control register in the PHY at offset and stores the | |
1560 | * information read to data. | |
1561 | **/ | |
1562 | static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) | |
1563 | { | |
bb2ac47b AD |
1564 | s32 ret_val; |
1565 | ||
1566 | ||
1567 | ret_val = hw->phy.ops.acquire(hw); | |
1568 | if (ret_val) | |
1569 | goto out; | |
1570 | ||
bb2ac47b AD |
1571 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); |
1572 | ||
1573 | hw->phy.ops.release(hw); | |
1574 | ||
1575 | out: | |
1576 | return ret_val; | |
1577 | } | |
1578 | ||
1579 | /** | |
1580 | * igb_write_phy_reg_82580 - Write 82580 MDI control register | |
1581 | * @hw: pointer to the HW structure | |
1582 | * @offset: register offset to write to | |
1583 | * @data: data to write to register at offset | |
1584 | * | |
1585 | * Writes data to MDI control register in the PHY at offset. | |
1586 | **/ | |
1587 | static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) | |
1588 | { | |
bb2ac47b AD |
1589 | s32 ret_val; |
1590 | ||
1591 | ||
1592 | ret_val = hw->phy.ops.acquire(hw); | |
1593 | if (ret_val) | |
1594 | goto out; | |
1595 | ||
bb2ac47b AD |
1596 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); |
1597 | ||
1598 | hw->phy.ops.release(hw); | |
1599 | ||
1600 | out: | |
1601 | return ret_val; | |
1602 | } | |
1603 | ||
08451e25 NN |
1604 | /** |
1605 | * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits | |
1606 | * @hw: pointer to the HW structure | |
1607 | * | |
1608 | * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on | |
1609 | * the values found in the EEPROM. This addresses an issue in which these | |
1610 | * bits are not restored from EEPROM after reset. | |
1611 | **/ | |
1612 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) | |
1613 | { | |
1614 | s32 ret_val = 0; | |
1615 | u32 mdicnfg; | |
1b5dda33 | 1616 | u16 nvm_data = 0; |
08451e25 NN |
1617 | |
1618 | if (hw->mac.type != e1000_82580) | |
1619 | goto out; | |
1620 | if (!igb_sgmii_active_82575(hw)) | |
1621 | goto out; | |
1622 | ||
1623 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | |
1624 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
1625 | &nvm_data); | |
1626 | if (ret_val) { | |
1627 | hw_dbg("NVM Read Error\n"); | |
1628 | goto out; | |
1629 | } | |
1630 | ||
1631 | mdicnfg = rd32(E1000_MDICNFG); | |
1632 | if (nvm_data & NVM_WORD24_EXT_MDIO) | |
1633 | mdicnfg |= E1000_MDICNFG_EXT_MDIO; | |
1634 | if (nvm_data & NVM_WORD24_COM_MDIO) | |
1635 | mdicnfg |= E1000_MDICNFG_COM_MDIO; | |
1636 | wr32(E1000_MDICNFG, mdicnfg); | |
1637 | out: | |
1638 | return ret_val; | |
1639 | } | |
1640 | ||
bb2ac47b AD |
1641 | /** |
1642 | * igb_reset_hw_82580 - Reset hardware | |
1643 | * @hw: pointer to the HW structure | |
1644 | * | |
1645 | * This resets function or entire device (all ports, etc.) | |
1646 | * to a known state. | |
1647 | **/ | |
1648 | static s32 igb_reset_hw_82580(struct e1000_hw *hw) | |
1649 | { | |
1650 | s32 ret_val = 0; | |
1651 | /* BH SW mailbox bit in SW_FW_SYNC */ | |
1652 | u16 swmbsw_mask = E1000_SW_SYNCH_MB; | |
1653 | u32 ctrl, icr; | |
1654 | bool global_device_reset = hw->dev_spec._82575.global_device_reset; | |
1655 | ||
1656 | ||
1657 | hw->dev_spec._82575.global_device_reset = false; | |
1658 | ||
1659 | /* Get current control state. */ | |
1660 | ctrl = rd32(E1000_CTRL); | |
1661 | ||
1662 | /* | |
1663 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
1664 | * on the last TLP read/write transaction when MAC is reset. | |
1665 | */ | |
1666 | ret_val = igb_disable_pcie_master(hw); | |
1667 | if (ret_val) | |
1668 | hw_dbg("PCI-E Master disable polling has failed.\n"); | |
1669 | ||
1670 | hw_dbg("Masking off all interrupts\n"); | |
1671 | wr32(E1000_IMC, 0xffffffff); | |
1672 | wr32(E1000_RCTL, 0); | |
1673 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
1674 | wrfl(); | |
1675 | ||
1676 | msleep(10); | |
1677 | ||
1678 | /* Determine whether or not a global dev reset is requested */ | |
1679 | if (global_device_reset && | |
1680 | igb_acquire_swfw_sync_82575(hw, swmbsw_mask)) | |
1681 | global_device_reset = false; | |
1682 | ||
1683 | if (global_device_reset && | |
1684 | !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) | |
1685 | ctrl |= E1000_CTRL_DEV_RST; | |
1686 | else | |
1687 | ctrl |= E1000_CTRL_RST; | |
1688 | ||
1689 | wr32(E1000_CTRL, ctrl); | |
1690 | ||
1691 | /* Add delay to insure DEV_RST has time to complete */ | |
1692 | if (global_device_reset) | |
1693 | msleep(5); | |
1694 | ||
1695 | ret_val = igb_get_auto_rd_done(hw); | |
1696 | if (ret_val) { | |
1697 | /* | |
1698 | * When auto config read does not complete, do not | |
1699 | * return with an error. This can happen in situations | |
1700 | * where there is no eeprom and prevents getting link. | |
1701 | */ | |
1702 | hw_dbg("Auto Read Done did not complete\n"); | |
1703 | } | |
1704 | ||
1705 | /* If EEPROM is not present, run manual init scripts */ | |
1706 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
1707 | igb_reset_init_script_82575(hw); | |
1708 | ||
1709 | /* clear global device reset status bit */ | |
1710 | wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); | |
1711 | ||
1712 | /* Clear any pending interrupt events. */ | |
1713 | wr32(E1000_IMC, 0xffffffff); | |
1714 | icr = rd32(E1000_ICR); | |
1715 | ||
08451e25 NN |
1716 | ret_val = igb_reset_mdicnfg_82580(hw); |
1717 | if (ret_val) | |
1718 | hw_dbg("Could not reset MDICNFG based on EEPROM\n"); | |
1719 | ||
bb2ac47b AD |
1720 | /* Install any alternate MAC address into RAR0 */ |
1721 | ret_val = igb_check_alt_mac_addr(hw); | |
1722 | ||
1723 | /* Release semaphore */ | |
1724 | if (global_device_reset) | |
1725 | igb_release_swfw_sync_82575(hw, swmbsw_mask); | |
1726 | ||
1727 | return ret_val; | |
1728 | } | |
1729 | ||
1730 | /** | |
1731 | * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size | |
1732 | * @data: data received by reading RXPBS register | |
1733 | * | |
1734 | * The 82580 uses a table based approach for packet buffer allocation sizes. | |
1735 | * This function converts the retrieved value into the correct table value | |
1736 | * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 | |
1737 | * 0x0 36 72 144 1 2 4 8 16 | |
1738 | * 0x8 35 70 140 rsv rsv rsv rsv rsv | |
1739 | */ | |
1740 | u16 igb_rxpbs_adjust_82580(u32 data) | |
1741 | { | |
1742 | u16 ret_val = 0; | |
1743 | ||
1744 | if (data < E1000_82580_RXPBS_TABLE_SIZE) | |
1745 | ret_val = e1000_82580_rxpbs_table[data]; | |
1746 | ||
1747 | return ret_val; | |
1748 | } | |
1749 | ||
9d5c8243 | 1750 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
9d5c8243 AK |
1751 | .init_hw = igb_init_hw_82575, |
1752 | .check_for_link = igb_check_for_link_82575, | |
2d064c06 | 1753 | .rar_set = igb_rar_set, |
9d5c8243 AK |
1754 | .read_mac_addr = igb_read_mac_addr_82575, |
1755 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | |
1756 | }; | |
1757 | ||
1758 | static struct e1000_phy_operations e1000_phy_ops_82575 = { | |
a8d2a0c2 | 1759 | .acquire = igb_acquire_phy_82575, |
9d5c8243 | 1760 | .get_cfg_done = igb_get_cfg_done_82575, |
a8d2a0c2 | 1761 | .release = igb_release_phy_82575, |
9d5c8243 AK |
1762 | }; |
1763 | ||
1764 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { | |
312c75ae AD |
1765 | .acquire = igb_acquire_nvm_82575, |
1766 | .read = igb_read_nvm_eerd, | |
1767 | .release = igb_release_nvm_82575, | |
1768 | .write = igb_write_nvm_spi, | |
9d5c8243 AK |
1769 | }; |
1770 | ||
1771 | const struct e1000_info e1000_82575_info = { | |
1772 | .get_invariants = igb_get_invariants_82575, | |
1773 | .mac_ops = &e1000_mac_ops_82575, | |
1774 | .phy_ops = &e1000_phy_ops_82575, | |
1775 | .nvm_ops = &e1000_nvm_ops_82575, | |
1776 | }; | |
1777 |