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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* e1000_82575 | |
29 | * e1000_82576 | |
30 | */ | |
31 | ||
32 | #include <linux/types.h> | |
33 | #include <linux/slab.h> | |
2d064c06 | 34 | #include <linux/if_ether.h> |
9d5c8243 AK |
35 | |
36 | #include "e1000_mac.h" | |
37 | #include "e1000_82575.h" | |
38 | ||
39 | static s32 igb_get_invariants_82575(struct e1000_hw *); | |
40 | static s32 igb_acquire_phy_82575(struct e1000_hw *); | |
41 | static void igb_release_phy_82575(struct e1000_hw *); | |
42 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); | |
43 | static void igb_release_nvm_82575(struct e1000_hw *); | |
44 | static s32 igb_check_for_link_82575(struct e1000_hw *); | |
45 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |
46 | static s32 igb_init_hw_82575(struct e1000_hw *); | |
47 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | |
48 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | |
bb2ac47b AD |
49 | static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); |
50 | static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); | |
9d5c8243 | 51 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
bb2ac47b | 52 | static s32 igb_reset_hw_82580(struct e1000_hw *); |
9d5c8243 AK |
53 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
54 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | |
2fb02a26 | 55 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *); |
9d5c8243 AK |
56 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
57 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); | |
58 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); | |
9d5c8243 AK |
59 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
60 | u16 *); | |
61 | static s32 igb_get_phy_id_82575(struct e1000_hw *); | |
62 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); | |
63 | static bool igb_sgmii_active_82575(struct e1000_hw *); | |
64 | static s32 igb_reset_init_script_82575(struct e1000_hw *); | |
65 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); | |
009bc06e | 66 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
9d5c8243 | 67 | |
bb2ac47b AD |
68 | static const u16 e1000_82580_rxpbs_table[] = |
69 | { 36, 72, 144, 1, 2, 4, 8, 16, | |
70 | 35, 70, 140 }; | |
71 | #define E1000_82580_RXPBS_TABLE_SIZE \ | |
72 | (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) | |
73 | ||
9d5c8243 AK |
74 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
75 | { | |
76 | struct e1000_phy_info *phy = &hw->phy; | |
77 | struct e1000_nvm_info *nvm = &hw->nvm; | |
78 | struct e1000_mac_info *mac = &hw->mac; | |
c1889bfe | 79 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
9d5c8243 AK |
80 | u32 eecd; |
81 | s32 ret_val; | |
82 | u16 size; | |
83 | u32 ctrl_ext = 0; | |
84 | ||
85 | switch (hw->device_id) { | |
86 | case E1000_DEV_ID_82575EB_COPPER: | |
87 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
88 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
89 | mac->type = e1000_82575; | |
90 | break; | |
2d064c06 | 91 | case E1000_DEV_ID_82576: |
9eb2341d | 92 | case E1000_DEV_ID_82576_NS: |
747d49ba | 93 | case E1000_DEV_ID_82576_NS_SERDES: |
2d064c06 AD |
94 | case E1000_DEV_ID_82576_FIBER: |
95 | case E1000_DEV_ID_82576_SERDES: | |
c8ea5ea9 | 96 | case E1000_DEV_ID_82576_QUAD_COPPER: |
4703bf73 | 97 | case E1000_DEV_ID_82576_SERDES_QUAD: |
2d064c06 AD |
98 | mac->type = e1000_82576; |
99 | break; | |
bb2ac47b AD |
100 | case E1000_DEV_ID_82580_COPPER: |
101 | case E1000_DEV_ID_82580_FIBER: | |
102 | case E1000_DEV_ID_82580_SERDES: | |
103 | case E1000_DEV_ID_82580_SGMII: | |
104 | case E1000_DEV_ID_82580_COPPER_DUAL: | |
105 | mac->type = e1000_82580; | |
106 | break; | |
9d5c8243 AK |
107 | default: |
108 | return -E1000_ERR_MAC_INIT; | |
109 | break; | |
110 | } | |
111 | ||
9d5c8243 AK |
112 | /* Set media type */ |
113 | /* | |
114 | * The 82575 uses bits 22:23 for link mode. The mode can be changed | |
115 | * based on the EEPROM. We cannot rely upon device ID. There | |
116 | * is no distinguishable difference between fiber and internal | |
117 | * SerDes mode on the 82575. There can be an external PHY attached | |
118 | * on the SGMII interface. For this, we'll set sgmii_active to true. | |
119 | */ | |
120 | phy->media_type = e1000_media_type_copper; | |
121 | dev_spec->sgmii_active = false; | |
122 | ||
123 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
2fb02a26 AD |
124 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
125 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
9d5c8243 AK |
126 | dev_spec->sgmii_active = true; |
127 | ctrl_ext |= E1000_CTRL_I2C_ENA; | |
2fb02a26 | 128 | break; |
bb2ac47b | 129 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
2fb02a26 AD |
130 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: |
131 | hw->phy.media_type = e1000_media_type_internal_serdes; | |
132 | ctrl_ext |= E1000_CTRL_I2C_ENA; | |
133 | break; | |
134 | default: | |
9d5c8243 | 135 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
2fb02a26 | 136 | break; |
9d5c8243 | 137 | } |
2fb02a26 | 138 | |
9d5c8243 AK |
139 | wr32(E1000_CTRL_EXT, ctrl_ext); |
140 | ||
bb2ac47b AD |
141 | /* |
142 | * if using i2c make certain the MDICNFG register is cleared to prevent | |
143 | * communications from being misrouted to the mdic registers | |
144 | */ | |
145 | if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580)) | |
146 | wr32(E1000_MDICNFG, 0); | |
147 | ||
9d5c8243 AK |
148 | /* Set mta register count */ |
149 | mac->mta_reg_count = 128; | |
150 | /* Set rar entry count */ | |
151 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | |
2d064c06 AD |
152 | if (mac->type == e1000_82576) |
153 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | |
bb2ac47b AD |
154 | if (mac->type == e1000_82580) |
155 | mac->rar_entry_count = E1000_RAR_ENTRIES_82580; | |
156 | /* reset */ | |
157 | if (mac->type == e1000_82580) | |
158 | mac->ops.reset_hw = igb_reset_hw_82580; | |
159 | else | |
160 | mac->ops.reset_hw = igb_reset_hw_82575; | |
9d5c8243 AK |
161 | /* Set if part includes ASF firmware */ |
162 | mac->asf_firmware_present = true; | |
163 | /* Set if manageability features are enabled. */ | |
164 | mac->arc_subsystem_valid = | |
165 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) | |
166 | ? true : false; | |
167 | ||
168 | /* physical interface link setup */ | |
169 | mac->ops.setup_physical_interface = | |
170 | (hw->phy.media_type == e1000_media_type_copper) | |
171 | ? igb_setup_copper_link_82575 | |
2fb02a26 | 172 | : igb_setup_serdes_link_82575; |
9d5c8243 AK |
173 | |
174 | /* NVM initialization */ | |
175 | eecd = rd32(E1000_EECD); | |
176 | ||
177 | nvm->opcode_bits = 8; | |
178 | nvm->delay_usec = 1; | |
179 | switch (nvm->override) { | |
180 | case e1000_nvm_override_spi_large: | |
181 | nvm->page_size = 32; | |
182 | nvm->address_bits = 16; | |
183 | break; | |
184 | case e1000_nvm_override_spi_small: | |
185 | nvm->page_size = 8; | |
186 | nvm->address_bits = 8; | |
187 | break; | |
188 | default: | |
189 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
190 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
191 | break; | |
192 | } | |
193 | ||
194 | nvm->type = e1000_nvm_eeprom_spi; | |
195 | ||
196 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
197 | E1000_EECD_SIZE_EX_SHIFT); | |
198 | ||
199 | /* | |
200 | * Added to a constant, "size" becomes the left-shift value | |
201 | * for setting word_size. | |
202 | */ | |
203 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
5c3cad75 JK |
204 | |
205 | /* EEPROM access above 16k is unsupported */ | |
206 | if (size > 14) | |
207 | size = 14; | |
9d5c8243 AK |
208 | nvm->word_size = 1 << size; |
209 | ||
a0c98605 AD |
210 | /* if 82576 then initialize mailbox parameters */ |
211 | if (mac->type == e1000_82576) | |
212 | igb_init_mbx_params_pf(hw); | |
213 | ||
9d5c8243 AK |
214 | /* setup PHY parameters */ |
215 | if (phy->media_type != e1000_media_type_copper) { | |
216 | phy->type = e1000_phy_none; | |
217 | return 0; | |
218 | } | |
219 | ||
220 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
221 | phy->reset_delay_us = 100; | |
222 | ||
223 | /* PHY function pointers */ | |
224 | if (igb_sgmii_active_82575(hw)) { | |
a8d2a0c2 AD |
225 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
226 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; | |
227 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; | |
bb2ac47b AD |
228 | } else if (hw->mac.type == e1000_82580) { |
229 | phy->ops.reset = igb_phy_hw_reset; | |
230 | phy->ops.read_reg = igb_read_phy_reg_82580; | |
231 | phy->ops.write_reg = igb_write_phy_reg_82580; | |
9d5c8243 | 232 | } else { |
a8d2a0c2 AD |
233 | phy->ops.reset = igb_phy_hw_reset; |
234 | phy->ops.read_reg = igb_read_phy_reg_igp; | |
235 | phy->ops.write_reg = igb_write_phy_reg_igp; | |
9d5c8243 AK |
236 | } |
237 | ||
19e588e7 AD |
238 | /* set lan id */ |
239 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> | |
240 | E1000_STATUS_FUNC_SHIFT; | |
241 | ||
9d5c8243 AK |
242 | /* Set phy->phy_addr and phy->id. */ |
243 | ret_val = igb_get_phy_id_82575(hw); | |
244 | if (ret_val) | |
245 | return ret_val; | |
246 | ||
247 | /* Verify phy id and set remaining function pointers */ | |
248 | switch (phy->id) { | |
249 | case M88E1111_I_PHY_ID: | |
250 | phy->type = e1000_phy_m88; | |
251 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
252 | phy->ops.get_cable_length = igb_get_cable_length_m88; | |
253 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; | |
254 | break; | |
255 | case IGP03E1000_E_PHY_ID: | |
256 | phy->type = e1000_phy_igp_3; | |
257 | phy->ops.get_phy_info = igb_get_phy_info_igp; | |
258 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; | |
259 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; | |
260 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; | |
261 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; | |
262 | break; | |
bb2ac47b AD |
263 | case I82580_I_PHY_ID: |
264 | phy->type = e1000_phy_82580; | |
265 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580; | |
266 | phy->ops.get_cable_length = igb_get_cable_length_82580; | |
267 | phy->ops.get_phy_info = igb_get_phy_info_82580; | |
268 | break; | |
9d5c8243 AK |
269 | default: |
270 | return -E1000_ERR_PHY; | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | /** | |
733596be | 277 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
9d5c8243 AK |
278 | * @hw: pointer to the HW structure |
279 | * | |
280 | * Acquire access rights to the correct PHY. This is a | |
281 | * function pointer entry point called by the api module. | |
282 | **/ | |
283 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) | |
284 | { | |
008c3422 | 285 | u16 mask = E1000_SWFW_PHY0_SM; |
9d5c8243 | 286 | |
008c3422 AD |
287 | if (hw->bus.func == E1000_FUNC_1) |
288 | mask = E1000_SWFW_PHY1_SM; | |
9d5c8243 AK |
289 | |
290 | return igb_acquire_swfw_sync_82575(hw, mask); | |
291 | } | |
292 | ||
293 | /** | |
733596be | 294 | * igb_release_phy_82575 - Release rights to access PHY |
9d5c8243 AK |
295 | * @hw: pointer to the HW structure |
296 | * | |
297 | * A wrapper to release access rights to the correct PHY. This is a | |
298 | * function pointer entry point called by the api module. | |
299 | **/ | |
300 | static void igb_release_phy_82575(struct e1000_hw *hw) | |
301 | { | |
008c3422 AD |
302 | u16 mask = E1000_SWFW_PHY0_SM; |
303 | ||
304 | if (hw->bus.func == E1000_FUNC_1) | |
305 | mask = E1000_SWFW_PHY1_SM; | |
9d5c8243 | 306 | |
9d5c8243 AK |
307 | igb_release_swfw_sync_82575(hw, mask); |
308 | } | |
309 | ||
310 | /** | |
733596be | 311 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
9d5c8243 AK |
312 | * @hw: pointer to the HW structure |
313 | * @offset: register offset to be read | |
314 | * @data: pointer to the read data | |
315 | * | |
316 | * Reads the PHY register at offset using the serial gigabit media independent | |
317 | * interface and stores the retrieved information in data. | |
318 | **/ | |
319 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
320 | u16 *data) | |
321 | { | |
bf6f7a92 | 322 | s32 ret_val = -E1000_ERR_PARAM; |
9d5c8243 AK |
323 | |
324 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 325 | hw_dbg("PHY Address %u is out of range\n", offset); |
bf6f7a92 | 326 | goto out; |
9d5c8243 AK |
327 | } |
328 | ||
bf6f7a92 AD |
329 | ret_val = hw->phy.ops.acquire(hw); |
330 | if (ret_val) | |
331 | goto out; | |
9d5c8243 | 332 | |
bf6f7a92 | 333 | ret_val = igb_read_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 334 | |
bf6f7a92 AD |
335 | hw->phy.ops.release(hw); |
336 | ||
337 | out: | |
338 | return ret_val; | |
9d5c8243 AK |
339 | } |
340 | ||
341 | /** | |
733596be | 342 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
9d5c8243 AK |
343 | * @hw: pointer to the HW structure |
344 | * @offset: register offset to write to | |
345 | * @data: data to write at register offset | |
346 | * | |
347 | * Writes the data to PHY register at the offset using the serial gigabit | |
348 | * media independent interface. | |
349 | **/ | |
350 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
351 | u16 data) | |
352 | { | |
bf6f7a92 AD |
353 | s32 ret_val = -E1000_ERR_PARAM; |
354 | ||
9d5c8243 AK |
355 | |
356 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 357 | hw_dbg("PHY Address %d is out of range\n", offset); |
bf6f7a92 | 358 | goto out; |
9d5c8243 AK |
359 | } |
360 | ||
bf6f7a92 AD |
361 | ret_val = hw->phy.ops.acquire(hw); |
362 | if (ret_val) | |
363 | goto out; | |
9d5c8243 | 364 | |
bf6f7a92 | 365 | ret_val = igb_write_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 366 | |
bf6f7a92 AD |
367 | hw->phy.ops.release(hw); |
368 | ||
369 | out: | |
370 | return ret_val; | |
9d5c8243 AK |
371 | } |
372 | ||
373 | /** | |
733596be | 374 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
9d5c8243 AK |
375 | * @hw: pointer to the HW structure |
376 | * | |
652fff32 | 377 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
9d5c8243 AK |
378 | * sgmi interface. |
379 | **/ | |
380 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) | |
381 | { | |
382 | struct e1000_phy_info *phy = &hw->phy; | |
383 | s32 ret_val = 0; | |
384 | u16 phy_id; | |
2fb02a26 | 385 | u32 ctrl_ext; |
9d5c8243 AK |
386 | |
387 | /* | |
388 | * For SGMII PHYs, we try the list of possible addresses until | |
389 | * we find one that works. For non-SGMII PHYs | |
390 | * (e.g. integrated copper PHYs), an address of 1 should | |
391 | * work. The result of this function should mean phy->phy_addr | |
392 | * and phy->id are set correctly. | |
393 | */ | |
394 | if (!(igb_sgmii_active_82575(hw))) { | |
395 | phy->addr = 1; | |
396 | ret_val = igb_get_phy_id(hw); | |
397 | goto out; | |
398 | } | |
399 | ||
2fb02a26 AD |
400 | /* Power on sgmii phy if it is disabled */ |
401 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
402 | wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); | |
403 | wrfl(); | |
404 | msleep(300); | |
405 | ||
9d5c8243 AK |
406 | /* |
407 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. | |
408 | * Therefore, we need to test 1-7 | |
409 | */ | |
410 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { | |
411 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); | |
412 | if (ret_val == 0) { | |
652fff32 AK |
413 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
414 | phy_id, phy->addr); | |
9d5c8243 AK |
415 | /* |
416 | * At the time of this writing, The M88 part is | |
417 | * the only supported SGMII PHY product. | |
418 | */ | |
419 | if (phy_id == M88_VENDOR) | |
420 | break; | |
421 | } else { | |
652fff32 | 422 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
9d5c8243 AK |
423 | } |
424 | } | |
425 | ||
426 | /* A valid PHY type couldn't be found. */ | |
427 | if (phy->addr == 8) { | |
428 | phy->addr = 0; | |
429 | ret_val = -E1000_ERR_PHY; | |
430 | goto out; | |
2fb02a26 AD |
431 | } else { |
432 | ret_val = igb_get_phy_id(hw); | |
9d5c8243 AK |
433 | } |
434 | ||
2fb02a26 AD |
435 | /* restore previous sfp cage power state */ |
436 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
9d5c8243 AK |
437 | |
438 | out: | |
439 | return ret_val; | |
440 | } | |
441 | ||
442 | /** | |
733596be | 443 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
9d5c8243 AK |
444 | * @hw: pointer to the HW structure |
445 | * | |
446 | * Resets the PHY using the serial gigabit media independent interface. | |
447 | **/ | |
448 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) | |
449 | { | |
450 | s32 ret_val; | |
451 | ||
452 | /* | |
453 | * This isn't a true "hard" reset, but is the only reset | |
454 | * available to us at this time. | |
455 | */ | |
456 | ||
652fff32 | 457 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
9d5c8243 AK |
458 | |
459 | /* | |
460 | * SFP documentation requires the following to configure the SPF module | |
461 | * to work on SGMII. No further documentation is given. | |
462 | */ | |
a8d2a0c2 | 463 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
9d5c8243 AK |
464 | if (ret_val) |
465 | goto out; | |
466 | ||
467 | ret_val = igb_phy_sw_reset(hw); | |
468 | ||
469 | out: | |
470 | return ret_val; | |
471 | } | |
472 | ||
473 | /** | |
733596be | 474 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
9d5c8243 AK |
475 | * @hw: pointer to the HW structure |
476 | * @active: true to enable LPLU, false to disable | |
477 | * | |
478 | * Sets the LPLU D0 state according to the active flag. When | |
479 | * activating LPLU this function also disables smart speed | |
480 | * and vice versa. LPLU will not be activated unless the | |
481 | * device autonegotiation advertisement meets standards of | |
482 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
483 | * This is a function pointer entry point only called by | |
484 | * PHY setup routines. | |
485 | **/ | |
486 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) | |
487 | { | |
488 | struct e1000_phy_info *phy = &hw->phy; | |
489 | s32 ret_val; | |
490 | u16 data; | |
491 | ||
a8d2a0c2 | 492 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
493 | if (ret_val) |
494 | goto out; | |
495 | ||
496 | if (active) { | |
497 | data |= IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 498 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 499 | data); |
9d5c8243 AK |
500 | if (ret_val) |
501 | goto out; | |
502 | ||
503 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 504 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 505 | &data); |
9d5c8243 | 506 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
a8d2a0c2 | 507 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 508 | data); |
9d5c8243 AK |
509 | if (ret_val) |
510 | goto out; | |
511 | } else { | |
512 | data &= ~IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 513 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 514 | data); |
9d5c8243 AK |
515 | /* |
516 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
517 | * during Dx states where the power conservation is most | |
518 | * important. During driver activity we should enable | |
519 | * SmartSpeed, so performance is maintained. | |
520 | */ | |
521 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 522 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 523 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
524 | if (ret_val) |
525 | goto out; | |
526 | ||
527 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 528 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 529 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
530 | if (ret_val) |
531 | goto out; | |
532 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 533 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 534 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
535 | if (ret_val) |
536 | goto out; | |
537 | ||
538 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 539 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 540 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
541 | if (ret_val) |
542 | goto out; | |
543 | } | |
544 | } | |
545 | ||
546 | out: | |
547 | return ret_val; | |
548 | } | |
549 | ||
550 | /** | |
733596be | 551 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
9d5c8243 AK |
552 | * @hw: pointer to the HW structure |
553 | * | |
652fff32 | 554 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
9d5c8243 AK |
555 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
556 | * Return successful if access grant bit set, else clear the request for | |
557 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
558 | **/ | |
559 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) | |
560 | { | |
561 | s32 ret_val; | |
562 | ||
563 | ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
564 | if (ret_val) | |
565 | goto out; | |
566 | ||
567 | ret_val = igb_acquire_nvm(hw); | |
568 | ||
569 | if (ret_val) | |
570 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
571 | ||
572 | out: | |
573 | return ret_val; | |
574 | } | |
575 | ||
576 | /** | |
733596be | 577 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
9d5c8243 AK |
578 | * @hw: pointer to the HW structure |
579 | * | |
580 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, | |
581 | * then release the semaphores acquired. | |
582 | **/ | |
583 | static void igb_release_nvm_82575(struct e1000_hw *hw) | |
584 | { | |
585 | igb_release_nvm(hw); | |
586 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
587 | } | |
588 | ||
589 | /** | |
733596be | 590 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
9d5c8243 AK |
591 | * @hw: pointer to the HW structure |
592 | * @mask: specifies which semaphore to acquire | |
593 | * | |
594 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
595 | * will also specify which port we're acquiring the lock for. | |
596 | **/ | |
597 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
598 | { | |
599 | u32 swfw_sync; | |
600 | u32 swmask = mask; | |
601 | u32 fwmask = mask << 16; | |
602 | s32 ret_val = 0; | |
603 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | |
604 | ||
605 | while (i < timeout) { | |
606 | if (igb_get_hw_semaphore(hw)) { | |
607 | ret_val = -E1000_ERR_SWFW_SYNC; | |
608 | goto out; | |
609 | } | |
610 | ||
611 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
612 | if (!(swfw_sync & (fwmask | swmask))) | |
613 | break; | |
614 | ||
615 | /* | |
616 | * Firmware currently using resource (fwmask) | |
617 | * or other software thread using resource (swmask) | |
618 | */ | |
619 | igb_put_hw_semaphore(hw); | |
620 | mdelay(5); | |
621 | i++; | |
622 | } | |
623 | ||
624 | if (i == timeout) { | |
652fff32 | 625 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
9d5c8243 AK |
626 | ret_val = -E1000_ERR_SWFW_SYNC; |
627 | goto out; | |
628 | } | |
629 | ||
630 | swfw_sync |= swmask; | |
631 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
632 | ||
633 | igb_put_hw_semaphore(hw); | |
634 | ||
635 | out: | |
636 | return ret_val; | |
637 | } | |
638 | ||
639 | /** | |
733596be | 640 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
9d5c8243 AK |
641 | * @hw: pointer to the HW structure |
642 | * @mask: specifies which semaphore to acquire | |
643 | * | |
644 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
645 | * will also specify which port we're releasing the lock for. | |
646 | **/ | |
647 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
648 | { | |
649 | u32 swfw_sync; | |
650 | ||
651 | while (igb_get_hw_semaphore(hw) != 0); | |
652 | /* Empty */ | |
653 | ||
654 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
655 | swfw_sync &= ~mask; | |
656 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
657 | ||
658 | igb_put_hw_semaphore(hw); | |
659 | } | |
660 | ||
661 | /** | |
733596be | 662 | * igb_get_cfg_done_82575 - Read config done bit |
9d5c8243 AK |
663 | * @hw: pointer to the HW structure |
664 | * | |
665 | * Read the management control register for the config done bit for | |
666 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
667 | * to read the config done bit, so an error is *ONLY* logged and returns | |
668 | * 0. If we were to return with error, EEPROM-less silicon | |
669 | * would not be able to be reset or change link. | |
670 | **/ | |
671 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) | |
672 | { | |
673 | s32 timeout = PHY_CFG_TIMEOUT; | |
674 | s32 ret_val = 0; | |
675 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
676 | ||
677 | if (hw->bus.func == 1) | |
678 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
bb2ac47b AD |
679 | else if (hw->bus.func == E1000_FUNC_2) |
680 | mask = E1000_NVM_CFG_DONE_PORT_2; | |
681 | else if (hw->bus.func == E1000_FUNC_3) | |
682 | mask = E1000_NVM_CFG_DONE_PORT_3; | |
9d5c8243 AK |
683 | |
684 | while (timeout) { | |
685 | if (rd32(E1000_EEMNGCTL) & mask) | |
686 | break; | |
687 | msleep(1); | |
688 | timeout--; | |
689 | } | |
690 | if (!timeout) | |
652fff32 | 691 | hw_dbg("MNG configuration cycle has not completed.\n"); |
9d5c8243 AK |
692 | |
693 | /* If EEPROM is not marked present, init the PHY manually */ | |
694 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && | |
695 | (hw->phy.type == e1000_phy_igp_3)) | |
696 | igb_phy_init_script_igp3(hw); | |
697 | ||
698 | return ret_val; | |
699 | } | |
700 | ||
701 | /** | |
733596be | 702 | * igb_check_for_link_82575 - Check for link |
9d5c8243 AK |
703 | * @hw: pointer to the HW structure |
704 | * | |
705 | * If sgmii is enabled, then use the pcs register to determine link, otherwise | |
706 | * use the generic interface for determining link. | |
707 | **/ | |
708 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |
709 | { | |
710 | s32 ret_val; | |
711 | u16 speed, duplex; | |
712 | ||
70d92f86 | 713 | if (hw->phy.media_type != e1000_media_type_copper) { |
9d5c8243 | 714 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
2d064c06 | 715 | &duplex); |
5d0932a5 AD |
716 | /* |
717 | * Use this flag to determine if link needs to be checked or | |
718 | * not. If we have link clear the flag so that we do not | |
719 | * continue to check for link. | |
720 | */ | |
721 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | |
722 | } else { | |
9d5c8243 | 723 | ret_val = igb_check_for_copper_link(hw); |
5d0932a5 | 724 | } |
9d5c8243 AK |
725 | |
726 | return ret_val; | |
727 | } | |
70d92f86 | 728 | |
9d5c8243 | 729 | /** |
733596be | 730 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
9d5c8243 AK |
731 | * @hw: pointer to the HW structure |
732 | * @speed: stores the current speed | |
733 | * @duplex: stores the current duplex | |
734 | * | |
652fff32 | 735 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
9d5c8243 AK |
736 | * duplex, then store the values in the pointers provided. |
737 | **/ | |
738 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |
739 | u16 *duplex) | |
740 | { | |
741 | struct e1000_mac_info *mac = &hw->mac; | |
742 | u32 pcs; | |
743 | ||
744 | /* Set up defaults for the return values of this function */ | |
745 | mac->serdes_has_link = false; | |
746 | *speed = 0; | |
747 | *duplex = 0; | |
748 | ||
749 | /* | |
750 | * Read the PCS Status register for link state. For non-copper mode, | |
751 | * the status register is not accurate. The PCS status register is | |
752 | * used instead. | |
753 | */ | |
754 | pcs = rd32(E1000_PCS_LSTAT); | |
755 | ||
756 | /* | |
757 | * The link up bit determines when link is up on autoneg. The sync ok | |
758 | * gets set once both sides sync up and agree upon link. Stable link | |
759 | * can be determined by checking for both link up and link sync ok | |
760 | */ | |
761 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { | |
762 | mac->serdes_has_link = true; | |
763 | ||
764 | /* Detect and store PCS speed */ | |
765 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { | |
766 | *speed = SPEED_1000; | |
767 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { | |
768 | *speed = SPEED_100; | |
769 | } else { | |
770 | *speed = SPEED_10; | |
771 | } | |
772 | ||
773 | /* Detect and store PCS duplex */ | |
774 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { | |
775 | *duplex = FULL_DUPLEX; | |
776 | } else { | |
777 | *duplex = HALF_DUPLEX; | |
778 | } | |
779 | } | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
2d064c06 | 784 | /** |
2fb02a26 | 785 | * igb_shutdown_serdes_link_82575 - Remove link during power down |
9d5c8243 | 786 | * @hw: pointer to the HW structure |
9d5c8243 | 787 | * |
2d064c06 AD |
788 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
789 | * when management pass thru is not enabled. | |
9d5c8243 | 790 | **/ |
2fb02a26 | 791 | void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 792 | { |
2d064c06 AD |
793 | u32 reg; |
794 | ||
53c992fa | 795 | if (hw->phy.media_type != e1000_media_type_internal_serdes && |
2fb02a26 | 796 | igb_sgmii_active_82575(hw)) |
2d064c06 AD |
797 | return; |
798 | ||
53c992fa | 799 | if (!igb_enable_mng_pass_thru(hw)) { |
2d064c06 AD |
800 | /* Disable PCS to turn off link */ |
801 | reg = rd32(E1000_PCS_CFG0); | |
802 | reg &= ~E1000_PCS_CFG_PCS_EN; | |
803 | wr32(E1000_PCS_CFG0, reg); | |
804 | ||
805 | /* shutdown the laser */ | |
806 | reg = rd32(E1000_CTRL_EXT); | |
2fb02a26 | 807 | reg |= E1000_CTRL_EXT_SDP3_DATA; |
2d064c06 AD |
808 | wr32(E1000_CTRL_EXT, reg); |
809 | ||
810 | /* flush the write to verify completion */ | |
811 | wrfl(); | |
812 | msleep(1); | |
813 | } | |
9d5c8243 AK |
814 | } |
815 | ||
816 | /** | |
733596be | 817 | * igb_reset_hw_82575 - Reset hardware |
9d5c8243 AK |
818 | * @hw: pointer to the HW structure |
819 | * | |
820 | * This resets the hardware into a known state. This is a | |
821 | * function pointer entry point called by the api module. | |
822 | **/ | |
823 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) | |
824 | { | |
825 | u32 ctrl, icr; | |
826 | s32 ret_val; | |
827 | ||
828 | /* | |
829 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
830 | * on the last TLP read/write transaction when MAC is reset. | |
831 | */ | |
832 | ret_val = igb_disable_pcie_master(hw); | |
833 | if (ret_val) | |
652fff32 | 834 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
9d5c8243 | 835 | |
009bc06e AD |
836 | /* set the completion timeout for interface */ |
837 | ret_val = igb_set_pcie_completion_timeout(hw); | |
838 | if (ret_val) { | |
839 | hw_dbg("PCI-E Set completion timeout has failed.\n"); | |
840 | } | |
841 | ||
652fff32 | 842 | hw_dbg("Masking off all interrupts\n"); |
9d5c8243 AK |
843 | wr32(E1000_IMC, 0xffffffff); |
844 | ||
845 | wr32(E1000_RCTL, 0); | |
846 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
847 | wrfl(); | |
848 | ||
849 | msleep(10); | |
850 | ||
851 | ctrl = rd32(E1000_CTRL); | |
852 | ||
652fff32 | 853 | hw_dbg("Issuing a global reset to MAC\n"); |
9d5c8243 AK |
854 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
855 | ||
856 | ret_val = igb_get_auto_rd_done(hw); | |
857 | if (ret_val) { | |
858 | /* | |
859 | * When auto config read does not complete, do not | |
860 | * return with an error. This can happen in situations | |
861 | * where there is no eeprom and prevents getting link. | |
862 | */ | |
652fff32 | 863 | hw_dbg("Auto Read Done did not complete\n"); |
9d5c8243 AK |
864 | } |
865 | ||
866 | /* If EEPROM is not present, run manual init scripts */ | |
867 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
868 | igb_reset_init_script_82575(hw); | |
869 | ||
870 | /* Clear any pending interrupt events. */ | |
871 | wr32(E1000_IMC, 0xffffffff); | |
872 | icr = rd32(E1000_ICR); | |
873 | ||
5ac16659 AD |
874 | /* Install any alternate MAC address into RAR0 */ |
875 | ret_val = igb_check_alt_mac_addr(hw); | |
9d5c8243 AK |
876 | |
877 | return ret_val; | |
878 | } | |
879 | ||
880 | /** | |
733596be | 881 | * igb_init_hw_82575 - Initialize hardware |
9d5c8243 AK |
882 | * @hw: pointer to the HW structure |
883 | * | |
884 | * This inits the hardware readying it for operation. | |
885 | **/ | |
886 | static s32 igb_init_hw_82575(struct e1000_hw *hw) | |
887 | { | |
888 | struct e1000_mac_info *mac = &hw->mac; | |
889 | s32 ret_val; | |
890 | u16 i, rar_count = mac->rar_entry_count; | |
891 | ||
892 | /* Initialize identification LED */ | |
893 | ret_val = igb_id_led_init(hw); | |
894 | if (ret_val) { | |
652fff32 | 895 | hw_dbg("Error initializing identification LED\n"); |
9d5c8243 AK |
896 | /* This is not fatal and we should not stop init due to this */ |
897 | } | |
898 | ||
899 | /* Disabling VLAN filtering */ | |
652fff32 | 900 | hw_dbg("Initializing the IEEE VLAN\n"); |
9d5c8243 AK |
901 | igb_clear_vfta(hw); |
902 | ||
903 | /* Setup the receive address */ | |
5ac16659 AD |
904 | igb_init_rx_addrs(hw, rar_count); |
905 | ||
9d5c8243 | 906 | /* Zero out the Multicast HASH table */ |
652fff32 | 907 | hw_dbg("Zeroing the MTA\n"); |
9d5c8243 AK |
908 | for (i = 0; i < mac->mta_reg_count; i++) |
909 | array_wr32(E1000_MTA, i, 0); | |
910 | ||
68d480c4 AD |
911 | /* Zero out the Unicast HASH table */ |
912 | hw_dbg("Zeroing the UTA\n"); | |
913 | for (i = 0; i < mac->uta_reg_count; i++) | |
914 | array_wr32(E1000_UTA, i, 0); | |
915 | ||
9d5c8243 AK |
916 | /* Setup link and flow control */ |
917 | ret_val = igb_setup_link(hw); | |
918 | ||
919 | /* | |
920 | * Clear all of the statistics registers (clear on read). It is | |
921 | * important that we do this after we have tried to establish link | |
922 | * because the symbol error count will increment wildly if there | |
923 | * is no link. | |
924 | */ | |
925 | igb_clear_hw_cntrs_82575(hw); | |
926 | ||
927 | return ret_val; | |
928 | } | |
929 | ||
930 | /** | |
733596be | 931 | * igb_setup_copper_link_82575 - Configure copper link settings |
9d5c8243 AK |
932 | * @hw: pointer to the HW structure |
933 | * | |
934 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
935 | * for link, once link is established calls to configure collision distance | |
936 | * and flow control are called. | |
937 | **/ | |
938 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) | |
939 | { | |
12645a19 | 940 | u32 ctrl; |
9d5c8243 | 941 | s32 ret_val; |
9d5c8243 AK |
942 | |
943 | ctrl = rd32(E1000_CTRL); | |
944 | ctrl |= E1000_CTRL_SLU; | |
945 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
946 | wr32(E1000_CTRL, ctrl); | |
947 | ||
2fb02a26 AD |
948 | ret_val = igb_setup_serdes_link_82575(hw); |
949 | if (ret_val) | |
950 | goto out; | |
951 | ||
952 | if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { | |
bb2ac47b AD |
953 | /* allow time for SFP cage time to power up phy */ |
954 | msleep(300); | |
955 | ||
2fb02a26 AD |
956 | ret_val = hw->phy.ops.reset(hw); |
957 | if (ret_val) { | |
958 | hw_dbg("Error resetting the PHY.\n"); | |
959 | goto out; | |
960 | } | |
961 | } | |
9d5c8243 AK |
962 | switch (hw->phy.type) { |
963 | case e1000_phy_m88: | |
964 | ret_val = igb_copper_link_setup_m88(hw); | |
965 | break; | |
966 | case e1000_phy_igp_3: | |
967 | ret_val = igb_copper_link_setup_igp(hw); | |
9d5c8243 | 968 | break; |
bb2ac47b AD |
969 | case e1000_phy_82580: |
970 | ret_val = igb_copper_link_setup_82580(hw); | |
971 | break; | |
9d5c8243 AK |
972 | default: |
973 | ret_val = -E1000_ERR_PHY; | |
974 | break; | |
975 | } | |
976 | ||
977 | if (ret_val) | |
978 | goto out; | |
979 | ||
81fadd81 | 980 | ret_val = igb_setup_copper_link(hw); |
9d5c8243 AK |
981 | out: |
982 | return ret_val; | |
983 | } | |
984 | ||
985 | /** | |
70d92f86 | 986 | * igb_setup_serdes_link_82575 - Setup link for serdes |
9d5c8243 AK |
987 | * @hw: pointer to the HW structure |
988 | * | |
70d92f86 AD |
989 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
990 | * used on copper connections where the serialized gigabit media independent | |
991 | * interface (sgmii), or serdes fiber is being used. Configures the link | |
992 | * for auto-negotiation or forces speed/duplex. | |
9d5c8243 | 993 | **/ |
2fb02a26 | 994 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 995 | { |
bb2ac47b AD |
996 | u32 ctrl_ext, ctrl_reg, reg; |
997 | bool pcs_autoneg; | |
2fb02a26 AD |
998 | |
999 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1000 | !igb_sgmii_active_82575(hw)) | |
1001 | return 0; | |
9d5c8243 AK |
1002 | |
1003 | /* | |
1004 | * On the 82575, SerDes loopback mode persists until it is | |
1005 | * explicitly turned off or a power cycle is performed. A read to | |
1006 | * the register does not indicate its status. Therefore, we ensure | |
1007 | * loopback mode is disabled during initialization. | |
1008 | */ | |
1009 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1010 | ||
2fb02a26 | 1011 | /* power on the sfp cage if present */ |
bb2ac47b AD |
1012 | ctrl_ext = rd32(E1000_CTRL_EXT); |
1013 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1014 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
2fb02a26 AD |
1015 | |
1016 | ctrl_reg = rd32(E1000_CTRL); | |
1017 | ctrl_reg |= E1000_CTRL_SLU; | |
1018 | ||
1019 | if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { | |
1020 | /* set both sw defined pins */ | |
1021 | ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; | |
1022 | ||
1023 | /* Set switch control to serdes energy detect */ | |
1024 | reg = rd32(E1000_CONNSW); | |
1025 | reg |= E1000_CONNSW_ENRGSRC; | |
1026 | wr32(E1000_CONNSW, reg); | |
1027 | } | |
1028 | ||
1029 | reg = rd32(E1000_PCS_LCTL); | |
1030 | ||
bb2ac47b AD |
1031 | /* default pcs_autoneg to the same setting as mac autoneg */ |
1032 | pcs_autoneg = hw->mac.autoneg; | |
2fb02a26 | 1033 | |
bb2ac47b AD |
1034 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
1035 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
1036 | /* sgmii mode lets the phy handle forcing speed/duplex */ | |
1037 | pcs_autoneg = true; | |
1038 | /* autoneg time out should be disabled for SGMII mode */ | |
2fb02a26 | 1039 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
bb2ac47b AD |
1040 | break; |
1041 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: | |
1042 | /* disable PCS autoneg and support parallel detect only */ | |
1043 | pcs_autoneg = false; | |
1044 | default: | |
1045 | /* | |
1046 | * non-SGMII modes only supports a speed of 1000/Full for the | |
1047 | * link so it is best to just force the MAC and let the pcs | |
1048 | * link either autoneg or be forced to 1000/Full | |
1049 | */ | |
2fb02a26 AD |
1050 | ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | |
1051 | E1000_CTRL_FD | E1000_CTRL_FRCDPX; | |
bb2ac47b AD |
1052 | |
1053 | /* set speed of 1000/Full if speed/duplex is forced */ | |
1054 | reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; | |
1055 | break; | |
921aa749 AD |
1056 | } |
1057 | ||
2fb02a26 | 1058 | wr32(E1000_CTRL, ctrl_reg); |
9d5c8243 AK |
1059 | |
1060 | /* | |
1061 | * New SerDes mode allows for forcing speed or autonegotiating speed | |
1062 | * at 1gb. Autoneg should be default set by most drivers. This is the | |
1063 | * mode that will be compatible with older link partners and switches. | |
1064 | * However, both are supported by the hardware and some drivers/tools. | |
1065 | */ | |
9d5c8243 AK |
1066 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1067 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1068 | ||
2fb02a26 AD |
1069 | /* |
1070 | * We force flow control to prevent the CTRL register values from being | |
1071 | * overwritten by the autonegotiated flow control values | |
1072 | */ | |
1073 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1074 | ||
bb2ac47b | 1075 | if (pcs_autoneg) { |
9d5c8243 | 1076 | /* Set PCS register for autoneg */ |
bb2ac47b | 1077 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
70d92f86 | 1078 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
bb2ac47b | 1079 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
9d5c8243 | 1080 | } else { |
bb2ac47b | 1081 | /* Set PCS register for forced link */ |
d68caec6 | 1082 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
bb2ac47b AD |
1083 | |
1084 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); | |
9d5c8243 | 1085 | } |
726c09e7 | 1086 | |
9d5c8243 AK |
1087 | wr32(E1000_PCS_LCTL, reg); |
1088 | ||
2fb02a26 AD |
1089 | if (!igb_sgmii_active_82575(hw)) |
1090 | igb_force_mac_fc(hw); | |
9d5c8243 | 1091 | |
2fb02a26 | 1092 | return 0; |
9d5c8243 AK |
1093 | } |
1094 | ||
1095 | /** | |
733596be | 1096 | * igb_sgmii_active_82575 - Return sgmii state |
9d5c8243 AK |
1097 | * @hw: pointer to the HW structure |
1098 | * | |
1099 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) | |
1100 | * which can be enabled for use in the embedded applications. Simply | |
1101 | * return the current state of the sgmii interface. | |
1102 | **/ | |
1103 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) | |
1104 | { | |
c1889bfe | 1105 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
c1889bfe | 1106 | return dev_spec->sgmii_active; |
9d5c8243 AK |
1107 | } |
1108 | ||
1109 | /** | |
733596be | 1110 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
9d5c8243 AK |
1111 | * @hw: pointer to the HW structure |
1112 | * | |
1113 | * Inits recommended HW defaults after a reset when there is no EEPROM | |
1114 | * detected. This is only for the 82575. | |
1115 | **/ | |
1116 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) | |
1117 | { | |
1118 | if (hw->mac.type == e1000_82575) { | |
652fff32 | 1119 | hw_dbg("Running reset init script for 82575\n"); |
9d5c8243 AK |
1120 | /* SerDes configuration via SERDESCTRL */ |
1121 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); | |
1122 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); | |
1123 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); | |
1124 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); | |
1125 | ||
1126 | /* CCM configuration via CCMCTL register */ | |
1127 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); | |
1128 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); | |
1129 | ||
1130 | /* PCIe lanes configuration */ | |
1131 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); | |
1132 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); | |
1133 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); | |
1134 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); | |
1135 | ||
1136 | /* PCIe PLL Configuration */ | |
1137 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); | |
1138 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); | |
1139 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); | |
1140 | } | |
1141 | ||
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | /** | |
733596be | 1146 | * igb_read_mac_addr_82575 - Read device MAC address |
9d5c8243 AK |
1147 | * @hw: pointer to the HW structure |
1148 | **/ | |
1149 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) | |
1150 | { | |
1151 | s32 ret_val = 0; | |
1152 | ||
22896639 AD |
1153 | /* |
1154 | * If there's an alternate MAC address place it in RAR0 | |
1155 | * so that it will override the Si installed default perm | |
1156 | * address. | |
1157 | */ | |
1158 | ret_val = igb_check_alt_mac_addr(hw); | |
1159 | if (ret_val) | |
1160 | goto out; | |
1161 | ||
1162 | ret_val = igb_read_mac_addr(hw); | |
9d5c8243 | 1163 | |
22896639 | 1164 | out: |
9d5c8243 AK |
1165 | return ret_val; |
1166 | } | |
1167 | ||
1168 | /** | |
733596be | 1169 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
9d5c8243 AK |
1170 | * @hw: pointer to the HW structure |
1171 | * | |
1172 | * Clears the hardware counters by reading the counter registers. | |
1173 | **/ | |
1174 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) | |
1175 | { | |
9d5c8243 AK |
1176 | igb_clear_hw_cntrs_base(hw); |
1177 | ||
cc9073bb AD |
1178 | rd32(E1000_PRC64); |
1179 | rd32(E1000_PRC127); | |
1180 | rd32(E1000_PRC255); | |
1181 | rd32(E1000_PRC511); | |
1182 | rd32(E1000_PRC1023); | |
1183 | rd32(E1000_PRC1522); | |
1184 | rd32(E1000_PTC64); | |
1185 | rd32(E1000_PTC127); | |
1186 | rd32(E1000_PTC255); | |
1187 | rd32(E1000_PTC511); | |
1188 | rd32(E1000_PTC1023); | |
1189 | rd32(E1000_PTC1522); | |
1190 | ||
1191 | rd32(E1000_ALGNERRC); | |
1192 | rd32(E1000_RXERRC); | |
1193 | rd32(E1000_TNCRS); | |
1194 | rd32(E1000_CEXTERR); | |
1195 | rd32(E1000_TSCTC); | |
1196 | rd32(E1000_TSCTFC); | |
1197 | ||
1198 | rd32(E1000_MGTPRC); | |
1199 | rd32(E1000_MGTPDC); | |
1200 | rd32(E1000_MGTPTC); | |
1201 | ||
1202 | rd32(E1000_IAC); | |
1203 | rd32(E1000_ICRXOC); | |
1204 | ||
1205 | rd32(E1000_ICRXPTC); | |
1206 | rd32(E1000_ICRXATC); | |
1207 | rd32(E1000_ICTXPTC); | |
1208 | rd32(E1000_ICTXATC); | |
1209 | rd32(E1000_ICTXQEC); | |
1210 | rd32(E1000_ICTXQMTC); | |
1211 | rd32(E1000_ICRXDMTC); | |
1212 | ||
1213 | rd32(E1000_CBTMPC); | |
1214 | rd32(E1000_HTDPMC); | |
1215 | rd32(E1000_CBRMPC); | |
1216 | rd32(E1000_RPTHC); | |
1217 | rd32(E1000_HGPTC); | |
1218 | rd32(E1000_HTCBDPC); | |
1219 | rd32(E1000_HGORCL); | |
1220 | rd32(E1000_HGORCH); | |
1221 | rd32(E1000_HGOTCL); | |
1222 | rd32(E1000_HGOTCH); | |
1223 | rd32(E1000_LENERRS); | |
9d5c8243 AK |
1224 | |
1225 | /* This register should not be read in copper configurations */ | |
2fb02a26 AD |
1226 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
1227 | igb_sgmii_active_82575(hw)) | |
cc9073bb | 1228 | rd32(E1000_SCVPC); |
9d5c8243 AK |
1229 | } |
1230 | ||
662d7205 AD |
1231 | /** |
1232 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable | |
1233 | * @hw: pointer to the HW structure | |
1234 | * | |
1235 | * After rx enable if managability is enabled then there is likely some | |
1236 | * bad data at the start of the fifo and possibly in the DMA fifo. This | |
1237 | * function clears the fifos and flushes any packets that came in as rx was | |
1238 | * being enabled. | |
1239 | **/ | |
1240 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) | |
1241 | { | |
1242 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; | |
1243 | int i, ms_wait; | |
1244 | ||
1245 | if (hw->mac.type != e1000_82575 || | |
1246 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) | |
1247 | return; | |
1248 | ||
1249 | /* Disable all RX queues */ | |
1250 | for (i = 0; i < 4; i++) { | |
1251 | rxdctl[i] = rd32(E1000_RXDCTL(i)); | |
1252 | wr32(E1000_RXDCTL(i), | |
1253 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); | |
1254 | } | |
1255 | /* Poll all queues to verify they have shut down */ | |
1256 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { | |
1257 | msleep(1); | |
1258 | rx_enabled = 0; | |
1259 | for (i = 0; i < 4; i++) | |
1260 | rx_enabled |= rd32(E1000_RXDCTL(i)); | |
1261 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) | |
1262 | break; | |
1263 | } | |
1264 | ||
1265 | if (ms_wait == 10) | |
1266 | hw_dbg("Queue disable timed out after 10ms\n"); | |
1267 | ||
1268 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all | |
1269 | * incoming packets are rejected. Set enable and wait 2ms so that | |
1270 | * any packet that was coming in as RCTL.EN was set is flushed | |
1271 | */ | |
1272 | rfctl = rd32(E1000_RFCTL); | |
1273 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); | |
1274 | ||
1275 | rlpml = rd32(E1000_RLPML); | |
1276 | wr32(E1000_RLPML, 0); | |
1277 | ||
1278 | rctl = rd32(E1000_RCTL); | |
1279 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); | |
1280 | temp_rctl |= E1000_RCTL_LPE; | |
1281 | ||
1282 | wr32(E1000_RCTL, temp_rctl); | |
1283 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); | |
1284 | wrfl(); | |
1285 | msleep(2); | |
1286 | ||
1287 | /* Enable RX queues that were previously enabled and restore our | |
1288 | * previous state | |
1289 | */ | |
1290 | for (i = 0; i < 4; i++) | |
1291 | wr32(E1000_RXDCTL(i), rxdctl[i]); | |
1292 | wr32(E1000_RCTL, rctl); | |
1293 | wrfl(); | |
1294 | ||
1295 | wr32(E1000_RLPML, rlpml); | |
1296 | wr32(E1000_RFCTL, rfctl); | |
1297 | ||
1298 | /* Flush receive errors generated by workaround */ | |
1299 | rd32(E1000_ROC); | |
1300 | rd32(E1000_RNBC); | |
1301 | rd32(E1000_MPC); | |
1302 | } | |
1303 | ||
009bc06e AD |
1304 | /** |
1305 | * igb_set_pcie_completion_timeout - set pci-e completion timeout | |
1306 | * @hw: pointer to the HW structure | |
1307 | * | |
1308 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, | |
1309 | * however the hardware default for these parts is 500us to 1ms which is less | |
1310 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
1311 | * increase the value to either 10ms to 200ms for capability version 1 config, | |
1312 | * or 16ms to 55ms for version 2. | |
1313 | **/ | |
1314 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) | |
1315 | { | |
1316 | u32 gcr = rd32(E1000_GCR); | |
1317 | s32 ret_val = 0; | |
1318 | u16 pcie_devctl2; | |
1319 | ||
1320 | /* only take action if timeout value is defaulted to 0 */ | |
1321 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) | |
1322 | goto out; | |
1323 | ||
1324 | /* | |
1325 | * if capababilities version is type 1 we can write the | |
1326 | * timeout of 10ms to 200ms through the GCR register | |
1327 | */ | |
1328 | if (!(gcr & E1000_GCR_CAP_VER2)) { | |
1329 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; | |
1330 | goto out; | |
1331 | } | |
1332 | ||
1333 | /* | |
1334 | * for version 2 capabilities we need to write the config space | |
1335 | * directly in order to set the completion timeout value for | |
1336 | * 16ms to 55ms | |
1337 | */ | |
1338 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1339 | &pcie_devctl2); | |
1340 | if (ret_val) | |
1341 | goto out; | |
1342 | ||
1343 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; | |
1344 | ||
1345 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1346 | &pcie_devctl2); | |
1347 | out: | |
1348 | /* disable completion timeout resend */ | |
1349 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; | |
1350 | ||
1351 | wr32(E1000_GCR, gcr); | |
1352 | return ret_val; | |
1353 | } | |
1354 | ||
4ae196df AD |
1355 | /** |
1356 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback | |
1357 | * @hw: pointer to the hardware struct | |
1358 | * @enable: state to enter, either enabled or disabled | |
1359 | * | |
1360 | * enables/disables L2 switch loopback functionality. | |
1361 | **/ | |
1362 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) | |
1363 | { | |
1364 | u32 dtxswc = rd32(E1000_DTXSWC); | |
1365 | ||
1366 | if (enable) | |
1367 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1368 | else | |
1369 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1370 | ||
1371 | wr32(E1000_DTXSWC, dtxswc); | |
1372 | } | |
1373 | ||
1374 | /** | |
1375 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication | |
1376 | * @hw: pointer to the hardware struct | |
1377 | * @enable: state to enter, either enabled or disabled | |
1378 | * | |
1379 | * enables/disables replication of packets across multiple pools. | |
1380 | **/ | |
1381 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) | |
1382 | { | |
1383 | u32 vt_ctl = rd32(E1000_VT_CTL); | |
1384 | ||
1385 | if (enable) | |
1386 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; | |
1387 | else | |
1388 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; | |
1389 | ||
1390 | wr32(E1000_VT_CTL, vt_ctl); | |
1391 | } | |
1392 | ||
bb2ac47b AD |
1393 | /** |
1394 | * igb_read_phy_reg_82580 - Read 82580 MDI control register | |
1395 | * @hw: pointer to the HW structure | |
1396 | * @offset: register offset to be read | |
1397 | * @data: pointer to the read data | |
1398 | * | |
1399 | * Reads the MDI control register in the PHY at offset and stores the | |
1400 | * information read to data. | |
1401 | **/ | |
1402 | static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) | |
1403 | { | |
1404 | u32 mdicnfg = 0; | |
1405 | s32 ret_val; | |
1406 | ||
1407 | ||
1408 | ret_val = hw->phy.ops.acquire(hw); | |
1409 | if (ret_val) | |
1410 | goto out; | |
1411 | ||
1412 | /* | |
1413 | * We config the phy address in MDICNFG register now. Same bits | |
1414 | * as before. The values in MDIC can be written but will be | |
1415 | * ignored. This allows us to call the old function after | |
1416 | * configuring the PHY address in the new register | |
1417 | */ | |
1418 | mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT); | |
1419 | wr32(E1000_MDICNFG, mdicnfg); | |
1420 | ||
1421 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); | |
1422 | ||
1423 | hw->phy.ops.release(hw); | |
1424 | ||
1425 | out: | |
1426 | return ret_val; | |
1427 | } | |
1428 | ||
1429 | /** | |
1430 | * igb_write_phy_reg_82580 - Write 82580 MDI control register | |
1431 | * @hw: pointer to the HW structure | |
1432 | * @offset: register offset to write to | |
1433 | * @data: data to write to register at offset | |
1434 | * | |
1435 | * Writes data to MDI control register in the PHY at offset. | |
1436 | **/ | |
1437 | static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) | |
1438 | { | |
1439 | u32 mdicnfg = 0; | |
1440 | s32 ret_val; | |
1441 | ||
1442 | ||
1443 | ret_val = hw->phy.ops.acquire(hw); | |
1444 | if (ret_val) | |
1445 | goto out; | |
1446 | ||
1447 | /* | |
1448 | * We config the phy address in MDICNFG register now. Same bits | |
1449 | * as before. The values in MDIC can be written but will be | |
1450 | * ignored. This allows us to call the old function after | |
1451 | * configuring the PHY address in the new register | |
1452 | */ | |
1453 | mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT); | |
1454 | wr32(E1000_MDICNFG, mdicnfg); | |
1455 | ||
1456 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); | |
1457 | ||
1458 | hw->phy.ops.release(hw); | |
1459 | ||
1460 | out: | |
1461 | return ret_val; | |
1462 | } | |
1463 | ||
1464 | /** | |
1465 | * igb_reset_hw_82580 - Reset hardware | |
1466 | * @hw: pointer to the HW structure | |
1467 | * | |
1468 | * This resets function or entire device (all ports, etc.) | |
1469 | * to a known state. | |
1470 | **/ | |
1471 | static s32 igb_reset_hw_82580(struct e1000_hw *hw) | |
1472 | { | |
1473 | s32 ret_val = 0; | |
1474 | /* BH SW mailbox bit in SW_FW_SYNC */ | |
1475 | u16 swmbsw_mask = E1000_SW_SYNCH_MB; | |
1476 | u32 ctrl, icr; | |
1477 | bool global_device_reset = hw->dev_spec._82575.global_device_reset; | |
1478 | ||
1479 | ||
1480 | hw->dev_spec._82575.global_device_reset = false; | |
1481 | ||
1482 | /* Get current control state. */ | |
1483 | ctrl = rd32(E1000_CTRL); | |
1484 | ||
1485 | /* | |
1486 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
1487 | * on the last TLP read/write transaction when MAC is reset. | |
1488 | */ | |
1489 | ret_val = igb_disable_pcie_master(hw); | |
1490 | if (ret_val) | |
1491 | hw_dbg("PCI-E Master disable polling has failed.\n"); | |
1492 | ||
1493 | hw_dbg("Masking off all interrupts\n"); | |
1494 | wr32(E1000_IMC, 0xffffffff); | |
1495 | wr32(E1000_RCTL, 0); | |
1496 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
1497 | wrfl(); | |
1498 | ||
1499 | msleep(10); | |
1500 | ||
1501 | /* Determine whether or not a global dev reset is requested */ | |
1502 | if (global_device_reset && | |
1503 | igb_acquire_swfw_sync_82575(hw, swmbsw_mask)) | |
1504 | global_device_reset = false; | |
1505 | ||
1506 | if (global_device_reset && | |
1507 | !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) | |
1508 | ctrl |= E1000_CTRL_DEV_RST; | |
1509 | else | |
1510 | ctrl |= E1000_CTRL_RST; | |
1511 | ||
1512 | wr32(E1000_CTRL, ctrl); | |
1513 | ||
1514 | /* Add delay to insure DEV_RST has time to complete */ | |
1515 | if (global_device_reset) | |
1516 | msleep(5); | |
1517 | ||
1518 | ret_val = igb_get_auto_rd_done(hw); | |
1519 | if (ret_val) { | |
1520 | /* | |
1521 | * When auto config read does not complete, do not | |
1522 | * return with an error. This can happen in situations | |
1523 | * where there is no eeprom and prevents getting link. | |
1524 | */ | |
1525 | hw_dbg("Auto Read Done did not complete\n"); | |
1526 | } | |
1527 | ||
1528 | /* If EEPROM is not present, run manual init scripts */ | |
1529 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
1530 | igb_reset_init_script_82575(hw); | |
1531 | ||
1532 | /* clear global device reset status bit */ | |
1533 | wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); | |
1534 | ||
1535 | /* Clear any pending interrupt events. */ | |
1536 | wr32(E1000_IMC, 0xffffffff); | |
1537 | icr = rd32(E1000_ICR); | |
1538 | ||
1539 | /* Install any alternate MAC address into RAR0 */ | |
1540 | ret_val = igb_check_alt_mac_addr(hw); | |
1541 | ||
1542 | /* Release semaphore */ | |
1543 | if (global_device_reset) | |
1544 | igb_release_swfw_sync_82575(hw, swmbsw_mask); | |
1545 | ||
1546 | return ret_val; | |
1547 | } | |
1548 | ||
1549 | /** | |
1550 | * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size | |
1551 | * @data: data received by reading RXPBS register | |
1552 | * | |
1553 | * The 82580 uses a table based approach for packet buffer allocation sizes. | |
1554 | * This function converts the retrieved value into the correct table value | |
1555 | * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 | |
1556 | * 0x0 36 72 144 1 2 4 8 16 | |
1557 | * 0x8 35 70 140 rsv rsv rsv rsv rsv | |
1558 | */ | |
1559 | u16 igb_rxpbs_adjust_82580(u32 data) | |
1560 | { | |
1561 | u16 ret_val = 0; | |
1562 | ||
1563 | if (data < E1000_82580_RXPBS_TABLE_SIZE) | |
1564 | ret_val = e1000_82580_rxpbs_table[data]; | |
1565 | ||
1566 | return ret_val; | |
1567 | } | |
1568 | ||
9d5c8243 | 1569 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
9d5c8243 AK |
1570 | .init_hw = igb_init_hw_82575, |
1571 | .check_for_link = igb_check_for_link_82575, | |
2d064c06 | 1572 | .rar_set = igb_rar_set, |
9d5c8243 AK |
1573 | .read_mac_addr = igb_read_mac_addr_82575, |
1574 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | |
1575 | }; | |
1576 | ||
1577 | static struct e1000_phy_operations e1000_phy_ops_82575 = { | |
a8d2a0c2 | 1578 | .acquire = igb_acquire_phy_82575, |
9d5c8243 | 1579 | .get_cfg_done = igb_get_cfg_done_82575, |
a8d2a0c2 | 1580 | .release = igb_release_phy_82575, |
9d5c8243 AK |
1581 | }; |
1582 | ||
1583 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { | |
312c75ae AD |
1584 | .acquire = igb_acquire_nvm_82575, |
1585 | .read = igb_read_nvm_eerd, | |
1586 | .release = igb_release_nvm_82575, | |
1587 | .write = igb_write_nvm_spi, | |
9d5c8243 AK |
1588 | }; |
1589 | ||
1590 | const struct e1000_info e1000_82575_info = { | |
1591 | .get_invariants = igb_get_invariants_82575, | |
1592 | .mac_ops = &e1000_mac_ops_82575, | |
1593 | .phy_ops = &e1000_phy_ops_82575, | |
1594 | .nvm_ops = &e1000_nvm_ops_82575, | |
1595 | }; | |
1596 |