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igb: igb should not flag lltx
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
652fff32 4 Copyright(c) 2007 - 2008 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
33#include <linux/slab.h>
2d064c06 34#include <linux/if_ether.h>
9d5c8243
AK		 35
36#include "e1000_mac.h"
37#include "e1000_82575.h"
38
39static s32 igb_get_invariants_82575(struct e1000_hw *);
40static s32 igb_acquire_phy_82575(struct e1000_hw *);
41static void igb_release_phy_82575(struct e1000_hw *);
42static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43static void igb_release_nvm_82575(struct e1000_hw *);
44static s32 igb_check_for_link_82575(struct e1000_hw *);
45static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46static s32 igb_init_hw_82575(struct e1000_hw *);
47static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
9d5c8243
AK		 49static s32 igb_reset_hw_82575(struct e1000_hw *);
50static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51static s32 igb_setup_copper_link_82575(struct e1000_hw *);
52static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
53static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56static s32 igb_configure_pcs_link_82575(struct e1000_hw *);
57static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
58 u16 *);
59static s32 igb_get_phy_id_82575(struct e1000_hw *);
60static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
61static bool igb_sgmii_active_82575(struct e1000_hw *);
62static s32 igb_reset_init_script_82575(struct e1000_hw *);
63static s32 igb_read_mac_addr_82575(struct e1000_hw *);
64
65
66struct e1000_dev_spec_82575 {
67 bool sgmii_active;
68};
69
70static s32 igb_get_invariants_82575(struct e1000_hw *hw)
71{
72 struct e1000_phy_info *phy = &hw->phy;
73 struct e1000_nvm_info *nvm = &hw->nvm;
74 struct e1000_mac_info *mac = &hw->mac;
75 struct e1000_dev_spec_82575 *dev_spec;
76 u32 eecd;
77 s32 ret_val;
78 u16 size;
79 u32 ctrl_ext = 0;
80
81 switch (hw->device_id) {
82 case E1000_DEV_ID_82575EB_COPPER:
83 case E1000_DEV_ID_82575EB_FIBER_SERDES:
84 case E1000_DEV_ID_82575GB_QUAD_COPPER:
85 mac->type = e1000_82575;
86 break;
2d064c06
AD		 87 case E1000_DEV_ID_82576:
88 case E1000_DEV_ID_82576_FIBER:
89 case E1000_DEV_ID_82576_SERDES:
2d064c06
AD		 90 mac->type = e1000_82576;
91 break;
9d5c8243
AK		 92 default:
93 return -E1000_ERR_MAC_INIT;
94 break;
95 }
96
97 /* MAC initialization */
98 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575);
99
100 /* Device-specific structure allocation */
101 hw->dev_spec = kzalloc(hw->dev_spec_size, GFP_KERNEL);
102
103 if (!hw->dev_spec)
104 return -ENOMEM;
105
106 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
107
108 /* Set media type */
109 /*
110 * The 82575 uses bits 22:23 for link mode. The mode can be changed
111 * based on the EEPROM. We cannot rely upon device ID. There
112 * is no distinguishable difference between fiber and internal
113 * SerDes mode on the 82575. There can be an external PHY attached
114 * on the SGMII interface. For this, we'll set sgmii_active to true.
115 */
116 phy->media_type = e1000_media_type_copper;
117 dev_spec->sgmii_active = false;
118
119 ctrl_ext = rd32(E1000_CTRL_EXT);
120 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
121 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
122 hw->phy.media_type = e1000_media_type_internal_serdes;
123 ctrl_ext |= E1000_CTRL_I2C_ENA;
124 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
125 dev_spec->sgmii_active = true;
126 ctrl_ext |= E1000_CTRL_I2C_ENA;
127 } else {
128 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
129 }
130 wr32(E1000_CTRL_EXT, ctrl_ext);
131
132 /* Set mta register count */
133 mac->mta_reg_count = 128;
134 /* Set rar entry count */
135 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
2d064c06
AD		 136 if (mac->type == e1000_82576)
137 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
9d5c8243
AK		 138 /* Set if part includes ASF firmware */
139 mac->asf_firmware_present = true;
140 /* Set if manageability features are enabled. */
141 mac->arc_subsystem_valid =
142 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
143 ? true : false;
144
145 /* physical interface link setup */
146 mac->ops.setup_physical_interface =
147 (hw->phy.media_type == e1000_media_type_copper)
148 ? igb_setup_copper_link_82575
149 : igb_setup_fiber_serdes_link_82575;
150
151 /* NVM initialization */
152 eecd = rd32(E1000_EECD);
153
154 nvm->opcode_bits = 8;
155 nvm->delay_usec = 1;
156 switch (nvm->override) {
157 case e1000_nvm_override_spi_large:
158 nvm->page_size = 32;
159 nvm->address_bits = 16;
160 break;
161 case e1000_nvm_override_spi_small:
162 nvm->page_size = 8;
163 nvm->address_bits = 8;
164 break;
165 default:
166 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
167 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
168 break;
169 }
170
171 nvm->type = e1000_nvm_eeprom_spi;
172
173 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
174 E1000_EECD_SIZE_EX_SHIFT);
175
176 /*
177 * Added to a constant, "size" becomes the left-shift value
178 * for setting word_size.
179 */
180 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75
JK		 181
182 /* EEPROM access above 16k is unsupported */
183 if (size > 14)
184 size = 14;
9d5c8243
AK		 185 nvm->word_size = 1 << size;
186
187 /* setup PHY parameters */
188 if (phy->media_type != e1000_media_type_copper) {
189 phy->type = e1000_phy_none;
190 return 0;
191 }
192
193 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
194 phy->reset_delay_us = 100;
195
196 /* PHY function pointers */
197 if (igb_sgmii_active_82575(hw)) {
198 phy->ops.reset_phy = igb_phy_hw_reset_sgmii_82575;
199 phy->ops.read_phy_reg = igb_read_phy_reg_sgmii_82575;
200 phy->ops.write_phy_reg = igb_write_phy_reg_sgmii_82575;
201 } else {
202 phy->ops.reset_phy = igb_phy_hw_reset;
203 phy->ops.read_phy_reg = igb_read_phy_reg_igp;
204 phy->ops.write_phy_reg = igb_write_phy_reg_igp;
205 }
206
207 /* Set phy->phy_addr and phy->id. */
208 ret_val = igb_get_phy_id_82575(hw);
209 if (ret_val)
210 return ret_val;
211
212 /* Verify phy id and set remaining function pointers */
213 switch (phy->id) {
214 case M88E1111_I_PHY_ID:
215 phy->type = e1000_phy_m88;
216 phy->ops.get_phy_info = igb_get_phy_info_m88;
217 phy->ops.get_cable_length = igb_get_cable_length_m88;
218 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
219 break;
220 case IGP03E1000_E_PHY_ID:
221 phy->type = e1000_phy_igp_3;
222 phy->ops.get_phy_info = igb_get_phy_info_igp;
223 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
224 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
225 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
226 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
227 break;
228 default:
229 return -E1000_ERR_PHY;
230 }
231
232 return 0;
233}
234
235/**
733596be 236 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 237 * @hw: pointer to the HW structure
238 *
239 * Acquire access rights to the correct PHY. This is a
240 * function pointer entry point called by the api module.
241 **/
242static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
243{
244 u16 mask;
245
246 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
247
248 return igb_acquire_swfw_sync_82575(hw, mask);
249}
250
251/**
733596be 252 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 253 * @hw: pointer to the HW structure
254 *
255 * A wrapper to release access rights to the correct PHY. This is a
256 * function pointer entry point called by the api module.
257 **/
258static void igb_release_phy_82575(struct e1000_hw *hw)
259{
260 u16 mask;
261
262 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
263 igb_release_swfw_sync_82575(hw, mask);
264}
265
266/**
733596be 267 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 268 * @hw: pointer to the HW structure
269 * @offset: register offset to be read
270 * @data: pointer to the read data
271 *
272 * Reads the PHY register at offset using the serial gigabit media independent
273 * interface and stores the retrieved information in data.
274 **/
275static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
276 u16 *data)
277{
278 struct e1000_phy_info *phy = &hw->phy;
279 u32 i, i2ccmd = 0;
280
281 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 282 hw_dbg("PHY Address %u is out of range\n", offset);
9d5c8243
AK		 283 return -E1000_ERR_PARAM;
284 }
285
286 /*
287 * Set up Op-code, Phy Address, and register address in the I2CCMD
288 * register. The MAC will take care of interfacing with the
289 * PHY to retrieve the desired data.
290 */
291 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
292 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
293 (E1000_I2CCMD_OPCODE_READ));
294
295 wr32(E1000_I2CCMD, i2ccmd);
296
297 /* Poll the ready bit to see if the I2C read completed */
298 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
299 udelay(50);
300 i2ccmd = rd32(E1000_I2CCMD);
301 if (i2ccmd & E1000_I2CCMD_READY)
302 break;
303 }
304 if (!(i2ccmd & E1000_I2CCMD_READY)) {
652fff32 305 hw_dbg("I2CCMD Read did not complete\n");
9d5c8243
AK		 306 return -E1000_ERR_PHY;
307 }
308 if (i2ccmd & E1000_I2CCMD_ERROR) {
652fff32 309 hw_dbg("I2CCMD Error bit set\n");
9d5c8243
AK		 310 return -E1000_ERR_PHY;
311 }
312
313 /* Need to byte-swap the 16-bit value. */
314 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
315
316 return 0;
317}
318
319/**
733596be 320 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 321 * @hw: pointer to the HW structure
322 * @offset: register offset to write to
323 * @data: data to write at register offset
324 *
325 * Writes the data to PHY register at the offset using the serial gigabit
326 * media independent interface.
327 **/
328static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
329 u16 data)
330{
331 struct e1000_phy_info *phy = &hw->phy;
332 u32 i, i2ccmd = 0;
333 u16 phy_data_swapped;
334
335 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 336 hw_dbg("PHY Address %d is out of range\n", offset);
9d5c8243
AK		 337 return -E1000_ERR_PARAM;
338 }
339
340 /* Swap the data bytes for the I2C interface */
341 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
342
343 /*
344 * Set up Op-code, Phy Address, and register address in the I2CCMD
345 * register. The MAC will take care of interfacing with the
346 * PHY to retrieve the desired data.
347 */
348 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
349 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
350 E1000_I2CCMD_OPCODE_WRITE |
351 phy_data_swapped);
352
353 wr32(E1000_I2CCMD, i2ccmd);
354
355 /* Poll the ready bit to see if the I2C read completed */
356 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
357 udelay(50);
358 i2ccmd = rd32(E1000_I2CCMD);
359 if (i2ccmd & E1000_I2CCMD_READY)
360 break;
361 }
362 if (!(i2ccmd & E1000_I2CCMD_READY)) {
652fff32 363 hw_dbg("I2CCMD Write did not complete\n");
9d5c8243
AK		 364 return -E1000_ERR_PHY;
365 }
366 if (i2ccmd & E1000_I2CCMD_ERROR) {
652fff32 367 hw_dbg("I2CCMD Error bit set\n");
9d5c8243
AK		 368 return -E1000_ERR_PHY;
369 }
370
371 return 0;
372}
373
374/**
733596be 375 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 376 * @hw: pointer to the HW structure
377 *
652fff32 378 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 379 * sgmi interface.
380 **/
381static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
382{
383 struct e1000_phy_info *phy = &hw->phy;
384 s32 ret_val = 0;
385 u16 phy_id;
386
387 /*
388 * For SGMII PHYs, we try the list of possible addresses until
389 * we find one that works. For non-SGMII PHYs
390 * (e.g. integrated copper PHYs), an address of 1 should
391 * work. The result of this function should mean phy->phy_addr
392 * and phy->id are set correctly.
393 */
394 if (!(igb_sgmii_active_82575(hw))) {
395 phy->addr = 1;
396 ret_val = igb_get_phy_id(hw);
397 goto out;
398 }
399
400 /*
401 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
402 * Therefore, we need to test 1-7
403 */
404 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
405 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
406 if (ret_val == 0) {
652fff32
AK		 407 hw_dbg("Vendor ID 0x%08X read at address %u\n",
408 phy_id, phy->addr);
9d5c8243
AK		 409 /*
410 * At the time of this writing, The M88 part is
411 * the only supported SGMII PHY product.
412 */
413 if (phy_id == M88_VENDOR)
414 break;
415 } else {
652fff32 416 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 417 }
418 }
419
420 /* A valid PHY type couldn't be found. */
421 if (phy->addr == 8) {
422 phy->addr = 0;
423 ret_val = -E1000_ERR_PHY;
424 goto out;
425 }
426
427 ret_val = igb_get_phy_id(hw);
428
429out:
430 return ret_val;
431}
432
433/**
733596be 434 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 435 * @hw: pointer to the HW structure
436 *
437 * Resets the PHY using the serial gigabit media independent interface.
438 **/
439static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
440{
441 s32 ret_val;
442
443 /*
444 * This isn't a true "hard" reset, but is the only reset
445 * available to us at this time.
446 */
447
652fff32 448 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 449
450 /*
451 * SFP documentation requires the following to configure the SPF module
452 * to work on SGMII. No further documentation is given.
453 */
454 ret_val = hw->phy.ops.write_phy_reg(hw, 0x1B, 0x8084);
455 if (ret_val)
456 goto out;
457
458 ret_val = igb_phy_sw_reset(hw);
459
460out:
461 return ret_val;
462}
463
464/**
733596be 465 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 466 * @hw: pointer to the HW structure
467 * @active: true to enable LPLU, false to disable
468 *
469 * Sets the LPLU D0 state according to the active flag. When
470 * activating LPLU this function also disables smart speed
471 * and vice versa. LPLU will not be activated unless the
472 * device autonegotiation advertisement meets standards of
473 * either 10 or 10/100 or 10/100/1000 at all duplexes.
474 * This is a function pointer entry point only called by
475 * PHY setup routines.
476 **/
477static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
478{
479 struct e1000_phy_info *phy = &hw->phy;
480 s32 ret_val;
481 u16 data;
482
652fff32 483 ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 484 if (ret_val)
485 goto out;
486
487 if (active) {
488 data |= IGP02E1000_PM_D0_LPLU;
652fff32
AK		 489 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
490 data);
9d5c8243
AK		 491 if (ret_val)
492 goto out;
493
494 /* When LPLU is enabled, we should disable SmartSpeed */
652fff32
AK		 495 ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
496 &data);
9d5c8243 497 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
652fff32
AK		 498 ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
499 data);
9d5c8243
AK		 500 if (ret_val)
501 goto out;
502 } else {
503 data &= ~IGP02E1000_PM_D0_LPLU;
652fff32
AK		 504 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
505 data);
9d5c8243
AK		 506 /*
507 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
508 * during Dx states where the power conservation is most
509 * important. During driver activity we should enable
510 * SmartSpeed, so performance is maintained.
511 */
512 if (phy->smart_speed == e1000_smart_speed_on) {
652fff32
AK		 513 ret_val = phy->ops.read_phy_reg(hw,
514 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 515 if (ret_val)
516 goto out;
517
518 data |= IGP01E1000_PSCFR_SMART_SPEED;
652fff32
AK		 519 ret_val = phy->ops.write_phy_reg(hw,
520 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 521 if (ret_val)
522 goto out;
523 } else if (phy->smart_speed == e1000_smart_speed_off) {
652fff32
AK		 524 ret_val = phy->ops.read_phy_reg(hw,
525 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 526 if (ret_val)
527 goto out;
528
529 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
652fff32
AK		 530 ret_val = phy->ops.write_phy_reg(hw,
531 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 532 if (ret_val)
533 goto out;
534 }
535 }
536
537out:
538 return ret_val;
539}
540
541/**
733596be 542 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 543 * @hw: pointer to the HW structure
544 *
652fff32 545 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 546 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
547 * Return successful if access grant bit set, else clear the request for
548 * EEPROM access and return -E1000_ERR_NVM (-1).
549 **/
550static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
551{
552 s32 ret_val;
553
554 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
555 if (ret_val)
556 goto out;
557
558 ret_val = igb_acquire_nvm(hw);
559
560 if (ret_val)
561 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
562
563out:
564 return ret_val;
565}
566
567/**
733596be 568 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 569 * @hw: pointer to the HW structure
570 *
571 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
572 * then release the semaphores acquired.
573 **/
574static void igb_release_nvm_82575(struct e1000_hw *hw)
575{
576 igb_release_nvm(hw);
577 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
578}
579
580/**
733596be 581 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 582 * @hw: pointer to the HW structure
583 * @mask: specifies which semaphore to acquire
584 *
585 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
586 * will also specify which port we're acquiring the lock for.
587 **/
588static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
589{
590 u32 swfw_sync;
591 u32 swmask = mask;
592 u32 fwmask = mask << 16;
593 s32 ret_val = 0;
594 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
595
596 while (i < timeout) {
597 if (igb_get_hw_semaphore(hw)) {
598 ret_val = -E1000_ERR_SWFW_SYNC;
599 goto out;
600 }
601
602 swfw_sync = rd32(E1000_SW_FW_SYNC);
603 if (!(swfw_sync & (fwmask | swmask)))
604 break;
605
606 /*
607 * Firmware currently using resource (fwmask)
608 * or other software thread using resource (swmask)
609 */
610 igb_put_hw_semaphore(hw);
611 mdelay(5);
612 i++;
613 }
614
615 if (i == timeout) {
652fff32 616 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 617 ret_val = -E1000_ERR_SWFW_SYNC;
618 goto out;
619 }
620
621 swfw_sync |= swmask;
622 wr32(E1000_SW_FW_SYNC, swfw_sync);
623
624 igb_put_hw_semaphore(hw);
625
626out:
627 return ret_val;
628}
629
630/**
733596be 631 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 632 * @hw: pointer to the HW structure
633 * @mask: specifies which semaphore to acquire
634 *
635 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
636 * will also specify which port we're releasing the lock for.
637 **/
638static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
639{
640 u32 swfw_sync;
641
642 while (igb_get_hw_semaphore(hw) != 0);
643 /* Empty */
644
645 swfw_sync = rd32(E1000_SW_FW_SYNC);
646 swfw_sync &= ~mask;
647 wr32(E1000_SW_FW_SYNC, swfw_sync);
648
649 igb_put_hw_semaphore(hw);
650}
651
652/**
733596be 653 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 654 * @hw: pointer to the HW structure
655 *
656 * Read the management control register for the config done bit for
657 * completion status. NOTE: silicon which is EEPROM-less will fail trying
658 * to read the config done bit, so an error is *ONLY* logged and returns
659 * 0. If we were to return with error, EEPROM-less silicon
660 * would not be able to be reset or change link.
661 **/
662static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
663{
664 s32 timeout = PHY_CFG_TIMEOUT;
665 s32 ret_val = 0;
666 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
667
668 if (hw->bus.func == 1)
669 mask = E1000_NVM_CFG_DONE_PORT_1;
670
671 while (timeout) {
672 if (rd32(E1000_EEMNGCTL) & mask)
673 break;
674 msleep(1);
675 timeout--;
676 }
677 if (!timeout)
652fff32 678 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 679
680 /* If EEPROM is not marked present, init the PHY manually */
681 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
682 (hw->phy.type == e1000_phy_igp_3))
683 igb_phy_init_script_igp3(hw);
684
685 return ret_val;
686}
687
688/**
733596be 689 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 690 * @hw: pointer to the HW structure
691 *
692 * If sgmii is enabled, then use the pcs register to determine link, otherwise
693 * use the generic interface for determining link.
694 **/
695static s32 igb_check_for_link_82575(struct e1000_hw *hw)
696{
697 s32 ret_val;
698 u16 speed, duplex;
699
700 /* SGMII link check is done through the PCS register. */
701 if ((hw->phy.media_type != e1000_media_type_copper) ||
702 (igb_sgmii_active_82575(hw)))
703 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 704 &duplex);
9d5c8243
AK		 705 else
706 ret_val = igb_check_for_copper_link(hw);
707
708 return ret_val;
709}
9d5c8243 710/**
733596be 711 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 712 * @hw: pointer to the HW structure
713 * @speed: stores the current speed
714 * @duplex: stores the current duplex
715 *
652fff32 716 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 717 * duplex, then store the values in the pointers provided.
718 **/
719static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
720 u16 *duplex)
721{
722 struct e1000_mac_info *mac = &hw->mac;
723 u32 pcs;
724
725 /* Set up defaults for the return values of this function */
726 mac->serdes_has_link = false;
727 *speed = 0;
728 *duplex = 0;
729
730 /*
731 * Read the PCS Status register for link state. For non-copper mode,
732 * the status register is not accurate. The PCS status register is
733 * used instead.
734 */
735 pcs = rd32(E1000_PCS_LSTAT);
736
737 /*
738 * The link up bit determines when link is up on autoneg. The sync ok
739 * gets set once both sides sync up and agree upon link. Stable link
740 * can be determined by checking for both link up and link sync ok
741 */
742 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
743 mac->serdes_has_link = true;
744
745 /* Detect and store PCS speed */
746 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
747 *speed = SPEED_1000;
748 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
749 *speed = SPEED_100;
750 } else {
751 *speed = SPEED_10;
752 }
753
754 /* Detect and store PCS duplex */
755 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
756 *duplex = FULL_DUPLEX;
757 } else {
758 *duplex = HALF_DUPLEX;
759 }
760 }
761
762 return 0;
763}
764
765/**
2d064c06
AD		 766 * igb_init_rx_addrs_82575 - Initialize receive address's
767 * @hw: pointer to the HW structure
768 * @rar_count: receive address registers
769 *
770 * Setups the receive address registers by setting the base receive address
771 * register to the devices MAC address and clearing all the other receive
772 * address registers to 0.
773 **/
774static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
775{
776 u32 i;
777 u8 addr[6] = {0,0,0,0,0,0};
778 /*
779 * This function is essentially the same as that of
780 * e1000_init_rx_addrs_generic. However it also takes care
781 * of the special case where the register offset of the
782 * second set of RARs begins elsewhere. This is implicitly taken care by
783 * function e1000_rar_set_generic.
784 */
785
786 hw_dbg("e1000_init_rx_addrs_82575");
787
788 /* Setup the receive address */
789 hw_dbg("Programming MAC Address into RAR[0]\n");
790 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
791
792 /* Zero out the other (rar_entry_count - 1) receive addresses */
793 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
794 for (i = 1; i < rar_count; i++)
795 hw->mac.ops.rar_set(hw, addr, i);
796}
797
798/**
799 * igb_update_mc_addr_list_82575 - Update Multicast addresses
800 * @hw: pointer to the HW structure
801 * @mc_addr_list: array of multicast addresses to program
802 * @mc_addr_count: number of multicast addresses to program
803 * @rar_used_count: the first RAR register free to program
804 * @rar_count: total number of supported Receive Address Registers
805 *
806 * Updates the Receive Address Registers and Multicast Table Array.
807 * The caller must have a packed mc_addr_list of multicast addresses.
808 * The parameter rar_count will usually be hw->mac.rar_entry_count
809 * unless there are workarounds that change this.
810 **/
811void igb_update_mc_addr_list_82575(struct e1000_hw *hw,
812 u8 *mc_addr_list, u32 mc_addr_count,
813 u32 rar_used_count, u32 rar_count)
814{
815 u32 hash_value;
816 u32 i;
817 u8 addr[6] = {0,0,0,0,0,0};
818 /*
819 * This function is essentially the same as that of
820 * igb_update_mc_addr_list_generic. However it also takes care
821 * of the special case where the register offset of the
822 * second set of RARs begins elsewhere. This is implicitly taken care by
823 * function e1000_rar_set_generic.
824 */
825
826 /*
827 * Load the first set of multicast addresses into the exact
828 * filters (RAR). If there are not enough to fill the RAR
829 * array, clear the filters.
830 */
831 for (i = rar_used_count; i < rar_count; i++) {
832 if (mc_addr_count) {
833 igb_rar_set(hw, mc_addr_list, i);
834 mc_addr_count--;
835 mc_addr_list += ETH_ALEN;
836 } else {
837 igb_rar_set(hw, addr, i);
838 }
839 }
840
841 /* Clear the old settings from the MTA */
842 hw_dbg("Clearing MTA\n");
843 for (i = 0; i < hw->mac.mta_reg_count; i++) {
844 array_wr32(E1000_MTA, i, 0);
845 wrfl();
846 }
847
848 /* Load any remaining multicast addresses into the hash table. */
849 for (; mc_addr_count > 0; mc_addr_count--) {
850 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
851 hw_dbg("Hash value = 0x%03X\n", hash_value);
549bdd84 852 igb_mta_set(hw, hash_value);
2d064c06
AD		 853 mc_addr_list += ETH_ALEN;
854 }
855}
856
857/**
858 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
9d5c8243 859 * @hw: pointer to the HW structure
9d5c8243 860 *
2d064c06
AD		 861 * In the case of fiber serdes, shut down optics and PCS on driver unload
862 * when management pass thru is not enabled.
9d5c8243 863 **/
2d064c06 864void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 865{
2d064c06
AD		 866 u32 reg;
867
868 if (hw->mac.type != e1000_82576 ||
869 (hw->phy.media_type != e1000_media_type_fiber &&
870 hw->phy.media_type != e1000_media_type_internal_serdes))
871 return;
872
873 /* if the management interface is not enabled, then power down */
874 if (!igb_enable_mng_pass_thru(hw)) {
875 /* Disable PCS to turn off link */
876 reg = rd32(E1000_PCS_CFG0);
877 reg &= ~E1000_PCS_CFG_PCS_EN;
878 wr32(E1000_PCS_CFG0, reg);
879
880 /* shutdown the laser */
881 reg = rd32(E1000_CTRL_EXT);
882 reg |= E1000_CTRL_EXT_SDP7_DATA;
883 wr32(E1000_CTRL_EXT, reg);
884
885 /* flush the write to verify completion */
886 wrfl();
887 msleep(1);
888 }
9d5c8243
AK		 889
890 return;
891}
892
893/**
733596be 894 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 895 * @hw: pointer to the HW structure
896 *
897 * This resets the hardware into a known state. This is a
898 * function pointer entry point called by the api module.
899 **/
900static s32 igb_reset_hw_82575(struct e1000_hw *hw)
901{
902 u32 ctrl, icr;
903 s32 ret_val;
904
905 /*
906 * Prevent the PCI-E bus from sticking if there is no TLP connection
907 * on the last TLP read/write transaction when MAC is reset.
908 */
909 ret_val = igb_disable_pcie_master(hw);
910 if (ret_val)
652fff32 911 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 912
652fff32 913 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 914 wr32(E1000_IMC, 0xffffffff);
915
916 wr32(E1000_RCTL, 0);
917 wr32(E1000_TCTL, E1000_TCTL_PSP);
918 wrfl();
919
920 msleep(10);
921
922 ctrl = rd32(E1000_CTRL);
923
652fff32 924 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 925 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
926
927 ret_val = igb_get_auto_rd_done(hw);
928 if (ret_val) {
929 /*
930 * When auto config read does not complete, do not
931 * return with an error. This can happen in situations
932 * where there is no eeprom and prevents getting link.
933 */
652fff32 934 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 935 }
936
937 /* If EEPROM is not present, run manual init scripts */
938 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
939 igb_reset_init_script_82575(hw);
940
941 /* Clear any pending interrupt events. */
942 wr32(E1000_IMC, 0xffffffff);
943 icr = rd32(E1000_ICR);
944
945 igb_check_alt_mac_addr(hw);
946
947 return ret_val;
948}
949
950/**
733596be 951 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 952 * @hw: pointer to the HW structure
953 *
954 * This inits the hardware readying it for operation.
955 **/
956static s32 igb_init_hw_82575(struct e1000_hw *hw)
957{
958 struct e1000_mac_info *mac = &hw->mac;
959 s32 ret_val;
960 u16 i, rar_count = mac->rar_entry_count;
961
962 /* Initialize identification LED */
963 ret_val = igb_id_led_init(hw);
964 if (ret_val) {
652fff32 965 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 966 /* This is not fatal and we should not stop init due to this */
967 }
968
969 /* Disabling VLAN filtering */
652fff32 970 hw_dbg("Initializing the IEEE VLAN\n");
9d5c8243
AK		 971 igb_clear_vfta(hw);
972
973 /* Setup the receive address */
2d064c06 974 igb_init_rx_addrs_82575(hw, rar_count);
9d5c8243 975 /* Zero out the Multicast HASH table */
652fff32 976 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 977 for (i = 0; i < mac->mta_reg_count; i++)
978 array_wr32(E1000_MTA, i, 0);
979
980 /* Setup link and flow control */
981 ret_val = igb_setup_link(hw);
982
983 /*
984 * Clear all of the statistics registers (clear on read). It is
985 * important that we do this after we have tried to establish link
986 * because the symbol error count will increment wildly if there
987 * is no link.
988 */
989 igb_clear_hw_cntrs_82575(hw);
990
991 return ret_val;
992}
993
994/**
733596be 995 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 996 * @hw: pointer to the HW structure
997 *
998 * Configures the link for auto-neg or forced speed and duplex. Then we check
999 * for link, once link is established calls to configure collision distance
1000 * and flow control are called.
1001 **/
1002static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1003{
1004 u32 ctrl, led_ctrl;
1005 s32 ret_val;
1006 bool link;
1007
1008 ctrl = rd32(E1000_CTRL);
1009 ctrl |= E1000_CTRL_SLU;
1010 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1011 wr32(E1000_CTRL, ctrl);
1012
1013 switch (hw->phy.type) {
1014 case e1000_phy_m88:
1015 ret_val = igb_copper_link_setup_m88(hw);
1016 break;
1017 case e1000_phy_igp_3:
1018 ret_val = igb_copper_link_setup_igp(hw);
1019 /* Setup activity LED */
1020 led_ctrl = rd32(E1000_LEDCTL);
1021 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1022 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1023 wr32(E1000_LEDCTL, led_ctrl);
1024 break;
1025 default:
1026 ret_val = -E1000_ERR_PHY;
1027 break;
1028 }
1029
1030 if (ret_val)
1031 goto out;
1032
1033 if (hw->mac.autoneg) {
1034 /*
1035 * Setup autoneg and flow control advertisement
1036 * and perform autonegotiation.
1037 */
1038 ret_val = igb_copper_link_autoneg(hw);
1039 if (ret_val)
1040 goto out;
1041 } else {
1042 /*
1043 * PHY will be set to 10H, 10F, 100H or 100F
1044 * depending on user settings.
1045 */
652fff32 1046 hw_dbg("Forcing Speed and Duplex\n");
9d5c8243
AK		 1047 ret_val = igb_phy_force_speed_duplex(hw);
1048 if (ret_val) {
652fff32 1049 hw_dbg("Error Forcing Speed and Duplex\n");
9d5c8243
AK		 1050 goto out;
1051 }
1052 }
1053
1054 ret_val = igb_configure_pcs_link_82575(hw);
1055 if (ret_val)
1056 goto out;
1057
1058 /*
1059 * Check link status. Wait up to 100 microseconds for link to become
1060 * valid.
1061 */
652fff32 1062 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
9d5c8243
AK		 1063 if (ret_val)
1064 goto out;
1065
1066 if (link) {
652fff32 1067 hw_dbg("Valid link established!!!\n");
9d5c8243
AK		 1068 /* Config the MAC and PHY after link is up */
1069 igb_config_collision_dist(hw);
1070 ret_val = igb_config_fc_after_link_up(hw);
1071 } else {
652fff32 1072 hw_dbg("Unable to establish link!!!\n");
9d5c8243
AK		 1073 }
1074
1075out:
1076 return ret_val;
1077}
1078
1079/**
733596be 1080 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
9d5c8243
AK		 1081 * @hw: pointer to the HW structure
1082 *
1083 * Configures speed and duplex for fiber and serdes links.
1084 **/
1085static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1086{
1087 u32 reg;
1088
1089 /*
1090 * On the 82575, SerDes loopback mode persists until it is
1091 * explicitly turned off or a power cycle is performed. A read to
1092 * the register does not indicate its status. Therefore, we ensure
1093 * loopback mode is disabled during initialization.
1094 */
1095 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1096
1097 /* Force link up, set 1gb, set both sw defined pins */
1098 reg = rd32(E1000_CTRL);
1099 reg |= E1000_CTRL_SLU |
1100 E1000_CTRL_SPD_1000 |
1101 E1000_CTRL_FRCSPD |
1102 E1000_CTRL_SWDPIN0 |
1103 E1000_CTRL_SWDPIN1;
1104 wr32(E1000_CTRL, reg);
1105
1106 /* Set switch control to serdes energy detect */
1107 reg = rd32(E1000_CONNSW);
1108 reg |= E1000_CONNSW_ENRGSRC;
1109 wr32(E1000_CONNSW, reg);
1110
1111 /*
1112 * New SerDes mode allows for forcing speed or autonegotiating speed
1113 * at 1gb. Autoneg should be default set by most drivers. This is the
1114 * mode that will be compatible with older link partners and switches.
1115 * However, both are supported by the hardware and some drivers/tools.
1116 */
1117 reg = rd32(E1000_PCS_LCTL);
1118
1119 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1120 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1121
1122 if (hw->mac.autoneg) {
1123 /* Set PCS register for autoneg */
1124 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1125 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1126 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1127 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
652fff32 1128 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
9d5c8243
AK		 1129 } else {
1130 /* Set PCS register for forced speed */
1131 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1132 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1133 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1134 E1000_PCS_LCTL_FSD | /* Force Speed */
1135 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
652fff32 1136 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
9d5c8243 1137 }
726c09e7
AD		 1138
1139 if (hw->mac.type == e1000_82576) {
1140 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1141 igb_force_mac_fc(hw);
1142 }
1143
9d5c8243
AK		 1144 wr32(E1000_PCS_LCTL, reg);
1145
1146 return 0;
1147}
1148
1149/**
733596be 1150 * igb_configure_pcs_link_82575 - Configure PCS link
9d5c8243
AK		 1151 * @hw: pointer to the HW structure
1152 *
1153 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1154 * only used on copper connections where the serialized gigabit media
1155 * independent interface (sgmii) is being used. Configures the link
1156 * for auto-negotiation or forces speed/duplex.
1157 **/
1158static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1159{
1160 struct e1000_mac_info *mac = &hw->mac;
1161 u32 reg = 0;
1162
1163 if (hw->phy.media_type != e1000_media_type_copper ||
1164 !(igb_sgmii_active_82575(hw)))
1165 goto out;
1166
1167 /* For SGMII, we need to issue a PCS autoneg restart */
1168 reg = rd32(E1000_PCS_LCTL);
1169
1170 /* AN time out should be disabled for SGMII mode */
1171 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1172
1173 if (mac->autoneg) {
1174 /* Make sure forced speed and force link are not set */
1175 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1176
1177 /*
1178 * The PHY should be setup prior to calling this function.
1179 * All we need to do is restart autoneg and enable autoneg.
1180 */
1181 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1182 } else {
652fff32 1183 /* Set PCS register for forced speed */
9d5c8243
AK		 1184
1185 /* Turn off bits for full duplex, speed, and autoneg */
1186 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1187 E1000_PCS_LCTL_FSV_100 |
1188 E1000_PCS_LCTL_FDV_FULL |
1189 E1000_PCS_LCTL_AN_ENABLE);
1190
1191 /* Check for duplex first */
1192 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1193 reg |= E1000_PCS_LCTL_FDV_FULL;
1194
1195 /* Now set speed */
1196 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1197 reg |= E1000_PCS_LCTL_FSV_100;
1198
1199 /* Force speed and force link */
1200 reg |= E1000_PCS_LCTL_FSD |
1201 E1000_PCS_LCTL_FORCE_LINK |
1202 E1000_PCS_LCTL_FLV_LINK_UP;
1203
652fff32 1204 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
9d5c8243
AK		 1205 reg);
1206 }
1207 wr32(E1000_PCS_LCTL, reg);
1208
1209out:
1210 return 0;
1211}
1212
1213/**
733596be 1214 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1215 * @hw: pointer to the HW structure
1216 *
1217 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1218 * which can be enabled for use in the embedded applications. Simply
1219 * return the current state of the sgmii interface.
1220 **/
1221static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1222{
1223 struct e1000_dev_spec_82575 *dev_spec;
1224 bool ret_val;
1225
1226 if (hw->mac.type != e1000_82575) {
1227 ret_val = false;
1228 goto out;
1229 }
1230
1231 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1232
1233 ret_val = dev_spec->sgmii_active;
1234
1235out:
1236 return ret_val;
1237}
1238
1239/**
733596be 1240 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1241 * @hw: pointer to the HW structure
1242 *
1243 * Inits recommended HW defaults after a reset when there is no EEPROM
1244 * detected. This is only for the 82575.
1245 **/
1246static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1247{
1248 if (hw->mac.type == e1000_82575) {
652fff32 1249 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1250 /* SerDes configuration via SERDESCTRL */
1251 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1252 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1253 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1254 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1255
1256 /* CCM configuration via CCMCTL register */
1257 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1258 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1259
1260 /* PCIe lanes configuration */
1261 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1262 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1263 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1264 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1265
1266 /* PCIe PLL Configuration */
1267 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1268 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1269 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1270 }
1271
1272 return 0;
1273}
1274
1275/**
733596be 1276 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1277 * @hw: pointer to the HW structure
1278 **/
1279static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1280{
1281 s32 ret_val = 0;
1282
1283 if (igb_check_alt_mac_addr(hw))
1284 ret_val = igb_read_mac_addr(hw);
1285
1286 return ret_val;
1287}
1288
1289/**
733596be 1290 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1291 * @hw: pointer to the HW structure
1292 *
1293 * Clears the hardware counters by reading the counter registers.
1294 **/
1295static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1296{
1297 u32 temp;
1298
1299 igb_clear_hw_cntrs_base(hw);
1300
1301 temp = rd32(E1000_PRC64);
1302 temp = rd32(E1000_PRC127);
1303 temp = rd32(E1000_PRC255);
1304 temp = rd32(E1000_PRC511);
1305 temp = rd32(E1000_PRC1023);
1306 temp = rd32(E1000_PRC1522);
1307 temp = rd32(E1000_PTC64);
1308 temp = rd32(E1000_PTC127);
1309 temp = rd32(E1000_PTC255);
1310 temp = rd32(E1000_PTC511);
1311 temp = rd32(E1000_PTC1023);
1312 temp = rd32(E1000_PTC1522);
1313
1314 temp = rd32(E1000_ALGNERRC);
1315 temp = rd32(E1000_RXERRC);
1316 temp = rd32(E1000_TNCRS);
1317 temp = rd32(E1000_CEXTERR);
1318 temp = rd32(E1000_TSCTC);
1319 temp = rd32(E1000_TSCTFC);
1320
1321 temp = rd32(E1000_MGTPRC);
1322 temp = rd32(E1000_MGTPDC);
1323 temp = rd32(E1000_MGTPTC);
1324
1325 temp = rd32(E1000_IAC);
1326 temp = rd32(E1000_ICRXOC);
1327
1328 temp = rd32(E1000_ICRXPTC);
1329 temp = rd32(E1000_ICRXATC);
1330 temp = rd32(E1000_ICTXPTC);
1331 temp = rd32(E1000_ICTXATC);
1332 temp = rd32(E1000_ICTXQEC);
1333 temp = rd32(E1000_ICTXQMTC);
1334 temp = rd32(E1000_ICRXDMTC);
1335
1336 temp = rd32(E1000_CBTMPC);
1337 temp = rd32(E1000_HTDPMC);
1338 temp = rd32(E1000_CBRMPC);
1339 temp = rd32(E1000_RPTHC);
1340 temp = rd32(E1000_HGPTC);
1341 temp = rd32(E1000_HTCBDPC);
1342 temp = rd32(E1000_HGORCL);
1343 temp = rd32(E1000_HGORCH);
1344 temp = rd32(E1000_HGOTCL);
1345 temp = rd32(E1000_HGOTCH);
1346 temp = rd32(E1000_LENERRS);
1347
1348 /* This register should not be read in copper configurations */
1349 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1350 temp = rd32(E1000_SCVPC);
1351}
1352
662d7205
AD		 1353/**
1354 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1355 * @hw: pointer to the HW structure
1356 *
1357 * After rx enable if managability is enabled then there is likely some
1358 * bad data at the start of the fifo and possibly in the DMA fifo. This
1359 * function clears the fifos and flushes any packets that came in as rx was
1360 * being enabled.
1361 **/
1362void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1363{
1364 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1365 int i, ms_wait;
1366
1367 if (hw->mac.type != e1000_82575 ||
1368 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1369 return;
1370
1371 /* Disable all RX queues */
1372 for (i = 0; i < 4; i++) {
1373 rxdctl[i] = rd32(E1000_RXDCTL(i));
1374 wr32(E1000_RXDCTL(i),
1375 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1376 }
1377 /* Poll all queues to verify they have shut down */
1378 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1379 msleep(1);
1380 rx_enabled = 0;
1381 for (i = 0; i < 4; i++)
1382 rx_enabled |= rd32(E1000_RXDCTL(i));
1383 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1384 break;
1385 }
1386
1387 if (ms_wait == 10)
1388 hw_dbg("Queue disable timed out after 10ms\n");
1389
1390 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1391 * incoming packets are rejected. Set enable and wait 2ms so that
1392 * any packet that was coming in as RCTL.EN was set is flushed
1393 */
1394 rfctl = rd32(E1000_RFCTL);
1395 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1396
1397 rlpml = rd32(E1000_RLPML);
1398 wr32(E1000_RLPML, 0);
1399
1400 rctl = rd32(E1000_RCTL);
1401 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1402 temp_rctl |= E1000_RCTL_LPE;
1403
1404 wr32(E1000_RCTL, temp_rctl);
1405 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1406 wrfl();
1407 msleep(2);
1408
1409 /* Enable RX queues that were previously enabled and restore our
1410 * previous state
1411 */
1412 for (i = 0; i < 4; i++)
1413 wr32(E1000_RXDCTL(i), rxdctl[i]);
1414 wr32(E1000_RCTL, rctl);
1415 wrfl();
1416
1417 wr32(E1000_RLPML, rlpml);
1418 wr32(E1000_RFCTL, rfctl);
1419
1420 /* Flush receive errors generated by workaround */
1421 rd32(E1000_ROC);
1422 rd32(E1000_RNBC);
1423 rd32(E1000_MPC);
1424}
1425
9d5c8243
AK		 1426static struct e1000_mac_operations e1000_mac_ops_82575 = {
1427 .reset_hw = igb_reset_hw_82575,
1428 .init_hw = igb_init_hw_82575,
1429 .check_for_link = igb_check_for_link_82575,
2d064c06 1430 .rar_set = igb_rar_set,
9d5c8243
AK		 1431 .read_mac_addr = igb_read_mac_addr_82575,
1432 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1433};
1434
1435static struct e1000_phy_operations e1000_phy_ops_82575 = {
1436 .acquire_phy = igb_acquire_phy_82575,
1437 .get_cfg_done = igb_get_cfg_done_82575,
1438 .release_phy = igb_release_phy_82575,
1439};
1440
1441static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1442 .acquire_nvm = igb_acquire_nvm_82575,
1443 .read_nvm = igb_read_nvm_eerd,
1444 .release_nvm = igb_release_nvm_82575,
1445 .write_nvm = igb_write_nvm_spi,
1446};
1447
1448const struct e1000_info e1000_82575_info = {
1449 .get_invariants = igb_get_invariants_82575,
1450 .mac_ops = &e1000_mac_ops_82575,
1451 .phy_ops = &e1000_phy_ops_82575,
1452 .nvm_ops = &e1000_nvm_ops_82575,
1453};
1454
Linux kernel - Deliverables
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