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1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
652fff32 | 4 | Copyright(c) 2007 - 2008 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _E1000_82575_H_ | |
29 | #define _E1000_82575_H_ | |
30 | ||
662d7205 AD |
31 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); |
32 | ||
9d5c8243 AK |
33 | #define E1000_RAR_ENTRIES_82575 16 |
34 | ||
35 | /* SRRCTL bit definitions */ | |
36 | #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ | |
37 | #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ | |
38 | #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 | |
39 | #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 | |
40 | ||
41 | #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 | |
42 | #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 | |
43 | #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 | |
44 | #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 | |
45 | ||
46 | #define E1000_EICR_TX_QUEUE ( \ | |
47 | E1000_EICR_TX_QUEUE0 | \ | |
48 | E1000_EICR_TX_QUEUE1 | \ | |
49 | E1000_EICR_TX_QUEUE2 | \ | |
50 | E1000_EICR_TX_QUEUE3) | |
51 | ||
52 | #define E1000_EICR_RX_QUEUE ( \ | |
53 | E1000_EICR_RX_QUEUE0 | \ | |
54 | E1000_EICR_RX_QUEUE1 | \ | |
55 | E1000_EICR_RX_QUEUE2 | \ | |
56 | E1000_EICR_RX_QUEUE3) | |
57 | ||
58 | #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE | |
59 | #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE | |
60 | ||
652fff32 | 61 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ |
9d5c8243 AK |
62 | |
63 | /* Receive Descriptor - Advanced */ | |
64 | union e1000_adv_rx_desc { | |
65 | struct { | |
6d8126f9 AV |
66 | __le64 pkt_addr; /* Packet buffer address */ |
67 | __le64 hdr_addr; /* Header buffer address */ | |
9d5c8243 AK |
68 | } read; |
69 | struct { | |
70 | struct { | |
71 | struct { | |
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72 | __le16 pkt_info; /* RSS type, Packet type */ |
73 | __le16 hdr_info; /* Split Header, | |
74 | * header buffer length */ | |
9d5c8243 AK |
75 | } lo_dword; |
76 | union { | |
6d8126f9 | 77 | __le32 rss; /* RSS Hash */ |
9d5c8243 | 78 | struct { |
6d8126f9 AV |
79 | __le16 ip_id; /* IP id */ |
80 | __le16 csum; /* Packet Checksum */ | |
9d5c8243 AK |
81 | } csum_ip; |
82 | } hi_dword; | |
83 | } lower; | |
84 | struct { | |
6d8126f9 AV |
85 | __le32 status_error; /* ext status/error */ |
86 | __le16 length; /* Packet length */ | |
87 | __le16 vlan; /* VLAN tag */ | |
9d5c8243 AK |
88 | } upper; |
89 | } wb; /* writeback */ | |
90 | }; | |
91 | ||
92 | #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 | |
93 | #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 | |
94 | ||
95 | /* RSS Hash results */ | |
96 | ||
97 | /* RSS Packet Types as indicated in the receive descriptor */ | |
98 | ||
99 | /* Transmit Descriptor - Advanced */ | |
100 | union e1000_adv_tx_desc { | |
101 | struct { | |
6d8126f9 AV |
102 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
103 | __le32 cmd_type_len; | |
104 | __le32 olinfo_status; | |
9d5c8243 AK |
105 | } read; |
106 | struct { | |
6d8126f9 AV |
107 | __le64 rsvd; /* Reserved */ |
108 | __le32 nxtseq_seed; | |
109 | __le32 status; | |
9d5c8243 AK |
110 | } wb; |
111 | }; | |
112 | ||
113 | /* Adv Transmit Descriptor Config Masks */ | |
114 | #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ | |
115 | #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ | |
116 | #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
117 | #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ | |
118 | #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ | |
119 | #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ | |
120 | #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | |
121 | ||
122 | /* Context descriptors */ | |
123 | struct e1000_adv_tx_context_desc { | |
6d8126f9 AV |
124 | __le32 vlan_macip_lens; |
125 | __le32 seqnum_seed; | |
126 | __le32 type_tucmd_mlhl; | |
127 | __le32 mss_l4len_idx; | |
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128 | }; |
129 | ||
130 | #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ | |
131 | #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ | |
132 | #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ | |
133 | /* IPSec Encrypt Enable for ESP */ | |
134 | #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ | |
135 | #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ | |
136 | /* Adv ctxt IPSec SA IDX mask */ | |
137 | /* Adv ctxt IPSec ESP len mask */ | |
138 | ||
139 | /* Additional Transmit Descriptor Control definitions */ | |
140 | #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ | |
141 | /* Tx Queue Arbitration Priority 0=low, 1=high */ | |
142 | ||
143 | /* Additional Receive Descriptor Control definitions */ | |
144 | #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ | |
145 | ||
146 | /* Direct Cache Access (DCA) definitions */ | |
147 | ||
148 | ||
149 | ||
652fff32 | 150 | #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ |
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151 | |
152 | #endif |