[deliverable/linux.git] / drivers / net / igb / e1000_hw.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/io.h>

#include "e1000_regs.h"
#include "e1000_defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82576                    0x10C9
#define E1000_DEV_ID_82576_FIBER              0x10E6
#define E1000_DEV_ID_82576_SERDES             0x10E7
#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
#define E1000_DEV_ID_82576_NS                 0x150A
#define E1000_DEV_ID_82575EB_COPPER           0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6

#define E1000_REVISION_2 2
#define E1000_REVISION_4 4

#define E1000_FUNC_1     1

enum e1000_mac_type {
	e1000_undefined = 0,
	e1000_82575,
	e1000_82576,
	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_fiber = 2,
	e1000_media_type_internal_serdes = 3,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_eeprom_microwire,
	e1000_nvm_flash_hw,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large,
	e1000_nvm_override_microwire_small,
	e1000_nvm_override_microwire_large
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
};

enum e1000_bus_type {
	e1000_bus_type_unknown = 0,
	e1000_bus_type_pci,
	e1000_bus_type_pcix,
	e1000_bus_type_pci_express,
	e1000_bus_type_reserved
};

enum e1000_bus_speed {
	e1000_bus_speed_unknown = 0,
	e1000_bus_speed_33,
	e1000_bus_speed_66,
	e1000_bus_speed_100,
	e1000_bus_speed_120,
	e1000_bus_speed_133,
	e1000_bus_speed_2500,
	e1000_bus_speed_5000,
	e1000_bus_speed_reserved
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_pcie_x8 = 8,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity {
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_type {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
	u64 cbtmpc;
	u64 htdpmc;
	u64 cbrdpc;
	u64 cbrmpc;
	u64 rpthc;
	u64 hgptc;
	u64 htcbdpc;
	u64 hgorc;
	u64 hgotc;
	u64 lenerrs;
	u64 scvpc;
	u64 hrmpc;
	u64 doosync;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8  status;
	u8  reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8  reserved3;
	u8  checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH     252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8  command_id;
	u8  checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_nvm.h"
#include "e1000_mbx.h"

struct e1000_mac_operations {
	s32  (*check_for_link)(struct e1000_hw *);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32  (*setup_physical_interface)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
	s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
};

struct e1000_phy_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*check_reset_block)(struct e1000_hw *);
	s32  (*force_speed_duplex)(struct e1000_hw *);
	s32  (*get_cfg_done)(struct e1000_hw *hw);
	s32  (*get_cable_length)(struct e1000_hw *);
	s32  (*get_phy_info)(struct e1000_hw *);
	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*reset)(struct e1000_hw *);
	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32  (*write_reg)(struct e1000_hw *, u32, u16);
};

struct e1000_nvm_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
};

struct e1000_info {
	s32 (*get_invariants)(struct e1000_hw *);
	struct e1000_mac_operations *mac_ops;
	struct e1000_phy_operations *phy_ops;
	struct e1000_nvm_operations *nvm_ops;
};

extern const struct e1000_info e1000_82575_info;

struct e1000_mac_info {
	struct e1000_mac_operations ops;

	u8 addr[6];
	u8 perm_addr[6];

	enum e1000_mac_type type;

	u32 collision_delta;
	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 tx_packet_delta;
	u32 txcw;

	u16 current_ifs_val;
	u16 ifs_max_val;
	u16 ifs_min_val;
	u16 ifs_ratio;
	u16 ifs_step_size;
	u16 mta_reg_count;
	u16 rar_entry_count;

	u8  forced_speed_duplex;

	bool adaptive_ifs;
	bool arc_subsystem_valid;
	bool asf_firmware_present;
	bool autoneg;
	bool autoneg_failed;
	bool disable_hw_init_bits;
	bool get_link_status;
	bool ifs_params_forced;
	bool in_ifs_mode;
	bool report_tx_early;
	bool serdes_has_link;
	bool tx_pkt_filtering;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us; /* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool reset_disable;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;

	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_type type;
	enum e1000_bus_speed speed;
	enum e1000_bus_width width;

	u32 snoop;

	u16 func;
	u16 pci_cmd_word;
};

struct e1000_fc_info {
	u32 high_water;     /* Flow control high-water mark */
	u32 low_water;      /* Flow control low-water mark */
	u16 pause_time;     /* Flow control pause timer */
	bool send_xon;      /* Flow control send XON */
	bool strict_ieee;   /* Strict IEEE mode */
	enum e1000_fc_type type; /* Type of flow control */
	enum e1000_fc_type original_type;
};

struct e1000_mbx_operations {
	s32 (*init_params)(struct e1000_hw *hw);
	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*check_for_msg)(struct e1000_hw *, u16);
	s32 (*check_for_ack)(struct e1000_hw *, u16);
	s32 (*check_for_rst)(struct e1000_hw *, u16);
};

struct e1000_mbx_stats {
	u32 msgs_tx;
	u32 msgs_rx;

	u32 acks;
	u32 reqs;
	u32 rsts;
};

struct e1000_mbx_info {
	struct e1000_mbx_operations ops;
	struct e1000_mbx_stats stats;
	u32 timeout;
	u32 usec_delay;
	u16 size;
};

struct e1000_dev_spec_82575 {
	bool sgmii_active;
};

struct e1000_hw {
	void *back;

	u8 __iomem *hw_addr;
	u8 __iomem *flash_address;
	unsigned long io_base;

	struct e1000_mac_info  mac;
	struct e1000_fc_info   fc;
	struct e1000_phy_info  phy;
	struct e1000_nvm_info  nvm;
	struct e1000_bus_info  bus;
	struct e1000_mbx_info mbx;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82575	_82575;
	} dev_spec;

	u16 device_id;
	u16 subsystem_vendor_id;
	u16 subsystem_device_id;
	u16 vendor_id;

	u8  revision_id;
};

#ifdef DEBUG
extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
#define hw_dbg(format, arg...) \
	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
#else
#define hw_dbg(format, arg...)
#endif

#endif
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _E1000_HW_H_
	29	#define _E1000_HW_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/delay.h>
	33	#include <linux/io.h>
	34
9d5c8243 AK	35	#include "e1000_regs.h"
	36	#include "e1000_defines.h"
	37
	38	struct e1000_hw;
	39
2d064c06 AD	40	#define E1000_DEV_ID_82576 0x10C9
	41	#define E1000_DEV_ID_82576_FIBER 0x10E6
	42	#define E1000_DEV_ID_82576_SERDES 0x10E7
c8ea5ea9	43	#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
9eb2341d	44	#define E1000_DEV_ID_82576_NS 0x150A
9d5c8243 AK	45	#define E1000_DEV_ID_82575EB_COPPER 0x10A7
	46	#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
	47	#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
	48
	49	#define E1000_REVISION_2 2
	50	#define E1000_REVISION_4 4
	51
	52	#define E1000_FUNC_1 1
	53
	54	enum e1000_mac_type {
	55	e1000_undefined = 0,
	56	e1000_82575,
2d064c06	57	e1000_82576,
9d5c8243 AK	58	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	59	};
	60
	61	enum e1000_media_type {
	62	e1000_media_type_unknown = 0,
	63	e1000_media_type_copper = 1,
	64	e1000_media_type_fiber = 2,
	65	e1000_media_type_internal_serdes = 3,
	66	e1000_num_media_types
	67	};
	68
	69	enum e1000_nvm_type {
	70	e1000_nvm_unknown = 0,
	71	e1000_nvm_none,
	72	e1000_nvm_eeprom_spi,
	73	e1000_nvm_eeprom_microwire,
	74	e1000_nvm_flash_hw,
	75	e1000_nvm_flash_sw
	76	};
	77
	78	enum e1000_nvm_override {
	79	e1000_nvm_override_none = 0,
	80	e1000_nvm_override_spi_small,
	81	e1000_nvm_override_spi_large,
	82	e1000_nvm_override_microwire_small,
	83	e1000_nvm_override_microwire_large
	84	};
	85
	86	enum e1000_phy_type {
	87	e1000_phy_unknown = 0,
	88	e1000_phy_none,
	89	e1000_phy_m88,
	90	e1000_phy_igp,
	91	e1000_phy_igp_2,
	92	e1000_phy_gg82563,
	93	e1000_phy_igp_3,
	94	e1000_phy_ife,
	95	};
	96
	97	enum e1000_bus_type {
	98	e1000_bus_type_unknown = 0,
	99	e1000_bus_type_pci,
	100	e1000_bus_type_pcix,
	101	e1000_bus_type_pci_express,
	102	e1000_bus_type_reserved
	103	};
	104
	105	enum e1000_bus_speed {
	106	e1000_bus_speed_unknown = 0,
	107	e1000_bus_speed_33,
	108	e1000_bus_speed_66,
	109	e1000_bus_speed_100,
	110	e1000_bus_speed_120,
	111	e1000_bus_speed_133,
	112	e1000_bus_speed_2500,
	113	e1000_bus_speed_5000,
	114	e1000_bus_speed_reserved
	115	};
	116
	117	enum e1000_bus_width {
	118	e1000_bus_width_unknown = 0,
	119	e1000_bus_width_pcie_x1,
	120	e1000_bus_width_pcie_x2,
	121	e1000_bus_width_pcie_x4 = 4,
122	e1000_bus_width_pcie_x8 = 8,
123	e1000_bus_width_32,
124	e1000_bus_width_64,
125	e1000_bus_width_reserved
126	};
127
128	enum e1000_1000t_rx_status {
129	e1000_1000t_rx_status_not_ok = 0,
130	e1000_1000t_rx_status_ok,
131	e1000_1000t_rx_status_undefined = 0xFF
132	};
133
134	enum e1000_rev_polarity {
135	e1000_rev_polarity_normal = 0,
136	e1000_rev_polarity_reversed,
137	e1000_rev_polarity_undefined = 0xFF
138	};
139
140	enum e1000_fc_type {
141	e1000_fc_none = 0,
142	e1000_fc_rx_pause,
143	e1000_fc_tx_pause,
144	e1000_fc_full,
145	e1000_fc_default = 0xFF
146	};
147
9d5c8243 AK	148	/* Statistics counters collected by the MAC */
	149	struct e1000_hw_stats {
	150	u64 crcerrs;
	151	u64 algnerrc;
	152	u64 symerrs;
	153	u64 rxerrc;
	154	u64 mpc;
	155	u64 scc;
	156	u64 ecol;
	157	u64 mcc;
	158	u64 latecol;
	159	u64 colc;
	160	u64 dc;
	161	u64 tncrs;
	162	u64 sec;
	163	u64 cexterr;
	164	u64 rlec;
	165	u64 xonrxc;
	166	u64 xontxc;
	167	u64 xoffrxc;
	168	u64 xofftxc;
	169	u64 fcruc;
	170	u64 prc64;
	171	u64 prc127;
	172	u64 prc255;
	173	u64 prc511;
	174	u64 prc1023;
	175	u64 prc1522;
	176	u64 gprc;
	177	u64 bprc;
	178	u64 mprc;
	179	u64 gptc;
	180	u64 gorc;
	181	u64 gotc;
	182	u64 rnbc;
	183	u64 ruc;
	184	u64 rfc;
	185	u64 roc;
	186	u64 rjc;
	187	u64 mgprc;
	188	u64 mgpdc;
	189	u64 mgptc;
	190	u64 tor;
	191	u64 tot;
	192	u64 tpr;
	193	u64 tpt;
	194	u64 ptc64;
	195	u64 ptc127;
	196	u64 ptc255;
	197	u64 ptc511;
	198	u64 ptc1023;
	199	u64 ptc1522;
	200	u64 mptc;
	201	u64 bptc;
	202	u64 tsctc;
	203	u64 tsctfc;
	204	u64 iac;
	205	u64 icrxptc;
	206	u64 icrxatc;
	207	u64 ictxptc;
	208	u64 ictxatc;
	209	u64 ictxqec;
	210	u64 ictxqmtc;
	211	u64 icrxdmtc;
212	u64 icrxoc;
213	u64 cbtmpc;
214	u64 htdpmc;
215	u64 cbrdpc;
216	u64 cbrmpc;
217	u64 rpthc;
218	u64 hgptc;
219	u64 htcbdpc;
220	u64 hgorc;
221	u64 hgotc;
222	u64 lenerrs;
223	u64 scvpc;
224	u64 hrmpc;
dda0e083	225	u64 doosync;
9d5c8243 AK	226	};
	227
	228	struct e1000_phy_stats {
	229	u32 idle_errors;
	230	u32 receive_errors;
	231	};
	232
	233	struct e1000_host_mng_dhcp_cookie {
	234	u32 signature;
	235	u8 status;
	236	u8 reserved0;
	237	u16 vlan_id;
	238	u32 reserved1;
	239	u16 reserved2;
	240	u8 reserved3;
	241	u8 checksum;
	242	};
	243
	244	/* Host Interface "Rev 1" */
	245	struct e1000_host_command_header {
	246	u8 command_id;
	247	u8 command_length;
	248	u8 command_options;
	249	u8 checksum;
	250	};
	251
	252	#define E1000_HI_MAX_DATA_LENGTH 252
	253	struct e1000_host_command_info {
	254	struct e1000_host_command_header command_header;
	255	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	256	};
	257
	258	/* Host Interface "Rev 2" */
	259	struct e1000_host_mng_command_header {
	260	u8 command_id;
	261	u8 checksum;
	262	u16 reserved1;
	263	u16 reserved2;
	264	u16 command_length;
	265	};
	266
	267	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
	268	struct e1000_host_mng_command_info {
	269	struct e1000_host_mng_command_header command_header;
	270	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	271	};
	272
	273	#include "e1000_mac.h"
	274	#include "e1000_phy.h"
	275	#include "e1000_nvm.h"
4ae196df	276	#include "e1000_mbx.h"
9d5c8243 AK	277
	278	struct e1000_mac_operations {
	279	s32 (check_for_link)(struct e1000_hw );
	280	s32 (reset_hw)(struct e1000_hw );
	281	s32 (init_hw)(struct e1000_hw );
2d064c06	282	bool (check_mng_mode)(struct e1000_hw );
9d5c8243 AK	283	s32 (setup_physical_interface)(struct e1000_hw );
	284	void (rar_set)(struct e1000_hw , u8 *, u32);
	285	s32 (read_mac_addr)(struct e1000_hw );
	286	s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );
	287	};
	288
	289	struct e1000_phy_operations {
a8d2a0c2	290	s32 (acquire)(struct e1000_hw );
2d064c06	291	s32 (check_reset_block)(struct e1000_hw );
9d5c8243 AK	292	s32 (force_speed_duplex)(struct e1000_hw );
	293	s32 (get_cfg_done)(struct e1000_hw hw);
	294	s32 (get_cable_length)(struct e1000_hw );
	295	s32 (get_phy_info)(struct e1000_hw );
a8d2a0c2 AD	296	s32 (read_reg)(struct e1000_hw , u32, u16 *);
	297	void (release)(struct e1000_hw );
	298	s32 (reset)(struct e1000_hw );
9d5c8243 AK	299	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
9d5c8243 AK	300	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
a8d2a0c2	301	s32 (write_reg)(struct e1000_hw , u32, u16);
9d5c8243 AK	302	};
	303
	304	struct e1000_nvm_operations {
312c75ae AD	305	s32 (acquire)(struct e1000_hw );
	306	s32 (read)(struct e1000_hw , u16, u16, u16 *);
	307	void (release)(struct e1000_hw );
	308	s32 (write)(struct e1000_hw , u16, u16, u16 *);
9d5c8243 AK	309	};
	310
	311	struct e1000_info {
	312	s32 (get_invariants)(struct e1000_hw );
	313	struct e1000_mac_operations *mac_ops;
	314	struct e1000_phy_operations *phy_ops;
	315	struct e1000_nvm_operations *nvm_ops;
	316	};
	317
	318	extern const struct e1000_info e1000_82575_info;
	319
	320	struct e1000_mac_info {
	321	struct e1000_mac_operations ops;
	322
	323	u8 addr[6];
	324	u8 perm_addr[6];
	325
	326	enum e1000_mac_type type;
	327
	328	u32 collision_delta;
	329	u32 ledctl_default;
	330	u32 ledctl_mode1;
	331	u32 ledctl_mode2;
	332	u32 mc_filter_type;
	333	u32 tx_packet_delta;
	334	u32 txcw;
	335
	336	u16 current_ifs_val;
	337	u16 ifs_max_val;
	338	u16 ifs_min_val;
	339	u16 ifs_ratio;
	340	u16 ifs_step_size;
	341	u16 mta_reg_count;
	342	u16 rar_entry_count;
	343
	344	u8 forced_speed_duplex;
	345
	346	bool adaptive_ifs;
	347	bool arc_subsystem_valid;
	348	bool asf_firmware_present;
	349	bool autoneg;
	350	bool autoneg_failed;
9d5c8243 AK	351	bool disable_hw_init_bits;
	352	bool get_link_status;
	353	bool ifs_params_forced;
	354	bool in_ifs_mode;
	355	bool report_tx_early;
	356	bool serdes_has_link;
	357	bool tx_pkt_filtering;
	358	};
	359
	360	struct e1000_phy_info {
	361	struct e1000_phy_operations ops;
	362
	363	enum e1000_phy_type type;
	364
	365	enum e1000_1000t_rx_status local_rx;
	366	enum e1000_1000t_rx_status remote_rx;
	367	enum e1000_ms_type ms_type;
	368	enum e1000_ms_type original_ms_type;
	369	enum e1000_rev_polarity cable_polarity;
	370	enum e1000_smart_speed smart_speed;
	371
	372	u32 addr;
	373	u32 id;
	374	u32 reset_delay_us; /* in usec */
	375	u32 revision;
	376
	377	enum e1000_media_type media_type;
	378
	379	u16 autoneg_advertised;
	380	u16 autoneg_mask;
	381	u16 cable_length;
	382	u16 max_cable_length;
	383	u16 min_cable_length;
	384
	385	u8 mdix;
	386
	387	bool disable_polarity_correction;
	388	bool is_mdix;
	389	bool polarity_correction;
	390	bool reset_disable;
	391	bool speed_downgraded;
	392	bool autoneg_wait_to_complete;
	393	};
	394
	395	struct e1000_nvm_info {
	396	struct e1000_nvm_operations ops;
	397
	398	enum e1000_nvm_type type;
	399	enum e1000_nvm_override override;
	400
	401	u32 flash_bank_size;
	402	u32 flash_base_addr;
	403
	404	u16 word_size;
	405	u16 delay_usec;
	406	u16 address_bits;
	407	u16 opcode_bits;
	408	u16 page_size;
	409	};
	410
	411	struct e1000_bus_info {
	412	enum e1000_bus_type type;
	413	enum e1000_bus_speed speed;
	414	enum e1000_bus_width width;
415
416	u32 snoop;
417
418	u16 func;
419	u16 pci_cmd_word;
420	};
421
422	struct e1000_fc_info {
423	u32 high_water; /* Flow control high-water mark */
424	u32 low_water; /* Flow control low-water mark */
425	u16 pause_time; /* Flow control pause timer */
426	bool send_xon; /* Flow control send XON */
427	bool strict_ieee; /* Strict IEEE mode */
428	enum e1000_fc_type type; /* Type of flow control */
429	enum e1000_fc_type original_type;
430	};
431
4ae196df AD	432	struct e1000_mbx_operations {
	433	s32 (init_params)(struct e1000_hw hw);
	434	s32 (read)(struct e1000_hw , u32 *, u16, u16);
	435	s32 (write)(struct e1000_hw , u32 *, u16, u16);
	436	s32 (read_posted)(struct e1000_hw , u32 *, u16, u16);
	437	s32 (write_posted)(struct e1000_hw , u32 *, u16, u16);
	438	s32 (check_for_msg)(struct e1000_hw , u16);
	439	s32 (check_for_ack)(struct e1000_hw , u16);
	440	s32 (check_for_rst)(struct e1000_hw , u16);
	441	};
	442
	443	struct e1000_mbx_stats {
	444	u32 msgs_tx;
	445	u32 msgs_rx;
	446
	447	u32 acks;
	448	u32 reqs;
	449	u32 rsts;
	450	};
	451
	452	struct e1000_mbx_info {
	453	struct e1000_mbx_operations ops;
	454	struct e1000_mbx_stats stats;
	455	u32 timeout;
	456	u32 usec_delay;
	457	u16 size;
	458	};
	459
c1889bfe AD	460	struct e1000_dev_spec_82575 {
	461	bool sgmii_active;
	462	};
	463
9d5c8243 AK	464	struct e1000_hw {
9d5c8243 AK	465	void *back;
9d5c8243 AK	466
	467	u8 __iomem *hw_addr;
	468	u8 __iomem *flash_address;
	469	unsigned long io_base;
	470
	471	struct e1000_mac_info mac;
	472	struct e1000_fc_info fc;
	473	struct e1000_phy_info phy;
	474	struct e1000_nvm_info nvm;
	475	struct e1000_bus_info bus;
4ae196df	476	struct e1000_mbx_info mbx;
9d5c8243 AK	477	struct e1000_host_mng_dhcp_cookie mng_cookie;
9d5c8243 AK	478
c1889bfe AD	479	union {
	480	struct e1000_dev_spec_82575 _82575;
	481	} dev_spec;
9d5c8243 AK	482
	483	u16 device_id;
	484	u16 subsystem_vendor_id;
	485	u16 subsystem_device_id;
	486	u16 vendor_id;
	487
	488	u8 revision_id;
	489	};
	490
	491	#ifdef DEBUG
	492	extern char igb_get_hw_dev_name(struct e1000_hw hw);
652fff32	493	#define hw_dbg(format, arg...) \
9d5c8243 AK	494	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
9d5c8243 AK	495	#else
652fff32	496	#define hw_dbg(format, arg...)
9d5c8243 AK	497	#endif
	498
	499	#endif