[deliverable/linux.git] / drivers / net / igb / e1000_hw.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/io.h>

#include "e1000_regs.h"
#include "e1000_defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82576                    0x10C9
#define E1000_DEV_ID_82576_FIBER              0x10E6
#define E1000_DEV_ID_82576_SERDES             0x10E7
#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
#define E1000_DEV_ID_82576_NS                 0x150A
#define E1000_DEV_ID_82576_NS_SERDES          0x1518
#define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
#define E1000_DEV_ID_82575EB_COPPER           0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6

#define E1000_REVISION_2 2
#define E1000_REVISION_4 4

#define E1000_FUNC_0     0
#define E1000_FUNC_1     1

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3

enum e1000_mac_type {
	e1000_undefined = 0,
	e1000_82575,
	e1000_82576,
	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_internal_serdes = 2,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_flash_hw,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large,
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
};

enum e1000_bus_type {
	e1000_bus_type_unknown = 0,
	e1000_bus_type_pci,
	e1000_bus_type_pcix,
	e1000_bus_type_pci_express,
	e1000_bus_type_reserved
};

enum e1000_bus_speed {
	e1000_bus_speed_unknown = 0,
	e1000_bus_speed_33,
	e1000_bus_speed_66,
	e1000_bus_speed_100,
	e1000_bus_speed_120,
	e1000_bus_speed_133,
	e1000_bus_speed_2500,
	e1000_bus_speed_5000,
	e1000_bus_speed_reserved
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_pcie_x8 = 8,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity {
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_mode {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
	u64 cbtmpc;
	u64 htdpmc;
	u64 cbrdpc;
	u64 cbrmpc;
	u64 rpthc;
	u64 hgptc;
	u64 htcbdpc;
	u64 hgorc;
	u64 hgotc;
	u64 lenerrs;
	u64 scvpc;
	u64 hrmpc;
	u64 doosync;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8  status;
	u8  reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8  reserved3;
	u8  checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH     252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8  command_id;
	u8  checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_nvm.h"
#include "e1000_mbx.h"

struct e1000_mac_operations {
	s32  (*check_for_link)(struct e1000_hw *);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32  (*setup_physical_interface)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
	s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
};

struct e1000_phy_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*check_reset_block)(struct e1000_hw *);
	s32  (*force_speed_duplex)(struct e1000_hw *);
	s32  (*get_cfg_done)(struct e1000_hw *hw);
	s32  (*get_cable_length)(struct e1000_hw *);
	s32  (*get_phy_info)(struct e1000_hw *);
	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*reset)(struct e1000_hw *);
	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32  (*write_reg)(struct e1000_hw *, u32, u16);
};

struct e1000_nvm_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
};

struct e1000_info {
	s32 (*get_invariants)(struct e1000_hw *);
	struct e1000_mac_operations *mac_ops;
	struct e1000_phy_operations *phy_ops;
	struct e1000_nvm_operations *nvm_ops;
};

extern const struct e1000_info e1000_82575_info;

struct e1000_mac_info {
	struct e1000_mac_operations ops;

	u8 addr[6];
	u8 perm_addr[6];

	enum e1000_mac_type type;

	u32 collision_delta;
	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 tx_packet_delta;
	u32 txcw;

	u16 current_ifs_val;
	u16 ifs_max_val;
	u16 ifs_min_val;
	u16 ifs_ratio;
	u16 ifs_step_size;
	u16 mta_reg_count;
	u16 uta_reg_count;

	/* Maximum size of the MTA register table in all supported adapters */
	#define MAX_MTA_REG 128
	u32 mta_shadow[MAX_MTA_REG];
	u16 rar_entry_count;

	u8  forced_speed_duplex;

	bool adaptive_ifs;
	bool arc_subsystem_valid;
	bool asf_firmware_present;
	bool autoneg;
	bool autoneg_failed;
	bool disable_hw_init_bits;
	bool get_link_status;
	bool ifs_params_forced;
	bool in_ifs_mode;
	bool report_tx_early;
	bool serdes_has_link;
	bool tx_pkt_filtering;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us; /* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool reset_disable;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;

	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_type type;
	enum e1000_bus_speed speed;
	enum e1000_bus_width width;

	u32 snoop;

	u16 func;
	u16 pci_cmd_word;
};

struct e1000_fc_info {
	u32 high_water;     /* Flow control high-water mark */
	u32 low_water;      /* Flow control low-water mark */
	u16 pause_time;     /* Flow control pause timer */
	bool send_xon;      /* Flow control send XON */
	bool strict_ieee;   /* Strict IEEE mode */
	enum e1000_fc_mode current_mode; /* Type of flow control */
	enum e1000_fc_mode requested_mode;
};

struct e1000_mbx_operations {
	s32 (*init_params)(struct e1000_hw *hw);
	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*check_for_msg)(struct e1000_hw *, u16);
	s32 (*check_for_ack)(struct e1000_hw *, u16);
	s32 (*check_for_rst)(struct e1000_hw *, u16);
};

struct e1000_mbx_stats {
	u32 msgs_tx;
	u32 msgs_rx;

	u32 acks;
	u32 reqs;
	u32 rsts;
};

struct e1000_mbx_info {
	struct e1000_mbx_operations ops;
	struct e1000_mbx_stats stats;
	u32 timeout;
	u32 usec_delay;
	u16 size;
};

struct e1000_dev_spec_82575 {
	bool sgmii_active;
};

struct e1000_hw {
	void *back;

	u8 __iomem *hw_addr;
	u8 __iomem *flash_address;
	unsigned long io_base;

	struct e1000_mac_info  mac;
	struct e1000_fc_info   fc;
	struct e1000_phy_info  phy;
	struct e1000_nvm_info  nvm;
	struct e1000_bus_info  bus;
	struct e1000_mbx_info mbx;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82575	_82575;
	} dev_spec;

	u16 device_id;
	u16 subsystem_vendor_id;
	u16 subsystem_device_id;
	u16 vendor_id;

	u8  revision_id;
};

#ifdef DEBUG
extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
#define hw_dbg(format, arg...) \
	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
#else
#define hw_dbg(format, arg...)
#endif
#endif
/* These functions must be implemented by drivers */
s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _E1000_HW_H_
	29	#define _E1000_HW_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/delay.h>
	33	#include <linux/io.h>
	34
9d5c8243 AK	35	#include "e1000_regs.h"
	36	#include "e1000_defines.h"
	37
	38	struct e1000_hw;
	39
2d064c06 AD	40	#define E1000_DEV_ID_82576 0x10C9
	41	#define E1000_DEV_ID_82576_FIBER 0x10E6
	42	#define E1000_DEV_ID_82576_SERDES 0x10E7
c8ea5ea9	43	#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
9eb2341d	44	#define E1000_DEV_ID_82576_NS 0x150A
747d49ba	45	#define E1000_DEV_ID_82576_NS_SERDES 0x1518
4703bf73	46	#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
9d5c8243 AK	47	#define E1000_DEV_ID_82575EB_COPPER 0x10A7
	48	#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
	49	#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
	50
	51	#define E1000_REVISION_2 2
	52	#define E1000_REVISION_4 4
	53
70d92f86	54	#define E1000_FUNC_0 0
9d5c8243 AK	55	#define E1000_FUNC_1 1
9d5c8243 AK	56
22896639 AD	57	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
22896639 AD	58
9d5c8243 AK	59	enum e1000_mac_type {
	60	e1000_undefined = 0,
	61	e1000_82575,
2d064c06	62	e1000_82576,
9d5c8243 AK	63	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	64	};
	65
	66	enum e1000_media_type {
	67	e1000_media_type_unknown = 0,
	68	e1000_media_type_copper = 1,
dcc3ae9a	69	e1000_media_type_internal_serdes = 2,
9d5c8243 AK	70	e1000_num_media_types
	71	};
	72
	73	enum e1000_nvm_type {
	74	e1000_nvm_unknown = 0,
	75	e1000_nvm_none,
	76	e1000_nvm_eeprom_spi,
9d5c8243 AK	77	e1000_nvm_flash_hw,
	78	e1000_nvm_flash_sw
	79	};
	80
	81	enum e1000_nvm_override {
	82	e1000_nvm_override_none = 0,
	83	e1000_nvm_override_spi_small,
	84	e1000_nvm_override_spi_large,
9d5c8243 AK	85	};
	86
	87	enum e1000_phy_type {
	88	e1000_phy_unknown = 0,
	89	e1000_phy_none,
	90	e1000_phy_m88,
	91	e1000_phy_igp,
	92	e1000_phy_igp_2,
	93	e1000_phy_gg82563,
	94	e1000_phy_igp_3,
	95	e1000_phy_ife,
	96	};
	97
	98	enum e1000_bus_type {
	99	e1000_bus_type_unknown = 0,
	100	e1000_bus_type_pci,
	101	e1000_bus_type_pcix,
	102	e1000_bus_type_pci_express,
	103	e1000_bus_type_reserved
	104	};
	105
	106	enum e1000_bus_speed {
	107	e1000_bus_speed_unknown = 0,
	108	e1000_bus_speed_33,
	109	e1000_bus_speed_66,
	110	e1000_bus_speed_100,
	111	e1000_bus_speed_120,
	112	e1000_bus_speed_133,
	113	e1000_bus_speed_2500,
	114	e1000_bus_speed_5000,
	115	e1000_bus_speed_reserved
	116	};
	117
	118	enum e1000_bus_width {
	119	e1000_bus_width_unknown = 0,
	120	e1000_bus_width_pcie_x1,
	121	e1000_bus_width_pcie_x2,
	122	e1000_bus_width_pcie_x4 = 4,
	123	e1000_bus_width_pcie_x8 = 8,
	124	e1000_bus_width_32,
	125	e1000_bus_width_64,
	126	e1000_bus_width_reserved
	127	};
	128
	129	enum e1000_1000t_rx_status {
	130	e1000_1000t_rx_status_not_ok = 0,
	131	e1000_1000t_rx_status_ok,
	132	e1000_1000t_rx_status_undefined = 0xFF
	133	};
	134
	135	enum e1000_rev_polarity {
	136	e1000_rev_polarity_normal = 0,
	137	e1000_rev_polarity_reversed,
	138	e1000_rev_polarity_undefined = 0xFF
	139	};
	140
0cce119a	141	enum e1000_fc_mode {
9d5c8243 AK	142	e1000_fc_none = 0,
	143	e1000_fc_rx_pause,
	144	e1000_fc_tx_pause,
	145	e1000_fc_full,
	146	e1000_fc_default = 0xFF
	147	};
	148
9d5c8243 AK	149	/* Statistics counters collected by the MAC */
	150	struct e1000_hw_stats {
	151	u64 crcerrs;
	152	u64 algnerrc;
	153	u64 symerrs;
	154	u64 rxerrc;
	155	u64 mpc;
	156	u64 scc;
	157	u64 ecol;
	158	u64 mcc;
	159	u64 latecol;
	160	u64 colc;
	161	u64 dc;
	162	u64 tncrs;
	163	u64 sec;
	164	u64 cexterr;
	165	u64 rlec;
	166	u64 xonrxc;
	167	u64 xontxc;
	168	u64 xoffrxc;
	169	u64 xofftxc;
	170	u64 fcruc;
	171	u64 prc64;
	172	u64 prc127;
	173	u64 prc255;
	174	u64 prc511;
	175	u64 prc1023;
	176	u64 prc1522;
	177	u64 gprc;
	178	u64 bprc;
	179	u64 mprc;
	180	u64 gptc;
	181	u64 gorc;
	182	u64 gotc;
	183	u64 rnbc;
	184	u64 ruc;
	185	u64 rfc;
	186	u64 roc;
	187	u64 rjc;
	188	u64 mgprc;
	189	u64 mgpdc;
	190	u64 mgptc;
	191	u64 tor;
	192	u64 tot;
	193	u64 tpr;
	194	u64 tpt;
	195	u64 ptc64;
	196	u64 ptc127;
	197	u64 ptc255;
	198	u64 ptc511;
	199	u64 ptc1023;
	200	u64 ptc1522;
	201	u64 mptc;
	202	u64 bptc;
	203	u64 tsctc;
	204	u64 tsctfc;
	205	u64 iac;
	206	u64 icrxptc;
	207	u64 icrxatc;
	208	u64 ictxptc;
	209	u64 ictxatc;
	210	u64 ictxqec;
	211	u64 ictxqmtc;
	212	u64 icrxdmtc;
213	u64 icrxoc;
214	u64 cbtmpc;
215	u64 htdpmc;
216	u64 cbrdpc;
217	u64 cbrmpc;
218	u64 rpthc;
219	u64 hgptc;
220	u64 htcbdpc;
221	u64 hgorc;
222	u64 hgotc;
223	u64 lenerrs;
224	u64 scvpc;
225	u64 hrmpc;
dda0e083	226	u64 doosync;
9d5c8243 AK	227	};
	228
	229	struct e1000_phy_stats {
	230	u32 idle_errors;
	231	u32 receive_errors;
	232	};
	233
	234	struct e1000_host_mng_dhcp_cookie {
	235	u32 signature;
	236	u8 status;
	237	u8 reserved0;
	238	u16 vlan_id;
	239	u32 reserved1;
	240	u16 reserved2;
	241	u8 reserved3;
	242	u8 checksum;
	243	};
	244
	245	/* Host Interface "Rev 1" */
	246	struct e1000_host_command_header {
	247	u8 command_id;
	248	u8 command_length;
	249	u8 command_options;
	250	u8 checksum;
	251	};
	252
	253	#define E1000_HI_MAX_DATA_LENGTH 252
	254	struct e1000_host_command_info {
	255	struct e1000_host_command_header command_header;
	256	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	257	};
	258
	259	/* Host Interface "Rev 2" */
	260	struct e1000_host_mng_command_header {
	261	u8 command_id;
	262	u8 checksum;
	263	u16 reserved1;
	264	u16 reserved2;
	265	u16 command_length;
	266	};
	267
	268	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
	269	struct e1000_host_mng_command_info {
	270	struct e1000_host_mng_command_header command_header;
	271	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	272	};
	273
	274	#include "e1000_mac.h"
	275	#include "e1000_phy.h"
	276	#include "e1000_nvm.h"
4ae196df	277	#include "e1000_mbx.h"
9d5c8243 AK	278
	279	struct e1000_mac_operations {
	280	s32 (check_for_link)(struct e1000_hw );
	281	s32 (reset_hw)(struct e1000_hw );
	282	s32 (init_hw)(struct e1000_hw );
2d064c06	283	bool (check_mng_mode)(struct e1000_hw );
9d5c8243 AK	284	s32 (setup_physical_interface)(struct e1000_hw );
	285	void (rar_set)(struct e1000_hw , u8 *, u32);
	286	s32 (read_mac_addr)(struct e1000_hw );
	287	s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );
	288	};
	289
	290	struct e1000_phy_operations {
a8d2a0c2	291	s32 (acquire)(struct e1000_hw );
2d064c06	292	s32 (check_reset_block)(struct e1000_hw );
9d5c8243 AK	293	s32 (force_speed_duplex)(struct e1000_hw );
	294	s32 (get_cfg_done)(struct e1000_hw hw);
	295	s32 (get_cable_length)(struct e1000_hw );
	296	s32 (get_phy_info)(struct e1000_hw );
a8d2a0c2 AD	297	s32 (read_reg)(struct e1000_hw , u32, u16 *);
	298	void (release)(struct e1000_hw );
	299	s32 (reset)(struct e1000_hw );
9d5c8243 AK	300	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
9d5c8243 AK	301	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
a8d2a0c2	302	s32 (write_reg)(struct e1000_hw , u32, u16);
9d5c8243 AK	303	};
	304
	305	struct e1000_nvm_operations {
312c75ae AD	306	s32 (acquire)(struct e1000_hw );
	307	s32 (read)(struct e1000_hw , u16, u16, u16 *);
	308	void (release)(struct e1000_hw );
	309	s32 (write)(struct e1000_hw , u16, u16, u16 *);
9d5c8243 AK	310	};
	311
	312	struct e1000_info {
	313	s32 (get_invariants)(struct e1000_hw );
	314	struct e1000_mac_operations *mac_ops;
	315	struct e1000_phy_operations *phy_ops;
	316	struct e1000_nvm_operations *nvm_ops;
	317	};
	318
	319	extern const struct e1000_info e1000_82575_info;
	320
	321	struct e1000_mac_info {
	322	struct e1000_mac_operations ops;
	323
	324	u8 addr[6];
	325	u8 perm_addr[6];
	326
	327	enum e1000_mac_type type;
	328
	329	u32 collision_delta;
	330	u32 ledctl_default;
	331	u32 ledctl_mode1;
	332	u32 ledctl_mode2;
	333	u32 mc_filter_type;
	334	u32 tx_packet_delta;
	335	u32 txcw;
	336
	337	u16 current_ifs_val;
	338	u16 ifs_max_val;
	339	u16 ifs_min_val;
	340	u16 ifs_ratio;
	341	u16 ifs_step_size;
	342	u16 mta_reg_count;
68d480c4	343	u16 uta_reg_count;
28fc06f5 AD	344
	345	/* Maximum size of the MTA register table in all supported adapters */
	346	#define MAX_MTA_REG 128
	347	u32 mta_shadow[MAX_MTA_REG];
9d5c8243 AK	348	u16 rar_entry_count;
	349
	350	u8 forced_speed_duplex;
	351
	352	bool adaptive_ifs;
	353	bool arc_subsystem_valid;
	354	bool asf_firmware_present;
	355	bool autoneg;
	356	bool autoneg_failed;
9d5c8243 AK	357	bool disable_hw_init_bits;
	358	bool get_link_status;
	359	bool ifs_params_forced;
	360	bool in_ifs_mode;
	361	bool report_tx_early;
	362	bool serdes_has_link;
	363	bool tx_pkt_filtering;
	364	};
	365
	366	struct e1000_phy_info {
	367	struct e1000_phy_operations ops;
	368
	369	enum e1000_phy_type type;
	370
	371	enum e1000_1000t_rx_status local_rx;
	372	enum e1000_1000t_rx_status remote_rx;
	373	enum e1000_ms_type ms_type;
	374	enum e1000_ms_type original_ms_type;
	375	enum e1000_rev_polarity cable_polarity;
	376	enum e1000_smart_speed smart_speed;
	377
	378	u32 addr;
	379	u32 id;
	380	u32 reset_delay_us; /* in usec */
	381	u32 revision;
	382
	383	enum e1000_media_type media_type;
	384
	385	u16 autoneg_advertised;
	386	u16 autoneg_mask;
	387	u16 cable_length;
	388	u16 max_cable_length;
	389	u16 min_cable_length;
	390
	391	u8 mdix;
	392
	393	bool disable_polarity_correction;
	394	bool is_mdix;
	395	bool polarity_correction;
	396	bool reset_disable;
	397	bool speed_downgraded;
	398	bool autoneg_wait_to_complete;
	399	};
	400
	401	struct e1000_nvm_info {
	402	struct e1000_nvm_operations ops;
	403
	404	enum e1000_nvm_type type;
	405	enum e1000_nvm_override override;
	406
	407	u32 flash_bank_size;
	408	u32 flash_base_addr;
	409
	410	u16 word_size;
	411	u16 delay_usec;
	412	u16 address_bits;
	413	u16 opcode_bits;
	414	u16 page_size;
	415	};
	416
	417	struct e1000_bus_info {
	418	enum e1000_bus_type type;
	419	enum e1000_bus_speed speed;
	420	enum e1000_bus_width width;
421
422	u32 snoop;
423
424	u16 func;
425	u16 pci_cmd_word;
426	};
427
428	struct e1000_fc_info {
429	u32 high_water; /* Flow control high-water mark */
430	u32 low_water; /* Flow control low-water mark */
431	u16 pause_time; /* Flow control pause timer */
432	bool send_xon; /* Flow control send XON */
433	bool strict_ieee; /* Strict IEEE mode */
0cce119a AD	434	enum e1000_fc_mode current_mode; /* Type of flow control */
0cce119a AD	435	enum e1000_fc_mode requested_mode;
9d5c8243 AK	436	};
9d5c8243 AK	437
4ae196df AD	438	struct e1000_mbx_operations {
	439	s32 (init_params)(struct e1000_hw hw);
	440	s32 (read)(struct e1000_hw , u32 *, u16, u16);
	441	s32 (write)(struct e1000_hw , u32 *, u16, u16);
	442	s32 (read_posted)(struct e1000_hw , u32 *, u16, u16);
	443	s32 (write_posted)(struct e1000_hw , u32 *, u16, u16);
	444	s32 (check_for_msg)(struct e1000_hw , u16);
	445	s32 (check_for_ack)(struct e1000_hw , u16);
	446	s32 (check_for_rst)(struct e1000_hw , u16);
	447	};
	448
	449	struct e1000_mbx_stats {
	450	u32 msgs_tx;
	451	u32 msgs_rx;
	452
	453	u32 acks;
	454	u32 reqs;
	455	u32 rsts;
	456	};
	457
	458	struct e1000_mbx_info {
	459	struct e1000_mbx_operations ops;
	460	struct e1000_mbx_stats stats;
	461	u32 timeout;
	462	u32 usec_delay;
	463	u16 size;
	464	};
	465
c1889bfe AD	466	struct e1000_dev_spec_82575 {
	467	bool sgmii_active;
	468	};
	469
9d5c8243 AK	470	struct e1000_hw {
9d5c8243 AK	471	void *back;
9d5c8243 AK	472
	473	u8 __iomem *hw_addr;
	474	u8 __iomem *flash_address;
	475	unsigned long io_base;
	476
	477	struct e1000_mac_info mac;
	478	struct e1000_fc_info fc;
	479	struct e1000_phy_info phy;
	480	struct e1000_nvm_info nvm;
	481	struct e1000_bus_info bus;
4ae196df	482	struct e1000_mbx_info mbx;
9d5c8243 AK	483	struct e1000_host_mng_dhcp_cookie mng_cookie;
9d5c8243 AK	484
c1889bfe AD	485	union {
	486	struct e1000_dev_spec_82575 _82575;
	487	} dev_spec;
9d5c8243 AK	488
	489	u16 device_id;
	490	u16 subsystem_vendor_id;
	491	u16 subsystem_device_id;
	492	u16 vendor_id;
	493
	494	u8 revision_id;
	495	};
	496
	497	#ifdef DEBUG
	498	extern char igb_get_hw_dev_name(struct e1000_hw hw);
652fff32	499	#define hw_dbg(format, arg...) \
9d5c8243 AK	500	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
9d5c8243 AK	501	#else
652fff32	502	#define hw_dbg(format, arg...)
9d5c8243	503	#endif
9d5c8243	504	#endif
009bc06e AD	505	/* These functions must be implemented by drivers */
	506	s32 igb_read_pcie_cap_reg(struct e1000_hw hw, u32 reg, u16 value);
	507	s32 igb_write_pcie_cap_reg(struct e1000_hw hw, u32 reg, u16 value);