[deliverable/linux.git] / drivers / net / igb / e1000_hw.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/io.h>

#include "e1000_mac.h"
#include "e1000_regs.h"
#include "e1000_defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82576                    0x10C9
#define E1000_DEV_ID_82576_FIBER              0x10E6
#define E1000_DEV_ID_82576_SERDES             0x10E7
#define E1000_DEV_ID_82575EB_COPPER           0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6

#define E1000_REVISION_2 2
#define E1000_REVISION_4 4

#define E1000_FUNC_1     1

enum e1000_mac_type {
	e1000_undefined = 0,
	e1000_82575,
	e1000_82576,
	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_fiber = 2,
	e1000_media_type_internal_serdes = 3,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_eeprom_microwire,
	e1000_nvm_flash_hw,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large,
	e1000_nvm_override_microwire_small,
	e1000_nvm_override_microwire_large
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
};

enum e1000_bus_type {
	e1000_bus_type_unknown = 0,
	e1000_bus_type_pci,
	e1000_bus_type_pcix,
	e1000_bus_type_pci_express,
	e1000_bus_type_reserved
};

enum e1000_bus_speed {
	e1000_bus_speed_unknown = 0,
	e1000_bus_speed_33,
	e1000_bus_speed_66,
	e1000_bus_speed_100,
	e1000_bus_speed_120,
	e1000_bus_speed_133,
	e1000_bus_speed_2500,
	e1000_bus_speed_5000,
	e1000_bus_speed_reserved
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_pcie_x8 = 8,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity {
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_type {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
	u64 cbtmpc;
	u64 htdpmc;
	u64 cbrdpc;
	u64 cbrmpc;
	u64 rpthc;
	u64 hgptc;
	u64 htcbdpc;
	u64 hgorc;
	u64 hgotc;
	u64 lenerrs;
	u64 scvpc;
	u64 hrmpc;
	u64 doosync;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8  status;
	u8  reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8  reserved3;
	u8  checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH     252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8  command_id;
	u8  checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_nvm.h"

struct e1000_mac_operations {
	s32  (*check_for_link)(struct e1000_hw *);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32  (*setup_physical_interface)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
	s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
};

struct e1000_phy_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*check_reset_block)(struct e1000_hw *);
	s32  (*force_speed_duplex)(struct e1000_hw *);
	s32  (*get_cfg_done)(struct e1000_hw *hw);
	s32  (*get_cable_length)(struct e1000_hw *);
	s32  (*get_phy_info)(struct e1000_hw *);
	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*reset)(struct e1000_hw *);
	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32  (*write_reg)(struct e1000_hw *, u32, u16);
};

struct e1000_nvm_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
};

struct e1000_info {
	s32 (*get_invariants)(struct e1000_hw *);
	struct e1000_mac_operations *mac_ops;
	struct e1000_phy_operations *phy_ops;
	struct e1000_nvm_operations *nvm_ops;
};

extern const struct e1000_info e1000_82575_info;

struct e1000_mac_info {
	struct e1000_mac_operations ops;

	u8 addr[6];
	u8 perm_addr[6];

	enum e1000_mac_type type;

	u32 collision_delta;
	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 tx_packet_delta;
	u32 txcw;

	u16 current_ifs_val;
	u16 ifs_max_val;
	u16 ifs_min_val;
	u16 ifs_ratio;
	u16 ifs_step_size;
	u16 mta_reg_count;
	u16 rar_entry_count;

	u8  forced_speed_duplex;

	bool adaptive_ifs;
	bool arc_subsystem_valid;
	bool asf_firmware_present;
	bool autoneg;
	bool autoneg_failed;
	bool disable_hw_init_bits;
	bool get_link_status;
	bool ifs_params_forced;
	bool in_ifs_mode;
	bool report_tx_early;
	bool serdes_has_link;
	bool tx_pkt_filtering;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us; /* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool reset_disable;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;

	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_type type;
	enum e1000_bus_speed speed;
	enum e1000_bus_width width;

	u32 snoop;

	u16 func;
	u16 pci_cmd_word;
};

struct e1000_fc_info {
	u32 high_water;     /* Flow control high-water mark */
	u32 low_water;      /* Flow control low-water mark */
	u16 pause_time;     /* Flow control pause timer */
	bool send_xon;      /* Flow control send XON */
	bool strict_ieee;   /* Strict IEEE mode */
	enum e1000_fc_type type; /* Type of flow control */
	enum e1000_fc_type original_type;
};

struct e1000_dev_spec_82575 {
	bool sgmii_active;
};

struct e1000_hw {
	void *back;

	u8 __iomem *hw_addr;
	u8 __iomem *flash_address;
	unsigned long io_base;

	struct e1000_mac_info  mac;
	struct e1000_fc_info   fc;
	struct e1000_phy_info  phy;
	struct e1000_nvm_info  nvm;
	struct e1000_bus_info  bus;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82575	_82575;
	} dev_spec;

	u16 device_id;
	u16 subsystem_vendor_id;
	u16 subsystem_device_id;
	u16 vendor_id;

	u8  revision_id;
};

#ifdef DEBUG
extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
#define hw_dbg(format, arg...) \
	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
#else
#define hw_dbg(format, arg...)
#endif

#endif
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _E1000_HW_H_
	29	#define _E1000_HW_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/delay.h>
	33	#include <linux/io.h>
	34
	35	#include "e1000_mac.h"
	36	#include "e1000_regs.h"
	37	#include "e1000_defines.h"
	38
	39	struct e1000_hw;
	40
2d064c06 AD	41	#define E1000_DEV_ID_82576 0x10C9
	42	#define E1000_DEV_ID_82576_FIBER 0x10E6
	43	#define E1000_DEV_ID_82576_SERDES 0x10E7
9d5c8243 AK	44	#define E1000_DEV_ID_82575EB_COPPER 0x10A7
	45	#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
	46	#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
	47
	48	#define E1000_REVISION_2 2
	49	#define E1000_REVISION_4 4
	50
	51	#define E1000_FUNC_1 1
	52
	53	enum e1000_mac_type {
	54	e1000_undefined = 0,
	55	e1000_82575,
2d064c06	56	e1000_82576,
9d5c8243 AK	57	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	58	};
	59
	60	enum e1000_media_type {
	61	e1000_media_type_unknown = 0,
	62	e1000_media_type_copper = 1,
	63	e1000_media_type_fiber = 2,
	64	e1000_media_type_internal_serdes = 3,
	65	e1000_num_media_types
	66	};
	67
	68	enum e1000_nvm_type {
	69	e1000_nvm_unknown = 0,
	70	e1000_nvm_none,
	71	e1000_nvm_eeprom_spi,
	72	e1000_nvm_eeprom_microwire,
	73	e1000_nvm_flash_hw,
	74	e1000_nvm_flash_sw
	75	};
	76
	77	enum e1000_nvm_override {
	78	e1000_nvm_override_none = 0,
	79	e1000_nvm_override_spi_small,
	80	e1000_nvm_override_spi_large,
	81	e1000_nvm_override_microwire_small,
	82	e1000_nvm_override_microwire_large
	83	};
	84
	85	enum e1000_phy_type {
	86	e1000_phy_unknown = 0,
	87	e1000_phy_none,
	88	e1000_phy_m88,
	89	e1000_phy_igp,
	90	e1000_phy_igp_2,
	91	e1000_phy_gg82563,
	92	e1000_phy_igp_3,
	93	e1000_phy_ife,
	94	};
	95
	96	enum e1000_bus_type {
	97	e1000_bus_type_unknown = 0,
	98	e1000_bus_type_pci,
	99	e1000_bus_type_pcix,
	100	e1000_bus_type_pci_express,
	101	e1000_bus_type_reserved
	102	};
	103
	104	enum e1000_bus_speed {
	105	e1000_bus_speed_unknown = 0,
	106	e1000_bus_speed_33,
	107	e1000_bus_speed_66,
	108	e1000_bus_speed_100,
	109	e1000_bus_speed_120,
	110	e1000_bus_speed_133,
	111	e1000_bus_speed_2500,
	112	e1000_bus_speed_5000,
	113	e1000_bus_speed_reserved
	114	};
	115
	116	enum e1000_bus_width {
	117	e1000_bus_width_unknown = 0,
	118	e1000_bus_width_pcie_x1,
	119	e1000_bus_width_pcie_x2,
	120	e1000_bus_width_pcie_x4 = 4,
121	e1000_bus_width_pcie_x8 = 8,
122	e1000_bus_width_32,
123	e1000_bus_width_64,
124	e1000_bus_width_reserved
125	};
126
127	enum e1000_1000t_rx_status {
128	e1000_1000t_rx_status_not_ok = 0,
129	e1000_1000t_rx_status_ok,
130	e1000_1000t_rx_status_undefined = 0xFF
131	};
132
133	enum e1000_rev_polarity {
134	e1000_rev_polarity_normal = 0,
135	e1000_rev_polarity_reversed,
136	e1000_rev_polarity_undefined = 0xFF
137	};
138
139	enum e1000_fc_type {
140	e1000_fc_none = 0,
141	e1000_fc_rx_pause,
142	e1000_fc_tx_pause,
143	e1000_fc_full,
144	e1000_fc_default = 0xFF
145	};
146
9d5c8243 AK	147	/* Statistics counters collected by the MAC */
	148	struct e1000_hw_stats {
	149	u64 crcerrs;
	150	u64 algnerrc;
	151	u64 symerrs;
	152	u64 rxerrc;
	153	u64 mpc;
	154	u64 scc;
	155	u64 ecol;
	156	u64 mcc;
	157	u64 latecol;
	158	u64 colc;
	159	u64 dc;
	160	u64 tncrs;
	161	u64 sec;
	162	u64 cexterr;
	163	u64 rlec;
	164	u64 xonrxc;
	165	u64 xontxc;
	166	u64 xoffrxc;
	167	u64 xofftxc;
	168	u64 fcruc;
	169	u64 prc64;
	170	u64 prc127;
	171	u64 prc255;
	172	u64 prc511;
	173	u64 prc1023;
	174	u64 prc1522;
	175	u64 gprc;
	176	u64 bprc;
	177	u64 mprc;
	178	u64 gptc;
	179	u64 gorc;
	180	u64 gotc;
	181	u64 rnbc;
	182	u64 ruc;
	183	u64 rfc;
	184	u64 roc;
	185	u64 rjc;
	186	u64 mgprc;
	187	u64 mgpdc;
	188	u64 mgptc;
	189	u64 tor;
	190	u64 tot;
	191	u64 tpr;
	192	u64 tpt;
	193	u64 ptc64;
	194	u64 ptc127;
	195	u64 ptc255;
	196	u64 ptc511;
	197	u64 ptc1023;
	198	u64 ptc1522;
	199	u64 mptc;
	200	u64 bptc;
	201	u64 tsctc;
	202	u64 tsctfc;
	203	u64 iac;
	204	u64 icrxptc;
	205	u64 icrxatc;
	206	u64 ictxptc;
	207	u64 ictxatc;
	208	u64 ictxqec;
	209	u64 ictxqmtc;
	210	u64 icrxdmtc;
211	u64 icrxoc;
212	u64 cbtmpc;
213	u64 htdpmc;
214	u64 cbrdpc;
215	u64 cbrmpc;
216	u64 rpthc;
217	u64 hgptc;
218	u64 htcbdpc;
219	u64 hgorc;
220	u64 hgotc;
221	u64 lenerrs;
222	u64 scvpc;
223	u64 hrmpc;
dda0e083	224	u64 doosync;
9d5c8243 AK	225	};
	226
	227	struct e1000_phy_stats {
	228	u32 idle_errors;
	229	u32 receive_errors;
	230	};
	231
	232	struct e1000_host_mng_dhcp_cookie {
	233	u32 signature;
	234	u8 status;
	235	u8 reserved0;
	236	u16 vlan_id;
	237	u32 reserved1;
	238	u16 reserved2;
	239	u8 reserved3;
	240	u8 checksum;
	241	};
	242
	243	/* Host Interface "Rev 1" */
	244	struct e1000_host_command_header {
	245	u8 command_id;
	246	u8 command_length;
	247	u8 command_options;
	248	u8 checksum;
	249	};
	250
	251	#define E1000_HI_MAX_DATA_LENGTH 252
	252	struct e1000_host_command_info {
	253	struct e1000_host_command_header command_header;
	254	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	255	};
	256
	257	/* Host Interface "Rev 2" */
	258	struct e1000_host_mng_command_header {
	259	u8 command_id;
	260	u8 checksum;
	261	u16 reserved1;
	262	u16 reserved2;
	263	u16 command_length;
	264	};
	265
	266	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
	267	struct e1000_host_mng_command_info {
	268	struct e1000_host_mng_command_header command_header;
	269	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	270	};
	271
	272	#include "e1000_mac.h"
	273	#include "e1000_phy.h"
	274	#include "e1000_nvm.h"
	275
	276	struct e1000_mac_operations {
	277	s32 (check_for_link)(struct e1000_hw );
	278	s32 (reset_hw)(struct e1000_hw );
	279	s32 (init_hw)(struct e1000_hw );
2d064c06	280	bool (check_mng_mode)(struct e1000_hw );
9d5c8243 AK	281	s32 (setup_physical_interface)(struct e1000_hw );
	282	void (rar_set)(struct e1000_hw , u8 *, u32);
	283	s32 (read_mac_addr)(struct e1000_hw );
	284	s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );
	285	};
	286
	287	struct e1000_phy_operations {
a8d2a0c2	288	s32 (acquire)(struct e1000_hw );
2d064c06	289	s32 (check_reset_block)(struct e1000_hw );
9d5c8243 AK	290	s32 (force_speed_duplex)(struct e1000_hw );
	291	s32 (get_cfg_done)(struct e1000_hw hw);
	292	s32 (get_cable_length)(struct e1000_hw );
	293	s32 (get_phy_info)(struct e1000_hw );
a8d2a0c2 AD	294	s32 (read_reg)(struct e1000_hw , u32, u16 *);
	295	void (release)(struct e1000_hw );
	296	s32 (reset)(struct e1000_hw );
9d5c8243 AK	297	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
9d5c8243 AK	298	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
a8d2a0c2	299	s32 (write_reg)(struct e1000_hw , u32, u16);
9d5c8243 AK	300	};
	301
	302	struct e1000_nvm_operations {
312c75ae AD	303	s32 (acquire)(struct e1000_hw );
	304	s32 (read)(struct e1000_hw , u16, u16, u16 *);
	305	void (release)(struct e1000_hw );
	306	s32 (write)(struct e1000_hw , u16, u16, u16 *);
9d5c8243 AK	307	};
	308
	309	struct e1000_info {
	310	s32 (get_invariants)(struct e1000_hw );
	311	struct e1000_mac_operations *mac_ops;
	312	struct e1000_phy_operations *phy_ops;
	313	struct e1000_nvm_operations *nvm_ops;
	314	};
	315
	316	extern const struct e1000_info e1000_82575_info;
	317
	318	struct e1000_mac_info {
	319	struct e1000_mac_operations ops;
	320
	321	u8 addr[6];
	322	u8 perm_addr[6];
	323
	324	enum e1000_mac_type type;
	325
	326	u32 collision_delta;
	327	u32 ledctl_default;
	328	u32 ledctl_mode1;
	329	u32 ledctl_mode2;
	330	u32 mc_filter_type;
	331	u32 tx_packet_delta;
	332	u32 txcw;
	333
	334	u16 current_ifs_val;
	335	u16 ifs_max_val;
	336	u16 ifs_min_val;
	337	u16 ifs_ratio;
	338	u16 ifs_step_size;
	339	u16 mta_reg_count;
	340	u16 rar_entry_count;
	341
	342	u8 forced_speed_duplex;
	343
	344	bool adaptive_ifs;
	345	bool arc_subsystem_valid;
	346	bool asf_firmware_present;
	347	bool autoneg;
	348	bool autoneg_failed;
9d5c8243 AK	349	bool disable_hw_init_bits;
	350	bool get_link_status;
	351	bool ifs_params_forced;
	352	bool in_ifs_mode;
	353	bool report_tx_early;
	354	bool serdes_has_link;
	355	bool tx_pkt_filtering;
	356	};
	357
	358	struct e1000_phy_info {
	359	struct e1000_phy_operations ops;
	360
	361	enum e1000_phy_type type;
	362
	363	enum e1000_1000t_rx_status local_rx;
	364	enum e1000_1000t_rx_status remote_rx;
	365	enum e1000_ms_type ms_type;
	366	enum e1000_ms_type original_ms_type;
	367	enum e1000_rev_polarity cable_polarity;
	368	enum e1000_smart_speed smart_speed;
	369
	370	u32 addr;
	371	u32 id;
	372	u32 reset_delay_us; /* in usec */
	373	u32 revision;
	374
	375	enum e1000_media_type media_type;
	376
	377	u16 autoneg_advertised;
	378	u16 autoneg_mask;
	379	u16 cable_length;
	380	u16 max_cable_length;
	381	u16 min_cable_length;
	382
	383	u8 mdix;
	384
	385	bool disable_polarity_correction;
	386	bool is_mdix;
	387	bool polarity_correction;
	388	bool reset_disable;
	389	bool speed_downgraded;
	390	bool autoneg_wait_to_complete;
	391	};
	392
	393	struct e1000_nvm_info {
	394	struct e1000_nvm_operations ops;
	395
	396	enum e1000_nvm_type type;
	397	enum e1000_nvm_override override;
	398
	399	u32 flash_bank_size;
	400	u32 flash_base_addr;
	401
	402	u16 word_size;
	403	u16 delay_usec;
	404	u16 address_bits;
	405	u16 opcode_bits;
	406	u16 page_size;
	407	};
	408
	409	struct e1000_bus_info {
	410	enum e1000_bus_type type;
	411	enum e1000_bus_speed speed;
	412	enum e1000_bus_width width;
413
414	u32 snoop;
415
416	u16 func;
417	u16 pci_cmd_word;
418	};
419
420	struct e1000_fc_info {
421	u32 high_water; /* Flow control high-water mark */
422	u32 low_water; /* Flow control low-water mark */
423	u16 pause_time; /* Flow control pause timer */
424	bool send_xon; /* Flow control send XON */
425	bool strict_ieee; /* Strict IEEE mode */
426	enum e1000_fc_type type; /* Type of flow control */
427	enum e1000_fc_type original_type;
428	};
429
c1889bfe AD	430	struct e1000_dev_spec_82575 {
	431	bool sgmii_active;
	432	};
	433
9d5c8243 AK	434	struct e1000_hw {
9d5c8243 AK	435	void *back;
9d5c8243 AK	436
	437	u8 __iomem *hw_addr;
	438	u8 __iomem *flash_address;
	439	unsigned long io_base;
	440
	441	struct e1000_mac_info mac;
	442	struct e1000_fc_info fc;
	443	struct e1000_phy_info phy;
	444	struct e1000_nvm_info nvm;
	445	struct e1000_bus_info bus;
	446	struct e1000_host_mng_dhcp_cookie mng_cookie;
	447
c1889bfe AD	448	union {
	449	struct e1000_dev_spec_82575 _82575;
	450	} dev_spec;
9d5c8243 AK	451
	452	u16 device_id;
	453	u16 subsystem_vendor_id;
	454	u16 subsystem_device_id;
	455	u16 vendor_id;
	456
	457	u8 revision_id;
	458	};
	459
	460	#ifdef DEBUG
	461	extern char igb_get_hw_dev_name(struct e1000_hw hw);
652fff32	462	#define hw_dbg(format, arg...) \
9d5c8243 AK	463	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
9d5c8243 AK	464	#else
652fff32	465	#define hw_dbg(format, arg...)
9d5c8243 AK	466	#endif
	467
	468	#endif