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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4 | Copyright(c) 2007 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/if_ether.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | ||
33 | #include "e1000_mac.h" | |
34 | ||
35 | #include "igb.h" | |
36 | ||
37 | static s32 igb_set_default_fc(struct e1000_hw *hw); | |
38 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw); | |
9d5c8243 | 39 | |
9d5c8243 AK |
40 | static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
41 | { | |
42 | struct igb_adapter *adapter = hw->back; | |
43 | u16 cap_offset; | |
44 | ||
45 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | |
46 | if (!cap_offset) | |
47 | return -E1000_ERR_CONFIG; | |
48 | ||
49 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); | |
50 | ||
51 | return 0; | |
52 | } | |
53 | ||
54 | /** | |
733596be | 55 | * igb_get_bus_info_pcie - Get PCIe bus information |
9d5c8243 AK |
56 | * @hw: pointer to the HW structure |
57 | * | |
58 | * Determines and stores the system bus information for a particular | |
59 | * network interface. The following bus information is determined and stored: | |
60 | * bus speed, bus width, type (PCIe), and PCIe function. | |
61 | **/ | |
62 | s32 igb_get_bus_info_pcie(struct e1000_hw *hw) | |
63 | { | |
64 | struct e1000_bus_info *bus = &hw->bus; | |
65 | s32 ret_val; | |
5e8427e5 AD |
66 | u32 reg; |
67 | u16 pcie_link_status; | |
9d5c8243 AK |
68 | |
69 | bus->type = e1000_bus_type_pci_express; | |
70 | bus->speed = e1000_bus_speed_2500; | |
71 | ||
72 | ret_val = igb_read_pcie_cap_reg(hw, | |
73 | PCIE_LINK_STATUS, | |
74 | &pcie_link_status); | |
75 | if (ret_val) | |
76 | bus->width = e1000_bus_width_unknown; | |
77 | else | |
78 | bus->width = (enum e1000_bus_width)((pcie_link_status & | |
79 | PCIE_LINK_WIDTH_MASK) >> | |
80 | PCIE_LINK_WIDTH_SHIFT); | |
81 | ||
5e8427e5 AD |
82 | reg = rd32(E1000_STATUS); |
83 | bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; | |
9d5c8243 AK |
84 | |
85 | return 0; | |
86 | } | |
87 | ||
88 | /** | |
733596be | 89 | * igb_clear_vfta - Clear VLAN filter table |
9d5c8243 AK |
90 | * @hw: pointer to the HW structure |
91 | * | |
92 | * Clears the register array which contains the VLAN filter table by | |
93 | * setting all the values to 0. | |
94 | **/ | |
95 | void igb_clear_vfta(struct e1000_hw *hw) | |
96 | { | |
97 | u32 offset; | |
98 | ||
99 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
100 | array_wr32(E1000_VFTA, offset, 0); | |
101 | wrfl(); | |
102 | } | |
103 | } | |
104 | ||
105 | /** | |
733596be | 106 | * igb_write_vfta - Write value to VLAN filter table |
9d5c8243 AK |
107 | * @hw: pointer to the HW structure |
108 | * @offset: register offset in VLAN filter table | |
109 | * @value: register value written to VLAN filter table | |
110 | * | |
111 | * Writes value at the given offset in the register array which stores | |
112 | * the VLAN filter table. | |
113 | **/ | |
114 | void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) | |
115 | { | |
116 | array_wr32(E1000_VFTA, offset, value); | |
117 | wrfl(); | |
118 | } | |
119 | ||
9d5c8243 | 120 | /** |
733596be | 121 | * igb_check_alt_mac_addr - Check for alternate MAC addr |
9d5c8243 AK |
122 | * @hw: pointer to the HW structure |
123 | * | |
124 | * Checks the nvm for an alternate MAC address. An alternate MAC address | |
125 | * can be setup by pre-boot software and must be treated like a permanent | |
126 | * address and must override the actual permanent MAC address. If an | |
127 | * alternate MAC address is fopund it is saved in the hw struct and | |
128 | * prgrammed into RAR0 and the cuntion returns success, otherwise the | |
129 | * fucntion returns an error. | |
130 | **/ | |
131 | s32 igb_check_alt_mac_addr(struct e1000_hw *hw) | |
132 | { | |
133 | u32 i; | |
134 | s32 ret_val = 0; | |
135 | u16 offset, nvm_alt_mac_addr_offset, nvm_data; | |
136 | u8 alt_mac_addr[ETH_ALEN]; | |
137 | ||
138 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, | |
139 | &nvm_alt_mac_addr_offset); | |
140 | if (ret_val) { | |
652fff32 | 141 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
142 | goto out; |
143 | } | |
144 | ||
145 | if (nvm_alt_mac_addr_offset == 0xFFFF) { | |
146 | ret_val = -(E1000_NOT_IMPLEMENTED); | |
147 | goto out; | |
148 | } | |
149 | ||
150 | if (hw->bus.func == E1000_FUNC_1) | |
151 | nvm_alt_mac_addr_offset += ETH_ALEN/sizeof(u16); | |
152 | ||
153 | for (i = 0; i < ETH_ALEN; i += 2) { | |
154 | offset = nvm_alt_mac_addr_offset + (i >> 1); | |
155 | ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); | |
156 | if (ret_val) { | |
652fff32 | 157 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
158 | goto out; |
159 | } | |
160 | ||
161 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); | |
162 | alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); | |
163 | } | |
164 | ||
165 | /* if multicast bit is set, the alternate address will not be used */ | |
166 | if (alt_mac_addr[0] & 0x01) { | |
167 | ret_val = -(E1000_NOT_IMPLEMENTED); | |
168 | goto out; | |
169 | } | |
170 | ||
171 | for (i = 0; i < ETH_ALEN; i++) | |
172 | hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; | |
173 | ||
174 | hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); | |
175 | ||
176 | out: | |
177 | return ret_val; | |
178 | } | |
179 | ||
180 | /** | |
733596be | 181 | * igb_rar_set - Set receive address register |
9d5c8243 AK |
182 | * @hw: pointer to the HW structure |
183 | * @addr: pointer to the receive address | |
184 | * @index: receive address array register | |
185 | * | |
186 | * Sets the receive address array register at index to the address passed | |
187 | * in by addr. | |
188 | **/ | |
189 | void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) | |
190 | { | |
191 | u32 rar_low, rar_high; | |
192 | ||
193 | /* | |
194 | * HW expects these in little endian so we reverse the byte order | |
195 | * from network order (big endian) to little endian | |
196 | */ | |
197 | rar_low = ((u32) addr[0] | | |
198 | ((u32) addr[1] << 8) | | |
199 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
200 | ||
201 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
202 | ||
203 | if (!hw->mac.disable_av) | |
204 | rar_high |= E1000_RAH_AV; | |
205 | ||
5e8427e5 AD |
206 | wr32(E1000_RAL(index), rar_low); |
207 | wr32(E1000_RAH(index), rar_high); | |
9d5c8243 AK |
208 | } |
209 | ||
210 | /** | |
733596be | 211 | * igb_mta_set - Set multicast filter table address |
9d5c8243 AK |
212 | * @hw: pointer to the HW structure |
213 | * @hash_value: determines the MTA register and bit to set | |
214 | * | |
215 | * The multicast table address is a register array of 32-bit registers. | |
216 | * The hash_value is used to determine what register the bit is in, the | |
217 | * current value is read, the new bit is OR'd in and the new value is | |
218 | * written back into the register. | |
219 | **/ | |
549bdd84 | 220 | void igb_mta_set(struct e1000_hw *hw, u32 hash_value) |
9d5c8243 AK |
221 | { |
222 | u32 hash_bit, hash_reg, mta; | |
223 | ||
224 | /* | |
225 | * The MTA is a register array of 32-bit registers. It is | |
226 | * treated like an array of (32*mta_reg_count) bits. We want to | |
227 | * set bit BitArray[hash_value]. So we figure out what register | |
228 | * the bit is in, read it, OR in the new bit, then write | |
229 | * back the new value. The (hw->mac.mta_reg_count - 1) serves as a | |
230 | * mask to bits 31:5 of the hash value which gives us the | |
231 | * register we're modifying. The hash bit within that register | |
232 | * is determined by the lower 5 bits of the hash value. | |
233 | */ | |
234 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); | |
235 | hash_bit = hash_value & 0x1F; | |
236 | ||
237 | mta = array_rd32(E1000_MTA, hash_reg); | |
238 | ||
239 | mta |= (1 << hash_bit); | |
240 | ||
241 | array_wr32(E1000_MTA, hash_reg, mta); | |
242 | wrfl(); | |
243 | } | |
244 | ||
9d5c8243 | 245 | /** |
733596be | 246 | * igb_hash_mc_addr - Generate a multicast hash value |
9d5c8243 AK |
247 | * @hw: pointer to the HW structure |
248 | * @mc_addr: pointer to a multicast address | |
249 | * | |
250 | * Generates a multicast address hash value which is used to determine | |
251 | * the multicast filter table array address and new table value. See | |
252 | * igb_mta_set() | |
253 | **/ | |
2d064c06 | 254 | u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
9d5c8243 AK |
255 | { |
256 | u32 hash_value, hash_mask; | |
257 | u8 bit_shift = 0; | |
258 | ||
259 | /* Register count multiplied by bits per register */ | |
260 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; | |
261 | ||
262 | /* | |
263 | * For a mc_filter_type of 0, bit_shift is the number of left-shifts | |
264 | * where 0xFF would still fall within the hash mask. | |
265 | */ | |
266 | while (hash_mask >> bit_shift != 0xFF) | |
267 | bit_shift++; | |
268 | ||
269 | /* | |
270 | * The portion of the address that is used for the hash table | |
271 | * is determined by the mc_filter_type setting. | |
272 | * The algorithm is such that there is a total of 8 bits of shifting. | |
273 | * The bit_shift for a mc_filter_type of 0 represents the number of | |
274 | * left-shifts where the MSB of mc_addr[5] would still fall within | |
275 | * the hash_mask. Case 0 does this exactly. Since there are a total | |
276 | * of 8 bits of shifting, then mc_addr[4] will shift right the | |
277 | * remaining number of bits. Thus 8 - bit_shift. The rest of the | |
278 | * cases are a variation of this algorithm...essentially raising the | |
279 | * number of bits to shift mc_addr[5] left, while still keeping the | |
280 | * 8-bit shifting total. | |
281 | * | |
282 | * For example, given the following Destination MAC Address and an | |
283 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), | |
284 | * we can see that the bit_shift for case 0 is 4. These are the hash | |
285 | * values resulting from each mc_filter_type... | |
286 | * [0] [1] [2] [3] [4] [5] | |
287 | * 01 AA 00 12 34 56 | |
288 | * LSB MSB | |
289 | * | |
290 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 | |
291 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 | |
292 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 | |
293 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 | |
294 | */ | |
295 | switch (hw->mac.mc_filter_type) { | |
296 | default: | |
297 | case 0: | |
298 | break; | |
299 | case 1: | |
300 | bit_shift += 1; | |
301 | break; | |
302 | case 2: | |
303 | bit_shift += 2; | |
304 | break; | |
305 | case 3: | |
306 | bit_shift += 4; | |
307 | break; | |
308 | } | |
309 | ||
310 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | | |
311 | (((u16) mc_addr[5]) << bit_shift))); | |
312 | ||
313 | return hash_value; | |
314 | } | |
315 | ||
316 | /** | |
733596be | 317 | * igb_clear_hw_cntrs_base - Clear base hardware counters |
9d5c8243 AK |
318 | * @hw: pointer to the HW structure |
319 | * | |
320 | * Clears the base hardware counters by reading the counter registers. | |
321 | **/ | |
322 | void igb_clear_hw_cntrs_base(struct e1000_hw *hw) | |
323 | { | |
324 | u32 temp; | |
325 | ||
326 | temp = rd32(E1000_CRCERRS); | |
327 | temp = rd32(E1000_SYMERRS); | |
328 | temp = rd32(E1000_MPC); | |
329 | temp = rd32(E1000_SCC); | |
330 | temp = rd32(E1000_ECOL); | |
331 | temp = rd32(E1000_MCC); | |
332 | temp = rd32(E1000_LATECOL); | |
333 | temp = rd32(E1000_COLC); | |
334 | temp = rd32(E1000_DC); | |
335 | temp = rd32(E1000_SEC); | |
336 | temp = rd32(E1000_RLEC); | |
337 | temp = rd32(E1000_XONRXC); | |
338 | temp = rd32(E1000_XONTXC); | |
339 | temp = rd32(E1000_XOFFRXC); | |
340 | temp = rd32(E1000_XOFFTXC); | |
341 | temp = rd32(E1000_FCRUC); | |
342 | temp = rd32(E1000_GPRC); | |
343 | temp = rd32(E1000_BPRC); | |
344 | temp = rd32(E1000_MPRC); | |
345 | temp = rd32(E1000_GPTC); | |
346 | temp = rd32(E1000_GORCL); | |
347 | temp = rd32(E1000_GORCH); | |
348 | temp = rd32(E1000_GOTCL); | |
349 | temp = rd32(E1000_GOTCH); | |
350 | temp = rd32(E1000_RNBC); | |
351 | temp = rd32(E1000_RUC); | |
352 | temp = rd32(E1000_RFC); | |
353 | temp = rd32(E1000_ROC); | |
354 | temp = rd32(E1000_RJC); | |
355 | temp = rd32(E1000_TORL); | |
356 | temp = rd32(E1000_TORH); | |
357 | temp = rd32(E1000_TOTL); | |
358 | temp = rd32(E1000_TOTH); | |
359 | temp = rd32(E1000_TPR); | |
360 | temp = rd32(E1000_TPT); | |
361 | temp = rd32(E1000_MPTC); | |
362 | temp = rd32(E1000_BPTC); | |
363 | } | |
364 | ||
365 | /** | |
733596be | 366 | * igb_check_for_copper_link - Check for link (Copper) |
9d5c8243 AK |
367 | * @hw: pointer to the HW structure |
368 | * | |
369 | * Checks to see of the link status of the hardware has changed. If a | |
370 | * change in link status has been detected, then we read the PHY registers | |
371 | * to get the current speed/duplex if link exists. | |
372 | **/ | |
373 | s32 igb_check_for_copper_link(struct e1000_hw *hw) | |
374 | { | |
375 | struct e1000_mac_info *mac = &hw->mac; | |
376 | s32 ret_val; | |
377 | bool link; | |
378 | ||
379 | /* | |
380 | * We only want to go out to the PHY registers to see if Auto-Neg | |
381 | * has completed and/or if our link status has changed. The | |
382 | * get_link_status flag is set upon receiving a Link Status | |
383 | * Change or Rx Sequence Error interrupt. | |
384 | */ | |
385 | if (!mac->get_link_status) { | |
386 | ret_val = 0; | |
387 | goto out; | |
388 | } | |
389 | ||
390 | /* | |
391 | * First we want to see if the MII Status Register reports | |
392 | * link. If so, then we want to get the current speed/duplex | |
393 | * of the PHY. | |
394 | */ | |
395 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
396 | if (ret_val) | |
397 | goto out; | |
398 | ||
399 | if (!link) | |
400 | goto out; /* No link detected */ | |
401 | ||
402 | mac->get_link_status = false; | |
403 | ||
404 | /* | |
405 | * Check if there was DownShift, must be checked | |
406 | * immediately after link-up | |
407 | */ | |
408 | igb_check_downshift(hw); | |
409 | ||
410 | /* | |
411 | * If we are forcing speed/duplex, then we simply return since | |
412 | * we have already determined whether we have link or not. | |
413 | */ | |
414 | if (!mac->autoneg) { | |
415 | ret_val = -E1000_ERR_CONFIG; | |
416 | goto out; | |
417 | } | |
418 | ||
419 | /* | |
420 | * Auto-Neg is enabled. Auto Speed Detection takes care | |
421 | * of MAC speed/duplex configuration. So we only need to | |
422 | * configure Collision Distance in the MAC. | |
423 | */ | |
424 | igb_config_collision_dist(hw); | |
425 | ||
426 | /* | |
427 | * Configure Flow Control now that Auto-Neg has completed. | |
428 | * First, we need to restore the desired flow control | |
429 | * settings because we may have had to re-autoneg with a | |
430 | * different link partner. | |
431 | */ | |
432 | ret_val = igb_config_fc_after_link_up(hw); | |
433 | if (ret_val) | |
652fff32 | 434 | hw_dbg("Error configuring flow control\n"); |
9d5c8243 AK |
435 | |
436 | out: | |
437 | return ret_val; | |
438 | } | |
439 | ||
440 | /** | |
733596be | 441 | * igb_setup_link - Setup flow control and link settings |
9d5c8243 AK |
442 | * @hw: pointer to the HW structure |
443 | * | |
444 | * Determines which flow control settings to use, then configures flow | |
445 | * control. Calls the appropriate media-specific link configuration | |
446 | * function. Assuming the adapter has a valid link partner, a valid link | |
447 | * should be established. Assumes the hardware has previously been reset | |
448 | * and the transmitter and receiver are not enabled. | |
449 | **/ | |
450 | s32 igb_setup_link(struct e1000_hw *hw) | |
451 | { | |
452 | s32 ret_val = 0; | |
453 | ||
454 | /* | |
455 | * In the case of the phy reset being blocked, we already have a link. | |
456 | * We do not need to set it up again. | |
457 | */ | |
458 | if (igb_check_reset_block(hw)) | |
459 | goto out; | |
460 | ||
461 | ret_val = igb_set_default_fc(hw); | |
462 | if (ret_val) | |
463 | goto out; | |
464 | ||
465 | /* | |
466 | * We want to save off the original Flow Control configuration just | |
467 | * in case we get disconnected and then reconnected into a different | |
468 | * hub or switch with different Flow Control capabilities. | |
469 | */ | |
470 | hw->fc.original_type = hw->fc.type; | |
471 | ||
652fff32 | 472 | hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type); |
9d5c8243 AK |
473 | |
474 | /* Call the necessary media_type subroutine to configure the link. */ | |
475 | ret_val = hw->mac.ops.setup_physical_interface(hw); | |
476 | if (ret_val) | |
477 | goto out; | |
478 | ||
479 | /* | |
480 | * Initialize the flow control address, type, and PAUSE timer | |
481 | * registers to their default values. This is done even if flow | |
482 | * control is disabled, because it does not hurt anything to | |
483 | * initialize these registers. | |
484 | */ | |
652fff32 | 485 | hw_dbg("Initializing the Flow Control address, type and timer regs\n"); |
9d5c8243 AK |
486 | wr32(E1000_FCT, FLOW_CONTROL_TYPE); |
487 | wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
488 | wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
489 | ||
490 | wr32(E1000_FCTTV, hw->fc.pause_time); | |
491 | ||
492 | ret_val = igb_set_fc_watermarks(hw); | |
493 | ||
494 | out: | |
495 | return ret_val; | |
496 | } | |
497 | ||
498 | /** | |
733596be | 499 | * igb_config_collision_dist - Configure collision distance |
9d5c8243 AK |
500 | * @hw: pointer to the HW structure |
501 | * | |
502 | * Configures the collision distance to the default value and is used | |
503 | * during link setup. Currently no func pointer exists and all | |
504 | * implementations are handled in the generic version of this function. | |
505 | **/ | |
506 | void igb_config_collision_dist(struct e1000_hw *hw) | |
507 | { | |
508 | u32 tctl; | |
509 | ||
510 | tctl = rd32(E1000_TCTL); | |
511 | ||
512 | tctl &= ~E1000_TCTL_COLD; | |
513 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; | |
514 | ||
515 | wr32(E1000_TCTL, tctl); | |
516 | wrfl(); | |
517 | } | |
518 | ||
519 | /** | |
733596be | 520 | * igb_set_fc_watermarks - Set flow control high/low watermarks |
9d5c8243 AK |
521 | * @hw: pointer to the HW structure |
522 | * | |
523 | * Sets the flow control high/low threshold (watermark) registers. If | |
524 | * flow control XON frame transmission is enabled, then set XON frame | |
525 | * tansmission as well. | |
526 | **/ | |
527 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw) | |
528 | { | |
529 | s32 ret_val = 0; | |
530 | u32 fcrtl = 0, fcrth = 0; | |
531 | ||
532 | /* | |
533 | * Set the flow control receive threshold registers. Normally, | |
534 | * these registers will be set to a default threshold that may be | |
535 | * adjusted later by the driver's runtime code. However, if the | |
536 | * ability to transmit pause frames is not enabled, then these | |
537 | * registers will be set to 0. | |
538 | */ | |
539 | if (hw->fc.type & e1000_fc_tx_pause) { | |
540 | /* | |
541 | * We need to set up the Receive Threshold high and low water | |
542 | * marks as well as (optionally) enabling the transmission of | |
543 | * XON frames. | |
544 | */ | |
545 | fcrtl = hw->fc.low_water; | |
546 | if (hw->fc.send_xon) | |
547 | fcrtl |= E1000_FCRTL_XONE; | |
548 | ||
549 | fcrth = hw->fc.high_water; | |
550 | } | |
551 | wr32(E1000_FCRTL, fcrtl); | |
552 | wr32(E1000_FCRTH, fcrth); | |
553 | ||
554 | return ret_val; | |
555 | } | |
556 | ||
557 | /** | |
733596be | 558 | * igb_set_default_fc - Set flow control default values |
9d5c8243 AK |
559 | * @hw: pointer to the HW structure |
560 | * | |
561 | * Read the EEPROM for the default values for flow control and store the | |
562 | * values. | |
563 | **/ | |
564 | static s32 igb_set_default_fc(struct e1000_hw *hw) | |
565 | { | |
566 | s32 ret_val = 0; | |
567 | u16 nvm_data; | |
568 | ||
569 | /* | |
570 | * Read and store word 0x0F of the EEPROM. This word contains bits | |
571 | * that determine the hardware's default PAUSE (flow control) mode, | |
572 | * a bit that determines whether the HW defaults to enabling or | |
573 | * disabling auto-negotiation, and the direction of the | |
574 | * SW defined pins. If there is no SW over-ride of the flow | |
575 | * control setting, then the variable hw->fc will | |
576 | * be initialized based on a value in the EEPROM. | |
577 | */ | |
578 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, | |
579 | &nvm_data); | |
580 | ||
581 | if (ret_val) { | |
652fff32 | 582 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
583 | goto out; |
584 | } | |
585 | ||
586 | if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) | |
587 | hw->fc.type = e1000_fc_none; | |
588 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == | |
589 | NVM_WORD0F_ASM_DIR) | |
590 | hw->fc.type = e1000_fc_tx_pause; | |
591 | else | |
592 | hw->fc.type = e1000_fc_full; | |
593 | ||
594 | out: | |
595 | return ret_val; | |
596 | } | |
597 | ||
598 | /** | |
733596be | 599 | * igb_force_mac_fc - Force the MAC's flow control settings |
9d5c8243 AK |
600 | * @hw: pointer to the HW structure |
601 | * | |
602 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the | |
603 | * device control register to reflect the adapter settings. TFCE and RFCE | |
604 | * need to be explicitly set by software when a copper PHY is used because | |
605 | * autonegotiation is managed by the PHY rather than the MAC. Software must | |
606 | * also configure these bits when link is forced on a fiber connection. | |
607 | **/ | |
608 | s32 igb_force_mac_fc(struct e1000_hw *hw) | |
609 | { | |
610 | u32 ctrl; | |
611 | s32 ret_val = 0; | |
612 | ||
613 | ctrl = rd32(E1000_CTRL); | |
614 | ||
615 | /* | |
616 | * Because we didn't get link via the internal auto-negotiation | |
617 | * mechanism (we either forced link or we got link via PHY | |
618 | * auto-neg), we have to manually enable/disable transmit an | |
619 | * receive flow control. | |
620 | * | |
621 | * The "Case" statement below enables/disable flow control | |
622 | * according to the "hw->fc.type" parameter. | |
623 | * | |
624 | * The possible values of the "fc" parameter are: | |
625 | * 0: Flow control is completely disabled | |
626 | * 1: Rx flow control is enabled (we can receive pause | |
627 | * frames but not send pause frames). | |
628 | * 2: Tx flow control is enabled (we can send pause frames | |
629 | * frames but we do not receive pause frames). | |
630 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
631 | * other: No other values should be possible at this point. | |
632 | */ | |
652fff32 | 633 | hw_dbg("hw->fc.type = %u\n", hw->fc.type); |
9d5c8243 AK |
634 | |
635 | switch (hw->fc.type) { | |
636 | case e1000_fc_none: | |
637 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | |
638 | break; | |
639 | case e1000_fc_rx_pause: | |
640 | ctrl &= (~E1000_CTRL_TFCE); | |
641 | ctrl |= E1000_CTRL_RFCE; | |
642 | break; | |
643 | case e1000_fc_tx_pause: | |
644 | ctrl &= (~E1000_CTRL_RFCE); | |
645 | ctrl |= E1000_CTRL_TFCE; | |
646 | break; | |
647 | case e1000_fc_full: | |
648 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | |
649 | break; | |
650 | default: | |
652fff32 | 651 | hw_dbg("Flow control param set incorrectly\n"); |
9d5c8243 AK |
652 | ret_val = -E1000_ERR_CONFIG; |
653 | goto out; | |
654 | } | |
655 | ||
656 | wr32(E1000_CTRL, ctrl); | |
657 | ||
658 | out: | |
659 | return ret_val; | |
660 | } | |
661 | ||
662 | /** | |
733596be | 663 | * igb_config_fc_after_link_up - Configures flow control after link |
9d5c8243 AK |
664 | * @hw: pointer to the HW structure |
665 | * | |
666 | * Checks the status of auto-negotiation after link up to ensure that the | |
667 | * speed and duplex were not forced. If the link needed to be forced, then | |
668 | * flow control needs to be forced also. If auto-negotiation is enabled | |
669 | * and did not fail, then we configure flow control based on our link | |
670 | * partner. | |
671 | **/ | |
672 | s32 igb_config_fc_after_link_up(struct e1000_hw *hw) | |
673 | { | |
674 | struct e1000_mac_info *mac = &hw->mac; | |
675 | s32 ret_val = 0; | |
676 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; | |
677 | u16 speed, duplex; | |
678 | ||
679 | /* | |
680 | * Check for the case where we have fiber media and auto-neg failed | |
681 | * so we had to force link. In this case, we need to force the | |
682 | * configuration of the MAC to match the "fc" parameter. | |
683 | */ | |
684 | if (mac->autoneg_failed) { | |
685 | if (hw->phy.media_type == e1000_media_type_fiber || | |
686 | hw->phy.media_type == e1000_media_type_internal_serdes) | |
687 | ret_val = igb_force_mac_fc(hw); | |
688 | } else { | |
689 | if (hw->phy.media_type == e1000_media_type_copper) | |
690 | ret_val = igb_force_mac_fc(hw); | |
691 | } | |
692 | ||
693 | if (ret_val) { | |
652fff32 | 694 | hw_dbg("Error forcing flow control settings\n"); |
9d5c8243 AK |
695 | goto out; |
696 | } | |
697 | ||
698 | /* | |
699 | * Check for the case where we have copper media and auto-neg is | |
700 | * enabled. In this case, we need to check and see if Auto-Neg | |
701 | * has completed, and if so, how the PHY and link partner has | |
702 | * flow control configured. | |
703 | */ | |
704 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { | |
705 | /* | |
706 | * Read the MII Status Register and check to see if AutoNeg | |
707 | * has completed. We read this twice because this reg has | |
708 | * some "sticky" (latched) bits. | |
709 | */ | |
710 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, | |
711 | &mii_status_reg); | |
712 | if (ret_val) | |
713 | goto out; | |
714 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, | |
715 | &mii_status_reg); | |
716 | if (ret_val) | |
717 | goto out; | |
718 | ||
719 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { | |
652fff32 | 720 | hw_dbg("Copper PHY and Auto Neg " |
9d5c8243 AK |
721 | "has not completed.\n"); |
722 | goto out; | |
723 | } | |
724 | ||
725 | /* | |
726 | * The AutoNeg process has completed, so we now need to | |
727 | * read both the Auto Negotiation Advertisement | |
728 | * Register (Address 4) and the Auto_Negotiation Base | |
729 | * Page Ability Register (Address 5) to determine how | |
730 | * flow control was negotiated. | |
731 | */ | |
732 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV, | |
733 | &mii_nway_adv_reg); | |
734 | if (ret_val) | |
735 | goto out; | |
736 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_LP_ABILITY, | |
737 | &mii_nway_lp_ability_reg); | |
738 | if (ret_val) | |
739 | goto out; | |
740 | ||
741 | /* | |
742 | * Two bits in the Auto Negotiation Advertisement Register | |
743 | * (Address 4) and two bits in the Auto Negotiation Base | |
744 | * Page Ability Register (Address 5) determine flow control | |
745 | * for both the PHY and the link partner. The following | |
746 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
747 | * 1999, describes these PAUSE resolution bits and how flow | |
748 | * control is determined based upon these settings. | |
749 | * NOTE: DC = Don't Care | |
750 | * | |
751 | * LOCAL DEVICE | LINK PARTNER | |
752 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
753 | *-------|---------|-------|---------|-------------------- | |
754 | * 0 | 0 | DC | DC | e1000_fc_none | |
755 | * 0 | 1 | 0 | DC | e1000_fc_none | |
756 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
757 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
758 | * 1 | 0 | 0 | DC | e1000_fc_none | |
759 | * 1 | DC | 1 | DC | e1000_fc_full | |
760 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
761 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
762 | * | |
763 | * Are both PAUSE bits set to 1? If so, this implies | |
764 | * Symmetric Flow Control is enabled at both ends. The | |
765 | * ASM_DIR bits are irrelevant per the spec. | |
766 | * | |
767 | * For Symmetric Flow Control: | |
768 | * | |
769 | * LOCAL DEVICE | LINK PARTNER | |
770 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
771 | *-------|---------|-------|---------|-------------------- | |
772 | * 1 | DC | 1 | DC | E1000_fc_full | |
773 | * | |
774 | */ | |
775 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
776 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
777 | /* | |
778 | * Now we need to check if the user selected RX ONLY | |
779 | * of pause frames. In this case, we had to advertise | |
780 | * FULL flow control because we could not advertise RX | |
781 | * ONLY. Hence, we must now check to see if we need to | |
782 | * turn OFF the TRANSMISSION of PAUSE frames. | |
783 | */ | |
784 | if (hw->fc.original_type == e1000_fc_full) { | |
785 | hw->fc.type = e1000_fc_full; | |
652fff32 | 786 | hw_dbg("Flow Control = FULL.\r\n"); |
9d5c8243 AK |
787 | } else { |
788 | hw->fc.type = e1000_fc_rx_pause; | |
652fff32 AK |
789 | hw_dbg("Flow Control = " |
790 | "RX PAUSE frames only.\r\n"); | |
9d5c8243 AK |
791 | } |
792 | } | |
793 | /* | |
794 | * For receiving PAUSE frames ONLY. | |
795 | * | |
796 | * LOCAL DEVICE | LINK PARTNER | |
797 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
798 | *-------|---------|-------|---------|-------------------- | |
799 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
800 | */ | |
801 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
802 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
803 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
804 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
805 | hw->fc.type = e1000_fc_tx_pause; | |
652fff32 | 806 | hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); |
9d5c8243 AK |
807 | } |
808 | /* | |
809 | * For transmitting PAUSE frames ONLY. | |
810 | * | |
811 | * LOCAL DEVICE | LINK PARTNER | |
812 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
813 | *-------|---------|-------|---------|-------------------- | |
814 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
815 | */ | |
816 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
817 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
818 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
819 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
820 | hw->fc.type = e1000_fc_rx_pause; | |
652fff32 | 821 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
9d5c8243 AK |
822 | } |
823 | /* | |
824 | * Per the IEEE spec, at this point flow control should be | |
825 | * disabled. However, we want to consider that we could | |
826 | * be connected to a legacy switch that doesn't advertise | |
827 | * desired flow control, but can be forced on the link | |
828 | * partner. So if we advertised no flow control, that is | |
829 | * what we will resolve to. If we advertised some kind of | |
830 | * receive capability (Rx Pause Only or Full Flow Control) | |
831 | * and the link partner advertised none, we will configure | |
832 | * ourselves to enable Rx Flow Control only. We can do | |
833 | * this safely for two reasons: If the link partner really | |
834 | * didn't want flow control enabled, and we enable Rx, no | |
835 | * harm done since we won't be receiving any PAUSE frames | |
836 | * anyway. If the intent on the link partner was to have | |
837 | * flow control enabled, then by us enabling RX only, we | |
838 | * can at least receive pause frames and process them. | |
839 | * This is a good idea because in most cases, since we are | |
840 | * predominantly a server NIC, more times than not we will | |
841 | * be asked to delay transmission of packets than asking | |
842 | * our link partner to pause transmission of frames. | |
843 | */ | |
844 | else if ((hw->fc.original_type == e1000_fc_none || | |
845 | hw->fc.original_type == e1000_fc_tx_pause) || | |
846 | hw->fc.strict_ieee) { | |
847 | hw->fc.type = e1000_fc_none; | |
652fff32 | 848 | hw_dbg("Flow Control = NONE.\r\n"); |
9d5c8243 AK |
849 | } else { |
850 | hw->fc.type = e1000_fc_rx_pause; | |
652fff32 | 851 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
9d5c8243 AK |
852 | } |
853 | ||
854 | /* | |
855 | * Now we need to do one last check... If we auto- | |
856 | * negotiated to HALF DUPLEX, flow control should not be | |
857 | * enabled per IEEE 802.3 spec. | |
858 | */ | |
859 | ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); | |
860 | if (ret_val) { | |
652fff32 | 861 | hw_dbg("Error getting link speed and duplex\n"); |
9d5c8243 AK |
862 | goto out; |
863 | } | |
864 | ||
865 | if (duplex == HALF_DUPLEX) | |
866 | hw->fc.type = e1000_fc_none; | |
867 | ||
868 | /* | |
869 | * Now we call a subroutine to actually force the MAC | |
870 | * controller to use the correct flow control settings. | |
871 | */ | |
872 | ret_val = igb_force_mac_fc(hw); | |
873 | if (ret_val) { | |
652fff32 | 874 | hw_dbg("Error forcing flow control settings\n"); |
9d5c8243 AK |
875 | goto out; |
876 | } | |
877 | } | |
878 | ||
879 | out: | |
880 | return ret_val; | |
881 | } | |
882 | ||
883 | /** | |
733596be | 884 | * igb_get_speed_and_duplex_copper - Retreive current speed/duplex |
9d5c8243 AK |
885 | * @hw: pointer to the HW structure |
886 | * @speed: stores the current speed | |
887 | * @duplex: stores the current duplex | |
888 | * | |
889 | * Read the status register for the current speed/duplex and store the current | |
890 | * speed and duplex for copper connections. | |
891 | **/ | |
892 | s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, | |
893 | u16 *duplex) | |
894 | { | |
895 | u32 status; | |
896 | ||
897 | status = rd32(E1000_STATUS); | |
898 | if (status & E1000_STATUS_SPEED_1000) { | |
899 | *speed = SPEED_1000; | |
652fff32 | 900 | hw_dbg("1000 Mbs, "); |
9d5c8243 AK |
901 | } else if (status & E1000_STATUS_SPEED_100) { |
902 | *speed = SPEED_100; | |
652fff32 | 903 | hw_dbg("100 Mbs, "); |
9d5c8243 AK |
904 | } else { |
905 | *speed = SPEED_10; | |
652fff32 | 906 | hw_dbg("10 Mbs, "); |
9d5c8243 AK |
907 | } |
908 | ||
909 | if (status & E1000_STATUS_FD) { | |
910 | *duplex = FULL_DUPLEX; | |
652fff32 | 911 | hw_dbg("Full Duplex\n"); |
9d5c8243 AK |
912 | } else { |
913 | *duplex = HALF_DUPLEX; | |
652fff32 | 914 | hw_dbg("Half Duplex\n"); |
9d5c8243 AK |
915 | } |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | /** | |
733596be | 921 | * igb_get_hw_semaphore - Acquire hardware semaphore |
9d5c8243 AK |
922 | * @hw: pointer to the HW structure |
923 | * | |
924 | * Acquire the HW semaphore to access the PHY or NVM | |
925 | **/ | |
926 | s32 igb_get_hw_semaphore(struct e1000_hw *hw) | |
927 | { | |
928 | u32 swsm; | |
929 | s32 ret_val = 0; | |
930 | s32 timeout = hw->nvm.word_size + 1; | |
931 | s32 i = 0; | |
932 | ||
933 | /* Get the SW semaphore */ | |
934 | while (i < timeout) { | |
935 | swsm = rd32(E1000_SWSM); | |
936 | if (!(swsm & E1000_SWSM_SMBI)) | |
937 | break; | |
938 | ||
939 | udelay(50); | |
940 | i++; | |
941 | } | |
942 | ||
943 | if (i == timeout) { | |
652fff32 | 944 | hw_dbg("Driver can't access device - SMBI bit is set.\n"); |
9d5c8243 AK |
945 | ret_val = -E1000_ERR_NVM; |
946 | goto out; | |
947 | } | |
948 | ||
949 | /* Get the FW semaphore. */ | |
950 | for (i = 0; i < timeout; i++) { | |
951 | swsm = rd32(E1000_SWSM); | |
952 | wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); | |
953 | ||
954 | /* Semaphore acquired if bit latched */ | |
955 | if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) | |
956 | break; | |
957 | ||
958 | udelay(50); | |
959 | } | |
960 | ||
961 | if (i == timeout) { | |
962 | /* Release semaphores */ | |
963 | igb_put_hw_semaphore(hw); | |
652fff32 | 964 | hw_dbg("Driver can't access the NVM\n"); |
9d5c8243 AK |
965 | ret_val = -E1000_ERR_NVM; |
966 | goto out; | |
967 | } | |
968 | ||
969 | out: | |
970 | return ret_val; | |
971 | } | |
972 | ||
973 | /** | |
733596be | 974 | * igb_put_hw_semaphore - Release hardware semaphore |
9d5c8243 AK |
975 | * @hw: pointer to the HW structure |
976 | * | |
977 | * Release hardware semaphore used to access the PHY or NVM | |
978 | **/ | |
979 | void igb_put_hw_semaphore(struct e1000_hw *hw) | |
980 | { | |
981 | u32 swsm; | |
982 | ||
983 | swsm = rd32(E1000_SWSM); | |
984 | ||
985 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
986 | ||
987 | wr32(E1000_SWSM, swsm); | |
988 | } | |
989 | ||
990 | /** | |
733596be | 991 | * igb_get_auto_rd_done - Check for auto read completion |
9d5c8243 AK |
992 | * @hw: pointer to the HW structure |
993 | * | |
994 | * Check EEPROM for Auto Read done bit. | |
995 | **/ | |
996 | s32 igb_get_auto_rd_done(struct e1000_hw *hw) | |
997 | { | |
998 | s32 i = 0; | |
999 | s32 ret_val = 0; | |
1000 | ||
1001 | ||
1002 | while (i < AUTO_READ_DONE_TIMEOUT) { | |
1003 | if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD) | |
1004 | break; | |
1005 | msleep(1); | |
1006 | i++; | |
1007 | } | |
1008 | ||
1009 | if (i == AUTO_READ_DONE_TIMEOUT) { | |
652fff32 | 1010 | hw_dbg("Auto read by HW from NVM has not completed.\n"); |
9d5c8243 AK |
1011 | ret_val = -E1000_ERR_RESET; |
1012 | goto out; | |
1013 | } | |
1014 | ||
1015 | out: | |
1016 | return ret_val; | |
1017 | } | |
1018 | ||
1019 | /** | |
733596be | 1020 | * igb_valid_led_default - Verify a valid default LED config |
9d5c8243 AK |
1021 | * @hw: pointer to the HW structure |
1022 | * @data: pointer to the NVM (EEPROM) | |
1023 | * | |
1024 | * Read the EEPROM for the current default LED configuration. If the | |
1025 | * LED configuration is not valid, set to a valid LED configuration. | |
1026 | **/ | |
1027 | static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) | |
1028 | { | |
1029 | s32 ret_val; | |
1030 | ||
1031 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1032 | if (ret_val) { | |
652fff32 | 1033 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
1034 | goto out; |
1035 | } | |
1036 | ||
1037 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) | |
1038 | *data = ID_LED_DEFAULT; | |
1039 | ||
1040 | out: | |
1041 | return ret_val; | |
1042 | } | |
1043 | ||
1044 | /** | |
733596be | 1045 | * igb_id_led_init - |
9d5c8243 AK |
1046 | * @hw: pointer to the HW structure |
1047 | * | |
1048 | **/ | |
1049 | s32 igb_id_led_init(struct e1000_hw *hw) | |
1050 | { | |
1051 | struct e1000_mac_info *mac = &hw->mac; | |
1052 | s32 ret_val; | |
1053 | const u32 ledctl_mask = 0x000000FF; | |
1054 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; | |
1055 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | |
1056 | u16 data, i, temp; | |
1057 | const u16 led_mask = 0x0F; | |
1058 | ||
1059 | ret_val = igb_valid_led_default(hw, &data); | |
1060 | if (ret_val) | |
1061 | goto out; | |
1062 | ||
1063 | mac->ledctl_default = rd32(E1000_LEDCTL); | |
1064 | mac->ledctl_mode1 = mac->ledctl_default; | |
1065 | mac->ledctl_mode2 = mac->ledctl_default; | |
1066 | ||
1067 | for (i = 0; i < 4; i++) { | |
1068 | temp = (data >> (i << 2)) & led_mask; | |
1069 | switch (temp) { | |
1070 | case ID_LED_ON1_DEF2: | |
1071 | case ID_LED_ON1_ON2: | |
1072 | case ID_LED_ON1_OFF2: | |
1073 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
1074 | mac->ledctl_mode1 |= ledctl_on << (i << 3); | |
1075 | break; | |
1076 | case ID_LED_OFF1_DEF2: | |
1077 | case ID_LED_OFF1_ON2: | |
1078 | case ID_LED_OFF1_OFF2: | |
1079 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
1080 | mac->ledctl_mode1 |= ledctl_off << (i << 3); | |
1081 | break; | |
1082 | default: | |
1083 | /* Do nothing */ | |
1084 | break; | |
1085 | } | |
1086 | switch (temp) { | |
1087 | case ID_LED_DEF1_ON2: | |
1088 | case ID_LED_ON1_ON2: | |
1089 | case ID_LED_OFF1_ON2: | |
1090 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
1091 | mac->ledctl_mode2 |= ledctl_on << (i << 3); | |
1092 | break; | |
1093 | case ID_LED_DEF1_OFF2: | |
1094 | case ID_LED_ON1_OFF2: | |
1095 | case ID_LED_OFF1_OFF2: | |
1096 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
1097 | mac->ledctl_mode2 |= ledctl_off << (i << 3); | |
1098 | break; | |
1099 | default: | |
1100 | /* Do nothing */ | |
1101 | break; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | out: | |
1106 | return ret_val; | |
1107 | } | |
1108 | ||
1109 | /** | |
733596be | 1110 | * igb_cleanup_led - Set LED config to default operation |
9d5c8243 AK |
1111 | * @hw: pointer to the HW structure |
1112 | * | |
1113 | * Remove the current LED configuration and set the LED configuration | |
1114 | * to the default value, saved from the EEPROM. | |
1115 | **/ | |
1116 | s32 igb_cleanup_led(struct e1000_hw *hw) | |
1117 | { | |
1118 | wr32(E1000_LEDCTL, hw->mac.ledctl_default); | |
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | /** | |
733596be | 1123 | * igb_blink_led - Blink LED |
9d5c8243 AK |
1124 | * @hw: pointer to the HW structure |
1125 | * | |
1126 | * Blink the led's which are set to be on. | |
1127 | **/ | |
1128 | s32 igb_blink_led(struct e1000_hw *hw) | |
1129 | { | |
1130 | u32 ledctl_blink = 0; | |
1131 | u32 i; | |
1132 | ||
1133 | if (hw->phy.media_type == e1000_media_type_fiber) { | |
1134 | /* always blink LED0 for PCI-E fiber */ | |
1135 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | | |
1136 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); | |
1137 | } else { | |
1138 | /* | |
1139 | * set the blink bit for each LED that's "on" (0x0E) | |
1140 | * in ledctl_mode2 | |
1141 | */ | |
1142 | ledctl_blink = hw->mac.ledctl_mode2; | |
1143 | for (i = 0; i < 4; i++) | |
1144 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1145 | E1000_LEDCTL_MODE_LED_ON) | |
1146 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << | |
1147 | (i * 8)); | |
1148 | } | |
1149 | ||
1150 | wr32(E1000_LEDCTL, ledctl_blink); | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /** | |
733596be | 1156 | * igb_led_off - Turn LED off |
9d5c8243 AK |
1157 | * @hw: pointer to the HW structure |
1158 | * | |
1159 | * Turn LED off. | |
1160 | **/ | |
1161 | s32 igb_led_off(struct e1000_hw *hw) | |
1162 | { | |
1163 | u32 ctrl; | |
1164 | ||
1165 | switch (hw->phy.media_type) { | |
1166 | case e1000_media_type_fiber: | |
1167 | ctrl = rd32(E1000_CTRL); | |
1168 | ctrl |= E1000_CTRL_SWDPIN0; | |
1169 | ctrl |= E1000_CTRL_SWDPIO0; | |
1170 | wr32(E1000_CTRL, ctrl); | |
1171 | break; | |
1172 | case e1000_media_type_copper: | |
1173 | wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); | |
1174 | break; | |
1175 | default: | |
1176 | break; | |
1177 | } | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /** | |
733596be | 1183 | * igb_disable_pcie_master - Disables PCI-express master access |
9d5c8243 AK |
1184 | * @hw: pointer to the HW structure |
1185 | * | |
1186 | * Returns 0 (0) if successful, else returns -10 | |
1187 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued | |
1188 | * the master requests to be disabled. | |
1189 | * | |
1190 | * Disables PCI-Express master access and verifies there are no pending | |
1191 | * requests. | |
1192 | **/ | |
1193 | s32 igb_disable_pcie_master(struct e1000_hw *hw) | |
1194 | { | |
1195 | u32 ctrl; | |
1196 | s32 timeout = MASTER_DISABLE_TIMEOUT; | |
1197 | s32 ret_val = 0; | |
1198 | ||
1199 | if (hw->bus.type != e1000_bus_type_pci_express) | |
1200 | goto out; | |
1201 | ||
1202 | ctrl = rd32(E1000_CTRL); | |
1203 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | |
1204 | wr32(E1000_CTRL, ctrl); | |
1205 | ||
1206 | while (timeout) { | |
1207 | if (!(rd32(E1000_STATUS) & | |
1208 | E1000_STATUS_GIO_MASTER_ENABLE)) | |
1209 | break; | |
1210 | udelay(100); | |
1211 | timeout--; | |
1212 | } | |
1213 | ||
1214 | if (!timeout) { | |
652fff32 | 1215 | hw_dbg("Master requests are pending.\n"); |
9d5c8243 AK |
1216 | ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; |
1217 | goto out; | |
1218 | } | |
1219 | ||
1220 | out: | |
1221 | return ret_val; | |
1222 | } | |
1223 | ||
1224 | /** | |
733596be | 1225 | * igb_reset_adaptive - Reset Adaptive Interframe Spacing |
9d5c8243 AK |
1226 | * @hw: pointer to the HW structure |
1227 | * | |
1228 | * Reset the Adaptive Interframe Spacing throttle to default values. | |
1229 | **/ | |
1230 | void igb_reset_adaptive(struct e1000_hw *hw) | |
1231 | { | |
1232 | struct e1000_mac_info *mac = &hw->mac; | |
1233 | ||
1234 | if (!mac->adaptive_ifs) { | |
652fff32 | 1235 | hw_dbg("Not in Adaptive IFS mode!\n"); |
9d5c8243 AK |
1236 | goto out; |
1237 | } | |
1238 | ||
1239 | if (!mac->ifs_params_forced) { | |
1240 | mac->current_ifs_val = 0; | |
1241 | mac->ifs_min_val = IFS_MIN; | |
1242 | mac->ifs_max_val = IFS_MAX; | |
1243 | mac->ifs_step_size = IFS_STEP; | |
1244 | mac->ifs_ratio = IFS_RATIO; | |
1245 | } | |
1246 | ||
1247 | mac->in_ifs_mode = false; | |
1248 | wr32(E1000_AIT, 0); | |
1249 | out: | |
1250 | return; | |
1251 | } | |
1252 | ||
1253 | /** | |
733596be | 1254 | * igb_update_adaptive - Update Adaptive Interframe Spacing |
9d5c8243 AK |
1255 | * @hw: pointer to the HW structure |
1256 | * | |
1257 | * Update the Adaptive Interframe Spacing Throttle value based on the | |
1258 | * time between transmitted packets and time between collisions. | |
1259 | **/ | |
1260 | void igb_update_adaptive(struct e1000_hw *hw) | |
1261 | { | |
1262 | struct e1000_mac_info *mac = &hw->mac; | |
1263 | ||
1264 | if (!mac->adaptive_ifs) { | |
652fff32 | 1265 | hw_dbg("Not in Adaptive IFS mode!\n"); |
9d5c8243 AK |
1266 | goto out; |
1267 | } | |
1268 | ||
1269 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { | |
1270 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { | |
1271 | mac->in_ifs_mode = true; | |
1272 | if (mac->current_ifs_val < mac->ifs_max_val) { | |
1273 | if (!mac->current_ifs_val) | |
1274 | mac->current_ifs_val = mac->ifs_min_val; | |
1275 | else | |
1276 | mac->current_ifs_val += | |
1277 | mac->ifs_step_size; | |
1278 | wr32(E1000_AIT, | |
1279 | mac->current_ifs_val); | |
1280 | } | |
1281 | } | |
1282 | } else { | |
1283 | if (mac->in_ifs_mode && | |
1284 | (mac->tx_packet_delta <= MIN_NUM_XMITS)) { | |
1285 | mac->current_ifs_val = 0; | |
1286 | mac->in_ifs_mode = false; | |
1287 | wr32(E1000_AIT, 0); | |
1288 | } | |
1289 | } | |
1290 | out: | |
1291 | return; | |
1292 | } | |
1293 | ||
1294 | /** | |
733596be | 1295 | * igb_validate_mdi_setting - Verify MDI/MDIx settings |
9d5c8243 AK |
1296 | * @hw: pointer to the HW structure |
1297 | * | |
1298 | * Verify that when not using auto-negotitation that MDI/MDIx is correctly | |
1299 | * set, which is forced to MDI mode only. | |
1300 | **/ | |
1301 | s32 igb_validate_mdi_setting(struct e1000_hw *hw) | |
1302 | { | |
1303 | s32 ret_val = 0; | |
1304 | ||
1305 | if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { | |
652fff32 | 1306 | hw_dbg("Invalid MDI setting detected\n"); |
9d5c8243 AK |
1307 | hw->phy.mdix = 1; |
1308 | ret_val = -E1000_ERR_CONFIG; | |
1309 | goto out; | |
1310 | } | |
1311 | ||
1312 | out: | |
1313 | return ret_val; | |
1314 | } | |
1315 | ||
1316 | /** | |
733596be | 1317 | * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register |
9d5c8243 AK |
1318 | * @hw: pointer to the HW structure |
1319 | * @reg: 32bit register offset such as E1000_SCTL | |
1320 | * @offset: register offset to write to | |
1321 | * @data: data to write at register offset | |
1322 | * | |
1323 | * Writes an address/data control type register. There are several of these | |
1324 | * and they all have the format address << 8 | data and bit 31 is polled for | |
1325 | * completion. | |
1326 | **/ | |
1327 | s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, | |
1328 | u32 offset, u8 data) | |
1329 | { | |
1330 | u32 i, regvalue = 0; | |
1331 | s32 ret_val = 0; | |
1332 | ||
1333 | /* Set up the address and data */ | |
1334 | regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); | |
1335 | wr32(reg, regvalue); | |
1336 | ||
1337 | /* Poll the ready bit to see if the MDI read completed */ | |
1338 | for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { | |
1339 | udelay(5); | |
1340 | regvalue = rd32(reg); | |
1341 | if (regvalue & E1000_GEN_CTL_READY) | |
1342 | break; | |
1343 | } | |
1344 | if (!(regvalue & E1000_GEN_CTL_READY)) { | |
652fff32 | 1345 | hw_dbg("Reg %08x did not indicate ready\n", reg); |
9d5c8243 AK |
1346 | ret_val = -E1000_ERR_PHY; |
1347 | goto out; | |
1348 | } | |
1349 | ||
1350 | out: | |
1351 | return ret_val; | |
1352 | } | |
1353 | ||
1354 | /** | |
733596be | 1355 | * igb_enable_mng_pass_thru - Enable processing of ARP's |
9d5c8243 AK |
1356 | * @hw: pointer to the HW structure |
1357 | * | |
1358 | * Verifies the hardware needs to allow ARPs to be processed by the host. | |
1359 | **/ | |
1360 | bool igb_enable_mng_pass_thru(struct e1000_hw *hw) | |
1361 | { | |
1362 | u32 manc; | |
1363 | u32 fwsm, factps; | |
1364 | bool ret_val = false; | |
1365 | ||
1366 | if (!hw->mac.asf_firmware_present) | |
1367 | goto out; | |
1368 | ||
1369 | manc = rd32(E1000_MANC); | |
1370 | ||
1371 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | |
1372 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | |
1373 | goto out; | |
1374 | ||
1375 | if (hw->mac.arc_subsystem_valid) { | |
1376 | fwsm = rd32(E1000_FWSM); | |
1377 | factps = rd32(E1000_FACTPS); | |
1378 | ||
1379 | if (!(factps & E1000_FACTPS_MNGCG) && | |
1380 | ((fwsm & E1000_FWSM_MODE_MASK) == | |
1381 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { | |
1382 | ret_val = true; | |
1383 | goto out; | |
1384 | } | |
1385 | } else { | |
1386 | if ((manc & E1000_MANC_SMBUS_EN) && | |
1387 | !(manc & E1000_MANC_ASF_EN)) { | |
1388 | ret_val = true; | |
1389 | goto out; | |
1390 | } | |
1391 | } | |
1392 | ||
1393 | out: | |
1394 | return ret_val; | |
1395 | } |