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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4 | Copyright(c) 2007 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/if_ether.h> | |
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000_mac.h" | |
32 | #include "e1000_nvm.h" | |
33 | ||
34 | /** | |
733596be | 35 | * igb_raise_eec_clk - Raise EEPROM clock |
9d5c8243 AK |
36 | * @hw: pointer to the HW structure |
37 | * @eecd: pointer to the EEPROM | |
38 | * | |
39 | * Enable/Raise the EEPROM clock bit. | |
40 | **/ | |
41 | static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) | |
42 | { | |
43 | *eecd = *eecd | E1000_EECD_SK; | |
44 | wr32(E1000_EECD, *eecd); | |
45 | wrfl(); | |
46 | udelay(hw->nvm.delay_usec); | |
47 | } | |
48 | ||
49 | /** | |
733596be | 50 | * igb_lower_eec_clk - Lower EEPROM clock |
9d5c8243 AK |
51 | * @hw: pointer to the HW structure |
52 | * @eecd: pointer to the EEPROM | |
53 | * | |
54 | * Clear/Lower the EEPROM clock bit. | |
55 | **/ | |
56 | static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) | |
57 | { | |
58 | *eecd = *eecd & ~E1000_EECD_SK; | |
59 | wr32(E1000_EECD, *eecd); | |
60 | wrfl(); | |
61 | udelay(hw->nvm.delay_usec); | |
62 | } | |
63 | ||
64 | /** | |
733596be | 65 | * igb_shift_out_eec_bits - Shift data bits our to the EEPROM |
9d5c8243 AK |
66 | * @hw: pointer to the HW structure |
67 | * @data: data to send to the EEPROM | |
68 | * @count: number of bits to shift out | |
69 | * | |
70 | * We need to shift 'count' bits out to the EEPROM. So, the value in the | |
71 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
72 | * In order to do this, "data" must be broken down into bits. | |
73 | **/ | |
74 | static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) | |
75 | { | |
76 | struct e1000_nvm_info *nvm = &hw->nvm; | |
77 | u32 eecd = rd32(E1000_EECD); | |
78 | u32 mask; | |
79 | ||
80 | mask = 0x01 << (count - 1); | |
81 | if (nvm->type == e1000_nvm_eeprom_microwire) | |
82 | eecd &= ~E1000_EECD_DO; | |
83 | else if (nvm->type == e1000_nvm_eeprom_spi) | |
84 | eecd |= E1000_EECD_DO; | |
85 | ||
86 | do { | |
87 | eecd &= ~E1000_EECD_DI; | |
88 | ||
89 | if (data & mask) | |
90 | eecd |= E1000_EECD_DI; | |
91 | ||
92 | wr32(E1000_EECD, eecd); | |
93 | wrfl(); | |
94 | ||
95 | udelay(nvm->delay_usec); | |
96 | ||
97 | igb_raise_eec_clk(hw, &eecd); | |
98 | igb_lower_eec_clk(hw, &eecd); | |
99 | ||
100 | mask >>= 1; | |
101 | } while (mask); | |
102 | ||
103 | eecd &= ~E1000_EECD_DI; | |
104 | wr32(E1000_EECD, eecd); | |
105 | } | |
106 | ||
107 | /** | |
733596be | 108 | * igb_shift_in_eec_bits - Shift data bits in from the EEPROM |
9d5c8243 AK |
109 | * @hw: pointer to the HW structure |
110 | * @count: number of bits to shift in | |
111 | * | |
112 | * In order to read a register from the EEPROM, we need to shift 'count' bits | |
113 | * in from the EEPROM. Bits are "shifted in" by raising the clock input to | |
114 | * the EEPROM (setting the SK bit), and then reading the value of the data out | |
115 | * "DO" bit. During this "shifting in" process the data in "DI" bit should | |
116 | * always be clear. | |
117 | **/ | |
118 | static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) | |
119 | { | |
120 | u32 eecd; | |
121 | u32 i; | |
122 | u16 data; | |
123 | ||
124 | eecd = rd32(E1000_EECD); | |
125 | ||
126 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
127 | data = 0; | |
128 | ||
129 | for (i = 0; i < count; i++) { | |
130 | data <<= 1; | |
131 | igb_raise_eec_clk(hw, &eecd); | |
132 | ||
133 | eecd = rd32(E1000_EECD); | |
134 | ||
135 | eecd &= ~E1000_EECD_DI; | |
136 | if (eecd & E1000_EECD_DO) | |
137 | data |= 1; | |
138 | ||
139 | igb_lower_eec_clk(hw, &eecd); | |
140 | } | |
141 | ||
142 | return data; | |
143 | } | |
144 | ||
145 | /** | |
733596be | 146 | * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
9d5c8243 AK |
147 | * @hw: pointer to the HW structure |
148 | * @ee_reg: EEPROM flag for polling | |
149 | * | |
150 | * Polls the EEPROM status bit for either read or write completion based | |
151 | * upon the value of 'ee_reg'. | |
152 | **/ | |
153 | static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) | |
154 | { | |
155 | u32 attempts = 100000; | |
156 | u32 i, reg = 0; | |
157 | s32 ret_val = -E1000_ERR_NVM; | |
158 | ||
159 | for (i = 0; i < attempts; i++) { | |
160 | if (ee_reg == E1000_NVM_POLL_READ) | |
161 | reg = rd32(E1000_EERD); | |
162 | else | |
163 | reg = rd32(E1000_EEWR); | |
164 | ||
165 | if (reg & E1000_NVM_RW_REG_DONE) { | |
166 | ret_val = 0; | |
167 | break; | |
168 | } | |
169 | ||
170 | udelay(5); | |
171 | } | |
172 | ||
173 | return ret_val; | |
174 | } | |
175 | ||
176 | /** | |
733596be | 177 | * igb_acquire_nvm - Generic request for access to EEPROM |
9d5c8243 AK |
178 | * @hw: pointer to the HW structure |
179 | * | |
180 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. | |
181 | * Return successful if access grant bit set, else clear the request for | |
182 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
183 | **/ | |
184 | s32 igb_acquire_nvm(struct e1000_hw *hw) | |
185 | { | |
186 | u32 eecd = rd32(E1000_EECD); | |
187 | s32 timeout = E1000_NVM_GRANT_ATTEMPTS; | |
188 | s32 ret_val = 0; | |
189 | ||
190 | ||
191 | wr32(E1000_EECD, eecd | E1000_EECD_REQ); | |
192 | eecd = rd32(E1000_EECD); | |
193 | ||
194 | while (timeout) { | |
195 | if (eecd & E1000_EECD_GNT) | |
196 | break; | |
197 | udelay(5); | |
198 | eecd = rd32(E1000_EECD); | |
199 | timeout--; | |
200 | } | |
201 | ||
202 | if (!timeout) { | |
203 | eecd &= ~E1000_EECD_REQ; | |
204 | wr32(E1000_EECD, eecd); | |
652fff32 | 205 | hw_dbg("Could not acquire NVM grant\n"); |
9d5c8243 AK |
206 | ret_val = -E1000_ERR_NVM; |
207 | } | |
208 | ||
209 | return ret_val; | |
210 | } | |
211 | ||
212 | /** | |
733596be | 213 | * igb_standby_nvm - Return EEPROM to standby state |
9d5c8243 AK |
214 | * @hw: pointer to the HW structure |
215 | * | |
216 | * Return the EEPROM to a standby state. | |
217 | **/ | |
218 | static void igb_standby_nvm(struct e1000_hw *hw) | |
219 | { | |
220 | struct e1000_nvm_info *nvm = &hw->nvm; | |
221 | u32 eecd = rd32(E1000_EECD); | |
222 | ||
223 | if (nvm->type == e1000_nvm_eeprom_microwire) { | |
224 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
225 | wr32(E1000_EECD, eecd); | |
226 | wrfl(); | |
227 | udelay(nvm->delay_usec); | |
228 | ||
229 | igb_raise_eec_clk(hw, &eecd); | |
230 | ||
231 | /* Select EEPROM */ | |
232 | eecd |= E1000_EECD_CS; | |
233 | wr32(E1000_EECD, eecd); | |
234 | wrfl(); | |
235 | udelay(nvm->delay_usec); | |
236 | ||
237 | igb_lower_eec_clk(hw, &eecd); | |
238 | } else if (nvm->type == e1000_nvm_eeprom_spi) { | |
239 | /* Toggle CS to flush commands */ | |
240 | eecd |= E1000_EECD_CS; | |
241 | wr32(E1000_EECD, eecd); | |
242 | wrfl(); | |
243 | udelay(nvm->delay_usec); | |
244 | eecd &= ~E1000_EECD_CS; | |
245 | wr32(E1000_EECD, eecd); | |
246 | wrfl(); | |
247 | udelay(nvm->delay_usec); | |
248 | } | |
249 | } | |
250 | ||
251 | /** | |
252 | * e1000_stop_nvm - Terminate EEPROM command | |
253 | * @hw: pointer to the HW structure | |
254 | * | |
255 | * Terminates the current command by inverting the EEPROM's chip select pin. | |
256 | **/ | |
257 | static void e1000_stop_nvm(struct e1000_hw *hw) | |
258 | { | |
259 | u32 eecd; | |
260 | ||
261 | eecd = rd32(E1000_EECD); | |
262 | if (hw->nvm.type == e1000_nvm_eeprom_spi) { | |
263 | /* Pull CS high */ | |
264 | eecd |= E1000_EECD_CS; | |
265 | igb_lower_eec_clk(hw, &eecd); | |
266 | } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { | |
267 | /* CS on Microcwire is active-high */ | |
268 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
269 | wr32(E1000_EECD, eecd); | |
270 | igb_raise_eec_clk(hw, &eecd); | |
271 | igb_lower_eec_clk(hw, &eecd); | |
272 | } | |
273 | } | |
274 | ||
275 | /** | |
733596be | 276 | * igb_release_nvm - Release exclusive access to EEPROM |
9d5c8243 AK |
277 | * @hw: pointer to the HW structure |
278 | * | |
279 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
280 | **/ | |
281 | void igb_release_nvm(struct e1000_hw *hw) | |
282 | { | |
283 | u32 eecd; | |
284 | ||
285 | e1000_stop_nvm(hw); | |
286 | ||
287 | eecd = rd32(E1000_EECD); | |
288 | eecd &= ~E1000_EECD_REQ; | |
289 | wr32(E1000_EECD, eecd); | |
290 | } | |
291 | ||
292 | /** | |
733596be | 293 | * igb_ready_nvm_eeprom - Prepares EEPROM for read/write |
9d5c8243 AK |
294 | * @hw: pointer to the HW structure |
295 | * | |
296 | * Setups the EEPROM for reading and writing. | |
297 | **/ | |
298 | static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) | |
299 | { | |
300 | struct e1000_nvm_info *nvm = &hw->nvm; | |
301 | u32 eecd = rd32(E1000_EECD); | |
302 | s32 ret_val = 0; | |
303 | u16 timeout = 0; | |
304 | u8 spi_stat_reg; | |
305 | ||
306 | ||
307 | if (nvm->type == e1000_nvm_eeprom_microwire) { | |
308 | /* Clear SK and DI */ | |
309 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
310 | wr32(E1000_EECD, eecd); | |
311 | /* Set CS */ | |
312 | eecd |= E1000_EECD_CS; | |
313 | wr32(E1000_EECD, eecd); | |
314 | } else if (nvm->type == e1000_nvm_eeprom_spi) { | |
315 | /* Clear SK and CS */ | |
316 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
317 | wr32(E1000_EECD, eecd); | |
318 | udelay(1); | |
319 | timeout = NVM_MAX_RETRY_SPI; | |
320 | ||
321 | /* | |
322 | * Read "Status Register" repeatedly until the LSB is cleared. | |
323 | * The EEPROM will signal that the command has been completed | |
324 | * by clearing bit 0 of the internal status register. If it's | |
325 | * not cleared within 'timeout', then error out. | |
326 | */ | |
327 | while (timeout) { | |
328 | igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, | |
329 | hw->nvm.opcode_bits); | |
330 | spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); | |
331 | if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) | |
332 | break; | |
333 | ||
334 | udelay(5); | |
335 | igb_standby_nvm(hw); | |
336 | timeout--; | |
337 | } | |
338 | ||
339 | if (!timeout) { | |
652fff32 | 340 | hw_dbg("SPI NVM Status error\n"); |
9d5c8243 AK |
341 | ret_val = -E1000_ERR_NVM; |
342 | goto out; | |
343 | } | |
344 | } | |
345 | ||
346 | out: | |
347 | return ret_val; | |
348 | } | |
349 | ||
350 | /** | |
733596be | 351 | * igb_read_nvm_eerd - Reads EEPROM using EERD register |
9d5c8243 AK |
352 | * @hw: pointer to the HW structure |
353 | * @offset: offset of word in the EEPROM to read | |
354 | * @words: number of words to read | |
355 | * @data: word read from the EEPROM | |
356 | * | |
357 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
358 | **/ | |
359 | s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
360 | { | |
361 | struct e1000_nvm_info *nvm = &hw->nvm; | |
362 | u32 i, eerd = 0; | |
363 | s32 ret_val = 0; | |
364 | ||
365 | /* | |
366 | * A check for invalid values: offset too large, too many words, | |
367 | * and not enough words. | |
368 | */ | |
369 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
370 | (words == 0)) { | |
652fff32 | 371 | hw_dbg("nvm parameter(s) out of bounds\n"); |
9d5c8243 AK |
372 | ret_val = -E1000_ERR_NVM; |
373 | goto out; | |
374 | } | |
375 | ||
376 | for (i = 0; i < words; i++) { | |
377 | eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + | |
378 | E1000_NVM_RW_REG_START; | |
379 | ||
380 | wr32(E1000_EERD, eerd); | |
381 | ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); | |
382 | if (ret_val) | |
383 | break; | |
384 | ||
385 | data[i] = (rd32(E1000_EERD) >> | |
386 | E1000_NVM_RW_REG_DATA); | |
387 | } | |
388 | ||
389 | out: | |
390 | return ret_val; | |
391 | } | |
392 | ||
393 | /** | |
733596be | 394 | * igb_write_nvm_spi - Write to EEPROM using SPI |
9d5c8243 AK |
395 | * @hw: pointer to the HW structure |
396 | * @offset: offset within the EEPROM to be written to | |
397 | * @words: number of words to write | |
398 | * @data: 16 bit word(s) to be written to the EEPROM | |
399 | * | |
400 | * Writes data to EEPROM at offset using SPI interface. | |
401 | * | |
402 | * If e1000_update_nvm_checksum is not called after this function , the | |
403 | * EEPROM will most likley contain an invalid checksum. | |
404 | **/ | |
405 | s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
406 | { | |
407 | struct e1000_nvm_info *nvm = &hw->nvm; | |
408 | s32 ret_val; | |
409 | u16 widx = 0; | |
410 | ||
411 | /* | |
412 | * A check for invalid values: offset too large, too many words, | |
413 | * and not enough words. | |
414 | */ | |
415 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
416 | (words == 0)) { | |
652fff32 | 417 | hw_dbg("nvm parameter(s) out of bounds\n"); |
9d5c8243 AK |
418 | ret_val = -E1000_ERR_NVM; |
419 | goto out; | |
420 | } | |
421 | ||
422 | ret_val = hw->nvm.ops.acquire_nvm(hw); | |
423 | if (ret_val) | |
424 | goto out; | |
425 | ||
426 | msleep(10); | |
427 | ||
428 | while (widx < words) { | |
429 | u8 write_opcode = NVM_WRITE_OPCODE_SPI; | |
430 | ||
431 | ret_val = igb_ready_nvm_eeprom(hw); | |
432 | if (ret_val) | |
433 | goto release; | |
434 | ||
435 | igb_standby_nvm(hw); | |
436 | ||
437 | /* Send the WRITE ENABLE command (8 bit opcode) */ | |
438 | igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, | |
439 | nvm->opcode_bits); | |
440 | ||
441 | igb_standby_nvm(hw); | |
442 | ||
443 | /* | |
444 | * Some SPI eeproms use the 8th address bit embedded in the | |
445 | * opcode | |
446 | */ | |
447 | if ((nvm->address_bits == 8) && (offset >= 128)) | |
448 | write_opcode |= NVM_A8_OPCODE_SPI; | |
449 | ||
450 | /* Send the Write command (8-bit opcode + addr) */ | |
451 | igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); | |
452 | igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), | |
453 | nvm->address_bits); | |
454 | ||
455 | /* Loop to allow for up to whole page write of eeprom */ | |
456 | while (widx < words) { | |
457 | u16 word_out = data[widx]; | |
458 | word_out = (word_out >> 8) | (word_out << 8); | |
459 | igb_shift_out_eec_bits(hw, word_out, 16); | |
460 | widx++; | |
461 | ||
462 | if ((((offset + widx) * 2) % nvm->page_size) == 0) { | |
463 | igb_standby_nvm(hw); | |
464 | break; | |
465 | } | |
466 | } | |
467 | } | |
468 | ||
469 | msleep(10); | |
470 | release: | |
471 | hw->nvm.ops.release_nvm(hw); | |
472 | ||
473 | out: | |
474 | return ret_val; | |
475 | } | |
476 | ||
477 | /** | |
733596be | 478 | * igb_read_part_num - Read device part number |
9d5c8243 AK |
479 | * @hw: pointer to the HW structure |
480 | * @part_num: pointer to device part number | |
481 | * | |
482 | * Reads the product board assembly (PBA) number from the EEPROM and stores | |
483 | * the value in part_num. | |
484 | **/ | |
485 | s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num) | |
486 | { | |
487 | s32 ret_val; | |
488 | u16 nvm_data; | |
489 | ||
490 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); | |
491 | if (ret_val) { | |
652fff32 | 492 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
493 | goto out; |
494 | } | |
495 | *part_num = (u32)(nvm_data << 16); | |
496 | ||
497 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); | |
498 | if (ret_val) { | |
652fff32 | 499 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
500 | goto out; |
501 | } | |
502 | *part_num |= nvm_data; | |
503 | ||
504 | out: | |
505 | return ret_val; | |
506 | } | |
507 | ||
508 | /** | |
733596be | 509 | * igb_read_mac_addr - Read device MAC address |
9d5c8243 AK |
510 | * @hw: pointer to the HW structure |
511 | * | |
512 | * Reads the device MAC address from the EEPROM and stores the value. | |
513 | * Since devices with two ports use the same EEPROM, we increment the | |
514 | * last bit in the MAC address for the second port. | |
515 | **/ | |
516 | s32 igb_read_mac_addr(struct e1000_hw *hw) | |
517 | { | |
518 | s32 ret_val = 0; | |
519 | u16 offset, nvm_data, i; | |
520 | ||
521 | for (i = 0; i < ETH_ALEN; i += 2) { | |
522 | offset = i >> 1; | |
523 | ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); | |
524 | if (ret_val) { | |
652fff32 | 525 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
526 | goto out; |
527 | } | |
528 | hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); | |
529 | hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); | |
530 | } | |
531 | ||
532 | /* Flip last bit of mac address if we're on second port */ | |
533 | if (hw->bus.func == E1000_FUNC_1) | |
534 | hw->mac.perm_addr[5] ^= 1; | |
535 | ||
536 | for (i = 0; i < ETH_ALEN; i++) | |
537 | hw->mac.addr[i] = hw->mac.perm_addr[i]; | |
538 | ||
539 | out: | |
540 | return ret_val; | |
541 | } | |
542 | ||
543 | /** | |
733596be | 544 | * igb_validate_nvm_checksum - Validate EEPROM checksum |
9d5c8243 AK |
545 | * @hw: pointer to the HW structure |
546 | * | |
547 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
548 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
549 | **/ | |
550 | s32 igb_validate_nvm_checksum(struct e1000_hw *hw) | |
551 | { | |
552 | s32 ret_val = 0; | |
553 | u16 checksum = 0; | |
554 | u16 i, nvm_data; | |
555 | ||
556 | for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { | |
557 | ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); | |
558 | if (ret_val) { | |
652fff32 | 559 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
560 | goto out; |
561 | } | |
562 | checksum += nvm_data; | |
563 | } | |
564 | ||
565 | if (checksum != (u16) NVM_SUM) { | |
652fff32 | 566 | hw_dbg("NVM Checksum Invalid\n"); |
9d5c8243 AK |
567 | ret_val = -E1000_ERR_NVM; |
568 | goto out; | |
569 | } | |
570 | ||
571 | out: | |
572 | return ret_val; | |
573 | } | |
574 | ||
575 | /** | |
733596be | 576 | * igb_update_nvm_checksum - Update EEPROM checksum |
9d5c8243 AK |
577 | * @hw: pointer to the HW structure |
578 | * | |
579 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
580 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
581 | * value to the EEPROM. | |
582 | **/ | |
583 | s32 igb_update_nvm_checksum(struct e1000_hw *hw) | |
584 | { | |
585 | s32 ret_val; | |
586 | u16 checksum = 0; | |
587 | u16 i, nvm_data; | |
588 | ||
589 | for (i = 0; i < NVM_CHECKSUM_REG; i++) { | |
590 | ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); | |
591 | if (ret_val) { | |
652fff32 | 592 | hw_dbg("NVM Read Error while updating checksum.\n"); |
9d5c8243 AK |
593 | goto out; |
594 | } | |
595 | checksum += nvm_data; | |
596 | } | |
597 | checksum = (u16) NVM_SUM - checksum; | |
598 | ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); | |
599 | if (ret_val) | |
652fff32 | 600 | hw_dbg("NVM Write Error while updating checksum.\n"); |
9d5c8243 AK |
601 | |
602 | out: | |
603 | return ret_val; | |
604 | } | |
605 |