[deliverable/linux.git] / drivers / net / igb / e1000_nvm.c

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include <linux/if_ether.h>
#include <linux/delay.h>

#include "e1000_mac.h"
#include "e1000_nvm.h"

/**
 *  igb_raise_eec_clk - Raise EEPROM clock
 *  @hw: pointer to the HW structure
 *  @eecd: pointer to the EEPROM
 *
 *  Enable/Raise the EEPROM clock bit.
 **/
static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
{
	*eecd = *eecd | E1000_EECD_SK;
	wr32(E1000_EECD, *eecd);
	wrfl();
	udelay(hw->nvm.delay_usec);
}

/**
 *  igb_lower_eec_clk - Lower EEPROM clock
 *  @hw: pointer to the HW structure
 *  @eecd: pointer to the EEPROM
 *
 *  Clear/Lower the EEPROM clock bit.
 **/
static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
{
	*eecd = *eecd & ~E1000_EECD_SK;
	wr32(E1000_EECD, *eecd);
	wrfl();
	udelay(hw->nvm.delay_usec);
}

/**
 *  igb_shift_out_eec_bits - Shift data bits our to the EEPROM
 *  @hw: pointer to the HW structure
 *  @data: data to send to the EEPROM
 *  @count: number of bits to shift out
 *
 *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 *  In order to do this, "data" must be broken down into bits.
 **/
static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	u32 eecd = rd32(E1000_EECD);
	u32 mask;

	mask = 0x01 << (count - 1);
	if (nvm->type == e1000_nvm_eeprom_spi)
		eecd |= E1000_EECD_DO;

	do {
		eecd &= ~E1000_EECD_DI;

		if (data & mask)
			eecd |= E1000_EECD_DI;

		wr32(E1000_EECD, eecd);
		wrfl();

		udelay(nvm->delay_usec);

		igb_raise_eec_clk(hw, &eecd);
		igb_lower_eec_clk(hw, &eecd);

		mask >>= 1;
	} while (mask);

	eecd &= ~E1000_EECD_DI;
	wr32(E1000_EECD, eecd);
}

/**
 *  igb_shift_in_eec_bits - Shift data bits in from the EEPROM
 *  @hw: pointer to the HW structure
 *  @count: number of bits to shift in
 *
 *  In order to read a register from the EEPROM, we need to shift 'count' bits
 *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 *  the EEPROM (setting the SK bit), and then reading the value of the data out
 *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 *  always be clear.
 **/
static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
{
	u32 eecd;
	u32 i;
	u16 data;

	eecd = rd32(E1000_EECD);

	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
	data = 0;

	for (i = 0; i < count; i++) {
		data <<= 1;
		igb_raise_eec_clk(hw, &eecd);

		eecd = rd32(E1000_EECD);

		eecd &= ~E1000_EECD_DI;
		if (eecd & E1000_EECD_DO)
			data |= 1;

		igb_lower_eec_clk(hw, &eecd);
	}

	return data;
}

/**
 *  igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 *  @hw: pointer to the HW structure
 *  @ee_reg: EEPROM flag for polling
 *
 *  Polls the EEPROM status bit for either read or write completion based
 *  upon the value of 'ee_reg'.
 **/
static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
{
	u32 attempts = 100000;
	u32 i, reg = 0;
	s32 ret_val = -E1000_ERR_NVM;

	for (i = 0; i < attempts; i++) {
		if (ee_reg == E1000_NVM_POLL_READ)
			reg = rd32(E1000_EERD);
		else
			reg = rd32(E1000_EEWR);

		if (reg & E1000_NVM_RW_REG_DONE) {
			ret_val = 0;
			break;
		}

		udelay(5);
	}

	return ret_val;
}

/**
 *  igb_acquire_nvm - Generic request for access to EEPROM
 *  @hw: pointer to the HW structure
 *
 *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 *  Return successful if access grant bit set, else clear the request for
 *  EEPROM access and return -E1000_ERR_NVM (-1).
 **/
s32 igb_acquire_nvm(struct e1000_hw *hw)
{
	u32 eecd = rd32(E1000_EECD);
	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
	s32 ret_val = 0;


	wr32(E1000_EECD, eecd | E1000_EECD_REQ);
	eecd = rd32(E1000_EECD);

	while (timeout) {
		if (eecd & E1000_EECD_GNT)
			break;
		udelay(5);
		eecd = rd32(E1000_EECD);
		timeout--;
	}

	if (!timeout) {
		eecd &= ~E1000_EECD_REQ;
		wr32(E1000_EECD, eecd);
		hw_dbg("Could not acquire NVM grant\n");
		ret_val = -E1000_ERR_NVM;
	}

	return ret_val;
}

/**
 *  igb_standby_nvm - Return EEPROM to standby state
 *  @hw: pointer to the HW structure
 *
 *  Return the EEPROM to a standby state.
 **/
static void igb_standby_nvm(struct e1000_hw *hw)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	u32 eecd = rd32(E1000_EECD);

	if (nvm->type == e1000_nvm_eeprom_spi) {
		/* Toggle CS to flush commands */
		eecd |= E1000_EECD_CS;
		wr32(E1000_EECD, eecd);
		wrfl();
		udelay(nvm->delay_usec);
		eecd &= ~E1000_EECD_CS;
		wr32(E1000_EECD, eecd);
		wrfl();
		udelay(nvm->delay_usec);
	}
}

/**
 *  e1000_stop_nvm - Terminate EEPROM command
 *  @hw: pointer to the HW structure
 *
 *  Terminates the current command by inverting the EEPROM's chip select pin.
 **/
static void e1000_stop_nvm(struct e1000_hw *hw)
{
	u32 eecd;

	eecd = rd32(E1000_EECD);
	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
		/* Pull CS high */
		eecd |= E1000_EECD_CS;
		igb_lower_eec_clk(hw, &eecd);
	}
}

/**
 *  igb_release_nvm - Release exclusive access to EEPROM
 *  @hw: pointer to the HW structure
 *
 *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 **/
void igb_release_nvm(struct e1000_hw *hw)
{
	u32 eecd;

	e1000_stop_nvm(hw);

	eecd = rd32(E1000_EECD);
	eecd &= ~E1000_EECD_REQ;
	wr32(E1000_EECD, eecd);
}

/**
 *  igb_ready_nvm_eeprom - Prepares EEPROM for read/write
 *  @hw: pointer to the HW structure
 *
 *  Setups the EEPROM for reading and writing.
 **/
static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	u32 eecd = rd32(E1000_EECD);
	s32 ret_val = 0;
	u16 timeout = 0;
	u8 spi_stat_reg;


	if (nvm->type == e1000_nvm_eeprom_spi) {
		/* Clear SK and CS */
		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
		wr32(E1000_EECD, eecd);
		udelay(1);
		timeout = NVM_MAX_RETRY_SPI;

		/*
		 * Read "Status Register" repeatedly until the LSB is cleared.
		 * The EEPROM will signal that the command has been completed
		 * by clearing bit 0 of the internal status register.  If it's
		 * not cleared within 'timeout', then error out.
		 */
		while (timeout) {
			igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
						 hw->nvm.opcode_bits);
			spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
				break;

			udelay(5);
			igb_standby_nvm(hw);
			timeout--;
		}

		if (!timeout) {
			hw_dbg("SPI NVM Status error\n");
			ret_val = -E1000_ERR_NVM;
			goto out;
		}
	}

out:
	return ret_val;
}

/**
 *  igb_read_nvm_eerd - Reads EEPROM using EERD register
 *  @hw: pointer to the HW structure
 *  @offset: offset of word in the EEPROM to read
 *  @words: number of words to read
 *  @data: word read from the EEPROM
 *
 *  Reads a 16 bit word from the EEPROM using the EERD register.
 **/
s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	u32 i, eerd = 0;
	s32 ret_val = 0;

	/*
	 * A check for invalid values:  offset too large, too many words,
	 * and not enough words.
	 */
	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
	    (words == 0)) {
		hw_dbg("nvm parameter(s) out of bounds\n");
		ret_val = -E1000_ERR_NVM;
		goto out;
	}

	for (i = 0; i < words; i++) {
		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
		       E1000_NVM_RW_REG_START;

		wr32(E1000_EERD, eerd);
		ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
		if (ret_val)
			break;

		data[i] = (rd32(E1000_EERD) >>
			   E1000_NVM_RW_REG_DATA);
	}

out:
	return ret_val;
}

/**
 *  igb_write_nvm_spi - Write to EEPROM using SPI
 *  @hw: pointer to the HW structure
 *  @offset: offset within the EEPROM to be written to
 *  @words: number of words to write
 *  @data: 16 bit word(s) to be written to the EEPROM
 *
 *  Writes data to EEPROM at offset using SPI interface.
 *
 *  If e1000_update_nvm_checksum is not called after this function , the
 *  EEPROM will most likley contain an invalid checksum.
 **/
s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	s32 ret_val;
	u16 widx = 0;

	/*
	 * A check for invalid values:  offset too large, too many words,
	 * and not enough words.
	 */
	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
	    (words == 0)) {
		hw_dbg("nvm parameter(s) out of bounds\n");
		ret_val = -E1000_ERR_NVM;
		goto out;
	}

	ret_val = hw->nvm.ops.acquire(hw);
	if (ret_val)
		goto out;

	msleep(10);

	while (widx < words) {
		u8 write_opcode = NVM_WRITE_OPCODE_SPI;

		ret_val = igb_ready_nvm_eeprom(hw);
		if (ret_val)
			goto release;

		igb_standby_nvm(hw);

		/* Send the WRITE ENABLE command (8 bit opcode) */
		igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
					 nvm->opcode_bits);

		igb_standby_nvm(hw);

		/*
		 * Some SPI eeproms use the 8th address bit embedded in the
		 * opcode
		 */
		if ((nvm->address_bits == 8) && (offset >= 128))
			write_opcode |= NVM_A8_OPCODE_SPI;

		/* Send the Write command (8-bit opcode + addr) */
		igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
		igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
					 nvm->address_bits);

		/* Loop to allow for up to whole page write of eeprom */
		while (widx < words) {
			u16 word_out = data[widx];
			word_out = (word_out >> 8) | (word_out << 8);
			igb_shift_out_eec_bits(hw, word_out, 16);
			widx++;

			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
				igb_standby_nvm(hw);
				break;
			}
		}
	}

	msleep(10);
release:
	hw->nvm.ops.release(hw);

out:
	return ret_val;
}

/**
 *  igb_read_part_string - Read device part number
 *  @hw: pointer to the HW structure
 *  @part_num: pointer to device part number
 *  @part_num_size: size of part number buffer
 *
 *  Reads the product board assembly (PBA) number from the EEPROM and stores
 *  the value in part_num.
 **/
s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
{
	s32 ret_val;
	u16 nvm_data;
	u16 pointer;
	u16 offset;
	u16 length;

	if (part_num == NULL) {
		hw_dbg("PBA string buffer was null\n");
		ret_val = E1000_ERR_INVALID_ARGUMENT;
		goto out;
	}

	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
	if (ret_val) {
		hw_dbg("NVM Read Error\n");
		goto out;
	}

	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
	if (ret_val) {
		hw_dbg("NVM Read Error\n");
		goto out;
	}

	/*
	 * if nvm_data is not ptr guard the PBA must be in legacy format which
	 * means pointer is actually our second data word for the PBA number
	 * and we can decode it into an ascii string
	 */
	if (nvm_data != NVM_PBA_PTR_GUARD) {
		hw_dbg("NVM PBA number is not stored as string\n");

		/* we will need 11 characters to store the PBA */
		if (part_num_size < 11) {
			hw_dbg("PBA string buffer too small\n");
			return E1000_ERR_NO_SPACE;
		}

		/* extract hex string from data and pointer */
		part_num[0] = (nvm_data >> 12) & 0xF;
		part_num[1] = (nvm_data >> 8) & 0xF;
		part_num[2] = (nvm_data >> 4) & 0xF;
		part_num[3] = nvm_data & 0xF;
		part_num[4] = (pointer >> 12) & 0xF;
		part_num[5] = (pointer >> 8) & 0xF;
		part_num[6] = '-';
		part_num[7] = 0;
		part_num[8] = (pointer >> 4) & 0xF;
		part_num[9] = pointer & 0xF;

		/* put a null character on the end of our string */
		part_num[10] = '\0';

		/* switch all the data but the '-' to hex char */
		for (offset = 0; offset < 10; offset++) {
			if (part_num[offset] < 0xA)
				part_num[offset] += '0';
			else if (part_num[offset] < 0x10)
				part_num[offset] += 'A' - 0xA;
		}

		goto out;
	}

	ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
	if (ret_val) {
		hw_dbg("NVM Read Error\n");
		goto out;
	}

	if (length == 0xFFFF || length == 0) {
		hw_dbg("NVM PBA number section invalid length\n");
		ret_val = E1000_ERR_NVM_PBA_SECTION;
		goto out;
	}
	/* check if part_num buffer is big enough */
	if (part_num_size < (((u32)length * 2) - 1)) {
		hw_dbg("PBA string buffer too small\n");
		ret_val = E1000_ERR_NO_SPACE;
		goto out;
	}

	/* trim pba length from start of string */
	pointer++;
	length--;

	for (offset = 0; offset < length; offset++) {
		ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
		if (ret_val) {
			hw_dbg("NVM Read Error\n");
			goto out;
		}
		part_num[offset * 2] = (u8)(nvm_data >> 8);
		part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
	}
	part_num[offset * 2] = '\0';

out:
	return ret_val;
}

/**
 *  igb_read_mac_addr - Read device MAC address
 *  @hw: pointer to the HW structure
 *
 *  Reads the device MAC address from the EEPROM and stores the value.
 *  Since devices with two ports use the same EEPROM, we increment the
 *  last bit in the MAC address for the second port.
 **/
s32 igb_read_mac_addr(struct e1000_hw *hw)
{
	u32 rar_high;
	u32 rar_low;
	u16 i;

	rar_high = rd32(E1000_RAH(0));
	rar_low = rd32(E1000_RAL(0));

	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));

	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));

	for (i = 0; i < ETH_ALEN; i++)
		hw->mac.addr[i] = hw->mac.perm_addr[i];

	return 0;
}

/**
 *  igb_validate_nvm_checksum - Validate EEPROM checksum
 *  @hw: pointer to the HW structure
 *
 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 **/
s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
{
	s32 ret_val = 0;
	u16 checksum = 0;
	u16 i, nvm_data;

	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
		if (ret_val) {
			hw_dbg("NVM Read Error\n");
			goto out;
		}
		checksum += nvm_data;
	}

	if (checksum != (u16) NVM_SUM) {
		hw_dbg("NVM Checksum Invalid\n");
		ret_val = -E1000_ERR_NVM;
		goto out;
	}

out:
	return ret_val;
}

/**
 *  igb_update_nvm_checksum - Update EEPROM checksum
 *  @hw: pointer to the HW structure
 *
 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 *  value to the EEPROM.
 **/
s32 igb_update_nvm_checksum(struct e1000_hw *hw)
{
	s32  ret_val;
	u16 checksum = 0;
	u16 i, nvm_data;

	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
		if (ret_val) {
			hw_dbg("NVM Read Error while updating checksum.\n");
			goto out;
		}
		checksum += nvm_data;
	}
	checksum = (u16) NVM_SUM - checksum;
	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
	if (ret_val)
		hw_dbg("NVM Write Error while updating checksum.\n");

out:
	return ret_val;
}
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#include <linux/if_ether.h>
	29	#include <linux/delay.h>
	30
	31	#include "e1000_mac.h"
	32	#include "e1000_nvm.h"
	33
	34	/**
733596be	35	* igb_raise_eec_clk - Raise EEPROM clock
9d5c8243 AK	36	* @hw: pointer to the HW structure
	37	* @eecd: pointer to the EEPROM
	38	*
	39	* Enable/Raise the EEPROM clock bit.
	40	**/
	41	static void igb_raise_eec_clk(struct e1000_hw hw, u32 eecd)
	42	{
	43	eecd = eecd \| E1000_EECD_SK;
	44	wr32(E1000_EECD, *eecd);
	45	wrfl();
	46	udelay(hw->nvm.delay_usec);
	47	}
	48
	49	/**
733596be	50	* igb_lower_eec_clk - Lower EEPROM clock
9d5c8243 AK	51	* @hw: pointer to the HW structure
	52	* @eecd: pointer to the EEPROM
	53	*
	54	* Clear/Lower the EEPROM clock bit.
	55	**/
	56	static void igb_lower_eec_clk(struct e1000_hw hw, u32 eecd)
	57	{
	58	eecd = eecd & ~E1000_EECD_SK;
	59	wr32(E1000_EECD, *eecd);
	60	wrfl();
	61	udelay(hw->nvm.delay_usec);
	62	}
	63
	64	/**
733596be	65	* igb_shift_out_eec_bits - Shift data bits our to the EEPROM
9d5c8243 AK	66	* @hw: pointer to the HW structure
	67	* @data: data to send to the EEPROM
	68	* @count: number of bits to shift out
	69	*
	70	* We need to shift 'count' bits out to the EEPROM. So, the value in the
	71	* "data" parameter will be shifted out to the EEPROM one bit at a time.
	72	* In order to do this, "data" must be broken down into bits.
	73	**/
	74	static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
	75	{
	76	struct e1000_nvm_info *nvm = &hw->nvm;
	77	u32 eecd = rd32(E1000_EECD);
	78	u32 mask;
	79
	80	mask = 0x01 << (count - 1);
285b4167	81	if (nvm->type == e1000_nvm_eeprom_spi)
9d5c8243 AK	82	eecd \|= E1000_EECD_DO;
	83
	84	do {
	85	eecd &= ~E1000_EECD_DI;
	86
	87	if (data & mask)
	88	eecd \|= E1000_EECD_DI;
	89
	90	wr32(E1000_EECD, eecd);
	91	wrfl();
	92
	93	udelay(nvm->delay_usec);
	94
	95	igb_raise_eec_clk(hw, &eecd);
	96	igb_lower_eec_clk(hw, &eecd);
	97
	98	mask >>= 1;
	99	} while (mask);
	100
	101	eecd &= ~E1000_EECD_DI;
	102	wr32(E1000_EECD, eecd);
	103	}
	104
	105	/**
733596be	106	* igb_shift_in_eec_bits - Shift data bits in from the EEPROM
9d5c8243 AK	107	* @hw: pointer to the HW structure
	108	* @count: number of bits to shift in
	109	*
	110	* In order to read a register from the EEPROM, we need to shift 'count' bits
	111	* in from the EEPROM. Bits are "shifted in" by raising the clock input to
	112	* the EEPROM (setting the SK bit), and then reading the value of the data out
	113	* "DO" bit. During this "shifting in" process the data in "DI" bit should
	114	* always be clear.
	115	**/
	116	static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
	117	{
	118	u32 eecd;
	119	u32 i;
	120	u16 data;
	121
	122	eecd = rd32(E1000_EECD);
	123
	124	eecd &= ~(E1000_EECD_DO \| E1000_EECD_DI);
	125	data = 0;
	126
	127	for (i = 0; i < count; i++) {
	128	data <<= 1;
	129	igb_raise_eec_clk(hw, &eecd);
	130
	131	eecd = rd32(E1000_EECD);
	132
	133	eecd &= ~E1000_EECD_DI;
	134	if (eecd & E1000_EECD_DO)
	135	data \|= 1;
	136
	137	igb_lower_eec_clk(hw, &eecd);
	138	}
	139
	140	return data;
	141	}
	142
	143	/**
733596be	144	* igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
9d5c8243 AK	145	* @hw: pointer to the HW structure
	146	* @ee_reg: EEPROM flag for polling
	147	*
	148	* Polls the EEPROM status bit for either read or write completion based
	149	* upon the value of 'ee_reg'.
	150	**/
	151	static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
	152	{
	153	u32 attempts = 100000;
	154	u32 i, reg = 0;
	155	s32 ret_val = -E1000_ERR_NVM;
	156
	157	for (i = 0; i < attempts; i++) {
	158	if (ee_reg == E1000_NVM_POLL_READ)
	159	reg = rd32(E1000_EERD);
	160	else
	161	reg = rd32(E1000_EEWR);
	162
	163	if (reg & E1000_NVM_RW_REG_DONE) {
	164	ret_val = 0;
	165	break;
	166	}
	167
	168	udelay(5);
	169	}
	170
	171	return ret_val;
	172	}
	173
	174	/**
733596be	175	* igb_acquire_nvm - Generic request for access to EEPROM
9d5c8243 AK	176	* @hw: pointer to the HW structure
	177	*
	178	* Set the EEPROM access request bit and wait for EEPROM access grant bit.
	179	* Return successful if access grant bit set, else clear the request for
	180	* EEPROM access and return -E1000_ERR_NVM (-1).
	181	**/
	182	s32 igb_acquire_nvm(struct e1000_hw *hw)
	183	{
	184	u32 eecd = rd32(E1000_EECD);
	185	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
	186	s32 ret_val = 0;
	187
	188
	189	wr32(E1000_EECD, eecd \| E1000_EECD_REQ);
	190	eecd = rd32(E1000_EECD);
	191
	192	while (timeout) {
	193	if (eecd & E1000_EECD_GNT)
	194	break;
	195	udelay(5);
	196	eecd = rd32(E1000_EECD);
	197	timeout--;
	198	}
	199
	200	if (!timeout) {
	201	eecd &= ~E1000_EECD_REQ;
	202	wr32(E1000_EECD, eecd);
652fff32	203	hw_dbg("Could not acquire NVM grant\n");
9d5c8243 AK	204	ret_val = -E1000_ERR_NVM;
	205	}
	206
	207	return ret_val;
	208	}
	209
	210	/**
733596be	211	* igb_standby_nvm - Return EEPROM to standby state
9d5c8243 AK	212	* @hw: pointer to the HW structure
	213	*
	214	* Return the EEPROM to a standby state.
	215	**/
	216	static void igb_standby_nvm(struct e1000_hw *hw)
	217	{
	218	struct e1000_nvm_info *nvm = &hw->nvm;
	219	u32 eecd = rd32(E1000_EECD);
	220
285b4167	221	if (nvm->type == e1000_nvm_eeprom_spi) {
9d5c8243 AK	222	/* Toggle CS to flush commands */
	223	eecd \|= E1000_EECD_CS;
	224	wr32(E1000_EECD, eecd);
	225	wrfl();
	226	udelay(nvm->delay_usec);
	227	eecd &= ~E1000_EECD_CS;
	228	wr32(E1000_EECD, eecd);
	229	wrfl();
	230	udelay(nvm->delay_usec);
	231	}
	232	}
	233
	234	/**
	235	* e1000_stop_nvm - Terminate EEPROM command
	236	* @hw: pointer to the HW structure
	237	*
	238	* Terminates the current command by inverting the EEPROM's chip select pin.
	239	**/
	240	static void e1000_stop_nvm(struct e1000_hw *hw)
	241	{
	242	u32 eecd;
	243
	244	eecd = rd32(E1000_EECD);
	245	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
	246	/* Pull CS high */
	247	eecd \|= E1000_EECD_CS;
	248	igb_lower_eec_clk(hw, &eecd);
9d5c8243 AK	249	}
	250	}
	251
	252	/**
733596be	253	* igb_release_nvm - Release exclusive access to EEPROM
9d5c8243 AK	254	* @hw: pointer to the HW structure
	255	*
	256	* Stop any current commands to the EEPROM and clear the EEPROM request bit.
	257	**/
	258	void igb_release_nvm(struct e1000_hw *hw)
	259	{
	260	u32 eecd;
	261
	262	e1000_stop_nvm(hw);
	263
	264	eecd = rd32(E1000_EECD);
	265	eecd &= ~E1000_EECD_REQ;
	266	wr32(E1000_EECD, eecd);
	267	}
	268
	269	/**
733596be	270	* igb_ready_nvm_eeprom - Prepares EEPROM for read/write
9d5c8243 AK	271	* @hw: pointer to the HW structure
	272	*
	273	* Setups the EEPROM for reading and writing.
	274	**/
	275	static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
	276	{
	277	struct e1000_nvm_info *nvm = &hw->nvm;
	278	u32 eecd = rd32(E1000_EECD);
	279	s32 ret_val = 0;
	280	u16 timeout = 0;
	281	u8 spi_stat_reg;
	282
	283
285b4167	284	if (nvm->type == e1000_nvm_eeprom_spi) {
9d5c8243 AK	285	/* Clear SK and CS */
	286	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
	287	wr32(E1000_EECD, eecd);
	288	udelay(1);
	289	timeout = NVM_MAX_RETRY_SPI;
	290
	291	/*
	292	* Read "Status Register" repeatedly until the LSB is cleared.
	293	* The EEPROM will signal that the command has been completed
	294	* by clearing bit 0 of the internal status register. If it's
	295	* not cleared within 'timeout', then error out.
	296	*/
	297	while (timeout) {
	298	igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
	299	hw->nvm.opcode_bits);
	300	spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
	301	if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
	302	break;
	303
	304	udelay(5);
	305	igb_standby_nvm(hw);
	306	timeout--;
	307	}
	308
	309	if (!timeout) {
652fff32	310	hw_dbg("SPI NVM Status error\n");
9d5c8243 AK	311	ret_val = -E1000_ERR_NVM;
	312	goto out;
	313	}
	314	}
	315
	316	out:
	317	return ret_val;
	318	}
	319
	320	/**
733596be	321	* igb_read_nvm_eerd - Reads EEPROM using EERD register
9d5c8243 AK	322	* @hw: pointer to the HW structure
	323	* @offset: offset of word in the EEPROM to read
	324	* @words: number of words to read
	325	* @data: word read from the EEPROM
	326	*
	327	* Reads a 16 bit word from the EEPROM using the EERD register.
	328	**/
	329	s32 igb_read_nvm_eerd(struct e1000_hw hw, u16 offset, u16 words, u16 data)
	330	{
	331	struct e1000_nvm_info *nvm = &hw->nvm;
	332	u32 i, eerd = 0;
	333	s32 ret_val = 0;
	334
	335	/*
	336	* A check for invalid values: offset too large, too many words,
	337	* and not enough words.
	338	*/
	339	if ((offset >= nvm->word_size) \|\| (words > (nvm->word_size - offset)) \|\|
	340	(words == 0)) {
652fff32	341	hw_dbg("nvm parameter(s) out of bounds\n");
9d5c8243 AK	342	ret_val = -E1000_ERR_NVM;
	343	goto out;
	344	}
	345
	346	for (i = 0; i < words; i++) {
	347	eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
	348	E1000_NVM_RW_REG_START;
	349
	350	wr32(E1000_EERD, eerd);
	351	ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
	352	if (ret_val)
	353	break;
	354
	355	data[i] = (rd32(E1000_EERD) >>
	356	E1000_NVM_RW_REG_DATA);
	357	}
	358
	359	out:
	360	return ret_val;
	361	}
	362
	363	/**
733596be	364	* igb_write_nvm_spi - Write to EEPROM using SPI
9d5c8243 AK	365	* @hw: pointer to the HW structure
	366	* @offset: offset within the EEPROM to be written to
	367	* @words: number of words to write
	368	* @data: 16 bit word(s) to be written to the EEPROM
	369	*
	370	* Writes data to EEPROM at offset using SPI interface.
	371	*
	372	* If e1000_update_nvm_checksum is not called after this function , the
	373	* EEPROM will most likley contain an invalid checksum.
	374	**/
	375	s32 igb_write_nvm_spi(struct e1000_hw hw, u16 offset, u16 words, u16 data)
	376	{
	377	struct e1000_nvm_info *nvm = &hw->nvm;
	378	s32 ret_val;
	379	u16 widx = 0;
	380
	381	/*
	382	* A check for invalid values: offset too large, too many words,
	383	* and not enough words.
	384	*/
	385	if ((offset >= nvm->word_size) \|\| (words > (nvm->word_size - offset)) \|\|
	386	(words == 0)) {
652fff32	387	hw_dbg("nvm parameter(s) out of bounds\n");
9d5c8243 AK	388	ret_val = -E1000_ERR_NVM;
	389	goto out;
	390	}
	391
312c75ae	392	ret_val = hw->nvm.ops.acquire(hw);
9d5c8243 AK	393	if (ret_val)
	394	goto out;
	395
	396	msleep(10);
	397
	398	while (widx < words) {
	399	u8 write_opcode = NVM_WRITE_OPCODE_SPI;
	400
	401	ret_val = igb_ready_nvm_eeprom(hw);
	402	if (ret_val)
	403	goto release;
	404
	405	igb_standby_nvm(hw);
	406
	407	/* Send the WRITE ENABLE command (8 bit opcode) */
	408	igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
	409	nvm->opcode_bits);
	410
	411	igb_standby_nvm(hw);
	412
	413	/*
	414	* Some SPI eeproms use the 8th address bit embedded in the
	415	* opcode
	416	*/
	417	if ((nvm->address_bits == 8) && (offset >= 128))
	418	write_opcode \|= NVM_A8_OPCODE_SPI;
	419
	420	/* Send the Write command (8-bit opcode + addr) */
	421	igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
	422	igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
	423	nvm->address_bits);
	424
	425	/* Loop to allow for up to whole page write of eeprom */
	426	while (widx < words) {
	427	u16 word_out = data[widx];
	428	word_out = (word_out >> 8) \| (word_out << 8);
	429	igb_shift_out_eec_bits(hw, word_out, 16);
	430	widx++;
	431
	432	if ((((offset + widx) * 2) % nvm->page_size) == 0) {
	433	igb_standby_nvm(hw);
	434	break;
	435	}
	436	}
	437	}
	438
	439	msleep(10);
	440	release:
312c75ae	441	hw->nvm.ops.release(hw);
9d5c8243 AK	442
	443	out:
	444	return ret_val;
	445	}
	446
	447	/**
9835fd73	448	* igb_read_part_string - Read device part number
9d5c8243 AK	449	* @hw: pointer to the HW structure
9d5c8243 AK	450	* @part_num: pointer to device part number
9835fd73	451	* @part_num_size: size of part number buffer
9d5c8243 AK	452	*
	453	* Reads the product board assembly (PBA) number from the EEPROM and stores
	454	* the value in part_num.
	455	**/
9835fd73	456	s32 igb_read_part_string(struct e1000_hw hw, u8 part_num, u32 part_num_size)
9d5c8243	457	{
9835fd73	458	s32 ret_val;
9d5c8243	459	u16 nvm_data;
9835fd73 CW	460	u16 pointer;
	461	u16 offset;
	462	u16 length;
	463
	464	if (part_num == NULL) {
	465	hw_dbg("PBA string buffer was null\n");
	466	ret_val = E1000_ERR_INVALID_ARGUMENT;
	467	goto out;
	468	}
9d5c8243	469
312c75ae	470	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
9d5c8243	471	if (ret_val) {
652fff32	472	hw_dbg("NVM Read Error\n");
9d5c8243 AK	473	goto out;
9d5c8243 AK	474	}
9d5c8243	475
9835fd73	476	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
9d5c8243	477	if (ret_val) {
652fff32	478	hw_dbg("NVM Read Error\n");
9d5c8243 AK	479	goto out;
9d5c8243 AK	480	}
9835fd73 CW	481
	482	/*
	483	* if nvm_data is not ptr guard the PBA must be in legacy format which
	484	* means pointer is actually our second data word for the PBA number
	485	* and we can decode it into an ascii string
	486	*/
	487	if (nvm_data != NVM_PBA_PTR_GUARD) {
	488	hw_dbg("NVM PBA number is not stored as string\n");
	489
	490	/* we will need 11 characters to store the PBA */
	491	if (part_num_size < 11) {
	492	hw_dbg("PBA string buffer too small\n");
	493	return E1000_ERR_NO_SPACE;
	494	}
	495
	496	/* extract hex string from data and pointer */
	497	part_num[0] = (nvm_data >> 12) & 0xF;
	498	part_num[1] = (nvm_data >> 8) & 0xF;
	499	part_num[2] = (nvm_data >> 4) & 0xF;
	500	part_num[3] = nvm_data & 0xF;
	501	part_num[4] = (pointer >> 12) & 0xF;
	502	part_num[5] = (pointer >> 8) & 0xF;
	503	part_num[6] = '-';
	504	part_num[7] = 0;
	505	part_num[8] = (pointer >> 4) & 0xF;
	506	part_num[9] = pointer & 0xF;
	507
	508	/* put a null character on the end of our string */
	509	part_num[10] = '\0';
	510
	511	/* switch all the data but the '-' to hex char */
	512	for (offset = 0; offset < 10; offset++) {
	513	if (part_num[offset] < 0xA)
	514	part_num[offset] += '0';
	515	else if (part_num[offset] < 0x10)
	516	part_num[offset] += 'A' - 0xA;
	517	}
	518
	519	goto out;
	520	}
	521
	522	ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
	523	if (ret_val) {
	524	hw_dbg("NVM Read Error\n");
	525	goto out;
	526	}
	527
	528	if (length == 0xFFFF \|\| length == 0) {
	529	hw_dbg("NVM PBA number section invalid length\n");
	530	ret_val = E1000_ERR_NVM_PBA_SECTION;
	531	goto out;
	532	}
	533	/* check if part_num buffer is big enough */
	534	if (part_num_size < (((u32)length * 2) - 1)) {
	535	hw_dbg("PBA string buffer too small\n");
	536	ret_val = E1000_ERR_NO_SPACE;
	537	goto out;
	538	}
	539
	540	/* trim pba length from start of string */
	541	pointer++;
	542	length--;
	543
	544	for (offset = 0; offset < length; offset++) {
545	ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
546	if (ret_val) {
547	hw_dbg("NVM Read Error\n");
548	goto out;
549	}
550	part_num[offset * 2] = (u8)(nvm_data >> 8);
551	part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
552	}
553	part_num[offset * 2] = '\0';
9d5c8243 AK	554
	555	out:
	556	return ret_val;
	557	}
	558
	559	/**
733596be	560	* igb_read_mac_addr - Read device MAC address
9d5c8243 AK	561	* @hw: pointer to the HW structure
	562	*
	563	* Reads the device MAC address from the EEPROM and stores the value.
	564	* Since devices with two ports use the same EEPROM, we increment the
	565	* last bit in the MAC address for the second port.
	566	**/
	567	s32 igb_read_mac_addr(struct e1000_hw *hw)
	568	{
40a70b38 AD	569	u32 rar_high;
	570	u32 rar_low;
	571	u16 i;
9d5c8243	572
40a70b38 AD	573	rar_high = rd32(E1000_RAH(0));
40a70b38 AD	574	rar_low = rd32(E1000_RAL(0));
9d5c8243	575
40a70b38 AD	576	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
	577	hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
	578
	579	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
	580	hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
9d5c8243 AK	581
	582	for (i = 0; i < ETH_ALEN; i++)
	583	hw->mac.addr[i] = hw->mac.perm_addr[i];
	584
40a70b38	585	return 0;
9d5c8243 AK	586	}
	587
	588	/**
733596be	589	* igb_validate_nvm_checksum - Validate EEPROM checksum
9d5c8243 AK	590	* @hw: pointer to the HW structure
	591	*
	592	* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
	593	* and then verifies that the sum of the EEPROM is equal to 0xBABA.
	594	**/
	595	s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
	596	{
	597	s32 ret_val = 0;
	598	u16 checksum = 0;
	599	u16 i, nvm_data;
	600
	601	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
312c75ae	602	ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
9d5c8243	603	if (ret_val) {
652fff32	604	hw_dbg("NVM Read Error\n");
9d5c8243 AK	605	goto out;
	606	}
	607	checksum += nvm_data;
	608	}
	609
	610	if (checksum != (u16) NVM_SUM) {
652fff32	611	hw_dbg("NVM Checksum Invalid\n");
9d5c8243 AK	612	ret_val = -E1000_ERR_NVM;
	613	goto out;
	614	}
	615
	616	out:
	617	return ret_val;
	618	}
	619
	620	/**
733596be	621	* igb_update_nvm_checksum - Update EEPROM checksum
9d5c8243 AK	622	* @hw: pointer to the HW structure
	623	*
	624	* Updates the EEPROM checksum by reading/adding each word of the EEPROM
	625	* up to the checksum. Then calculates the EEPROM checksum and writes the
	626	* value to the EEPROM.
	627	**/
	628	s32 igb_update_nvm_checksum(struct e1000_hw *hw)
	629	{
	630	s32 ret_val;
	631	u16 checksum = 0;
	632	u16 i, nvm_data;
	633
	634	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
312c75ae	635	ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
9d5c8243	636	if (ret_val) {
652fff32	637	hw_dbg("NVM Read Error while updating checksum.\n");
9d5c8243 AK	638	goto out;
	639	}
	640	checksum += nvm_data;
	641	}
	642	checksum = (u16) NVM_SUM - checksum;
312c75ae	643	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
9d5c8243	644	if (ret_val)
652fff32	645	hw_dbg("NVM Write Error while updating checksum.\n");
9d5c8243 AK	646
	647	out:
	648	return ret_val;
	649	}
	650