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Merge commit 'v2.6.27-rc6' into timers/hpet
[deliverable/linux.git] / drivers / net / igb / e1000_phy.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/if_ether.h>
29#include <linux/delay.h>
30
31#include "e1000_mac.h"
32#include "e1000_phy.h"
33
34static s32 igb_get_phy_cfg_done(struct e1000_hw *hw);
35static void igb_release_phy(struct e1000_hw *hw);
36static s32 igb_acquire_phy(struct e1000_hw *hw);
37static s32 igb_phy_reset_dsp(struct e1000_hw *hw);
38static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
39static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
40 u16 *phy_ctrl);
41static s32 igb_wait_autoneg(struct e1000_hw *hw);
42
43/* Cable length tables */
44static const u16 e1000_m88_cable_length_table[] =
45 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
49
50static const u16 e1000_igp_2_cable_length_table[] =
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
52 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
53 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
54 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
55 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
56 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
57 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
58 104, 109, 114, 118, 121, 124};
59#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 (sizeof(e1000_igp_2_cable_length_table) / \
61 sizeof(e1000_igp_2_cable_length_table[0]))
62
63/**
733596be 64 * igb_check_reset_block - Check if PHY reset is blocked
9d5c8243
AK		 65 * @hw: pointer to the HW structure
66 *
67 * Read the PHY management control register and check whether a PHY reset
68 * is blocked. If a reset is not blocked return 0, otherwise
69 * return E1000_BLK_PHY_RESET (12).
70 **/
71s32 igb_check_reset_block(struct e1000_hw *hw)
72{
73 u32 manc;
74
75 manc = rd32(E1000_MANC);
76
77 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
78 E1000_BLK_PHY_RESET : 0;
79}
80
81/**
733596be 82 * igb_get_phy_id - Retrieve the PHY ID and revision
9d5c8243
AK		 83 * @hw: pointer to the HW structure
84 *
85 * Reads the PHY registers and stores the PHY ID and possibly the PHY
86 * revision in the hardware structure.
87 **/
88s32 igb_get_phy_id(struct e1000_hw *hw)
89{
90 struct e1000_phy_info *phy = &hw->phy;
91 s32 ret_val = 0;
92 u16 phy_id;
93
94 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID1, &phy_id);
95 if (ret_val)
96 goto out;
97
98 phy->id = (u32)(phy_id << 16);
99 udelay(20);
100 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID2, &phy_id);
101 if (ret_val)
102 goto out;
103
104 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
105 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
106
107out:
108 return ret_val;
109}
110
111/**
733596be 112 * igb_phy_reset_dsp - Reset PHY DSP
9d5c8243
AK		 113 * @hw: pointer to the HW structure
114 *
115 * Reset the digital signal processor.
116 **/
117static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
118{
119 s32 ret_val;
120
121 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
122 if (ret_val)
123 goto out;
124
125 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
126
127out:
128 return ret_val;
129}
130
131/**
733596be 132 * igb_read_phy_reg_mdic - Read MDI control register
9d5c8243
AK		 133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read
135 * @data: pointer to the read data
136 *
137 * Reads the MDI control regsiter in the PHY at offset and stores the
138 * information read to data.
139 **/
140static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
141{
142 struct e1000_phy_info *phy = &hw->phy;
143 u32 i, mdic = 0;
144 s32 ret_val = 0;
145
146 if (offset > MAX_PHY_REG_ADDRESS) {
652fff32 147 hw_dbg("PHY Address %d is out of range\n", offset);
9d5c8243
AK		 148 ret_val = -E1000_ERR_PARAM;
149 goto out;
150 }
151
152 /*
153 * Set up Op-code, Phy Address, and register offset in the MDI
154 * Control register. The MAC will take care of interfacing with the
155 * PHY to retrieve the desired data.
156 */
157 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
158 (phy->addr << E1000_MDIC_PHY_SHIFT) |
159 (E1000_MDIC_OP_READ));
160
161 wr32(E1000_MDIC, mdic);
162
163 /*
164 * Poll the ready bit to see if the MDI read completed
165 * Increasing the time out as testing showed failures with
166 * the lower time out
167 */
168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
169 udelay(50);
170 mdic = rd32(E1000_MDIC);
171 if (mdic & E1000_MDIC_READY)
172 break;
173 }
174 if (!(mdic & E1000_MDIC_READY)) {
652fff32 175 hw_dbg("MDI Read did not complete\n");
9d5c8243
AK		 176 ret_val = -E1000_ERR_PHY;
177 goto out;
178 }
179 if (mdic & E1000_MDIC_ERROR) {
652fff32 180 hw_dbg("MDI Error\n");
9d5c8243
AK		 181 ret_val = -E1000_ERR_PHY;
182 goto out;
183 }
184 *data = (u16) mdic;
185
186out:
187 return ret_val;
188}
189
190/**
733596be 191 * igb_write_phy_reg_mdic - Write MDI control register
9d5c8243
AK		 192 * @hw: pointer to the HW structure
193 * @offset: register offset to write to
194 * @data: data to write to register at offset
195 *
196 * Writes data to MDI control register in the PHY at offset.
197 **/
198static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
199{
200 struct e1000_phy_info *phy = &hw->phy;
201 u32 i, mdic = 0;
202 s32 ret_val = 0;
203
204 if (offset > MAX_PHY_REG_ADDRESS) {
652fff32 205 hw_dbg("PHY Address %d is out of range\n", offset);
9d5c8243
AK		 206 ret_val = -E1000_ERR_PARAM;
207 goto out;
208 }
209
210 /*
211 * Set up Op-code, Phy Address, and register offset in the MDI
212 * Control register. The MAC will take care of interfacing with the
213 * PHY to retrieve the desired data.
214 */
215 mdic = (((u32)data) |
216 (offset << E1000_MDIC_REG_SHIFT) |
217 (phy->addr << E1000_MDIC_PHY_SHIFT) |
218 (E1000_MDIC_OP_WRITE));
219
220 wr32(E1000_MDIC, mdic);
221
222 /*
223 * Poll the ready bit to see if the MDI read completed
224 * Increasing the time out as testing showed failures with
225 * the lower time out
226 */
227 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
228 udelay(50);
229 mdic = rd32(E1000_MDIC);
230 if (mdic & E1000_MDIC_READY)
231 break;
232 }
233 if (!(mdic & E1000_MDIC_READY)) {
652fff32 234 hw_dbg("MDI Write did not complete\n");
9d5c8243
AK		 235 ret_val = -E1000_ERR_PHY;
236 goto out;
237 }
238 if (mdic & E1000_MDIC_ERROR) {
652fff32 239 hw_dbg("MDI Error\n");
9d5c8243
AK		 240 ret_val = -E1000_ERR_PHY;
241 goto out;
242 }
243
244out:
245 return ret_val;
246}
247
248/**
733596be 249 * igb_read_phy_reg_igp - Read igp PHY register
9d5c8243
AK		 250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read
252 * @data: pointer to the read data
253 *
254 * Acquires semaphore, if necessary, then reads the PHY register at offset
255 * and storing the retrieved information in data. Release any acquired
256 * semaphores before exiting.
257 **/
258s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
259{
260 s32 ret_val;
261
262 ret_val = igb_acquire_phy(hw);
263 if (ret_val)
264 goto out;
265
266 if (offset > MAX_PHY_MULTI_PAGE_REG) {
267 ret_val = igb_write_phy_reg_mdic(hw,
268 IGP01E1000_PHY_PAGE_SELECT,
269 (u16)offset);
270 if (ret_val) {
271 igb_release_phy(hw);
272 goto out;
273 }
274 }
275
276 ret_val = igb_read_phy_reg_mdic(hw,
277 MAX_PHY_REG_ADDRESS & offset,
278 data);
279
280 igb_release_phy(hw);
281
282out:
283 return ret_val;
284}
285
286/**
733596be 287 * igb_write_phy_reg_igp - Write igp PHY register
9d5c8243
AK		 288 * @hw: pointer to the HW structure
289 * @offset: register offset to write to
290 * @data: data to write at register offset
291 *
292 * Acquires semaphore, if necessary, then writes the data to PHY register
293 * at the offset. Release any acquired semaphores before exiting.
294 **/
295s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
296{
297 s32 ret_val;
298
299 ret_val = igb_acquire_phy(hw);
300 if (ret_val)
301 goto out;
302
303 if (offset > MAX_PHY_MULTI_PAGE_REG) {
304 ret_val = igb_write_phy_reg_mdic(hw,
305 IGP01E1000_PHY_PAGE_SELECT,
306 (u16)offset);
307 if (ret_val) {
308 igb_release_phy(hw);
309 goto out;
310 }
311 }
312
313 ret_val = igb_write_phy_reg_mdic(hw,
314 MAX_PHY_REG_ADDRESS & offset,
315 data);
316
317 igb_release_phy(hw);
318
319out:
320 return ret_val;
321}
322
323/**
733596be 324 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
9d5c8243
AK		 325 * @hw: pointer to the HW structure
326 *
327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
328 * and downshift values are set also.
329 **/
330s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
331{
332 struct e1000_phy_info *phy = &hw->phy;
333 s32 ret_val;
334 u16 phy_data;
335
336 if (phy->reset_disable) {
337 ret_val = 0;
338 goto out;
339 }
340
341 /* Enable CRS on TX. This must be set for half-duplex operation. */
342 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
343 &phy_data);
344 if (ret_val)
345 goto out;
346
347 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
348
349 /*
350 * Options:
351 * MDI/MDI-X = 0 (default)
352 * 0 - Auto for all speeds
353 * 1 - MDI mode
354 * 2 - MDI-X mode
355 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
356 */
357 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
358
359 switch (phy->mdix) {
360 case 1:
361 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
362 break;
363 case 2:
364 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
365 break;
366 case 3:
367 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
368 break;
369 case 0:
370 default:
371 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
372 break;
373 }
374
375 /*
376 * Options:
377 * disable_polarity_correction = 0 (default)
378 * Automatic Correction for Reversed Cable Polarity
379 * 0 - Disabled
380 * 1 - Enabled
381 */
382 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
383 if (phy->disable_polarity_correction == 1)
384 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
385
386 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
387 phy_data);
388 if (ret_val)
389 goto out;
390
391 if (phy->revision < E1000_REVISION_4) {
392 /*
393 * Force TX_CLK in the Extended PHY Specific Control Register
394 * to 25MHz clock.
395 */
396 ret_val = hw->phy.ops.read_phy_reg(hw,
397 M88E1000_EXT_PHY_SPEC_CTRL,
398 &phy_data);
399 if (ret_val)
400 goto out;
401
402 phy_data |= M88E1000_EPSCR_TX_CLK_25;
403
404 if ((phy->revision == E1000_REVISION_2) &&
405 (phy->id == M88E1111_I_PHY_ID)) {
406 /* 82573L PHY - set the downshift counter to 5x. */
407 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
408 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
409 } else {
410 /* Configure Master and Slave downshift values */
411 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
412 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
413 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
414 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
415 }
416 ret_val = hw->phy.ops.write_phy_reg(hw,
417 M88E1000_EXT_PHY_SPEC_CTRL,
418 phy_data);
419 if (ret_val)
420 goto out;
421 }
422
423 /* Commit the changes. */
424 ret_val = igb_phy_sw_reset(hw);
425 if (ret_val) {
652fff32 426 hw_dbg("Error committing the PHY changes\n");
9d5c8243
AK		 427 goto out;
428 }
429
430out:
431 return ret_val;
432}
433
434/**
733596be 435 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
9d5c8243
AK		 436 * @hw: pointer to the HW structure
437 *
438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
439 * igp PHY's.
440 **/
441s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
442{
443 struct e1000_phy_info *phy = &hw->phy;
444 s32 ret_val;
445 u16 data;
446
447 if (phy->reset_disable) {
448 ret_val = 0;
449 goto out;
450 }
451
452 ret_val = hw->phy.ops.reset_phy(hw);
453 if (ret_val) {
652fff32 454 hw_dbg("Error resetting the PHY.\n");
9d5c8243
AK		 455 goto out;
456 }
457
458 /* Wait 15ms for MAC to configure PHY from NVM settings. */
459 msleep(15);
460
461 /*
462 * The NVM settings will configure LPLU in D3 for
463 * non-IGP1 PHYs.
464 */
465 if (phy->type == e1000_phy_igp) {
466 /* disable lplu d3 during driver init */
467 if (hw->phy.ops.set_d3_lplu_state)
468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
469 if (ret_val) {
652fff32 470 hw_dbg("Error Disabling LPLU D3\n");
9d5c8243
AK		 471 goto out;
472 }
473 }
474
475 /* disable lplu d0 during driver init */
476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
477 if (ret_val) {
652fff32 478 hw_dbg("Error Disabling LPLU D0\n");
9d5c8243
AK		 479 goto out;
480 }
481 /* Configure mdi-mdix settings */
482 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
483 if (ret_val)
484 goto out;
485
486 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
487
488 switch (phy->mdix) {
489 case 1:
490 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
491 break;
492 case 2:
493 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
494 break;
495 case 0:
496 default:
497 data |= IGP01E1000_PSCR_AUTO_MDIX;
498 break;
499 }
500 ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
501 if (ret_val)
502 goto out;
503
504 /* set auto-master slave resolution settings */
505 if (hw->mac.autoneg) {
506 /*
507 * when autonegotiation advertisement is only 1000Mbps then we
508 * should disable SmartSpeed and enable Auto MasterSlave
509 * resolution as hardware default.
510 */
511 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
512 /* Disable SmartSpeed */
513 ret_val = hw->phy.ops.read_phy_reg(hw,
514 IGP01E1000_PHY_PORT_CONFIG,
515 &data);
516 if (ret_val)
517 goto out;
518
519 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
520 ret_val = hw->phy.ops.write_phy_reg(hw,
521 IGP01E1000_PHY_PORT_CONFIG,
522 data);
523 if (ret_val)
524 goto out;
525
526 /* Set auto Master/Slave resolution process */
527 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL,
528 &data);
529 if (ret_val)
530 goto out;
531
532 data &= ~CR_1000T_MS_ENABLE;
533 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL,
534 data);
535 if (ret_val)
536 goto out;
537 }
538
539 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL, &data);
540 if (ret_val)
541 goto out;
542
543 /* load defaults for future use */
544 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
545 ((data & CR_1000T_MS_VALUE) ?
546 e1000_ms_force_master :
547 e1000_ms_force_slave) :
548 e1000_ms_auto;
549
550 switch (phy->ms_type) {
551 case e1000_ms_force_master:
552 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
553 break;
554 case e1000_ms_force_slave:
555 data |= CR_1000T_MS_ENABLE;
556 data &= ~(CR_1000T_MS_VALUE);
557 break;
558 case e1000_ms_auto:
559 data &= ~CR_1000T_MS_ENABLE;
560 default:
561 break;
562 }
563 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL, data);
564 if (ret_val)
565 goto out;
566 }
567
568out:
569 return ret_val;
570}
571
572/**
733596be 573 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
9d5c8243
AK		 574 * @hw: pointer to the HW structure
575 *
576 * Performs initial bounds checking on autoneg advertisement parameter, then
577 * configure to advertise the full capability. Setup the PHY to autoneg
578 * and restart the negotiation process between the link partner. If
579 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
580 **/
581s32 igb_copper_link_autoneg(struct e1000_hw *hw)
582{
583 struct e1000_phy_info *phy = &hw->phy;
584 s32 ret_val;
585 u16 phy_ctrl;
586
587 /*
588 * Perform some bounds checking on the autoneg advertisement
589 * parameter.
590 */
591 phy->autoneg_advertised &= phy->autoneg_mask;
592
593 /*
594 * If autoneg_advertised is zero, we assume it was not defaulted
595 * by the calling code so we set to advertise full capability.
596 */
597 if (phy->autoneg_advertised == 0)
598 phy->autoneg_advertised = phy->autoneg_mask;
599
652fff32 600 hw_dbg("Reconfiguring auto-neg advertisement params\n");
9d5c8243
AK		 601 ret_val = igb_phy_setup_autoneg(hw);
602 if (ret_val) {
652fff32 603 hw_dbg("Error Setting up Auto-Negotiation\n");
9d5c8243
AK		 604 goto out;
605 }
652fff32 606 hw_dbg("Restarting Auto-Neg\n");
9d5c8243
AK		 607
608 /*
609 * Restart auto-negotiation by setting the Auto Neg Enable bit and
610 * the Auto Neg Restart bit in the PHY control register.
611 */
612 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
613 if (ret_val)
614 goto out;
615
616 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
617 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
618 if (ret_val)
619 goto out;
620
621 /*
622 * Does the user want to wait for Auto-Neg to complete here, or
623 * check at a later time (for example, callback routine).
624 */
625 if (phy->autoneg_wait_to_complete) {
626 ret_val = igb_wait_autoneg(hw);
627 if (ret_val) {
652fff32
AK		 628 hw_dbg("Error while waiting for "
629 "autoneg to complete\n");
9d5c8243
AK		 630 goto out;
631 }
632 }
633
634 hw->mac.get_link_status = true;
635
636out:
637 return ret_val;
638}
639
640/**
733596be 641 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
9d5c8243
AK		 642 * @hw: pointer to the HW structure
643 *
644 * Reads the MII auto-neg advertisement register and/or the 1000T control
645 * register and if the PHY is already setup for auto-negotiation, then
646 * return successful. Otherwise, setup advertisement and flow control to
647 * the appropriate values for the wanted auto-negotiation.
648 **/
649static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
650{
651 struct e1000_phy_info *phy = &hw->phy;
652 s32 ret_val;
653 u16 mii_autoneg_adv_reg;
654 u16 mii_1000t_ctrl_reg = 0;
655
656 phy->autoneg_advertised &= phy->autoneg_mask;
657
658 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
659 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV,
660 &mii_autoneg_adv_reg);
661 if (ret_val)
662 goto out;
663
664 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
665 /* Read the MII 1000Base-T Control Register (Address 9). */
666 ret_val = hw->phy.ops.read_phy_reg(hw,
667 PHY_1000T_CTRL,
668 &mii_1000t_ctrl_reg);
669 if (ret_val)
670 goto out;
671 }
672
673 /*
674 * Need to parse both autoneg_advertised and fc and set up
675 * the appropriate PHY registers. First we will parse for
676 * autoneg_advertised software override. Since we can advertise
677 * a plethora of combinations, we need to check each bit
678 * individually.
679 */
680
681 /*
682 * First we clear all the 10/100 mb speed bits in the Auto-Neg
683 * Advertisement Register (Address 4) and the 1000 mb speed bits in
684 * the 1000Base-T Control Register (Address 9).
685 */
686 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
687 NWAY_AR_100TX_HD_CAPS |
688 NWAY_AR_10T_FD_CAPS |
689 NWAY_AR_10T_HD_CAPS);
690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
691
652fff32 692 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
9d5c8243
AK		 693
694 /* Do we want to advertise 10 Mb Half Duplex? */
695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
652fff32 696 hw_dbg("Advertise 10mb Half duplex\n");
9d5c8243
AK		 697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
698 }
699
700 /* Do we want to advertise 10 Mb Full Duplex? */
701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
652fff32 702 hw_dbg("Advertise 10mb Full duplex\n");
9d5c8243
AK		 703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
704 }
705
706 /* Do we want to advertise 100 Mb Half Duplex? */
707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
652fff32 708 hw_dbg("Advertise 100mb Half duplex\n");
9d5c8243
AK		 709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
710 }
711
712 /* Do we want to advertise 100 Mb Full Duplex? */
713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
652fff32 714 hw_dbg("Advertise 100mb Full duplex\n");
9d5c8243
AK		 715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
716 }
717
718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
652fff32 720 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
9d5c8243
AK		 721
722 /* Do we want to advertise 1000 Mb Full Duplex? */
723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
652fff32 724 hw_dbg("Advertise 1000mb Full duplex\n");
9d5c8243
AK		 725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
726 }
727
728 /*
729 * Check for a software override of the flow control settings, and
730 * setup the PHY advertisement registers accordingly. If
731 * auto-negotiation is enabled, then software will have to set the
732 * "PAUSE" bits to the correct value in the Auto-Negotiation
733 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
734 * negotiation.
735 *
736 * The possible values of the "fc" parameter are:
737 * 0: Flow control is completely disabled
738 * 1: Rx flow control is enabled (we can receive pause frames
739 * but not send pause frames).
740 * 2: Tx flow control is enabled (we can send pause frames
741 * but we do not support receiving pause frames).
742 * 3: Both Rx and TX flow control (symmetric) are enabled.
743 * other: No software override. The flow control configuration
744 * in the EEPROM is used.
745 */
746 switch (hw->fc.type) {
747 case e1000_fc_none:
748 /*
749 * Flow control (RX & TX) is completely disabled by a
750 * software over-ride.
751 */
752 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
753 break;
754 case e1000_fc_rx_pause:
755 /*
756 * RX Flow control is enabled, and TX Flow control is
757 * disabled, by a software over-ride.
758 *
759 * Since there really isn't a way to advertise that we are
760 * capable of RX Pause ONLY, we will advertise that we
761 * support both symmetric and asymmetric RX PAUSE. Later
762 * (in e1000_config_fc_after_link_up) we will disable the
763 * hw's ability to send PAUSE frames.
764 */
765 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
766 break;
767 case e1000_fc_tx_pause:
768 /*
769 * TX Flow control is enabled, and RX Flow control is
770 * disabled, by a software over-ride.
771 */
772 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
773 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
774 break;
775 case e1000_fc_full:
776 /*
777 * Flow control (both RX and TX) is enabled by a software
778 * over-ride.
779 */
780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
781 break;
782 default:
652fff32 783 hw_dbg("Flow control param set incorrectly\n");
9d5c8243
AK		 784 ret_val = -E1000_ERR_CONFIG;
785 goto out;
786 }
787
788 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_AUTONEG_ADV,
789 mii_autoneg_adv_reg);
790 if (ret_val)
791 goto out;
792
652fff32 793 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
9d5c8243
AK		 794
795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
796 ret_val = hw->phy.ops.write_phy_reg(hw,
797 PHY_1000T_CTRL,
798 mii_1000t_ctrl_reg);
799 if (ret_val)
800 goto out;
801 }
802
803out:
804 return ret_val;
805}
806
807/**
733596be 808 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
9d5c8243
AK		 809 * @hw: pointer to the HW structure
810 *
811 * Calls the PHY setup function to force speed and duplex. Clears the
812 * auto-crossover to force MDI manually. Waits for link and returns
813 * successful if link up is successful, else -E1000_ERR_PHY (-2).
814 **/
815s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
816{
817 struct e1000_phy_info *phy = &hw->phy;
818 s32 ret_val;
819 u16 phy_data;
820 bool link;
821
822 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
823 if (ret_val)
824 goto out;
825
826 igb_phy_force_speed_duplex_setup(hw, &phy_data);
827
828 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
829 if (ret_val)
830 goto out;
831
832 /*
833 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
834 * forced whenever speed and duplex are forced.
835 */
836 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
837 &phy_data);
838 if (ret_val)
839 goto out;
840
841 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
842 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
843
844 ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
845 phy_data);
846 if (ret_val)
847 goto out;
848
652fff32 849 hw_dbg("IGP PSCR: %X\n", phy_data);
9d5c8243
AK		 850
851 udelay(1);
852
853 if (phy->autoneg_wait_to_complete) {
652fff32 854 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
9d5c8243
AK		 855
856 ret_val = igb_phy_has_link(hw,
857 PHY_FORCE_LIMIT,
858 100000,
859 &link);
860 if (ret_val)
861 goto out;
862
863 if (!link)
652fff32 864 hw_dbg("Link taking longer than expected.\n");
9d5c8243
AK		 865
866 /* Try once more */
867 ret_val = igb_phy_has_link(hw,
868 PHY_FORCE_LIMIT,
869 100000,
870 &link);
871 if (ret_val)
872 goto out;
873 }
874
875out:
876 return ret_val;
877}
878
879/**
733596be 880 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
9d5c8243
AK		 881 * @hw: pointer to the HW structure
882 *
883 * Calls the PHY setup function to force speed and duplex. Clears the
884 * auto-crossover to force MDI manually. Resets the PHY to commit the
885 * changes. If time expires while waiting for link up, we reset the DSP.
886 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
887 * successful completion, else return corresponding error code.
888 **/
889s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
890{
891 struct e1000_phy_info *phy = &hw->phy;
892 s32 ret_val;
893 u16 phy_data;
894 bool link;
895
896 /*
897 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
898 * forced whenever speed and duplex are forced.
899 */
900 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
901 &phy_data);
902 if (ret_val)
903 goto out;
904
905 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
906 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
907 phy_data);
908 if (ret_val)
909 goto out;
910
652fff32 911 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
9d5c8243
AK		 912
913 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
914 if (ret_val)
915 goto out;
916
917 igb_phy_force_speed_duplex_setup(hw, &phy_data);
918
919 /* Reset the phy to commit changes. */
920 phy_data |= MII_CR_RESET;
921
922 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
923 if (ret_val)
924 goto out;
925
926 udelay(1);
927
928 if (phy->autoneg_wait_to_complete) {
652fff32 929 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
9d5c8243
AK		 930
931 ret_val = igb_phy_has_link(hw,
932 PHY_FORCE_LIMIT,
933 100000,
934 &link);
935 if (ret_val)
936 goto out;
937
938 if (!link) {
939 /*
940 * We didn't get link.
941 * Reset the DSP and cross our fingers.
942 */
943 ret_val = hw->phy.ops.write_phy_reg(hw,
944 M88E1000_PHY_PAGE_SELECT,
945 0x001d);
946 if (ret_val)
947 goto out;
948 ret_val = igb_phy_reset_dsp(hw);
949 if (ret_val)
950 goto out;
951 }
952
953 /* Try once more */
954 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
955 100000, &link);
956 if (ret_val)
957 goto out;
958 }
959
960 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
961 &phy_data);
962 if (ret_val)
963 goto out;
964
965 /*
966 * Resetting the phy means we need to re-force TX_CLK in the
967 * Extended PHY Specific Control Register to 25MHz clock from
968 * the reset value of 2.5MHz.
969 */
970 phy_data |= M88E1000_EPSCR_TX_CLK_25;
971 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
972 phy_data);
973 if (ret_val)
974 goto out;
975
976 /*
977 * In addition, we must re-enable CRS on Tx for both half and full
978 * duplex.
979 */
980 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
981 &phy_data);
982 if (ret_val)
983 goto out;
984
985 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
986 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
987 phy_data);
988
989out:
990 return ret_val;
991}
992
993/**
733596be 994 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
9d5c8243
AK		 995 * @hw: pointer to the HW structure
996 * @phy_ctrl: pointer to current value of PHY_CONTROL
997 *
998 * Forces speed and duplex on the PHY by doing the following: disable flow
999 * control, force speed/duplex on the MAC, disable auto speed detection,
1000 * disable auto-negotiation, configure duplex, configure speed, configure
1001 * the collision distance, write configuration to CTRL register. The
1002 * caller must write to the PHY_CONTROL register for these settings to
1003 * take affect.
1004 **/
1005static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1006 u16 *phy_ctrl)
1007{
1008 struct e1000_mac_info *mac = &hw->mac;
1009 u32 ctrl;
1010
1011 /* Turn off flow control when forcing speed/duplex */
1012 hw->fc.type = e1000_fc_none;
1013
1014 /* Force speed/duplex on the mac */
1015 ctrl = rd32(E1000_CTRL);
1016 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1017 ctrl &= ~E1000_CTRL_SPD_SEL;
1018
1019 /* Disable Auto Speed Detection */
1020 ctrl &= ~E1000_CTRL_ASDE;
1021
1022 /* Disable autoneg on the phy */
1023 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1024
1025 /* Forcing Full or Half Duplex? */
1026 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1027 ctrl &= ~E1000_CTRL_FD;
1028 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
652fff32 1029 hw_dbg("Half Duplex\n");
9d5c8243
AK		 1030 } else {
1031 ctrl |= E1000_CTRL_FD;
1032 *phy_ctrl |= MII_CR_FULL_DUPLEX;
652fff32 1033 hw_dbg("Full Duplex\n");
9d5c8243
AK		 1034 }
1035
1036 /* Forcing 10mb or 100mb? */
1037 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1038 ctrl |= E1000_CTRL_SPD_100;
1039 *phy_ctrl |= MII_CR_SPEED_100;
1040 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
652fff32 1041 hw_dbg("Forcing 100mb\n");
9d5c8243
AK		 1042 } else {
1043 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1044 *phy_ctrl |= MII_CR_SPEED_10;
1045 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
652fff32 1046 hw_dbg("Forcing 10mb\n");
9d5c8243
AK		 1047 }
1048
1049 igb_config_collision_dist(hw);
1050
1051 wr32(E1000_CTRL, ctrl);
1052}
1053
1054/**
733596be 1055 * igb_set_d3_lplu_state - Sets low power link up state for D3
9d5c8243
AK		 1056 * @hw: pointer to the HW structure
1057 * @active: boolean used to enable/disable lplu
1058 *
1059 * Success returns 0, Failure returns 1
1060 *
1061 * The low power link up (lplu) state is set to the power management level D3
1062 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1063 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1064 * is used during Dx states where the power conservation is most important.
1065 * During driver activity, SmartSpeed should be enabled so performance is
1066 * maintained.
1067 **/
1068s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1069{
1070 struct e1000_phy_info *phy = &hw->phy;
1071 s32 ret_val;
1072 u16 data;
1073
1074 ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1075 &data);
1076 if (ret_val)
1077 goto out;
1078
1079 if (!active) {
1080 data &= ~IGP02E1000_PM_D3_LPLU;
1081 ret_val = hw->phy.ops.write_phy_reg(hw,
1082 IGP02E1000_PHY_POWER_MGMT,
1083 data);
1084 if (ret_val)
1085 goto out;
1086 /*
1087 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1088 * during Dx states where the power conservation is most
1089 * important. During driver activity we should enable
1090 * SmartSpeed, so performance is maintained.
1091 */
1092 if (phy->smart_speed == e1000_smart_speed_on) {
1093 ret_val = hw->phy.ops.read_phy_reg(hw,
1094 IGP01E1000_PHY_PORT_CONFIG,
1095 &data);
1096 if (ret_val)
1097 goto out;
1098
1099 data |= IGP01E1000_PSCFR_SMART_SPEED;
1100 ret_val = hw->phy.ops.write_phy_reg(hw,
1101 IGP01E1000_PHY_PORT_CONFIG,
1102 data);
1103 if (ret_val)
1104 goto out;
1105 } else if (phy->smart_speed == e1000_smart_speed_off) {
1106 ret_val = hw->phy.ops.read_phy_reg(hw,
1107 IGP01E1000_PHY_PORT_CONFIG,
1108 &data);
1109 if (ret_val)
1110 goto out;
1111
1112 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1113 ret_val = hw->phy.ops.write_phy_reg(hw,
1114 IGP01E1000_PHY_PORT_CONFIG,
1115 data);
1116 if (ret_val)
1117 goto out;
1118 }
1119 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1120 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1121 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1122 data |= IGP02E1000_PM_D3_LPLU;
1123 ret_val = hw->phy.ops.write_phy_reg(hw,
1124 IGP02E1000_PHY_POWER_MGMT,
1125 data);
1126 if (ret_val)
1127 goto out;
1128
1129 /* When LPLU is enabled, we should disable SmartSpeed */
1130 ret_val = hw->phy.ops.read_phy_reg(hw,
1131 IGP01E1000_PHY_PORT_CONFIG,
1132 &data);
1133 if (ret_val)
1134 goto out;
1135
1136 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1137 ret_val = hw->phy.ops.write_phy_reg(hw,
1138 IGP01E1000_PHY_PORT_CONFIG,
1139 data);
1140 }
1141
1142out:
1143 return ret_val;
1144}
1145
1146/**
733596be 1147 * igb_check_downshift - Checks whether a downshift in speed occured
9d5c8243
AK		 1148 * @hw: pointer to the HW structure
1149 *
1150 * Success returns 0, Failure returns 1
1151 *
1152 * A downshift is detected by querying the PHY link health.
1153 **/
1154s32 igb_check_downshift(struct e1000_hw *hw)
1155{
1156 struct e1000_phy_info *phy = &hw->phy;
1157 s32 ret_val;
1158 u16 phy_data, offset, mask;
1159
1160 switch (phy->type) {
1161 case e1000_phy_m88:
1162 case e1000_phy_gg82563:
1163 offset = M88E1000_PHY_SPEC_STATUS;
1164 mask = M88E1000_PSSR_DOWNSHIFT;
1165 break;
1166 case e1000_phy_igp_2:
1167 case e1000_phy_igp:
1168 case e1000_phy_igp_3:
1169 offset = IGP01E1000_PHY_LINK_HEALTH;
1170 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1171 break;
1172 default:
1173 /* speed downshift not supported */
1174 phy->speed_downgraded = false;
1175 ret_val = 0;
1176 goto out;
1177 }
1178
1179 ret_val = hw->phy.ops.read_phy_reg(hw, offset, &phy_data);
1180
1181 if (!ret_val)
1182 phy->speed_downgraded = (phy_data & mask) ? true : false;
1183
1184out:
1185 return ret_val;
1186}
1187
1188/**
733596be 1189 * igb_check_polarity_m88 - Checks the polarity.
9d5c8243
AK		 1190 * @hw: pointer to the HW structure
1191 *
1192 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1193 *
1194 * Polarity is determined based on the PHY specific status register.
1195 **/
1196static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1197{
1198 struct e1000_phy_info *phy = &hw->phy;
1199 s32 ret_val;
1200 u16 data;
1201
1202 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1203
1204 if (!ret_val)
1205 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1206 ? e1000_rev_polarity_reversed
1207 : e1000_rev_polarity_normal;
1208
1209 return ret_val;
1210}
1211
1212/**
733596be 1213 * igb_check_polarity_igp - Checks the polarity.
9d5c8243
AK		 1214 * @hw: pointer to the HW structure
1215 *
1216 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1217 *
1218 * Polarity is determined based on the PHY port status register, and the
1219 * current speed (since there is no polarity at 100Mbps).
1220 **/
1221static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1222{
1223 struct e1000_phy_info *phy = &hw->phy;
1224 s32 ret_val;
1225 u16 data, offset, mask;
1226
1227 /*
1228 * Polarity is determined based on the speed of
1229 * our connection.
1230 */
1231 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1232 &data);
1233 if (ret_val)
1234 goto out;
1235
1236 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1237 IGP01E1000_PSSR_SPEED_1000MBPS) {
1238 offset = IGP01E1000_PHY_PCS_INIT_REG;
1239 mask = IGP01E1000_PHY_POLARITY_MASK;
1240 } else {
1241 /*
1242 * This really only applies to 10Mbps since
1243 * there is no polarity for 100Mbps (always 0).
1244 */
1245 offset = IGP01E1000_PHY_PORT_STATUS;
1246 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1247 }
1248
1249 ret_val = hw->phy.ops.read_phy_reg(hw, offset, &data);
1250
1251 if (!ret_val)
1252 phy->cable_polarity = (data & mask)
1253 ? e1000_rev_polarity_reversed
1254 : e1000_rev_polarity_normal;
1255
1256out:
1257 return ret_val;
1258}
1259
1260/**
733596be 1261 * igb_wait_autoneg - Wait for auto-neg compeletion
9d5c8243
AK		 1262 * @hw: pointer to the HW structure
1263 *
1264 * Waits for auto-negotiation to complete or for the auto-negotiation time
1265 * limit to expire, which ever happens first.
1266 **/
1267static s32 igb_wait_autoneg(struct e1000_hw *hw)
1268{
1269 s32 ret_val = 0;
1270 u16 i, phy_status;
1271
1272 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1273 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1274 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1275 if (ret_val)
1276 break;
1277 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1278 if (ret_val)
1279 break;
1280 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1281 break;
1282 msleep(100);
1283 }
1284
1285 /*
1286 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1287 * has completed.
1288 */
1289 return ret_val;
1290}
1291
1292/**
733596be 1293 * igb_phy_has_link - Polls PHY for link
9d5c8243
AK		 1294 * @hw: pointer to the HW structure
1295 * @iterations: number of times to poll for link
1296 * @usec_interval: delay between polling attempts
1297 * @success: pointer to whether polling was successful or not
1298 *
1299 * Polls the PHY status register for link, 'iterations' number of times.
1300 **/
1301s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1302 u32 usec_interval, bool *success)
1303{
1304 s32 ret_val = 0;
1305 u16 i, phy_status;
1306
1307 for (i = 0; i < iterations; i++) {
1308 /*
1309 * Some PHYs require the PHY_STATUS register to be read
1310 * twice due to the link bit being sticky. No harm doing
1311 * it across the board.
1312 */
1313 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1314 if (ret_val)
1315 break;
1316 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1317 if (ret_val)
1318 break;
1319 if (phy_status & MII_SR_LINK_STATUS)
1320 break;
1321 if (usec_interval >= 1000)
1322 mdelay(usec_interval/1000);
1323 else
1324 udelay(usec_interval);
1325 }
1326
1327 *success = (i < iterations) ? true : false;
1328
1329 return ret_val;
1330}
1331
1332/**
733596be 1333 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
9d5c8243
AK		 1334 * @hw: pointer to the HW structure
1335 *
1336 * Reads the PHY specific status register to retrieve the cable length
1337 * information. The cable length is determined by averaging the minimum and
1338 * maximum values to get the "average" cable length. The m88 PHY has four
1339 * possible cable length values, which are:
1340 * Register Value Cable Length
1341 * 0 < 50 meters
1342 * 1 50 - 80 meters
1343 * 2 80 - 110 meters
1344 * 3 110 - 140 meters
1345 * 4 > 140 meters
1346 **/
1347s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1348{
1349 struct e1000_phy_info *phy = &hw->phy;
1350 s32 ret_val;
1351 u16 phy_data, index;
1352
1353 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1354 &phy_data);
1355 if (ret_val)
1356 goto out;
1357
1358 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1359 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1360 phy->min_cable_length = e1000_m88_cable_length_table[index];
1361 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1362
1363 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1364
1365out:
1366 return ret_val;
1367}
1368
1369/**
733596be 1370 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
9d5c8243
AK		 1371 * @hw: pointer to the HW structure
1372 *
1373 * The automatic gain control (agc) normalizes the amplitude of the
1374 * received signal, adjusting for the attenuation produced by the
1375 * cable. By reading the AGC registers, which reperesent the
1376 * cobination of course and fine gain value, the value can be put
1377 * into a lookup table to obtain the approximate cable length
1378 * for each channel.
1379 **/
1380s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1381{
1382 struct e1000_phy_info *phy = &hw->phy;
1383 s32 ret_val = 0;
1384 u16 phy_data, i, agc_value = 0;
1385 u16 cur_agc_index, max_agc_index = 0;
1386 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1387 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1388 {IGP02E1000_PHY_AGC_A,
1389 IGP02E1000_PHY_AGC_B,
1390 IGP02E1000_PHY_AGC_C,
1391 IGP02E1000_PHY_AGC_D};
1392
1393 /* Read the AGC registers for all channels */
1394 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1395 ret_val = hw->phy.ops.read_phy_reg(hw, agc_reg_array[i],
1396 &phy_data);
1397 if (ret_val)
1398 goto out;
1399
1400 /*
1401 * Getting bits 15:9, which represent the combination of
1402 * course and fine gain values. The result is a number
1403 * that can be put into the lookup table to obtain the
1404 * approximate cable length.
1405 */
1406 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1407 IGP02E1000_AGC_LENGTH_MASK;
1408
1409 /* Array index bound check. */
1410 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1411 (cur_agc_index == 0)) {
1412 ret_val = -E1000_ERR_PHY;
1413 goto out;
1414 }
1415
1416 /* Remove min & max AGC values from calculation. */
1417 if (e1000_igp_2_cable_length_table[min_agc_index] >
1418 e1000_igp_2_cable_length_table[cur_agc_index])
1419 min_agc_index = cur_agc_index;
1420 if (e1000_igp_2_cable_length_table[max_agc_index] <
1421 e1000_igp_2_cable_length_table[cur_agc_index])
1422 max_agc_index = cur_agc_index;
1423
1424 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1425 }
1426
1427 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1428 e1000_igp_2_cable_length_table[max_agc_index]);
1429 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1430
1431 /* Calculate cable length with the error range of +/- 10 meters. */
1432 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1433 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1434 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1435
1436 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1437
1438out:
1439 return ret_val;
1440}
1441
1442/**
733596be 1443 * igb_get_phy_info_m88 - Retrieve PHY information
9d5c8243
AK		 1444 * @hw: pointer to the HW structure
1445 *
1446 * Valid for only copper links. Read the PHY status register (sticky read)
1447 * to verify that link is up. Read the PHY special control register to
1448 * determine the polarity and 10base-T extended distance. Read the PHY
1449 * special status register to determine MDI/MDIx and current speed. If
1450 * speed is 1000, then determine cable length, local and remote receiver.
1451 **/
1452s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1453{
1454 struct e1000_phy_info *phy = &hw->phy;
1455 s32 ret_val;
1456 u16 phy_data;
1457 bool link;
1458
1459 if (hw->phy.media_type != e1000_media_type_copper) {
652fff32 1460 hw_dbg("Phy info is only valid for copper media\n");
9d5c8243
AK		 1461 ret_val = -E1000_ERR_CONFIG;
1462 goto out;
1463 }
1464
1465 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1466 if (ret_val)
1467 goto out;
1468
1469 if (!link) {
652fff32 1470 hw_dbg("Phy info is only valid if link is up\n");
9d5c8243
AK		 1471 ret_val = -E1000_ERR_CONFIG;
1472 goto out;
1473 }
1474
1475 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1476 &phy_data);
1477 if (ret_val)
1478 goto out;
1479
1480 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1481 ? true
1482 : false;
1483
1484 ret_val = igb_check_polarity_m88(hw);
1485 if (ret_val)
1486 goto out;
1487
1488 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1489 &phy_data);
1490 if (ret_val)
1491 goto out;
1492
1493 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1494
1495 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1496 ret_val = hw->phy.ops.get_cable_length(hw);
1497 if (ret_val)
1498 goto out;
1499
1500 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
1501 &phy_data);
1502 if (ret_val)
1503 goto out;
1504
1505 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1506 ? e1000_1000t_rx_status_ok
1507 : e1000_1000t_rx_status_not_ok;
1508
1509 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1510 ? e1000_1000t_rx_status_ok
1511 : e1000_1000t_rx_status_not_ok;
1512 } else {
1513 /* Set values to "undefined" */
1514 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1515 phy->local_rx = e1000_1000t_rx_status_undefined;
1516 phy->remote_rx = e1000_1000t_rx_status_undefined;
1517 }
1518
1519out:
1520 return ret_val;
1521}
1522
1523/**
733596be 1524 * igb_get_phy_info_igp - Retrieve igp PHY information
9d5c8243
AK		 1525 * @hw: pointer to the HW structure
1526 *
1527 * Read PHY status to determine if link is up. If link is up, then
1528 * set/determine 10base-T extended distance and polarity correction. Read
1529 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1530 * determine on the cable length, local and remote receiver.
1531 **/
1532s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1533{
1534 struct e1000_phy_info *phy = &hw->phy;
1535 s32 ret_val;
1536 u16 data;
1537 bool link;
1538
1539 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1540 if (ret_val)
1541 goto out;
1542
1543 if (!link) {
652fff32 1544 hw_dbg("Phy info is only valid if link is up\n");
9d5c8243
AK		 1545 ret_val = -E1000_ERR_CONFIG;
1546 goto out;
1547 }
1548
1549 phy->polarity_correction = true;
1550
1551 ret_val = igb_check_polarity_igp(hw);
1552 if (ret_val)
1553 goto out;
1554
1555 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1556 &data);
1557 if (ret_val)
1558 goto out;
1559
1560 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1561
1562 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1563 IGP01E1000_PSSR_SPEED_1000MBPS) {
1564 ret_val = hw->phy.ops.get_cable_length(hw);
1565 if (ret_val)
1566 goto out;
1567
1568 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
1569 &data);
1570 if (ret_val)
1571 goto out;
1572
1573 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1574 ? e1000_1000t_rx_status_ok
1575 : e1000_1000t_rx_status_not_ok;
1576
1577 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1578 ? e1000_1000t_rx_status_ok
1579 : e1000_1000t_rx_status_not_ok;
1580 } else {
1581 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1582 phy->local_rx = e1000_1000t_rx_status_undefined;
1583 phy->remote_rx = e1000_1000t_rx_status_undefined;
1584 }
1585
1586out:
1587 return ret_val;
1588}
1589
1590/**
733596be 1591 * igb_phy_sw_reset - PHY software reset
9d5c8243
AK		 1592 * @hw: pointer to the HW structure
1593 *
1594 * Does a software reset of the PHY by reading the PHY control register and
1595 * setting/write the control register reset bit to the PHY.
1596 **/
1597s32 igb_phy_sw_reset(struct e1000_hw *hw)
1598{
1599 s32 ret_val;
1600 u16 phy_ctrl;
1601
1602 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
1603 if (ret_val)
1604 goto out;
1605
1606 phy_ctrl |= MII_CR_RESET;
1607 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
1608 if (ret_val)
1609 goto out;
1610
1611 udelay(1);
1612
1613out:
1614 return ret_val;
1615}
1616
1617/**
733596be 1618 * igb_phy_hw_reset - PHY hardware reset
9d5c8243
AK		 1619 * @hw: pointer to the HW structure
1620 *
1621 * Verify the reset block is not blocking us from resetting. Acquire
1622 * semaphore (if necessary) and read/set/write the device control reset
1623 * bit in the PHY. Wait the appropriate delay time for the device to
1624 * reset and relase the semaphore (if necessary).
1625 **/
1626s32 igb_phy_hw_reset(struct e1000_hw *hw)
1627{
1628 struct e1000_phy_info *phy = &hw->phy;
1629 s32 ret_val;
1630 u32 ctrl;
1631
1632 ret_val = igb_check_reset_block(hw);
1633 if (ret_val) {
1634 ret_val = 0;
1635 goto out;
1636 }
1637
1638 ret_val = igb_acquire_phy(hw);
1639 if (ret_val)
1640 goto out;
1641
1642 ctrl = rd32(E1000_CTRL);
1643 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1644 wrfl();
1645
1646 udelay(phy->reset_delay_us);
1647
1648 wr32(E1000_CTRL, ctrl);
1649 wrfl();
1650
1651 udelay(150);
1652
1653 igb_release_phy(hw);
1654
1655 ret_val = igb_get_phy_cfg_done(hw);
1656
1657out:
1658 return ret_val;
1659}
1660
1661/* Internal function pointers */
1662
1663/**
733596be 1664 * igb_get_phy_cfg_done - Generic PHY configuration done
9d5c8243
AK		 1665 * @hw: pointer to the HW structure
1666 *
1667 * Return success if silicon family did not implement a family specific
1668 * get_cfg_done function.
1669 **/
1670static s32 igb_get_phy_cfg_done(struct e1000_hw *hw)
1671{
1672 if (hw->phy.ops.get_cfg_done)
1673 return hw->phy.ops.get_cfg_done(hw);
1674
1675 return 0;
1676}
1677
1678/**
733596be 1679 * igb_release_phy - Generic release PHY
9d5c8243
AK		 1680 * @hw: pointer to the HW structure
1681 *
1682 * Return if silicon family does not require a semaphore when accessing the
1683 * PHY.
1684 **/
1685static void igb_release_phy(struct e1000_hw *hw)
1686{
1687 if (hw->phy.ops.release_phy)
1688 hw->phy.ops.release_phy(hw);
1689}
1690
1691/**
733596be 1692 * igb_acquire_phy - Generic acquire PHY
9d5c8243
AK		 1693 * @hw: pointer to the HW structure
1694 *
1695 * Return success if silicon family does not require a semaphore when
1696 * accessing the PHY.
1697 **/
1698static s32 igb_acquire_phy(struct e1000_hw *hw)
1699{
1700 if (hw->phy.ops.acquire_phy)
1701 return hw->phy.ops.acquire_phy(hw);
1702
1703 return 0;
1704}
1705
1706/**
733596be 1707 * igb_phy_force_speed_duplex - Generic force PHY speed/duplex
9d5c8243
AK		 1708 * @hw: pointer to the HW structure
1709 *
1710 * When the silicon family has not implemented a forced speed/duplex
1711 * function for the PHY, simply return 0.
1712 **/
1713s32 igb_phy_force_speed_duplex(struct e1000_hw *hw)
1714{
1715 if (hw->phy.ops.force_speed_duplex)
1716 return hw->phy.ops.force_speed_duplex(hw);
1717
1718 return 0;
1719}
1720
1721/**
733596be 1722 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
9d5c8243
AK		 1723 * @hw: pointer to the HW structure
1724 *
1725 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1726 **/
1727s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1728{
652fff32 1729 hw_dbg("Running IGP 3 PHY init script\n");
9d5c8243
AK		 1730
1731 /* PHY init IGP 3 */
1732 /* Enable rise/fall, 10-mode work in class-A */
1733 hw->phy.ops.write_phy_reg(hw, 0x2F5B, 0x9018);
1734 /* Remove all caps from Replica path filter */
1735 hw->phy.ops.write_phy_reg(hw, 0x2F52, 0x0000);
1736 /* Bias trimming for ADC, AFE and Driver (Default) */
1737 hw->phy.ops.write_phy_reg(hw, 0x2FB1, 0x8B24);
1738 /* Increase Hybrid poly bias */
1739 hw->phy.ops.write_phy_reg(hw, 0x2FB2, 0xF8F0);
1740 /* Add 4% to TX amplitude in Giga mode */
1741 hw->phy.ops.write_phy_reg(hw, 0x2010, 0x10B0);
1742 /* Disable trimming (TTT) */
1743 hw->phy.ops.write_phy_reg(hw, 0x2011, 0x0000);
1744 /* Poly DC correction to 94.6% + 2% for all channels */
1745 hw->phy.ops.write_phy_reg(hw, 0x20DD, 0x249A);
1746 /* ABS DC correction to 95.9% */
1747 hw->phy.ops.write_phy_reg(hw, 0x20DE, 0x00D3);
1748 /* BG temp curve trim */
1749 hw->phy.ops.write_phy_reg(hw, 0x28B4, 0x04CE);
1750 /* Increasing ADC OPAMP stage 1 currents to max */
1751 hw->phy.ops.write_phy_reg(hw, 0x2F70, 0x29E4);
1752 /* Force 1000 ( required for enabling PHY regs configuration) */
1753 hw->phy.ops.write_phy_reg(hw, 0x0000, 0x0140);
1754 /* Set upd_freq to 6 */
1755 hw->phy.ops.write_phy_reg(hw, 0x1F30, 0x1606);
1756 /* Disable NPDFE */
1757 hw->phy.ops.write_phy_reg(hw, 0x1F31, 0xB814);
1758 /* Disable adaptive fixed FFE (Default) */
1759 hw->phy.ops.write_phy_reg(hw, 0x1F35, 0x002A);
1760 /* Enable FFE hysteresis */
1761 hw->phy.ops.write_phy_reg(hw, 0x1F3E, 0x0067);
1762 /* Fixed FFE for short cable lengths */
1763 hw->phy.ops.write_phy_reg(hw, 0x1F54, 0x0065);
1764 /* Fixed FFE for medium cable lengths */
1765 hw->phy.ops.write_phy_reg(hw, 0x1F55, 0x002A);
1766 /* Fixed FFE for long cable lengths */
1767 hw->phy.ops.write_phy_reg(hw, 0x1F56, 0x002A);
1768 /* Enable Adaptive Clip Threshold */
1769 hw->phy.ops.write_phy_reg(hw, 0x1F72, 0x3FB0);
1770 /* AHT reset limit to 1 */
1771 hw->phy.ops.write_phy_reg(hw, 0x1F76, 0xC0FF);
1772 /* Set AHT master delay to 127 msec */
1773 hw->phy.ops.write_phy_reg(hw, 0x1F77, 0x1DEC);
1774 /* Set scan bits for AHT */
1775 hw->phy.ops.write_phy_reg(hw, 0x1F78, 0xF9EF);
1776 /* Set AHT Preset bits */
1777 hw->phy.ops.write_phy_reg(hw, 0x1F79, 0x0210);
1778 /* Change integ_factor of channel A to 3 */
1779 hw->phy.ops.write_phy_reg(hw, 0x1895, 0x0003);
1780 /* Change prop_factor of channels BCD to 8 */
1781 hw->phy.ops.write_phy_reg(hw, 0x1796, 0x0008);
1782 /* Change cg_icount + enable integbp for channels BCD */
1783 hw->phy.ops.write_phy_reg(hw, 0x1798, 0xD008);
1784 /*
1785 * Change cg_icount + enable integbp + change prop_factor_master
1786 * to 8 for channel A
1787 */
1788 hw->phy.ops.write_phy_reg(hw, 0x1898, 0xD918);
1789 /* Disable AHT in Slave mode on channel A */
1790 hw->phy.ops.write_phy_reg(hw, 0x187A, 0x0800);
1791 /*
1792 * Enable LPLU and disable AN to 1000 in non-D0a states,
1793 * Enable SPD+B2B
1794 */
1795 hw->phy.ops.write_phy_reg(hw, 0x0019, 0x008D);
1796 /* Enable restart AN on an1000_dis change */
1797 hw->phy.ops.write_phy_reg(hw, 0x001B, 0x2080);
1798 /* Enable wh_fifo read clock in 10/100 modes */
1799 hw->phy.ops.write_phy_reg(hw, 0x0014, 0x0045);
1800 /* Restart AN, Speed selection is 1000 */
1801 hw->phy.ops.write_phy_reg(hw, 0x0000, 0x1340);
1802
1803 return 0;
1804}
1805
Linux kernel - Deliverables
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