Commit | Line | Data |
---|---|---|
9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/if_ether.h> | |
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000_mac.h" | |
32 | #include "e1000_phy.h" | |
33 | ||
9d5c8243 AK |
34 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); |
35 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
36 | u16 *phy_ctrl); | |
37 | static s32 igb_wait_autoneg(struct e1000_hw *hw); | |
38 | ||
39 | /* Cable length tables */ | |
40 | static const u16 e1000_m88_cable_length_table[] = | |
41 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
2553bb26 AD |
42 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
43 | (sizeof(e1000_m88_cable_length_table) / \ | |
44 | sizeof(e1000_m88_cable_length_table[0])) | |
9d5c8243 AK |
45 | |
46 | static const u16 e1000_igp_2_cable_length_table[] = | |
47 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, | |
48 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
49 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
50 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
51 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
52 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
53 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
54 | 104, 109, 114, 118, 121, 124}; | |
55 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ | |
56 | (sizeof(e1000_igp_2_cable_length_table) / \ | |
57 | sizeof(e1000_igp_2_cable_length_table[0])) | |
58 | ||
59 | /** | |
733596be | 60 | * igb_check_reset_block - Check if PHY reset is blocked |
9d5c8243 AK |
61 | * @hw: pointer to the HW structure |
62 | * | |
63 | * Read the PHY management control register and check whether a PHY reset | |
64 | * is blocked. If a reset is not blocked return 0, otherwise | |
65 | * return E1000_BLK_PHY_RESET (12). | |
66 | **/ | |
67 | s32 igb_check_reset_block(struct e1000_hw *hw) | |
68 | { | |
69 | u32 manc; | |
70 | ||
71 | manc = rd32(E1000_MANC); | |
72 | ||
73 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
74 | E1000_BLK_PHY_RESET : 0; | |
75 | } | |
76 | ||
77 | /** | |
733596be | 78 | * igb_get_phy_id - Retrieve the PHY ID and revision |
9d5c8243 AK |
79 | * @hw: pointer to the HW structure |
80 | * | |
81 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
82 | * revision in the hardware structure. | |
83 | **/ | |
84 | s32 igb_get_phy_id(struct e1000_hw *hw) | |
85 | { | |
86 | struct e1000_phy_info *phy = &hw->phy; | |
87 | s32 ret_val = 0; | |
88 | u16 phy_id; | |
89 | ||
a8d2a0c2 | 90 | ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); |
9d5c8243 AK |
91 | if (ret_val) |
92 | goto out; | |
93 | ||
94 | phy->id = (u32)(phy_id << 16); | |
95 | udelay(20); | |
a8d2a0c2 | 96 | ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); |
9d5c8243 AK |
97 | if (ret_val) |
98 | goto out; | |
99 | ||
100 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | |
101 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
102 | ||
103 | out: | |
104 | return ret_val; | |
105 | } | |
106 | ||
107 | /** | |
733596be | 108 | * igb_phy_reset_dsp - Reset PHY DSP |
9d5c8243 AK |
109 | * @hw: pointer to the HW structure |
110 | * | |
111 | * Reset the digital signal processor. | |
112 | **/ | |
113 | static s32 igb_phy_reset_dsp(struct e1000_hw *hw) | |
114 | { | |
2553bb26 AD |
115 | s32 ret_val = 0; |
116 | ||
117 | if (!(hw->phy.ops.write_reg)) | |
118 | goto out; | |
9d5c8243 | 119 | |
a8d2a0c2 | 120 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
9d5c8243 AK |
121 | if (ret_val) |
122 | goto out; | |
123 | ||
a8d2a0c2 | 124 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); |
9d5c8243 AK |
125 | |
126 | out: | |
127 | return ret_val; | |
128 | } | |
129 | ||
130 | /** | |
733596be | 131 | * igb_read_phy_reg_mdic - Read MDI control register |
9d5c8243 AK |
132 | * @hw: pointer to the HW structure |
133 | * @offset: register offset to be read | |
134 | * @data: pointer to the read data | |
135 | * | |
136 | * Reads the MDI control regsiter in the PHY at offset and stores the | |
137 | * information read to data. | |
138 | **/ | |
bb2ac47b | 139 | s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
9d5c8243 AK |
140 | { |
141 | struct e1000_phy_info *phy = &hw->phy; | |
142 | u32 i, mdic = 0; | |
143 | s32 ret_val = 0; | |
144 | ||
145 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 146 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
147 | ret_val = -E1000_ERR_PARAM; |
148 | goto out; | |
149 | } | |
150 | ||
151 | /* | |
152 | * Set up Op-code, Phy Address, and register offset in the MDI | |
153 | * Control register. The MAC will take care of interfacing with the | |
154 | * PHY to retrieve the desired data. | |
155 | */ | |
156 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
157 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
158 | (E1000_MDIC_OP_READ)); | |
159 | ||
160 | wr32(E1000_MDIC, mdic); | |
161 | ||
162 | /* | |
163 | * Poll the ready bit to see if the MDI read completed | |
164 | * Increasing the time out as testing showed failures with | |
165 | * the lower time out | |
166 | */ | |
167 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
168 | udelay(50); | |
169 | mdic = rd32(E1000_MDIC); | |
170 | if (mdic & E1000_MDIC_READY) | |
171 | break; | |
172 | } | |
173 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 174 | hw_dbg("MDI Read did not complete\n"); |
9d5c8243 AK |
175 | ret_val = -E1000_ERR_PHY; |
176 | goto out; | |
177 | } | |
178 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 179 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
180 | ret_val = -E1000_ERR_PHY; |
181 | goto out; | |
182 | } | |
183 | *data = (u16) mdic; | |
184 | ||
185 | out: | |
186 | return ret_val; | |
187 | } | |
188 | ||
189 | /** | |
733596be | 190 | * igb_write_phy_reg_mdic - Write MDI control register |
9d5c8243 AK |
191 | * @hw: pointer to the HW structure |
192 | * @offset: register offset to write to | |
193 | * @data: data to write to register at offset | |
194 | * | |
195 | * Writes data to MDI control register in the PHY at offset. | |
196 | **/ | |
bb2ac47b | 197 | s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
9d5c8243 AK |
198 | { |
199 | struct e1000_phy_info *phy = &hw->phy; | |
200 | u32 i, mdic = 0; | |
201 | s32 ret_val = 0; | |
202 | ||
203 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 204 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
205 | ret_val = -E1000_ERR_PARAM; |
206 | goto out; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Set up Op-code, Phy Address, and register offset in the MDI | |
211 | * Control register. The MAC will take care of interfacing with the | |
212 | * PHY to retrieve the desired data. | |
213 | */ | |
214 | mdic = (((u32)data) | | |
215 | (offset << E1000_MDIC_REG_SHIFT) | | |
216 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
217 | (E1000_MDIC_OP_WRITE)); | |
218 | ||
219 | wr32(E1000_MDIC, mdic); | |
220 | ||
221 | /* | |
222 | * Poll the ready bit to see if the MDI read completed | |
223 | * Increasing the time out as testing showed failures with | |
224 | * the lower time out | |
225 | */ | |
226 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
227 | udelay(50); | |
228 | mdic = rd32(E1000_MDIC); | |
229 | if (mdic & E1000_MDIC_READY) | |
230 | break; | |
231 | } | |
232 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 233 | hw_dbg("MDI Write did not complete\n"); |
9d5c8243 AK |
234 | ret_val = -E1000_ERR_PHY; |
235 | goto out; | |
236 | } | |
237 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 238 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
239 | ret_val = -E1000_ERR_PHY; |
240 | goto out; | |
241 | } | |
242 | ||
243 | out: | |
244 | return ret_val; | |
245 | } | |
246 | ||
bf6f7a92 AD |
247 | /** |
248 | * igb_read_phy_reg_i2c - Read PHY register using i2c | |
249 | * @hw: pointer to the HW structure | |
250 | * @offset: register offset to be read | |
251 | * @data: pointer to the read data | |
252 | * | |
253 | * Reads the PHY register at offset using the i2c interface and stores the | |
254 | * retrieved information in data. | |
255 | **/ | |
256 | s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) | |
257 | { | |
258 | struct e1000_phy_info *phy = &hw->phy; | |
259 | u32 i, i2ccmd = 0; | |
260 | ||
261 | ||
262 | /* | |
263 | * Set up Op-code, Phy Address, and register address in the I2CCMD | |
264 | * register. The MAC will take care of interfacing with the | |
265 | * PHY to retrieve the desired data. | |
266 | */ | |
267 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
268 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | | |
269 | (E1000_I2CCMD_OPCODE_READ)); | |
270 | ||
271 | wr32(E1000_I2CCMD, i2ccmd); | |
272 | ||
273 | /* Poll the ready bit to see if the I2C read completed */ | |
274 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
275 | udelay(50); | |
276 | i2ccmd = rd32(E1000_I2CCMD); | |
277 | if (i2ccmd & E1000_I2CCMD_READY) | |
278 | break; | |
279 | } | |
280 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
281 | hw_dbg("I2CCMD Read did not complete\n"); | |
282 | return -E1000_ERR_PHY; | |
283 | } | |
284 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
285 | hw_dbg("I2CCMD Error bit set\n"); | |
286 | return -E1000_ERR_PHY; | |
287 | } | |
288 | ||
289 | /* Need to byte-swap the 16-bit value. */ | |
290 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | /** | |
296 | * igb_write_phy_reg_i2c - Write PHY register using i2c | |
297 | * @hw: pointer to the HW structure | |
298 | * @offset: register offset to write to | |
299 | * @data: data to write at register offset | |
300 | * | |
301 | * Writes the data to PHY register at the offset using the i2c interface. | |
302 | **/ | |
303 | s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) | |
304 | { | |
305 | struct e1000_phy_info *phy = &hw->phy; | |
306 | u32 i, i2ccmd = 0; | |
307 | u16 phy_data_swapped; | |
308 | ||
309 | ||
310 | /* Swap the data bytes for the I2C interface */ | |
311 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); | |
312 | ||
313 | /* | |
314 | * Set up Op-code, Phy Address, and register address in the I2CCMD | |
315 | * register. The MAC will take care of interfacing with the | |
316 | * PHY to retrieve the desired data. | |
317 | */ | |
318 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
319 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | | |
320 | E1000_I2CCMD_OPCODE_WRITE | | |
321 | phy_data_swapped); | |
322 | ||
323 | wr32(E1000_I2CCMD, i2ccmd); | |
324 | ||
325 | /* Poll the ready bit to see if the I2C read completed */ | |
326 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
327 | udelay(50); | |
328 | i2ccmd = rd32(E1000_I2CCMD); | |
329 | if (i2ccmd & E1000_I2CCMD_READY) | |
330 | break; | |
331 | } | |
332 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
333 | hw_dbg("I2CCMD Write did not complete\n"); | |
334 | return -E1000_ERR_PHY; | |
335 | } | |
336 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
337 | hw_dbg("I2CCMD Error bit set\n"); | |
338 | return -E1000_ERR_PHY; | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
9d5c8243 | 344 | /** |
733596be | 345 | * igb_read_phy_reg_igp - Read igp PHY register |
9d5c8243 AK |
346 | * @hw: pointer to the HW structure |
347 | * @offset: register offset to be read | |
348 | * @data: pointer to the read data | |
349 | * | |
350 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
351 | * and storing the retrieved information in data. Release any acquired | |
352 | * semaphores before exiting. | |
353 | **/ | |
354 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
355 | { | |
a8d2a0c2 AD |
356 | s32 ret_val = 0; |
357 | ||
358 | if (!(hw->phy.ops.acquire)) | |
359 | goto out; | |
9d5c8243 | 360 | |
a8d2a0c2 | 361 | ret_val = hw->phy.ops.acquire(hw); |
9d5c8243 AK |
362 | if (ret_val) |
363 | goto out; | |
364 | ||
365 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
366 | ret_val = igb_write_phy_reg_mdic(hw, | |
367 | IGP01E1000_PHY_PAGE_SELECT, | |
368 | (u16)offset); | |
369 | if (ret_val) { | |
a8d2a0c2 | 370 | hw->phy.ops.release(hw); |
9d5c8243 AK |
371 | goto out; |
372 | } | |
373 | } | |
374 | ||
a8d2a0c2 AD |
375 | ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
376 | data); | |
9d5c8243 | 377 | |
a8d2a0c2 | 378 | hw->phy.ops.release(hw); |
9d5c8243 AK |
379 | |
380 | out: | |
381 | return ret_val; | |
382 | } | |
383 | ||
384 | /** | |
733596be | 385 | * igb_write_phy_reg_igp - Write igp PHY register |
9d5c8243 AK |
386 | * @hw: pointer to the HW structure |
387 | * @offset: register offset to write to | |
388 | * @data: data to write at register offset | |
389 | * | |
390 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
391 | * at the offset. Release any acquired semaphores before exiting. | |
392 | **/ | |
393 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
394 | { | |
a8d2a0c2 | 395 | s32 ret_val = 0; |
9d5c8243 | 396 | |
a8d2a0c2 AD |
397 | if (!(hw->phy.ops.acquire)) |
398 | goto out; | |
399 | ||
400 | ret_val = hw->phy.ops.acquire(hw); | |
9d5c8243 AK |
401 | if (ret_val) |
402 | goto out; | |
403 | ||
404 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
405 | ret_val = igb_write_phy_reg_mdic(hw, | |
406 | IGP01E1000_PHY_PAGE_SELECT, | |
407 | (u16)offset); | |
408 | if (ret_val) { | |
a8d2a0c2 | 409 | hw->phy.ops.release(hw); |
9d5c8243 AK |
410 | goto out; |
411 | } | |
412 | } | |
413 | ||
a8d2a0c2 | 414 | ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
9d5c8243 AK |
415 | data); |
416 | ||
a8d2a0c2 | 417 | hw->phy.ops.release(hw); |
9d5c8243 AK |
418 | |
419 | out: | |
420 | return ret_val; | |
421 | } | |
422 | ||
2909c3f7 AD |
423 | /** |
424 | * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link | |
425 | * @hw: pointer to the HW structure | |
426 | * | |
427 | * Sets up Carrier-sense on Transmit and downshift values. | |
428 | **/ | |
429 | s32 igb_copper_link_setup_82580(struct e1000_hw *hw) | |
430 | { | |
431 | struct e1000_phy_info *phy = &hw->phy; | |
432 | s32 ret_val; | |
433 | u16 phy_data; | |
434 | ||
435 | ||
436 | if (phy->reset_disable) { | |
437 | ret_val = 0; | |
438 | goto out; | |
439 | } | |
440 | ||
441 | if (phy->type == e1000_phy_82580) { | |
442 | ret_val = hw->phy.ops.reset(hw); | |
443 | if (ret_val) { | |
444 | hw_dbg("Error resetting the PHY.\n"); | |
445 | goto out; | |
446 | } | |
447 | } | |
448 | ||
449 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
450 | ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); | |
451 | if (ret_val) | |
452 | goto out; | |
453 | ||
454 | phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; | |
455 | ||
456 | /* Enable downshift */ | |
457 | phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; | |
458 | ||
459 | ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); | |
2909c3f7 AD |
460 | |
461 | out: | |
462 | return ret_val; | |
463 | } | |
464 | ||
9d5c8243 | 465 | /** |
733596be | 466 | * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link |
9d5c8243 AK |
467 | * @hw: pointer to the HW structure |
468 | * | |
469 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
470 | * and downshift values are set also. | |
471 | **/ | |
472 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw) | |
473 | { | |
474 | struct e1000_phy_info *phy = &hw->phy; | |
475 | s32 ret_val; | |
476 | u16 phy_data; | |
477 | ||
478 | if (phy->reset_disable) { | |
479 | ret_val = 0; | |
480 | goto out; | |
481 | } | |
482 | ||
483 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
a8d2a0c2 | 484 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
485 | if (ret_val) |
486 | goto out; | |
487 | ||
488 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
489 | ||
490 | /* | |
491 | * Options: | |
492 | * MDI/MDI-X = 0 (default) | |
493 | * 0 - Auto for all speeds | |
494 | * 1 - MDI mode | |
495 | * 2 - MDI-X mode | |
496 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
497 | */ | |
498 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
499 | ||
500 | switch (phy->mdix) { | |
501 | case 1: | |
502 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
503 | break; | |
504 | case 2: | |
505 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
506 | break; | |
507 | case 3: | |
508 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
509 | break; | |
510 | case 0: | |
511 | default: | |
512 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
513 | break; | |
514 | } | |
515 | ||
516 | /* | |
517 | * Options: | |
518 | * disable_polarity_correction = 0 (default) | |
519 | * Automatic Correction for Reversed Cable Polarity | |
520 | * 0 - Disabled | |
521 | * 1 - Enabled | |
522 | */ | |
523 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
524 | if (phy->disable_polarity_correction == 1) | |
525 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
526 | ||
a8d2a0c2 | 527 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
528 | if (ret_val) |
529 | goto out; | |
530 | ||
531 | if (phy->revision < E1000_REVISION_4) { | |
532 | /* | |
533 | * Force TX_CLK in the Extended PHY Specific Control Register | |
534 | * to 25MHz clock. | |
535 | */ | |
a8d2a0c2 | 536 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
537 | &phy_data); |
538 | if (ret_val) | |
539 | goto out; | |
540 | ||
541 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
542 | ||
543 | if ((phy->revision == E1000_REVISION_2) && | |
544 | (phy->id == M88E1111_I_PHY_ID)) { | |
545 | /* 82573L PHY - set the downshift counter to 5x. */ | |
546 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
547 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
548 | } else { | |
549 | /* Configure Master and Slave downshift values */ | |
550 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
551 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
552 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
553 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
554 | } | |
a8d2a0c2 | 555 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
556 | phy_data); |
557 | if (ret_val) | |
558 | goto out; | |
559 | } | |
560 | ||
561 | /* Commit the changes. */ | |
562 | ret_val = igb_phy_sw_reset(hw); | |
563 | if (ret_val) { | |
652fff32 | 564 | hw_dbg("Error committing the PHY changes\n"); |
9d5c8243 AK |
565 | goto out; |
566 | } | |
567 | ||
568 | out: | |
569 | return ret_val; | |
570 | } | |
571 | ||
572 | /** | |
733596be | 573 | * igb_copper_link_setup_igp - Setup igp PHY's for copper link |
9d5c8243 AK |
574 | * @hw: pointer to the HW structure |
575 | * | |
576 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
577 | * igp PHY's. | |
578 | **/ | |
579 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw) | |
580 | { | |
581 | struct e1000_phy_info *phy = &hw->phy; | |
582 | s32 ret_val; | |
583 | u16 data; | |
584 | ||
585 | if (phy->reset_disable) { | |
586 | ret_val = 0; | |
587 | goto out; | |
588 | } | |
589 | ||
a8d2a0c2 | 590 | ret_val = phy->ops.reset(hw); |
9d5c8243 | 591 | if (ret_val) { |
652fff32 | 592 | hw_dbg("Error resetting the PHY.\n"); |
9d5c8243 AK |
593 | goto out; |
594 | } | |
595 | ||
a6a60569 AD |
596 | /* |
597 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
598 | * timeout issues when LFS is enabled. | |
599 | */ | |
600 | msleep(100); | |
9d5c8243 AK |
601 | |
602 | /* | |
603 | * The NVM settings will configure LPLU in D3 for | |
604 | * non-IGP1 PHYs. | |
605 | */ | |
606 | if (phy->type == e1000_phy_igp) { | |
607 | /* disable lplu d3 during driver init */ | |
a8d2a0c2 AD |
608 | if (phy->ops.set_d3_lplu_state) |
609 | ret_val = phy->ops.set_d3_lplu_state(hw, false); | |
9d5c8243 | 610 | if (ret_val) { |
652fff32 | 611 | hw_dbg("Error Disabling LPLU D3\n"); |
9d5c8243 AK |
612 | goto out; |
613 | } | |
614 | } | |
615 | ||
616 | /* disable lplu d0 during driver init */ | |
a8d2a0c2 | 617 | ret_val = phy->ops.set_d0_lplu_state(hw, false); |
9d5c8243 | 618 | if (ret_val) { |
652fff32 | 619 | hw_dbg("Error Disabling LPLU D0\n"); |
9d5c8243 AK |
620 | goto out; |
621 | } | |
622 | /* Configure mdi-mdix settings */ | |
a8d2a0c2 | 623 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
9d5c8243 AK |
624 | if (ret_val) |
625 | goto out; | |
626 | ||
627 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
628 | ||
629 | switch (phy->mdix) { | |
630 | case 1: | |
631 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
632 | break; | |
633 | case 2: | |
634 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
635 | break; | |
636 | case 0: | |
637 | default: | |
638 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
639 | break; | |
640 | } | |
a8d2a0c2 | 641 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); |
9d5c8243 AK |
642 | if (ret_val) |
643 | goto out; | |
644 | ||
645 | /* set auto-master slave resolution settings */ | |
646 | if (hw->mac.autoneg) { | |
647 | /* | |
648 | * when autonegotiation advertisement is only 1000Mbps then we | |
649 | * should disable SmartSpeed and enable Auto MasterSlave | |
650 | * resolution as hardware default. | |
651 | */ | |
652 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { | |
653 | /* Disable SmartSpeed */ | |
a8d2a0c2 AD |
654 | ret_val = phy->ops.read_reg(hw, |
655 | IGP01E1000_PHY_PORT_CONFIG, | |
656 | &data); | |
9d5c8243 AK |
657 | if (ret_val) |
658 | goto out; | |
659 | ||
660 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 661 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
662 | IGP01E1000_PHY_PORT_CONFIG, |
663 | data); | |
664 | if (ret_val) | |
665 | goto out; | |
666 | ||
667 | /* Set auto Master/Slave resolution process */ | |
a8d2a0c2 | 668 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
669 | if (ret_val) |
670 | goto out; | |
671 | ||
672 | data &= ~CR_1000T_MS_ENABLE; | |
a8d2a0c2 | 673 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
674 | if (ret_val) |
675 | goto out; | |
676 | } | |
677 | ||
a8d2a0c2 | 678 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
679 | if (ret_val) |
680 | goto out; | |
681 | ||
682 | /* load defaults for future use */ | |
683 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
684 | ((data & CR_1000T_MS_VALUE) ? | |
685 | e1000_ms_force_master : | |
686 | e1000_ms_force_slave) : | |
687 | e1000_ms_auto; | |
688 | ||
689 | switch (phy->ms_type) { | |
690 | case e1000_ms_force_master: | |
691 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
692 | break; | |
693 | case e1000_ms_force_slave: | |
694 | data |= CR_1000T_MS_ENABLE; | |
695 | data &= ~(CR_1000T_MS_VALUE); | |
696 | break; | |
697 | case e1000_ms_auto: | |
698 | data &= ~CR_1000T_MS_ENABLE; | |
699 | default: | |
700 | break; | |
701 | } | |
a8d2a0c2 | 702 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
703 | if (ret_val) |
704 | goto out; | |
705 | } | |
706 | ||
707 | out: | |
708 | return ret_val; | |
709 | } | |
710 | ||
711 | /** | |
733596be | 712 | * igb_copper_link_autoneg - Setup/Enable autoneg for copper link |
9d5c8243 AK |
713 | * @hw: pointer to the HW structure |
714 | * | |
715 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
716 | * configure to advertise the full capability. Setup the PHY to autoneg | |
717 | * and restart the negotiation process between the link partner. If | |
718 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. | |
719 | **/ | |
81fadd81 | 720 | static s32 igb_copper_link_autoneg(struct e1000_hw *hw) |
9d5c8243 AK |
721 | { |
722 | struct e1000_phy_info *phy = &hw->phy; | |
723 | s32 ret_val; | |
724 | u16 phy_ctrl; | |
725 | ||
726 | /* | |
727 | * Perform some bounds checking on the autoneg advertisement | |
728 | * parameter. | |
729 | */ | |
730 | phy->autoneg_advertised &= phy->autoneg_mask; | |
731 | ||
732 | /* | |
733 | * If autoneg_advertised is zero, we assume it was not defaulted | |
734 | * by the calling code so we set to advertise full capability. | |
735 | */ | |
736 | if (phy->autoneg_advertised == 0) | |
737 | phy->autoneg_advertised = phy->autoneg_mask; | |
738 | ||
652fff32 | 739 | hw_dbg("Reconfiguring auto-neg advertisement params\n"); |
9d5c8243 AK |
740 | ret_val = igb_phy_setup_autoneg(hw); |
741 | if (ret_val) { | |
652fff32 | 742 | hw_dbg("Error Setting up Auto-Negotiation\n"); |
9d5c8243 AK |
743 | goto out; |
744 | } | |
652fff32 | 745 | hw_dbg("Restarting Auto-Neg\n"); |
9d5c8243 AK |
746 | |
747 | /* | |
748 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
749 | * the Auto Neg Restart bit in the PHY control register. | |
750 | */ | |
a8d2a0c2 | 751 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
752 | if (ret_val) |
753 | goto out; | |
754 | ||
755 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
a8d2a0c2 | 756 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
757 | if (ret_val) |
758 | goto out; | |
759 | ||
760 | /* | |
761 | * Does the user want to wait for Auto-Neg to complete here, or | |
762 | * check at a later time (for example, callback routine). | |
763 | */ | |
764 | if (phy->autoneg_wait_to_complete) { | |
765 | ret_val = igb_wait_autoneg(hw); | |
766 | if (ret_val) { | |
652fff32 AK |
767 | hw_dbg("Error while waiting for " |
768 | "autoneg to complete\n"); | |
9d5c8243 AK |
769 | goto out; |
770 | } | |
771 | } | |
772 | ||
773 | hw->mac.get_link_status = true; | |
774 | ||
775 | out: | |
776 | return ret_val; | |
777 | } | |
778 | ||
779 | /** | |
733596be | 780 | * igb_phy_setup_autoneg - Configure PHY for auto-negotiation |
9d5c8243 AK |
781 | * @hw: pointer to the HW structure |
782 | * | |
783 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
784 | * register and if the PHY is already setup for auto-negotiation, then | |
785 | * return successful. Otherwise, setup advertisement and flow control to | |
786 | * the appropriate values for the wanted auto-negotiation. | |
787 | **/ | |
788 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) | |
789 | { | |
790 | struct e1000_phy_info *phy = &hw->phy; | |
791 | s32 ret_val; | |
792 | u16 mii_autoneg_adv_reg; | |
793 | u16 mii_1000t_ctrl_reg = 0; | |
794 | ||
795 | phy->autoneg_advertised &= phy->autoneg_mask; | |
796 | ||
797 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
a8d2a0c2 | 798 | ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
9d5c8243 AK |
799 | if (ret_val) |
800 | goto out; | |
801 | ||
802 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
803 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
a8d2a0c2 | 804 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, |
9d5c8243 AK |
805 | &mii_1000t_ctrl_reg); |
806 | if (ret_val) | |
807 | goto out; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Need to parse both autoneg_advertised and fc and set up | |
812 | * the appropriate PHY registers. First we will parse for | |
813 | * autoneg_advertised software override. Since we can advertise | |
814 | * a plethora of combinations, we need to check each bit | |
815 | * individually. | |
816 | */ | |
817 | ||
818 | /* | |
819 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
820 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
821 | * the 1000Base-T Control Register (Address 9). | |
822 | */ | |
823 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
824 | NWAY_AR_100TX_HD_CAPS | | |
825 | NWAY_AR_10T_FD_CAPS | | |
826 | NWAY_AR_10T_HD_CAPS); | |
827 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
828 | ||
652fff32 | 829 | hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
9d5c8243 AK |
830 | |
831 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
832 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
652fff32 | 833 | hw_dbg("Advertise 10mb Half duplex\n"); |
9d5c8243 AK |
834 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
835 | } | |
836 | ||
837 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
838 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
652fff32 | 839 | hw_dbg("Advertise 10mb Full duplex\n"); |
9d5c8243 AK |
840 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
841 | } | |
842 | ||
843 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
844 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
652fff32 | 845 | hw_dbg("Advertise 100mb Half duplex\n"); |
9d5c8243 AK |
846 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
847 | } | |
848 | ||
849 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
850 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
652fff32 | 851 | hw_dbg("Advertise 100mb Full duplex\n"); |
9d5c8243 AK |
852 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
853 | } | |
854 | ||
855 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
856 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
652fff32 | 857 | hw_dbg("Advertise 1000mb Half duplex request denied!\n"); |
9d5c8243 AK |
858 | |
859 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
860 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
652fff32 | 861 | hw_dbg("Advertise 1000mb Full duplex\n"); |
9d5c8243 AK |
862 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
863 | } | |
864 | ||
865 | /* | |
866 | * Check for a software override of the flow control settings, and | |
867 | * setup the PHY advertisement registers accordingly. If | |
868 | * auto-negotiation is enabled, then software will have to set the | |
869 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
870 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
871 | * negotiation. | |
872 | * | |
873 | * The possible values of the "fc" parameter are: | |
874 | * 0: Flow control is completely disabled | |
875 | * 1: Rx flow control is enabled (we can receive pause frames | |
876 | * but not send pause frames). | |
877 | * 2: Tx flow control is enabled (we can send pause frames | |
878 | * but we do not support receiving pause frames). | |
879 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
880 | * other: No software override. The flow control configuration | |
881 | * in the EEPROM is used. | |
882 | */ | |
0cce119a | 883 | switch (hw->fc.current_mode) { |
9d5c8243 AK |
884 | case e1000_fc_none: |
885 | /* | |
886 | * Flow control (RX & TX) is completely disabled by a | |
887 | * software over-ride. | |
888 | */ | |
889 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
890 | break; | |
891 | case e1000_fc_rx_pause: | |
892 | /* | |
893 | * RX Flow control is enabled, and TX Flow control is | |
894 | * disabled, by a software over-ride. | |
895 | * | |
896 | * Since there really isn't a way to advertise that we are | |
897 | * capable of RX Pause ONLY, we will advertise that we | |
898 | * support both symmetric and asymmetric RX PAUSE. Later | |
899 | * (in e1000_config_fc_after_link_up) we will disable the | |
900 | * hw's ability to send PAUSE frames. | |
901 | */ | |
902 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
903 | break; | |
904 | case e1000_fc_tx_pause: | |
905 | /* | |
906 | * TX Flow control is enabled, and RX Flow control is | |
907 | * disabled, by a software over-ride. | |
908 | */ | |
909 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
910 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
911 | break; | |
912 | case e1000_fc_full: | |
913 | /* | |
914 | * Flow control (both RX and TX) is enabled by a software | |
915 | * over-ride. | |
916 | */ | |
917 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
918 | break; | |
919 | default: | |
652fff32 | 920 | hw_dbg("Flow control param set incorrectly\n"); |
9d5c8243 AK |
921 | ret_val = -E1000_ERR_CONFIG; |
922 | goto out; | |
923 | } | |
924 | ||
a8d2a0c2 | 925 | ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
9d5c8243 AK |
926 | if (ret_val) |
927 | goto out; | |
928 | ||
652fff32 | 929 | hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
9d5c8243 AK |
930 | |
931 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
a8d2a0c2 AD |
932 | ret_val = phy->ops.write_reg(hw, |
933 | PHY_1000T_CTRL, | |
934 | mii_1000t_ctrl_reg); | |
9d5c8243 AK |
935 | if (ret_val) |
936 | goto out; | |
937 | } | |
938 | ||
939 | out: | |
940 | return ret_val; | |
941 | } | |
942 | ||
81fadd81 AD |
943 | /** |
944 | * igb_setup_copper_link - Configure copper link settings | |
945 | * @hw: pointer to the HW structure | |
946 | * | |
947 | * Calls the appropriate function to configure the link for auto-neg or forced | |
948 | * speed and duplex. Then we check for link, once link is established calls | |
949 | * to configure collision distance and flow control are called. If link is | |
950 | * not established, we return -E1000_ERR_PHY (-2). | |
951 | **/ | |
952 | s32 igb_setup_copper_link(struct e1000_hw *hw) | |
953 | { | |
954 | s32 ret_val; | |
955 | bool link; | |
956 | ||
957 | ||
958 | if (hw->mac.autoneg) { | |
959 | /* | |
960 | * Setup autoneg and flow control advertisement and perform | |
961 | * autonegotiation. | |
962 | */ | |
963 | ret_val = igb_copper_link_autoneg(hw); | |
964 | if (ret_val) | |
965 | goto out; | |
966 | } else { | |
967 | /* | |
968 | * PHY will be set to 10H, 10F, 100H or 100F | |
969 | * depending on user settings. | |
970 | */ | |
971 | hw_dbg("Forcing Speed and Duplex\n"); | |
972 | ret_val = hw->phy.ops.force_speed_duplex(hw); | |
973 | if (ret_val) { | |
974 | hw_dbg("Error Forcing Speed and Duplex\n"); | |
975 | goto out; | |
976 | } | |
977 | } | |
978 | ||
979 | /* | |
980 | * Check link status. Wait up to 100 microseconds for link to become | |
981 | * valid. | |
982 | */ | |
983 | ret_val = igb_phy_has_link(hw, | |
984 | COPPER_LINK_UP_LIMIT, | |
985 | 10, | |
986 | &link); | |
987 | if (ret_val) | |
988 | goto out; | |
989 | ||
990 | if (link) { | |
991 | hw_dbg("Valid link established!!!\n"); | |
992 | igb_config_collision_dist(hw); | |
993 | ret_val = igb_config_fc_after_link_up(hw); | |
994 | } else { | |
995 | hw_dbg("Unable to establish link!!!\n"); | |
996 | } | |
997 | ||
998 | out: | |
999 | return ret_val; | |
1000 | } | |
1001 | ||
9d5c8243 | 1002 | /** |
733596be | 1003 | * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
9d5c8243 AK |
1004 | * @hw: pointer to the HW structure |
1005 | * | |
1006 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1007 | * auto-crossover to force MDI manually. Waits for link and returns | |
1008 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1009 | **/ | |
1010 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1011 | { | |
1012 | struct e1000_phy_info *phy = &hw->phy; | |
1013 | s32 ret_val; | |
1014 | u16 phy_data; | |
1015 | bool link; | |
1016 | ||
a8d2a0c2 | 1017 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
1018 | if (ret_val) |
1019 | goto out; | |
1020 | ||
1021 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
1022 | ||
a8d2a0c2 | 1023 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
1024 | if (ret_val) |
1025 | goto out; | |
1026 | ||
1027 | /* | |
1028 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
1029 | * forced whenever speed and duplex are forced. | |
1030 | */ | |
a8d2a0c2 | 1031 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
9d5c8243 AK |
1032 | if (ret_val) |
1033 | goto out; | |
1034 | ||
1035 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1036 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1037 | ||
a8d2a0c2 | 1038 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
9d5c8243 AK |
1039 | if (ret_val) |
1040 | goto out; | |
1041 | ||
652fff32 | 1042 | hw_dbg("IGP PSCR: %X\n", phy_data); |
9d5c8243 AK |
1043 | |
1044 | udelay(1); | |
1045 | ||
1046 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 1047 | hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
9d5c8243 AK |
1048 | |
1049 | ret_val = igb_phy_has_link(hw, | |
1050 | PHY_FORCE_LIMIT, | |
1051 | 100000, | |
1052 | &link); | |
1053 | if (ret_val) | |
1054 | goto out; | |
1055 | ||
1056 | if (!link) | |
652fff32 | 1057 | hw_dbg("Link taking longer than expected.\n"); |
9d5c8243 AK |
1058 | |
1059 | /* Try once more */ | |
1060 | ret_val = igb_phy_has_link(hw, | |
1061 | PHY_FORCE_LIMIT, | |
1062 | 100000, | |
1063 | &link); | |
1064 | if (ret_val) | |
1065 | goto out; | |
1066 | } | |
1067 | ||
1068 | out: | |
1069 | return ret_val; | |
1070 | } | |
1071 | ||
1072 | /** | |
733596be | 1073 | * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
9d5c8243 AK |
1074 | * @hw: pointer to the HW structure |
1075 | * | |
1076 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1077 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1078 | * changes. If time expires while waiting for link up, we reset the DSP. | |
1079 | * After reset, TX_CLK and CRS on TX must be set. Return successful upon | |
1080 | * successful completion, else return corresponding error code. | |
1081 | **/ | |
1082 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1083 | { | |
1084 | struct e1000_phy_info *phy = &hw->phy; | |
1085 | s32 ret_val; | |
1086 | u16 phy_data; | |
1087 | bool link; | |
1088 | ||
1089 | /* | |
1090 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
1091 | * forced whenever speed and duplex are forced. | |
1092 | */ | |
a8d2a0c2 | 1093 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1094 | if (ret_val) |
1095 | goto out; | |
1096 | ||
1097 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
a8d2a0c2 | 1098 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1099 | if (ret_val) |
1100 | goto out; | |
1101 | ||
652fff32 | 1102 | hw_dbg("M88E1000 PSCR: %X\n", phy_data); |
9d5c8243 | 1103 | |
a8d2a0c2 | 1104 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
1105 | if (ret_val) |
1106 | goto out; | |
1107 | ||
1108 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
1109 | ||
a8d2a0c2 | 1110 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
1111 | if (ret_val) |
1112 | goto out; | |
1113 | ||
2553bb26 AD |
1114 | /* Reset the phy to commit changes. */ |
1115 | ret_val = igb_phy_sw_reset(hw); | |
1116 | if (ret_val) | |
1117 | goto out; | |
9d5c8243 AK |
1118 | |
1119 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 1120 | hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
9d5c8243 | 1121 | |
2553bb26 | 1122 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
9d5c8243 AK |
1123 | if (ret_val) |
1124 | goto out; | |
1125 | ||
1126 | if (!link) { | |
1127 | /* | |
1128 | * We didn't get link. | |
1129 | * Reset the DSP and cross our fingers. | |
1130 | */ | |
a8d2a0c2 | 1131 | ret_val = phy->ops.write_reg(hw, |
2553bb26 AD |
1132 | M88E1000_PHY_PAGE_SELECT, |
1133 | 0x001d); | |
9d5c8243 AK |
1134 | if (ret_val) |
1135 | goto out; | |
1136 | ret_val = igb_phy_reset_dsp(hw); | |
1137 | if (ret_val) | |
1138 | goto out; | |
1139 | } | |
1140 | ||
1141 | /* Try once more */ | |
1142 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, | |
2553bb26 | 1143 | 100000, &link); |
9d5c8243 AK |
1144 | if (ret_val) |
1145 | goto out; | |
1146 | } | |
1147 | ||
a8d2a0c2 | 1148 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1149 | if (ret_val) |
1150 | goto out; | |
1151 | ||
1152 | /* | |
1153 | * Resetting the phy means we need to re-force TX_CLK in the | |
1154 | * Extended PHY Specific Control Register to 25MHz clock from | |
1155 | * the reset value of 2.5MHz. | |
1156 | */ | |
1157 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
a8d2a0c2 | 1158 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1159 | if (ret_val) |
1160 | goto out; | |
1161 | ||
1162 | /* | |
1163 | * In addition, we must re-enable CRS on Tx for both half and full | |
1164 | * duplex. | |
1165 | */ | |
a8d2a0c2 | 1166 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1167 | if (ret_val) |
1168 | goto out; | |
1169 | ||
1170 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
a8d2a0c2 | 1171 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1172 | |
1173 | out: | |
1174 | return ret_val; | |
1175 | } | |
1176 | ||
1177 | /** | |
733596be | 1178 | * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
9d5c8243 AK |
1179 | * @hw: pointer to the HW structure |
1180 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1181 | * | |
1182 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1183 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1184 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1185 | * the collision distance, write configuration to CTRL register. The | |
1186 | * caller must write to the PHY_CONTROL register for these settings to | |
1187 | * take affect. | |
1188 | **/ | |
1189 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
1190 | u16 *phy_ctrl) | |
1191 | { | |
1192 | struct e1000_mac_info *mac = &hw->mac; | |
1193 | u32 ctrl; | |
1194 | ||
1195 | /* Turn off flow control when forcing speed/duplex */ | |
0cce119a | 1196 | hw->fc.current_mode = e1000_fc_none; |
9d5c8243 AK |
1197 | |
1198 | /* Force speed/duplex on the mac */ | |
1199 | ctrl = rd32(E1000_CTRL); | |
1200 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1201 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1202 | ||
1203 | /* Disable Auto Speed Detection */ | |
1204 | ctrl &= ~E1000_CTRL_ASDE; | |
1205 | ||
1206 | /* Disable autoneg on the phy */ | |
1207 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1208 | ||
1209 | /* Forcing Full or Half Duplex? */ | |
1210 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1211 | ctrl &= ~E1000_CTRL_FD; | |
1212 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
652fff32 | 1213 | hw_dbg("Half Duplex\n"); |
9d5c8243 AK |
1214 | } else { |
1215 | ctrl |= E1000_CTRL_FD; | |
1216 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
652fff32 | 1217 | hw_dbg("Full Duplex\n"); |
9d5c8243 AK |
1218 | } |
1219 | ||
1220 | /* Forcing 10mb or 100mb? */ | |
1221 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1222 | ctrl |= E1000_CTRL_SPD_100; | |
1223 | *phy_ctrl |= MII_CR_SPEED_100; | |
1224 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
652fff32 | 1225 | hw_dbg("Forcing 100mb\n"); |
9d5c8243 AK |
1226 | } else { |
1227 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1228 | *phy_ctrl |= MII_CR_SPEED_10; | |
1229 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
652fff32 | 1230 | hw_dbg("Forcing 10mb\n"); |
9d5c8243 AK |
1231 | } |
1232 | ||
1233 | igb_config_collision_dist(hw); | |
1234 | ||
1235 | wr32(E1000_CTRL, ctrl); | |
1236 | } | |
1237 | ||
1238 | /** | |
733596be | 1239 | * igb_set_d3_lplu_state - Sets low power link up state for D3 |
9d5c8243 AK |
1240 | * @hw: pointer to the HW structure |
1241 | * @active: boolean used to enable/disable lplu | |
1242 | * | |
1243 | * Success returns 0, Failure returns 1 | |
1244 | * | |
1245 | * The low power link up (lplu) state is set to the power management level D3 | |
1246 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1247 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1248 | * is used during Dx states where the power conservation is most important. | |
1249 | * During driver activity, SmartSpeed should be enabled so performance is | |
1250 | * maintained. | |
1251 | **/ | |
1252 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1253 | { | |
1254 | struct e1000_phy_info *phy = &hw->phy; | |
2553bb26 | 1255 | s32 ret_val = 0; |
9d5c8243 AK |
1256 | u16 data; |
1257 | ||
2553bb26 AD |
1258 | if (!(hw->phy.ops.read_reg)) |
1259 | goto out; | |
1260 | ||
a8d2a0c2 | 1261 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
1262 | if (ret_val) |
1263 | goto out; | |
1264 | ||
1265 | if (!active) { | |
1266 | data &= ~IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1267 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1268 | data); |
1269 | if (ret_val) | |
1270 | goto out; | |
1271 | /* | |
1272 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
1273 | * during Dx states where the power conservation is most | |
1274 | * important. During driver activity we should enable | |
1275 | * SmartSpeed, so performance is maintained. | |
1276 | */ | |
1277 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 1278 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1279 | IGP01E1000_PHY_PORT_CONFIG, |
1280 | &data); | |
1281 | if (ret_val) | |
1282 | goto out; | |
1283 | ||
1284 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1285 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1286 | IGP01E1000_PHY_PORT_CONFIG, |
1287 | data); | |
1288 | if (ret_val) | |
1289 | goto out; | |
1290 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 1291 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1292 | IGP01E1000_PHY_PORT_CONFIG, |
1293 | &data); | |
1294 | if (ret_val) | |
1295 | goto out; | |
1296 | ||
1297 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1298 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1299 | IGP01E1000_PHY_PORT_CONFIG, |
1300 | data); | |
1301 | if (ret_val) | |
1302 | goto out; | |
1303 | } | |
1304 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1305 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1306 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1307 | data |= IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1308 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1309 | data); |
1310 | if (ret_val) | |
1311 | goto out; | |
1312 | ||
1313 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 1314 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
9d5c8243 AK |
1315 | &data); |
1316 | if (ret_val) | |
1317 | goto out; | |
1318 | ||
1319 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1320 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
9d5c8243 AK |
1321 | data); |
1322 | } | |
1323 | ||
1324 | out: | |
1325 | return ret_val; | |
1326 | } | |
1327 | ||
1328 | /** | |
733596be | 1329 | * igb_check_downshift - Checks whether a downshift in speed occured |
9d5c8243 AK |
1330 | * @hw: pointer to the HW structure |
1331 | * | |
1332 | * Success returns 0, Failure returns 1 | |
1333 | * | |
1334 | * A downshift is detected by querying the PHY link health. | |
1335 | **/ | |
1336 | s32 igb_check_downshift(struct e1000_hw *hw) | |
1337 | { | |
1338 | struct e1000_phy_info *phy = &hw->phy; | |
1339 | s32 ret_val; | |
1340 | u16 phy_data, offset, mask; | |
1341 | ||
1342 | switch (phy->type) { | |
1343 | case e1000_phy_m88: | |
1344 | case e1000_phy_gg82563: | |
1345 | offset = M88E1000_PHY_SPEC_STATUS; | |
1346 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1347 | break; | |
1348 | case e1000_phy_igp_2: | |
1349 | case e1000_phy_igp: | |
1350 | case e1000_phy_igp_3: | |
1351 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1352 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1353 | break; | |
1354 | default: | |
1355 | /* speed downshift not supported */ | |
1356 | phy->speed_downgraded = false; | |
1357 | ret_val = 0; | |
1358 | goto out; | |
1359 | } | |
1360 | ||
a8d2a0c2 | 1361 | ret_val = phy->ops.read_reg(hw, offset, &phy_data); |
9d5c8243 AK |
1362 | |
1363 | if (!ret_val) | |
1364 | phy->speed_downgraded = (phy_data & mask) ? true : false; | |
1365 | ||
1366 | out: | |
1367 | return ret_val; | |
1368 | } | |
1369 | ||
1370 | /** | |
733596be | 1371 | * igb_check_polarity_m88 - Checks the polarity. |
9d5c8243 AK |
1372 | * @hw: pointer to the HW structure |
1373 | * | |
1374 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1375 | * | |
1376 | * Polarity is determined based on the PHY specific status register. | |
1377 | **/ | |
1378 | static s32 igb_check_polarity_m88(struct e1000_hw *hw) | |
1379 | { | |
1380 | struct e1000_phy_info *phy = &hw->phy; | |
1381 | s32 ret_val; | |
1382 | u16 data; | |
1383 | ||
a8d2a0c2 | 1384 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); |
9d5c8243 AK |
1385 | |
1386 | if (!ret_val) | |
1387 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1388 | ? e1000_rev_polarity_reversed | |
1389 | : e1000_rev_polarity_normal; | |
1390 | ||
1391 | return ret_val; | |
1392 | } | |
1393 | ||
1394 | /** | |
733596be | 1395 | * igb_check_polarity_igp - Checks the polarity. |
9d5c8243 AK |
1396 | * @hw: pointer to the HW structure |
1397 | * | |
1398 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1399 | * | |
1400 | * Polarity is determined based on the PHY port status register, and the | |
1401 | * current speed (since there is no polarity at 100Mbps). | |
1402 | **/ | |
1403 | static s32 igb_check_polarity_igp(struct e1000_hw *hw) | |
1404 | { | |
1405 | struct e1000_phy_info *phy = &hw->phy; | |
1406 | s32 ret_val; | |
1407 | u16 data, offset, mask; | |
1408 | ||
1409 | /* | |
1410 | * Polarity is determined based on the speed of | |
1411 | * our connection. | |
1412 | */ | |
a8d2a0c2 | 1413 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1414 | if (ret_val) |
1415 | goto out; | |
1416 | ||
1417 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1418 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1419 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1420 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1421 | } else { | |
1422 | /* | |
1423 | * This really only applies to 10Mbps since | |
1424 | * there is no polarity for 100Mbps (always 0). | |
1425 | */ | |
1426 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1427 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1428 | } | |
1429 | ||
a8d2a0c2 | 1430 | ret_val = phy->ops.read_reg(hw, offset, &data); |
9d5c8243 AK |
1431 | |
1432 | if (!ret_val) | |
1433 | phy->cable_polarity = (data & mask) | |
1434 | ? e1000_rev_polarity_reversed | |
1435 | : e1000_rev_polarity_normal; | |
1436 | ||
1437 | out: | |
1438 | return ret_val; | |
1439 | } | |
1440 | ||
1441 | /** | |
733596be | 1442 | * igb_wait_autoneg - Wait for auto-neg compeletion |
9d5c8243 AK |
1443 | * @hw: pointer to the HW structure |
1444 | * | |
1445 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1446 | * limit to expire, which ever happens first. | |
1447 | **/ | |
1448 | static s32 igb_wait_autoneg(struct e1000_hw *hw) | |
1449 | { | |
1450 | s32 ret_val = 0; | |
1451 | u16 i, phy_status; | |
1452 | ||
1453 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1454 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
a8d2a0c2 | 1455 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1456 | if (ret_val) |
1457 | break; | |
a8d2a0c2 | 1458 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1459 | if (ret_val) |
1460 | break; | |
1461 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1462 | break; | |
1463 | msleep(100); | |
1464 | } | |
1465 | ||
1466 | /* | |
1467 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
1468 | * has completed. | |
1469 | */ | |
1470 | return ret_val; | |
1471 | } | |
1472 | ||
1473 | /** | |
733596be | 1474 | * igb_phy_has_link - Polls PHY for link |
9d5c8243 AK |
1475 | * @hw: pointer to the HW structure |
1476 | * @iterations: number of times to poll for link | |
1477 | * @usec_interval: delay between polling attempts | |
1478 | * @success: pointer to whether polling was successful or not | |
1479 | * | |
1480 | * Polls the PHY status register for link, 'iterations' number of times. | |
1481 | **/ | |
1482 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, | |
1483 | u32 usec_interval, bool *success) | |
1484 | { | |
1485 | s32 ret_val = 0; | |
1486 | u16 i, phy_status; | |
1487 | ||
1488 | for (i = 0; i < iterations; i++) { | |
1489 | /* | |
1490 | * Some PHYs require the PHY_STATUS register to be read | |
1491 | * twice due to the link bit being sticky. No harm doing | |
1492 | * it across the board. | |
1493 | */ | |
a8d2a0c2 | 1494 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
ab576389 AD |
1495 | if (ret_val) { |
1496 | /* | |
1497 | * If the first read fails, another entity may have | |
1498 | * ownership of the resources, wait and try again to | |
1499 | * see if they have relinquished the resources yet. | |
1500 | */ | |
1501 | udelay(usec_interval); | |
1502 | } | |
a8d2a0c2 | 1503 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1504 | if (ret_val) |
1505 | break; | |
1506 | if (phy_status & MII_SR_LINK_STATUS) | |
1507 | break; | |
1508 | if (usec_interval >= 1000) | |
1509 | mdelay(usec_interval/1000); | |
1510 | else | |
1511 | udelay(usec_interval); | |
1512 | } | |
1513 | ||
1514 | *success = (i < iterations) ? true : false; | |
1515 | ||
1516 | return ret_val; | |
1517 | } | |
1518 | ||
1519 | /** | |
733596be | 1520 | * igb_get_cable_length_m88 - Determine cable length for m88 PHY |
9d5c8243 AK |
1521 | * @hw: pointer to the HW structure |
1522 | * | |
1523 | * Reads the PHY specific status register to retrieve the cable length | |
1524 | * information. The cable length is determined by averaging the minimum and | |
1525 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1526 | * possible cable length values, which are: | |
1527 | * Register Value Cable Length | |
1528 | * 0 < 50 meters | |
1529 | * 1 50 - 80 meters | |
1530 | * 2 80 - 110 meters | |
1531 | * 3 110 - 140 meters | |
1532 | * 4 > 140 meters | |
1533 | **/ | |
1534 | s32 igb_get_cable_length_m88(struct e1000_hw *hw) | |
1535 | { | |
1536 | struct e1000_phy_info *phy = &hw->phy; | |
1537 | s32 ret_val; | |
1538 | u16 phy_data, index; | |
1539 | ||
a8d2a0c2 | 1540 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1541 | if (ret_val) |
1542 | goto out; | |
1543 | ||
1544 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1545 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
2553bb26 AD |
1546 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { |
1547 | ret_val = -E1000_ERR_PHY; | |
1548 | goto out; | |
1549 | } | |
1550 | ||
9d5c8243 | 1551 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
2553bb26 | 1552 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
9d5c8243 AK |
1553 | |
1554 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1555 | ||
1556 | out: | |
1557 | return ret_val; | |
1558 | } | |
1559 | ||
1560 | /** | |
733596be | 1561 | * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
9d5c8243 AK |
1562 | * @hw: pointer to the HW structure |
1563 | * | |
1564 | * The automatic gain control (agc) normalizes the amplitude of the | |
1565 | * received signal, adjusting for the attenuation produced by the | |
a8d2a0c2 AD |
1566 | * cable. By reading the AGC registers, which represent the |
1567 | * combination of coarse and fine gain value, the value can be put | |
9d5c8243 AK |
1568 | * into a lookup table to obtain the approximate cable length |
1569 | * for each channel. | |
1570 | **/ | |
1571 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) | |
1572 | { | |
1573 | struct e1000_phy_info *phy = &hw->phy; | |
1574 | s32 ret_val = 0; | |
1575 | u16 phy_data, i, agc_value = 0; | |
1576 | u16 cur_agc_index, max_agc_index = 0; | |
1577 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
1578 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
1579 | {IGP02E1000_PHY_AGC_A, | |
1580 | IGP02E1000_PHY_AGC_B, | |
1581 | IGP02E1000_PHY_AGC_C, | |
1582 | IGP02E1000_PHY_AGC_D}; | |
1583 | ||
1584 | /* Read the AGC registers for all channels */ | |
1585 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
a8d2a0c2 | 1586 | ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); |
9d5c8243 AK |
1587 | if (ret_val) |
1588 | goto out; | |
1589 | ||
1590 | /* | |
1591 | * Getting bits 15:9, which represent the combination of | |
a8d2a0c2 | 1592 | * coarse and fine gain values. The result is a number |
9d5c8243 AK |
1593 | * that can be put into the lookup table to obtain the |
1594 | * approximate cable length. | |
1595 | */ | |
1596 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | |
1597 | IGP02E1000_AGC_LENGTH_MASK; | |
1598 | ||
1599 | /* Array index bound check. */ | |
1600 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1601 | (cur_agc_index == 0)) { | |
1602 | ret_val = -E1000_ERR_PHY; | |
1603 | goto out; | |
1604 | } | |
1605 | ||
1606 | /* Remove min & max AGC values from calculation. */ | |
1607 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1608 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1609 | min_agc_index = cur_agc_index; | |
1610 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1611 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1612 | max_agc_index = cur_agc_index; | |
1613 | ||
1614 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1615 | } | |
1616 | ||
1617 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1618 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1619 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1620 | ||
1621 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1622 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1623 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1624 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1625 | ||
1626 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1627 | ||
1628 | out: | |
1629 | return ret_val; | |
1630 | } | |
1631 | ||
1632 | /** | |
733596be | 1633 | * igb_get_phy_info_m88 - Retrieve PHY information |
9d5c8243 AK |
1634 | * @hw: pointer to the HW structure |
1635 | * | |
1636 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1637 | * to verify that link is up. Read the PHY special control register to | |
1638 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1639 | * special status register to determine MDI/MDIx and current speed. If | |
1640 | * speed is 1000, then determine cable length, local and remote receiver. | |
1641 | **/ | |
1642 | s32 igb_get_phy_info_m88(struct e1000_hw *hw) | |
1643 | { | |
1644 | struct e1000_phy_info *phy = &hw->phy; | |
1645 | s32 ret_val; | |
1646 | u16 phy_data; | |
1647 | bool link; | |
1648 | ||
a8d2a0c2 | 1649 | if (phy->media_type != e1000_media_type_copper) { |
652fff32 | 1650 | hw_dbg("Phy info is only valid for copper media\n"); |
9d5c8243 AK |
1651 | ret_val = -E1000_ERR_CONFIG; |
1652 | goto out; | |
1653 | } | |
1654 | ||
1655 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1656 | if (ret_val) | |
1657 | goto out; | |
1658 | ||
1659 | if (!link) { | |
652fff32 | 1660 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1661 | ret_val = -E1000_ERR_CONFIG; |
1662 | goto out; | |
1663 | } | |
1664 | ||
a8d2a0c2 | 1665 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1666 | if (ret_val) |
1667 | goto out; | |
1668 | ||
1669 | phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) | |
a8d2a0c2 | 1670 | ? true : false; |
9d5c8243 AK |
1671 | |
1672 | ret_val = igb_check_polarity_m88(hw); | |
1673 | if (ret_val) | |
1674 | goto out; | |
1675 | ||
a8d2a0c2 | 1676 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1677 | if (ret_val) |
1678 | goto out; | |
1679 | ||
1680 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; | |
1681 | ||
1682 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
a8d2a0c2 | 1683 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1684 | if (ret_val) |
1685 | goto out; | |
1686 | ||
a8d2a0c2 | 1687 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); |
9d5c8243 AK |
1688 | if (ret_val) |
1689 | goto out; | |
1690 | ||
1691 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1692 | ? e1000_1000t_rx_status_ok | |
1693 | : e1000_1000t_rx_status_not_ok; | |
1694 | ||
1695 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1696 | ? e1000_1000t_rx_status_ok | |
1697 | : e1000_1000t_rx_status_not_ok; | |
1698 | } else { | |
1699 | /* Set values to "undefined" */ | |
1700 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1701 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1702 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1703 | } | |
1704 | ||
1705 | out: | |
1706 | return ret_val; | |
1707 | } | |
1708 | ||
1709 | /** | |
733596be | 1710 | * igb_get_phy_info_igp - Retrieve igp PHY information |
9d5c8243 AK |
1711 | * @hw: pointer to the HW structure |
1712 | * | |
1713 | * Read PHY status to determine if link is up. If link is up, then | |
1714 | * set/determine 10base-T extended distance and polarity correction. Read | |
1715 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1716 | * determine on the cable length, local and remote receiver. | |
1717 | **/ | |
1718 | s32 igb_get_phy_info_igp(struct e1000_hw *hw) | |
1719 | { | |
1720 | struct e1000_phy_info *phy = &hw->phy; | |
1721 | s32 ret_val; | |
1722 | u16 data; | |
1723 | bool link; | |
1724 | ||
1725 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1726 | if (ret_val) | |
1727 | goto out; | |
1728 | ||
1729 | if (!link) { | |
652fff32 | 1730 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1731 | ret_val = -E1000_ERR_CONFIG; |
1732 | goto out; | |
1733 | } | |
1734 | ||
1735 | phy->polarity_correction = true; | |
1736 | ||
1737 | ret_val = igb_check_polarity_igp(hw); | |
1738 | if (ret_val) | |
1739 | goto out; | |
1740 | ||
a8d2a0c2 | 1741 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1742 | if (ret_val) |
1743 | goto out; | |
1744 | ||
1745 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; | |
1746 | ||
1747 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1748 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
a8d2a0c2 | 1749 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1750 | if (ret_val) |
1751 | goto out; | |
1752 | ||
a8d2a0c2 | 1753 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
9d5c8243 AK |
1754 | if (ret_val) |
1755 | goto out; | |
1756 | ||
1757 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
1758 | ? e1000_1000t_rx_status_ok | |
1759 | : e1000_1000t_rx_status_not_ok; | |
1760 | ||
1761 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
1762 | ? e1000_1000t_rx_status_ok | |
1763 | : e1000_1000t_rx_status_not_ok; | |
1764 | } else { | |
1765 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1766 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1767 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1768 | } | |
1769 | ||
1770 | out: | |
1771 | return ret_val; | |
1772 | } | |
1773 | ||
1774 | /** | |
733596be | 1775 | * igb_phy_sw_reset - PHY software reset |
9d5c8243 AK |
1776 | * @hw: pointer to the HW structure |
1777 | * | |
1778 | * Does a software reset of the PHY by reading the PHY control register and | |
1779 | * setting/write the control register reset bit to the PHY. | |
1780 | **/ | |
1781 | s32 igb_phy_sw_reset(struct e1000_hw *hw) | |
1782 | { | |
d314737a | 1783 | s32 ret_val = 0; |
9d5c8243 AK |
1784 | u16 phy_ctrl; |
1785 | ||
d314737a AD |
1786 | if (!(hw->phy.ops.read_reg)) |
1787 | goto out; | |
1788 | ||
a8d2a0c2 | 1789 | ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
1790 | if (ret_val) |
1791 | goto out; | |
1792 | ||
1793 | phy_ctrl |= MII_CR_RESET; | |
a8d2a0c2 | 1794 | ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
1795 | if (ret_val) |
1796 | goto out; | |
1797 | ||
1798 | udelay(1); | |
1799 | ||
1800 | out: | |
1801 | return ret_val; | |
1802 | } | |
1803 | ||
1804 | /** | |
733596be | 1805 | * igb_phy_hw_reset - PHY hardware reset |
9d5c8243 AK |
1806 | * @hw: pointer to the HW structure |
1807 | * | |
1808 | * Verify the reset block is not blocking us from resetting. Acquire | |
1809 | * semaphore (if necessary) and read/set/write the device control reset | |
1810 | * bit in the PHY. Wait the appropriate delay time for the device to | |
1811 | * reset and relase the semaphore (if necessary). | |
1812 | **/ | |
1813 | s32 igb_phy_hw_reset(struct e1000_hw *hw) | |
1814 | { | |
1815 | struct e1000_phy_info *phy = &hw->phy; | |
1816 | s32 ret_val; | |
1817 | u32 ctrl; | |
1818 | ||
1819 | ret_val = igb_check_reset_block(hw); | |
1820 | if (ret_val) { | |
1821 | ret_val = 0; | |
1822 | goto out; | |
1823 | } | |
1824 | ||
a8d2a0c2 | 1825 | ret_val = phy->ops.acquire(hw); |
9d5c8243 AK |
1826 | if (ret_val) |
1827 | goto out; | |
1828 | ||
1829 | ctrl = rd32(E1000_CTRL); | |
1830 | wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); | |
1831 | wrfl(); | |
1832 | ||
1833 | udelay(phy->reset_delay_us); | |
1834 | ||
1835 | wr32(E1000_CTRL, ctrl); | |
1836 | wrfl(); | |
1837 | ||
1838 | udelay(150); | |
1839 | ||
a8d2a0c2 | 1840 | phy->ops.release(hw); |
9d5c8243 | 1841 | |
a8d2a0c2 | 1842 | ret_val = phy->ops.get_cfg_done(hw); |
9d5c8243 AK |
1843 | |
1844 | out: | |
1845 | return ret_val; | |
1846 | } | |
1847 | ||
9d5c8243 | 1848 | /** |
733596be | 1849 | * igb_phy_init_script_igp3 - Inits the IGP3 PHY |
9d5c8243 AK |
1850 | * @hw: pointer to the HW structure |
1851 | * | |
1852 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
1853 | **/ | |
1854 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw) | |
1855 | { | |
652fff32 | 1856 | hw_dbg("Running IGP 3 PHY init script\n"); |
9d5c8243 AK |
1857 | |
1858 | /* PHY init IGP 3 */ | |
1859 | /* Enable rise/fall, 10-mode work in class-A */ | |
a8d2a0c2 | 1860 | hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); |
9d5c8243 | 1861 | /* Remove all caps from Replica path filter */ |
a8d2a0c2 | 1862 | hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); |
9d5c8243 | 1863 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
a8d2a0c2 | 1864 | hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); |
9d5c8243 | 1865 | /* Increase Hybrid poly bias */ |
a8d2a0c2 | 1866 | hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); |
9d5c8243 | 1867 | /* Add 4% to TX amplitude in Giga mode */ |
a8d2a0c2 | 1868 | hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); |
9d5c8243 | 1869 | /* Disable trimming (TTT) */ |
a8d2a0c2 | 1870 | hw->phy.ops.write_reg(hw, 0x2011, 0x0000); |
9d5c8243 | 1871 | /* Poly DC correction to 94.6% + 2% for all channels */ |
a8d2a0c2 | 1872 | hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); |
9d5c8243 | 1873 | /* ABS DC correction to 95.9% */ |
a8d2a0c2 | 1874 | hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); |
9d5c8243 | 1875 | /* BG temp curve trim */ |
a8d2a0c2 | 1876 | hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); |
9d5c8243 | 1877 | /* Increasing ADC OPAMP stage 1 currents to max */ |
a8d2a0c2 | 1878 | hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); |
9d5c8243 | 1879 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
a8d2a0c2 | 1880 | hw->phy.ops.write_reg(hw, 0x0000, 0x0140); |
9d5c8243 | 1881 | /* Set upd_freq to 6 */ |
a8d2a0c2 | 1882 | hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); |
9d5c8243 | 1883 | /* Disable NPDFE */ |
a8d2a0c2 | 1884 | hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); |
9d5c8243 | 1885 | /* Disable adaptive fixed FFE (Default) */ |
a8d2a0c2 | 1886 | hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); |
9d5c8243 | 1887 | /* Enable FFE hysteresis */ |
a8d2a0c2 | 1888 | hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); |
9d5c8243 | 1889 | /* Fixed FFE for short cable lengths */ |
a8d2a0c2 | 1890 | hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); |
9d5c8243 | 1891 | /* Fixed FFE for medium cable lengths */ |
a8d2a0c2 | 1892 | hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); |
9d5c8243 | 1893 | /* Fixed FFE for long cable lengths */ |
a8d2a0c2 | 1894 | hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); |
9d5c8243 | 1895 | /* Enable Adaptive Clip Threshold */ |
a8d2a0c2 | 1896 | hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); |
9d5c8243 | 1897 | /* AHT reset limit to 1 */ |
a8d2a0c2 | 1898 | hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); |
9d5c8243 | 1899 | /* Set AHT master delay to 127 msec */ |
a8d2a0c2 | 1900 | hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); |
9d5c8243 | 1901 | /* Set scan bits for AHT */ |
a8d2a0c2 | 1902 | hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); |
9d5c8243 | 1903 | /* Set AHT Preset bits */ |
a8d2a0c2 | 1904 | hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); |
9d5c8243 | 1905 | /* Change integ_factor of channel A to 3 */ |
a8d2a0c2 | 1906 | hw->phy.ops.write_reg(hw, 0x1895, 0x0003); |
9d5c8243 | 1907 | /* Change prop_factor of channels BCD to 8 */ |
a8d2a0c2 | 1908 | hw->phy.ops.write_reg(hw, 0x1796, 0x0008); |
9d5c8243 | 1909 | /* Change cg_icount + enable integbp for channels BCD */ |
a8d2a0c2 | 1910 | hw->phy.ops.write_reg(hw, 0x1798, 0xD008); |
9d5c8243 AK |
1911 | /* |
1912 | * Change cg_icount + enable integbp + change prop_factor_master | |
1913 | * to 8 for channel A | |
1914 | */ | |
a8d2a0c2 | 1915 | hw->phy.ops.write_reg(hw, 0x1898, 0xD918); |
9d5c8243 | 1916 | /* Disable AHT in Slave mode on channel A */ |
a8d2a0c2 | 1917 | hw->phy.ops.write_reg(hw, 0x187A, 0x0800); |
9d5c8243 AK |
1918 | /* |
1919 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
1920 | * Enable SPD+B2B | |
1921 | */ | |
a8d2a0c2 | 1922 | hw->phy.ops.write_reg(hw, 0x0019, 0x008D); |
9d5c8243 | 1923 | /* Enable restart AN on an1000_dis change */ |
a8d2a0c2 | 1924 | hw->phy.ops.write_reg(hw, 0x001B, 0x2080); |
9d5c8243 | 1925 | /* Enable wh_fifo read clock in 10/100 modes */ |
a8d2a0c2 | 1926 | hw->phy.ops.write_reg(hw, 0x0014, 0x0045); |
9d5c8243 | 1927 | /* Restart AN, Speed selection is 1000 */ |
a8d2a0c2 | 1928 | hw->phy.ops.write_reg(hw, 0x0000, 0x1340); |
9d5c8243 AK |
1929 | |
1930 | return 0; | |
1931 | } | |
1932 | ||
88a268c1 NN |
1933 | /** |
1934 | * igb_power_up_phy_copper - Restore copper link in case of PHY power down | |
1935 | * @hw: pointer to the HW structure | |
1936 | * | |
1937 | * In the case of a PHY power down to save power, or to turn off link during a | |
1938 | * driver unload, restore the link to previous settings. | |
1939 | **/ | |
1940 | void igb_power_up_phy_copper(struct e1000_hw *hw) | |
1941 | { | |
1942 | u16 mii_reg = 0; | |
1943 | ||
1944 | /* The PHY will retain its settings across a power down/up cycle */ | |
1945 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); | |
1946 | mii_reg &= ~MII_CR_POWER_DOWN; | |
1947 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); | |
1948 | } | |
1949 | ||
1950 | /** | |
1951 | * igb_power_down_phy_copper - Power down copper PHY | |
1952 | * @hw: pointer to the HW structure | |
1953 | * | |
1954 | * Power down PHY to save power when interface is down and wake on lan | |
1955 | * is not enabled. | |
1956 | **/ | |
1957 | void igb_power_down_phy_copper(struct e1000_hw *hw) | |
1958 | { | |
1959 | u16 mii_reg = 0; | |
1960 | ||
1961 | /* The PHY will retain its settings across a power down/up cycle */ | |
1962 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); | |
1963 | mii_reg |= MII_CR_POWER_DOWN; | |
1964 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); | |
1965 | msleep(1); | |
1966 | } | |
1967 | ||
2909c3f7 AD |
1968 | /** |
1969 | * igb_check_polarity_82580 - Checks the polarity. | |
1970 | * @hw: pointer to the HW structure | |
1971 | * | |
1972 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1973 | * | |
1974 | * Polarity is determined based on the PHY specific status register. | |
1975 | **/ | |
bb2ac47b | 1976 | static s32 igb_check_polarity_82580(struct e1000_hw *hw) |
2909c3f7 AD |
1977 | { |
1978 | struct e1000_phy_info *phy = &hw->phy; | |
1979 | s32 ret_val; | |
1980 | u16 data; | |
1981 | ||
1982 | ||
1983 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); | |
1984 | ||
1985 | if (!ret_val) | |
1986 | phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) | |
1987 | ? e1000_rev_polarity_reversed | |
1988 | : e1000_rev_polarity_normal; | |
1989 | ||
1990 | return ret_val; | |
1991 | } | |
1992 | ||
1993 | /** | |
1994 | * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY | |
1995 | * @hw: pointer to the HW structure | |
1996 | * | |
1997 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1998 | * auto-crossover to force MDI manually. Waits for link and returns | |
1999 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
2000 | **/ | |
2001 | s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) | |
2002 | { | |
2003 | struct e1000_phy_info *phy = &hw->phy; | |
2004 | s32 ret_val; | |
2005 | u16 phy_data; | |
2006 | bool link; | |
2007 | ||
2008 | ||
2009 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); | |
2010 | if (ret_val) | |
2011 | goto out; | |
2012 | ||
2013 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
2014 | ||
2015 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); | |
2016 | if (ret_val) | |
2017 | goto out; | |
2018 | ||
2019 | /* | |
2020 | * Clear Auto-Crossover to force MDI manually. 82580 requires MDI | |
2021 | * forced whenever speed and duplex are forced. | |
2022 | */ | |
2023 | ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); | |
2024 | if (ret_val) | |
2025 | goto out; | |
2026 | ||
2027 | phy_data &= ~I82580_PHY_CTRL2_AUTO_MDIX; | |
2028 | phy_data &= ~I82580_PHY_CTRL2_FORCE_MDI_MDIX; | |
2029 | ||
2030 | ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); | |
2031 | if (ret_val) | |
2032 | goto out; | |
2033 | ||
2034 | hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); | |
2035 | ||
2036 | udelay(1); | |
2037 | ||
2038 | if (phy->autoneg_wait_to_complete) { | |
2039 | hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); | |
2040 | ||
2041 | ret_val = igb_phy_has_link(hw, | |
2042 | PHY_FORCE_LIMIT, | |
2043 | 100000, | |
2044 | &link); | |
2045 | if (ret_val) | |
2046 | goto out; | |
2047 | ||
2048 | if (!link) | |
2049 | hw_dbg("Link taking longer than expected.\n"); | |
2050 | ||
2051 | /* Try once more */ | |
2052 | ret_val = igb_phy_has_link(hw, | |
2053 | PHY_FORCE_LIMIT, | |
2054 | 100000, | |
2055 | &link); | |
2056 | if (ret_val) | |
2057 | goto out; | |
2058 | } | |
2059 | ||
2060 | out: | |
2061 | return ret_val; | |
2062 | } | |
2063 | ||
2064 | /** | |
2065 | * igb_get_phy_info_82580 - Retrieve I82580 PHY information | |
2066 | * @hw: pointer to the HW structure | |
2067 | * | |
2068 | * Read PHY status to determine if link is up. If link is up, then | |
2069 | * set/determine 10base-T extended distance and polarity correction. Read | |
2070 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
2071 | * determine on the cable length, local and remote receiver. | |
2072 | **/ | |
2073 | s32 igb_get_phy_info_82580(struct e1000_hw *hw) | |
2074 | { | |
2075 | struct e1000_phy_info *phy = &hw->phy; | |
2076 | s32 ret_val; | |
2077 | u16 data; | |
2078 | bool link; | |
2079 | ||
2080 | ||
2081 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
2082 | if (ret_val) | |
2083 | goto out; | |
2084 | ||
2085 | if (!link) { | |
2086 | hw_dbg("Phy info is only valid if link is up\n"); | |
2087 | ret_val = -E1000_ERR_CONFIG; | |
2088 | goto out; | |
2089 | } | |
2090 | ||
2091 | phy->polarity_correction = true; | |
2092 | ||
2093 | ret_val = igb_check_polarity_82580(hw); | |
2094 | if (ret_val) | |
2095 | goto out; | |
2096 | ||
2097 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); | |
2098 | if (ret_val) | |
2099 | goto out; | |
2100 | ||
2101 | phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; | |
2102 | ||
2103 | if ((data & I82580_PHY_STATUS2_SPEED_MASK) == | |
2104 | I82580_PHY_STATUS2_SPEED_1000MBPS) { | |
2105 | ret_val = hw->phy.ops.get_cable_length(hw); | |
2106 | if (ret_val) | |
2107 | goto out; | |
2108 | ||
2109 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); | |
2110 | if (ret_val) | |
2111 | goto out; | |
2112 | ||
2113 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
2114 | ? e1000_1000t_rx_status_ok | |
2115 | : e1000_1000t_rx_status_not_ok; | |
2116 | ||
2117 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
2118 | ? e1000_1000t_rx_status_ok | |
2119 | : e1000_1000t_rx_status_not_ok; | |
2120 | } else { | |
2121 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2122 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2123 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2124 | } | |
2125 | ||
2126 | out: | |
2127 | return ret_val; | |
2128 | } | |
2129 | ||
2130 | /** | |
2131 | * igb_get_cable_length_82580 - Determine cable length for 82580 PHY | |
2132 | * @hw: pointer to the HW structure | |
2133 | * | |
2134 | * Reads the diagnostic status register and verifies result is valid before | |
2135 | * placing it in the phy_cable_length field. | |
2136 | **/ | |
2137 | s32 igb_get_cable_length_82580(struct e1000_hw *hw) | |
2138 | { | |
2139 | struct e1000_phy_info *phy = &hw->phy; | |
2140 | s32 ret_val; | |
2141 | u16 phy_data, length; | |
2142 | ||
2143 | ||
2144 | ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); | |
2145 | if (ret_val) | |
2146 | goto out; | |
2147 | ||
2148 | length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> | |
2149 | I82580_DSTATUS_CABLE_LENGTH_SHIFT; | |
2150 | ||
2151 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
2152 | ret_val = -E1000_ERR_PHY; | |
2153 | ||
2154 | phy->cable_length = length; | |
2155 | ||
2156 | out: | |
2157 | return ret_val; | |
2158 | } |