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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/if_ether.h> | |
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000_mac.h" | |
32 | #include "e1000_phy.h" | |
33 | ||
9d5c8243 AK |
34 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); |
35 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
36 | u16 *phy_ctrl); | |
37 | static s32 igb_wait_autoneg(struct e1000_hw *hw); | |
38 | ||
39 | /* Cable length tables */ | |
40 | static const u16 e1000_m88_cable_length_table[] = | |
41 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
9d5c8243 AK |
42 | |
43 | static const u16 e1000_igp_2_cable_length_table[] = | |
44 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, | |
45 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
46 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
47 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
48 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
49 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
50 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
51 | 104, 109, 114, 118, 121, 124}; | |
52 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ | |
53 | (sizeof(e1000_igp_2_cable_length_table) / \ | |
54 | sizeof(e1000_igp_2_cable_length_table[0])) | |
55 | ||
56 | /** | |
733596be | 57 | * igb_check_reset_block - Check if PHY reset is blocked |
9d5c8243 AK |
58 | * @hw: pointer to the HW structure |
59 | * | |
60 | * Read the PHY management control register and check whether a PHY reset | |
61 | * is blocked. If a reset is not blocked return 0, otherwise | |
62 | * return E1000_BLK_PHY_RESET (12). | |
63 | **/ | |
64 | s32 igb_check_reset_block(struct e1000_hw *hw) | |
65 | { | |
66 | u32 manc; | |
67 | ||
68 | manc = rd32(E1000_MANC); | |
69 | ||
70 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
71 | E1000_BLK_PHY_RESET : 0; | |
72 | } | |
73 | ||
74 | /** | |
733596be | 75 | * igb_get_phy_id - Retrieve the PHY ID and revision |
9d5c8243 AK |
76 | * @hw: pointer to the HW structure |
77 | * | |
78 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
79 | * revision in the hardware structure. | |
80 | **/ | |
81 | s32 igb_get_phy_id(struct e1000_hw *hw) | |
82 | { | |
83 | struct e1000_phy_info *phy = &hw->phy; | |
84 | s32 ret_val = 0; | |
85 | u16 phy_id; | |
86 | ||
a8d2a0c2 | 87 | ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); |
9d5c8243 AK |
88 | if (ret_val) |
89 | goto out; | |
90 | ||
91 | phy->id = (u32)(phy_id << 16); | |
92 | udelay(20); | |
a8d2a0c2 | 93 | ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); |
9d5c8243 AK |
94 | if (ret_val) |
95 | goto out; | |
96 | ||
97 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | |
98 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
99 | ||
100 | out: | |
101 | return ret_val; | |
102 | } | |
103 | ||
104 | /** | |
733596be | 105 | * igb_phy_reset_dsp - Reset PHY DSP |
9d5c8243 AK |
106 | * @hw: pointer to the HW structure |
107 | * | |
108 | * Reset the digital signal processor. | |
109 | **/ | |
110 | static s32 igb_phy_reset_dsp(struct e1000_hw *hw) | |
111 | { | |
112 | s32 ret_val; | |
113 | ||
a8d2a0c2 | 114 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
9d5c8243 AK |
115 | if (ret_val) |
116 | goto out; | |
117 | ||
a8d2a0c2 | 118 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); |
9d5c8243 AK |
119 | |
120 | out: | |
121 | return ret_val; | |
122 | } | |
123 | ||
124 | /** | |
733596be | 125 | * igb_read_phy_reg_mdic - Read MDI control register |
9d5c8243 AK |
126 | * @hw: pointer to the HW structure |
127 | * @offset: register offset to be read | |
128 | * @data: pointer to the read data | |
129 | * | |
130 | * Reads the MDI control regsiter in the PHY at offset and stores the | |
131 | * information read to data. | |
132 | **/ | |
133 | static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) | |
134 | { | |
135 | struct e1000_phy_info *phy = &hw->phy; | |
136 | u32 i, mdic = 0; | |
137 | s32 ret_val = 0; | |
138 | ||
139 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 140 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
141 | ret_val = -E1000_ERR_PARAM; |
142 | goto out; | |
143 | } | |
144 | ||
145 | /* | |
146 | * Set up Op-code, Phy Address, and register offset in the MDI | |
147 | * Control register. The MAC will take care of interfacing with the | |
148 | * PHY to retrieve the desired data. | |
149 | */ | |
150 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
151 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
152 | (E1000_MDIC_OP_READ)); | |
153 | ||
154 | wr32(E1000_MDIC, mdic); | |
155 | ||
156 | /* | |
157 | * Poll the ready bit to see if the MDI read completed | |
158 | * Increasing the time out as testing showed failures with | |
159 | * the lower time out | |
160 | */ | |
161 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
162 | udelay(50); | |
163 | mdic = rd32(E1000_MDIC); | |
164 | if (mdic & E1000_MDIC_READY) | |
165 | break; | |
166 | } | |
167 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 168 | hw_dbg("MDI Read did not complete\n"); |
9d5c8243 AK |
169 | ret_val = -E1000_ERR_PHY; |
170 | goto out; | |
171 | } | |
172 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 173 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
174 | ret_val = -E1000_ERR_PHY; |
175 | goto out; | |
176 | } | |
177 | *data = (u16) mdic; | |
178 | ||
179 | out: | |
180 | return ret_val; | |
181 | } | |
182 | ||
183 | /** | |
733596be | 184 | * igb_write_phy_reg_mdic - Write MDI control register |
9d5c8243 AK |
185 | * @hw: pointer to the HW structure |
186 | * @offset: register offset to write to | |
187 | * @data: data to write to register at offset | |
188 | * | |
189 | * Writes data to MDI control register in the PHY at offset. | |
190 | **/ | |
191 | static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) | |
192 | { | |
193 | struct e1000_phy_info *phy = &hw->phy; | |
194 | u32 i, mdic = 0; | |
195 | s32 ret_val = 0; | |
196 | ||
197 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 198 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
199 | ret_val = -E1000_ERR_PARAM; |
200 | goto out; | |
201 | } | |
202 | ||
203 | /* | |
204 | * Set up Op-code, Phy Address, and register offset in the MDI | |
205 | * Control register. The MAC will take care of interfacing with the | |
206 | * PHY to retrieve the desired data. | |
207 | */ | |
208 | mdic = (((u32)data) | | |
209 | (offset << E1000_MDIC_REG_SHIFT) | | |
210 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
211 | (E1000_MDIC_OP_WRITE)); | |
212 | ||
213 | wr32(E1000_MDIC, mdic); | |
214 | ||
215 | /* | |
216 | * Poll the ready bit to see if the MDI read completed | |
217 | * Increasing the time out as testing showed failures with | |
218 | * the lower time out | |
219 | */ | |
220 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
221 | udelay(50); | |
222 | mdic = rd32(E1000_MDIC); | |
223 | if (mdic & E1000_MDIC_READY) | |
224 | break; | |
225 | } | |
226 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 227 | hw_dbg("MDI Write did not complete\n"); |
9d5c8243 AK |
228 | ret_val = -E1000_ERR_PHY; |
229 | goto out; | |
230 | } | |
231 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 232 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
233 | ret_val = -E1000_ERR_PHY; |
234 | goto out; | |
235 | } | |
236 | ||
237 | out: | |
238 | return ret_val; | |
239 | } | |
240 | ||
241 | /** | |
733596be | 242 | * igb_read_phy_reg_igp - Read igp PHY register |
9d5c8243 AK |
243 | * @hw: pointer to the HW structure |
244 | * @offset: register offset to be read | |
245 | * @data: pointer to the read data | |
246 | * | |
247 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
248 | * and storing the retrieved information in data. Release any acquired | |
249 | * semaphores before exiting. | |
250 | **/ | |
251 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
252 | { | |
a8d2a0c2 AD |
253 | s32 ret_val = 0; |
254 | ||
255 | if (!(hw->phy.ops.acquire)) | |
256 | goto out; | |
9d5c8243 | 257 | |
a8d2a0c2 | 258 | ret_val = hw->phy.ops.acquire(hw); |
9d5c8243 AK |
259 | if (ret_val) |
260 | goto out; | |
261 | ||
262 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
263 | ret_val = igb_write_phy_reg_mdic(hw, | |
264 | IGP01E1000_PHY_PAGE_SELECT, | |
265 | (u16)offset); | |
266 | if (ret_val) { | |
a8d2a0c2 | 267 | hw->phy.ops.release(hw); |
9d5c8243 AK |
268 | goto out; |
269 | } | |
270 | } | |
271 | ||
a8d2a0c2 AD |
272 | ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
273 | data); | |
9d5c8243 | 274 | |
a8d2a0c2 | 275 | hw->phy.ops.release(hw); |
9d5c8243 AK |
276 | |
277 | out: | |
278 | return ret_val; | |
279 | } | |
280 | ||
281 | /** | |
733596be | 282 | * igb_write_phy_reg_igp - Write igp PHY register |
9d5c8243 AK |
283 | * @hw: pointer to the HW structure |
284 | * @offset: register offset to write to | |
285 | * @data: data to write at register offset | |
286 | * | |
287 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
288 | * at the offset. Release any acquired semaphores before exiting. | |
289 | **/ | |
290 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
291 | { | |
a8d2a0c2 | 292 | s32 ret_val = 0; |
9d5c8243 | 293 | |
a8d2a0c2 AD |
294 | if (!(hw->phy.ops.acquire)) |
295 | goto out; | |
296 | ||
297 | ret_val = hw->phy.ops.acquire(hw); | |
9d5c8243 AK |
298 | if (ret_val) |
299 | goto out; | |
300 | ||
301 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
302 | ret_val = igb_write_phy_reg_mdic(hw, | |
303 | IGP01E1000_PHY_PAGE_SELECT, | |
304 | (u16)offset); | |
305 | if (ret_val) { | |
a8d2a0c2 | 306 | hw->phy.ops.release(hw); |
9d5c8243 AK |
307 | goto out; |
308 | } | |
309 | } | |
310 | ||
a8d2a0c2 | 311 | ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
9d5c8243 AK |
312 | data); |
313 | ||
a8d2a0c2 | 314 | hw->phy.ops.release(hw); |
9d5c8243 AK |
315 | |
316 | out: | |
317 | return ret_val; | |
318 | } | |
319 | ||
320 | /** | |
733596be | 321 | * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link |
9d5c8243 AK |
322 | * @hw: pointer to the HW structure |
323 | * | |
324 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
325 | * and downshift values are set also. | |
326 | **/ | |
327 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw) | |
328 | { | |
329 | struct e1000_phy_info *phy = &hw->phy; | |
330 | s32 ret_val; | |
331 | u16 phy_data; | |
332 | ||
333 | if (phy->reset_disable) { | |
334 | ret_val = 0; | |
335 | goto out; | |
336 | } | |
337 | ||
338 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
a8d2a0c2 | 339 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
340 | if (ret_val) |
341 | goto out; | |
342 | ||
343 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
344 | ||
345 | /* | |
346 | * Options: | |
347 | * MDI/MDI-X = 0 (default) | |
348 | * 0 - Auto for all speeds | |
349 | * 1 - MDI mode | |
350 | * 2 - MDI-X mode | |
351 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
352 | */ | |
353 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
354 | ||
355 | switch (phy->mdix) { | |
356 | case 1: | |
357 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
358 | break; | |
359 | case 2: | |
360 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
361 | break; | |
362 | case 3: | |
363 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
364 | break; | |
365 | case 0: | |
366 | default: | |
367 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
368 | break; | |
369 | } | |
370 | ||
371 | /* | |
372 | * Options: | |
373 | * disable_polarity_correction = 0 (default) | |
374 | * Automatic Correction for Reversed Cable Polarity | |
375 | * 0 - Disabled | |
376 | * 1 - Enabled | |
377 | */ | |
378 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
379 | if (phy->disable_polarity_correction == 1) | |
380 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
381 | ||
a8d2a0c2 | 382 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
383 | if (ret_val) |
384 | goto out; | |
385 | ||
386 | if (phy->revision < E1000_REVISION_4) { | |
387 | /* | |
388 | * Force TX_CLK in the Extended PHY Specific Control Register | |
389 | * to 25MHz clock. | |
390 | */ | |
a8d2a0c2 | 391 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
392 | &phy_data); |
393 | if (ret_val) | |
394 | goto out; | |
395 | ||
396 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
397 | ||
398 | if ((phy->revision == E1000_REVISION_2) && | |
399 | (phy->id == M88E1111_I_PHY_ID)) { | |
400 | /* 82573L PHY - set the downshift counter to 5x. */ | |
401 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
402 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
403 | } else { | |
404 | /* Configure Master and Slave downshift values */ | |
405 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
406 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
407 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
408 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
409 | } | |
a8d2a0c2 | 410 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
411 | phy_data); |
412 | if (ret_val) | |
413 | goto out; | |
414 | } | |
415 | ||
416 | /* Commit the changes. */ | |
417 | ret_val = igb_phy_sw_reset(hw); | |
418 | if (ret_val) { | |
652fff32 | 419 | hw_dbg("Error committing the PHY changes\n"); |
9d5c8243 AK |
420 | goto out; |
421 | } | |
422 | ||
423 | out: | |
424 | return ret_val; | |
425 | } | |
426 | ||
427 | /** | |
733596be | 428 | * igb_copper_link_setup_igp - Setup igp PHY's for copper link |
9d5c8243 AK |
429 | * @hw: pointer to the HW structure |
430 | * | |
431 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
432 | * igp PHY's. | |
433 | **/ | |
434 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw) | |
435 | { | |
436 | struct e1000_phy_info *phy = &hw->phy; | |
437 | s32 ret_val; | |
438 | u16 data; | |
439 | ||
440 | if (phy->reset_disable) { | |
441 | ret_val = 0; | |
442 | goto out; | |
443 | } | |
444 | ||
a8d2a0c2 | 445 | ret_val = phy->ops.reset(hw); |
9d5c8243 | 446 | if (ret_val) { |
652fff32 | 447 | hw_dbg("Error resetting the PHY.\n"); |
9d5c8243 AK |
448 | goto out; |
449 | } | |
450 | ||
a6a60569 AD |
451 | /* |
452 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
453 | * timeout issues when LFS is enabled. | |
454 | */ | |
455 | msleep(100); | |
9d5c8243 AK |
456 | |
457 | /* | |
458 | * The NVM settings will configure LPLU in D3 for | |
459 | * non-IGP1 PHYs. | |
460 | */ | |
461 | if (phy->type == e1000_phy_igp) { | |
462 | /* disable lplu d3 during driver init */ | |
a8d2a0c2 AD |
463 | if (phy->ops.set_d3_lplu_state) |
464 | ret_val = phy->ops.set_d3_lplu_state(hw, false); | |
9d5c8243 | 465 | if (ret_val) { |
652fff32 | 466 | hw_dbg("Error Disabling LPLU D3\n"); |
9d5c8243 AK |
467 | goto out; |
468 | } | |
469 | } | |
470 | ||
471 | /* disable lplu d0 during driver init */ | |
a8d2a0c2 | 472 | ret_val = phy->ops.set_d0_lplu_state(hw, false); |
9d5c8243 | 473 | if (ret_val) { |
652fff32 | 474 | hw_dbg("Error Disabling LPLU D0\n"); |
9d5c8243 AK |
475 | goto out; |
476 | } | |
477 | /* Configure mdi-mdix settings */ | |
a8d2a0c2 | 478 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
9d5c8243 AK |
479 | if (ret_val) |
480 | goto out; | |
481 | ||
482 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
483 | ||
484 | switch (phy->mdix) { | |
485 | case 1: | |
486 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
487 | break; | |
488 | case 2: | |
489 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
490 | break; | |
491 | case 0: | |
492 | default: | |
493 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
494 | break; | |
495 | } | |
a8d2a0c2 | 496 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); |
9d5c8243 AK |
497 | if (ret_val) |
498 | goto out; | |
499 | ||
500 | /* set auto-master slave resolution settings */ | |
501 | if (hw->mac.autoneg) { | |
502 | /* | |
503 | * when autonegotiation advertisement is only 1000Mbps then we | |
504 | * should disable SmartSpeed and enable Auto MasterSlave | |
505 | * resolution as hardware default. | |
506 | */ | |
507 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { | |
508 | /* Disable SmartSpeed */ | |
a8d2a0c2 AD |
509 | ret_val = phy->ops.read_reg(hw, |
510 | IGP01E1000_PHY_PORT_CONFIG, | |
511 | &data); | |
9d5c8243 AK |
512 | if (ret_val) |
513 | goto out; | |
514 | ||
515 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 516 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
517 | IGP01E1000_PHY_PORT_CONFIG, |
518 | data); | |
519 | if (ret_val) | |
520 | goto out; | |
521 | ||
522 | /* Set auto Master/Slave resolution process */ | |
a8d2a0c2 | 523 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
524 | if (ret_val) |
525 | goto out; | |
526 | ||
527 | data &= ~CR_1000T_MS_ENABLE; | |
a8d2a0c2 | 528 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
529 | if (ret_val) |
530 | goto out; | |
531 | } | |
532 | ||
a8d2a0c2 | 533 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
534 | if (ret_val) |
535 | goto out; | |
536 | ||
537 | /* load defaults for future use */ | |
538 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
539 | ((data & CR_1000T_MS_VALUE) ? | |
540 | e1000_ms_force_master : | |
541 | e1000_ms_force_slave) : | |
542 | e1000_ms_auto; | |
543 | ||
544 | switch (phy->ms_type) { | |
545 | case e1000_ms_force_master: | |
546 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
547 | break; | |
548 | case e1000_ms_force_slave: | |
549 | data |= CR_1000T_MS_ENABLE; | |
550 | data &= ~(CR_1000T_MS_VALUE); | |
551 | break; | |
552 | case e1000_ms_auto: | |
553 | data &= ~CR_1000T_MS_ENABLE; | |
554 | default: | |
555 | break; | |
556 | } | |
a8d2a0c2 | 557 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
558 | if (ret_val) |
559 | goto out; | |
560 | } | |
561 | ||
562 | out: | |
563 | return ret_val; | |
564 | } | |
565 | ||
566 | /** | |
733596be | 567 | * igb_copper_link_autoneg - Setup/Enable autoneg for copper link |
9d5c8243 AK |
568 | * @hw: pointer to the HW structure |
569 | * | |
570 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
571 | * configure to advertise the full capability. Setup the PHY to autoneg | |
572 | * and restart the negotiation process between the link partner. If | |
573 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. | |
574 | **/ | |
575 | s32 igb_copper_link_autoneg(struct e1000_hw *hw) | |
576 | { | |
577 | struct e1000_phy_info *phy = &hw->phy; | |
578 | s32 ret_val; | |
579 | u16 phy_ctrl; | |
580 | ||
581 | /* | |
582 | * Perform some bounds checking on the autoneg advertisement | |
583 | * parameter. | |
584 | */ | |
585 | phy->autoneg_advertised &= phy->autoneg_mask; | |
586 | ||
587 | /* | |
588 | * If autoneg_advertised is zero, we assume it was not defaulted | |
589 | * by the calling code so we set to advertise full capability. | |
590 | */ | |
591 | if (phy->autoneg_advertised == 0) | |
592 | phy->autoneg_advertised = phy->autoneg_mask; | |
593 | ||
652fff32 | 594 | hw_dbg("Reconfiguring auto-neg advertisement params\n"); |
9d5c8243 AK |
595 | ret_val = igb_phy_setup_autoneg(hw); |
596 | if (ret_val) { | |
652fff32 | 597 | hw_dbg("Error Setting up Auto-Negotiation\n"); |
9d5c8243 AK |
598 | goto out; |
599 | } | |
652fff32 | 600 | hw_dbg("Restarting Auto-Neg\n"); |
9d5c8243 AK |
601 | |
602 | /* | |
603 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
604 | * the Auto Neg Restart bit in the PHY control register. | |
605 | */ | |
a8d2a0c2 | 606 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
607 | if (ret_val) |
608 | goto out; | |
609 | ||
610 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
a8d2a0c2 | 611 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
612 | if (ret_val) |
613 | goto out; | |
614 | ||
615 | /* | |
616 | * Does the user want to wait for Auto-Neg to complete here, or | |
617 | * check at a later time (for example, callback routine). | |
618 | */ | |
619 | if (phy->autoneg_wait_to_complete) { | |
620 | ret_val = igb_wait_autoneg(hw); | |
621 | if (ret_val) { | |
652fff32 AK |
622 | hw_dbg("Error while waiting for " |
623 | "autoneg to complete\n"); | |
9d5c8243 AK |
624 | goto out; |
625 | } | |
626 | } | |
627 | ||
628 | hw->mac.get_link_status = true; | |
629 | ||
630 | out: | |
631 | return ret_val; | |
632 | } | |
633 | ||
634 | /** | |
733596be | 635 | * igb_phy_setup_autoneg - Configure PHY for auto-negotiation |
9d5c8243 AK |
636 | * @hw: pointer to the HW structure |
637 | * | |
638 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
639 | * register and if the PHY is already setup for auto-negotiation, then | |
640 | * return successful. Otherwise, setup advertisement and flow control to | |
641 | * the appropriate values for the wanted auto-negotiation. | |
642 | **/ | |
643 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) | |
644 | { | |
645 | struct e1000_phy_info *phy = &hw->phy; | |
646 | s32 ret_val; | |
647 | u16 mii_autoneg_adv_reg; | |
648 | u16 mii_1000t_ctrl_reg = 0; | |
649 | ||
650 | phy->autoneg_advertised &= phy->autoneg_mask; | |
651 | ||
652 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
a8d2a0c2 | 653 | ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
9d5c8243 AK |
654 | if (ret_val) |
655 | goto out; | |
656 | ||
657 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
658 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
a8d2a0c2 | 659 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, |
9d5c8243 AK |
660 | &mii_1000t_ctrl_reg); |
661 | if (ret_val) | |
662 | goto out; | |
663 | } | |
664 | ||
665 | /* | |
666 | * Need to parse both autoneg_advertised and fc and set up | |
667 | * the appropriate PHY registers. First we will parse for | |
668 | * autoneg_advertised software override. Since we can advertise | |
669 | * a plethora of combinations, we need to check each bit | |
670 | * individually. | |
671 | */ | |
672 | ||
673 | /* | |
674 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
675 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
676 | * the 1000Base-T Control Register (Address 9). | |
677 | */ | |
678 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
679 | NWAY_AR_100TX_HD_CAPS | | |
680 | NWAY_AR_10T_FD_CAPS | | |
681 | NWAY_AR_10T_HD_CAPS); | |
682 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
683 | ||
652fff32 | 684 | hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
9d5c8243 AK |
685 | |
686 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
687 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
652fff32 | 688 | hw_dbg("Advertise 10mb Half duplex\n"); |
9d5c8243 AK |
689 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
690 | } | |
691 | ||
692 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
693 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
652fff32 | 694 | hw_dbg("Advertise 10mb Full duplex\n"); |
9d5c8243 AK |
695 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
696 | } | |
697 | ||
698 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
699 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
652fff32 | 700 | hw_dbg("Advertise 100mb Half duplex\n"); |
9d5c8243 AK |
701 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
702 | } | |
703 | ||
704 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
705 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
652fff32 | 706 | hw_dbg("Advertise 100mb Full duplex\n"); |
9d5c8243 AK |
707 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
708 | } | |
709 | ||
710 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
711 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
652fff32 | 712 | hw_dbg("Advertise 1000mb Half duplex request denied!\n"); |
9d5c8243 AK |
713 | |
714 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
715 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
652fff32 | 716 | hw_dbg("Advertise 1000mb Full duplex\n"); |
9d5c8243 AK |
717 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
718 | } | |
719 | ||
720 | /* | |
721 | * Check for a software override of the flow control settings, and | |
722 | * setup the PHY advertisement registers accordingly. If | |
723 | * auto-negotiation is enabled, then software will have to set the | |
724 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
725 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
726 | * negotiation. | |
727 | * | |
728 | * The possible values of the "fc" parameter are: | |
729 | * 0: Flow control is completely disabled | |
730 | * 1: Rx flow control is enabled (we can receive pause frames | |
731 | * but not send pause frames). | |
732 | * 2: Tx flow control is enabled (we can send pause frames | |
733 | * but we do not support receiving pause frames). | |
734 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
735 | * other: No software override. The flow control configuration | |
736 | * in the EEPROM is used. | |
737 | */ | |
738 | switch (hw->fc.type) { | |
739 | case e1000_fc_none: | |
740 | /* | |
741 | * Flow control (RX & TX) is completely disabled by a | |
742 | * software over-ride. | |
743 | */ | |
744 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
745 | break; | |
746 | case e1000_fc_rx_pause: | |
747 | /* | |
748 | * RX Flow control is enabled, and TX Flow control is | |
749 | * disabled, by a software over-ride. | |
750 | * | |
751 | * Since there really isn't a way to advertise that we are | |
752 | * capable of RX Pause ONLY, we will advertise that we | |
753 | * support both symmetric and asymmetric RX PAUSE. Later | |
754 | * (in e1000_config_fc_after_link_up) we will disable the | |
755 | * hw's ability to send PAUSE frames. | |
756 | */ | |
757 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
758 | break; | |
759 | case e1000_fc_tx_pause: | |
760 | /* | |
761 | * TX Flow control is enabled, and RX Flow control is | |
762 | * disabled, by a software over-ride. | |
763 | */ | |
764 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
765 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
766 | break; | |
767 | case e1000_fc_full: | |
768 | /* | |
769 | * Flow control (both RX and TX) is enabled by a software | |
770 | * over-ride. | |
771 | */ | |
772 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
773 | break; | |
774 | default: | |
652fff32 | 775 | hw_dbg("Flow control param set incorrectly\n"); |
9d5c8243 AK |
776 | ret_val = -E1000_ERR_CONFIG; |
777 | goto out; | |
778 | } | |
779 | ||
a8d2a0c2 | 780 | ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
9d5c8243 AK |
781 | if (ret_val) |
782 | goto out; | |
783 | ||
652fff32 | 784 | hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
9d5c8243 AK |
785 | |
786 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
a8d2a0c2 AD |
787 | ret_val = phy->ops.write_reg(hw, |
788 | PHY_1000T_CTRL, | |
789 | mii_1000t_ctrl_reg); | |
9d5c8243 AK |
790 | if (ret_val) |
791 | goto out; | |
792 | } | |
793 | ||
794 | out: | |
795 | return ret_val; | |
796 | } | |
797 | ||
798 | /** | |
733596be | 799 | * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
9d5c8243 AK |
800 | * @hw: pointer to the HW structure |
801 | * | |
802 | * Calls the PHY setup function to force speed and duplex. Clears the | |
803 | * auto-crossover to force MDI manually. Waits for link and returns | |
804 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
805 | **/ | |
806 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
807 | { | |
808 | struct e1000_phy_info *phy = &hw->phy; | |
809 | s32 ret_val; | |
810 | u16 phy_data; | |
811 | bool link; | |
812 | ||
a8d2a0c2 | 813 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
814 | if (ret_val) |
815 | goto out; | |
816 | ||
817 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
818 | ||
a8d2a0c2 | 819 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
820 | if (ret_val) |
821 | goto out; | |
822 | ||
823 | /* | |
824 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
825 | * forced whenever speed and duplex are forced. | |
826 | */ | |
a8d2a0c2 | 827 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
9d5c8243 AK |
828 | if (ret_val) |
829 | goto out; | |
830 | ||
831 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
832 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
833 | ||
a8d2a0c2 | 834 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
9d5c8243 AK |
835 | if (ret_val) |
836 | goto out; | |
837 | ||
652fff32 | 838 | hw_dbg("IGP PSCR: %X\n", phy_data); |
9d5c8243 AK |
839 | |
840 | udelay(1); | |
841 | ||
842 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 843 | hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
9d5c8243 AK |
844 | |
845 | ret_val = igb_phy_has_link(hw, | |
846 | PHY_FORCE_LIMIT, | |
847 | 100000, | |
848 | &link); | |
849 | if (ret_val) | |
850 | goto out; | |
851 | ||
852 | if (!link) | |
652fff32 | 853 | hw_dbg("Link taking longer than expected.\n"); |
9d5c8243 AK |
854 | |
855 | /* Try once more */ | |
856 | ret_val = igb_phy_has_link(hw, | |
857 | PHY_FORCE_LIMIT, | |
858 | 100000, | |
859 | &link); | |
860 | if (ret_val) | |
861 | goto out; | |
862 | } | |
863 | ||
864 | out: | |
865 | return ret_val; | |
866 | } | |
867 | ||
868 | /** | |
733596be | 869 | * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
9d5c8243 AK |
870 | * @hw: pointer to the HW structure |
871 | * | |
872 | * Calls the PHY setup function to force speed and duplex. Clears the | |
873 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
874 | * changes. If time expires while waiting for link up, we reset the DSP. | |
875 | * After reset, TX_CLK and CRS on TX must be set. Return successful upon | |
876 | * successful completion, else return corresponding error code. | |
877 | **/ | |
878 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
879 | { | |
880 | struct e1000_phy_info *phy = &hw->phy; | |
881 | s32 ret_val; | |
882 | u16 phy_data; | |
883 | bool link; | |
884 | ||
885 | /* | |
886 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
887 | * forced whenever speed and duplex are forced. | |
888 | */ | |
a8d2a0c2 | 889 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
890 | if (ret_val) |
891 | goto out; | |
892 | ||
893 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
a8d2a0c2 | 894 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
895 | if (ret_val) |
896 | goto out; | |
897 | ||
652fff32 | 898 | hw_dbg("M88E1000 PSCR: %X\n", phy_data); |
9d5c8243 | 899 | |
a8d2a0c2 | 900 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
901 | if (ret_val) |
902 | goto out; | |
903 | ||
904 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
905 | ||
906 | /* Reset the phy to commit changes. */ | |
907 | phy_data |= MII_CR_RESET; | |
908 | ||
a8d2a0c2 | 909 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
910 | if (ret_val) |
911 | goto out; | |
912 | ||
913 | udelay(1); | |
914 | ||
915 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 916 | hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
9d5c8243 AK |
917 | |
918 | ret_val = igb_phy_has_link(hw, | |
919 | PHY_FORCE_LIMIT, | |
920 | 100000, | |
921 | &link); | |
922 | if (ret_val) | |
923 | goto out; | |
924 | ||
925 | if (!link) { | |
926 | /* | |
927 | * We didn't get link. | |
928 | * Reset the DSP and cross our fingers. | |
929 | */ | |
a8d2a0c2 | 930 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
931 | M88E1000_PHY_PAGE_SELECT, |
932 | 0x001d); | |
933 | if (ret_val) | |
934 | goto out; | |
935 | ret_val = igb_phy_reset_dsp(hw); | |
936 | if (ret_val) | |
937 | goto out; | |
938 | } | |
939 | ||
940 | /* Try once more */ | |
941 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, | |
942 | 100000, &link); | |
943 | if (ret_val) | |
944 | goto out; | |
945 | } | |
946 | ||
a8d2a0c2 | 947 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
948 | if (ret_val) |
949 | goto out; | |
950 | ||
951 | /* | |
952 | * Resetting the phy means we need to re-force TX_CLK in the | |
953 | * Extended PHY Specific Control Register to 25MHz clock from | |
954 | * the reset value of 2.5MHz. | |
955 | */ | |
956 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
a8d2a0c2 | 957 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
958 | if (ret_val) |
959 | goto out; | |
960 | ||
961 | /* | |
962 | * In addition, we must re-enable CRS on Tx for both half and full | |
963 | * duplex. | |
964 | */ | |
a8d2a0c2 | 965 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
966 | if (ret_val) |
967 | goto out; | |
968 | ||
969 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
a8d2a0c2 | 970 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
971 | |
972 | out: | |
973 | return ret_val; | |
974 | } | |
975 | ||
976 | /** | |
733596be | 977 | * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
9d5c8243 AK |
978 | * @hw: pointer to the HW structure |
979 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
980 | * | |
981 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
982 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
983 | * disable auto-negotiation, configure duplex, configure speed, configure | |
984 | * the collision distance, write configuration to CTRL register. The | |
985 | * caller must write to the PHY_CONTROL register for these settings to | |
986 | * take affect. | |
987 | **/ | |
988 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
989 | u16 *phy_ctrl) | |
990 | { | |
991 | struct e1000_mac_info *mac = &hw->mac; | |
992 | u32 ctrl; | |
993 | ||
994 | /* Turn off flow control when forcing speed/duplex */ | |
995 | hw->fc.type = e1000_fc_none; | |
996 | ||
997 | /* Force speed/duplex on the mac */ | |
998 | ctrl = rd32(E1000_CTRL); | |
999 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1000 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1001 | ||
1002 | /* Disable Auto Speed Detection */ | |
1003 | ctrl &= ~E1000_CTRL_ASDE; | |
1004 | ||
1005 | /* Disable autoneg on the phy */ | |
1006 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1007 | ||
1008 | /* Forcing Full or Half Duplex? */ | |
1009 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1010 | ctrl &= ~E1000_CTRL_FD; | |
1011 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
652fff32 | 1012 | hw_dbg("Half Duplex\n"); |
9d5c8243 AK |
1013 | } else { |
1014 | ctrl |= E1000_CTRL_FD; | |
1015 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
652fff32 | 1016 | hw_dbg("Full Duplex\n"); |
9d5c8243 AK |
1017 | } |
1018 | ||
1019 | /* Forcing 10mb or 100mb? */ | |
1020 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1021 | ctrl |= E1000_CTRL_SPD_100; | |
1022 | *phy_ctrl |= MII_CR_SPEED_100; | |
1023 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
652fff32 | 1024 | hw_dbg("Forcing 100mb\n"); |
9d5c8243 AK |
1025 | } else { |
1026 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1027 | *phy_ctrl |= MII_CR_SPEED_10; | |
1028 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
652fff32 | 1029 | hw_dbg("Forcing 10mb\n"); |
9d5c8243 AK |
1030 | } |
1031 | ||
1032 | igb_config_collision_dist(hw); | |
1033 | ||
1034 | wr32(E1000_CTRL, ctrl); | |
1035 | } | |
1036 | ||
1037 | /** | |
733596be | 1038 | * igb_set_d3_lplu_state - Sets low power link up state for D3 |
9d5c8243 AK |
1039 | * @hw: pointer to the HW structure |
1040 | * @active: boolean used to enable/disable lplu | |
1041 | * | |
1042 | * Success returns 0, Failure returns 1 | |
1043 | * | |
1044 | * The low power link up (lplu) state is set to the power management level D3 | |
1045 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1046 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1047 | * is used during Dx states where the power conservation is most important. | |
1048 | * During driver activity, SmartSpeed should be enabled so performance is | |
1049 | * maintained. | |
1050 | **/ | |
1051 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1052 | { | |
1053 | struct e1000_phy_info *phy = &hw->phy; | |
1054 | s32 ret_val; | |
1055 | u16 data; | |
1056 | ||
a8d2a0c2 | 1057 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
1058 | if (ret_val) |
1059 | goto out; | |
1060 | ||
1061 | if (!active) { | |
1062 | data &= ~IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1063 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1064 | data); |
1065 | if (ret_val) | |
1066 | goto out; | |
1067 | /* | |
1068 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
1069 | * during Dx states where the power conservation is most | |
1070 | * important. During driver activity we should enable | |
1071 | * SmartSpeed, so performance is maintained. | |
1072 | */ | |
1073 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 1074 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1075 | IGP01E1000_PHY_PORT_CONFIG, |
1076 | &data); | |
1077 | if (ret_val) | |
1078 | goto out; | |
1079 | ||
1080 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1081 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1082 | IGP01E1000_PHY_PORT_CONFIG, |
1083 | data); | |
1084 | if (ret_val) | |
1085 | goto out; | |
1086 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 1087 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1088 | IGP01E1000_PHY_PORT_CONFIG, |
1089 | &data); | |
1090 | if (ret_val) | |
1091 | goto out; | |
1092 | ||
1093 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1094 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1095 | IGP01E1000_PHY_PORT_CONFIG, |
1096 | data); | |
1097 | if (ret_val) | |
1098 | goto out; | |
1099 | } | |
1100 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1101 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1102 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1103 | data |= IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1104 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1105 | data); |
1106 | if (ret_val) | |
1107 | goto out; | |
1108 | ||
1109 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 1110 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
9d5c8243 AK |
1111 | &data); |
1112 | if (ret_val) | |
1113 | goto out; | |
1114 | ||
1115 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1116 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
9d5c8243 AK |
1117 | data); |
1118 | } | |
1119 | ||
1120 | out: | |
1121 | return ret_val; | |
1122 | } | |
1123 | ||
1124 | /** | |
733596be | 1125 | * igb_check_downshift - Checks whether a downshift in speed occured |
9d5c8243 AK |
1126 | * @hw: pointer to the HW structure |
1127 | * | |
1128 | * Success returns 0, Failure returns 1 | |
1129 | * | |
1130 | * A downshift is detected by querying the PHY link health. | |
1131 | **/ | |
1132 | s32 igb_check_downshift(struct e1000_hw *hw) | |
1133 | { | |
1134 | struct e1000_phy_info *phy = &hw->phy; | |
1135 | s32 ret_val; | |
1136 | u16 phy_data, offset, mask; | |
1137 | ||
1138 | switch (phy->type) { | |
1139 | case e1000_phy_m88: | |
1140 | case e1000_phy_gg82563: | |
1141 | offset = M88E1000_PHY_SPEC_STATUS; | |
1142 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1143 | break; | |
1144 | case e1000_phy_igp_2: | |
1145 | case e1000_phy_igp: | |
1146 | case e1000_phy_igp_3: | |
1147 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1148 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1149 | break; | |
1150 | default: | |
1151 | /* speed downshift not supported */ | |
1152 | phy->speed_downgraded = false; | |
1153 | ret_val = 0; | |
1154 | goto out; | |
1155 | } | |
1156 | ||
a8d2a0c2 | 1157 | ret_val = phy->ops.read_reg(hw, offset, &phy_data); |
9d5c8243 AK |
1158 | |
1159 | if (!ret_val) | |
1160 | phy->speed_downgraded = (phy_data & mask) ? true : false; | |
1161 | ||
1162 | out: | |
1163 | return ret_val; | |
1164 | } | |
1165 | ||
1166 | /** | |
733596be | 1167 | * igb_check_polarity_m88 - Checks the polarity. |
9d5c8243 AK |
1168 | * @hw: pointer to the HW structure |
1169 | * | |
1170 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1171 | * | |
1172 | * Polarity is determined based on the PHY specific status register. | |
1173 | **/ | |
1174 | static s32 igb_check_polarity_m88(struct e1000_hw *hw) | |
1175 | { | |
1176 | struct e1000_phy_info *phy = &hw->phy; | |
1177 | s32 ret_val; | |
1178 | u16 data; | |
1179 | ||
a8d2a0c2 | 1180 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); |
9d5c8243 AK |
1181 | |
1182 | if (!ret_val) | |
1183 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1184 | ? e1000_rev_polarity_reversed | |
1185 | : e1000_rev_polarity_normal; | |
1186 | ||
1187 | return ret_val; | |
1188 | } | |
1189 | ||
1190 | /** | |
733596be | 1191 | * igb_check_polarity_igp - Checks the polarity. |
9d5c8243 AK |
1192 | * @hw: pointer to the HW structure |
1193 | * | |
1194 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1195 | * | |
1196 | * Polarity is determined based on the PHY port status register, and the | |
1197 | * current speed (since there is no polarity at 100Mbps). | |
1198 | **/ | |
1199 | static s32 igb_check_polarity_igp(struct e1000_hw *hw) | |
1200 | { | |
1201 | struct e1000_phy_info *phy = &hw->phy; | |
1202 | s32 ret_val; | |
1203 | u16 data, offset, mask; | |
1204 | ||
1205 | /* | |
1206 | * Polarity is determined based on the speed of | |
1207 | * our connection. | |
1208 | */ | |
a8d2a0c2 | 1209 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1210 | if (ret_val) |
1211 | goto out; | |
1212 | ||
1213 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1214 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1215 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1216 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1217 | } else { | |
1218 | /* | |
1219 | * This really only applies to 10Mbps since | |
1220 | * there is no polarity for 100Mbps (always 0). | |
1221 | */ | |
1222 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1223 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1224 | } | |
1225 | ||
a8d2a0c2 | 1226 | ret_val = phy->ops.read_reg(hw, offset, &data); |
9d5c8243 AK |
1227 | |
1228 | if (!ret_val) | |
1229 | phy->cable_polarity = (data & mask) | |
1230 | ? e1000_rev_polarity_reversed | |
1231 | : e1000_rev_polarity_normal; | |
1232 | ||
1233 | out: | |
1234 | return ret_val; | |
1235 | } | |
1236 | ||
1237 | /** | |
733596be | 1238 | * igb_wait_autoneg - Wait for auto-neg compeletion |
9d5c8243 AK |
1239 | * @hw: pointer to the HW structure |
1240 | * | |
1241 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1242 | * limit to expire, which ever happens first. | |
1243 | **/ | |
1244 | static s32 igb_wait_autoneg(struct e1000_hw *hw) | |
1245 | { | |
1246 | s32 ret_val = 0; | |
1247 | u16 i, phy_status; | |
1248 | ||
1249 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1250 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
a8d2a0c2 | 1251 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1252 | if (ret_val) |
1253 | break; | |
a8d2a0c2 | 1254 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1255 | if (ret_val) |
1256 | break; | |
1257 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1258 | break; | |
1259 | msleep(100); | |
1260 | } | |
1261 | ||
1262 | /* | |
1263 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
1264 | * has completed. | |
1265 | */ | |
1266 | return ret_val; | |
1267 | } | |
1268 | ||
1269 | /** | |
733596be | 1270 | * igb_phy_has_link - Polls PHY for link |
9d5c8243 AK |
1271 | * @hw: pointer to the HW structure |
1272 | * @iterations: number of times to poll for link | |
1273 | * @usec_interval: delay between polling attempts | |
1274 | * @success: pointer to whether polling was successful or not | |
1275 | * | |
1276 | * Polls the PHY status register for link, 'iterations' number of times. | |
1277 | **/ | |
1278 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, | |
1279 | u32 usec_interval, bool *success) | |
1280 | { | |
1281 | s32 ret_val = 0; | |
1282 | u16 i, phy_status; | |
1283 | ||
1284 | for (i = 0; i < iterations; i++) { | |
1285 | /* | |
1286 | * Some PHYs require the PHY_STATUS register to be read | |
1287 | * twice due to the link bit being sticky. No harm doing | |
1288 | * it across the board. | |
1289 | */ | |
a8d2a0c2 | 1290 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1291 | if (ret_val) |
1292 | break; | |
a8d2a0c2 | 1293 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1294 | if (ret_val) |
1295 | break; | |
1296 | if (phy_status & MII_SR_LINK_STATUS) | |
1297 | break; | |
1298 | if (usec_interval >= 1000) | |
1299 | mdelay(usec_interval/1000); | |
1300 | else | |
1301 | udelay(usec_interval); | |
1302 | } | |
1303 | ||
1304 | *success = (i < iterations) ? true : false; | |
1305 | ||
1306 | return ret_val; | |
1307 | } | |
1308 | ||
1309 | /** | |
733596be | 1310 | * igb_get_cable_length_m88 - Determine cable length for m88 PHY |
9d5c8243 AK |
1311 | * @hw: pointer to the HW structure |
1312 | * | |
1313 | * Reads the PHY specific status register to retrieve the cable length | |
1314 | * information. The cable length is determined by averaging the minimum and | |
1315 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1316 | * possible cable length values, which are: | |
1317 | * Register Value Cable Length | |
1318 | * 0 < 50 meters | |
1319 | * 1 50 - 80 meters | |
1320 | * 2 80 - 110 meters | |
1321 | * 3 110 - 140 meters | |
1322 | * 4 > 140 meters | |
1323 | **/ | |
1324 | s32 igb_get_cable_length_m88(struct e1000_hw *hw) | |
1325 | { | |
1326 | struct e1000_phy_info *phy = &hw->phy; | |
1327 | s32 ret_val; | |
1328 | u16 phy_data, index; | |
1329 | ||
a8d2a0c2 | 1330 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1331 | if (ret_val) |
1332 | goto out; | |
1333 | ||
1334 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1335 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
1336 | phy->min_cable_length = e1000_m88_cable_length_table[index]; | |
1337 | phy->max_cable_length = e1000_m88_cable_length_table[index+1]; | |
1338 | ||
1339 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1340 | ||
1341 | out: | |
1342 | return ret_val; | |
1343 | } | |
1344 | ||
1345 | /** | |
733596be | 1346 | * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
9d5c8243 AK |
1347 | * @hw: pointer to the HW structure |
1348 | * | |
1349 | * The automatic gain control (agc) normalizes the amplitude of the | |
1350 | * received signal, adjusting for the attenuation produced by the | |
a8d2a0c2 AD |
1351 | * cable. By reading the AGC registers, which represent the |
1352 | * combination of coarse and fine gain value, the value can be put | |
9d5c8243 AK |
1353 | * into a lookup table to obtain the approximate cable length |
1354 | * for each channel. | |
1355 | **/ | |
1356 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) | |
1357 | { | |
1358 | struct e1000_phy_info *phy = &hw->phy; | |
1359 | s32 ret_val = 0; | |
1360 | u16 phy_data, i, agc_value = 0; | |
1361 | u16 cur_agc_index, max_agc_index = 0; | |
1362 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
1363 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
1364 | {IGP02E1000_PHY_AGC_A, | |
1365 | IGP02E1000_PHY_AGC_B, | |
1366 | IGP02E1000_PHY_AGC_C, | |
1367 | IGP02E1000_PHY_AGC_D}; | |
1368 | ||
1369 | /* Read the AGC registers for all channels */ | |
1370 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
a8d2a0c2 | 1371 | ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); |
9d5c8243 AK |
1372 | if (ret_val) |
1373 | goto out; | |
1374 | ||
1375 | /* | |
1376 | * Getting bits 15:9, which represent the combination of | |
a8d2a0c2 | 1377 | * coarse and fine gain values. The result is a number |
9d5c8243 AK |
1378 | * that can be put into the lookup table to obtain the |
1379 | * approximate cable length. | |
1380 | */ | |
1381 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | |
1382 | IGP02E1000_AGC_LENGTH_MASK; | |
1383 | ||
1384 | /* Array index bound check. */ | |
1385 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1386 | (cur_agc_index == 0)) { | |
1387 | ret_val = -E1000_ERR_PHY; | |
1388 | goto out; | |
1389 | } | |
1390 | ||
1391 | /* Remove min & max AGC values from calculation. */ | |
1392 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1393 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1394 | min_agc_index = cur_agc_index; | |
1395 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1396 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1397 | max_agc_index = cur_agc_index; | |
1398 | ||
1399 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1400 | } | |
1401 | ||
1402 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1403 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1404 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1405 | ||
1406 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1407 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1408 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1409 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1410 | ||
1411 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1412 | ||
1413 | out: | |
1414 | return ret_val; | |
1415 | } | |
1416 | ||
1417 | /** | |
733596be | 1418 | * igb_get_phy_info_m88 - Retrieve PHY information |
9d5c8243 AK |
1419 | * @hw: pointer to the HW structure |
1420 | * | |
1421 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1422 | * to verify that link is up. Read the PHY special control register to | |
1423 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1424 | * special status register to determine MDI/MDIx and current speed. If | |
1425 | * speed is 1000, then determine cable length, local and remote receiver. | |
1426 | **/ | |
1427 | s32 igb_get_phy_info_m88(struct e1000_hw *hw) | |
1428 | { | |
1429 | struct e1000_phy_info *phy = &hw->phy; | |
1430 | s32 ret_val; | |
1431 | u16 phy_data; | |
1432 | bool link; | |
1433 | ||
a8d2a0c2 | 1434 | if (phy->media_type != e1000_media_type_copper) { |
652fff32 | 1435 | hw_dbg("Phy info is only valid for copper media\n"); |
9d5c8243 AK |
1436 | ret_val = -E1000_ERR_CONFIG; |
1437 | goto out; | |
1438 | } | |
1439 | ||
1440 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1441 | if (ret_val) | |
1442 | goto out; | |
1443 | ||
1444 | if (!link) { | |
652fff32 | 1445 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1446 | ret_val = -E1000_ERR_CONFIG; |
1447 | goto out; | |
1448 | } | |
1449 | ||
a8d2a0c2 | 1450 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1451 | if (ret_val) |
1452 | goto out; | |
1453 | ||
1454 | phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) | |
a8d2a0c2 | 1455 | ? true : false; |
9d5c8243 AK |
1456 | |
1457 | ret_val = igb_check_polarity_m88(hw); | |
1458 | if (ret_val) | |
1459 | goto out; | |
1460 | ||
a8d2a0c2 | 1461 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1462 | if (ret_val) |
1463 | goto out; | |
1464 | ||
1465 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; | |
1466 | ||
1467 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
a8d2a0c2 | 1468 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1469 | if (ret_val) |
1470 | goto out; | |
1471 | ||
a8d2a0c2 | 1472 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); |
9d5c8243 AK |
1473 | if (ret_val) |
1474 | goto out; | |
1475 | ||
1476 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1477 | ? e1000_1000t_rx_status_ok | |
1478 | : e1000_1000t_rx_status_not_ok; | |
1479 | ||
1480 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1481 | ? e1000_1000t_rx_status_ok | |
1482 | : e1000_1000t_rx_status_not_ok; | |
1483 | } else { | |
1484 | /* Set values to "undefined" */ | |
1485 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1486 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1487 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1488 | } | |
1489 | ||
1490 | out: | |
1491 | return ret_val; | |
1492 | } | |
1493 | ||
1494 | /** | |
733596be | 1495 | * igb_get_phy_info_igp - Retrieve igp PHY information |
9d5c8243 AK |
1496 | * @hw: pointer to the HW structure |
1497 | * | |
1498 | * Read PHY status to determine if link is up. If link is up, then | |
1499 | * set/determine 10base-T extended distance and polarity correction. Read | |
1500 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1501 | * determine on the cable length, local and remote receiver. | |
1502 | **/ | |
1503 | s32 igb_get_phy_info_igp(struct e1000_hw *hw) | |
1504 | { | |
1505 | struct e1000_phy_info *phy = &hw->phy; | |
1506 | s32 ret_val; | |
1507 | u16 data; | |
1508 | bool link; | |
1509 | ||
1510 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1511 | if (ret_val) | |
1512 | goto out; | |
1513 | ||
1514 | if (!link) { | |
652fff32 | 1515 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1516 | ret_val = -E1000_ERR_CONFIG; |
1517 | goto out; | |
1518 | } | |
1519 | ||
1520 | phy->polarity_correction = true; | |
1521 | ||
1522 | ret_val = igb_check_polarity_igp(hw); | |
1523 | if (ret_val) | |
1524 | goto out; | |
1525 | ||
a8d2a0c2 | 1526 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1527 | if (ret_val) |
1528 | goto out; | |
1529 | ||
1530 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; | |
1531 | ||
1532 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1533 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
a8d2a0c2 | 1534 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1535 | if (ret_val) |
1536 | goto out; | |
1537 | ||
a8d2a0c2 | 1538 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
9d5c8243 AK |
1539 | if (ret_val) |
1540 | goto out; | |
1541 | ||
1542 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
1543 | ? e1000_1000t_rx_status_ok | |
1544 | : e1000_1000t_rx_status_not_ok; | |
1545 | ||
1546 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
1547 | ? e1000_1000t_rx_status_ok | |
1548 | : e1000_1000t_rx_status_not_ok; | |
1549 | } else { | |
1550 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1551 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1552 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1553 | } | |
1554 | ||
1555 | out: | |
1556 | return ret_val; | |
1557 | } | |
1558 | ||
1559 | /** | |
733596be | 1560 | * igb_phy_sw_reset - PHY software reset |
9d5c8243 AK |
1561 | * @hw: pointer to the HW structure |
1562 | * | |
1563 | * Does a software reset of the PHY by reading the PHY control register and | |
1564 | * setting/write the control register reset bit to the PHY. | |
1565 | **/ | |
1566 | s32 igb_phy_sw_reset(struct e1000_hw *hw) | |
1567 | { | |
1568 | s32 ret_val; | |
1569 | u16 phy_ctrl; | |
1570 | ||
a8d2a0c2 | 1571 | ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
1572 | if (ret_val) |
1573 | goto out; | |
1574 | ||
1575 | phy_ctrl |= MII_CR_RESET; | |
a8d2a0c2 | 1576 | ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
1577 | if (ret_val) |
1578 | goto out; | |
1579 | ||
1580 | udelay(1); | |
1581 | ||
1582 | out: | |
1583 | return ret_val; | |
1584 | } | |
1585 | ||
1586 | /** | |
733596be | 1587 | * igb_phy_hw_reset - PHY hardware reset |
9d5c8243 AK |
1588 | * @hw: pointer to the HW structure |
1589 | * | |
1590 | * Verify the reset block is not blocking us from resetting. Acquire | |
1591 | * semaphore (if necessary) and read/set/write the device control reset | |
1592 | * bit in the PHY. Wait the appropriate delay time for the device to | |
1593 | * reset and relase the semaphore (if necessary). | |
1594 | **/ | |
1595 | s32 igb_phy_hw_reset(struct e1000_hw *hw) | |
1596 | { | |
1597 | struct e1000_phy_info *phy = &hw->phy; | |
1598 | s32 ret_val; | |
1599 | u32 ctrl; | |
1600 | ||
1601 | ret_val = igb_check_reset_block(hw); | |
1602 | if (ret_val) { | |
1603 | ret_val = 0; | |
1604 | goto out; | |
1605 | } | |
1606 | ||
a8d2a0c2 | 1607 | ret_val = phy->ops.acquire(hw); |
9d5c8243 AK |
1608 | if (ret_val) |
1609 | goto out; | |
1610 | ||
1611 | ctrl = rd32(E1000_CTRL); | |
1612 | wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); | |
1613 | wrfl(); | |
1614 | ||
1615 | udelay(phy->reset_delay_us); | |
1616 | ||
1617 | wr32(E1000_CTRL, ctrl); | |
1618 | wrfl(); | |
1619 | ||
1620 | udelay(150); | |
1621 | ||
a8d2a0c2 | 1622 | phy->ops.release(hw); |
9d5c8243 | 1623 | |
a8d2a0c2 | 1624 | ret_val = phy->ops.get_cfg_done(hw); |
9d5c8243 AK |
1625 | |
1626 | out: | |
1627 | return ret_val; | |
1628 | } | |
1629 | ||
9d5c8243 | 1630 | /** |
733596be | 1631 | * igb_phy_init_script_igp3 - Inits the IGP3 PHY |
9d5c8243 AK |
1632 | * @hw: pointer to the HW structure |
1633 | * | |
1634 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
1635 | **/ | |
1636 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw) | |
1637 | { | |
652fff32 | 1638 | hw_dbg("Running IGP 3 PHY init script\n"); |
9d5c8243 AK |
1639 | |
1640 | /* PHY init IGP 3 */ | |
1641 | /* Enable rise/fall, 10-mode work in class-A */ | |
a8d2a0c2 | 1642 | hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); |
9d5c8243 | 1643 | /* Remove all caps from Replica path filter */ |
a8d2a0c2 | 1644 | hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); |
9d5c8243 | 1645 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
a8d2a0c2 | 1646 | hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); |
9d5c8243 | 1647 | /* Increase Hybrid poly bias */ |
a8d2a0c2 | 1648 | hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); |
9d5c8243 | 1649 | /* Add 4% to TX amplitude in Giga mode */ |
a8d2a0c2 | 1650 | hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); |
9d5c8243 | 1651 | /* Disable trimming (TTT) */ |
a8d2a0c2 | 1652 | hw->phy.ops.write_reg(hw, 0x2011, 0x0000); |
9d5c8243 | 1653 | /* Poly DC correction to 94.6% + 2% for all channels */ |
a8d2a0c2 | 1654 | hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); |
9d5c8243 | 1655 | /* ABS DC correction to 95.9% */ |
a8d2a0c2 | 1656 | hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); |
9d5c8243 | 1657 | /* BG temp curve trim */ |
a8d2a0c2 | 1658 | hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); |
9d5c8243 | 1659 | /* Increasing ADC OPAMP stage 1 currents to max */ |
a8d2a0c2 | 1660 | hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); |
9d5c8243 | 1661 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
a8d2a0c2 | 1662 | hw->phy.ops.write_reg(hw, 0x0000, 0x0140); |
9d5c8243 | 1663 | /* Set upd_freq to 6 */ |
a8d2a0c2 | 1664 | hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); |
9d5c8243 | 1665 | /* Disable NPDFE */ |
a8d2a0c2 | 1666 | hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); |
9d5c8243 | 1667 | /* Disable adaptive fixed FFE (Default) */ |
a8d2a0c2 | 1668 | hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); |
9d5c8243 | 1669 | /* Enable FFE hysteresis */ |
a8d2a0c2 | 1670 | hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); |
9d5c8243 | 1671 | /* Fixed FFE for short cable lengths */ |
a8d2a0c2 | 1672 | hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); |
9d5c8243 | 1673 | /* Fixed FFE for medium cable lengths */ |
a8d2a0c2 | 1674 | hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); |
9d5c8243 | 1675 | /* Fixed FFE for long cable lengths */ |
a8d2a0c2 | 1676 | hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); |
9d5c8243 | 1677 | /* Enable Adaptive Clip Threshold */ |
a8d2a0c2 | 1678 | hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); |
9d5c8243 | 1679 | /* AHT reset limit to 1 */ |
a8d2a0c2 | 1680 | hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); |
9d5c8243 | 1681 | /* Set AHT master delay to 127 msec */ |
a8d2a0c2 | 1682 | hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); |
9d5c8243 | 1683 | /* Set scan bits for AHT */ |
a8d2a0c2 | 1684 | hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); |
9d5c8243 | 1685 | /* Set AHT Preset bits */ |
a8d2a0c2 | 1686 | hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); |
9d5c8243 | 1687 | /* Change integ_factor of channel A to 3 */ |
a8d2a0c2 | 1688 | hw->phy.ops.write_reg(hw, 0x1895, 0x0003); |
9d5c8243 | 1689 | /* Change prop_factor of channels BCD to 8 */ |
a8d2a0c2 | 1690 | hw->phy.ops.write_reg(hw, 0x1796, 0x0008); |
9d5c8243 | 1691 | /* Change cg_icount + enable integbp for channels BCD */ |
a8d2a0c2 | 1692 | hw->phy.ops.write_reg(hw, 0x1798, 0xD008); |
9d5c8243 AK |
1693 | /* |
1694 | * Change cg_icount + enable integbp + change prop_factor_master | |
1695 | * to 8 for channel A | |
1696 | */ | |
a8d2a0c2 | 1697 | hw->phy.ops.write_reg(hw, 0x1898, 0xD918); |
9d5c8243 | 1698 | /* Disable AHT in Slave mode on channel A */ |
a8d2a0c2 | 1699 | hw->phy.ops.write_reg(hw, 0x187A, 0x0800); |
9d5c8243 AK |
1700 | /* |
1701 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
1702 | * Enable SPD+B2B | |
1703 | */ | |
a8d2a0c2 | 1704 | hw->phy.ops.write_reg(hw, 0x0019, 0x008D); |
9d5c8243 | 1705 | /* Enable restart AN on an1000_dis change */ |
a8d2a0c2 | 1706 | hw->phy.ops.write_reg(hw, 0x001B, 0x2080); |
9d5c8243 | 1707 | /* Enable wh_fifo read clock in 10/100 modes */ |
a8d2a0c2 | 1708 | hw->phy.ops.write_reg(hw, 0x0014, 0x0045); |
9d5c8243 | 1709 | /* Restart AN, Speed selection is 1000 */ |
a8d2a0c2 | 1710 | hw->phy.ops.write_reg(hw, 0x0000, 0x1340); |
9d5c8243 AK |
1711 | |
1712 | return 0; | |
1713 | } | |
1714 |