[deliverable/linux.git] / drivers / net / igb / e1000_regs.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_REGS_H_
#define _E1000_REGS_H_

#define E1000_CTRL     0x00000  /* Device Control - RW */
#define E1000_STATUS   0x00008  /* Device Status - RO */
#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
#define E1000_EERD     0x00014  /* EEPROM Read - RW */
#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
#define E1000_MDIC     0x00020  /* MDI Control - RW */
#define E1000_SCTL     0x00024  /* SerDes Control - RW */
#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
#define E1000_FCT      0x00030  /* Flow Control Type - RW */
#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
#define E1000_RCTL     0x00100  /* RX Control - RW */
#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
#define E1000_GPIE     0x01514  /* General Purpose Interrupt Enable - RW */
#define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
#define E1000_TCTL     0x00400  /* TX Control - RW */
#define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
#define E1000_PBS      0x01008  /* Packet Buffer Size */
#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */
#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */

/* IEEE 1588 TIMESYNCH */
#define E1000_TSYNCTXCTL 0x0B614
#define E1000_TSYNCTXCTL_VALID (1<<0)
#define E1000_TSYNCTXCTL_ENABLED (1<<4)
#define E1000_TSYNCRXCTL 0x0B620
#define E1000_TSYNCRXCTL_VALID (1<<0)
#define E1000_TSYNCRXCTL_ENABLED (1<<4)
enum {
	E1000_TSYNCRXCTL_TYPE_L2_V2 = 0,
	E1000_TSYNCRXCTL_TYPE_L4_V1 = (1<<1),
	E1000_TSYNCRXCTL_TYPE_L2_L4_V2 = (1<<2),
	E1000_TSYNCRXCTL_TYPE_ALL = (1<<3),
	E1000_TSYNCRXCTL_TYPE_EVENT_V2 = (1<<3) | (1<<1),
};
#define E1000_TSYNCRXCFG 0x05F50
enum {
	E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE = 0<<0,
	E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE = 1<<0,
	E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE = 2<<0,
	E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE = 3<<0,
	E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE = 4<<0,

	E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE = 0<<8,
	E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE = 1<<8,
	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE = 2<<8,
	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE = 3<<8,
	E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE = 8<<8,
	E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE = 9<<8,
	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE = 0xA<<8,
	E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE = 0xB<<8,
	E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE = 0xC<<8,
	E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE = 0xD<<8,
};
#define E1000_SYSTIML 0x0B600
#define E1000_SYSTIMH 0x0B604
#define E1000_TIMINCA 0x0B608

#define E1000_RXMTRL     0x0B634
#define E1000_RXSTMPL 0x0B624
#define E1000_RXSTMPH 0x0B628
#define E1000_RXSATRL 0x0B62C
#define E1000_RXSATRH 0x0B630

#define E1000_TXSTMPL 0x0B618
#define E1000_TXSTMPH 0x0B61C

#define E1000_ETQF0   0x05CB0
#define E1000_ETQF1   0x05CB4
#define E1000_ETQF2   0x05CB8
#define E1000_ETQF3   0x05CBC
#define E1000_ETQF4   0x05CC0
#define E1000_ETQF5   0x05CC4
#define E1000_ETQF6   0x05CC8
#define E1000_ETQF7   0x05CCC

/* Filtering Registers */
#define E1000_SAQF(_n) (0x5980 + 4 * (_n))
#define E1000_DAQF(_n) (0x59A0 + 4 * (_n))
#define E1000_SPQF(_n) (0x59C0 + 4 * (_n))
#define E1000_FTQF(_n) (0x59E0 + 4 * (_n))
#define E1000_SAQF0 E1000_SAQF(0)
#define E1000_DAQF0 E1000_DAQF(0)
#define E1000_SPQF0 E1000_SPQF(0)
#define E1000_FTQF0 E1000_FTQF(0)
#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
#define E1000_ETQF(_n)  (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */

#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
/* Split and Replication RX Control - RW */
/*
 * Convenience macros
 *
 * Note: "_n" is the queue number of the register to be written to.
 *
 * Example usage:
 * E1000_RDBAL_REG(current_rx_queue)
 */
#define E1000_RDBAL(_n)   ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \
				    : (0x0C000 + ((_n) * 0x40)))
#define E1000_RDBAH(_n)   ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \
				    : (0x0C004 + ((_n) * 0x40)))
#define E1000_RDLEN(_n)   ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \
				    : (0x0C008 + ((_n) * 0x40)))
#define E1000_SRRCTL(_n)  ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \
				    : (0x0C00C + ((_n) * 0x40)))
#define E1000_RDH(_n)     ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \
				    : (0x0C010 + ((_n) * 0x40)))
#define E1000_RDT(_n)     ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \
				    : (0x0C018 + ((_n) * 0x40)))
#define E1000_RXDCTL(_n)  ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \
				    : (0x0C028 + ((_n) * 0x40)))
#define E1000_TDBAL(_n)   ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \
				    : (0x0E000 + ((_n) * 0x40)))
#define E1000_TDBAH(_n)   ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \
				    : (0x0E004 + ((_n) * 0x40)))
#define E1000_TDLEN(_n)   ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \
				    : (0x0E008 + ((_n) * 0x40)))
#define E1000_TDH(_n)     ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \
				    : (0x0E010 + ((_n) * 0x40)))
#define E1000_TDT(_n)     ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \
				    : (0x0E018 + ((_n) * 0x40)))
#define E1000_TXDCTL(_n)  ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
				    : (0x0E028 + ((_n) * 0x40)))
#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
#define E1000_TDWBAL(_n)  ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
				    : (0x0E038 + ((_n) * 0x40)))
#define E1000_TDWBAH(_n)  ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \
				    : (0x0E03C + ((_n) * 0x40)))
#define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
#define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
#define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
#define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
#define E1000_DTXCTL   0x03590  /* DMA TX Control - RW */
#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
#define E1000_COLC     0x04028  /* Collision Count - R/clr */
#define E1000_DC       0x04030  /* Defer Count - R/clr */
#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
/* Interrupt Cause Rx Packet Timer Expire Count */
#define E1000_ICRXPTC  0x04104
/* Interrupt Cause Rx Absolute Timer Expire Count */
#define E1000_ICRXATC  0x04108
/* Interrupt Cause Tx Packet Timer Expire Count */
#define E1000_ICTXPTC  0x0410C
/* Interrupt Cause Tx Absolute Timer Expire Count */
#define E1000_ICTXATC  0x04110
/* Interrupt Cause Tx Queue Empty Count */
#define E1000_ICTXQEC  0x04118
/* Interrupt Cause Tx Queue Minimum Threshold Count */
#define E1000_ICTXQMTC 0x0411C
/* Interrupt Cause Rx Descriptor Minimum Threshold Count */
#define E1000_ICRXDMTC 0x04120
#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
#define E1000_CBTMPC      0x0402C  /* Circuit Breaker TX Packet Count */
#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
#define E1000_CBRMPC      0x040FC  /* Circuit Breaker RX Packet Count */
#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
#define E1000_HGPTC       0x04118  /* Host Good Packets TX Count */
#define E1000_HTCBDPC     0x04124  /* Host TX Circuit Breaker Dropped Count */
#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
#define E1000_LENERRS     0x04138  /* Length Errors Count */
#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
#define E1000_RLPML    0x05004  /* RX Long Packet Max Length */
#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
#define E1000_RA       0x05400  /* Receive Address - RW Array */
#define E1000_RA2      0x054E0  /* 2nd half of receive address array - RW Array */
#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
                                       (0x054E0 + ((_i - 16) * 8)))
#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
                                       (0x054E4 + ((_i - 16) * 8)))
#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
#define E1000_WUC      0x05800  /* Wakeup Control - RW */
#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
#define E1000_WUS      0x05810  /* Wakeup Status - RO */
#define E1000_MANC     0x05820  /* Management Control - RW */
#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */

#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
#define E1000_SWSM      0x05B50 /* SW Semaphore */
#define E1000_FWSM      0x05B54 /* FW Semaphore */
#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */

/* RSS registers */
#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
/* MSI-X Allocation Register (_i) - RW */
#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4))
/* Redirection Table - RW Array */
#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4))
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */

/* VT Registers */
#define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
#define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
#define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
#define E1000_VFRE      0x00C8C /* VF Receive Enables */
#define E1000_VFTE      0x00C90 /* VF Transmit Enables */
#define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
#define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
#define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
#define E1000_IOVTCL    0x05BBC /* IOV Control Register */
/* These act per VF so an array friendly macro is used */
#define E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
#define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
#define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))
#define E1000_VLVF(_n)         (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
                                                       * Filter - RW */

#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
#define rd32(reg) (readl(hw->hw_addr + reg))
#define wrfl() ((void)rd32(E1000_STATUS))

#define array_wr32(reg, offset, value) \
	(writel(value, hw->hw_addr + reg + ((offset) << 2)))
#define array_rd32(reg, offset) \
	(readl(hw->hw_addr + reg + ((offset) << 2)))

#endif
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _E1000_REGS_H_
	29	#define _E1000_REGS_H_
	30
	31	#define E1000_CTRL 0x00000 /* Device Control - RW */
	32	#define E1000_STATUS 0x00008 /* Device Status - RO */
	33	#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
	34	#define E1000_EERD 0x00014 /* EEPROM Read - RW */
	35	#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
	36	#define E1000_MDIC 0x00020 /* MDI Control - RW */
	37	#define E1000_SCTL 0x00024 /* SerDes Control - RW */
	38	#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
	39	#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
	40	#define E1000_FCT 0x00030 /* Flow Control Type - RW */
	41	#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
	42	#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
	43	#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
	44	#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
	45	#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
	46	#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
	47	#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
	48	#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
	49	#define E1000_RCTL 0x00100 /* RX Control - RW */
	50	#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
	51	#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
	52	#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
	53	#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
	54	#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
	55	#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
	56	#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
	57	#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
	58	#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
2d064c06 AD	59	#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
	60	#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
	61	#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
9d5c8243 AK	62	#define E1000_TCTL 0x00400 /* TX Control - RW */
	63	#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
	64	#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
	65	#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
	66	#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
	67	#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
	68	#define E1000_PBS 0x01008 /* Packet Buffer Size */
	69	#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
	70	#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
	71	#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
	72	#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
	73	#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
	74	#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
	75	#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
9d5c8243	76	#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
38c845c7 PO	77
	78	/* IEEE 1588 TIMESYNCH */
	79	#define E1000_TSYNCTXCTL 0x0B614
33af6bcc PO	80	#define E1000_TSYNCTXCTL_VALID (1<<0)
33af6bcc PO	81	#define E1000_TSYNCTXCTL_ENABLED (1<<4)
38c845c7	82	#define E1000_TSYNCRXCTL 0x0B620
33af6bcc PO	83	#define E1000_TSYNCRXCTL_VALID (1<<0)
	84	#define E1000_TSYNCRXCTL_ENABLED (1<<4)
	85	enum {
	86	E1000_TSYNCRXCTL_TYPE_L2_V2 = 0,
	87	E1000_TSYNCRXCTL_TYPE_L4_V1 = (1<<1),
	88	E1000_TSYNCRXCTL_TYPE_L2_L4_V2 = (1<<2),
	89	E1000_TSYNCRXCTL_TYPE_ALL = (1<<3),
	90	E1000_TSYNCRXCTL_TYPE_EVENT_V2 = (1<<3) \| (1<<1),
	91	};
38c845c7	92	#define E1000_TSYNCRXCFG 0x05F50
33af6bcc PO	93	enum {
	94	E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE = 0<<0,
	95	E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE = 1<<0,
	96	E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE = 2<<0,
	97	E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE = 3<<0,
	98	E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE = 4<<0,
38c845c7	99
33af6bcc PO	100	E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE = 0<<8,
	101	E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE = 1<<8,
	102	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE = 2<<8,
	103	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE = 3<<8,
	104	E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE = 8<<8,
	105	E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE = 9<<8,
	106	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE = 0xA<<8,
	107	E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE = 0xB<<8,
	108	E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE = 0xC<<8,
	109	E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE = 0xD<<8,
	110	};
38c845c7 PO	111	#define E1000_SYSTIML 0x0B600
	112	#define E1000_SYSTIMH 0x0B604
	113	#define E1000_TIMINCA 0x0B608
	114
	115	#define E1000_RXMTRL 0x0B634
	116	#define E1000_RXSTMPL 0x0B624
	117	#define E1000_RXSTMPH 0x0B628
	118	#define E1000_RXSATRL 0x0B62C
	119	#define E1000_RXSATRH 0x0B630
	120
	121	#define E1000_TXSTMPL 0x0B618
	122	#define E1000_TXSTMPH 0x0B61C
	123
	124	#define E1000_ETQF0 0x05CB0
	125	#define E1000_ETQF1 0x05CB4
	126	#define E1000_ETQF2 0x05CB8
	127	#define E1000_ETQF3 0x05CBC
	128	#define E1000_ETQF4 0x05CC0
	129	#define E1000_ETQF5 0x05CC4
	130	#define E1000_ETQF6 0x05CC8
	131	#define E1000_ETQF7 0x05CCC
	132
33af6bcc PO	133	/* Filtering Registers */
	134	#define E1000_SAQF(_n) (0x5980 + 4 * (_n))
	135	#define E1000_DAQF(_n) (0x59A0 + 4 * (_n))
	136	#define E1000_SPQF(_n) (0x59C0 + 4 * (_n))
	137	#define E1000_FTQF(_n) (0x59E0 + 4 * (_n))
	138	#define E1000_SAQF0 E1000_SAQF(0)
	139	#define E1000_DAQF0 E1000_DAQF(0)
	140	#define E1000_SPQF0 E1000_SPQF(0)
	141	#define E1000_FTQF0 E1000_FTQF(0)
	142	#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
	143	#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
	144
3c514ce2	145	#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
9d5c8243 AK	146	/* Split and Replication RX Control - RW */
	147	/*
	148	* Convenience macros
	149	*
	150	* Note: "_n" is the queue number of the register to be written to.
	151	*
	152	* Example usage:
	153	* E1000_RDBAL_REG(current_rx_queue)
	154	*/
	155	#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \
	156	: (0x0C000 + ((_n) * 0x40)))
	157	#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \
	158	: (0x0C004 + ((_n) * 0x40)))
	159	#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \
	160	: (0x0C008 + ((_n) * 0x40)))
	161	#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \
	162	: (0x0C00C + ((_n) * 0x40)))
	163	#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \
	164	: (0x0C010 + ((_n) * 0x40)))
	165	#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \
	166	: (0x0C018 + ((_n) * 0x40)))
	167	#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \
	168	: (0x0C028 + ((_n) * 0x40)))
	169	#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \
	170	: (0x0E000 + ((_n) * 0x40)))
	171	#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \
	172	: (0x0E004 + ((_n) * 0x40)))
	173	#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \
	174	: (0x0E008 + ((_n) * 0x40)))
	175	#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \
	176	: (0x0E010 + ((_n) * 0x40)))
	177	#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \
	178	: (0x0E018 + ((_n) * 0x40)))
	179	#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
	180	: (0x0E028 + ((_n) * 0x40)))
9d5c8243 AK	181	#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
	182	#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
	183	#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
	184	: (0x0E038 + ((_n) * 0x40)))
	185	#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \
	186	: (0x0E03C + ((_n) * 0x40)))
	187	#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
	188	#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
	189	#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
	190	#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
	191	#define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */
	192	#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
	193	#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
	194	#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
	195	#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
	196	#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
	197	#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
	198	#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
	199	#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
	200	#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
	201	#define E1000_COLC 0x04028 /* Collision Count - R/clr */
	202	#define E1000_DC 0x04030 /* Defer Count - R/clr */
	203	#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
	204	#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
	205	#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
	206	#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
	207	#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
	208	#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
	209	#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
	210	#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
	211	#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
	212	#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
	213	#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
	214	#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
	215	#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
	216	#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
	217	#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
	218	#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
	219	#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
	220	#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
	221	#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
	222	#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
	223	#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
	224	#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
	225	#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
	226	#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
	227	#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
	228	#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
	229	#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
	230	#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
	231	#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
	232	#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
	233	#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
	234	#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
	235	#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
	236	#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
	237	#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
	238	#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
	239	#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
	240	#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
	241	#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
	242	#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
	243	#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
	244	#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
245	#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
246	#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
247	#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
248	#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
249	#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
250	#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
251	/* Interrupt Cause Rx Packet Timer Expire Count */
252	#define E1000_ICRXPTC 0x04104
253	/* Interrupt Cause Rx Absolute Timer Expire Count */
254	#define E1000_ICRXATC 0x04108
255	/* Interrupt Cause Tx Packet Timer Expire Count */
256	#define E1000_ICTXPTC 0x0410C
257	/* Interrupt Cause Tx Absolute Timer Expire Count */
258	#define E1000_ICTXATC 0x04110
259	/* Interrupt Cause Tx Queue Empty Count */
260	#define E1000_ICTXQEC 0x04118
261	/* Interrupt Cause Tx Queue Minimum Threshold Count */
262	#define E1000_ICTXQMTC 0x0411C
263	/* Interrupt Cause Rx Descriptor Minimum Threshold Count */
264	#define E1000_ICRXDMTC 0x04120
265	#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
266	#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
267	#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
268	#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
269	#define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */
270	#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
271	#define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */
272	#define E1000_RPTHC 0x04104 /* Rx Packets To Host */
273	#define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */
274	#define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */
275	#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
276	#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
277	#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
278	#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
279	#define E1000_LENERRS 0x04138 /* Length Errors Count */
280	#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
281	#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
282	#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
283	#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
284	#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
285	#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
286	#define E1000_RLPML 0x05004 /* RX Long Packet Max Length */
287	#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
288	#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
289	#define E1000_RA 0x05400 /* Receive Address - RW Array */
2d064c06	290	#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */
5e8427e5 AD	291	#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
	292	(0x054E0 + ((_i - 16) * 8)))
	293	#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
	294	(0x054E4 + ((_i - 16) * 8)))
9d5c8243	295	#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
e1739522	296	#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
9d5c8243 AK	297	#define E1000_WUC 0x05800 /* Wakeup Control - RW */
	298	#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
	299	#define E1000_WUS 0x05810 /* Wakeup Status - RO */
	300	#define E1000_MANC 0x05820 /* Management Control - RW */
	301	#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
	302	#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
9d5c8243	303
9d5c8243 AK	304	#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
	305	#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
	306	#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
	307	#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
	308	#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
	309	#define E1000_SWSM 0x05B50 /* SW Semaphore */
	310	#define E1000_FWSM 0x05B54 /* FW Semaphore */
fe4506b6	311	#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
9d5c8243 AK	312
	313	/* RSS registers */
	314	#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
	315	#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
	316	#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
	317	#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
	318	/* MSI-X Allocation Register (_i) - RW */
	319	#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
9d5c8243 AK	320	/* Redirection Table - RW Array */
	321	#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
	322	#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
	323
e1739522	324	/* VT Registers */
4ae196df AD	325	#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
	326	#define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
	327	#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
	328	#define E1000_VFRE 0x00C8C /* VF Receive Enables */
	329	#define E1000_VFTE 0x00C90 /* VF Transmit Enables */
e1739522	330	#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
4ae196df AD	331	#define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
	332	#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
	333	#define E1000_IOVTCL 0x05BBC /* IOV Control Register */
e1739522	334	/* These act per VF so an array friendly macro is used */
4ae196df AD	335	#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
4ae196df AD	336	#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
e1739522	337	#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
4ae196df AD	338	#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
4ae196df AD	339	* Filter - RW */
e1739522	340
9d5c8243 AK	341	#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
	342	#define rd32(reg) (readl(hw->hw_addr + reg))
	343	#define wrfl() ((void)rd32(E1000_STATUS))
	344
	345	#define array_wr32(reg, offset, value) \
	346	(writel(value, hw->hw_addr + reg + ((offset) << 2)))
	347	#define array_rd32(reg, offset) \
	348	(readl(hw->hw_addr + reg + ((offset) << 2)))
	349
	350	#endif