[deliverable/linux.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
                               (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
#define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
#define IGB_ABS_MAX_TX_QUEUES     4

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	bool clear_to_send;
};

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                    (hw->mac.type <= e1000_82576 ? 16 : 8)
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
                                             adapter->msix_entries) ? 0 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_16384 16384

#define MAX_STD_JUMBO_FRAME_SIZE 9234

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
		};
		/* RX */
		struct {
			struct page *page;
			u64 page_dma;
			unsigned int page_offset;
		};
	};
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;

	u16 itr_val;
	u8 set_itr;
	u8 itr_shift;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector; /* backlink to q_vector */
	struct net_device *netdev;     /* back pointer to net_device */
	struct pci_dev *pdev;          /* pci device for dma mapping */
	dma_addr_t dma;                /* phys address of the ring */
	void *desc;                    /* descriptor ring memory */
	unsigned int size;             /* length of desc. ring in bytes */
	unsigned int count;            /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	void __iomem *head;
	void __iomem *tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	u8 queue_index;
	u8 reg_idx;

	unsigned int total_bytes;
	unsigned int total_packets;

	u32 flags;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			u32 rx_buffer_len;
		};
	};
};

#define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
#define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */

#define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */

#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))

/* board specific private data structure */

struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;
	unsigned int total_tx_bytes;
	unsigned int total_tx_packets;
	unsigned int total_rx_bytes;
	unsigned int total_rx_packets;
	/* Interrupt Throttle Rate */
	u32 itr;
	u32 itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring;      /* One per active queue */
	unsigned long tx_queue_len;
	u32 gotc;
	u64 gotc_old;
	u64 tpt_old;
	u64 colc_old;
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring;      /* One per active queue */
	int num_tx_queues;
	int num_rx_queues;

	u32 gorc;
	u64 gorc_old;
	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	unsigned int num_q_vectors;
	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)

enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_update_stats(struct igb_adapter *);
extern void igb_set_ethtool_ops(struct net_device *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
38c845c7	40
9d5c8243 AK	41	struct igb_adapter;
9d5c8243 AK	42
6eb5a7f1 AD	43	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	44	#define IGB_START_ITR 648
9d5c8243	45
9d5c8243 AK	46	/* TX/RX descriptor defines */
	47	#define IGB_DEFAULT_TXD 256
	48	#define IGB_MIN_TXD 80
	49	#define IGB_MAX_TXD 4096
	50
	51	#define IGB_DEFAULT_RXD 256
	52	#define IGB_MIN_RXD 80
	53	#define IGB_MAX_RXD 4096
	54
	55	#define IGB_DEFAULT_ITR 3 /* dynamic */
	56	#define IGB_MAX_ITR_USECS 10000
	57	#define IGB_MIN_ITR_USECS 10
047e0030 AD	58	#define NON_Q_VECTORS 1
047e0030 AD	59	#define MAX_Q_VECTORS 8
9d5c8243 AK	60
9d5c8243 AK	61	/* Transmit and receive queues */
1bfaf07b AD	62	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \
	63	(adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
	64	#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
	65	#define IGB_ABS_MAX_TX_QUEUES 4
9d5c8243	66
4ae196df AD	67	#define IGB_MAX_VF_MC_ENTRIES 30
	68	#define IGB_MAX_VF_FUNCTIONS 8
	69	#define IGB_MAX_VFTA_ENTRIES 128
	70
	71	struct vf_data_storage {
	72	unsigned char vf_mac_addresses[ETH_ALEN];
	73	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	74	u16 num_vf_mc_hashes;
ae641bdc	75	u16 vlans_enabled;
4ae196df AD	76	bool clear_to_send;
	77	};
	78
9d5c8243 AK	79	/* RX descriptor control thresholds.
	80	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	81	* descriptors available in its onboard memory.
	82	* Setting this to 0 disables RX descriptor prefetch.
	83	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	84	* available in host memory.
	85	* If PTHRESH is 0, this should also be 0.
	86	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	87	* descriptors until either it has this many to write back, or the
	88	* ITR timer expires.
	89	*/
85b430b4	90	#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
9d5c8243 AK	91	#define IGB_RX_HTHRESH 8
9d5c8243 AK	92	#define IGB_RX_WTHRESH 1
85b430b4 AD	93	#define IGB_TX_PTHRESH 8
	94	#define IGB_TX_HTHRESH 1
	95	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
	96	adapter->msix_entries) ? 0 : 16)
9d5c8243 AK	97
	98	/* this is the size past which hardware will drop packets when setting LPE=0 */
	99	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	100
	101	/* Supported Rx Buffer Sizes */
	102	#define IGB_RXBUFFER_128 128 /* Used for packet split */
9d5c8243 AK	103	#define IGB_RXBUFFER_1024 1024
9d5c8243 AK	104	#define IGB_RXBUFFER_2048 2048
9d5c8243 AK	105	#define IGB_RXBUFFER_16384 16384
9d5c8243 AK	106
e1739522	107	#define MAX_STD_JUMBO_FRAME_SIZE 9234
9d5c8243 AK	108
	109	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	110	#define IGB_TX_QUEUE_WAKE 16
	111	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	112	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	113
	114	#define AUTO_ALL_MODES 0
	115	#define IGB_EEPROM_APME 0x0400
	116
	117	#ifndef IGB_MASTER_SLAVE
	118	/* Switch to override PHY master/slave setting */
	119	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	120	#endif
	121
	122	#define IGB_MNG_VLAN_NONE -1
	123
	124	/* wrapper around a pointer to a socket buffer,
	125	* so a DMA handle can be stored along with the buffer */
	126	struct igb_buffer {
	127	struct sk_buff *skb;
	128	dma_addr_t dma;
	129	union {
	130	/* TX */
	131	struct {
	132	unsigned long time_stamp;
0e014cb1 AD	133	u16 length;
0e014cb1 AD	134	u16 next_to_watch;
9d5c8243 AK	135	};
	136	/* RX */
	137	struct {
	138	struct page *page;
	139	u64 page_dma;
bf36c1a0	140	unsigned int page_offset;
9d5c8243 AK	141	};
	142	};
	143	};
	144
8c0ab70a	145	struct igb_tx_queue_stats {
9d5c8243 AK	146	u64 packets;
9d5c8243 AK	147	u64 bytes;
04a5fcaa	148	u64 restart_queue;
9d5c8243 AK	149	};
9d5c8243 AK	150
8c0ab70a JDB	151	struct igb_rx_queue_stats {
	152	u64 packets;
	153	u64 bytes;
	154	u64 drops;
04a5fcaa AD	155	u64 csum_err;
04a5fcaa AD	156	u64 alloc_failed;
8c0ab70a JDB	157	};
8c0ab70a JDB	158
047e0030	159	struct igb_q_vector {
9d5c8243	160	struct igb_adapter adapter; / backlink */
047e0030 AD	161	struct igb_ring *rx_ring;
	162	struct igb_ring *tx_ring;
	163	struct napi_struct napi;
	164
	165	u32 eims_value;
	166	u16 cpu;
	167
	168	u16 itr_val;
	169	u8 set_itr;
	170	u8 itr_shift;
	171	void __iomem *itr_register;
	172
	173	char name[IFNAMSIZ + 9];
	174	};
	175
	176	struct igb_ring {
	177	struct igb_q_vector q_vector; / backlink to q_vector */
e694e964	178	struct net_device netdev; / back pointer to net_device */
80785298	179	struct pci_dev pdev; / pci device for dma mapping */
047e0030	180	dma_addr_t dma; /* phys address of the ring */
e694e964	181	void desc; / descriptor ring memory */
047e0030 AD	182	unsigned int size; /* length of desc. ring in bytes */
047e0030 AD	183	unsigned int count; /* number of desc. in the ring */
9d5c8243 AK	184	u16 next_to_use;
9d5c8243 AK	185	u16 next_to_clean;
fce99e34 AD	186	void __iomem *head;
fce99e34 AD	187	void __iomem *tail;
9d5c8243 AK	188	struct igb_buffer buffer_info; / array of buffer info structs */
9d5c8243 AK	189
047e0030 AD	190	u8 queue_index;
047e0030 AD	191	u8 reg_idx;
9d5c8243 AK	192
	193	unsigned int total_bytes;
	194	unsigned int total_packets;
	195
85ad76b2 AD	196	u32 flags;
85ad76b2 AD	197
9d5c8243 AK	198	union {
	199	/* TX */
	200	struct {
8c0ab70a	201	struct igb_tx_queue_stats tx_stats;
9d5c8243 AK	202	bool detect_tx_hung;
	203	};
	204	/* RX */
	205	struct {
8c0ab70a	206	struct igb_rx_queue_stats rx_stats;
4c844851	207	u32 rx_buffer_len;
9d5c8243 AK	208	};
9d5c8243 AK	209	};
9d5c8243 AK	210	};
9d5c8243 AK	211
85ad76b2 AD	212	#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
	213	#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
	214
	215	#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
	216
	217	#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP \| E1000_TXD_CMD_RS)
	218
9d5c8243 AK	219	#define E1000_RX_DESC_ADV(R, i) \
	220	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	221	#define E1000_TX_DESC_ADV(R, i) \
	222	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	223	#define E1000_TX_CTXTDESC_ADV(R, i) \
	224	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
9d5c8243 AK	225
	226	/* board specific private data structure */
	227
	228	struct igb_adapter {
	229	struct timer_list watchdog_timer;
	230	struct timer_list phy_info_timer;
	231	struct vlan_group *vlgrp;
	232	u16 mng_vlan_id;
	233	u32 bd_number;
9d5c8243 AK	234	u32 wol;
	235	u32 en_mng_pt;
	236	u16 link_speed;
	237	u16 link_duplex;
	238	unsigned int total_tx_bytes;
	239	unsigned int total_tx_packets;
	240	unsigned int total_rx_bytes;
	241	unsigned int total_rx_packets;
	242	/* Interrupt Throttle Rate */
	243	u32 itr;
	244	u32 itr_setting;
	245	u16 tx_itr;
	246	u16 rx_itr;
9d5c8243 AK	247
	248	struct work_struct reset_task;
	249	struct work_struct watchdog_task;
	250	bool fc_autoneg;
	251	u8 tx_timeout_factor;
	252	struct timer_list blink_timer;
	253	unsigned long led_status;
	254
	255	/* TX */
	256	struct igb_ring tx_ring; / One per active queue */
9d5c8243	257	unsigned long tx_queue_len;
9d5c8243 AK	258	u32 gotc;
	259	u64 gotc_old;
	260	u64 tpt_old;
	261	u64 colc_old;
	262	u32 tx_timeout_count;
	263
	264	/* RX */
	265	struct igb_ring rx_ring; / One per active queue */
	266	int num_tx_queues;
	267	int num_rx_queues;
	268
9d5c8243 AK	269	u32 gorc;
9d5c8243 AK	270	u64 gorc_old;
9d5c8243 AK	271	u32 max_frame_size;
	272	u32 min_frame_size;
	273
	274	/* OS defined structs */
	275	struct net_device *netdev;
9d5c8243	276	struct pci_dev *pdev;
38c845c7 PO	277	struct cyclecounter cycles;
38c845c7 PO	278	struct timecounter clock;
33af6bcc PO	279	struct timecompare compare;
33af6bcc PO	280	struct hwtstamp_config hwtstamp_config;
9d5c8243 AK	281
	282	/* structs defined in e1000_hw.h */
	283	struct e1000_hw hw;
	284	struct e1000_hw_stats stats;
	285	struct e1000_phy_info phy_info;
	286	struct e1000_phy_stats phy_stats;
	287
	288	u32 test_icr;
	289	struct igb_ring test_tx_ring;
	290	struct igb_ring test_rx_ring;
	291
	292	int msg_enable;
047e0030 AD	293
	294	unsigned int num_q_vectors;
	295	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243 AK	296	struct msix_entry *msix_entries;
9d5c8243 AK	297	u32 eims_enable_mask;
844290e5	298	u32 eims_other;
9d5c8243 AK	299
	300	/* to not mess up cache alignment, always add to the bottom */
	301	unsigned long state;
7dfc16fa	302	unsigned int flags;
9d5c8243	303	u32 eeprom_wol;
42bfd33a	304
1bfaf07b	305	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
68fd9910 AD	306	unsigned int tx_ring_count;
68fd9910 AD	307	unsigned int rx_ring_count;
1bfaf07b	308	unsigned int vfs_allocated_count;
4ae196df	309	struct vf_data_storage *vf_data;
9d5c8243 AK	310	};
9d5c8243 AK	311
7dfc16fa	312	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	313	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	314	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
7dfc16fa	315
9d5c8243 AK	316	enum e1000_state_t {
	317	__IGB_TESTING,
	318	__IGB_RESETTING,
	319	__IGB_DOWN
	320	};
	321
	322	enum igb_boards {
	323	board_82575,
	324	};
	325
	326	extern char igb_driver_name[];
	327	extern char igb_driver_version[];
	328
	329	extern char igb_get_hw_dev_name(struct e1000_hw hw);
	330	extern int igb_up(struct igb_adapter *);
	331	extern void igb_down(struct igb_adapter *);
	332	extern void igb_reinit_locked(struct igb_adapter *);
	333	extern void igb_reset(struct igb_adapter *);
	334	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
80785298 AD	335	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	336	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	337	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	338	extern void igb_free_rx_resources(struct igb_ring *);
9d5c8243 AK	339	extern void igb_update_stats(struct igb_adapter *);
	340	extern void igb_set_ethtool_ops(struct net_device *);
	341
f5f4cf08 AD	342	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	343	{
a8d2a0c2 AD	344	if (hw->phy.ops.reset)
a8d2a0c2 AD	345	return hw->phy.ops.reset(hw);
f5f4cf08 AD	346
	347	return 0;
	348	}
	349
	350	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	351	{
a8d2a0c2 AD	352	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	353	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	354
	355	return 0;
	356	}
	357
	358	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	359	{
a8d2a0c2 AD	360	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	361	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	362
	363	return 0;
	364	}
	365
	366	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	367	{
	368	if (hw->phy.ops.get_phy_info)
	369	return hw->phy.ops.get_phy_info(hw);
	370
	371	return 0;
	372	}
	373
9d5c8243	374	#endif /* _IGB_H_ */