[deliverable/linux.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

struct igb_adapter;

/* Interrupt defines */
#define IGB_MAX_TX_CLEAN 72

#define IGB_MIN_DYN_ITR 3000
#define IGB_MAX_DYN_ITR 96000
#define IGB_START_ITR 6000

#define IGB_DYN_ITR_PACKET_THRESHOLD 2
#define IGB_DYN_ITR_LENGTH_LOW 200
#define IGB_DYN_ITR_LENGTH_HIGH 1000

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  4
#define IGB_MAX_TX_QUEUES                  4

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                    16
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_256   256    /* Used for packet split */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_4096  4096
#define IGB_RXBUFFER_8192  8192
#define IGB_RXBUFFER_16384 16384

/* Packet Buffer allocations */


/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u32 length;
		};
		/* RX */
		struct {
			struct page *page;
			u64 page_dma;
		};
	};
};

struct igb_queue_stats {
	u64 packets;
	u64 bytes;
};

struct igb_ring {
	struct igb_adapter *adapter; /* backlink */
	void *desc;                  /* descriptor ring memory */
	dma_addr_t dma;              /* phys address of the ring */
	unsigned int size;           /* length of desc. ring in bytes */
	unsigned int count;          /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	u16 head;
	u16 tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	u32 eims_value;
	u32 itr_val;
	u16 itr_register;
	u16 cpu;

	int queue_index;
	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_queue_stats tx_stats;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			/* arrays of page information for packet split */
			struct sk_buff *pending_skb;
			int pending_skb_page;
			int no_itr_adjust;
			struct igb_queue_stats rx_stats;
			struct napi_struct napi;
		};
	};

	char name[IFNAMSIZ + 5];
};

#define IGB_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)

/* board specific private data structure */

struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 rx_buffer_len;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;
	unsigned int total_tx_bytes;
	unsigned int total_tx_packets;
	unsigned int total_rx_bytes;
	unsigned int total_rx_packets;
	/* Interrupt Throttle Rate */
	u32 itr;
	u32 itr_setting;
	u16 tx_itr;
	u16 rx_itr;
	int set_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring;      /* One per active queue */
	unsigned int restart_queue;
	unsigned long tx_queue_len;
	u32 txd_cmd;
	u32 gotc;
	u64 gotc_old;
	u64 tpt_old;
	u64 colc_old;
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring;      /* One per active queue */
	int num_tx_queues;
	int num_rx_queues;

	u64 hw_csum_err;
	u64 hw_csum_good;
	u64 rx_hdr_split;
	u32 alloc_rx_buff_failed;
	bool rx_csum;
	u32 gorc;
	u64 gorc_old;
	u16 rx_ps_hdr_size;
	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct napi_struct napi;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int msi_enabled;
#ifdef CONFIG_DCA
	unsigned int dca_enabled;
#endif
	u32 eeprom_wol;

	/* for ioport free */
	int bars;
	int need_ioport;

#ifdef CONFIG_NETDEVICES_MULTIQUEUE
	struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
};

enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
extern void igb_update_stats(struct igb_adapter *);
extern void igb_set_ethtool_ops(struct net_device *);

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
	4	Copyright(c) 2007 Intel Corporation.
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
	37	struct igb_adapter;
	38
	39	/* Interrupt defines */
	40	#define IGB_MAX_TX_CLEAN 72
	41
	42	#define IGB_MIN_DYN_ITR 3000
	43	#define IGB_MAX_DYN_ITR 96000
	44	#define IGB_START_ITR 6000
	45
	46	#define IGB_DYN_ITR_PACKET_THRESHOLD 2
	47	#define IGB_DYN_ITR_LENGTH_LOW 200
	48	#define IGB_DYN_ITR_LENGTH_HIGH 1000
	49
	50	/* TX/RX descriptor defines */
	51	#define IGB_DEFAULT_TXD 256
	52	#define IGB_MIN_TXD 80
	53	#define IGB_MAX_TXD 4096
	54
	55	#define IGB_DEFAULT_RXD 256
	56	#define IGB_MIN_RXD 80
	57	#define IGB_MAX_RXD 4096
	58
	59	#define IGB_DEFAULT_ITR 3 /* dynamic */
	60	#define IGB_MAX_ITR_USECS 10000
	61	#define IGB_MIN_ITR_USECS 10
	62
	63	/* Transmit and receive queues */
	64	#define IGB_MAX_RX_QUEUES 4
661086df	65	#define IGB_MAX_TX_QUEUES 4
9d5c8243 AK	66
	67	/* RX descriptor control thresholds.
	68	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	69	* descriptors available in its onboard memory.
	70	* Setting this to 0 disables RX descriptor prefetch.
	71	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	72	* available in host memory.
	73	* If PTHRESH is 0, this should also be 0.
	74	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	75	* descriptors until either it has this many to write back, or the
	76	* ITR timer expires.
	77	*/
	78	#define IGB_RX_PTHRESH 16
	79	#define IGB_RX_HTHRESH 8
	80	#define IGB_RX_WTHRESH 1
	81
	82	/* this is the size past which hardware will drop packets when setting LPE=0 */
	83	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	84
	85	/* Supported Rx Buffer Sizes */
	86	#define IGB_RXBUFFER_128 128 /* Used for packet split */
	87	#define IGB_RXBUFFER_256 256 /* Used for packet split */
	88	#define IGB_RXBUFFER_512 512
	89	#define IGB_RXBUFFER_1024 1024
	90	#define IGB_RXBUFFER_2048 2048
	91	#define IGB_RXBUFFER_4096 4096
	92	#define IGB_RXBUFFER_8192 8192
	93	#define IGB_RXBUFFER_16384 16384
	94
	95	/* Packet Buffer allocations */
	96
	97
	98	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	99	#define IGB_TX_QUEUE_WAKE 16
	100	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	101	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	102
	103	#define AUTO_ALL_MODES 0
	104	#define IGB_EEPROM_APME 0x0400
	105
	106	#ifndef IGB_MASTER_SLAVE
	107	/* Switch to override PHY master/slave setting */
	108	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	109	#endif
	110
	111	#define IGB_MNG_VLAN_NONE -1
	112
	113	/* wrapper around a pointer to a socket buffer,
	114	* so a DMA handle can be stored along with the buffer */
	115	struct igb_buffer {
	116	struct sk_buff *skb;
	117	dma_addr_t dma;
	118	union {
	119	/* TX */
	120	struct {
	121	unsigned long time_stamp;
	122	u32 length;
	123	};
	124	/* RX */
	125	struct {
	126	struct page *page;
	127	u64 page_dma;
	128	};
	129	};
130	};
131
132	struct igb_queue_stats {
133	u64 packets;
134	u64 bytes;
135	};
136
137	struct igb_ring {
138	struct igb_adapter adapter; / backlink */
139	void desc; / descriptor ring memory */
140	dma_addr_t dma; /* phys address of the ring */
141	unsigned int size; /* length of desc. ring in bytes */
142	unsigned int count; /* number of desc. in the ring */
143	u16 next_to_use;
144	u16 next_to_clean;
145	u16 head;
146	u16 tail;
147	struct igb_buffer buffer_info; / array of buffer info structs */
148
149	u32 eims_value;
150	u32 itr_val;
151	u16 itr_register;
152	u16 cpu;
153
844290e5	154	int queue_index;
9d5c8243 AK	155	unsigned int total_bytes;
	156	unsigned int total_packets;
	157
	158	union {
	159	/* TX */
	160	struct {
e21ed353	161	struct igb_queue_stats tx_stats;
9d5c8243 AK	162	bool detect_tx_hung;
	163	};
	164	/* RX */
	165	struct {
	166	/* arrays of page information for packet split */
	167	struct sk_buff *pending_skb;
	168	int pending_skb_page;
	169	int no_itr_adjust;
	170	struct igb_queue_stats rx_stats;
	171	struct napi_struct napi;
	172	};
	173	};
	174
	175	char name[IFNAMSIZ + 5];
	176	};
	177
	178	#define IGB_DESC_UNUSED(R) \
	179	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	180	(R)->next_to_clean - (R)->next_to_use - 1)
	181
	182	#define E1000_RX_DESC_ADV(R, i) \
	183	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	184	#define E1000_TX_DESC_ADV(R, i) \
	185	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	186	#define E1000_TX_CTXTDESC_ADV(R, i) \
	187	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
	188	#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
	189	#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
	190	#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
	191
	192	/* board specific private data structure */
	193
	194	struct igb_adapter {
	195	struct timer_list watchdog_timer;
	196	struct timer_list phy_info_timer;
	197	struct vlan_group *vlgrp;
	198	u16 mng_vlan_id;
	199	u32 bd_number;
	200	u32 rx_buffer_len;
	201	u32 wol;
	202	u32 en_mng_pt;
	203	u16 link_speed;
	204	u16 link_duplex;
	205	unsigned int total_tx_bytes;
	206	unsigned int total_tx_packets;
	207	unsigned int total_rx_bytes;
	208	unsigned int total_rx_packets;
	209	/* Interrupt Throttle Rate */
	210	u32 itr;
	211	u32 itr_setting;
	212	u16 tx_itr;
	213	u16 rx_itr;
	214	int set_itr;
	215
	216	struct work_struct reset_task;
	217	struct work_struct watchdog_task;
	218	bool fc_autoneg;
	219	u8 tx_timeout_factor;
	220	struct timer_list blink_timer;
	221	unsigned long led_status;
	222
	223	/* TX */
	224	struct igb_ring tx_ring; / One per active queue */
	225	unsigned int restart_queue;
226	unsigned long tx_queue_len;
227	u32 txd_cmd;
228	u32 gotc;
229	u64 gotc_old;
230	u64 tpt_old;
231	u64 colc_old;
232	u32 tx_timeout_count;
233
234	/* RX */
235	struct igb_ring rx_ring; / One per active queue */
236	int num_tx_queues;
237	int num_rx_queues;
238
239	u64 hw_csum_err;
240	u64 hw_csum_good;
241	u64 rx_hdr_split;
242	u32 alloc_rx_buff_failed;
243	bool rx_csum;
244	u32 gorc;
245	u64 gorc_old;
246	u16 rx_ps_hdr_size;
247	u32 max_frame_size;
248	u32 min_frame_size;
249
250	/* OS defined structs */
251	struct net_device *netdev;
252	struct napi_struct napi;
253	struct pci_dev *pdev;
254	struct net_device_stats net_stats;
255
256	/* structs defined in e1000_hw.h */
257	struct e1000_hw hw;
258	struct e1000_hw_stats stats;
259	struct e1000_phy_info phy_info;
260	struct e1000_phy_stats phy_stats;
261
262	u32 test_icr;
263	struct igb_ring test_tx_ring;
264	struct igb_ring test_rx_ring;
265
266	int msg_enable;
267	struct msix_entry *msix_entries;
268	u32 eims_enable_mask;
844290e5	269	u32 eims_other;
9d5c8243 AK	270
	271	/* to not mess up cache alignment, always add to the bottom */
	272	unsigned long state;
	273	unsigned int msi_enabled;
fe4506b6 JC	274	#ifdef CONFIG_DCA
	275	unsigned int dca_enabled;
	276	#endif
9d5c8243	277	u32 eeprom_wol;
42bfd33a TI	278
	279	/* for ioport free */
	280	int bars;
	281	int need_ioport;
661086df PWJ	282
	283	#ifdef CONFIG_NETDEVICES_MULTIQUEUE
	284	struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
	285	#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
9d5c8243 AK	286	};
	287
	288	enum e1000_state_t {
	289	__IGB_TESTING,
	290	__IGB_RESETTING,
	291	__IGB_DOWN
	292	};
	293
	294	enum igb_boards {
	295	board_82575,
	296	};
	297
	298	extern char igb_driver_name[];
	299	extern char igb_driver_version[];
	300
	301	extern char igb_get_hw_dev_name(struct e1000_hw hw);
	302	extern int igb_up(struct igb_adapter *);
	303	extern void igb_down(struct igb_adapter *);
	304	extern void igb_reinit_locked(struct igb_adapter *);
	305	extern void igb_reset(struct igb_adapter *);
	306	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
	307	extern int igb_setup_tx_resources(struct igb_adapter , struct igb_ring );
	308	extern int igb_setup_rx_resources(struct igb_adapter , struct igb_ring );
	309	extern void igb_update_stats(struct igb_adapter *);
	310	extern void igb_set_ethtool_ops(struct net_device *);
	311
	312	#endif /* _IGB_H_ */