[deliverable/linux.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
                               (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
#define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
#define IGB_ABS_MAX_TX_QUEUES     4

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	bool clear_to_send;
};

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                    (hw->mac.type <= e1000_82576 ? 16 : 8)
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
                                             adapter->msix_entries) ? 0 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_16384 16384

#define MAX_STD_JUMBO_FRAME_SIZE 9234

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
		};
		/* RX */
		struct {
			struct page *page;
			u64 page_dma;
			unsigned int page_offset;
		};
	};
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;

	u16 itr_val;
	u8 set_itr;
	u8 itr_shift;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector; /* backlink to q_vector */
	void *desc;                    /* descriptor ring memory */
	struct pci_dev *pdev;          /* pci device for dma mapping */
	dma_addr_t dma;                /* phys address of the ring */
	unsigned int size;             /* length of desc. ring in bytes */
	unsigned int count;            /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	void __iomem *head;
	void __iomem *tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	u8 queue_index;
	u8 reg_idx;

	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			u32 rx_buffer_len;
		};
	};
};

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))

/* board specific private data structure */

struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;
	unsigned int total_tx_bytes;
	unsigned int total_tx_packets;
	unsigned int total_rx_bytes;
	unsigned int total_rx_packets;
	/* Interrupt Throttle Rate */
	u32 itr;
	u32 itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring;      /* One per active queue */
	unsigned int restart_queue;
	unsigned long tx_queue_len;
	u32 txd_cmd;
	u32 gotc;
	u64 gotc_old;
	u64 tpt_old;
	u64 colc_old;
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring;      /* One per active queue */
	int num_tx_queues;
	int num_rx_queues;

	u64 hw_csum_err;
	u32 alloc_rx_buff_failed;
	u32 gorc;
	u64 gorc_old;
	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	unsigned int num_q_vectors;
	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_NEED_CTX_IDX      (1 << 3)
#define IGB_FLAG_RX_CSUM_DISABLED  (1 << 4)

enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_update_stats(struct igb_adapter *);
extern void igb_set_ethtool_ops(struct net_device *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
38c845c7	40
9d5c8243 AK	41	struct igb_adapter;
9d5c8243 AK	42
6eb5a7f1 AD	43	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	44	#define IGB_START_ITR 648
9d5c8243	45
9d5c8243 AK	46	/* TX/RX descriptor defines */
	47	#define IGB_DEFAULT_TXD 256
	48	#define IGB_MIN_TXD 80
	49	#define IGB_MAX_TXD 4096
	50
	51	#define IGB_DEFAULT_RXD 256
	52	#define IGB_MIN_RXD 80
	53	#define IGB_MAX_RXD 4096
	54
	55	#define IGB_DEFAULT_ITR 3 /* dynamic */
	56	#define IGB_MAX_ITR_USECS 10000
	57	#define IGB_MIN_ITR_USECS 10
047e0030 AD	58	#define NON_Q_VECTORS 1
047e0030 AD	59	#define MAX_Q_VECTORS 8
9d5c8243 AK	60
9d5c8243 AK	61	/* Transmit and receive queues */
1bfaf07b AD	62	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \
	63	(adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
	64	#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
	65	#define IGB_ABS_MAX_TX_QUEUES 4
9d5c8243	66
4ae196df AD	67	#define IGB_MAX_VF_MC_ENTRIES 30
	68	#define IGB_MAX_VF_FUNCTIONS 8
	69	#define IGB_MAX_VFTA_ENTRIES 128
	70
	71	struct vf_data_storage {
	72	unsigned char vf_mac_addresses[ETH_ALEN];
	73	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	74	u16 num_vf_mc_hashes;
ae641bdc	75	u16 vlans_enabled;
4ae196df AD	76	bool clear_to_send;
	77	};
	78
9d5c8243 AK	79	/* RX descriptor control thresholds.
	80	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	81	* descriptors available in its onboard memory.
	82	* Setting this to 0 disables RX descriptor prefetch.
	83	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	84	* available in host memory.
	85	* If PTHRESH is 0, this should also be 0.
	86	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	87	* descriptors until either it has this many to write back, or the
	88	* ITR timer expires.
	89	*/
85b430b4	90	#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
9d5c8243 AK	91	#define IGB_RX_HTHRESH 8
9d5c8243 AK	92	#define IGB_RX_WTHRESH 1
85b430b4 AD	93	#define IGB_TX_PTHRESH 8
	94	#define IGB_TX_HTHRESH 1
	95	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
	96	adapter->msix_entries) ? 0 : 16)
9d5c8243 AK	97
	98	/* this is the size past which hardware will drop packets when setting LPE=0 */
	99	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	100
	101	/* Supported Rx Buffer Sizes */
	102	#define IGB_RXBUFFER_128 128 /* Used for packet split */
9d5c8243 AK	103	#define IGB_RXBUFFER_1024 1024
9d5c8243 AK	104	#define IGB_RXBUFFER_2048 2048
9d5c8243 AK	105	#define IGB_RXBUFFER_16384 16384
9d5c8243 AK	106
e1739522	107	#define MAX_STD_JUMBO_FRAME_SIZE 9234
9d5c8243 AK	108
	109	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	110	#define IGB_TX_QUEUE_WAKE 16
	111	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	112	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	113
	114	#define AUTO_ALL_MODES 0
	115	#define IGB_EEPROM_APME 0x0400
	116
	117	#ifndef IGB_MASTER_SLAVE
	118	/* Switch to override PHY master/slave setting */
	119	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	120	#endif
	121
	122	#define IGB_MNG_VLAN_NONE -1
	123
	124	/* wrapper around a pointer to a socket buffer,
	125	* so a DMA handle can be stored along with the buffer */
	126	struct igb_buffer {
	127	struct sk_buff *skb;
	128	dma_addr_t dma;
	129	union {
	130	/* TX */
	131	struct {
	132	unsigned long time_stamp;
0e014cb1 AD	133	u16 length;
0e014cb1 AD	134	u16 next_to_watch;
9d5c8243 AK	135	};
	136	/* RX */
	137	struct {
	138	struct page *page;
	139	u64 page_dma;
bf36c1a0	140	unsigned int page_offset;
9d5c8243 AK	141	};
	142	};
	143	};
	144
8c0ab70a	145	struct igb_tx_queue_stats {
9d5c8243 AK	146	u64 packets;
	147	u64 bytes;
	148	};
	149
8c0ab70a JDB	150	struct igb_rx_queue_stats {
	151	u64 packets;
	152	u64 bytes;
	153	u64 drops;
	154	};
	155
047e0030	156	struct igb_q_vector {
9d5c8243	157	struct igb_adapter adapter; / backlink */
047e0030 AD	158	struct igb_ring *rx_ring;
	159	struct igb_ring *tx_ring;
	160	struct napi_struct napi;
	161
	162	u32 eims_value;
	163	u16 cpu;
	164
	165	u16 itr_val;
	166	u8 set_itr;
	167	u8 itr_shift;
	168	void __iomem *itr_register;
	169
	170	char name[IFNAMSIZ + 9];
	171	};
	172
	173	struct igb_ring {
	174	struct igb_q_vector q_vector; / backlink to q_vector */
	175	void desc; / descriptor ring memory */
80785298	176	struct pci_dev pdev; / pci device for dma mapping */
047e0030 AD	177	dma_addr_t dma; /* phys address of the ring */
	178	unsigned int size; /* length of desc. ring in bytes */
	179	unsigned int count; /* number of desc. in the ring */
9d5c8243 AK	180	u16 next_to_use;
9d5c8243 AK	181	u16 next_to_clean;
fce99e34 AD	182	void __iomem *head;
fce99e34 AD	183	void __iomem *tail;
9d5c8243 AK	184	struct igb_buffer buffer_info; / array of buffer info structs */
9d5c8243 AK	185
047e0030 AD	186	u8 queue_index;
047e0030 AD	187	u8 reg_idx;
9d5c8243 AK	188
	189	unsigned int total_bytes;
	190	unsigned int total_packets;
	191
	192	union {
	193	/* TX */
	194	struct {
8c0ab70a	195	struct igb_tx_queue_stats tx_stats;
9d5c8243 AK	196	bool detect_tx_hung;
	197	};
	198	/* RX */
	199	struct {
8c0ab70a	200	struct igb_rx_queue_stats rx_stats;
4c844851	201	u32 rx_buffer_len;
9d5c8243 AK	202	};
9d5c8243 AK	203	};
9d5c8243 AK	204	};
9d5c8243 AK	205
9d5c8243 AK	206	#define E1000_RX_DESC_ADV(R, i) \
	207	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	208	#define E1000_TX_DESC_ADV(R, i) \
	209	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	210	#define E1000_TX_CTXTDESC_ADV(R, i) \
	211	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
9d5c8243 AK	212
	213	/* board specific private data structure */
	214
	215	struct igb_adapter {
	216	struct timer_list watchdog_timer;
	217	struct timer_list phy_info_timer;
	218	struct vlan_group *vlgrp;
	219	u16 mng_vlan_id;
	220	u32 bd_number;
9d5c8243 AK	221	u32 wol;
	222	u32 en_mng_pt;
	223	u16 link_speed;
	224	u16 link_duplex;
	225	unsigned int total_tx_bytes;
	226	unsigned int total_tx_packets;
	227	unsigned int total_rx_bytes;
	228	unsigned int total_rx_packets;
	229	/* Interrupt Throttle Rate */
	230	u32 itr;
	231	u32 itr_setting;
	232	u16 tx_itr;
	233	u16 rx_itr;
9d5c8243 AK	234
	235	struct work_struct reset_task;
	236	struct work_struct watchdog_task;
	237	bool fc_autoneg;
	238	u8 tx_timeout_factor;
	239	struct timer_list blink_timer;
	240	unsigned long led_status;
	241
	242	/* TX */
	243	struct igb_ring tx_ring; / One per active queue */
	244	unsigned int restart_queue;
	245	unsigned long tx_queue_len;
	246	u32 txd_cmd;
	247	u32 gotc;
	248	u64 gotc_old;
	249	u64 tpt_old;
	250	u64 colc_old;
	251	u32 tx_timeout_count;
	252
	253	/* RX */
	254	struct igb_ring rx_ring; / One per active queue */
	255	int num_tx_queues;
	256	int num_rx_queues;
	257
	258	u64 hw_csum_err;
9d5c8243	259	u32 alloc_rx_buff_failed;
9d5c8243 AK	260	u32 gorc;
9d5c8243 AK	261	u64 gorc_old;
9d5c8243 AK	262	u32 max_frame_size;
	263	u32 min_frame_size;
	264
	265	/* OS defined structs */
	266	struct net_device *netdev;
9d5c8243	267	struct pci_dev *pdev;
38c845c7 PO	268	struct cyclecounter cycles;
38c845c7 PO	269	struct timecounter clock;
33af6bcc PO	270	struct timecompare compare;
33af6bcc PO	271	struct hwtstamp_config hwtstamp_config;
9d5c8243 AK	272
	273	/* structs defined in e1000_hw.h */
	274	struct e1000_hw hw;
	275	struct e1000_hw_stats stats;
	276	struct e1000_phy_info phy_info;
	277	struct e1000_phy_stats phy_stats;
	278
	279	u32 test_icr;
	280	struct igb_ring test_tx_ring;
	281	struct igb_ring test_rx_ring;
	282
	283	int msg_enable;
047e0030 AD	284
	285	unsigned int num_q_vectors;
	286	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243 AK	287	struct msix_entry *msix_entries;
9d5c8243 AK	288	u32 eims_enable_mask;
844290e5	289	u32 eims_other;
9d5c8243 AK	290
	291	/* to not mess up cache alignment, always add to the bottom */
	292	unsigned long state;
7dfc16fa	293	unsigned int flags;
9d5c8243	294	u32 eeprom_wol;
42bfd33a	295
1bfaf07b	296	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
68fd9910 AD	297	unsigned int tx_ring_count;
68fd9910 AD	298	unsigned int rx_ring_count;
1bfaf07b	299	unsigned int vfs_allocated_count;
4ae196df	300	struct vf_data_storage *vf_data;
9d5c8243 AK	301	};
9d5c8243 AK	302
7dfc16fa	303	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	304	#define IGB_FLAG_DCA_ENABLED (1 << 1)
	305	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
	306	#define IGB_FLAG_NEED_CTX_IDX (1 << 3)
7beb0146	307	#define IGB_FLAG_RX_CSUM_DISABLED (1 << 4)
7dfc16fa	308
9d5c8243 AK	309	enum e1000_state_t {
	310	__IGB_TESTING,
	311	__IGB_RESETTING,
	312	__IGB_DOWN
	313	};
	314
	315	enum igb_boards {
	316	board_82575,
	317	};
	318
	319	extern char igb_driver_name[];
	320	extern char igb_driver_version[];
	321
	322	extern char igb_get_hw_dev_name(struct e1000_hw hw);
	323	extern int igb_up(struct igb_adapter *);
	324	extern void igb_down(struct igb_adapter *);
	325	extern void igb_reinit_locked(struct igb_adapter *);
	326	extern void igb_reset(struct igb_adapter *);
	327	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
80785298 AD	328	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	329	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	330	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	331	extern void igb_free_rx_resources(struct igb_ring *);
9d5c8243 AK	332	extern void igb_update_stats(struct igb_adapter *);
	333	extern void igb_set_ethtool_ops(struct net_device *);
	334
f5f4cf08 AD	335	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	336	{
a8d2a0c2 AD	337	if (hw->phy.ops.reset)
a8d2a0c2 AD	338	return hw->phy.ops.reset(hw);
f5f4cf08 AD	339
	340	return 0;
	341	}
	342
	343	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	344	{
a8d2a0c2 AD	345	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	346	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	347
	348	return 0;
	349	}
	350
	351	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	352	{
a8d2a0c2 AD	353	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	354	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	355
	356	return 0;
	357	}
	358
	359	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	360	{
	361	if (hw->phy.ops.get_phy_info)
	362	return hw->phy.ops.get_phy_info(hw);
	363
	364	return 0;
	365	}
	366
9d5c8243	367	#endif /* _IGB_H_ */