[deliverable/linux.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
                               (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
#define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
#define IGB_ABS_MAX_TX_QUEUES     4

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	bool clear_to_send;
};

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                    16
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_256   256    /* Used for packet split */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_16384 16384

#define MAX_STD_JUMBO_FRAME_SIZE 9234

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
		};
		/* RX */
		struct {
			struct page *page;
			u64 page_dma;
			unsigned int page_offset;
		};
	};
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
};

struct igb_ring {
	struct igb_adapter *adapter; /* backlink */
	void *desc;                  /* descriptor ring memory */
	dma_addr_t dma;              /* phys address of the ring */
	unsigned int size;           /* length of desc. ring in bytes */
	unsigned int count;          /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	u16 head;
	u16 tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	u32 eims_value;
	u32 itr_val;
	u16 itr_register;
	u16 cpu;

	u16 queue_index;
	u16 reg_idx;
	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			u64 rx_queue_drops;
			struct napi_struct napi;
			int set_itr;
			struct igb_ring *buddy;
		};
	};

	char name[IFNAMSIZ + 5];
};

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))

/* board specific private data structure */

struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 rx_buffer_len;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;
	unsigned int total_tx_bytes;
	unsigned int total_tx_packets;
	unsigned int total_rx_bytes;
	unsigned int total_rx_packets;
	/* Interrupt Throttle Rate */
	u32 itr;
	u32 itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring;      /* One per active queue */
	unsigned int restart_queue;
	unsigned long tx_queue_len;
	u32 txd_cmd;
	u32 gotc;
	u64 gotc_old;
	u64 tpt_old;
	u64 colc_old;
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring;      /* One per active queue */
	int num_tx_queues;
	int num_rx_queues;

	u64 hw_csum_err;
	u64 hw_csum_good;
	u32 alloc_rx_buff_failed;
	u32 gorc;
	u64 gorc_old;
	u16 rx_ps_hdr_size;
	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct napi_struct napi;
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_NEED_CTX_IDX      (1 << 3)
#define IGB_FLAG_RX_CSUM_DISABLED  (1 << 4)

enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_update_stats(struct igb_adapter *);
extern void igb_set_ethtool_ops(struct net_device *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
38c845c7	40
9d5c8243 AK	41	struct igb_adapter;
9d5c8243 AK	42
6eb5a7f1 AD	43	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	44	#define IGB_START_ITR 648
9d5c8243	45
9d5c8243 AK	46	/* TX/RX descriptor defines */
	47	#define IGB_DEFAULT_TXD 256
	48	#define IGB_MIN_TXD 80
	49	#define IGB_MAX_TXD 4096
	50
	51	#define IGB_DEFAULT_RXD 256
	52	#define IGB_MIN_RXD 80
	53	#define IGB_MAX_RXD 4096
	54
	55	#define IGB_DEFAULT_ITR 3 /* dynamic */
	56	#define IGB_MAX_ITR_USECS 10000
	57	#define IGB_MIN_ITR_USECS 10
	58
	59	/* Transmit and receive queues */
1bfaf07b AD	60	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \
	61	(adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
	62	#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
	63	#define IGB_ABS_MAX_TX_QUEUES 4
9d5c8243	64
4ae196df AD	65	#define IGB_MAX_VF_MC_ENTRIES 30
	66	#define IGB_MAX_VF_FUNCTIONS 8
	67	#define IGB_MAX_VFTA_ENTRIES 128
	68
	69	struct vf_data_storage {
	70	unsigned char vf_mac_addresses[ETH_ALEN];
	71	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	72	u16 num_vf_mc_hashes;
ae641bdc	73	u16 vlans_enabled;
4ae196df AD	74	bool clear_to_send;
	75	};
	76
9d5c8243 AK	77	/* RX descriptor control thresholds.
	78	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	79	* descriptors available in its onboard memory.
	80	* Setting this to 0 disables RX descriptor prefetch.
	81	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	82	* available in host memory.
	83	* If PTHRESH is 0, this should also be 0.
	84	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	85	* descriptors until either it has this many to write back, or the
	86	* ITR timer expires.
	87	*/
	88	#define IGB_RX_PTHRESH 16
	89	#define IGB_RX_HTHRESH 8
	90	#define IGB_RX_WTHRESH 1
	91
	92	/* this is the size past which hardware will drop packets when setting LPE=0 */
	93	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	94
	95	/* Supported Rx Buffer Sizes */
	96	#define IGB_RXBUFFER_128 128 /* Used for packet split */
	97	#define IGB_RXBUFFER_256 256 /* Used for packet split */
	98	#define IGB_RXBUFFER_512 512
	99	#define IGB_RXBUFFER_1024 1024
	100	#define IGB_RXBUFFER_2048 2048
9d5c8243 AK	101	#define IGB_RXBUFFER_16384 16384
9d5c8243 AK	102
e1739522	103	#define MAX_STD_JUMBO_FRAME_SIZE 9234
9d5c8243 AK	104
	105	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	106	#define IGB_TX_QUEUE_WAKE 16
	107	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	108	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	109
	110	#define AUTO_ALL_MODES 0
	111	#define IGB_EEPROM_APME 0x0400
	112
	113	#ifndef IGB_MASTER_SLAVE
	114	/* Switch to override PHY master/slave setting */
	115	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	116	#endif
	117
	118	#define IGB_MNG_VLAN_NONE -1
	119
	120	/* wrapper around a pointer to a socket buffer,
	121	* so a DMA handle can be stored along with the buffer */
	122	struct igb_buffer {
	123	struct sk_buff *skb;
	124	dma_addr_t dma;
	125	union {
	126	/* TX */
	127	struct {
	128	unsigned long time_stamp;
0e014cb1 AD	129	u16 length;
0e014cb1 AD	130	u16 next_to_watch;
9d5c8243 AK	131	};
	132	/* RX */
	133	struct {
	134	struct page *page;
	135	u64 page_dma;
bf36c1a0	136	unsigned int page_offset;
9d5c8243 AK	137	};
	138	};
	139	};
	140
8c0ab70a	141	struct igb_tx_queue_stats {
9d5c8243 AK	142	u64 packets;
	143	u64 bytes;
	144	};
	145
8c0ab70a JDB	146	struct igb_rx_queue_stats {
	147	u64 packets;
	148	u64 bytes;
	149	u64 drops;
	150	};
	151
9d5c8243 AK	152	struct igb_ring {
	153	struct igb_adapter adapter; / backlink */
	154	void desc; / descriptor ring memory */
	155	dma_addr_t dma; /* phys address of the ring */
	156	unsigned int size; /* length of desc. ring in bytes */
	157	unsigned int count; /* number of desc. in the ring */
	158	u16 next_to_use;
	159	u16 next_to_clean;
	160	u16 head;
	161	u16 tail;
	162	struct igb_buffer buffer_info; / array of buffer info structs */
	163
	164	u32 eims_value;
	165	u32 itr_val;
	166	u16 itr_register;
	167	u16 cpu;
	168
26bc19ec AD	169	u16 queue_index;
26bc19ec AD	170	u16 reg_idx;
9d5c8243 AK	171	unsigned int total_bytes;
	172	unsigned int total_packets;
	173
	174	union {
	175	/* TX */
	176	struct {
8c0ab70a	177	struct igb_tx_queue_stats tx_stats;
9d5c8243 AK	178	bool detect_tx_hung;
	179	};
	180	/* RX */
	181	struct {
8c0ab70a JDB	182	struct igb_rx_queue_stats rx_stats;
8c0ab70a JDB	183	u64 rx_queue_drops;
9d5c8243	184	struct napi_struct napi;
6eb5a7f1 AD	185	int set_itr;
6eb5a7f1 AD	186	struct igb_ring *buddy;
9d5c8243 AK	187	};
	188	};
	189
	190	char name[IFNAMSIZ + 5];
	191	};
	192
9d5c8243 AK	193	#define E1000_RX_DESC_ADV(R, i) \
	194	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	195	#define E1000_TX_DESC_ADV(R, i) \
	196	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	197	#define E1000_TX_CTXTDESC_ADV(R, i) \
	198	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
9d5c8243 AK	199
	200	/* board specific private data structure */
	201
	202	struct igb_adapter {
	203	struct timer_list watchdog_timer;
	204	struct timer_list phy_info_timer;
	205	struct vlan_group *vlgrp;
	206	u16 mng_vlan_id;
	207	u32 bd_number;
	208	u32 rx_buffer_len;
	209	u32 wol;
	210	u32 en_mng_pt;
	211	u16 link_speed;
	212	u16 link_duplex;
	213	unsigned int total_tx_bytes;
	214	unsigned int total_tx_packets;
	215	unsigned int total_rx_bytes;
	216	unsigned int total_rx_packets;
	217	/* Interrupt Throttle Rate */
	218	u32 itr;
	219	u32 itr_setting;
	220	u16 tx_itr;
	221	u16 rx_itr;
9d5c8243 AK	222
	223	struct work_struct reset_task;
	224	struct work_struct watchdog_task;
	225	bool fc_autoneg;
	226	u8 tx_timeout_factor;
	227	struct timer_list blink_timer;
	228	unsigned long led_status;
	229
	230	/* TX */
	231	struct igb_ring tx_ring; / One per active queue */
	232	unsigned int restart_queue;
	233	unsigned long tx_queue_len;
	234	u32 txd_cmd;
	235	u32 gotc;
	236	u64 gotc_old;
	237	u64 tpt_old;
	238	u64 colc_old;
	239	u32 tx_timeout_count;
	240
	241	/* RX */
	242	struct igb_ring rx_ring; / One per active queue */
	243	int num_tx_queues;
	244	int num_rx_queues;
	245
	246	u64 hw_csum_err;
	247	u64 hw_csum_good;
9d5c8243	248	u32 alloc_rx_buff_failed;
9d5c8243 AK	249	u32 gorc;
	250	u64 gorc_old;
	251	u16 rx_ps_hdr_size;
	252	u32 max_frame_size;
	253	u32 min_frame_size;
	254
	255	/* OS defined structs */
	256	struct net_device *netdev;
	257	struct napi_struct napi;
	258	struct pci_dev *pdev;
38c845c7 PO	259	struct cyclecounter cycles;
38c845c7 PO	260	struct timecounter clock;
33af6bcc PO	261	struct timecompare compare;
33af6bcc PO	262	struct hwtstamp_config hwtstamp_config;
9d5c8243 AK	263
	264	/* structs defined in e1000_hw.h */
	265	struct e1000_hw hw;
	266	struct e1000_hw_stats stats;
	267	struct e1000_phy_info phy_info;
	268	struct e1000_phy_stats phy_stats;
	269
	270	u32 test_icr;
	271	struct igb_ring test_tx_ring;
	272	struct igb_ring test_rx_ring;
	273
	274	int msg_enable;
	275	struct msix_entry *msix_entries;
	276	u32 eims_enable_mask;
844290e5	277	u32 eims_other;
9d5c8243 AK	278
	279	/* to not mess up cache alignment, always add to the bottom */
	280	unsigned long state;
7dfc16fa	281	unsigned int flags;
9d5c8243	282	u32 eeprom_wol;
42bfd33a	283
1bfaf07b	284	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
68fd9910 AD	285	unsigned int tx_ring_count;
68fd9910 AD	286	unsigned int rx_ring_count;
1bfaf07b	287	unsigned int vfs_allocated_count;
4ae196df	288	struct vf_data_storage *vf_data;
9d5c8243 AK	289	};
9d5c8243 AK	290
7dfc16fa	291	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	292	#define IGB_FLAG_DCA_ENABLED (1 << 1)
	293	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
	294	#define IGB_FLAG_NEED_CTX_IDX (1 << 3)
7beb0146	295	#define IGB_FLAG_RX_CSUM_DISABLED (1 << 4)
7dfc16fa	296
9d5c8243 AK	297	enum e1000_state_t {
	298	__IGB_TESTING,
	299	__IGB_RESETTING,
	300	__IGB_DOWN
	301	};
	302
	303	enum igb_boards {
	304	board_82575,
	305	};
	306
	307	extern char igb_driver_name[];
	308	extern char igb_driver_version[];
	309
	310	extern char igb_get_hw_dev_name(struct e1000_hw hw);
	311	extern int igb_up(struct igb_adapter *);
	312	extern void igb_down(struct igb_adapter *);
	313	extern void igb_reinit_locked(struct igb_adapter *);
	314	extern void igb_reset(struct igb_adapter *);
	315	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
	316	extern int igb_setup_tx_resources(struct igb_adapter , struct igb_ring );
	317	extern int igb_setup_rx_resources(struct igb_adapter , struct igb_ring );
68fd9910 AD	318	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	319	extern void igb_free_rx_resources(struct igb_ring *);
9d5c8243 AK	320	extern void igb_update_stats(struct igb_adapter *);
	321	extern void igb_set_ethtool_ops(struct net_device *);
	322
f5f4cf08 AD	323	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	324	{
a8d2a0c2 AD	325	if (hw->phy.ops.reset)
a8d2a0c2 AD	326	return hw->phy.ops.reset(hw);
f5f4cf08 AD	327
	328	return 0;
	329	}
	330
	331	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	332	{
a8d2a0c2 AD	333	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	334	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	335
	336	return 0;
	337	}
	338
	339	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	340	{
a8d2a0c2 AD	341	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	342	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	343
	344	return 0;
	345	}
	346
	347	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	348	{
	349	if (hw->phy.ops.get_phy_info)
	350	return hw->phy.ops.get_phy_info(hw);
	351
	352	return 0;
	353	}
	354
9d5c8243	355	#endif /* _IGB_H_ */