[deliverable/linux.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  4
#define IGB_MAX_TX_QUEUES                  4

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                    16
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_256   256    /* Used for packet split */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_16384 16384

/* Packet Buffer allocations */


/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
		};
		/* RX */
		struct {
			struct page *page;
			u64 page_dma;
			unsigned int page_offset;
		};
	};
};

struct igb_queue_stats {
	u64 packets;
	u64 bytes;
};

struct igb_ring {
	struct igb_adapter *adapter; /* backlink */
	void *desc;                  /* descriptor ring memory */
	dma_addr_t dma;              /* phys address of the ring */
	unsigned int size;           /* length of desc. ring in bytes */
	unsigned int count;          /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	u16 head;
	u16 tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	u32 eims_value;
	u32 itr_val;
	u16 itr_register;
	u16 cpu;

	u16 queue_index;
	u16 reg_idx;
	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_queue_stats tx_stats;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_queue_stats rx_stats;
			struct napi_struct napi;
			int set_itr;
			struct igb_ring *buddy;
		};
	};

	char name[IFNAMSIZ + 5];
};

#define IGB_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))

/* board specific private data structure */

struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 rx_buffer_len;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;
	unsigned int total_tx_bytes;
	unsigned int total_tx_packets;
	unsigned int total_rx_bytes;
	unsigned int total_rx_packets;
	/* Interrupt Throttle Rate */
	u32 itr;
	u32 itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring;      /* One per active queue */
	unsigned int restart_queue;
	unsigned long tx_queue_len;
	u32 txd_cmd;
	u32 gotc;
	u64 gotc_old;
	u64 tpt_old;
	u64 colc_old;
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring;      /* One per active queue */
	int num_tx_queues;
	int num_rx_queues;

	u64 hw_csum_err;
	u64 hw_csum_good;
	u32 alloc_rx_buff_failed;
	bool rx_csum;
	u32 gorc;
	u64 gorc_old;
	u16 rx_ps_hdr_size;
	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct napi_struct napi;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_NEED_CTX_IDX      (1 << 3)

enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_update_stats(struct igb_adapter *);
extern void igb_set_ethtool_ops(struct net_device *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
38c845c7	40
9d5c8243 AK	41	struct igb_adapter;
9d5c8243 AK	42
6eb5a7f1 AD	43	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	44	#define IGB_START_ITR 648
9d5c8243	45
9d5c8243 AK	46	/* TX/RX descriptor defines */
	47	#define IGB_DEFAULT_TXD 256
	48	#define IGB_MIN_TXD 80
	49	#define IGB_MAX_TXD 4096
	50
	51	#define IGB_DEFAULT_RXD 256
	52	#define IGB_MIN_RXD 80
	53	#define IGB_MAX_RXD 4096
	54
	55	#define IGB_DEFAULT_ITR 3 /* dynamic */
	56	#define IGB_MAX_ITR_USECS 10000
	57	#define IGB_MIN_ITR_USECS 10
	58
	59	/* Transmit and receive queues */
	60	#define IGB_MAX_RX_QUEUES 4
661086df	61	#define IGB_MAX_TX_QUEUES 4
9d5c8243 AK	62
	63	/* RX descriptor control thresholds.
	64	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	65	* descriptors available in its onboard memory.
	66	* Setting this to 0 disables RX descriptor prefetch.
	67	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	68	* available in host memory.
	69	* If PTHRESH is 0, this should also be 0.
	70	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	71	* descriptors until either it has this many to write back, or the
	72	* ITR timer expires.
	73	*/
	74	#define IGB_RX_PTHRESH 16
	75	#define IGB_RX_HTHRESH 8
	76	#define IGB_RX_WTHRESH 1
	77
	78	/* this is the size past which hardware will drop packets when setting LPE=0 */
	79	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	80
	81	/* Supported Rx Buffer Sizes */
	82	#define IGB_RXBUFFER_128 128 /* Used for packet split */
	83	#define IGB_RXBUFFER_256 256 /* Used for packet split */
	84	#define IGB_RXBUFFER_512 512
	85	#define IGB_RXBUFFER_1024 1024
	86	#define IGB_RXBUFFER_2048 2048
9d5c8243 AK	87	#define IGB_RXBUFFER_16384 16384
	88
	89	/* Packet Buffer allocations */
	90
	91
	92	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	93	#define IGB_TX_QUEUE_WAKE 16
	94	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	95	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	96
	97	#define AUTO_ALL_MODES 0
	98	#define IGB_EEPROM_APME 0x0400
	99
	100	#ifndef IGB_MASTER_SLAVE
	101	/* Switch to override PHY master/slave setting */
	102	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	103	#endif
	104
	105	#define IGB_MNG_VLAN_NONE -1
	106
	107	/* wrapper around a pointer to a socket buffer,
	108	* so a DMA handle can be stored along with the buffer */
	109	struct igb_buffer {
	110	struct sk_buff *skb;
	111	dma_addr_t dma;
	112	union {
	113	/* TX */
	114	struct {
	115	unsigned long time_stamp;
0e014cb1 AD	116	u16 length;
0e014cb1 AD	117	u16 next_to_watch;
9d5c8243 AK	118	};
	119	/* RX */
	120	struct {
	121	struct page *page;
	122	u64 page_dma;
bf36c1a0	123	unsigned int page_offset;
9d5c8243 AK	124	};
	125	};
	126	};
	127
	128	struct igb_queue_stats {
	129	u64 packets;
	130	u64 bytes;
	131	};
	132
	133	struct igb_ring {
	134	struct igb_adapter adapter; / backlink */
	135	void desc; / descriptor ring memory */
	136	dma_addr_t dma; /* phys address of the ring */
	137	unsigned int size; /* length of desc. ring in bytes */
	138	unsigned int count; /* number of desc. in the ring */
	139	u16 next_to_use;
	140	u16 next_to_clean;
	141	u16 head;
	142	u16 tail;
	143	struct igb_buffer buffer_info; / array of buffer info structs */
	144
	145	u32 eims_value;
	146	u32 itr_val;
	147	u16 itr_register;
	148	u16 cpu;
	149
26bc19ec AD	150	u16 queue_index;
26bc19ec AD	151	u16 reg_idx;
9d5c8243 AK	152	unsigned int total_bytes;
	153	unsigned int total_packets;
	154
	155	union {
	156	/* TX */
	157	struct {
e21ed353	158	struct igb_queue_stats tx_stats;
9d5c8243 AK	159	bool detect_tx_hung;
	160	};
	161	/* RX */
	162	struct {
9d5c8243 AK	163	struct igb_queue_stats rx_stats;
9d5c8243 AK	164	struct napi_struct napi;
6eb5a7f1 AD	165	int set_itr;
6eb5a7f1 AD	166	struct igb_ring *buddy;
9d5c8243 AK	167	};
	168	};
	169
	170	char name[IFNAMSIZ + 5];
	171	};
	172
	173	#define IGB_DESC_UNUSED(R) \
	174	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	175	(R)->next_to_clean - (R)->next_to_use - 1)
	176
	177	#define E1000_RX_DESC_ADV(R, i) \
	178	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	179	#define E1000_TX_DESC_ADV(R, i) \
	180	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	181	#define E1000_TX_CTXTDESC_ADV(R, i) \
	182	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
9d5c8243 AK	183
	184	/* board specific private data structure */
	185
	186	struct igb_adapter {
	187	struct timer_list watchdog_timer;
	188	struct timer_list phy_info_timer;
	189	struct vlan_group *vlgrp;
	190	u16 mng_vlan_id;
	191	u32 bd_number;
	192	u32 rx_buffer_len;
	193	u32 wol;
	194	u32 en_mng_pt;
	195	u16 link_speed;
	196	u16 link_duplex;
	197	unsigned int total_tx_bytes;
	198	unsigned int total_tx_packets;
	199	unsigned int total_rx_bytes;
	200	unsigned int total_rx_packets;
	201	/* Interrupt Throttle Rate */
	202	u32 itr;
	203	u32 itr_setting;
	204	u16 tx_itr;
	205	u16 rx_itr;
9d5c8243 AK	206
	207	struct work_struct reset_task;
	208	struct work_struct watchdog_task;
	209	bool fc_autoneg;
	210	u8 tx_timeout_factor;
	211	struct timer_list blink_timer;
	212	unsigned long led_status;
	213
	214	/* TX */
	215	struct igb_ring tx_ring; / One per active queue */
	216	unsigned int restart_queue;
	217	unsigned long tx_queue_len;
	218	u32 txd_cmd;
	219	u32 gotc;
	220	u64 gotc_old;
	221	u64 tpt_old;
	222	u64 colc_old;
	223	u32 tx_timeout_count;
	224
	225	/* RX */
	226	struct igb_ring rx_ring; / One per active queue */
	227	int num_tx_queues;
	228	int num_rx_queues;
	229
	230	u64 hw_csum_err;
	231	u64 hw_csum_good;
9d5c8243 AK	232	u32 alloc_rx_buff_failed;
	233	bool rx_csum;
	234	u32 gorc;
	235	u64 gorc_old;
	236	u16 rx_ps_hdr_size;
	237	u32 max_frame_size;
	238	u32 min_frame_size;
	239
	240	/* OS defined structs */
	241	struct net_device *netdev;
	242	struct napi_struct napi;
	243	struct pci_dev *pdev;
	244	struct net_device_stats net_stats;
38c845c7 PO	245	struct cyclecounter cycles;
38c845c7 PO	246	struct timecounter clock;
33af6bcc PO	247	struct timecompare compare;
33af6bcc PO	248	struct hwtstamp_config hwtstamp_config;
9d5c8243 AK	249
	250	/* structs defined in e1000_hw.h */
	251	struct e1000_hw hw;
	252	struct e1000_hw_stats stats;
	253	struct e1000_phy_info phy_info;
	254	struct e1000_phy_stats phy_stats;
	255
	256	u32 test_icr;
	257	struct igb_ring test_tx_ring;
	258	struct igb_ring test_rx_ring;
	259
	260	int msg_enable;
	261	struct msix_entry *msix_entries;
	262	u32 eims_enable_mask;
844290e5	263	u32 eims_other;
9d5c8243 AK	264
	265	/* to not mess up cache alignment, always add to the bottom */
	266	unsigned long state;
7dfc16fa	267	unsigned int flags;
9d5c8243	268	u32 eeprom_wol;
42bfd33a	269
661086df	270	struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
68fd9910 AD	271	unsigned int tx_ring_count;
68fd9910 AD	272	unsigned int rx_ring_count;
9d5c8243 AK	273	};
9d5c8243 AK	274
7dfc16fa	275	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	276	#define IGB_FLAG_DCA_ENABLED (1 << 1)
	277	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
	278	#define IGB_FLAG_NEED_CTX_IDX (1 << 3)
7dfc16fa	279
9d5c8243 AK	280	enum e1000_state_t {
	281	__IGB_TESTING,
	282	__IGB_RESETTING,
	283	__IGB_DOWN
	284	};
	285
	286	enum igb_boards {
	287	board_82575,
	288	};
	289
	290	extern char igb_driver_name[];
	291	extern char igb_driver_version[];
	292
	293	extern char igb_get_hw_dev_name(struct e1000_hw hw);
	294	extern int igb_up(struct igb_adapter *);
	295	extern void igb_down(struct igb_adapter *);
	296	extern void igb_reinit_locked(struct igb_adapter *);
	297	extern void igb_reset(struct igb_adapter *);
	298	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
	299	extern int igb_setup_tx_resources(struct igb_adapter , struct igb_ring );
	300	extern int igb_setup_rx_resources(struct igb_adapter , struct igb_ring );
68fd9910 AD	301	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	302	extern void igb_free_rx_resources(struct igb_ring *);
9d5c8243 AK	303	extern void igb_update_stats(struct igb_adapter *);
	304	extern void igb_set_ethtool_ops(struct net_device *);
	305
f5f4cf08 AD	306	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	307	{
a8d2a0c2 AD	308	if (hw->phy.ops.reset)
a8d2a0c2 AD	309	return hw->phy.ops.reset(hw);
f5f4cf08 AD	310
	311	return 0;
	312	}
	313
	314	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	315	{
a8d2a0c2 AD	316	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	317	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	318
	319	return 0;
	320	}
	321
	322	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	323	{
a8d2a0c2 AD	324	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	325	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	326
	327	return 0;
	328	}
	329
	330	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	331	{
	332	if (hw->phy.ops.get_phy_info)
	333	return hw->phy.ops.get_phy_info(hw);
	334
	335	return 0;
	336	}
	337
9d5c8243	338	#endif /* _IGB_H_ */