[deliverable/linux.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>

struct igb_adapter;

/* Interrupt defines */
#define IGB_MIN_DYN_ITR 3000
#define IGB_MAX_DYN_ITR 96000

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

#define IGB_DYN_ITR_PACKET_THRESHOLD 2
#define IGB_DYN_ITR_LENGTH_LOW 200
#define IGB_DYN_ITR_LENGTH_HIGH 1000

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  4
#define IGB_MAX_TX_QUEUES                  4

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                    16
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_256   256    /* Used for packet split */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_4096  4096
#define IGB_RXBUFFER_8192  8192
#define IGB_RXBUFFER_16384 16384

/* Packet Buffer allocations */


/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
		};
		/* RX */
		struct {
			struct page *page;
			u64 page_dma;
			unsigned int page_offset;
		};
	};
};

struct igb_queue_stats {
	u64 packets;
	u64 bytes;
};

struct igb_ring {
	struct igb_adapter *adapter; /* backlink */
	void *desc;                  /* descriptor ring memory */
	dma_addr_t dma;              /* phys address of the ring */
	unsigned int size;           /* length of desc. ring in bytes */
	unsigned int count;          /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	u16 head;
	u16 tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	u32 eims_value;
	u32 itr_val;
	u16 itr_register;
	u16 cpu;

	u16 queue_index;
	u16 reg_idx;
	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_queue_stats tx_stats;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_queue_stats rx_stats;
			struct napi_struct napi;
			int set_itr;
			struct igb_ring *buddy;
		};
	};

	char name[IFNAMSIZ + 5];
};

#define IGB_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)

/* board specific private data structure */

struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 rx_buffer_len;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;
	unsigned int total_tx_bytes;
	unsigned int total_tx_packets;
	unsigned int total_rx_bytes;
	unsigned int total_rx_packets;
	/* Interrupt Throttle Rate */
	u32 itr;
	u32 itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring;      /* One per active queue */
	unsigned int restart_queue;
	unsigned long tx_queue_len;
	u32 txd_cmd;
	u32 gotc;
	u64 gotc_old;
	u64 tpt_old;
	u64 colc_old;
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring;      /* One per active queue */
	int num_tx_queues;
	int num_rx_queues;

	u64 hw_csum_err;
	u64 hw_csum_good;
	u32 alloc_rx_buff_failed;
	bool rx_csum;
	u32 gorc;
	u64 gorc_old;
	u16 rx_ps_hdr_size;
	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct napi_struct napi;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_MSI_ENABLE        (1 << 1)
#define IGB_FLAG_DCA_ENABLED       (1 << 2)
#define IGB_FLAG_QUAD_PORT_A       (1 << 3)
#define IGB_FLAG_NEED_CTX_IDX      (1 << 4)

enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_update_stats(struct igb_adapter *);
extern void igb_set_ethtool_ops(struct net_device *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
38c845c7	40
9d5c8243 AK	41	struct igb_adapter;
	42
	43	/* Interrupt defines */
9d5c8243 AK	44	#define IGB_MIN_DYN_ITR 3000
9d5c8243 AK	45	#define IGB_MAX_DYN_ITR 96000
6eb5a7f1 AD	46
	47	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
	48	#define IGB_START_ITR 648
9d5c8243 AK	49
	50	#define IGB_DYN_ITR_PACKET_THRESHOLD 2
	51	#define IGB_DYN_ITR_LENGTH_LOW 200
	52	#define IGB_DYN_ITR_LENGTH_HIGH 1000
	53
	54	/* TX/RX descriptor defines */
	55	#define IGB_DEFAULT_TXD 256
	56	#define IGB_MIN_TXD 80
	57	#define IGB_MAX_TXD 4096
	58
	59	#define IGB_DEFAULT_RXD 256
	60	#define IGB_MIN_RXD 80
	61	#define IGB_MAX_RXD 4096
	62
	63	#define IGB_DEFAULT_ITR 3 /* dynamic */
	64	#define IGB_MAX_ITR_USECS 10000
	65	#define IGB_MIN_ITR_USECS 10
	66
	67	/* Transmit and receive queues */
	68	#define IGB_MAX_RX_QUEUES 4
661086df	69	#define IGB_MAX_TX_QUEUES 4
9d5c8243 AK	70
	71	/* RX descriptor control thresholds.
	72	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	73	* descriptors available in its onboard memory.
	74	* Setting this to 0 disables RX descriptor prefetch.
	75	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	76	* available in host memory.
	77	* If PTHRESH is 0, this should also be 0.
	78	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	79	* descriptors until either it has this many to write back, or the
	80	* ITR timer expires.
	81	*/
	82	#define IGB_RX_PTHRESH 16
	83	#define IGB_RX_HTHRESH 8
	84	#define IGB_RX_WTHRESH 1
	85
	86	/* this is the size past which hardware will drop packets when setting LPE=0 */
	87	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	88
	89	/* Supported Rx Buffer Sizes */
	90	#define IGB_RXBUFFER_128 128 /* Used for packet split */
	91	#define IGB_RXBUFFER_256 256 /* Used for packet split */
	92	#define IGB_RXBUFFER_512 512
	93	#define IGB_RXBUFFER_1024 1024
	94	#define IGB_RXBUFFER_2048 2048
	95	#define IGB_RXBUFFER_4096 4096
	96	#define IGB_RXBUFFER_8192 8192
	97	#define IGB_RXBUFFER_16384 16384
	98
	99	/* Packet Buffer allocations */
	100
	101
	102	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	103	#define IGB_TX_QUEUE_WAKE 16
	104	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	105	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	106
	107	#define AUTO_ALL_MODES 0
	108	#define IGB_EEPROM_APME 0x0400
	109
	110	#ifndef IGB_MASTER_SLAVE
	111	/* Switch to override PHY master/slave setting */
	112	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	113	#endif
	114
	115	#define IGB_MNG_VLAN_NONE -1
	116
	117	/* wrapper around a pointer to a socket buffer,
	118	* so a DMA handle can be stored along with the buffer */
	119	struct igb_buffer {
	120	struct sk_buff *skb;
	121	dma_addr_t dma;
	122	union {
	123	/* TX */
	124	struct {
	125	unsigned long time_stamp;
0e014cb1 AD	126	u16 length;
0e014cb1 AD	127	u16 next_to_watch;
9d5c8243 AK	128	};
	129	/* RX */
	130	struct {
	131	struct page *page;
	132	u64 page_dma;
bf36c1a0	133	unsigned int page_offset;
9d5c8243 AK	134	};
	135	};
	136	};
	137
	138	struct igb_queue_stats {
	139	u64 packets;
	140	u64 bytes;
	141	};
	142
	143	struct igb_ring {
	144	struct igb_adapter adapter; / backlink */
	145	void desc; / descriptor ring memory */
	146	dma_addr_t dma; /* phys address of the ring */
	147	unsigned int size; /* length of desc. ring in bytes */
	148	unsigned int count; /* number of desc. in the ring */
	149	u16 next_to_use;
	150	u16 next_to_clean;
	151	u16 head;
	152	u16 tail;
	153	struct igb_buffer buffer_info; / array of buffer info structs */
	154
	155	u32 eims_value;
	156	u32 itr_val;
	157	u16 itr_register;
	158	u16 cpu;
	159
26bc19ec AD	160	u16 queue_index;
26bc19ec AD	161	u16 reg_idx;
9d5c8243 AK	162	unsigned int total_bytes;
	163	unsigned int total_packets;
	164
	165	union {
	166	/* TX */
	167	struct {
e21ed353	168	struct igb_queue_stats tx_stats;
9d5c8243 AK	169	bool detect_tx_hung;
	170	};
	171	/* RX */
	172	struct {
9d5c8243 AK	173	struct igb_queue_stats rx_stats;
9d5c8243 AK	174	struct napi_struct napi;
6eb5a7f1 AD	175	int set_itr;
6eb5a7f1 AD	176	struct igb_ring *buddy;
9d5c8243 AK	177	};
	178	};
	179
	180	char name[IFNAMSIZ + 5];
	181	};
	182
	183	#define IGB_DESC_UNUSED(R) \
	184	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	185	(R)->next_to_clean - (R)->next_to_use - 1)
	186
	187	#define E1000_RX_DESC_ADV(R, i) \
	188	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	189	#define E1000_TX_DESC_ADV(R, i) \
	190	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	191	#define E1000_TX_CTXTDESC_ADV(R, i) \
	192	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
	193	#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
	194	#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
	195	#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
	196
	197	/* board specific private data structure */
	198
	199	struct igb_adapter {
	200	struct timer_list watchdog_timer;
	201	struct timer_list phy_info_timer;
	202	struct vlan_group *vlgrp;
	203	u16 mng_vlan_id;
	204	u32 bd_number;
	205	u32 rx_buffer_len;
	206	u32 wol;
	207	u32 en_mng_pt;
	208	u16 link_speed;
	209	u16 link_duplex;
	210	unsigned int total_tx_bytes;
	211	unsigned int total_tx_packets;
	212	unsigned int total_rx_bytes;
	213	unsigned int total_rx_packets;
	214	/* Interrupt Throttle Rate */
	215	u32 itr;
	216	u32 itr_setting;
	217	u16 tx_itr;
	218	u16 rx_itr;
9d5c8243 AK	219
	220	struct work_struct reset_task;
	221	struct work_struct watchdog_task;
	222	bool fc_autoneg;
	223	u8 tx_timeout_factor;
	224	struct timer_list blink_timer;
	225	unsigned long led_status;
	226
	227	/* TX */
	228	struct igb_ring tx_ring; / One per active queue */
	229	unsigned int restart_queue;
	230	unsigned long tx_queue_len;
	231	u32 txd_cmd;
	232	u32 gotc;
	233	u64 gotc_old;
	234	u64 tpt_old;
	235	u64 colc_old;
	236	u32 tx_timeout_count;
	237
	238	/* RX */
	239	struct igb_ring rx_ring; / One per active queue */
	240	int num_tx_queues;
	241	int num_rx_queues;
	242
	243	u64 hw_csum_err;
	244	u64 hw_csum_good;
9d5c8243 AK	245	u32 alloc_rx_buff_failed;
	246	bool rx_csum;
	247	u32 gorc;
	248	u64 gorc_old;
	249	u16 rx_ps_hdr_size;
	250	u32 max_frame_size;
	251	u32 min_frame_size;
	252
	253	/* OS defined structs */
	254	struct net_device *netdev;
	255	struct napi_struct napi;
	256	struct pci_dev *pdev;
	257	struct net_device_stats net_stats;
38c845c7 PO	258	struct cyclecounter cycles;
38c845c7 PO	259	struct timecounter clock;
33af6bcc PO	260	struct timecompare compare;
33af6bcc PO	261	struct hwtstamp_config hwtstamp_config;
9d5c8243 AK	262
	263	/* structs defined in e1000_hw.h */
	264	struct e1000_hw hw;
	265	struct e1000_hw_stats stats;
	266	struct e1000_phy_info phy_info;
	267	struct e1000_phy_stats phy_stats;
	268
	269	u32 test_icr;
	270	struct igb_ring test_tx_ring;
	271	struct igb_ring test_rx_ring;
	272
	273	int msg_enable;
	274	struct msix_entry *msix_entries;
	275	u32 eims_enable_mask;
844290e5	276	u32 eims_other;
9d5c8243 AK	277
	278	/* to not mess up cache alignment, always add to the bottom */
	279	unsigned long state;
7dfc16fa	280	unsigned int flags;
9d5c8243	281	u32 eeprom_wol;
42bfd33a	282
661086df	283	struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
68fd9910 AD	284	unsigned int tx_ring_count;
68fd9910 AD	285	unsigned int rx_ring_count;
9d5c8243 AK	286	};
9d5c8243 AK	287
7dfc16fa AD	288	#define IGB_FLAG_HAS_MSI (1 << 0)
7dfc16fa AD	289	#define IGB_FLAG_MSI_ENABLE (1 << 1)
bbd98fe4	290	#define IGB_FLAG_DCA_ENABLED (1 << 2)
eebbbdba AD	291	#define IGB_FLAG_QUAD_PORT_A (1 << 3)
eebbbdba AD	292	#define IGB_FLAG_NEED_CTX_IDX (1 << 4)
7dfc16fa	293
9d5c8243 AK	294	enum e1000_state_t {
	295	__IGB_TESTING,
	296	__IGB_RESETTING,
	297	__IGB_DOWN
	298	};
	299
	300	enum igb_boards {
	301	board_82575,
	302	};
	303
	304	extern char igb_driver_name[];
	305	extern char igb_driver_version[];
	306
	307	extern char igb_get_hw_dev_name(struct e1000_hw hw);
	308	extern int igb_up(struct igb_adapter *);
	309	extern void igb_down(struct igb_adapter *);
	310	extern void igb_reinit_locked(struct igb_adapter *);
	311	extern void igb_reset(struct igb_adapter *);
	312	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
	313	extern int igb_setup_tx_resources(struct igb_adapter , struct igb_ring );
	314	extern int igb_setup_rx_resources(struct igb_adapter , struct igb_ring );
68fd9910 AD	315	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	316	extern void igb_free_rx_resources(struct igb_ring *);
9d5c8243 AK	317	extern void igb_update_stats(struct igb_adapter *);
	318	extern void igb_set_ethtool_ops(struct net_device *);
	319
f5f4cf08 AD	320	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	321	{
a8d2a0c2 AD	322	if (hw->phy.ops.reset)
a8d2a0c2 AD	323	return hw->phy.ops.reset(hw);
f5f4cf08 AD	324
	325	return 0;
	326	}
	327
	328	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	329	{
a8d2a0c2 AD	330	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	331	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	332
	333	return 0;
	334	}
	335
	336	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	337	{
a8d2a0c2 AD	338	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	339	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	340
	341	return 0;
	342	}
	343
	344	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	345	{
	346	if (hw->phy.ops.get_phy_info)
	347	return hw->phy.ops.get_phy_info(hw);
	348
	349	return 0;
	350	}
	351
9d5c8243	352	#endif /* _IGB_H_ */