projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: update testing done by ethtool
[deliverable/linux.git] / drivers / net / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
37
38#include "igb.h"
39
40struct igb_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44};
45
030ed68b 46#define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
9d5c8243
AK		 47 offsetof(struct igb_adapter, m)
48static const struct igb_stats igb_gstrings_stats[] = {
49 { "rx_packets", IGB_STAT(stats.gprc) },
50 { "tx_packets", IGB_STAT(stats.gptc) },
51 { "rx_bytes", IGB_STAT(stats.gorc) },
52 { "tx_bytes", IGB_STAT(stats.gotc) },
53 { "rx_broadcast", IGB_STAT(stats.bprc) },
54 { "tx_broadcast", IGB_STAT(stats.bptc) },
55 { "rx_multicast", IGB_STAT(stats.mprc) },
56 { "tx_multicast", IGB_STAT(stats.mptc) },
57 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
58 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
59 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
60 { "multicast", IGB_STAT(stats.mprc) },
61 { "collisions", IGB_STAT(stats.colc) },
62 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
63 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
64 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
65 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
66 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
67 { "rx_missed_errors", IGB_STAT(stats.mpc) },
68 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
69 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
70 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
71 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
72 { "tx_window_errors", IGB_STAT(stats.latecol) },
73 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
74 { "tx_deferred_ok", IGB_STAT(stats.dc) },
75 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
76 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
77 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
78 { "tx_restart_queue", IGB_STAT(restart_queue) },
79 { "rx_long_length_errors", IGB_STAT(stats.roc) },
80 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
81 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
82 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
83 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
84 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
85 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
86 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
87 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
88 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
89 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
90 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
9d5c8243
AK		 91 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
92 { "tx_smbus", IGB_STAT(stats.mgptc) },
93 { "rx_smbus", IGB_STAT(stats.mgprc) },
94 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
95};
96
97#define IGB_QUEUE_STATS_LEN \
4cf1653a
WC		 98 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues + \
99 ((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
9d5c8243
AK		 100 (sizeof(struct igb_queue_stats) / sizeof(u64)))
101#define IGB_GLOBAL_STATS_LEN \
102 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
103#define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
104static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
105 "Register test (offline)", "Eeprom test (offline)",
106 "Interrupt test (offline)", "Loopback test (offline)",
107 "Link test (on/offline)"
108};
109#define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
110
111static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
112{
113 struct igb_adapter *adapter = netdev_priv(netdev);
114 struct e1000_hw *hw = &adapter->hw;
115
116 if (hw->phy.media_type == e1000_media_type_copper) {
117
118 ecmd->supported = (SUPPORTED_10baseT_Half |
119 SUPPORTED_10baseT_Full |
120 SUPPORTED_100baseT_Half |
121 SUPPORTED_100baseT_Full |
122 SUPPORTED_1000baseT_Full|
123 SUPPORTED_Autoneg |
124 SUPPORTED_TP);
125 ecmd->advertising = ADVERTISED_TP;
126
127 if (hw->mac.autoneg == 1) {
128 ecmd->advertising |= ADVERTISED_Autoneg;
129 /* the e1000 autoneg seems to match ethtool nicely */
130 ecmd->advertising |= hw->phy.autoneg_advertised;
131 }
132
133 ecmd->port = PORT_TP;
134 ecmd->phy_address = hw->phy.addr;
135 } else {
136 ecmd->supported = (SUPPORTED_1000baseT_Full |
137 SUPPORTED_FIBRE |
138 SUPPORTED_Autoneg);
139
140 ecmd->advertising = (ADVERTISED_1000baseT_Full |
141 ADVERTISED_FIBRE |
142 ADVERTISED_Autoneg);
143
144 ecmd->port = PORT_FIBRE;
145 }
146
147 ecmd->transceiver = XCVR_INTERNAL;
148
149 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
150
151 adapter->hw.mac.ops.get_speed_and_duplex(hw,
152 &adapter->link_speed,
153 &adapter->link_duplex);
154 ecmd->speed = adapter->link_speed;
155
156 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
157 * and HALF_DUPLEX != DUPLEX_HALF */
158
159 if (adapter->link_duplex == FULL_DUPLEX)
160 ecmd->duplex = DUPLEX_FULL;
161 else
162 ecmd->duplex = DUPLEX_HALF;
163 } else {
164 ecmd->speed = -1;
165 ecmd->duplex = -1;
166 }
167
168 ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
169 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
170 return 0;
171}
172
173static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
174{
175 struct igb_adapter *adapter = netdev_priv(netdev);
176 struct e1000_hw *hw = &adapter->hw;
177
178 /* When SoL/IDER sessions are active, autoneg/speed/duplex
179 * cannot be changed */
180 if (igb_check_reset_block(hw)) {
181 dev_err(&adapter->pdev->dev, "Cannot change link "
182 "characteristics when SoL/IDER is active.\n");
183 return -EINVAL;
184 }
185
186 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
187 msleep(1);
188
189 if (ecmd->autoneg == AUTONEG_ENABLE) {
190 hw->mac.autoneg = 1;
191 if (hw->phy.media_type == e1000_media_type_fiber)
192 hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE |
194 ADVERTISED_Autoneg;
195 else
196 hw->phy.autoneg_advertised = ecmd->advertising |
197 ADVERTISED_TP |
198 ADVERTISED_Autoneg;
199 ecmd->advertising = hw->phy.autoneg_advertised;
200 } else
201 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
202 clear_bit(__IGB_RESETTING, &adapter->state);
203 return -EINVAL;
204 }
205
206 /* reset the link */
207
208 if (netif_running(adapter->netdev)) {
209 igb_down(adapter);
210 igb_up(adapter);
211 } else
212 igb_reset(adapter);
213
214 clear_bit(__IGB_RESETTING, &adapter->state);
215 return 0;
216}
217
218static void igb_get_pauseparam(struct net_device *netdev,
219 struct ethtool_pauseparam *pause)
220{
221 struct igb_adapter *adapter = netdev_priv(netdev);
222 struct e1000_hw *hw = &adapter->hw;
223
224 pause->autoneg =
225 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
226
227 if (hw->fc.type == e1000_fc_rx_pause)
228 pause->rx_pause = 1;
229 else if (hw->fc.type == e1000_fc_tx_pause)
230 pause->tx_pause = 1;
231 else if (hw->fc.type == e1000_fc_full) {
232 pause->rx_pause = 1;
233 pause->tx_pause = 1;
234 }
235}
236
237static int igb_set_pauseparam(struct net_device *netdev,
238 struct ethtool_pauseparam *pause)
239{
240 struct igb_adapter *adapter = netdev_priv(netdev);
241 struct e1000_hw *hw = &adapter->hw;
242 int retval = 0;
243
244 adapter->fc_autoneg = pause->autoneg;
245
246 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
247 msleep(1);
248
249 if (pause->rx_pause && pause->tx_pause)
250 hw->fc.type = e1000_fc_full;
251 else if (pause->rx_pause && !pause->tx_pause)
252 hw->fc.type = e1000_fc_rx_pause;
253 else if (!pause->rx_pause && pause->tx_pause)
254 hw->fc.type = e1000_fc_tx_pause;
255 else if (!pause->rx_pause && !pause->tx_pause)
256 hw->fc.type = e1000_fc_none;
257
258 hw->fc.original_type = hw->fc.type;
259
260 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
261 if (netif_running(adapter->netdev)) {
262 igb_down(adapter);
263 igb_up(adapter);
264 } else
265 igb_reset(adapter);
266 } else
267 retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
268 igb_setup_link(hw) : igb_force_mac_fc(hw));
269
270 clear_bit(__IGB_RESETTING, &adapter->state);
271 return retval;
272}
273
274static u32 igb_get_rx_csum(struct net_device *netdev)
275{
276 struct igb_adapter *adapter = netdev_priv(netdev);
277 return adapter->rx_csum;
278}
279
280static int igb_set_rx_csum(struct net_device *netdev, u32 data)
281{
282 struct igb_adapter *adapter = netdev_priv(netdev);
283 adapter->rx_csum = data;
284
285 return 0;
286}
287
288static u32 igb_get_tx_csum(struct net_device *netdev)
289{
7d8eb29e 290 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9d5c8243
AK		 291}
292
293static int igb_set_tx_csum(struct net_device *netdev, u32 data)
294{
295 if (data)
7d8eb29e 296 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
9d5c8243 297 else
7d8eb29e 298 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
9d5c8243
AK		 299
300 return 0;
301}
302
303static int igb_set_tso(struct net_device *netdev, u32 data)
304{
305 struct igb_adapter *adapter = netdev_priv(netdev);
306
7d8eb29e 307 if (data) {
9d5c8243 308 netdev->features |= NETIF_F_TSO;
9d5c8243 309 netdev->features |= NETIF_F_TSO6;
7d8eb29e
AD		 310 } else {
311 netdev->features &= ~NETIF_F_TSO;
9d5c8243 312 netdev->features &= ~NETIF_F_TSO6;
7d8eb29e 313 }
9d5c8243
AK		 314
315 dev_info(&adapter->pdev->dev, "TSO is %s\n",
316 data ? "Enabled" : "Disabled");
317 return 0;
318}
319
320static u32 igb_get_msglevel(struct net_device *netdev)
321{
322 struct igb_adapter *adapter = netdev_priv(netdev);
323 return adapter->msg_enable;
324}
325
326static void igb_set_msglevel(struct net_device *netdev, u32 data)
327{
328 struct igb_adapter *adapter = netdev_priv(netdev);
329 adapter->msg_enable = data;
330}
331
332static int igb_get_regs_len(struct net_device *netdev)
333{
334#define IGB_REGS_LEN 551
335 return IGB_REGS_LEN * sizeof(u32);
336}
337
338static void igb_get_regs(struct net_device *netdev,
339 struct ethtool_regs *regs, void *p)
340{
341 struct igb_adapter *adapter = netdev_priv(netdev);
342 struct e1000_hw *hw = &adapter->hw;
343 u32 *regs_buff = p;
344 u8 i;
345
346 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
347
348 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
349
350 /* General Registers */
351 regs_buff[0] = rd32(E1000_CTRL);
352 regs_buff[1] = rd32(E1000_STATUS);
353 regs_buff[2] = rd32(E1000_CTRL_EXT);
354 regs_buff[3] = rd32(E1000_MDIC);
355 regs_buff[4] = rd32(E1000_SCTL);
356 regs_buff[5] = rd32(E1000_CONNSW);
357 regs_buff[6] = rd32(E1000_VET);
358 regs_buff[7] = rd32(E1000_LEDCTL);
359 regs_buff[8] = rd32(E1000_PBA);
360 regs_buff[9] = rd32(E1000_PBS);
361 regs_buff[10] = rd32(E1000_FRTIMER);
362 regs_buff[11] = rd32(E1000_TCPTIMER);
363
364 /* NVM Register */
365 regs_buff[12] = rd32(E1000_EECD);
366
367 /* Interrupt */
fe59de38
AD		 368 /* Reading EICS for EICR because they read the
369 * same but EICS does not clear on read */
370 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 371 regs_buff[14] = rd32(E1000_EICS);
372 regs_buff[15] = rd32(E1000_EIMS);
373 regs_buff[16] = rd32(E1000_EIMC);
374 regs_buff[17] = rd32(E1000_EIAC);
375 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 376 /* Reading ICS for ICR because they read the
377 * same but ICS does not clear on read */
378 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 379 regs_buff[20] = rd32(E1000_ICS);
380 regs_buff[21] = rd32(E1000_IMS);
381 regs_buff[22] = rd32(E1000_IMC);
382 regs_buff[23] = rd32(E1000_IAC);
383 regs_buff[24] = rd32(E1000_IAM);
384 regs_buff[25] = rd32(E1000_IMIRVP);
385
386 /* Flow Control */
387 regs_buff[26] = rd32(E1000_FCAL);
388 regs_buff[27] = rd32(E1000_FCAH);
389 regs_buff[28] = rd32(E1000_FCTTV);
390 regs_buff[29] = rd32(E1000_FCRTL);
391 regs_buff[30] = rd32(E1000_FCRTH);
392 regs_buff[31] = rd32(E1000_FCRTV);
393
394 /* Receive */
395 regs_buff[32] = rd32(E1000_RCTL);
396 regs_buff[33] = rd32(E1000_RXCSUM);
397 regs_buff[34] = rd32(E1000_RLPML);
398 regs_buff[35] = rd32(E1000_RFCTL);
399 regs_buff[36] = rd32(E1000_MRQC);
400 regs_buff[37] = rd32(E1000_VMD_CTL);
401
402 /* Transmit */
403 regs_buff[38] = rd32(E1000_TCTL);
404 regs_buff[39] = rd32(E1000_TCTL_EXT);
405 regs_buff[40] = rd32(E1000_TIPG);
406 regs_buff[41] = rd32(E1000_DTXCTL);
407
408 /* Wake Up */
409 regs_buff[42] = rd32(E1000_WUC);
410 regs_buff[43] = rd32(E1000_WUFC);
411 regs_buff[44] = rd32(E1000_WUS);
412 regs_buff[45] = rd32(E1000_IPAV);
413 regs_buff[46] = rd32(E1000_WUPL);
414
415 /* MAC */
416 regs_buff[47] = rd32(E1000_PCS_CFG0);
417 regs_buff[48] = rd32(E1000_PCS_LCTL);
418 regs_buff[49] = rd32(E1000_PCS_LSTAT);
419 regs_buff[50] = rd32(E1000_PCS_ANADV);
420 regs_buff[51] = rd32(E1000_PCS_LPAB);
421 regs_buff[52] = rd32(E1000_PCS_NPTX);
422 regs_buff[53] = rd32(E1000_PCS_LPABNP);
423
424 /* Statistics */
425 regs_buff[54] = adapter->stats.crcerrs;
426 regs_buff[55] = adapter->stats.algnerrc;
427 regs_buff[56] = adapter->stats.symerrs;
428 regs_buff[57] = adapter->stats.rxerrc;
429 regs_buff[58] = adapter->stats.mpc;
430 regs_buff[59] = adapter->stats.scc;
431 regs_buff[60] = adapter->stats.ecol;
432 regs_buff[61] = adapter->stats.mcc;
433 regs_buff[62] = adapter->stats.latecol;
434 regs_buff[63] = adapter->stats.colc;
435 regs_buff[64] = adapter->stats.dc;
436 regs_buff[65] = adapter->stats.tncrs;
437 regs_buff[66] = adapter->stats.sec;
438 regs_buff[67] = adapter->stats.htdpmc;
439 regs_buff[68] = adapter->stats.rlec;
440 regs_buff[69] = adapter->stats.xonrxc;
441 regs_buff[70] = adapter->stats.xontxc;
442 regs_buff[71] = adapter->stats.xoffrxc;
443 regs_buff[72] = adapter->stats.xofftxc;
444 regs_buff[73] = adapter->stats.fcruc;
445 regs_buff[74] = adapter->stats.prc64;
446 regs_buff[75] = adapter->stats.prc127;
447 regs_buff[76] = adapter->stats.prc255;
448 regs_buff[77] = adapter->stats.prc511;
449 regs_buff[78] = adapter->stats.prc1023;
450 regs_buff[79] = adapter->stats.prc1522;
451 regs_buff[80] = adapter->stats.gprc;
452 regs_buff[81] = adapter->stats.bprc;
453 regs_buff[82] = adapter->stats.mprc;
454 regs_buff[83] = adapter->stats.gptc;
455 regs_buff[84] = adapter->stats.gorc;
456 regs_buff[86] = adapter->stats.gotc;
457 regs_buff[88] = adapter->stats.rnbc;
458 regs_buff[89] = adapter->stats.ruc;
459 regs_buff[90] = adapter->stats.rfc;
460 regs_buff[91] = adapter->stats.roc;
461 regs_buff[92] = adapter->stats.rjc;
462 regs_buff[93] = adapter->stats.mgprc;
463 regs_buff[94] = adapter->stats.mgpdc;
464 regs_buff[95] = adapter->stats.mgptc;
465 regs_buff[96] = adapter->stats.tor;
466 regs_buff[98] = adapter->stats.tot;
467 regs_buff[100] = adapter->stats.tpr;
468 regs_buff[101] = adapter->stats.tpt;
469 regs_buff[102] = adapter->stats.ptc64;
470 regs_buff[103] = adapter->stats.ptc127;
471 regs_buff[104] = adapter->stats.ptc255;
472 regs_buff[105] = adapter->stats.ptc511;
473 regs_buff[106] = adapter->stats.ptc1023;
474 regs_buff[107] = adapter->stats.ptc1522;
475 regs_buff[108] = adapter->stats.mptc;
476 regs_buff[109] = adapter->stats.bptc;
477 regs_buff[110] = adapter->stats.tsctc;
478 regs_buff[111] = adapter->stats.iac;
479 regs_buff[112] = adapter->stats.rpthc;
480 regs_buff[113] = adapter->stats.hgptc;
481 regs_buff[114] = adapter->stats.hgorc;
482 regs_buff[116] = adapter->stats.hgotc;
483 regs_buff[118] = adapter->stats.lenerrs;
484 regs_buff[119] = adapter->stats.scvpc;
485 regs_buff[120] = adapter->stats.hrmpc;
486
487 /* These should probably be added to e1000_regs.h instead */
488 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
9d5c8243
AK		 489 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
490 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
491 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
492 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
493 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
494 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
495
496 for (i = 0; i < 4; i++)
497 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
498 for (i = 0; i < 4; i++)
499 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
500 for (i = 0; i < 4; i++)
501 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
502 for (i = 0; i < 4; i++)
503 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
504 for (i = 0; i < 4; i++)
505 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
506 for (i = 0; i < 4; i++)
507 regs_buff[141 + i] = rd32(E1000_RDH(i));
508 for (i = 0; i < 4; i++)
509 regs_buff[145 + i] = rd32(E1000_RDT(i));
510 for (i = 0; i < 4; i++)
511 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
512
513 for (i = 0; i < 10; i++)
514 regs_buff[153 + i] = rd32(E1000_EITR(i));
515 for (i = 0; i < 8; i++)
516 regs_buff[163 + i] = rd32(E1000_IMIR(i));
517 for (i = 0; i < 8; i++)
518 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
519 for (i = 0; i < 16; i++)
520 regs_buff[179 + i] = rd32(E1000_RAL(i));
521 for (i = 0; i < 16; i++)
522 regs_buff[195 + i] = rd32(E1000_RAH(i));
523
524 for (i = 0; i < 4; i++)
525 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
526 for (i = 0; i < 4; i++)
527 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
528 for (i = 0; i < 4; i++)
529 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
530 for (i = 0; i < 4; i++)
531 regs_buff[223 + i] = rd32(E1000_TDH(i));
532 for (i = 0; i < 4; i++)
533 regs_buff[227 + i] = rd32(E1000_TDT(i));
534 for (i = 0; i < 4; i++)
535 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
536 for (i = 0; i < 4; i++)
537 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
538 for (i = 0; i < 4; i++)
539 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
540 for (i = 0; i < 4; i++)
541 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
542
543 for (i = 0; i < 4; i++)
544 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
547 for (i = 0; i < 32; i++)
548 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
549 for (i = 0; i < 128; i++)
550 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
551 for (i = 0; i < 128; i++)
552 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
553 for (i = 0; i < 4; i++)
554 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
555
556 regs_buff[547] = rd32(E1000_TDFH);
557 regs_buff[548] = rd32(E1000_TDFT);
558 regs_buff[549] = rd32(E1000_TDFHS);
559 regs_buff[550] = rd32(E1000_TDFPC);
560
561}
562
563static int igb_get_eeprom_len(struct net_device *netdev)
564{
565 struct igb_adapter *adapter = netdev_priv(netdev);
566 return adapter->hw.nvm.word_size * 2;
567}
568
569static int igb_get_eeprom(struct net_device *netdev,
570 struct ethtool_eeprom *eeprom, u8 *bytes)
571{
572 struct igb_adapter *adapter = netdev_priv(netdev);
573 struct e1000_hw *hw = &adapter->hw;
574 u16 *eeprom_buff;
575 int first_word, last_word;
576 int ret_val = 0;
577 u16 i;
578
579 if (eeprom->len == 0)
580 return -EINVAL;
581
582 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
583
584 first_word = eeprom->offset >> 1;
585 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
586
587 eeprom_buff = kmalloc(sizeof(u16) *
588 (last_word - first_word + 1), GFP_KERNEL);
589 if (!eeprom_buff)
590 return -ENOMEM;
591
592 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 593 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 594 last_word - first_word + 1,
595 eeprom_buff);
596 else {
597 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 598 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 599 &eeprom_buff[i]);
600 if (ret_val)
601 break;
602 }
603 }
604
605 /* Device's eeprom is always little-endian, word addressable */
606 for (i = 0; i < last_word - first_word + 1; i++)
607 le16_to_cpus(&eeprom_buff[i]);
608
609 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
610 eeprom->len);
611 kfree(eeprom_buff);
612
613 return ret_val;
614}
615
616static int igb_set_eeprom(struct net_device *netdev,
617 struct ethtool_eeprom *eeprom, u8 *bytes)
618{
619 struct igb_adapter *adapter = netdev_priv(netdev);
620 struct e1000_hw *hw = &adapter->hw;
621 u16 *eeprom_buff;
622 void *ptr;
623 int max_len, first_word, last_word, ret_val = 0;
624 u16 i;
625
626 if (eeprom->len == 0)
627 return -EOPNOTSUPP;
628
629 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
630 return -EFAULT;
631
632 max_len = hw->nvm.word_size * 2;
633
634 first_word = eeprom->offset >> 1;
635 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
636 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
637 if (!eeprom_buff)
638 return -ENOMEM;
639
640 ptr = (void *)eeprom_buff;
641
642 if (eeprom->offset & 1) {
643 /* need read/modify/write of first changed EEPROM word */
644 /* only the second byte of the word is being modified */
312c75ae 645 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 646 &eeprom_buff[0]);
647 ptr++;
648 }
649 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
650 /* need read/modify/write of last changed EEPROM word */
651 /* only the first byte of the word is being modified */
312c75ae 652 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 653 &eeprom_buff[last_word - first_word]);
654 }
655
656 /* Device's eeprom is always little-endian, word addressable */
657 for (i = 0; i < last_word - first_word + 1; i++)
658 le16_to_cpus(&eeprom_buff[i]);
659
660 memcpy(ptr, bytes, eeprom->len);
661
662 for (i = 0; i < last_word - first_word + 1; i++)
663 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
664
312c75ae 665 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 666 last_word - first_word + 1, eeprom_buff);
667
668 /* Update the checksum over the first part of the EEPROM if needed
669 * and flush shadow RAM for 82573 controllers */
670 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
671 igb_update_nvm_checksum(hw);
672
673 kfree(eeprom_buff);
674 return ret_val;
675}
676
677static void igb_get_drvinfo(struct net_device *netdev,
678 struct ethtool_drvinfo *drvinfo)
679{
680 struct igb_adapter *adapter = netdev_priv(netdev);
681 char firmware_version[32];
682 u16 eeprom_data;
683
684 strncpy(drvinfo->driver, igb_driver_name, 32);
685 strncpy(drvinfo->version, igb_driver_version, 32);
686
687 /* EEPROM image version # is reported as firmware version # for
688 * 82575 controllers */
312c75ae 689 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
9d5c8243
AK		 690 sprintf(firmware_version, "%d.%d-%d",
691 (eeprom_data & 0xF000) >> 12,
692 (eeprom_data & 0x0FF0) >> 4,
693 eeprom_data & 0x000F);
694
695 strncpy(drvinfo->fw_version, firmware_version, 32);
696 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
697 drvinfo->n_stats = IGB_STATS_LEN;
698 drvinfo->testinfo_len = IGB_TEST_LEN;
699 drvinfo->regdump_len = igb_get_regs_len(netdev);
700 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
701}
702
703static void igb_get_ringparam(struct net_device *netdev,
704 struct ethtool_ringparam *ring)
705{
706 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 707
708 ring->rx_max_pending = IGB_MAX_RXD;
709 ring->tx_max_pending = IGB_MAX_TXD;
710 ring->rx_mini_max_pending = 0;
711 ring->rx_jumbo_max_pending = 0;
68fd9910
AD		 712 ring->rx_pending = adapter->rx_ring_count;
713 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 714 ring->rx_mini_pending = 0;
715 ring->rx_jumbo_pending = 0;
716}
717
718static int igb_set_ringparam(struct net_device *netdev,
719 struct ethtool_ringparam *ring)
720{
721 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 722 struct igb_ring *temp_ring;
9d5c8243 723 int i, err;
68fd9910 724 u32 new_rx_count, new_tx_count;
9d5c8243
AK		 725
726 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
727 return -EINVAL;
728
729 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
730 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
731 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
732
733 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
734 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
735 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
736
68fd9910
AD		 737 if ((new_tx_count == adapter->tx_ring_count) &&
738 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 739 /* nothing to do */
740 return 0;
741 }
742
68fd9910
AD		 743 if (adapter->num_tx_queues > adapter->num_rx_queues)
744 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
745 else
746 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
747 if (!temp_ring)
748 return -ENOMEM;
749
9d5c8243
AK		 750 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
751 msleep(1);
752
753 if (netif_running(adapter->netdev))
754 igb_down(adapter);
755
756 /*
757 * We can't just free everything and then setup again,
758 * because the ISRs in MSI-X mode get passed pointers
759 * to the tx and rx ring structs.
760 */
68fd9910
AD		 761 if (new_tx_count != adapter->tx_ring_count) {
762 memcpy(temp_ring, adapter->tx_ring,
763 adapter->num_tx_queues * sizeof(struct igb_ring));
764
9d5c8243 765 for (i = 0; i < adapter->num_tx_queues; i++) {
68fd9910
AD		 766 temp_ring[i].count = new_tx_count;
767 err = igb_setup_tx_resources(adapter, &temp_ring[i]);
9d5c8243 768 if (err) {
68fd9910
AD		 769 while (i) {
770 i--;
771 igb_free_tx_resources(&temp_ring[i]);
772 }
9d5c8243
AK		 773 goto err_setup;
774 }
9d5c8243 775 }
68fd9910
AD		 776
777 for (i = 0; i < adapter->num_tx_queues; i++)
778 igb_free_tx_resources(&adapter->tx_ring[i]);
779
780 memcpy(adapter->tx_ring, temp_ring,
781 adapter->num_tx_queues * sizeof(struct igb_ring));
782
783 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 784 }
785
786 if (new_rx_count != adapter->rx_ring->count) {
68fd9910
AD		 787 memcpy(temp_ring, adapter->rx_ring,
788 adapter->num_rx_queues * sizeof(struct igb_ring));
9d5c8243 789
68fd9910
AD		 790 for (i = 0; i < adapter->num_rx_queues; i++) {
791 temp_ring[i].count = new_rx_count;
792 err = igb_setup_rx_resources(adapter, &temp_ring[i]);
9d5c8243 793 if (err) {
68fd9910
AD		 794 while (i) {
795 i--;
796 igb_free_rx_resources(&temp_ring[i]);
797 }
9d5c8243
AK		 798 goto err_setup;
799 }
800
9d5c8243 801 }
68fd9910
AD		 802
803 for (i = 0; i < adapter->num_rx_queues; i++)
804 igb_free_rx_resources(&adapter->rx_ring[i]);
805
806 memcpy(adapter->rx_ring, temp_ring,
807 adapter->num_rx_queues * sizeof(struct igb_ring));
808
809 adapter->rx_ring_count = new_rx_count;
9d5c8243
AK		 810 }
811
812 err = 0;
813err_setup:
814 if (netif_running(adapter->netdev))
815 igb_up(adapter);
816
817 clear_bit(__IGB_RESETTING, &adapter->state);
68fd9910 818 vfree(temp_ring);
9d5c8243
AK		 819 return err;
820}
821
822/* ethtool register test data */
823struct igb_reg_test {
824 u16 reg;
2d064c06
AD		 825 u16 reg_offset;
826 u16 array_len;
827 u16 test_type;
9d5c8243
AK		 828 u32 mask;
829 u32 write;
830};
831
832/* In the hardware, registers are laid out either singly, in arrays
833 * spaced 0x100 bytes apart, or in contiguous tables. We assume
834 * most tests take place on arrays or single registers (handled
835 * as a single-element array) and special-case the tables.
836 * Table tests are always pattern tests.
837 *
838 * We also make provision for some required setup steps by specifying
839 * registers to be written without any read-back testing.
840 */
841
842#define PATTERN_TEST 1
843#define SET_READ_TEST 2
844#define WRITE_NO_TEST 3
845#define TABLE32_TEST 4
846#define TABLE64_TEST_LO 5
847#define TABLE64_TEST_HI 6
848
2d064c06
AD		 849/* 82576 reg test */
850static struct igb_reg_test reg_test_82576[] = {
851 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
852 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
853 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
854 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
855 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
856 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
857 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 858 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
859 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
860 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
861 /* Enable all RX queues before testing. */
862 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
863 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 864 /* RDH is read-only for 82576, only test RDT. */
865 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 866 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 867 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 868 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 869 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
870 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
871 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
872 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
873 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
874 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 875 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
876 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
877 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 878 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
879 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
880 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
881 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
882 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
883 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
884 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
885 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
886 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
887 { 0, 0, 0, 0 }
888};
889
890/* 82575 register test */
9d5c8243 891static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 892 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
893 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
894 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
895 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
896 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
897 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
898 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 899 /* Enable all four RX queues before testing. */
2d064c06 900 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 901 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 902 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
903 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
904 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
905 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
906 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
907 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
908 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
909 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
910 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
911 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
912 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
913 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
914 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
915 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
916 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
917 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 918 { 0, 0, 0, 0 }
919};
920
921static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
922 int reg, u32 mask, u32 write)
923{
2753f4ce 924 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 925 u32 pat, val;
926 u32 _test[] =
927 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
928 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce
AD		 929 wr32(reg, (_test[pat] & write));
930 val = rd32(reg);
9d5c8243
AK		 931 if (val != (_test[pat] & write & mask)) {
932 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
933 "failed: got 0x%08X expected 0x%08X\n",
934 reg, val, (_test[pat] & write & mask));
935 *data = reg;
936 return 1;
937 }
938 }
939 return 0;
940}
941
942static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
943 int reg, u32 mask, u32 write)
944{
2753f4ce 945 struct e1000_hw *hw = &adapter->hw;
9d5c8243 946 u32 val;
2753f4ce
AD		 947 wr32(reg, write & mask);
948 val = rd32(reg);
9d5c8243
AK		 949 if ((write & mask) != (val & mask)) {
950 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
951 " got 0x%08X expected 0x%08X\n", reg,
952 (val & mask), (write & mask));
953 *data = reg;
954 return 1;
955 }
956 return 0;
957}
958
959#define REG_PATTERN_TEST(reg, mask, write) \
960 do { \
961 if (reg_pattern_test(adapter, data, reg, mask, write)) \
962 return 1; \
963 } while (0)
964
965#define REG_SET_AND_CHECK(reg, mask, write) \
966 do { \
967 if (reg_set_and_check(adapter, data, reg, mask, write)) \
968 return 1; \
969 } while (0)
970
971static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
972{
973 struct e1000_hw *hw = &adapter->hw;
974 struct igb_reg_test *test;
975 u32 value, before, after;
976 u32 i, toggle;
977
978 toggle = 0x7FFFF3FF;
2d064c06
AD		 979
980 switch (adapter->hw.mac.type) {
981 case e1000_82576:
982 test = reg_test_82576;
983 break;
984 default:
985 test = reg_test_82575;
986 break;
987 }
9d5c8243
AK		 988
989 /* Because the status register is such a special case,
990 * we handle it separately from the rest of the register
991 * tests. Some bits are read-only, some toggle, and some
992 * are writable on newer MACs.
993 */
994 before = rd32(E1000_STATUS);
995 value = (rd32(E1000_STATUS) & toggle);
996 wr32(E1000_STATUS, toggle);
997 after = rd32(E1000_STATUS) & toggle;
998 if (value != after) {
999 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1000 "got: 0x%08X expected: 0x%08X\n", after, value);
1001 *data = 1;
1002 return 1;
1003 }
1004 /* restore previous status */
1005 wr32(E1000_STATUS, before);
1006
1007 /* Perform the remainder of the register test, looping through
1008 * the test table until we either fail or reach the null entry.
1009 */
1010 while (test->reg) {
1011 for (i = 0; i < test->array_len; i++) {
1012 switch (test->test_type) {
1013 case PATTERN_TEST:
2753f4ce
AD		 1014 REG_PATTERN_TEST(test->reg +
1015 (i * test->reg_offset),
9d5c8243
AK		 1016 test->mask,
1017 test->write);
1018 break;
1019 case SET_READ_TEST:
2753f4ce
AD		 1020 REG_SET_AND_CHECK(test->reg +
1021 (i * test->reg_offset),
9d5c8243
AK		 1022 test->mask,
1023 test->write);
1024 break;
1025 case WRITE_NO_TEST:
1026 writel(test->write,
1027 (adapter->hw.hw_addr + test->reg)
2d064c06 1028 + (i * test->reg_offset));
9d5c8243
AK		 1029 break;
1030 case TABLE32_TEST:
1031 REG_PATTERN_TEST(test->reg + (i * 4),
1032 test->mask,
1033 test->write);
1034 break;
1035 case TABLE64_TEST_LO:
1036 REG_PATTERN_TEST(test->reg + (i * 8),
1037 test->mask,
1038 test->write);
1039 break;
1040 case TABLE64_TEST_HI:
1041 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1042 test->mask,
1043 test->write);
1044 break;
1045 }
1046 }
1047 test++;
1048 }
1049
1050 *data = 0;
1051 return 0;
1052}
1053
1054static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1055{
1056 u16 temp;
1057 u16 checksum = 0;
1058 u16 i;
1059
1060 *data = 0;
1061 /* Read and add up the contents of the EEPROM */
1062 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
312c75ae 1063 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
9d5c8243
AK		 1064 < 0) {
1065 *data = 1;
1066 break;
1067 }
1068 checksum += temp;
1069 }
1070
1071 /* If Checksum is not Correct return error else test passed */
1072 if ((checksum != (u16) NVM_SUM) && !(*data))
1073 *data = 2;
1074
1075 return *data;
1076}
1077
1078static irqreturn_t igb_test_intr(int irq, void *data)
1079{
1080 struct net_device *netdev = (struct net_device *) data;
1081 struct igb_adapter *adapter = netdev_priv(netdev);
1082 struct e1000_hw *hw = &adapter->hw;
1083
1084 adapter->test_icr |= rd32(E1000_ICR);
1085
1086 return IRQ_HANDLED;
1087}
1088
1089static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1090{
1091 struct e1000_hw *hw = &adapter->hw;
1092 struct net_device *netdev = adapter->netdev;
2753f4ce 1093 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1094 u32 irq = adapter->pdev->irq;
1095
1096 *data = 0;
1097
1098 /* Hook up test interrupt handler just for this test */
2753f4ce 1099 if (adapter->msix_entries)
9d5c8243
AK		 1100 /* NOTE: we don't test MSI-X interrupts here, yet */
1101 return 0;
2753f4ce
AD		 1102
1103 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 1104 shared_int = false;
1105 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1106 *data = 1;
1107 return -1;
1108 }
1109 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1110 netdev->name, netdev)) {
1111 shared_int = false;
1112 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1113 netdev->name, netdev)) {
1114 *data = 1;
1115 return -1;
1116 }
1117 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1118 (shared_int ? "shared" : "unshared"));
9d5c8243
AK		 1119 /* Disable all the interrupts */
1120 wr32(E1000_IMC, 0xFFFFFFFF);
1121 msleep(10);
1122
2753f4ce
AD		 1123 /* Define all writable bits for ICS */
1124 switch(hw->mac.type) {
1125 case e1000_82575:
1126 ics_mask = 0x37F47EDD;
1127 break;
1128 case e1000_82576:
1129 ics_mask = 0x77D4FBFD;
1130 break;
1131 default:
1132 ics_mask = 0x7FFFFFFF;
1133 break;
1134 }
1135
9d5c8243 1136 /* Test each interrupt */
2753f4ce 1137 for (; i < 31; i++) {
9d5c8243
AK		 1138 /* Interrupt to test */
1139 mask = 1 << i;
1140
2753f4ce
AD		 1141 if (!(mask & ics_mask))
1142 continue;
1143
9d5c8243
AK		 1144 if (!shared_int) {
1145 /* Disable the interrupt to be reported in
1146 * the cause register and then force the same
1147 * interrupt and see if one gets posted. If
1148 * an interrupt was posted to the bus, the
1149 * test failed.
1150 */
1151 adapter->test_icr = 0;
2753f4ce
AD		 1152
1153 /* Flush any pending interrupts */
1154 wr32(E1000_ICR, ~0);
1155
1156 wr32(E1000_IMC, mask);
1157 wr32(E1000_ICS, mask);
9d5c8243
AK		 1158 msleep(10);
1159
1160 if (adapter->test_icr & mask) {
1161 *data = 3;
1162 break;
1163 }
1164 }
1165
1166 /* Enable the interrupt to be reported in
1167 * the cause register and then force the same
1168 * interrupt and see if one gets posted. If
1169 * an interrupt was not posted to the bus, the
1170 * test failed.
1171 */
1172 adapter->test_icr = 0;
2753f4ce
AD		 1173
1174 /* Flush any pending interrupts */
1175 wr32(E1000_ICR, ~0);
1176
9d5c8243
AK		 1177 wr32(E1000_IMS, mask);
1178 wr32(E1000_ICS, mask);
1179 msleep(10);
1180
1181 if (!(adapter->test_icr & mask)) {
1182 *data = 4;
1183 break;
1184 }
1185
1186 if (!shared_int) {
1187 /* Disable the other interrupts to be reported in
1188 * the cause register and then force the other
1189 * interrupts and see if any get posted. If
1190 * an interrupt was posted to the bus, the
1191 * test failed.
1192 */
1193 adapter->test_icr = 0;
2753f4ce
AD		 1194
1195 /* Flush any pending interrupts */
1196 wr32(E1000_ICR, ~0);
1197
1198 wr32(E1000_IMC, ~mask);
1199 wr32(E1000_ICS, ~mask);
9d5c8243
AK		 1200 msleep(10);
1201
2753f4ce 1202 if (adapter->test_icr & mask) {
9d5c8243
AK		 1203 *data = 5;
1204 break;
1205 }
1206 }
1207 }
1208
1209 /* Disable all the interrupts */
2753f4ce 1210 wr32(E1000_IMC, ~0);
9d5c8243
AK		 1211 msleep(10);
1212
1213 /* Unhook test interrupt handler */
1214 free_irq(irq, netdev);
1215
1216 return *data;
1217}
1218
1219static void igb_free_desc_rings(struct igb_adapter *adapter)
1220{
1221 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1222 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1223 struct pci_dev *pdev = adapter->pdev;
1224 int i;
1225
1226 if (tx_ring->desc && tx_ring->buffer_info) {
1227 for (i = 0; i < tx_ring->count; i++) {
1228 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1229 if (buf->dma)
1230 pci_unmap_single(pdev, buf->dma, buf->length,
1231 PCI_DMA_TODEVICE);
1232 if (buf->skb)
1233 dev_kfree_skb(buf->skb);
1234 }
1235 }
1236
1237 if (rx_ring->desc && rx_ring->buffer_info) {
1238 for (i = 0; i < rx_ring->count; i++) {
1239 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1240 if (buf->dma)
1241 pci_unmap_single(pdev, buf->dma,
1242 IGB_RXBUFFER_2048,
1243 PCI_DMA_FROMDEVICE);
1244 if (buf->skb)
1245 dev_kfree_skb(buf->skb);
1246 }
1247 }
1248
1249 if (tx_ring->desc) {
1250 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1251 tx_ring->dma);
1252 tx_ring->desc = NULL;
1253 }
1254 if (rx_ring->desc) {
1255 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1256 rx_ring->dma);
1257 rx_ring->desc = NULL;
1258 }
1259
1260 kfree(tx_ring->buffer_info);
1261 tx_ring->buffer_info = NULL;
1262 kfree(rx_ring->buffer_info);
1263 rx_ring->buffer_info = NULL;
1264
1265 return;
1266}
1267
1268static int igb_setup_desc_rings(struct igb_adapter *adapter)
1269{
1270 struct e1000_hw *hw = &adapter->hw;
1271 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1272 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1273 struct pci_dev *pdev = adapter->pdev;
1274 u32 rctl;
1275 int i, ret_val;
1276
1277 /* Setup Tx descriptor ring and Tx buffers */
1278
1279 if (!tx_ring->count)
1280 tx_ring->count = IGB_DEFAULT_TXD;
1281
1282 tx_ring->buffer_info = kcalloc(tx_ring->count,
1283 sizeof(struct igb_buffer),
1284 GFP_KERNEL);
1285 if (!tx_ring->buffer_info) {
1286 ret_val = 1;
1287 goto err_nomem;
1288 }
1289
1290 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1291 tx_ring->size = ALIGN(tx_ring->size, 4096);
1292 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1293 &tx_ring->dma);
1294 if (!tx_ring->desc) {
1295 ret_val = 2;
1296 goto err_nomem;
1297 }
1298 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1299
1300 wr32(E1000_TDBAL(0),
1301 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1302 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1303 wr32(E1000_TDLEN(0),
1304 tx_ring->count * sizeof(struct e1000_tx_desc));
1305 wr32(E1000_TDH(0), 0);
1306 wr32(E1000_TDT(0), 0);
1307 wr32(E1000_TCTL,
1308 E1000_TCTL_PSP | E1000_TCTL_EN |
1309 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1310 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1311
1312 for (i = 0; i < tx_ring->count; i++) {
1313 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
1314 struct sk_buff *skb;
1315 unsigned int size = 1024;
1316
1317 skb = alloc_skb(size, GFP_KERNEL);
1318 if (!skb) {
1319 ret_val = 3;
1320 goto err_nomem;
1321 }
1322 skb_put(skb, size);
1323 tx_ring->buffer_info[i].skb = skb;
1324 tx_ring->buffer_info[i].length = skb->len;
1325 tx_ring->buffer_info[i].dma =
1326 pci_map_single(pdev, skb->data, skb->len,
1327 PCI_DMA_TODEVICE);
1328 tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
1329 tx_desc->lower.data = cpu_to_le32(skb->len);
1330 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1331 E1000_TXD_CMD_IFCS |
1332 E1000_TXD_CMD_RS);
1333 tx_desc->upper.data = 0;
1334 }
1335
1336 /* Setup Rx descriptor ring and Rx buffers */
1337
1338 if (!rx_ring->count)
1339 rx_ring->count = IGB_DEFAULT_RXD;
1340
1341 rx_ring->buffer_info = kcalloc(rx_ring->count,
1342 sizeof(struct igb_buffer),
1343 GFP_KERNEL);
1344 if (!rx_ring->buffer_info) {
1345 ret_val = 4;
1346 goto err_nomem;
1347 }
1348
1349 rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
1350 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1351 &rx_ring->dma);
1352 if (!rx_ring->desc) {
1353 ret_val = 5;
1354 goto err_nomem;
1355 }
1356 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1357
1358 rctl = rd32(E1000_RCTL);
1359 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1360 wr32(E1000_RDBAL(0),
1361 ((u64) rx_ring->dma & 0xFFFFFFFF));
1362 wr32(E1000_RDBAH(0),
1363 ((u64) rx_ring->dma >> 32));
1364 wr32(E1000_RDLEN(0), rx_ring->size);
1365 wr32(E1000_RDH(0), 0);
1366 wr32(E1000_RDT(0), 0);
69d728ba 1367 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1368 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
69d728ba 1369 E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1370 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1371 wr32(E1000_RCTL, rctl);
1372 wr32(E1000_SRRCTL(0), 0);
1373
1374 for (i = 0; i < rx_ring->count; i++) {
1375 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
1376 struct sk_buff *skb;
1377
1378 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1379 GFP_KERNEL);
1380 if (!skb) {
1381 ret_val = 6;
1382 goto err_nomem;
1383 }
1384 skb_reserve(skb, NET_IP_ALIGN);
1385 rx_ring->buffer_info[i].skb = skb;
1386 rx_ring->buffer_info[i].dma =
1387 pci_map_single(pdev, skb->data, IGB_RXBUFFER_2048,
1388 PCI_DMA_FROMDEVICE);
1389 rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
1390 memset(skb->data, 0x00, skb->len);
1391 }
1392
1393 return 0;
1394
1395err_nomem:
1396 igb_free_desc_rings(adapter);
1397 return ret_val;
1398}
1399
1400static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403
1404 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1405 igb_write_phy_reg(hw, 29, 0x001F);
1406 igb_write_phy_reg(hw, 30, 0x8FFC);
1407 igb_write_phy_reg(hw, 29, 0x001A);
1408 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1409}
1410
1411static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1412{
1413 struct e1000_hw *hw = &adapter->hw;
1414 u32 ctrl_reg = 0;
1415 u32 stat_reg = 0;
1416
1417 hw->mac.autoneg = false;
1418
1419 if (hw->phy.type == e1000_phy_m88) {
1420 /* Auto-MDI/MDIX Off */
f5f4cf08 1421 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
9d5c8243 1422 /* reset to update Auto-MDI/MDIX */
f5f4cf08 1423 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
9d5c8243 1424 /* autoneg off */
f5f4cf08 1425 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
9d5c8243
AK		 1426 }
1427
1428 ctrl_reg = rd32(E1000_CTRL);
1429
1430 /* force 1000, set loopback */
f5f4cf08 1431 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1432
1433 /* Now set up the MAC to the same speed/duplex as the PHY. */
1434 ctrl_reg = rd32(E1000_CTRL);
1435 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1436 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1437 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1438 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1439 E1000_CTRL_FD); /* Force Duplex to FULL */
1440
1441 if (hw->phy.media_type == e1000_media_type_copper &&
1442 hw->phy.type == e1000_phy_m88)
1443 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1444 else {
1445 /* Set the ILOS bit on the fiber Nic if half duplex link is
1446 * detected. */
1447 stat_reg = rd32(E1000_STATUS);
1448 if ((stat_reg & E1000_STATUS_FD) == 0)
1449 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1450 }
1451
1452 wr32(E1000_CTRL, ctrl_reg);
1453
1454 /* Disable the receiver on the PHY so when a cable is plugged in, the
1455 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1456 */
1457 if (hw->phy.type == e1000_phy_m88)
1458 igb_phy_disable_receiver(adapter);
1459
1460 udelay(500);
1461
1462 return 0;
1463}
1464
1465static int igb_set_phy_loopback(struct igb_adapter *adapter)
1466{
1467 return igb_integrated_phy_loopback(adapter);
1468}
1469
1470static int igb_setup_loopback_test(struct igb_adapter *adapter)
1471{
1472 struct e1000_hw *hw = &adapter->hw;
2d064c06 1473 u32 reg;
9d5c8243
AK		 1474
1475 if (hw->phy.media_type == e1000_media_type_fiber ||
1476 hw->phy.media_type == e1000_media_type_internal_serdes) {
2d064c06
AD		 1477 reg = rd32(E1000_RCTL);
1478 reg |= E1000_RCTL_LBM_TCVR;
1479 wr32(E1000_RCTL, reg);
1480
1481 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1482
1483 reg = rd32(E1000_CTRL);
1484 reg &= ~(E1000_CTRL_RFCE |
1485 E1000_CTRL_TFCE |
1486 E1000_CTRL_LRST);
1487 reg |= E1000_CTRL_SLU |
2753f4ce 1488 E1000_CTRL_FD;
2d064c06
AD		 1489 wr32(E1000_CTRL, reg);
1490
1491 /* Unset switch control to serdes energy detect */
1492 reg = rd32(E1000_CONNSW);
1493 reg &= ~E1000_CONNSW_ENRGSRC;
1494 wr32(E1000_CONNSW, reg);
1495
1496 /* Set PCS register for forced speed */
1497 reg = rd32(E1000_PCS_LCTL);
1498 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1499 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1500 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1501 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1502 E1000_PCS_LCTL_FSD | /* Force Speed */
1503 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1504 wr32(E1000_PCS_LCTL, reg);
1505
9d5c8243
AK		 1506 return 0;
1507 } else if (hw->phy.media_type == e1000_media_type_copper) {
1508 return igb_set_phy_loopback(adapter);
1509 }
1510
1511 return 7;
1512}
1513
1514static void igb_loopback_cleanup(struct igb_adapter *adapter)
1515{
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 rctl;
1518 u16 phy_reg;
1519
1520 rctl = rd32(E1000_RCTL);
1521 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1522 wr32(E1000_RCTL, rctl);
1523
1524 hw->mac.autoneg = true;
f5f4cf08 1525 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1526 if (phy_reg & MII_CR_LOOPBACK) {
1527 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1528 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1529 igb_phy_sw_reset(hw);
1530 }
1531}
1532
1533static void igb_create_lbtest_frame(struct sk_buff *skb,
1534 unsigned int frame_size)
1535{
1536 memset(skb->data, 0xFF, frame_size);
1537 frame_size &= ~1;
1538 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1539 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1540 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1541}
1542
1543static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1544{
1545 frame_size &= ~1;
1546 if (*(skb->data + 3) == 0xFF)
1547 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1548 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1549 return 0;
1550 return 13;
1551}
1552
1553static int igb_run_loopback_test(struct igb_adapter *adapter)
1554{
1555 struct e1000_hw *hw = &adapter->hw;
1556 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1557 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1558 struct pci_dev *pdev = adapter->pdev;
1559 int i, j, k, l, lc, good_cnt;
1560 int ret_val = 0;
1561 unsigned long time;
1562
1563 wr32(E1000_RDT(0), rx_ring->count - 1);
1564
1565 /* Calculate the loop count based on the largest descriptor ring
1566 * The idea is to wrap the largest ring a number of times using 64
1567 * send/receive pairs during each loop
1568 */
1569
1570 if (rx_ring->count <= tx_ring->count)
1571 lc = ((tx_ring->count / 64) * 2) + 1;
1572 else
1573 lc = ((rx_ring->count / 64) * 2) + 1;
1574
1575 k = l = 0;
1576 for (j = 0; j <= lc; j++) { /* loop count loop */
1577 for (i = 0; i < 64; i++) { /* send the packets */
1578 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1579 1024);
1580 pci_dma_sync_single_for_device(pdev,
1581 tx_ring->buffer_info[k].dma,
1582 tx_ring->buffer_info[k].length,
1583 PCI_DMA_TODEVICE);
1584 k++;
1585 if (k == tx_ring->count)
1586 k = 0;
1587 }
1588 wr32(E1000_TDT(0), k);
1589 msleep(200);
1590 time = jiffies; /* set the start time for the receive */
1591 good_cnt = 0;
1592 do { /* receive the sent packets */
1593 pci_dma_sync_single_for_cpu(pdev,
1594 rx_ring->buffer_info[l].dma,
1595 IGB_RXBUFFER_2048,
1596 PCI_DMA_FROMDEVICE);
1597
1598 ret_val = igb_check_lbtest_frame(
1599 rx_ring->buffer_info[l].skb, 1024);
1600 if (!ret_val)
1601 good_cnt++;
1602 l++;
1603 if (l == rx_ring->count)
1604 l = 0;
1605 /* time + 20 msecs (200 msecs on 2.4) is more than
1606 * enough time to complete the receives, if it's
1607 * exceeded, break and error off
1608 */
1609 } while (good_cnt < 64 && jiffies < (time + 20));
1610 if (good_cnt != 64) {
1611 ret_val = 13; /* ret_val is the same as mis-compare */
1612 break;
1613 }
1614 if (jiffies >= (time + 20)) {
1615 ret_val = 14; /* error code for time out error */
1616 break;
1617 }
1618 } /* end loop count loop */
1619 return ret_val;
1620}
1621
1622static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1623{
1624 /* PHY loopback cannot be performed if SoL/IDER
1625 * sessions are active */
1626 if (igb_check_reset_block(&adapter->hw)) {
1627 dev_err(&adapter->pdev->dev,
1628 "Cannot do PHY loopback test "
1629 "when SoL/IDER is active.\n");
1630 *data = 0;
1631 goto out;
1632 }
1633 *data = igb_setup_desc_rings(adapter);
1634 if (*data)
1635 goto out;
1636 *data = igb_setup_loopback_test(adapter);
1637 if (*data)
1638 goto err_loopback;
1639 *data = igb_run_loopback_test(adapter);
1640 igb_loopback_cleanup(adapter);
1641
1642err_loopback:
1643 igb_free_desc_rings(adapter);
1644out:
1645 return *data;
1646}
1647
1648static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1649{
1650 struct e1000_hw *hw = &adapter->hw;
1651 *data = 0;
1652 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1653 int i = 0;
1654 hw->mac.serdes_has_link = false;
1655
1656 /* On some blade server designs, link establishment
1657 * could take as long as 2-3 minutes */
1658 do {
1659 hw->mac.ops.check_for_link(&adapter->hw);
1660 if (hw->mac.serdes_has_link)
1661 return *data;
1662 msleep(20);
1663 } while (i++ < 3750);
1664
1665 *data = 1;
1666 } else {
1667 hw->mac.ops.check_for_link(&adapter->hw);
1668 if (hw->mac.autoneg)
1669 msleep(4000);
1670
1671 if (!(rd32(E1000_STATUS) &
1672 E1000_STATUS_LU))
1673 *data = 1;
1674 }
1675 return *data;
1676}
1677
1678static void igb_diag_test(struct net_device *netdev,
1679 struct ethtool_test *eth_test, u64 *data)
1680{
1681 struct igb_adapter *adapter = netdev_priv(netdev);
1682 u16 autoneg_advertised;
1683 u8 forced_speed_duplex, autoneg;
1684 bool if_running = netif_running(netdev);
1685
1686 set_bit(__IGB_TESTING, &adapter->state);
1687 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1688 /* Offline tests */
1689
1690 /* save speed, duplex, autoneg settings */
1691 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1692 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1693 autoneg = adapter->hw.mac.autoneg;
1694
1695 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1696
1697 /* Link test performed before hardware reset so autoneg doesn't
1698 * interfere with test result */
1699 if (igb_link_test(adapter, &data[4]))
1700 eth_test->flags |= ETH_TEST_FL_FAILED;
1701
1702 if (if_running)
1703 /* indicate we're in test mode */
1704 dev_close(netdev);
1705 else
1706 igb_reset(adapter);
1707
1708 if (igb_reg_test(adapter, &data[0]))
1709 eth_test->flags |= ETH_TEST_FL_FAILED;
1710
1711 igb_reset(adapter);
1712 if (igb_eeprom_test(adapter, &data[1]))
1713 eth_test->flags |= ETH_TEST_FL_FAILED;
1714
1715 igb_reset(adapter);
1716 if (igb_intr_test(adapter, &data[2]))
1717 eth_test->flags |= ETH_TEST_FL_FAILED;
1718
1719 igb_reset(adapter);
1720 if (igb_loopback_test(adapter, &data[3]))
1721 eth_test->flags |= ETH_TEST_FL_FAILED;
1722
1723 /* restore speed, duplex, autoneg settings */
1724 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1725 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1726 adapter->hw.mac.autoneg = autoneg;
1727
1728 /* force this routine to wait until autoneg complete/timeout */
1729 adapter->hw.phy.autoneg_wait_to_complete = true;
1730 igb_reset(adapter);
1731 adapter->hw.phy.autoneg_wait_to_complete = false;
1732
1733 clear_bit(__IGB_TESTING, &adapter->state);
1734 if (if_running)
1735 dev_open(netdev);
1736 } else {
1737 dev_info(&adapter->pdev->dev, "online testing starting\n");
1738 /* Online tests */
1739 if (igb_link_test(adapter, &data[4]))
1740 eth_test->flags |= ETH_TEST_FL_FAILED;
1741
1742 /* Online tests aren't run; pass by default */
1743 data[0] = 0;
1744 data[1] = 0;
1745 data[2] = 0;
1746 data[3] = 0;
1747
1748 clear_bit(__IGB_TESTING, &adapter->state);
1749 }
1750 msleep_interruptible(4 * 1000);
1751}
1752
1753static int igb_wol_exclusion(struct igb_adapter *adapter,
1754 struct ethtool_wolinfo *wol)
1755{
1756 struct e1000_hw *hw = &adapter->hw;
1757 int retval = 1; /* fail by default */
1758
1759 switch (hw->device_id) {
1760 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1761 /* WoL not supported */
1762 wol->supported = 0;
1763 break;
1764 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1765 case E1000_DEV_ID_82576_FIBER:
1766 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1767 /* Wake events not supported on port B */
1768 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1769 wol->supported = 0;
1770 break;
1771 }
7dfc16fa
AD		 1772 /* return success for non excluded adapter ports */
1773 retval = 0;
1774 break;
9d5c8243
AK		 1775 default:
1776 /* dual port cards only support WoL on port A from now on
1777 * unless it was enabled in the eeprom for port B
1778 * so exclude FUNC_1 ports from having WoL enabled */
1779 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1780 !adapter->eeprom_wol) {
1781 wol->supported = 0;
1782 break;
1783 }
1784
1785 retval = 0;
1786 }
1787
1788 return retval;
1789}
1790
1791static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1792{
1793 struct igb_adapter *adapter = netdev_priv(netdev);
1794
1795 wol->supported = WAKE_UCAST | WAKE_MCAST |
1796 WAKE_BCAST | WAKE_MAGIC;
1797 wol->wolopts = 0;
1798
1799 /* this function will set ->supported = 0 and return 1 if wol is not
1800 * supported by this hardware */
e1b86d84
RW		 1801 if (igb_wol_exclusion(adapter, wol) ||
1802 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1803 return;
1804
1805 /* apply any specific unsupported masks here */
1806 switch (adapter->hw.device_id) {
1807 default:
1808 break;
1809 }
1810
1811 if (adapter->wol & E1000_WUFC_EX)
1812 wol->wolopts |= WAKE_UCAST;
1813 if (adapter->wol & E1000_WUFC_MC)
1814 wol->wolopts |= WAKE_MCAST;
1815 if (adapter->wol & E1000_WUFC_BC)
1816 wol->wolopts |= WAKE_BCAST;
1817 if (adapter->wol & E1000_WUFC_MAG)
1818 wol->wolopts |= WAKE_MAGIC;
1819
1820 return;
1821}
1822
1823static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1824{
1825 struct igb_adapter *adapter = netdev_priv(netdev);
1826 struct e1000_hw *hw = &adapter->hw;
1827
1828 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1829 return -EOPNOTSUPP;
1830
e1b86d84
RW		 1831 if (igb_wol_exclusion(adapter, wol) ||
1832 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1833 return wol->wolopts ? -EOPNOTSUPP : 0;
1834
1835 switch (hw->device_id) {
1836 default:
1837 break;
1838 }
1839
1840 /* these settings will always override what we currently have */
1841 adapter->wol = 0;
1842
1843 if (wol->wolopts & WAKE_UCAST)
1844 adapter->wol |= E1000_WUFC_EX;
1845 if (wol->wolopts & WAKE_MCAST)
1846 adapter->wol |= E1000_WUFC_MC;
1847 if (wol->wolopts & WAKE_BCAST)
1848 adapter->wol |= E1000_WUFC_BC;
1849 if (wol->wolopts & WAKE_MAGIC)
1850 adapter->wol |= E1000_WUFC_MAG;
1851
e1b86d84
RW		 1852 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1853
9d5c8243
AK		 1854 return 0;
1855}
1856
1857/* toggle LED 4 times per second = 2 "blinks" per second */
1858#define IGB_ID_INTERVAL (HZ/4)
1859
1860/* bit defines for adapter->led_status */
1861#define IGB_LED_ON 0
1862
1863static int igb_phys_id(struct net_device *netdev, u32 data)
1864{
1865 struct igb_adapter *adapter = netdev_priv(netdev);
1866 struct e1000_hw *hw = &adapter->hw;
1867
1868 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1869 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1870
1871 igb_blink_led(hw);
1872 msleep_interruptible(data * 1000);
1873
1874 igb_led_off(hw);
1875 clear_bit(IGB_LED_ON, &adapter->led_status);
1876 igb_cleanup_led(hw);
1877
1878 return 0;
1879}
1880
1881static int igb_set_coalesce(struct net_device *netdev,
1882 struct ethtool_coalesce *ec)
1883{
1884 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1
AD		 1885 struct e1000_hw *hw = &adapter->hw;
1886 int i;
9d5c8243
AK		 1887
1888 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1889 ((ec->rx_coalesce_usecs > 3) &&
1890 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1891 (ec->rx_coalesce_usecs == 2))
1892 return -EINVAL;
1893
1894 /* convert to rate of irq's per second */
6eb5a7f1 1895 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
9d5c8243 1896 adapter->itr_setting = ec->rx_coalesce_usecs;
6eb5a7f1
AD		 1897 adapter->itr = IGB_START_ITR;
1898 } else {
1899 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1900 adapter->itr = adapter->itr_setting;
1901 }
9d5c8243 1902
6eb5a7f1
AD		 1903 for (i = 0; i < adapter->num_rx_queues; i++)
1904 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
9d5c8243
AK		 1905
1906 return 0;
1907}
1908
1909static int igb_get_coalesce(struct net_device *netdev,
1910 struct ethtool_coalesce *ec)
1911{
1912 struct igb_adapter *adapter = netdev_priv(netdev);
1913
1914 if (adapter->itr_setting <= 3)
1915 ec->rx_coalesce_usecs = adapter->itr_setting;
1916 else
6eb5a7f1 1917 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
9d5c8243
AK		 1918
1919 return 0;
1920}
1921
1922
1923static int igb_nway_reset(struct net_device *netdev)
1924{
1925 struct igb_adapter *adapter = netdev_priv(netdev);
1926 if (netif_running(netdev))
1927 igb_reinit_locked(adapter);
1928 return 0;
1929}
1930
1931static int igb_get_sset_count(struct net_device *netdev, int sset)
1932{
1933 switch (sset) {
1934 case ETH_SS_STATS:
1935 return IGB_STATS_LEN;
1936 case ETH_SS_TEST:
1937 return IGB_TEST_LEN;
1938 default:
1939 return -ENOTSUPP;
1940 }
1941}
1942
1943static void igb_get_ethtool_stats(struct net_device *netdev,
1944 struct ethtool_stats *stats, u64 *data)
1945{
1946 struct igb_adapter *adapter = netdev_priv(netdev);
1947 u64 *queue_stat;
1948 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1949 int j;
1950 int i;
1951
1952 igb_update_stats(adapter);
1953 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1954 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1955 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1956 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1957 }
e21ed353
AD		 1958 for (j = 0; j < adapter->num_tx_queues; j++) {
1959 int k;
1960 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1961 for (k = 0; k < stat_count; k++)
1962 data[i + k] = queue_stat[k];
1963 i += k;
1964 }
9d5c8243
AK		 1965 for (j = 0; j < adapter->num_rx_queues; j++) {
1966 int k;
1967 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1968 for (k = 0; k < stat_count; k++)
1969 data[i + k] = queue_stat[k];
1970 i += k;
1971 }
1972}
1973
1974static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1975{
1976 struct igb_adapter *adapter = netdev_priv(netdev);
1977 u8 *p = data;
1978 int i;
1979
1980 switch (stringset) {
1981 case ETH_SS_TEST:
1982 memcpy(data, *igb_gstrings_test,
1983 IGB_TEST_LEN*ETH_GSTRING_LEN);
1984 break;
1985 case ETH_SS_STATS:
1986 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1987 memcpy(p, igb_gstrings_stats[i].stat_string,
1988 ETH_GSTRING_LEN);
1989 p += ETH_GSTRING_LEN;
1990 }
1991 for (i = 0; i < adapter->num_tx_queues; i++) {
1992 sprintf(p, "tx_queue_%u_packets", i);
1993 p += ETH_GSTRING_LEN;
1994 sprintf(p, "tx_queue_%u_bytes", i);
1995 p += ETH_GSTRING_LEN;
1996 }
1997 for (i = 0; i < adapter->num_rx_queues; i++) {
1998 sprintf(p, "rx_queue_%u_packets", i);
1999 p += ETH_GSTRING_LEN;
2000 sprintf(p, "rx_queue_%u_bytes", i);
2001 p += ETH_GSTRING_LEN;
2002 }
2003/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2004 break;
2005 }
2006}
2007
2008static struct ethtool_ops igb_ethtool_ops = {
2009 .get_settings = igb_get_settings,
2010 .set_settings = igb_set_settings,
2011 .get_drvinfo = igb_get_drvinfo,
2012 .get_regs_len = igb_get_regs_len,
2013 .get_regs = igb_get_regs,
2014 .get_wol = igb_get_wol,
2015 .set_wol = igb_set_wol,
2016 .get_msglevel = igb_get_msglevel,
2017 .set_msglevel = igb_set_msglevel,
2018 .nway_reset = igb_nway_reset,
2019 .get_link = ethtool_op_get_link,
2020 .get_eeprom_len = igb_get_eeprom_len,
2021 .get_eeprom = igb_get_eeprom,
2022 .set_eeprom = igb_set_eeprom,
2023 .get_ringparam = igb_get_ringparam,
2024 .set_ringparam = igb_set_ringparam,
2025 .get_pauseparam = igb_get_pauseparam,
2026 .set_pauseparam = igb_set_pauseparam,
2027 .get_rx_csum = igb_get_rx_csum,
2028 .set_rx_csum = igb_set_rx_csum,
2029 .get_tx_csum = igb_get_tx_csum,
2030 .set_tx_csum = igb_set_tx_csum,
2031 .get_sg = ethtool_op_get_sg,
2032 .set_sg = ethtool_op_set_sg,
2033 .get_tso = ethtool_op_get_tso,
2034 .set_tso = igb_set_tso,
2035 .self_test = igb_diag_test,
2036 .get_strings = igb_get_strings,
2037 .phys_id = igb_phys_id,
2038 .get_sset_count = igb_get_sset_count,
2039 .get_ethtool_stats = igb_get_ethtool_stats,
2040 .get_coalesce = igb_get_coalesce,
2041 .set_coalesce = igb_set_coalesce,
2042};
2043
2044void igb_set_ethtool_ops(struct net_device *netdev)
2045{
2046 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2047}
Linux kernel - Deliverables
This page took 0.387876 seconds and 5 git commands to generate.