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igb: fix memory leak when setting ring size while interface is down
[deliverable/linux.git] / drivers / net / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
37
38#include "igb.h"
39
40struct igb_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44};
45
030ed68b 46#define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
9d5c8243
AK		 47 offsetof(struct igb_adapter, m)
48static const struct igb_stats igb_gstrings_stats[] = {
49 { "rx_packets", IGB_STAT(stats.gprc) },
50 { "tx_packets", IGB_STAT(stats.gptc) },
51 { "rx_bytes", IGB_STAT(stats.gorc) },
52 { "tx_bytes", IGB_STAT(stats.gotc) },
53 { "rx_broadcast", IGB_STAT(stats.bprc) },
54 { "tx_broadcast", IGB_STAT(stats.bptc) },
55 { "rx_multicast", IGB_STAT(stats.mprc) },
56 { "tx_multicast", IGB_STAT(stats.mptc) },
57 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
58 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
59 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
60 { "multicast", IGB_STAT(stats.mprc) },
61 { "collisions", IGB_STAT(stats.colc) },
62 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
63 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
64 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
65 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
66 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
3ea73afa 67 { "rx_queue_drop_packet_count", IGB_STAT(net_stats.rx_fifo_errors) },
9d5c8243
AK		 68 { "rx_missed_errors", IGB_STAT(stats.mpc) },
69 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
70 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
71 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
72 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
73 { "tx_window_errors", IGB_STAT(stats.latecol) },
74 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
75 { "tx_deferred_ok", IGB_STAT(stats.dc) },
76 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
77 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
78 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
79 { "tx_restart_queue", IGB_STAT(restart_queue) },
80 { "rx_long_length_errors", IGB_STAT(stats.roc) },
81 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
82 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
83 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
84 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
85 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
86 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
87 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
88 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
89 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
90 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
91 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
dda0e083 92 { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
9d5c8243
AK		 93 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
94 { "tx_smbus", IGB_STAT(stats.mgptc) },
95 { "rx_smbus", IGB_STAT(stats.mgprc) },
96 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
97};
98
99#define IGB_QUEUE_STATS_LEN \
8c0ab70a
JDB		 100 (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
101 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
102 ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
103 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
9d5c8243
AK		 104#define IGB_GLOBAL_STATS_LEN \
105 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
106#define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
107static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
108 "Register test (offline)", "Eeprom test (offline)",
109 "Interrupt test (offline)", "Loopback test (offline)",
110 "Link test (on/offline)"
111};
112#define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
113
114static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
115{
116 struct igb_adapter *adapter = netdev_priv(netdev);
117 struct e1000_hw *hw = &adapter->hw;
118
119 if (hw->phy.media_type == e1000_media_type_copper) {
120
121 ecmd->supported = (SUPPORTED_10baseT_Half |
122 SUPPORTED_10baseT_Full |
123 SUPPORTED_100baseT_Half |
124 SUPPORTED_100baseT_Full |
125 SUPPORTED_1000baseT_Full|
126 SUPPORTED_Autoneg |
127 SUPPORTED_TP);
128 ecmd->advertising = ADVERTISED_TP;
129
130 if (hw->mac.autoneg == 1) {
131 ecmd->advertising |= ADVERTISED_Autoneg;
132 /* the e1000 autoneg seems to match ethtool nicely */
133 ecmd->advertising |= hw->phy.autoneg_advertised;
134 }
135
136 ecmd->port = PORT_TP;
137 ecmd->phy_address = hw->phy.addr;
138 } else {
139 ecmd->supported = (SUPPORTED_1000baseT_Full |
140 SUPPORTED_FIBRE |
141 SUPPORTED_Autoneg);
142
143 ecmd->advertising = (ADVERTISED_1000baseT_Full |
144 ADVERTISED_FIBRE |
145 ADVERTISED_Autoneg);
146
147 ecmd->port = PORT_FIBRE;
148 }
149
150 ecmd->transceiver = XCVR_INTERNAL;
151
152 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
153
154 adapter->hw.mac.ops.get_speed_and_duplex(hw,
155 &adapter->link_speed,
156 &adapter->link_duplex);
157 ecmd->speed = adapter->link_speed;
158
159 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
160 * and HALF_DUPLEX != DUPLEX_HALF */
161
162 if (adapter->link_duplex == FULL_DUPLEX)
163 ecmd->duplex = DUPLEX_FULL;
164 else
165 ecmd->duplex = DUPLEX_HALF;
166 } else {
167 ecmd->speed = -1;
168 ecmd->duplex = -1;
169 }
170
dcc3ae9a 171 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
9d5c8243
AK		 172 return 0;
173}
174
175static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
176{
177 struct igb_adapter *adapter = netdev_priv(netdev);
178 struct e1000_hw *hw = &adapter->hw;
179
180 /* When SoL/IDER sessions are active, autoneg/speed/duplex
181 * cannot be changed */
182 if (igb_check_reset_block(hw)) {
183 dev_err(&adapter->pdev->dev, "Cannot change link "
184 "characteristics when SoL/IDER is active.\n");
185 return -EINVAL;
186 }
187
188 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
189 msleep(1);
190
191 if (ecmd->autoneg == AUTONEG_ENABLE) {
192 hw->mac.autoneg = 1;
dcc3ae9a
AD		 193 hw->phy.autoneg_advertised = ecmd->advertising |
194 ADVERTISED_TP |
195 ADVERTISED_Autoneg;
9d5c8243 196 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 197 if (adapter->fc_autoneg)
198 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 199 } else {
9d5c8243
AK		 200 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
201 clear_bit(__IGB_RESETTING, &adapter->state);
202 return -EINVAL;
203 }
dcc3ae9a 204 }
9d5c8243
AK		 205
206 /* reset the link */
9d5c8243
AK		 207 if (netif_running(adapter->netdev)) {
208 igb_down(adapter);
209 igb_up(adapter);
210 } else
211 igb_reset(adapter);
212
213 clear_bit(__IGB_RESETTING, &adapter->state);
214 return 0;
215}
216
217static void igb_get_pauseparam(struct net_device *netdev,
218 struct ethtool_pauseparam *pause)
219{
220 struct igb_adapter *adapter = netdev_priv(netdev);
221 struct e1000_hw *hw = &adapter->hw;
222
223 pause->autoneg =
224 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
225
0cce119a 226 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 227 pause->rx_pause = 1;
0cce119a 228 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 229 pause->tx_pause = 1;
0cce119a 230 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 231 pause->rx_pause = 1;
232 pause->tx_pause = 1;
233 }
234}
235
236static int igb_set_pauseparam(struct net_device *netdev,
237 struct ethtool_pauseparam *pause)
238{
239 struct igb_adapter *adapter = netdev_priv(netdev);
240 struct e1000_hw *hw = &adapter->hw;
241 int retval = 0;
242
243 adapter->fc_autoneg = pause->autoneg;
244
245 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
246 msleep(1);
247
9d5c8243 248 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 249 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 250 if (netif_running(adapter->netdev)) {
251 igb_down(adapter);
252 igb_up(adapter);
253 } else
254 igb_reset(adapter);
0cce119a
AD		 255 } else {
256 if (pause->rx_pause && pause->tx_pause)
257 hw->fc.requested_mode = e1000_fc_full;
258 else if (pause->rx_pause && !pause->tx_pause)
259 hw->fc.requested_mode = e1000_fc_rx_pause;
260 else if (!pause->rx_pause && pause->tx_pause)
261 hw->fc.requested_mode = e1000_fc_tx_pause;
262 else if (!pause->rx_pause && !pause->tx_pause)
263 hw->fc.requested_mode = e1000_fc_none;
264
265 hw->fc.current_mode = hw->fc.requested_mode;
266
dcc3ae9a
AD		 267 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
268 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 269 }
9d5c8243
AK		 270
271 clear_bit(__IGB_RESETTING, &adapter->state);
272 return retval;
273}
274
275static u32 igb_get_rx_csum(struct net_device *netdev)
276{
277 struct igb_adapter *adapter = netdev_priv(netdev);
7beb0146 278 return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
9d5c8243
AK		 279}
280
281static int igb_set_rx_csum(struct net_device *netdev, u32 data)
282{
283 struct igb_adapter *adapter = netdev_priv(netdev);
7beb0146
AD		 284
285 if (data)
286 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
287 else
288 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
9d5c8243
AK		 289
290 return 0;
291}
292
293static u32 igb_get_tx_csum(struct net_device *netdev)
294{
7d8eb29e 295 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9d5c8243
AK		 296}
297
298static int igb_set_tx_csum(struct net_device *netdev, u32 data)
299{
b9473560
JB		 300 struct igb_adapter *adapter = netdev_priv(netdev);
301
302 if (data) {
7d8eb29e 303 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b9473560
JB		 304 if (adapter->hw.mac.type == e1000_82576)
305 netdev->features |= NETIF_F_SCTP_CSUM;
306 } else {
307 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
308 NETIF_F_SCTP_CSUM);
309 }
9d5c8243
AK		 310
311 return 0;
312}
313
314static int igb_set_tso(struct net_device *netdev, u32 data)
315{
316 struct igb_adapter *adapter = netdev_priv(netdev);
317
7d8eb29e 318 if (data) {
9d5c8243 319 netdev->features |= NETIF_F_TSO;
9d5c8243 320 netdev->features |= NETIF_F_TSO6;
7d8eb29e
AD		 321 } else {
322 netdev->features &= ~NETIF_F_TSO;
9d5c8243 323 netdev->features &= ~NETIF_F_TSO6;
7d8eb29e 324 }
9d5c8243
AK		 325
326 dev_info(&adapter->pdev->dev, "TSO is %s\n",
327 data ? "Enabled" : "Disabled");
328 return 0;
329}
330
331static u32 igb_get_msglevel(struct net_device *netdev)
332{
333 struct igb_adapter *adapter = netdev_priv(netdev);
334 return adapter->msg_enable;
335}
336
337static void igb_set_msglevel(struct net_device *netdev, u32 data)
338{
339 struct igb_adapter *adapter = netdev_priv(netdev);
340 adapter->msg_enable = data;
341}
342
343static int igb_get_regs_len(struct net_device *netdev)
344{
345#define IGB_REGS_LEN 551
346 return IGB_REGS_LEN * sizeof(u32);
347}
348
349static void igb_get_regs(struct net_device *netdev,
350 struct ethtool_regs *regs, void *p)
351{
352 struct igb_adapter *adapter = netdev_priv(netdev);
353 struct e1000_hw *hw = &adapter->hw;
354 u32 *regs_buff = p;
355 u8 i;
356
357 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
358
359 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
360
361 /* General Registers */
362 regs_buff[0] = rd32(E1000_CTRL);
363 regs_buff[1] = rd32(E1000_STATUS);
364 regs_buff[2] = rd32(E1000_CTRL_EXT);
365 regs_buff[3] = rd32(E1000_MDIC);
366 regs_buff[4] = rd32(E1000_SCTL);
367 regs_buff[5] = rd32(E1000_CONNSW);
368 regs_buff[6] = rd32(E1000_VET);
369 regs_buff[7] = rd32(E1000_LEDCTL);
370 regs_buff[8] = rd32(E1000_PBA);
371 regs_buff[9] = rd32(E1000_PBS);
372 regs_buff[10] = rd32(E1000_FRTIMER);
373 regs_buff[11] = rd32(E1000_TCPTIMER);
374
375 /* NVM Register */
376 regs_buff[12] = rd32(E1000_EECD);
377
378 /* Interrupt */
fe59de38
AD		 379 /* Reading EICS for EICR because they read the
380 * same but EICS does not clear on read */
381 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 382 regs_buff[14] = rd32(E1000_EICS);
383 regs_buff[15] = rd32(E1000_EIMS);
384 regs_buff[16] = rd32(E1000_EIMC);
385 regs_buff[17] = rd32(E1000_EIAC);
386 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 387 /* Reading ICS for ICR because they read the
388 * same but ICS does not clear on read */
389 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 390 regs_buff[20] = rd32(E1000_ICS);
391 regs_buff[21] = rd32(E1000_IMS);
392 regs_buff[22] = rd32(E1000_IMC);
393 regs_buff[23] = rd32(E1000_IAC);
394 regs_buff[24] = rd32(E1000_IAM);
395 regs_buff[25] = rd32(E1000_IMIRVP);
396
397 /* Flow Control */
398 regs_buff[26] = rd32(E1000_FCAL);
399 regs_buff[27] = rd32(E1000_FCAH);
400 regs_buff[28] = rd32(E1000_FCTTV);
401 regs_buff[29] = rd32(E1000_FCRTL);
402 regs_buff[30] = rd32(E1000_FCRTH);
403 regs_buff[31] = rd32(E1000_FCRTV);
404
405 /* Receive */
406 regs_buff[32] = rd32(E1000_RCTL);
407 regs_buff[33] = rd32(E1000_RXCSUM);
408 regs_buff[34] = rd32(E1000_RLPML);
409 regs_buff[35] = rd32(E1000_RFCTL);
410 regs_buff[36] = rd32(E1000_MRQC);
e1739522 411 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 412
413 /* Transmit */
414 regs_buff[38] = rd32(E1000_TCTL);
415 regs_buff[39] = rd32(E1000_TCTL_EXT);
416 regs_buff[40] = rd32(E1000_TIPG);
417 regs_buff[41] = rd32(E1000_DTXCTL);
418
419 /* Wake Up */
420 regs_buff[42] = rd32(E1000_WUC);
421 regs_buff[43] = rd32(E1000_WUFC);
422 regs_buff[44] = rd32(E1000_WUS);
423 regs_buff[45] = rd32(E1000_IPAV);
424 regs_buff[46] = rd32(E1000_WUPL);
425
426 /* MAC */
427 regs_buff[47] = rd32(E1000_PCS_CFG0);
428 regs_buff[48] = rd32(E1000_PCS_LCTL);
429 regs_buff[49] = rd32(E1000_PCS_LSTAT);
430 regs_buff[50] = rd32(E1000_PCS_ANADV);
431 regs_buff[51] = rd32(E1000_PCS_LPAB);
432 regs_buff[52] = rd32(E1000_PCS_NPTX);
433 regs_buff[53] = rd32(E1000_PCS_LPABNP);
434
435 /* Statistics */
436 regs_buff[54] = adapter->stats.crcerrs;
437 regs_buff[55] = adapter->stats.algnerrc;
438 regs_buff[56] = adapter->stats.symerrs;
439 regs_buff[57] = adapter->stats.rxerrc;
440 regs_buff[58] = adapter->stats.mpc;
441 regs_buff[59] = adapter->stats.scc;
442 regs_buff[60] = adapter->stats.ecol;
443 regs_buff[61] = adapter->stats.mcc;
444 regs_buff[62] = adapter->stats.latecol;
445 regs_buff[63] = adapter->stats.colc;
446 regs_buff[64] = adapter->stats.dc;
447 regs_buff[65] = adapter->stats.tncrs;
448 regs_buff[66] = adapter->stats.sec;
449 regs_buff[67] = adapter->stats.htdpmc;
450 regs_buff[68] = adapter->stats.rlec;
451 regs_buff[69] = adapter->stats.xonrxc;
452 regs_buff[70] = adapter->stats.xontxc;
453 regs_buff[71] = adapter->stats.xoffrxc;
454 regs_buff[72] = adapter->stats.xofftxc;
455 regs_buff[73] = adapter->stats.fcruc;
456 regs_buff[74] = adapter->stats.prc64;
457 regs_buff[75] = adapter->stats.prc127;
458 regs_buff[76] = adapter->stats.prc255;
459 regs_buff[77] = adapter->stats.prc511;
460 regs_buff[78] = adapter->stats.prc1023;
461 regs_buff[79] = adapter->stats.prc1522;
462 regs_buff[80] = adapter->stats.gprc;
463 regs_buff[81] = adapter->stats.bprc;
464 regs_buff[82] = adapter->stats.mprc;
465 regs_buff[83] = adapter->stats.gptc;
466 regs_buff[84] = adapter->stats.gorc;
467 regs_buff[86] = adapter->stats.gotc;
468 regs_buff[88] = adapter->stats.rnbc;
469 regs_buff[89] = adapter->stats.ruc;
470 regs_buff[90] = adapter->stats.rfc;
471 regs_buff[91] = adapter->stats.roc;
472 regs_buff[92] = adapter->stats.rjc;
473 regs_buff[93] = adapter->stats.mgprc;
474 regs_buff[94] = adapter->stats.mgpdc;
475 regs_buff[95] = adapter->stats.mgptc;
476 regs_buff[96] = adapter->stats.tor;
477 regs_buff[98] = adapter->stats.tot;
478 regs_buff[100] = adapter->stats.tpr;
479 regs_buff[101] = adapter->stats.tpt;
480 regs_buff[102] = adapter->stats.ptc64;
481 regs_buff[103] = adapter->stats.ptc127;
482 regs_buff[104] = adapter->stats.ptc255;
483 regs_buff[105] = adapter->stats.ptc511;
484 regs_buff[106] = adapter->stats.ptc1023;
485 regs_buff[107] = adapter->stats.ptc1522;
486 regs_buff[108] = adapter->stats.mptc;
487 regs_buff[109] = adapter->stats.bptc;
488 regs_buff[110] = adapter->stats.tsctc;
489 regs_buff[111] = adapter->stats.iac;
490 regs_buff[112] = adapter->stats.rpthc;
491 regs_buff[113] = adapter->stats.hgptc;
492 regs_buff[114] = adapter->stats.hgorc;
493 regs_buff[116] = adapter->stats.hgotc;
494 regs_buff[118] = adapter->stats.lenerrs;
495 regs_buff[119] = adapter->stats.scvpc;
496 regs_buff[120] = adapter->stats.hrmpc;
497
498 /* These should probably be added to e1000_regs.h instead */
499 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
9d5c8243
AK		 500 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
501 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
502 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
503 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
504 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
505 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
506
507 for (i = 0; i < 4; i++)
508 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
509 for (i = 0; i < 4; i++)
510 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
511 for (i = 0; i < 4; i++)
512 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
513 for (i = 0; i < 4; i++)
514 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
515 for (i = 0; i < 4; i++)
516 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
517 for (i = 0; i < 4; i++)
518 regs_buff[141 + i] = rd32(E1000_RDH(i));
519 for (i = 0; i < 4; i++)
520 regs_buff[145 + i] = rd32(E1000_RDT(i));
521 for (i = 0; i < 4; i++)
522 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
523
524 for (i = 0; i < 10; i++)
525 regs_buff[153 + i] = rd32(E1000_EITR(i));
526 for (i = 0; i < 8; i++)
527 regs_buff[163 + i] = rd32(E1000_IMIR(i));
528 for (i = 0; i < 8; i++)
529 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
530 for (i = 0; i < 16; i++)
531 regs_buff[179 + i] = rd32(E1000_RAL(i));
532 for (i = 0; i < 16; i++)
533 regs_buff[195 + i] = rd32(E1000_RAH(i));
534
535 for (i = 0; i < 4; i++)
536 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
537 for (i = 0; i < 4; i++)
538 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
539 for (i = 0; i < 4; i++)
540 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
541 for (i = 0; i < 4; i++)
542 regs_buff[223 + i] = rd32(E1000_TDH(i));
543 for (i = 0; i < 4; i++)
544 regs_buff[227 + i] = rd32(E1000_TDT(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
547 for (i = 0; i < 4; i++)
548 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
549 for (i = 0; i < 4; i++)
550 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
551 for (i = 0; i < 4; i++)
552 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
553
554 for (i = 0; i < 4; i++)
555 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
556 for (i = 0; i < 4; i++)
557 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
558 for (i = 0; i < 32; i++)
559 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
560 for (i = 0; i < 128; i++)
561 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
562 for (i = 0; i < 128; i++)
563 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
564 for (i = 0; i < 4; i++)
565 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
566
567 regs_buff[547] = rd32(E1000_TDFH);
568 regs_buff[548] = rd32(E1000_TDFT);
569 regs_buff[549] = rd32(E1000_TDFHS);
570 regs_buff[550] = rd32(E1000_TDFPC);
571
572}
573
574static int igb_get_eeprom_len(struct net_device *netdev)
575{
576 struct igb_adapter *adapter = netdev_priv(netdev);
577 return adapter->hw.nvm.word_size * 2;
578}
579
580static int igb_get_eeprom(struct net_device *netdev,
581 struct ethtool_eeprom *eeprom, u8 *bytes)
582{
583 struct igb_adapter *adapter = netdev_priv(netdev);
584 struct e1000_hw *hw = &adapter->hw;
585 u16 *eeprom_buff;
586 int first_word, last_word;
587 int ret_val = 0;
588 u16 i;
589
590 if (eeprom->len == 0)
591 return -EINVAL;
592
593 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
594
595 first_word = eeprom->offset >> 1;
596 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
597
598 eeprom_buff = kmalloc(sizeof(u16) *
599 (last_word - first_word + 1), GFP_KERNEL);
600 if (!eeprom_buff)
601 return -ENOMEM;
602
603 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 604 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 605 last_word - first_word + 1,
606 eeprom_buff);
607 else {
608 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 609 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 610 &eeprom_buff[i]);
611 if (ret_val)
612 break;
613 }
614 }
615
616 /* Device's eeprom is always little-endian, word addressable */
617 for (i = 0; i < last_word - first_word + 1; i++)
618 le16_to_cpus(&eeprom_buff[i]);
619
620 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
621 eeprom->len);
622 kfree(eeprom_buff);
623
624 return ret_val;
625}
626
627static int igb_set_eeprom(struct net_device *netdev,
628 struct ethtool_eeprom *eeprom, u8 *bytes)
629{
630 struct igb_adapter *adapter = netdev_priv(netdev);
631 struct e1000_hw *hw = &adapter->hw;
632 u16 *eeprom_buff;
633 void *ptr;
634 int max_len, first_word, last_word, ret_val = 0;
635 u16 i;
636
637 if (eeprom->len == 0)
638 return -EOPNOTSUPP;
639
640 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
641 return -EFAULT;
642
643 max_len = hw->nvm.word_size * 2;
644
645 first_word = eeprom->offset >> 1;
646 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
647 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
648 if (!eeprom_buff)
649 return -ENOMEM;
650
651 ptr = (void *)eeprom_buff;
652
653 if (eeprom->offset & 1) {
654 /* need read/modify/write of first changed EEPROM word */
655 /* only the second byte of the word is being modified */
312c75ae 656 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 657 &eeprom_buff[0]);
658 ptr++;
659 }
660 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
661 /* need read/modify/write of last changed EEPROM word */
662 /* only the first byte of the word is being modified */
312c75ae 663 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 664 &eeprom_buff[last_word - first_word]);
665 }
666
667 /* Device's eeprom is always little-endian, word addressable */
668 for (i = 0; i < last_word - first_word + 1; i++)
669 le16_to_cpus(&eeprom_buff[i]);
670
671 memcpy(ptr, bytes, eeprom->len);
672
673 for (i = 0; i < last_word - first_word + 1; i++)
674 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
675
312c75ae 676 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 677 last_word - first_word + 1, eeprom_buff);
678
679 /* Update the checksum over the first part of the EEPROM if needed
680 * and flush shadow RAM for 82573 controllers */
681 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
682 igb_update_nvm_checksum(hw);
683
684 kfree(eeprom_buff);
685 return ret_val;
686}
687
688static void igb_get_drvinfo(struct net_device *netdev,
689 struct ethtool_drvinfo *drvinfo)
690{
691 struct igb_adapter *adapter = netdev_priv(netdev);
692 char firmware_version[32];
693 u16 eeprom_data;
694
695 strncpy(drvinfo->driver, igb_driver_name, 32);
696 strncpy(drvinfo->version, igb_driver_version, 32);
697
698 /* EEPROM image version # is reported as firmware version # for
699 * 82575 controllers */
312c75ae 700 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
9d5c8243
AK		 701 sprintf(firmware_version, "%d.%d-%d",
702 (eeprom_data & 0xF000) >> 12,
703 (eeprom_data & 0x0FF0) >> 4,
704 eeprom_data & 0x000F);
705
706 strncpy(drvinfo->fw_version, firmware_version, 32);
707 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
708 drvinfo->n_stats = IGB_STATS_LEN;
709 drvinfo->testinfo_len = IGB_TEST_LEN;
710 drvinfo->regdump_len = igb_get_regs_len(netdev);
711 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
712}
713
714static void igb_get_ringparam(struct net_device *netdev,
715 struct ethtool_ringparam *ring)
716{
717 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 718
719 ring->rx_max_pending = IGB_MAX_RXD;
720 ring->tx_max_pending = IGB_MAX_TXD;
721 ring->rx_mini_max_pending = 0;
722 ring->rx_jumbo_max_pending = 0;
68fd9910
AD		 723 ring->rx_pending = adapter->rx_ring_count;
724 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 725 ring->rx_mini_pending = 0;
726 ring->rx_jumbo_pending = 0;
727}
728
729static int igb_set_ringparam(struct net_device *netdev,
730 struct ethtool_ringparam *ring)
731{
732 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 733 struct igb_ring *temp_ring;
6d9f4fc4 734 int i, err = 0;
68fd9910 735 u32 new_rx_count, new_tx_count;
9d5c8243
AK		 736
737 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
738 return -EINVAL;
739
740 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
741 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
742 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
743
744 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
745 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
746 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
747
68fd9910
AD		 748 if ((new_tx_count == adapter->tx_ring_count) &&
749 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 750 /* nothing to do */
751 return 0;
752 }
753
6d9f4fc4
AD		 754 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
755 msleep(1);
756
757 if (!netif_running(adapter->netdev)) {
758 for (i = 0; i < adapter->num_tx_queues; i++)
759 adapter->tx_ring[i].count = new_tx_count;
760 for (i = 0; i < adapter->num_rx_queues; i++)
761 adapter->rx_ring[i].count = new_rx_count;
762 adapter->tx_ring_count = new_tx_count;
763 adapter->rx_ring_count = new_rx_count;
764 goto clear_reset;
765 }
766
68fd9910
AD		 767 if (adapter->num_tx_queues > adapter->num_rx_queues)
768 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
769 else
770 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 771
6d9f4fc4
AD		 772 if (!temp_ring) {
773 err = -ENOMEM;
774 goto clear_reset;
775 }
9d5c8243 776
6d9f4fc4 777 igb_down(adapter);
9d5c8243
AK		 778
779 /*
780 * We can't just free everything and then setup again,
781 * because the ISRs in MSI-X mode get passed pointers
782 * to the tx and rx ring structs.
783 */
68fd9910
AD		 784 if (new_tx_count != adapter->tx_ring_count) {
785 memcpy(temp_ring, adapter->tx_ring,
786 adapter->num_tx_queues * sizeof(struct igb_ring));
787
9d5c8243 788 for (i = 0; i < adapter->num_tx_queues; i++) {
68fd9910
AD		 789 temp_ring[i].count = new_tx_count;
790 err = igb_setup_tx_resources(adapter, &temp_ring[i]);
9d5c8243 791 if (err) {
68fd9910
AD		 792 while (i) {
793 i--;
794 igb_free_tx_resources(&temp_ring[i]);
795 }
9d5c8243
AK		 796 goto err_setup;
797 }
9d5c8243 798 }
68fd9910
AD		 799
800 for (i = 0; i < adapter->num_tx_queues; i++)
801 igb_free_tx_resources(&adapter->tx_ring[i]);
802
803 memcpy(adapter->tx_ring, temp_ring,
804 adapter->num_tx_queues * sizeof(struct igb_ring));
805
806 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 807 }
808
809 if (new_rx_count != adapter->rx_ring->count) {
68fd9910
AD		 810 memcpy(temp_ring, adapter->rx_ring,
811 adapter->num_rx_queues * sizeof(struct igb_ring));
9d5c8243 812
68fd9910
AD		 813 for (i = 0; i < adapter->num_rx_queues; i++) {
814 temp_ring[i].count = new_rx_count;
815 err = igb_setup_rx_resources(adapter, &temp_ring[i]);
9d5c8243 816 if (err) {
68fd9910
AD		 817 while (i) {
818 i--;
819 igb_free_rx_resources(&temp_ring[i]);
820 }
9d5c8243
AK		 821 goto err_setup;
822 }
823
9d5c8243 824 }
68fd9910
AD		 825
826 for (i = 0; i < adapter->num_rx_queues; i++)
827 igb_free_rx_resources(&adapter->rx_ring[i]);
828
829 memcpy(adapter->rx_ring, temp_ring,
830 adapter->num_rx_queues * sizeof(struct igb_ring));
831
832 adapter->rx_ring_count = new_rx_count;
9d5c8243 833 }
9d5c8243 834err_setup:
6d9f4fc4 835 igb_up(adapter);
68fd9910 836 vfree(temp_ring);
6d9f4fc4
AD		 837clear_reset:
838 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 839 return err;
840}
841
842/* ethtool register test data */
843struct igb_reg_test {
844 u16 reg;
2d064c06
AD		 845 u16 reg_offset;
846 u16 array_len;
847 u16 test_type;
9d5c8243
AK		 848 u32 mask;
849 u32 write;
850};
851
852/* In the hardware, registers are laid out either singly, in arrays
853 * spaced 0x100 bytes apart, or in contiguous tables. We assume
854 * most tests take place on arrays or single registers (handled
855 * as a single-element array) and special-case the tables.
856 * Table tests are always pattern tests.
857 *
858 * We also make provision for some required setup steps by specifying
859 * registers to be written without any read-back testing.
860 */
861
862#define PATTERN_TEST 1
863#define SET_READ_TEST 2
864#define WRITE_NO_TEST 3
865#define TABLE32_TEST 4
866#define TABLE64_TEST_LO 5
867#define TABLE64_TEST_HI 6
868
2d064c06
AD		 869/* 82576 reg test */
870static struct igb_reg_test reg_test_82576[] = {
871 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
872 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
873 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
874 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
875 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
876 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
877 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 878 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
879 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
880 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
881 /* Enable all RX queues before testing. */
882 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
883 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 884 /* RDH is read-only for 82576, only test RDT. */
885 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 886 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 887 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 888 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 889 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
890 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
891 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
892 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
893 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
894 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 895 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
896 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
897 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 898 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
899 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
900 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
901 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
902 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
903 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
904 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
905 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
906 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
907 { 0, 0, 0, 0 }
908};
909
910/* 82575 register test */
9d5c8243 911static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 912 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
913 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
914 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
915 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
916 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
917 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
918 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 919 /* Enable all four RX queues before testing. */
2d064c06 920 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 921 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 922 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
923 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
924 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
925 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
926 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
927 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
928 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
929 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
930 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
931 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
932 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
933 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
934 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
935 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
936 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
937 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 938 { 0, 0, 0, 0 }
939};
940
941static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
942 int reg, u32 mask, u32 write)
943{
2753f4ce 944 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 945 u32 pat, val;
946 u32 _test[] =
947 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
948 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce
AD		 949 wr32(reg, (_test[pat] & write));
950 val = rd32(reg);
9d5c8243
AK		 951 if (val != (_test[pat] & write & mask)) {
952 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
953 "failed: got 0x%08X expected 0x%08X\n",
954 reg, val, (_test[pat] & write & mask));
955 *data = reg;
956 return 1;
957 }
958 }
959 return 0;
960}
961
962static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
963 int reg, u32 mask, u32 write)
964{
2753f4ce 965 struct e1000_hw *hw = &adapter->hw;
9d5c8243 966 u32 val;
2753f4ce
AD		 967 wr32(reg, write & mask);
968 val = rd32(reg);
9d5c8243
AK		 969 if ((write & mask) != (val & mask)) {
970 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
971 " got 0x%08X expected 0x%08X\n", reg,
972 (val & mask), (write & mask));
973 *data = reg;
974 return 1;
975 }
976 return 0;
977}
978
979#define REG_PATTERN_TEST(reg, mask, write) \
980 do { \
981 if (reg_pattern_test(adapter, data, reg, mask, write)) \
982 return 1; \
983 } while (0)
984
985#define REG_SET_AND_CHECK(reg, mask, write) \
986 do { \
987 if (reg_set_and_check(adapter, data, reg, mask, write)) \
988 return 1; \
989 } while (0)
990
991static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
992{
993 struct e1000_hw *hw = &adapter->hw;
994 struct igb_reg_test *test;
995 u32 value, before, after;
996 u32 i, toggle;
997
998 toggle = 0x7FFFF3FF;
2d064c06
AD		 999
1000 switch (adapter->hw.mac.type) {
1001 case e1000_82576:
1002 test = reg_test_82576;
1003 break;
1004 default:
1005 test = reg_test_82575;
1006 break;
1007 }
9d5c8243
AK		 1008
1009 /* Because the status register is such a special case,
1010 * we handle it separately from the rest of the register
1011 * tests. Some bits are read-only, some toggle, and some
1012 * are writable on newer MACs.
1013 */
1014 before = rd32(E1000_STATUS);
1015 value = (rd32(E1000_STATUS) & toggle);
1016 wr32(E1000_STATUS, toggle);
1017 after = rd32(E1000_STATUS) & toggle;
1018 if (value != after) {
1019 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1020 "got: 0x%08X expected: 0x%08X\n", after, value);
1021 *data = 1;
1022 return 1;
1023 }
1024 /* restore previous status */
1025 wr32(E1000_STATUS, before);
1026
1027 /* Perform the remainder of the register test, looping through
1028 * the test table until we either fail or reach the null entry.
1029 */
1030 while (test->reg) {
1031 for (i = 0; i < test->array_len; i++) {
1032 switch (test->test_type) {
1033 case PATTERN_TEST:
2753f4ce
AD		 1034 REG_PATTERN_TEST(test->reg +
1035 (i * test->reg_offset),
9d5c8243
AK		 1036 test->mask,
1037 test->write);
1038 break;
1039 case SET_READ_TEST:
2753f4ce
AD		 1040 REG_SET_AND_CHECK(test->reg +
1041 (i * test->reg_offset),
9d5c8243
AK		 1042 test->mask,
1043 test->write);
1044 break;
1045 case WRITE_NO_TEST:
1046 writel(test->write,
1047 (adapter->hw.hw_addr + test->reg)
2d064c06 1048 + (i * test->reg_offset));
9d5c8243
AK		 1049 break;
1050 case TABLE32_TEST:
1051 REG_PATTERN_TEST(test->reg + (i * 4),
1052 test->mask,
1053 test->write);
1054 break;
1055 case TABLE64_TEST_LO:
1056 REG_PATTERN_TEST(test->reg + (i * 8),
1057 test->mask,
1058 test->write);
1059 break;
1060 case TABLE64_TEST_HI:
1061 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1062 test->mask,
1063 test->write);
1064 break;
1065 }
1066 }
1067 test++;
1068 }
1069
1070 *data = 0;
1071 return 0;
1072}
1073
1074static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1075{
1076 u16 temp;
1077 u16 checksum = 0;
1078 u16 i;
1079
1080 *data = 0;
1081 /* Read and add up the contents of the EEPROM */
1082 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
312c75ae 1083 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
9d5c8243
AK		 1084 < 0) {
1085 *data = 1;
1086 break;
1087 }
1088 checksum += temp;
1089 }
1090
1091 /* If Checksum is not Correct return error else test passed */
1092 if ((checksum != (u16) NVM_SUM) && !(*data))
1093 *data = 2;
1094
1095 return *data;
1096}
1097
1098static irqreturn_t igb_test_intr(int irq, void *data)
1099{
1100 struct net_device *netdev = (struct net_device *) data;
1101 struct igb_adapter *adapter = netdev_priv(netdev);
1102 struct e1000_hw *hw = &adapter->hw;
1103
1104 adapter->test_icr |= rd32(E1000_ICR);
1105
1106 return IRQ_HANDLED;
1107}
1108
1109static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1110{
1111 struct e1000_hw *hw = &adapter->hw;
1112 struct net_device *netdev = adapter->netdev;
2753f4ce 1113 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1114 u32 irq = adapter->pdev->irq;
1115
1116 *data = 0;
1117
1118 /* Hook up test interrupt handler just for this test */
2753f4ce 1119 if (adapter->msix_entries)
9d5c8243
AK		 1120 /* NOTE: we don't test MSI-X interrupts here, yet */
1121 return 0;
2753f4ce
AD		 1122
1123 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 1124 shared_int = false;
1125 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1126 *data = 1;
1127 return -1;
1128 }
1129 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1130 netdev->name, netdev)) {
1131 shared_int = false;
1132 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1133 netdev->name, netdev)) {
1134 *data = 1;
1135 return -1;
1136 }
1137 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1138 (shared_int ? "shared" : "unshared"));
9d5c8243
AK		 1139 /* Disable all the interrupts */
1140 wr32(E1000_IMC, 0xFFFFFFFF);
1141 msleep(10);
1142
2753f4ce
AD		 1143 /* Define all writable bits for ICS */
1144 switch(hw->mac.type) {
1145 case e1000_82575:
1146 ics_mask = 0x37F47EDD;
1147 break;
1148 case e1000_82576:
1149 ics_mask = 0x77D4FBFD;
1150 break;
1151 default:
1152 ics_mask = 0x7FFFFFFF;
1153 break;
1154 }
1155
9d5c8243 1156 /* Test each interrupt */
2753f4ce 1157 for (; i < 31; i++) {
9d5c8243
AK		 1158 /* Interrupt to test */
1159 mask = 1 << i;
1160
2753f4ce
AD		 1161 if (!(mask & ics_mask))
1162 continue;
1163
9d5c8243
AK		 1164 if (!shared_int) {
1165 /* Disable the interrupt to be reported in
1166 * the cause register and then force the same
1167 * interrupt and see if one gets posted. If
1168 * an interrupt was posted to the bus, the
1169 * test failed.
1170 */
1171 adapter->test_icr = 0;
2753f4ce
AD		 1172
1173 /* Flush any pending interrupts */
1174 wr32(E1000_ICR, ~0);
1175
1176 wr32(E1000_IMC, mask);
1177 wr32(E1000_ICS, mask);
9d5c8243
AK		 1178 msleep(10);
1179
1180 if (adapter->test_icr & mask) {
1181 *data = 3;
1182 break;
1183 }
1184 }
1185
1186 /* Enable the interrupt to be reported in
1187 * the cause register and then force the same
1188 * interrupt and see if one gets posted. If
1189 * an interrupt was not posted to the bus, the
1190 * test failed.
1191 */
1192 adapter->test_icr = 0;
2753f4ce
AD		 1193
1194 /* Flush any pending interrupts */
1195 wr32(E1000_ICR, ~0);
1196
9d5c8243
AK		 1197 wr32(E1000_IMS, mask);
1198 wr32(E1000_ICS, mask);
1199 msleep(10);
1200
1201 if (!(adapter->test_icr & mask)) {
1202 *data = 4;
1203 break;
1204 }
1205
1206 if (!shared_int) {
1207 /* Disable the other interrupts to be reported in
1208 * the cause register and then force the other
1209 * interrupts and see if any get posted. If
1210 * an interrupt was posted to the bus, the
1211 * test failed.
1212 */
1213 adapter->test_icr = 0;
2753f4ce
AD		 1214
1215 /* Flush any pending interrupts */
1216 wr32(E1000_ICR, ~0);
1217
1218 wr32(E1000_IMC, ~mask);
1219 wr32(E1000_ICS, ~mask);
9d5c8243
AK		 1220 msleep(10);
1221
2753f4ce 1222 if (adapter->test_icr & mask) {
9d5c8243
AK		 1223 *data = 5;
1224 break;
1225 }
1226 }
1227 }
1228
1229 /* Disable all the interrupts */
2753f4ce 1230 wr32(E1000_IMC, ~0);
9d5c8243
AK		 1231 msleep(10);
1232
1233 /* Unhook test interrupt handler */
1234 free_irq(irq, netdev);
1235
1236 return *data;
1237}
1238
1239static void igb_free_desc_rings(struct igb_adapter *adapter)
1240{
1241 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1242 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1243 struct pci_dev *pdev = adapter->pdev;
1244 int i;
1245
1246 if (tx_ring->desc && tx_ring->buffer_info) {
1247 for (i = 0; i < tx_ring->count; i++) {
1248 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1249 if (buf->dma)
1250 pci_unmap_single(pdev, buf->dma, buf->length,
1251 PCI_DMA_TODEVICE);
1252 if (buf->skb)
1253 dev_kfree_skb(buf->skb);
1254 }
1255 }
1256
1257 if (rx_ring->desc && rx_ring->buffer_info) {
1258 for (i = 0; i < rx_ring->count; i++) {
1259 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1260 if (buf->dma)
1261 pci_unmap_single(pdev, buf->dma,
1262 IGB_RXBUFFER_2048,
1263 PCI_DMA_FROMDEVICE);
1264 if (buf->skb)
1265 dev_kfree_skb(buf->skb);
1266 }
1267 }
1268
1269 if (tx_ring->desc) {
1270 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1271 tx_ring->dma);
1272 tx_ring->desc = NULL;
1273 }
1274 if (rx_ring->desc) {
1275 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1276 rx_ring->dma);
1277 rx_ring->desc = NULL;
1278 }
1279
1280 kfree(tx_ring->buffer_info);
1281 tx_ring->buffer_info = NULL;
1282 kfree(rx_ring->buffer_info);
1283 rx_ring->buffer_info = NULL;
1284
1285 return;
1286}
1287
1288static int igb_setup_desc_rings(struct igb_adapter *adapter)
1289{
1290 struct e1000_hw *hw = &adapter->hw;
1291 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1292 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1293 struct pci_dev *pdev = adapter->pdev;
85e8d004 1294 struct igb_buffer *buffer_info;
9d5c8243
AK		 1295 u32 rctl;
1296 int i, ret_val;
1297
1298 /* Setup Tx descriptor ring and Tx buffers */
1299
1300 if (!tx_ring->count)
1301 tx_ring->count = IGB_DEFAULT_TXD;
1302
1303 tx_ring->buffer_info = kcalloc(tx_ring->count,
1304 sizeof(struct igb_buffer),
1305 GFP_KERNEL);
1306 if (!tx_ring->buffer_info) {
1307 ret_val = 1;
1308 goto err_nomem;
1309 }
1310
85e8d004 1311 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1312 tx_ring->size = ALIGN(tx_ring->size, 4096);
1313 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1314 &tx_ring->dma);
1315 if (!tx_ring->desc) {
1316 ret_val = 2;
1317 goto err_nomem;
1318 }
1319 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1320
1321 wr32(E1000_TDBAL(0),
1322 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1323 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1324 wr32(E1000_TDLEN(0),
85e8d004 1325 tx_ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243
AK		 1326 wr32(E1000_TDH(0), 0);
1327 wr32(E1000_TDT(0), 0);
1328 wr32(E1000_TCTL,
1329 E1000_TCTL_PSP | E1000_TCTL_EN |
1330 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1331 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1332
1333 for (i = 0; i < tx_ring->count; i++) {
85e8d004 1334 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 1335 struct sk_buff *skb;
1336 unsigned int size = 1024;
1337
85e8d004 1338 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243
AK		 1339 skb = alloc_skb(size, GFP_KERNEL);
1340 if (!skb) {
1341 ret_val = 3;
1342 goto err_nomem;
1343 }
1344 skb_put(skb, size);
85e8d004
AD		 1345 buffer_info = &tx_ring->buffer_info[i];
1346 buffer_info->skb = skb;
1347 buffer_info->length = skb->len;
1348 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1349 PCI_DMA_TODEVICE);
1350 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1351 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1352 E1000_ADVTXD_PAYLEN_SHIFT;
1353 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1354 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1355 E1000_TXD_CMD_IFCS |
1356 E1000_TXD_CMD_RS |
1357 E1000_ADVTXD_DTYP_DATA |
1358 E1000_ADVTXD_DCMD_DEXT);
9d5c8243
AK		 1359 }
1360
1361 /* Setup Rx descriptor ring and Rx buffers */
1362
1363 if (!rx_ring->count)
1364 rx_ring->count = IGB_DEFAULT_RXD;
1365
1366 rx_ring->buffer_info = kcalloc(rx_ring->count,
1367 sizeof(struct igb_buffer),
1368 GFP_KERNEL);
1369 if (!rx_ring->buffer_info) {
1370 ret_val = 4;
1371 goto err_nomem;
1372 }
1373
85e8d004 1374 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 1375 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1376 &rx_ring->dma);
1377 if (!rx_ring->desc) {
1378 ret_val = 5;
1379 goto err_nomem;
1380 }
1381 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1382
1383 rctl = rd32(E1000_RCTL);
1384 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1385 wr32(E1000_RDBAL(0),
1386 ((u64) rx_ring->dma & 0xFFFFFFFF));
1387 wr32(E1000_RDBAH(0),
1388 ((u64) rx_ring->dma >> 32));
1389 wr32(E1000_RDLEN(0), rx_ring->size);
1390 wr32(E1000_RDH(0), 0);
1391 wr32(E1000_RDT(0), 0);
69d728ba 1392 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
cbd347ad 1393 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1394 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1395 wr32(E1000_RCTL, rctl);
85e8d004 1396 wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
9d5c8243
AK		 1397
1398 for (i = 0; i < rx_ring->count; i++) {
85e8d004 1399 union e1000_adv_rx_desc *rx_desc;
9d5c8243
AK		 1400 struct sk_buff *skb;
1401
85e8d004
AD		 1402 buffer_info = &rx_ring->buffer_info[i];
1403 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
9d5c8243
AK		 1404 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1405 GFP_KERNEL);
1406 if (!skb) {
1407 ret_val = 6;
1408 goto err_nomem;
1409 }
1410 skb_reserve(skb, NET_IP_ALIGN);
85e8d004
AD		 1411 buffer_info->skb = skb;
1412 buffer_info->dma = pci_map_single(pdev, skb->data,
1413 IGB_RXBUFFER_2048,
1414 PCI_DMA_FROMDEVICE);
1415 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 1416 memset(skb->data, 0x00, skb->len);
1417 }
1418
1419 return 0;
1420
1421err_nomem:
1422 igb_free_desc_rings(adapter);
1423 return ret_val;
1424}
1425
1426static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1427{
1428 struct e1000_hw *hw = &adapter->hw;
1429
1430 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1431 igb_write_phy_reg(hw, 29, 0x001F);
1432 igb_write_phy_reg(hw, 30, 0x8FFC);
1433 igb_write_phy_reg(hw, 29, 0x001A);
1434 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1435}
1436
1437static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1438{
1439 struct e1000_hw *hw = &adapter->hw;
1440 u32 ctrl_reg = 0;
9d5c8243
AK		 1441
1442 hw->mac.autoneg = false;
1443
1444 if (hw->phy.type == e1000_phy_m88) {
1445 /* Auto-MDI/MDIX Off */
f5f4cf08 1446 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
9d5c8243 1447 /* reset to update Auto-MDI/MDIX */
f5f4cf08 1448 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
9d5c8243 1449 /* autoneg off */
f5f4cf08 1450 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
9d5c8243
AK		 1451 }
1452
1453 ctrl_reg = rd32(E1000_CTRL);
1454
1455 /* force 1000, set loopback */
f5f4cf08 1456 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1457
1458 /* Now set up the MAC to the same speed/duplex as the PHY. */
1459 ctrl_reg = rd32(E1000_CTRL);
1460 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1461 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1462 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1463 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1464 E1000_CTRL_FD | /* Force Duplex to FULL */
1465 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1466
cdfa9f64 1467 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1468 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1469
1470 wr32(E1000_CTRL, ctrl_reg);
1471
1472 /* Disable the receiver on the PHY so when a cable is plugged in, the
1473 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1474 */
1475 if (hw->phy.type == e1000_phy_m88)
1476 igb_phy_disable_receiver(adapter);
1477
1478 udelay(500);
1479
1480 return 0;
1481}
1482
1483static int igb_set_phy_loopback(struct igb_adapter *adapter)
1484{
1485 return igb_integrated_phy_loopback(adapter);
1486}
1487
1488static int igb_setup_loopback_test(struct igb_adapter *adapter)
1489{
1490 struct e1000_hw *hw = &adapter->hw;
2d064c06 1491 u32 reg;
9d5c8243 1492
dcc3ae9a 1493 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
2d064c06
AD		 1494 reg = rd32(E1000_RCTL);
1495 reg |= E1000_RCTL_LBM_TCVR;
1496 wr32(E1000_RCTL, reg);
1497
1498 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1499
1500 reg = rd32(E1000_CTRL);
1501 reg &= ~(E1000_CTRL_RFCE |
1502 E1000_CTRL_TFCE |
1503 E1000_CTRL_LRST);
1504 reg |= E1000_CTRL_SLU |
2753f4ce 1505 E1000_CTRL_FD;
2d064c06
AD		 1506 wr32(E1000_CTRL, reg);
1507
1508 /* Unset switch control to serdes energy detect */
1509 reg = rd32(E1000_CONNSW);
1510 reg &= ~E1000_CONNSW_ENRGSRC;
1511 wr32(E1000_CONNSW, reg);
1512
1513 /* Set PCS register for forced speed */
1514 reg = rd32(E1000_PCS_LCTL);
1515 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1516 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1517 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1518 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1519 E1000_PCS_LCTL_FSD | /* Force Speed */
1520 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1521 wr32(E1000_PCS_LCTL, reg);
1522
9d5c8243
AK		 1523 return 0;
1524 } else if (hw->phy.media_type == e1000_media_type_copper) {
1525 return igb_set_phy_loopback(adapter);
1526 }
1527
1528 return 7;
1529}
1530
1531static void igb_loopback_cleanup(struct igb_adapter *adapter)
1532{
1533 struct e1000_hw *hw = &adapter->hw;
1534 u32 rctl;
1535 u16 phy_reg;
1536
1537 rctl = rd32(E1000_RCTL);
1538 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1539 wr32(E1000_RCTL, rctl);
1540
1541 hw->mac.autoneg = true;
f5f4cf08 1542 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1543 if (phy_reg & MII_CR_LOOPBACK) {
1544 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1545 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1546 igb_phy_sw_reset(hw);
1547 }
1548}
1549
1550static void igb_create_lbtest_frame(struct sk_buff *skb,
1551 unsigned int frame_size)
1552{
1553 memset(skb->data, 0xFF, frame_size);
1554 frame_size &= ~1;
1555 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1556 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1557 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1558}
1559
1560static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1561{
1562 frame_size &= ~1;
1563 if (*(skb->data + 3) == 0xFF)
1564 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1565 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1566 return 0;
1567 return 13;
1568}
1569
1570static int igb_run_loopback_test(struct igb_adapter *adapter)
1571{
1572 struct e1000_hw *hw = &adapter->hw;
1573 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1574 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1575 struct pci_dev *pdev = adapter->pdev;
1576 int i, j, k, l, lc, good_cnt;
1577 int ret_val = 0;
1578 unsigned long time;
1579
1580 wr32(E1000_RDT(0), rx_ring->count - 1);
1581
1582 /* Calculate the loop count based on the largest descriptor ring
1583 * The idea is to wrap the largest ring a number of times using 64
1584 * send/receive pairs during each loop
1585 */
1586
1587 if (rx_ring->count <= tx_ring->count)
1588 lc = ((tx_ring->count / 64) * 2) + 1;
1589 else
1590 lc = ((rx_ring->count / 64) * 2) + 1;
1591
1592 k = l = 0;
1593 for (j = 0; j <= lc; j++) { /* loop count loop */
1594 for (i = 0; i < 64; i++) { /* send the packets */
1595 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1596 1024);
1597 pci_dma_sync_single_for_device(pdev,
1598 tx_ring->buffer_info[k].dma,
1599 tx_ring->buffer_info[k].length,
1600 PCI_DMA_TODEVICE);
1601 k++;
1602 if (k == tx_ring->count)
1603 k = 0;
1604 }
1605 wr32(E1000_TDT(0), k);
1606 msleep(200);
1607 time = jiffies; /* set the start time for the receive */
1608 good_cnt = 0;
1609 do { /* receive the sent packets */
1610 pci_dma_sync_single_for_cpu(pdev,
1611 rx_ring->buffer_info[l].dma,
1612 IGB_RXBUFFER_2048,
1613 PCI_DMA_FROMDEVICE);
1614
1615 ret_val = igb_check_lbtest_frame(
1616 rx_ring->buffer_info[l].skb, 1024);
1617 if (!ret_val)
1618 good_cnt++;
1619 l++;
1620 if (l == rx_ring->count)
1621 l = 0;
1622 /* time + 20 msecs (200 msecs on 2.4) is more than
1623 * enough time to complete the receives, if it's
1624 * exceeded, break and error off
1625 */
1626 } while (good_cnt < 64 && jiffies < (time + 20));
1627 if (good_cnt != 64) {
1628 ret_val = 13; /* ret_val is the same as mis-compare */
1629 break;
1630 }
1631 if (jiffies >= (time + 20)) {
1632 ret_val = 14; /* error code for time out error */
1633 break;
1634 }
1635 } /* end loop count loop */
1636 return ret_val;
1637}
1638
1639static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1640{
1641 /* PHY loopback cannot be performed if SoL/IDER
1642 * sessions are active */
1643 if (igb_check_reset_block(&adapter->hw)) {
1644 dev_err(&adapter->pdev->dev,
1645 "Cannot do PHY loopback test "
1646 "when SoL/IDER is active.\n");
1647 *data = 0;
1648 goto out;
1649 }
1650 *data = igb_setup_desc_rings(adapter);
1651 if (*data)
1652 goto out;
1653 *data = igb_setup_loopback_test(adapter);
1654 if (*data)
1655 goto err_loopback;
1656 *data = igb_run_loopback_test(adapter);
1657 igb_loopback_cleanup(adapter);
1658
1659err_loopback:
1660 igb_free_desc_rings(adapter);
1661out:
1662 return *data;
1663}
1664
1665static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1666{
1667 struct e1000_hw *hw = &adapter->hw;
1668 *data = 0;
1669 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1670 int i = 0;
1671 hw->mac.serdes_has_link = false;
1672
1673 /* On some blade server designs, link establishment
1674 * could take as long as 2-3 minutes */
1675 do {
1676 hw->mac.ops.check_for_link(&adapter->hw);
1677 if (hw->mac.serdes_has_link)
1678 return *data;
1679 msleep(20);
1680 } while (i++ < 3750);
1681
1682 *data = 1;
1683 } else {
1684 hw->mac.ops.check_for_link(&adapter->hw);
1685 if (hw->mac.autoneg)
1686 msleep(4000);
1687
1688 if (!(rd32(E1000_STATUS) &
1689 E1000_STATUS_LU))
1690 *data = 1;
1691 }
1692 return *data;
1693}
1694
1695static void igb_diag_test(struct net_device *netdev,
1696 struct ethtool_test *eth_test, u64 *data)
1697{
1698 struct igb_adapter *adapter = netdev_priv(netdev);
1699 u16 autoneg_advertised;
1700 u8 forced_speed_duplex, autoneg;
1701 bool if_running = netif_running(netdev);
1702
1703 set_bit(__IGB_TESTING, &adapter->state);
1704 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1705 /* Offline tests */
1706
1707 /* save speed, duplex, autoneg settings */
1708 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1709 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1710 autoneg = adapter->hw.mac.autoneg;
1711
1712 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1713
1714 /* Link test performed before hardware reset so autoneg doesn't
1715 * interfere with test result */
1716 if (igb_link_test(adapter, &data[4]))
1717 eth_test->flags |= ETH_TEST_FL_FAILED;
1718
1719 if (if_running)
1720 /* indicate we're in test mode */
1721 dev_close(netdev);
1722 else
1723 igb_reset(adapter);
1724
1725 if (igb_reg_test(adapter, &data[0]))
1726 eth_test->flags |= ETH_TEST_FL_FAILED;
1727
1728 igb_reset(adapter);
1729 if (igb_eeprom_test(adapter, &data[1]))
1730 eth_test->flags |= ETH_TEST_FL_FAILED;
1731
1732 igb_reset(adapter);
1733 if (igb_intr_test(adapter, &data[2]))
1734 eth_test->flags |= ETH_TEST_FL_FAILED;
1735
1736 igb_reset(adapter);
1737 if (igb_loopback_test(adapter, &data[3]))
1738 eth_test->flags |= ETH_TEST_FL_FAILED;
1739
1740 /* restore speed, duplex, autoneg settings */
1741 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1742 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1743 adapter->hw.mac.autoneg = autoneg;
1744
1745 /* force this routine to wait until autoneg complete/timeout */
1746 adapter->hw.phy.autoneg_wait_to_complete = true;
1747 igb_reset(adapter);
1748 adapter->hw.phy.autoneg_wait_to_complete = false;
1749
1750 clear_bit(__IGB_TESTING, &adapter->state);
1751 if (if_running)
1752 dev_open(netdev);
1753 } else {
1754 dev_info(&adapter->pdev->dev, "online testing starting\n");
1755 /* Online tests */
1756 if (igb_link_test(adapter, &data[4]))
1757 eth_test->flags |= ETH_TEST_FL_FAILED;
1758
1759 /* Online tests aren't run; pass by default */
1760 data[0] = 0;
1761 data[1] = 0;
1762 data[2] = 0;
1763 data[3] = 0;
1764
1765 clear_bit(__IGB_TESTING, &adapter->state);
1766 }
1767 msleep_interruptible(4 * 1000);
1768}
1769
1770static int igb_wol_exclusion(struct igb_adapter *adapter,
1771 struct ethtool_wolinfo *wol)
1772{
1773 struct e1000_hw *hw = &adapter->hw;
1774 int retval = 1; /* fail by default */
1775
1776 switch (hw->device_id) {
1777 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1778 /* WoL not supported */
1779 wol->supported = 0;
1780 break;
1781 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1782 case E1000_DEV_ID_82576_FIBER:
1783 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1784 /* Wake events not supported on port B */
1785 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1786 wol->supported = 0;
1787 break;
1788 }
7dfc16fa
AD		 1789 /* return success for non excluded adapter ports */
1790 retval = 0;
1791 break;
c8ea5ea9
AD		 1792 case E1000_DEV_ID_82576_QUAD_COPPER:
1793 /* quad port adapters only support WoL on port A */
1794 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1795 wol->supported = 0;
1796 break;
1797 }
1798 /* return success for non excluded adapter ports */
1799 retval = 0;
1800 break;
9d5c8243
AK		 1801 default:
1802 /* dual port cards only support WoL on port A from now on
1803 * unless it was enabled in the eeprom for port B
1804 * so exclude FUNC_1 ports from having WoL enabled */
1805 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1806 !adapter->eeprom_wol) {
1807 wol->supported = 0;
1808 break;
1809 }
1810
1811 retval = 0;
1812 }
1813
1814 return retval;
1815}
1816
1817static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1818{
1819 struct igb_adapter *adapter = netdev_priv(netdev);
1820
1821 wol->supported = WAKE_UCAST | WAKE_MCAST |
1822 WAKE_BCAST | WAKE_MAGIC;
1823 wol->wolopts = 0;
1824
1825 /* this function will set ->supported = 0 and return 1 if wol is not
1826 * supported by this hardware */
e1b86d84
RW		 1827 if (igb_wol_exclusion(adapter, wol) ||
1828 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1829 return;
1830
1831 /* apply any specific unsupported masks here */
1832 switch (adapter->hw.device_id) {
1833 default:
1834 break;
1835 }
1836
1837 if (adapter->wol & E1000_WUFC_EX)
1838 wol->wolopts |= WAKE_UCAST;
1839 if (adapter->wol & E1000_WUFC_MC)
1840 wol->wolopts |= WAKE_MCAST;
1841 if (adapter->wol & E1000_WUFC_BC)
1842 wol->wolopts |= WAKE_BCAST;
1843 if (adapter->wol & E1000_WUFC_MAG)
1844 wol->wolopts |= WAKE_MAGIC;
1845
1846 return;
1847}
1848
1849static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1850{
1851 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 1852
1853 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1854 return -EOPNOTSUPP;
1855
e1b86d84
RW		 1856 if (igb_wol_exclusion(adapter, wol) ||
1857 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1858 return wol->wolopts ? -EOPNOTSUPP : 0;
1859
9d5c8243
AK		 1860 /* these settings will always override what we currently have */
1861 adapter->wol = 0;
1862
1863 if (wol->wolopts & WAKE_UCAST)
1864 adapter->wol |= E1000_WUFC_EX;
1865 if (wol->wolopts & WAKE_MCAST)
1866 adapter->wol |= E1000_WUFC_MC;
1867 if (wol->wolopts & WAKE_BCAST)
1868 adapter->wol |= E1000_WUFC_BC;
1869 if (wol->wolopts & WAKE_MAGIC)
1870 adapter->wol |= E1000_WUFC_MAG;
1871
e1b86d84
RW		 1872 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1873
9d5c8243
AK		 1874 return 0;
1875}
1876
9d5c8243
AK		 1877/* bit defines for adapter->led_status */
1878#define IGB_LED_ON 0
1879
1880static int igb_phys_id(struct net_device *netdev, u32 data)
1881{
1882 struct igb_adapter *adapter = netdev_priv(netdev);
1883 struct e1000_hw *hw = &adapter->hw;
1884
1885 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1886 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1887
1888 igb_blink_led(hw);
1889 msleep_interruptible(data * 1000);
1890
1891 igb_led_off(hw);
1892 clear_bit(IGB_LED_ON, &adapter->led_status);
1893 igb_cleanup_led(hw);
1894
1895 return 0;
1896}
1897
1898static int igb_set_coalesce(struct net_device *netdev,
1899 struct ethtool_coalesce *ec)
1900{
1901 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1
AD		 1902 struct e1000_hw *hw = &adapter->hw;
1903 int i;
9d5c8243
AK		 1904
1905 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1906 ((ec->rx_coalesce_usecs > 3) &&
1907 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1908 (ec->rx_coalesce_usecs == 2))
1909 return -EINVAL;
1910
1911 /* convert to rate of irq's per second */
6eb5a7f1 1912 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
9d5c8243 1913 adapter->itr_setting = ec->rx_coalesce_usecs;
6eb5a7f1
AD		 1914 adapter->itr = IGB_START_ITR;
1915 } else {
1916 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1917 adapter->itr = adapter->itr_setting;
1918 }
9d5c8243 1919
6eb5a7f1
AD		 1920 for (i = 0; i < adapter->num_rx_queues; i++)
1921 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
9d5c8243
AK		 1922
1923 return 0;
1924}
1925
1926static int igb_get_coalesce(struct net_device *netdev,
1927 struct ethtool_coalesce *ec)
1928{
1929 struct igb_adapter *adapter = netdev_priv(netdev);
1930
1931 if (adapter->itr_setting <= 3)
1932 ec->rx_coalesce_usecs = adapter->itr_setting;
1933 else
6eb5a7f1 1934 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
9d5c8243
AK		 1935
1936 return 0;
1937}
1938
1939
1940static int igb_nway_reset(struct net_device *netdev)
1941{
1942 struct igb_adapter *adapter = netdev_priv(netdev);
1943 if (netif_running(netdev))
1944 igb_reinit_locked(adapter);
1945 return 0;
1946}
1947
1948static int igb_get_sset_count(struct net_device *netdev, int sset)
1949{
1950 switch (sset) {
1951 case ETH_SS_STATS:
1952 return IGB_STATS_LEN;
1953 case ETH_SS_TEST:
1954 return IGB_TEST_LEN;
1955 default:
1956 return -ENOTSUPP;
1957 }
1958}
1959
1960static void igb_get_ethtool_stats(struct net_device *netdev,
1961 struct ethtool_stats *stats, u64 *data)
1962{
1963 struct igb_adapter *adapter = netdev_priv(netdev);
1964 u64 *queue_stat;
8c0ab70a
JDB		 1965 int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1966 int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
9d5c8243
AK		 1967 int j;
1968 int i;
1969
1970 igb_update_stats(adapter);
1971 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1972 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1973 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1974 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1975 }
e21ed353
AD		 1976 for (j = 0; j < adapter->num_tx_queues; j++) {
1977 int k;
1978 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
8c0ab70a 1979 for (k = 0; k < stat_count_tx; k++)
e21ed353
AD		 1980 data[i + k] = queue_stat[k];
1981 i += k;
1982 }
9d5c8243
AK		 1983 for (j = 0; j < adapter->num_rx_queues; j++) {
1984 int k;
1985 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
8c0ab70a 1986 for (k = 0; k < stat_count_rx; k++)
9d5c8243
AK		 1987 data[i + k] = queue_stat[k];
1988 i += k;
1989 }
1990}
1991
1992static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1993{
1994 struct igb_adapter *adapter = netdev_priv(netdev);
1995 u8 *p = data;
1996 int i;
1997
1998 switch (stringset) {
1999 case ETH_SS_TEST:
2000 memcpy(data, *igb_gstrings_test,
2001 IGB_TEST_LEN*ETH_GSTRING_LEN);
2002 break;
2003 case ETH_SS_STATS:
2004 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2005 memcpy(p, igb_gstrings_stats[i].stat_string,
2006 ETH_GSTRING_LEN);
2007 p += ETH_GSTRING_LEN;
2008 }
2009 for (i = 0; i < adapter->num_tx_queues; i++) {
2010 sprintf(p, "tx_queue_%u_packets", i);
2011 p += ETH_GSTRING_LEN;
2012 sprintf(p, "tx_queue_%u_bytes", i);
2013 p += ETH_GSTRING_LEN;
2014 }
2015 for (i = 0; i < adapter->num_rx_queues; i++) {
2016 sprintf(p, "rx_queue_%u_packets", i);
2017 p += ETH_GSTRING_LEN;
2018 sprintf(p, "rx_queue_%u_bytes", i);
2019 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2020 sprintf(p, "rx_queue_%u_drops", i);
2021 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2022 }
2023/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2024 break;
2025 }
2026}
2027
0fc0b732 2028static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2029 .get_settings = igb_get_settings,
2030 .set_settings = igb_set_settings,
2031 .get_drvinfo = igb_get_drvinfo,
2032 .get_regs_len = igb_get_regs_len,
2033 .get_regs = igb_get_regs,
2034 .get_wol = igb_get_wol,
2035 .set_wol = igb_set_wol,
2036 .get_msglevel = igb_get_msglevel,
2037 .set_msglevel = igb_set_msglevel,
2038 .nway_reset = igb_nway_reset,
2039 .get_link = ethtool_op_get_link,
2040 .get_eeprom_len = igb_get_eeprom_len,
2041 .get_eeprom = igb_get_eeprom,
2042 .set_eeprom = igb_set_eeprom,
2043 .get_ringparam = igb_get_ringparam,
2044 .set_ringparam = igb_set_ringparam,
2045 .get_pauseparam = igb_get_pauseparam,
2046 .set_pauseparam = igb_set_pauseparam,
2047 .get_rx_csum = igb_get_rx_csum,
2048 .set_rx_csum = igb_set_rx_csum,
2049 .get_tx_csum = igb_get_tx_csum,
2050 .set_tx_csum = igb_set_tx_csum,
2051 .get_sg = ethtool_op_get_sg,
2052 .set_sg = ethtool_op_set_sg,
2053 .get_tso = ethtool_op_get_tso,
2054 .set_tso = igb_set_tso,
2055 .self_test = igb_diag_test,
2056 .get_strings = igb_get_strings,
2057 .phys_id = igb_phys_id,
2058 .get_sset_count = igb_get_sset_count,
2059 .get_ethtool_stats = igb_get_ethtool_stats,
2060 .get_coalesce = igb_get_coalesce,
2061 .set_coalesce = igb_set_coalesce,
2062};
2063
2064void igb_set_ethtool_ops(struct net_device *netdev)
2065{
2066 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2067}
Linux kernel - Deliverables
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