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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/pagemap.h> | |
33 | #include <linux/netdevice.h> | |
9d5c8243 AK |
34 | #include <linux/ipv6.h> |
35 | #include <net/checksum.h> | |
36 | #include <net/ip6_checksum.h> | |
c6cb090b | 37 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
38 | #include <linux/mii.h> |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/if_vlan.h> | |
41 | #include <linux/pci.h> | |
c54106bb | 42 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
43 | #include <linux/delay.h> |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/if_ether.h> | |
40a914fa | 46 | #include <linux/aer.h> |
421e02f0 | 47 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
48 | #include <linux/dca.h> |
49 | #endif | |
9d5c8243 AK |
50 | #include "igb.h" |
51 | ||
86d5d38f | 52 | #define DRV_VERSION "1.3.16-k2" |
9d5c8243 AK |
53 | char igb_driver_name[] = "igb"; |
54 | char igb_driver_version[] = DRV_VERSION; | |
55 | static const char igb_driver_string[] = | |
56 | "Intel(R) Gigabit Ethernet Network Driver"; | |
86d5d38f | 57 | static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation."; |
9d5c8243 | 58 | |
9d5c8243 AK |
59 | static const struct e1000_info *igb_info_tbl[] = { |
60 | [board_82575] = &e1000_82575_info, | |
61 | }; | |
62 | ||
63 | static struct pci_device_id igb_pci_tbl[] = { | |
2d064c06 AD |
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, | |
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
9d5c8243 AK |
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
70 | /* required last entry */ | |
71 | {0, } | |
72 | }; | |
73 | ||
74 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
75 | ||
76 | void igb_reset(struct igb_adapter *); | |
77 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
78 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
79 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
80 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
9d5c8243 AK |
81 | void igb_update_stats(struct igb_adapter *); |
82 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | |
83 | static void __devexit igb_remove(struct pci_dev *pdev); | |
84 | static int igb_sw_init(struct igb_adapter *); | |
85 | static int igb_open(struct net_device *); | |
86 | static int igb_close(struct net_device *); | |
87 | static void igb_configure_tx(struct igb_adapter *); | |
88 | static void igb_configure_rx(struct igb_adapter *); | |
89 | static void igb_setup_rctl(struct igb_adapter *); | |
90 | static void igb_clean_all_tx_rings(struct igb_adapter *); | |
91 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
92 | static void igb_clean_tx_ring(struct igb_ring *); |
93 | static void igb_clean_rx_ring(struct igb_ring *); | |
9d5c8243 AK |
94 | static void igb_set_multi(struct net_device *); |
95 | static void igb_update_phy_info(unsigned long); | |
96 | static void igb_watchdog(unsigned long); | |
97 | static void igb_watchdog_task(struct work_struct *); | |
98 | static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *, | |
99 | struct igb_ring *); | |
100 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); | |
101 | static struct net_device_stats *igb_get_stats(struct net_device *); | |
102 | static int igb_change_mtu(struct net_device *, int); | |
103 | static int igb_set_mac(struct net_device *, void *); | |
104 | static irqreturn_t igb_intr(int irq, void *); | |
105 | static irqreturn_t igb_intr_msi(int irq, void *); | |
106 | static irqreturn_t igb_msix_other(int irq, void *); | |
107 | static irqreturn_t igb_msix_rx(int irq, void *); | |
108 | static irqreturn_t igb_msix_tx(int irq, void *); | |
421e02f0 | 109 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
110 | static void igb_update_rx_dca(struct igb_ring *); |
111 | static void igb_update_tx_dca(struct igb_ring *); | |
112 | static void igb_setup_dca(struct igb_adapter *); | |
421e02f0 | 113 | #endif /* CONFIG_IGB_DCA */ |
3b644cf6 | 114 | static bool igb_clean_tx_irq(struct igb_ring *); |
661086df | 115 | static int igb_poll(struct napi_struct *, int); |
3b644cf6 MW |
116 | static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int); |
117 | static void igb_alloc_rx_buffers_adv(struct igb_ring *, int); | |
9d5c8243 AK |
118 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
119 | static void igb_tx_timeout(struct net_device *); | |
120 | static void igb_reset_task(struct work_struct *); | |
121 | static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |
122 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | |
123 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
124 | static void igb_restore_vlan(struct igb_adapter *); | |
125 | ||
126 | static int igb_suspend(struct pci_dev *, pm_message_t); | |
127 | #ifdef CONFIG_PM | |
128 | static int igb_resume(struct pci_dev *); | |
129 | #endif | |
130 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 131 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
132 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
133 | static struct notifier_block dca_notifier = { | |
134 | .notifier_call = igb_notify_dca, | |
135 | .next = NULL, | |
136 | .priority = 0 | |
137 | }; | |
138 | #endif | |
9d5c8243 AK |
139 | |
140 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
141 | /* for netdump / net console */ | |
142 | static void igb_netpoll(struct net_device *); | |
143 | #endif | |
144 | ||
145 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, | |
146 | pci_channel_state_t); | |
147 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
148 | static void igb_io_resume(struct pci_dev *); | |
149 | ||
150 | static struct pci_error_handlers igb_err_handler = { | |
151 | .error_detected = igb_io_error_detected, | |
152 | .slot_reset = igb_io_slot_reset, | |
153 | .resume = igb_io_resume, | |
154 | }; | |
155 | ||
156 | ||
157 | static struct pci_driver igb_driver = { | |
158 | .name = igb_driver_name, | |
159 | .id_table = igb_pci_tbl, | |
160 | .probe = igb_probe, | |
161 | .remove = __devexit_p(igb_remove), | |
162 | #ifdef CONFIG_PM | |
163 | /* Power Managment Hooks */ | |
164 | .suspend = igb_suspend, | |
165 | .resume = igb_resume, | |
166 | #endif | |
167 | .shutdown = igb_shutdown, | |
168 | .err_handler = &igb_err_handler | |
169 | }; | |
170 | ||
7dfc16fa AD |
171 | static int global_quad_port_a; /* global quad port a indication */ |
172 | ||
9d5c8243 AK |
173 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); |
174 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
175 | MODULE_LICENSE("GPL"); | |
176 | MODULE_VERSION(DRV_VERSION); | |
177 | ||
38c845c7 PO |
178 | /** |
179 | * Scale the NIC clock cycle by a large factor so that | |
180 | * relatively small clock corrections can be added or | |
181 | * substracted at each clock tick. The drawbacks of a | |
182 | * large factor are a) that the clock register overflows | |
183 | * more quickly (not such a big deal) and b) that the | |
184 | * increment per tick has to fit into 24 bits. | |
185 | * | |
186 | * Note that | |
187 | * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * | |
188 | * IGB_TSYNC_SCALE | |
189 | * TIMINCA += TIMINCA * adjustment [ppm] / 1e9 | |
190 | * | |
191 | * The base scale factor is intentionally a power of two | |
192 | * so that the division in %struct timecounter can be done with | |
193 | * a shift. | |
194 | */ | |
195 | #define IGB_TSYNC_SHIFT (19) | |
196 | #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT) | |
197 | ||
198 | /** | |
199 | * The duration of one clock cycle of the NIC. | |
200 | * | |
201 | * @todo This hard-coded value is part of the specification and might change | |
202 | * in future hardware revisions. Add revision check. | |
203 | */ | |
204 | #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16 | |
205 | ||
206 | #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24) | |
207 | # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA | |
208 | #endif | |
209 | ||
210 | /** | |
211 | * igb_read_clock - read raw cycle counter (to be used by time counter) | |
212 | */ | |
213 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | |
214 | { | |
215 | struct igb_adapter *adapter = | |
216 | container_of(tc, struct igb_adapter, cycles); | |
217 | struct e1000_hw *hw = &adapter->hw; | |
218 | u64 stamp; | |
219 | ||
220 | stamp = rd32(E1000_SYSTIML); | |
221 | stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL; | |
222 | ||
223 | return stamp; | |
224 | } | |
225 | ||
9d5c8243 AK |
226 | #ifdef DEBUG |
227 | /** | |
228 | * igb_get_hw_dev_name - return device name string | |
229 | * used by hardware layer to print debugging information | |
230 | **/ | |
231 | char *igb_get_hw_dev_name(struct e1000_hw *hw) | |
232 | { | |
233 | struct igb_adapter *adapter = hw->back; | |
234 | return adapter->netdev->name; | |
235 | } | |
38c845c7 PO |
236 | |
237 | /** | |
238 | * igb_get_time_str - format current NIC and system time as string | |
239 | */ | |
240 | static char *igb_get_time_str(struct igb_adapter *adapter, | |
241 | char buffer[160]) | |
242 | { | |
243 | cycle_t hw = adapter->cycles.read(&adapter->cycles); | |
244 | struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock)); | |
245 | struct timespec sys; | |
246 | struct timespec delta; | |
247 | getnstimeofday(&sys); | |
248 | ||
249 | delta = timespec_sub(nic, sys); | |
250 | ||
251 | sprintf(buffer, | |
33af6bcc PO |
252 | "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns", |
253 | hw, | |
38c845c7 PO |
254 | (long)nic.tv_sec, nic.tv_nsec, |
255 | (long)sys.tv_sec, sys.tv_nsec, | |
256 | (long)delta.tv_sec, delta.tv_nsec); | |
257 | ||
258 | return buffer; | |
259 | } | |
9d5c8243 AK |
260 | #endif |
261 | ||
262 | /** | |
263 | * igb_init_module - Driver Registration Routine | |
264 | * | |
265 | * igb_init_module is the first routine called when the driver is | |
266 | * loaded. All it does is register with the PCI subsystem. | |
267 | **/ | |
268 | static int __init igb_init_module(void) | |
269 | { | |
270 | int ret; | |
271 | printk(KERN_INFO "%s - version %s\n", | |
272 | igb_driver_string, igb_driver_version); | |
273 | ||
274 | printk(KERN_INFO "%s\n", igb_copyright); | |
275 | ||
7dfc16fa AD |
276 | global_quad_port_a = 0; |
277 | ||
421e02f0 | 278 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
279 | dca_register_notify(&dca_notifier); |
280 | #endif | |
bbd98fe4 AD |
281 | |
282 | ret = pci_register_driver(&igb_driver); | |
9d5c8243 AK |
283 | return ret; |
284 | } | |
285 | ||
286 | module_init(igb_init_module); | |
287 | ||
288 | /** | |
289 | * igb_exit_module - Driver Exit Cleanup Routine | |
290 | * | |
291 | * igb_exit_module is called just before the driver is removed | |
292 | * from memory. | |
293 | **/ | |
294 | static void __exit igb_exit_module(void) | |
295 | { | |
421e02f0 | 296 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
297 | dca_unregister_notify(&dca_notifier); |
298 | #endif | |
9d5c8243 AK |
299 | pci_unregister_driver(&igb_driver); |
300 | } | |
301 | ||
302 | module_exit(igb_exit_module); | |
303 | ||
26bc19ec AD |
304 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
305 | /** | |
306 | * igb_cache_ring_register - Descriptor ring to register mapping | |
307 | * @adapter: board private structure to initialize | |
308 | * | |
309 | * Once we know the feature-set enabled for the device, we'll cache | |
310 | * the register offset the descriptor ring is assigned to. | |
311 | **/ | |
312 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
313 | { | |
314 | int i; | |
1bfaf07b | 315 | unsigned int rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
316 | |
317 | switch (adapter->hw.mac.type) { | |
318 | case e1000_82576: | |
319 | /* The queues are allocated for virtualization such that VF 0 | |
320 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
321 | * In order to avoid collision we start at the first free queue | |
322 | * and continue consuming queues in the same sequence | |
323 | */ | |
324 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1bfaf07b AD |
325 | adapter->rx_ring[i].reg_idx = rbase_offset + |
326 | Q_IDX_82576(i); | |
26bc19ec | 327 | for (i = 0; i < adapter->num_tx_queues; i++) |
1bfaf07b AD |
328 | adapter->tx_ring[i].reg_idx = rbase_offset + |
329 | Q_IDX_82576(i); | |
26bc19ec AD |
330 | break; |
331 | case e1000_82575: | |
332 | default: | |
333 | for (i = 0; i < adapter->num_rx_queues; i++) | |
334 | adapter->rx_ring[i].reg_idx = i; | |
335 | for (i = 0; i < adapter->num_tx_queues; i++) | |
336 | adapter->tx_ring[i].reg_idx = i; | |
337 | break; | |
338 | } | |
339 | } | |
340 | ||
9d5c8243 AK |
341 | /** |
342 | * igb_alloc_queues - Allocate memory for all rings | |
343 | * @adapter: board private structure to initialize | |
344 | * | |
345 | * We allocate one ring per queue at run-time since we don't know the | |
346 | * number of queues at compile-time. | |
347 | **/ | |
348 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
349 | { | |
350 | int i; | |
351 | ||
352 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
353 | sizeof(struct igb_ring), GFP_KERNEL); | |
354 | if (!adapter->tx_ring) | |
355 | return -ENOMEM; | |
356 | ||
357 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
358 | sizeof(struct igb_ring), GFP_KERNEL); | |
359 | if (!adapter->rx_ring) { | |
360 | kfree(adapter->tx_ring); | |
361 | return -ENOMEM; | |
362 | } | |
363 | ||
6eb5a7f1 AD |
364 | adapter->rx_ring->buddy = adapter->tx_ring; |
365 | ||
661086df PWJ |
366 | for (i = 0; i < adapter->num_tx_queues; i++) { |
367 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
68fd9910 | 368 | ring->count = adapter->tx_ring_count; |
661086df PWJ |
369 | ring->adapter = adapter; |
370 | ring->queue_index = i; | |
371 | } | |
9d5c8243 AK |
372 | for (i = 0; i < adapter->num_rx_queues; i++) { |
373 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
68fd9910 | 374 | ring->count = adapter->rx_ring_count; |
9d5c8243 | 375 | ring->adapter = adapter; |
844290e5 | 376 | ring->queue_index = i; |
9d5c8243 AK |
377 | ring->itr_register = E1000_ITR; |
378 | ||
844290e5 | 379 | /* set a default napi handler for each rx_ring */ |
661086df | 380 | netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64); |
9d5c8243 | 381 | } |
26bc19ec AD |
382 | |
383 | igb_cache_ring_register(adapter); | |
9d5c8243 AK |
384 | return 0; |
385 | } | |
386 | ||
a88f10ec AD |
387 | static void igb_free_queues(struct igb_adapter *adapter) |
388 | { | |
389 | int i; | |
390 | ||
391 | for (i = 0; i < adapter->num_rx_queues; i++) | |
392 | netif_napi_del(&adapter->rx_ring[i].napi); | |
393 | ||
394 | kfree(adapter->tx_ring); | |
395 | kfree(adapter->rx_ring); | |
396 | } | |
397 | ||
9d5c8243 AK |
398 | #define IGB_N0_QUEUE -1 |
399 | static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |
400 | int tx_queue, int msix_vector) | |
401 | { | |
402 | u32 msixbm = 0; | |
403 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
404 | u32 ivar, index; |
405 | ||
406 | switch (hw->mac.type) { | |
407 | case e1000_82575: | |
9d5c8243 AK |
408 | /* The 82575 assigns vectors using a bitmask, which matches the |
409 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
410 | or more queues to a vector, we write the appropriate bits | |
411 | into the MSIXBM register for that vector. */ | |
412 | if (rx_queue > IGB_N0_QUEUE) { | |
413 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; | |
414 | adapter->rx_ring[rx_queue].eims_value = msixbm; | |
415 | } | |
416 | if (tx_queue > IGB_N0_QUEUE) { | |
417 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; | |
418 | adapter->tx_ring[tx_queue].eims_value = | |
419 | E1000_EICR_TX_QUEUE0 << tx_queue; | |
420 | } | |
421 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | |
2d064c06 AD |
422 | break; |
423 | case e1000_82576: | |
26bc19ec | 424 | /* 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
425 | Each queue has a single entry in the table to which we write |
426 | a vector number along with a "valid" bit. Sadly, the layout | |
427 | of the table is somewhat counterintuitive. */ | |
428 | if (rx_queue > IGB_N0_QUEUE) { | |
1bfaf07b | 429 | index = (rx_queue >> 1) + adapter->vfs_allocated_count; |
2d064c06 | 430 | ivar = array_rd32(E1000_IVAR0, index); |
26bc19ec | 431 | if (rx_queue & 0x1) { |
2d064c06 AD |
432 | /* vector goes into third byte of register */ |
433 | ivar = ivar & 0xFF00FFFF; | |
434 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
26bc19ec AD |
435 | } else { |
436 | /* vector goes into low byte of register */ | |
437 | ivar = ivar & 0xFFFFFF00; | |
438 | ivar |= msix_vector | E1000_IVAR_VALID; | |
2d064c06 AD |
439 | } |
440 | adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; | |
441 | array_wr32(E1000_IVAR0, index, ivar); | |
442 | } | |
443 | if (tx_queue > IGB_N0_QUEUE) { | |
1bfaf07b | 444 | index = (tx_queue >> 1) + adapter->vfs_allocated_count; |
2d064c06 | 445 | ivar = array_rd32(E1000_IVAR0, index); |
26bc19ec | 446 | if (tx_queue & 0x1) { |
2d064c06 AD |
447 | /* vector goes into high byte of register */ |
448 | ivar = ivar & 0x00FFFFFF; | |
449 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
26bc19ec AD |
450 | } else { |
451 | /* vector goes into second byte of register */ | |
452 | ivar = ivar & 0xFFFF00FF; | |
453 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
2d064c06 AD |
454 | } |
455 | adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; | |
456 | array_wr32(E1000_IVAR0, index, ivar); | |
457 | } | |
458 | break; | |
459 | default: | |
460 | BUG(); | |
461 | break; | |
462 | } | |
9d5c8243 AK |
463 | } |
464 | ||
465 | /** | |
466 | * igb_configure_msix - Configure MSI-X hardware | |
467 | * | |
468 | * igb_configure_msix sets up the hardware to properly | |
469 | * generate MSI-X interrupts. | |
470 | **/ | |
471 | static void igb_configure_msix(struct igb_adapter *adapter) | |
472 | { | |
473 | u32 tmp; | |
474 | int i, vector = 0; | |
475 | struct e1000_hw *hw = &adapter->hw; | |
476 | ||
477 | adapter->eims_enable_mask = 0; | |
2d064c06 AD |
478 | if (hw->mac.type == e1000_82576) |
479 | /* Turn on MSI-X capability first, or our settings | |
480 | * won't stick. And it will take days to debug. */ | |
481 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
eebbbdba | 482 | E1000_GPIE_PBA | E1000_GPIE_EIAME | |
2d064c06 | 483 | E1000_GPIE_NSICR); |
9d5c8243 AK |
484 | |
485 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
486 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
487 | igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); | |
488 | adapter->eims_enable_mask |= tx_ring->eims_value; | |
489 | if (tx_ring->itr_val) | |
6eb5a7f1 | 490 | writel(tx_ring->itr_val, |
9d5c8243 AK |
491 | hw->hw_addr + tx_ring->itr_register); |
492 | else | |
493 | writel(1, hw->hw_addr + tx_ring->itr_register); | |
494 | } | |
495 | ||
496 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
497 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
25ac3c24 | 498 | rx_ring->buddy = NULL; |
9d5c8243 AK |
499 | igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); |
500 | adapter->eims_enable_mask |= rx_ring->eims_value; | |
501 | if (rx_ring->itr_val) | |
6eb5a7f1 | 502 | writel(rx_ring->itr_val, |
9d5c8243 AK |
503 | hw->hw_addr + rx_ring->itr_register); |
504 | else | |
505 | writel(1, hw->hw_addr + rx_ring->itr_register); | |
506 | } | |
507 | ||
508 | ||
509 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
510 | switch (hw->mac.type) { |
511 | case e1000_82575: | |
9d5c8243 AK |
512 | array_wr32(E1000_MSIXBM(0), vector++, |
513 | E1000_EIMS_OTHER); | |
514 | ||
9d5c8243 AK |
515 | tmp = rd32(E1000_CTRL_EXT); |
516 | /* enable MSI-X PBA support*/ | |
517 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
518 | ||
519 | /* Auto-Mask interrupts upon ICR read. */ | |
520 | tmp |= E1000_CTRL_EXT_EIAME; | |
521 | tmp |= E1000_CTRL_EXT_IRCA; | |
522 | ||
523 | wr32(E1000_CTRL_EXT, tmp); | |
524 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; | |
844290e5 | 525 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 526 | |
2d064c06 AD |
527 | break; |
528 | ||
529 | case e1000_82576: | |
530 | tmp = (vector++ | E1000_IVAR_VALID) << 8; | |
531 | wr32(E1000_IVAR_MISC, tmp); | |
532 | ||
533 | adapter->eims_enable_mask = (1 << (vector)) - 1; | |
534 | adapter->eims_other = 1 << (vector - 1); | |
535 | break; | |
536 | default: | |
537 | /* do nothing, since nothing else supports MSI-X */ | |
538 | break; | |
539 | } /* switch (hw->mac.type) */ | |
9d5c8243 AK |
540 | wrfl(); |
541 | } | |
542 | ||
543 | /** | |
544 | * igb_request_msix - Initialize MSI-X interrupts | |
545 | * | |
546 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
547 | * kernel. | |
548 | **/ | |
549 | static int igb_request_msix(struct igb_adapter *adapter) | |
550 | { | |
551 | struct net_device *netdev = adapter->netdev; | |
552 | int i, err = 0, vector = 0; | |
553 | ||
554 | vector = 0; | |
555 | ||
556 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
557 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
cb7b48f6 | 558 | sprintf(ring->name, "%s-tx-%d", netdev->name, i); |
9d5c8243 AK |
559 | err = request_irq(adapter->msix_entries[vector].vector, |
560 | &igb_msix_tx, 0, ring->name, | |
561 | &(adapter->tx_ring[i])); | |
562 | if (err) | |
563 | goto out; | |
564 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
6eb5a7f1 | 565 | ring->itr_val = 976; /* ~4000 ints/sec */ |
9d5c8243 AK |
566 | vector++; |
567 | } | |
568 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
569 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
570 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
cb7b48f6 | 571 | sprintf(ring->name, "%s-rx-%d", netdev->name, i); |
9d5c8243 AK |
572 | else |
573 | memcpy(ring->name, netdev->name, IFNAMSIZ); | |
574 | err = request_irq(adapter->msix_entries[vector].vector, | |
575 | &igb_msix_rx, 0, ring->name, | |
576 | &(adapter->rx_ring[i])); | |
577 | if (err) | |
578 | goto out; | |
579 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
580 | ring->itr_val = adapter->itr; | |
844290e5 PW |
581 | /* overwrite the poll routine for MSIX, we've already done |
582 | * netif_napi_add */ | |
583 | ring->napi.poll = &igb_clean_rx_ring_msix; | |
9d5c8243 AK |
584 | vector++; |
585 | } | |
586 | ||
587 | err = request_irq(adapter->msix_entries[vector].vector, | |
588 | &igb_msix_other, 0, netdev->name, netdev); | |
589 | if (err) | |
590 | goto out; | |
591 | ||
9d5c8243 AK |
592 | igb_configure_msix(adapter); |
593 | return 0; | |
594 | out: | |
595 | return err; | |
596 | } | |
597 | ||
598 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
599 | { | |
600 | if (adapter->msix_entries) { | |
601 | pci_disable_msix(adapter->pdev); | |
602 | kfree(adapter->msix_entries); | |
603 | adapter->msix_entries = NULL; | |
7dfc16fa | 604 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) |
9d5c8243 AK |
605 | pci_disable_msi(adapter->pdev); |
606 | return; | |
607 | } | |
608 | ||
609 | ||
610 | /** | |
611 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
612 | * | |
613 | * Attempt to configure interrupts using the best available | |
614 | * capabilities of the hardware and kernel. | |
615 | **/ | |
616 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |
617 | { | |
618 | int err; | |
619 | int numvecs, i; | |
620 | ||
83b7180d AD |
621 | /* Number of supported queues. */ |
622 | /* Having more queues than CPUs doesn't make sense. */ | |
623 | adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); | |
624 | adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus()); | |
625 | ||
9d5c8243 AK |
626 | numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; |
627 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), | |
628 | GFP_KERNEL); | |
629 | if (!adapter->msix_entries) | |
630 | goto msi_only; | |
631 | ||
632 | for (i = 0; i < numvecs; i++) | |
633 | adapter->msix_entries[i].entry = i; | |
634 | ||
635 | err = pci_enable_msix(adapter->pdev, | |
636 | adapter->msix_entries, | |
637 | numvecs); | |
638 | if (err == 0) | |
34a20e89 | 639 | goto out; |
9d5c8243 AK |
640 | |
641 | igb_reset_interrupt_capability(adapter); | |
642 | ||
643 | /* If we can't do MSI-X, try MSI */ | |
644 | msi_only: | |
645 | adapter->num_rx_queues = 1; | |
661086df | 646 | adapter->num_tx_queues = 1; |
9d5c8243 | 647 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 648 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 649 | out: |
661086df | 650 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 651 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
9d5c8243 AK |
652 | return; |
653 | } | |
654 | ||
655 | /** | |
656 | * igb_request_irq - initialize interrupts | |
657 | * | |
658 | * Attempts to configure interrupts using the best available | |
659 | * capabilities of the hardware and kernel. | |
660 | **/ | |
661 | static int igb_request_irq(struct igb_adapter *adapter) | |
662 | { | |
663 | struct net_device *netdev = adapter->netdev; | |
664 | struct e1000_hw *hw = &adapter->hw; | |
665 | int err = 0; | |
666 | ||
667 | if (adapter->msix_entries) { | |
668 | err = igb_request_msix(adapter); | |
844290e5 | 669 | if (!err) |
9d5c8243 | 670 | goto request_done; |
9d5c8243 AK |
671 | /* fall back to MSI */ |
672 | igb_reset_interrupt_capability(adapter); | |
673 | if (!pci_enable_msi(adapter->pdev)) | |
7dfc16fa | 674 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
675 | igb_free_all_tx_resources(adapter); |
676 | igb_free_all_rx_resources(adapter); | |
677 | adapter->num_rx_queues = 1; | |
678 | igb_alloc_queues(adapter); | |
844290e5 | 679 | } else { |
2d064c06 AD |
680 | switch (hw->mac.type) { |
681 | case e1000_82575: | |
682 | wr32(E1000_MSIXBM(0), | |
683 | (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); | |
684 | break; | |
685 | case e1000_82576: | |
686 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | |
687 | break; | |
688 | default: | |
689 | break; | |
690 | } | |
9d5c8243 | 691 | } |
844290e5 | 692 | |
7dfc16fa | 693 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 AK |
694 | err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, |
695 | netdev->name, netdev); | |
696 | if (!err) | |
697 | goto request_done; | |
698 | /* fall back to legacy interrupts */ | |
699 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 700 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
701 | } |
702 | ||
703 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, | |
704 | netdev->name, netdev); | |
705 | ||
6cb5e577 | 706 | if (err) |
9d5c8243 AK |
707 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
708 | err); | |
9d5c8243 AK |
709 | |
710 | request_done: | |
711 | return err; | |
712 | } | |
713 | ||
714 | static void igb_free_irq(struct igb_adapter *adapter) | |
715 | { | |
716 | struct net_device *netdev = adapter->netdev; | |
717 | ||
718 | if (adapter->msix_entries) { | |
719 | int vector = 0, i; | |
720 | ||
721 | for (i = 0; i < adapter->num_tx_queues; i++) | |
722 | free_irq(adapter->msix_entries[vector++].vector, | |
723 | &(adapter->tx_ring[i])); | |
724 | for (i = 0; i < adapter->num_rx_queues; i++) | |
725 | free_irq(adapter->msix_entries[vector++].vector, | |
726 | &(adapter->rx_ring[i])); | |
727 | ||
728 | free_irq(adapter->msix_entries[vector++].vector, netdev); | |
729 | return; | |
730 | } | |
731 | ||
732 | free_irq(adapter->pdev->irq, netdev); | |
733 | } | |
734 | ||
735 | /** | |
736 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
737 | * @adapter: board private structure | |
738 | **/ | |
739 | static void igb_irq_disable(struct igb_adapter *adapter) | |
740 | { | |
741 | struct e1000_hw *hw = &adapter->hw; | |
742 | ||
743 | if (adapter->msix_entries) { | |
844290e5 | 744 | wr32(E1000_EIAM, 0); |
9d5c8243 AK |
745 | wr32(E1000_EIMC, ~0); |
746 | wr32(E1000_EIAC, 0); | |
747 | } | |
844290e5 PW |
748 | |
749 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
750 | wr32(E1000_IMC, ~0); |
751 | wrfl(); | |
752 | synchronize_irq(adapter->pdev->irq); | |
753 | } | |
754 | ||
755 | /** | |
756 | * igb_irq_enable - Enable default interrupt generation settings | |
757 | * @adapter: board private structure | |
758 | **/ | |
759 | static void igb_irq_enable(struct igb_adapter *adapter) | |
760 | { | |
761 | struct e1000_hw *hw = &adapter->hw; | |
762 | ||
763 | if (adapter->msix_entries) { | |
844290e5 PW |
764 | wr32(E1000_EIAC, adapter->eims_enable_mask); |
765 | wr32(E1000_EIAM, adapter->eims_enable_mask); | |
766 | wr32(E1000_EIMS, adapter->eims_enable_mask); | |
dda0e083 | 767 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); |
844290e5 PW |
768 | } else { |
769 | wr32(E1000_IMS, IMS_ENABLE_MASK); | |
770 | wr32(E1000_IAM, IMS_ENABLE_MASK); | |
771 | } | |
9d5c8243 AK |
772 | } |
773 | ||
774 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
775 | { | |
776 | struct net_device *netdev = adapter->netdev; | |
777 | u16 vid = adapter->hw.mng_cookie.vlan_id; | |
778 | u16 old_vid = adapter->mng_vlan_id; | |
779 | if (adapter->vlgrp) { | |
780 | if (!vlan_group_get_device(adapter->vlgrp, vid)) { | |
781 | if (adapter->hw.mng_cookie.status & | |
782 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
783 | igb_vlan_rx_add_vid(netdev, vid); | |
784 | adapter->mng_vlan_id = vid; | |
785 | } else | |
786 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
787 | ||
788 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
789 | (vid != old_vid) && | |
790 | !vlan_group_get_device(adapter->vlgrp, old_vid)) | |
791 | igb_vlan_rx_kill_vid(netdev, old_vid); | |
792 | } else | |
793 | adapter->mng_vlan_id = vid; | |
794 | } | |
795 | } | |
796 | ||
797 | /** | |
798 | * igb_release_hw_control - release control of the h/w to f/w | |
799 | * @adapter: address of board private structure | |
800 | * | |
801 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
802 | * For ASF and Pass Through versions of f/w this means that the | |
803 | * driver is no longer loaded. | |
804 | * | |
805 | **/ | |
806 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
807 | { | |
808 | struct e1000_hw *hw = &adapter->hw; | |
809 | u32 ctrl_ext; | |
810 | ||
811 | /* Let firmware take over control of h/w */ | |
812 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
813 | wr32(E1000_CTRL_EXT, | |
814 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
815 | } | |
816 | ||
817 | ||
818 | /** | |
819 | * igb_get_hw_control - get control of the h/w from f/w | |
820 | * @adapter: address of board private structure | |
821 | * | |
822 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
823 | * For ASF and Pass Through versions of f/w this means that | |
824 | * the driver is loaded. | |
825 | * | |
826 | **/ | |
827 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
828 | { | |
829 | struct e1000_hw *hw = &adapter->hw; | |
830 | u32 ctrl_ext; | |
831 | ||
832 | /* Let firmware know the driver has taken over */ | |
833 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
834 | wr32(E1000_CTRL_EXT, | |
835 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
836 | } | |
837 | ||
9d5c8243 AK |
838 | /** |
839 | * igb_configure - configure the hardware for RX and TX | |
840 | * @adapter: private board structure | |
841 | **/ | |
842 | static void igb_configure(struct igb_adapter *adapter) | |
843 | { | |
844 | struct net_device *netdev = adapter->netdev; | |
845 | int i; | |
846 | ||
847 | igb_get_hw_control(adapter); | |
848 | igb_set_multi(netdev); | |
849 | ||
850 | igb_restore_vlan(adapter); | |
9d5c8243 AK |
851 | |
852 | igb_configure_tx(adapter); | |
853 | igb_setup_rctl(adapter); | |
854 | igb_configure_rx(adapter); | |
662d7205 AD |
855 | |
856 | igb_rx_fifo_flush_82575(&adapter->hw); | |
857 | ||
9d5c8243 AK |
858 | /* call IGB_DESC_UNUSED which always leaves |
859 | * at least 1 descriptor unused to make sure | |
860 | * next_to_use != next_to_clean */ | |
861 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
862 | struct igb_ring *ring = &adapter->rx_ring[i]; | |
3b644cf6 | 863 | igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring)); |
9d5c8243 AK |
864 | } |
865 | ||
866 | ||
867 | adapter->tx_queue_len = netdev->tx_queue_len; | |
868 | } | |
869 | ||
870 | ||
871 | /** | |
872 | * igb_up - Open the interface and prepare it to handle traffic | |
873 | * @adapter: board private structure | |
874 | **/ | |
875 | ||
876 | int igb_up(struct igb_adapter *adapter) | |
877 | { | |
878 | struct e1000_hw *hw = &adapter->hw; | |
879 | int i; | |
880 | ||
881 | /* hardware has been reset, we need to reload some things */ | |
882 | igb_configure(adapter); | |
883 | ||
884 | clear_bit(__IGB_DOWN, &adapter->state); | |
885 | ||
844290e5 PW |
886 | for (i = 0; i < adapter->num_rx_queues; i++) |
887 | napi_enable(&adapter->rx_ring[i].napi); | |
888 | if (adapter->msix_entries) | |
9d5c8243 | 889 | igb_configure_msix(adapter); |
9d5c8243 AK |
890 | |
891 | /* Clear any pending interrupts. */ | |
892 | rd32(E1000_ICR); | |
893 | igb_irq_enable(adapter); | |
894 | ||
895 | /* Fire a link change interrupt to start the watchdog. */ | |
896 | wr32(E1000_ICS, E1000_ICS_LSC); | |
897 | return 0; | |
898 | } | |
899 | ||
900 | void igb_down(struct igb_adapter *adapter) | |
901 | { | |
902 | struct e1000_hw *hw = &adapter->hw; | |
903 | struct net_device *netdev = adapter->netdev; | |
904 | u32 tctl, rctl; | |
905 | int i; | |
906 | ||
907 | /* signal that we're down so the interrupt handler does not | |
908 | * reschedule our watchdog timer */ | |
909 | set_bit(__IGB_DOWN, &adapter->state); | |
910 | ||
911 | /* disable receives in the hardware */ | |
912 | rctl = rd32(E1000_RCTL); | |
913 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
914 | /* flush and sleep below */ | |
915 | ||
fd2ea0a7 | 916 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
917 | |
918 | /* disable transmits in the hardware */ | |
919 | tctl = rd32(E1000_TCTL); | |
920 | tctl &= ~E1000_TCTL_EN; | |
921 | wr32(E1000_TCTL, tctl); | |
922 | /* flush both disables and wait for them to finish */ | |
923 | wrfl(); | |
924 | msleep(10); | |
925 | ||
844290e5 PW |
926 | for (i = 0; i < adapter->num_rx_queues; i++) |
927 | napi_disable(&adapter->rx_ring[i].napi); | |
9d5c8243 | 928 | |
9d5c8243 AK |
929 | igb_irq_disable(adapter); |
930 | ||
931 | del_timer_sync(&adapter->watchdog_timer); | |
932 | del_timer_sync(&adapter->phy_info_timer); | |
933 | ||
934 | netdev->tx_queue_len = adapter->tx_queue_len; | |
935 | netif_carrier_off(netdev); | |
04fe6358 AD |
936 | |
937 | /* record the stats before reset*/ | |
938 | igb_update_stats(adapter); | |
939 | ||
9d5c8243 AK |
940 | adapter->link_speed = 0; |
941 | adapter->link_duplex = 0; | |
942 | ||
3023682e JK |
943 | if (!pci_channel_offline(adapter->pdev)) |
944 | igb_reset(adapter); | |
9d5c8243 AK |
945 | igb_clean_all_tx_rings(adapter); |
946 | igb_clean_all_rx_rings(adapter); | |
947 | } | |
948 | ||
949 | void igb_reinit_locked(struct igb_adapter *adapter) | |
950 | { | |
951 | WARN_ON(in_interrupt()); | |
952 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
953 | msleep(1); | |
954 | igb_down(adapter); | |
955 | igb_up(adapter); | |
956 | clear_bit(__IGB_RESETTING, &adapter->state); | |
957 | } | |
958 | ||
959 | void igb_reset(struct igb_adapter *adapter) | |
960 | { | |
961 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
962 | struct e1000_mac_info *mac = &hw->mac; |
963 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
964 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
965 | u16 hwm; | |
966 | ||
967 | /* Repartition Pba for greater than 9k mtu | |
968 | * To take effect CTRL.RST is required. | |
969 | */ | |
fa4dfae0 AD |
970 | switch (mac->type) { |
971 | case e1000_82576: | |
2d064c06 | 972 | pba = E1000_PBA_64K; |
fa4dfae0 AD |
973 | break; |
974 | case e1000_82575: | |
975 | default: | |
976 | pba = E1000_PBA_34K; | |
977 | break; | |
2d064c06 | 978 | } |
9d5c8243 | 979 | |
2d064c06 AD |
980 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
981 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
982 | /* adjust PBA for jumbo frames */ |
983 | wr32(E1000_PBA, pba); | |
984 | ||
985 | /* To maintain wire speed transmits, the Tx FIFO should be | |
986 | * large enough to accommodate two full transmit packets, | |
987 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
988 | * the Rx FIFO should be large enough to accommodate at least | |
989 | * one full receive packet and is similarly rounded up and | |
990 | * expressed in KB. */ | |
991 | pba = rd32(E1000_PBA); | |
992 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
993 | tx_space = pba >> 16; | |
994 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
995 | pba &= 0xffff; | |
996 | /* the tx fifo also stores 16 bytes of information about the tx | |
997 | * but don't include ethernet FCS because hardware appends it */ | |
998 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 999 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1000 | ETH_FCS_LEN) * 2; |
1001 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1002 | min_tx_space >>= 10; | |
1003 | /* software strips receive CRC, so leave room for it */ | |
1004 | min_rx_space = adapter->max_frame_size; | |
1005 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1006 | min_rx_space >>= 10; | |
1007 | ||
1008 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1009 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1010 | * allocation, take space away from current Rx allocation */ | |
1011 | if (tx_space < min_tx_space && | |
1012 | ((min_tx_space - tx_space) < pba)) { | |
1013 | pba = pba - (min_tx_space - tx_space); | |
1014 | ||
1015 | /* if short on rx space, rx wins and must trump tx | |
1016 | * adjustment */ | |
1017 | if (pba < min_rx_space) | |
1018 | pba = min_rx_space; | |
1019 | } | |
2d064c06 | 1020 | wr32(E1000_PBA, pba); |
9d5c8243 | 1021 | } |
9d5c8243 AK |
1022 | |
1023 | /* flow control settings */ | |
1024 | /* The high water mark must be low enough to fit one full frame | |
1025 | * (or the size used for early receive) above it in the Rx FIFO. | |
1026 | * Set it to the lower of: | |
1027 | * - 90% of the Rx FIFO size, or | |
1028 | * - the full Rx FIFO size minus one full frame */ | |
1029 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1030 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1031 | |
2d064c06 AD |
1032 | if (mac->type < e1000_82576) { |
1033 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | |
1034 | fc->low_water = fc->high_water - 8; | |
1035 | } else { | |
1036 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | |
1037 | fc->low_water = fc->high_water - 16; | |
1038 | } | |
9d5c8243 AK |
1039 | fc->pause_time = 0xFFFF; |
1040 | fc->send_xon = 1; | |
1041 | fc->type = fc->original_type; | |
1042 | ||
1043 | /* Allow time for pending master requests to run */ | |
1044 | adapter->hw.mac.ops.reset_hw(&adapter->hw); | |
1045 | wr32(E1000_WUC, 0); | |
1046 | ||
1047 | if (adapter->hw.mac.ops.init_hw(&adapter->hw)) | |
1048 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
1049 | ||
1050 | igb_update_mng_vlan(adapter); | |
1051 | ||
1052 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1053 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1054 | ||
1055 | igb_reset_adaptive(&adapter->hw); | |
f5f4cf08 | 1056 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
1057 | } |
1058 | ||
2e5c6922 SH |
1059 | static const struct net_device_ops igb_netdev_ops = { |
1060 | .ndo_open = igb_open, | |
1061 | .ndo_stop = igb_close, | |
00829823 | 1062 | .ndo_start_xmit = igb_xmit_frame_adv, |
2e5c6922 SH |
1063 | .ndo_get_stats = igb_get_stats, |
1064 | .ndo_set_multicast_list = igb_set_multi, | |
1065 | .ndo_set_mac_address = igb_set_mac, | |
1066 | .ndo_change_mtu = igb_change_mtu, | |
1067 | .ndo_do_ioctl = igb_ioctl, | |
1068 | .ndo_tx_timeout = igb_tx_timeout, | |
1069 | .ndo_validate_addr = eth_validate_addr, | |
1070 | .ndo_vlan_rx_register = igb_vlan_rx_register, | |
1071 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, | |
1072 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
1073 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1074 | .ndo_poll_controller = igb_netpoll, | |
1075 | #endif | |
1076 | }; | |
1077 | ||
9d5c8243 AK |
1078 | /** |
1079 | * igb_probe - Device Initialization Routine | |
1080 | * @pdev: PCI device information struct | |
1081 | * @ent: entry in igb_pci_tbl | |
1082 | * | |
1083 | * Returns 0 on success, negative on failure | |
1084 | * | |
1085 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1086 | * The OS initialization, configuring of the adapter private structure, | |
1087 | * and a hardware reset occur. | |
1088 | **/ | |
1089 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1090 | const struct pci_device_id *ent) | |
1091 | { | |
1092 | struct net_device *netdev; | |
1093 | struct igb_adapter *adapter; | |
1094 | struct e1000_hw *hw; | |
c54106bb | 1095 | struct pci_dev *us_dev; |
9d5c8243 AK |
1096 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1097 | unsigned long mmio_start, mmio_len; | |
450c87c8 | 1098 | int err, pci_using_dac, pos; |
c54106bb | 1099 | u16 eeprom_data = 0, state = 0; |
9d5c8243 AK |
1100 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
1101 | u32 part_num; | |
1102 | ||
aed5dec3 | 1103 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1104 | if (err) |
1105 | return err; | |
1106 | ||
1107 | pci_using_dac = 0; | |
1108 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
1109 | if (!err) { | |
1110 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1111 | if (!err) | |
1112 | pci_using_dac = 1; | |
1113 | } else { | |
1114 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1115 | if (err) { | |
1116 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1117 | if (err) { | |
1118 | dev_err(&pdev->dev, "No usable DMA " | |
1119 | "configuration, aborting\n"); | |
1120 | goto err_dma; | |
1121 | } | |
1122 | } | |
1123 | } | |
1124 | ||
c54106bb AD |
1125 | /* 82575 requires that the pci-e link partner disable the L0s state */ |
1126 | switch (pdev->device) { | |
1127 | case E1000_DEV_ID_82575EB_COPPER: | |
1128 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
1129 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1130 | us_dev = pdev->bus->self; | |
1131 | pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP); | |
1132 | if (pos) { | |
1133 | pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL, | |
1134 | &state); | |
1135 | state &= ~PCIE_LINK_STATE_L0S; | |
1136 | pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL, | |
1137 | state); | |
ac450208 BH |
1138 | dev_info(&pdev->dev, |
1139 | "Disabling ASPM L0s upstream switch port %s\n", | |
1140 | pci_name(us_dev)); | |
c54106bb AD |
1141 | } |
1142 | default: | |
1143 | break; | |
1144 | } | |
1145 | ||
aed5dec3 AD |
1146 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1147 | IORESOURCE_MEM), | |
1148 | igb_driver_name); | |
9d5c8243 AK |
1149 | if (err) |
1150 | goto err_pci_reg; | |
1151 | ||
ea943d41 JK |
1152 | err = pci_enable_pcie_error_reporting(pdev); |
1153 | if (err) { | |
1154 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
1155 | "0x%x\n", err); | |
1156 | /* non-fatal, continue */ | |
1157 | } | |
40a914fa | 1158 | |
9d5c8243 | 1159 | pci_set_master(pdev); |
c682fc23 | 1160 | pci_save_state(pdev); |
9d5c8243 AK |
1161 | |
1162 | err = -ENOMEM; | |
1bfaf07b AD |
1163 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1164 | IGB_ABS_MAX_TX_QUEUES); | |
9d5c8243 AK |
1165 | if (!netdev) |
1166 | goto err_alloc_etherdev; | |
1167 | ||
1168 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1169 | ||
1170 | pci_set_drvdata(pdev, netdev); | |
1171 | adapter = netdev_priv(netdev); | |
1172 | adapter->netdev = netdev; | |
1173 | adapter->pdev = pdev; | |
1174 | hw = &adapter->hw; | |
1175 | hw->back = adapter; | |
1176 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
1177 | ||
1178 | mmio_start = pci_resource_start(pdev, 0); | |
1179 | mmio_len = pci_resource_len(pdev, 0); | |
1180 | ||
1181 | err = -EIO; | |
28b0759c AD |
1182 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1183 | if (!hw->hw_addr) | |
9d5c8243 AK |
1184 | goto err_ioremap; |
1185 | ||
2e5c6922 | 1186 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1187 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1188 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1189 | |
1190 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1191 | ||
1192 | netdev->mem_start = mmio_start; | |
1193 | netdev->mem_end = mmio_start + mmio_len; | |
1194 | ||
9d5c8243 AK |
1195 | /* PCI config space info */ |
1196 | hw->vendor_id = pdev->vendor; | |
1197 | hw->device_id = pdev->device; | |
1198 | hw->revision_id = pdev->revision; | |
1199 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1200 | hw->subsystem_device_id = pdev->subsystem_device; | |
1201 | ||
1202 | /* setup the private structure */ | |
1203 | hw->back = adapter; | |
1204 | /* Copy the default MAC, PHY and NVM function pointers */ | |
1205 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1206 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1207 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1208 | /* Initialize skew-specific constants */ | |
1209 | err = ei->get_invariants(hw); | |
1210 | if (err) | |
450c87c8 | 1211 | goto err_sw_init; |
9d5c8243 | 1212 | |
450c87c8 | 1213 | /* setup the private structure */ |
9d5c8243 AK |
1214 | err = igb_sw_init(adapter); |
1215 | if (err) | |
1216 | goto err_sw_init; | |
1217 | ||
1218 | igb_get_bus_info_pcie(hw); | |
1219 | ||
7dfc16fa AD |
1220 | /* set flags */ |
1221 | switch (hw->mac.type) { | |
7dfc16fa | 1222 | case e1000_82575: |
7dfc16fa AD |
1223 | adapter->flags |= IGB_FLAG_NEED_CTX_IDX; |
1224 | break; | |
bbd98fe4 | 1225 | case e1000_82576: |
7dfc16fa AD |
1226 | default: |
1227 | break; | |
1228 | } | |
1229 | ||
9d5c8243 AK |
1230 | hw->phy.autoneg_wait_to_complete = false; |
1231 | hw->mac.adaptive_ifs = true; | |
1232 | ||
1233 | /* Copper options */ | |
1234 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1235 | hw->phy.mdix = AUTO_ALL_MODES; | |
1236 | hw->phy.disable_polarity_correction = false; | |
1237 | hw->phy.ms_type = e1000_ms_hw_default; | |
1238 | } | |
1239 | ||
1240 | if (igb_check_reset_block(hw)) | |
1241 | dev_info(&pdev->dev, | |
1242 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1243 | ||
1244 | netdev->features = NETIF_F_SG | | |
7d8eb29e | 1245 | NETIF_F_IP_CSUM | |
9d5c8243 AK |
1246 | NETIF_F_HW_VLAN_TX | |
1247 | NETIF_F_HW_VLAN_RX | | |
1248 | NETIF_F_HW_VLAN_FILTER; | |
1249 | ||
7d8eb29e | 1250 | netdev->features |= NETIF_F_IPV6_CSUM; |
9d5c8243 | 1251 | netdev->features |= NETIF_F_TSO; |
9d5c8243 | 1252 | netdev->features |= NETIF_F_TSO6; |
48f29ffc | 1253 | |
5c0999b7 | 1254 | netdev->features |= NETIF_F_GRO; |
d3352520 | 1255 | |
48f29ffc JK |
1256 | netdev->vlan_features |= NETIF_F_TSO; |
1257 | netdev->vlan_features |= NETIF_F_TSO6; | |
7d8eb29e | 1258 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
48f29ffc JK |
1259 | netdev->vlan_features |= NETIF_F_SG; |
1260 | ||
9d5c8243 AK |
1261 | if (pci_using_dac) |
1262 | netdev->features |= NETIF_F_HIGHDMA; | |
1263 | ||
9d5c8243 AK |
1264 | adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw); |
1265 | ||
1266 | /* before reading the NVM, reset the controller to put the device in a | |
1267 | * known good starting state */ | |
1268 | hw->mac.ops.reset_hw(hw); | |
1269 | ||
1270 | /* make sure the NVM is good */ | |
1271 | if (igb_validate_nvm_checksum(hw) < 0) { | |
1272 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
1273 | err = -EIO; | |
1274 | goto err_eeprom; | |
1275 | } | |
1276 | ||
1277 | /* copy the MAC address out of the NVM */ | |
1278 | if (hw->mac.ops.read_mac_addr(hw)) | |
1279 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1280 | ||
1281 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1282 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1283 | ||
1284 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1285 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1286 | err = -EIO; | |
1287 | goto err_eeprom; | |
1288 | } | |
1289 | ||
1290 | init_timer(&adapter->watchdog_timer); | |
1291 | adapter->watchdog_timer.function = &igb_watchdog; | |
1292 | adapter->watchdog_timer.data = (unsigned long) adapter; | |
1293 | ||
1294 | init_timer(&adapter->phy_info_timer); | |
1295 | adapter->phy_info_timer.function = &igb_update_phy_info; | |
1296 | adapter->phy_info_timer.data = (unsigned long) adapter; | |
1297 | ||
1298 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
1299 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
1300 | ||
450c87c8 | 1301 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
1302 | adapter->fc_autoneg = true; |
1303 | hw->mac.autoneg = true; | |
1304 | hw->phy.autoneg_advertised = 0x2f; | |
1305 | ||
1306 | hw->fc.original_type = e1000_fc_default; | |
1307 | hw->fc.type = e1000_fc_default; | |
1308 | ||
cbd347ad | 1309 | adapter->itr_setting = IGB_DEFAULT_ITR; |
9d5c8243 AK |
1310 | adapter->itr = IGB_START_ITR; |
1311 | ||
1312 | igb_validate_mdi_setting(hw); | |
1313 | ||
1314 | adapter->rx_csum = 1; | |
1315 | ||
1316 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, | |
1317 | * enable the ACPI Magic Packet filter | |
1318 | */ | |
1319 | ||
1320 | if (hw->bus.func == 0 || | |
1321 | hw->device_id == E1000_DEV_ID_82575EB_COPPER) | |
312c75ae | 1322 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
9d5c8243 AK |
1323 | |
1324 | if (eeprom_data & eeprom_apme_mask) | |
1325 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
1326 | ||
1327 | /* now that we have the eeprom settings, apply the special cases where | |
1328 | * the eeprom may be wrong or the board simply won't support wake on | |
1329 | * lan on a particular port */ | |
1330 | switch (pdev->device) { | |
1331 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1332 | adapter->eeprom_wol = 0; | |
1333 | break; | |
1334 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1335 | case E1000_DEV_ID_82576_FIBER: |
1336 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1337 | /* Wake events only supported on port A for dual fiber |
1338 | * regardless of eeprom setting */ | |
1339 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
1340 | adapter->eeprom_wol = 0; | |
1341 | break; | |
1342 | } | |
1343 | ||
1344 | /* initialize the wol settings based on the eeprom settings */ | |
1345 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 1346 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
1347 | |
1348 | /* reset the hardware with the new settings */ | |
1349 | igb_reset(adapter); | |
1350 | ||
1351 | /* let the f/w know that the h/w is now under the control of the | |
1352 | * driver. */ | |
1353 | igb_get_hw_control(adapter); | |
1354 | ||
1355 | /* tell the stack to leave us alone until igb_open() is called */ | |
1356 | netif_carrier_off(netdev); | |
fd2ea0a7 | 1357 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1358 | |
1359 | strcpy(netdev->name, "eth%d"); | |
1360 | err = register_netdev(netdev); | |
1361 | if (err) | |
1362 | goto err_register; | |
1363 | ||
421e02f0 | 1364 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 1365 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 1366 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
1367 | dev_info(&pdev->dev, "DCA enabled\n"); |
1368 | /* Always use CB2 mode, difference is masked | |
1369 | * in the CB driver. */ | |
cbd347ad | 1370 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
fe4506b6 JC |
1371 | igb_setup_dca(adapter); |
1372 | } | |
1373 | #endif | |
1374 | ||
38c845c7 PO |
1375 | /* |
1376 | * Initialize hardware timer: we keep it running just in case | |
1377 | * that some program needs it later on. | |
1378 | */ | |
1379 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
1380 | adapter->cycles.read = igb_read_clock; | |
1381 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
1382 | adapter->cycles.mult = 1; | |
1383 | adapter->cycles.shift = IGB_TSYNC_SHIFT; | |
1384 | wr32(E1000_TIMINCA, | |
1385 | (1<<24) | | |
1386 | IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE); | |
1387 | #if 0 | |
1388 | /* | |
1389 | * Avoid rollover while we initialize by resetting the time counter. | |
1390 | */ | |
1391 | wr32(E1000_SYSTIML, 0x00000000); | |
1392 | wr32(E1000_SYSTIMH, 0x00000000); | |
1393 | #else | |
1394 | /* | |
1395 | * Set registers so that rollover occurs soon to test this. | |
1396 | */ | |
1397 | wr32(E1000_SYSTIML, 0x00000000); | |
1398 | wr32(E1000_SYSTIMH, 0xFF800000); | |
1399 | #endif | |
1400 | wrfl(); | |
1401 | timecounter_init(&adapter->clock, | |
1402 | &adapter->cycles, | |
1403 | ktime_to_ns(ktime_get_real())); | |
1404 | ||
33af6bcc PO |
1405 | /* |
1406 | * Synchronize our NIC clock against system wall clock. NIC | |
1407 | * time stamp reading requires ~3us per sample, each sample | |
1408 | * was pretty stable even under load => only require 10 | |
1409 | * samples for each offset comparison. | |
1410 | */ | |
1411 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
1412 | adapter->compare.source = &adapter->clock; | |
1413 | adapter->compare.target = ktime_get_real; | |
1414 | adapter->compare.num_samples = 10; | |
1415 | timecompare_update(&adapter->compare, 0); | |
1416 | ||
38c845c7 PO |
1417 | #ifdef DEBUG |
1418 | { | |
1419 | char buffer[160]; | |
1420 | printk(KERN_DEBUG | |
1421 | "igb: %s: hw %p initialized timer\n", | |
1422 | igb_get_time_str(adapter, buffer), | |
1423 | &adapter->hw); | |
1424 | } | |
1425 | #endif | |
1426 | ||
9d5c8243 AK |
1427 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1428 | /* print bus type/speed/width info */ | |
7c510e4b | 1429 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 AK |
1430 | netdev->name, |
1431 | ((hw->bus.speed == e1000_bus_speed_2500) | |
1432 | ? "2.5Gb/s" : "unknown"), | |
1433 | ((hw->bus.width == e1000_bus_width_pcie_x4) | |
1434 | ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1) | |
1435 | ? "Width x1" : "unknown"), | |
7c510e4b | 1436 | netdev->dev_addr); |
9d5c8243 AK |
1437 | |
1438 | igb_read_part_num(hw, &part_num); | |
1439 | dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, | |
1440 | (part_num >> 8), (part_num & 0xff)); | |
1441 | ||
1442 | dev_info(&pdev->dev, | |
1443 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
1444 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 1445 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 AK |
1446 | adapter->num_rx_queues, adapter->num_tx_queues); |
1447 | ||
9d5c8243 AK |
1448 | return 0; |
1449 | ||
1450 | err_register: | |
1451 | igb_release_hw_control(adapter); | |
1452 | err_eeprom: | |
1453 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 1454 | igb_reset_phy(hw); |
9d5c8243 AK |
1455 | |
1456 | if (hw->flash_address) | |
1457 | iounmap(hw->flash_address); | |
1458 | ||
a88f10ec | 1459 | igb_free_queues(adapter); |
9d5c8243 | 1460 | err_sw_init: |
9d5c8243 AK |
1461 | iounmap(hw->hw_addr); |
1462 | err_ioremap: | |
1463 | free_netdev(netdev); | |
1464 | err_alloc_etherdev: | |
aed5dec3 AD |
1465 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
1466 | IORESOURCE_MEM)); | |
9d5c8243 AK |
1467 | err_pci_reg: |
1468 | err_dma: | |
1469 | pci_disable_device(pdev); | |
1470 | return err; | |
1471 | } | |
1472 | ||
1473 | /** | |
1474 | * igb_remove - Device Removal Routine | |
1475 | * @pdev: PCI device information struct | |
1476 | * | |
1477 | * igb_remove is called by the PCI subsystem to alert the driver | |
1478 | * that it should release a PCI device. The could be caused by a | |
1479 | * Hot-Plug event, or because the driver is going to be removed from | |
1480 | * memory. | |
1481 | **/ | |
1482 | static void __devexit igb_remove(struct pci_dev *pdev) | |
1483 | { | |
1484 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1485 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 1486 | struct e1000_hw *hw = &adapter->hw; |
ea943d41 | 1487 | int err; |
9d5c8243 AK |
1488 | |
1489 | /* flush_scheduled work may reschedule our watchdog task, so | |
1490 | * explicitly disable watchdog tasks from being rescheduled */ | |
1491 | set_bit(__IGB_DOWN, &adapter->state); | |
1492 | del_timer_sync(&adapter->watchdog_timer); | |
1493 | del_timer_sync(&adapter->phy_info_timer); | |
1494 | ||
1495 | flush_scheduled_work(); | |
1496 | ||
421e02f0 | 1497 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 1498 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
1499 | dev_info(&pdev->dev, "DCA disabled\n"); |
1500 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 1501 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 1502 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
1503 | } |
1504 | #endif | |
1505 | ||
9d5c8243 AK |
1506 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
1507 | * would have already happened in close and is redundant. */ | |
1508 | igb_release_hw_control(adapter); | |
1509 | ||
1510 | unregister_netdev(netdev); | |
1511 | ||
f5f4cf08 AD |
1512 | if (!igb_check_reset_block(&adapter->hw)) |
1513 | igb_reset_phy(&adapter->hw); | |
9d5c8243 | 1514 | |
9d5c8243 AK |
1515 | igb_reset_interrupt_capability(adapter); |
1516 | ||
a88f10ec | 1517 | igb_free_queues(adapter); |
9d5c8243 | 1518 | |
28b0759c AD |
1519 | iounmap(hw->hw_addr); |
1520 | if (hw->flash_address) | |
1521 | iounmap(hw->flash_address); | |
aed5dec3 AD |
1522 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
1523 | IORESOURCE_MEM)); | |
9d5c8243 AK |
1524 | |
1525 | free_netdev(netdev); | |
1526 | ||
ea943d41 JK |
1527 | err = pci_disable_pcie_error_reporting(pdev); |
1528 | if (err) | |
1529 | dev_err(&pdev->dev, | |
1530 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
40a914fa | 1531 | |
9d5c8243 AK |
1532 | pci_disable_device(pdev); |
1533 | } | |
1534 | ||
1535 | /** | |
1536 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
1537 | * @adapter: board private structure to initialize | |
1538 | * | |
1539 | * igb_sw_init initializes the Adapter private data structure. | |
1540 | * Fields are initialized based on PCI device information and | |
1541 | * OS network device settings (MTU size). | |
1542 | **/ | |
1543 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
1544 | { | |
1545 | struct e1000_hw *hw = &adapter->hw; | |
1546 | struct net_device *netdev = adapter->netdev; | |
1547 | struct pci_dev *pdev = adapter->pdev; | |
1548 | ||
1549 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
1550 | ||
68fd9910 AD |
1551 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
1552 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
9d5c8243 AK |
1553 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
1554 | adapter->rx_ps_hdr_size = 0; /* disable packet split */ | |
1555 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
1556 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
1557 | ||
661086df PWJ |
1558 | /* This call may decrease the number of queues depending on |
1559 | * interrupt mode. */ | |
9d5c8243 AK |
1560 | igb_set_interrupt_capability(adapter); |
1561 | ||
1562 | if (igb_alloc_queues(adapter)) { | |
1563 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
1564 | return -ENOMEM; | |
1565 | } | |
1566 | ||
1567 | /* Explicitly disable IRQ since the NIC can be in any state. */ | |
1568 | igb_irq_disable(adapter); | |
1569 | ||
1570 | set_bit(__IGB_DOWN, &adapter->state); | |
1571 | return 0; | |
1572 | } | |
1573 | ||
1574 | /** | |
1575 | * igb_open - Called when a network interface is made active | |
1576 | * @netdev: network interface device structure | |
1577 | * | |
1578 | * Returns 0 on success, negative value on failure | |
1579 | * | |
1580 | * The open entry point is called when a network interface is made | |
1581 | * active by the system (IFF_UP). At this point all resources needed | |
1582 | * for transmit and receive operations are allocated, the interrupt | |
1583 | * handler is registered with the OS, the watchdog timer is started, | |
1584 | * and the stack is notified that the interface is ready. | |
1585 | **/ | |
1586 | static int igb_open(struct net_device *netdev) | |
1587 | { | |
1588 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1589 | struct e1000_hw *hw = &adapter->hw; | |
1590 | int err; | |
1591 | int i; | |
1592 | ||
1593 | /* disallow open during test */ | |
1594 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
1595 | return -EBUSY; | |
1596 | ||
1597 | /* allocate transmit descriptors */ | |
1598 | err = igb_setup_all_tx_resources(adapter); | |
1599 | if (err) | |
1600 | goto err_setup_tx; | |
1601 | ||
1602 | /* allocate receive descriptors */ | |
1603 | err = igb_setup_all_rx_resources(adapter); | |
1604 | if (err) | |
1605 | goto err_setup_rx; | |
1606 | ||
1607 | /* e1000_power_up_phy(adapter); */ | |
1608 | ||
1609 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1610 | if ((adapter->hw.mng_cookie.status & | |
1611 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) | |
1612 | igb_update_mng_vlan(adapter); | |
1613 | ||
1614 | /* before we allocate an interrupt, we must be ready to handle it. | |
1615 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
1616 | * as soon as we call pci_request_irq, so we have to setup our | |
1617 | * clean_rx handler before we do so. */ | |
1618 | igb_configure(adapter); | |
1619 | ||
1620 | err = igb_request_irq(adapter); | |
1621 | if (err) | |
1622 | goto err_req_irq; | |
1623 | ||
1624 | /* From here on the code is the same as igb_up() */ | |
1625 | clear_bit(__IGB_DOWN, &adapter->state); | |
1626 | ||
844290e5 PW |
1627 | for (i = 0; i < adapter->num_rx_queues; i++) |
1628 | napi_enable(&adapter->rx_ring[i].napi); | |
9d5c8243 AK |
1629 | |
1630 | /* Clear any pending interrupts. */ | |
1631 | rd32(E1000_ICR); | |
844290e5 PW |
1632 | |
1633 | igb_irq_enable(adapter); | |
1634 | ||
d55b53ff JK |
1635 | netif_tx_start_all_queues(netdev); |
1636 | ||
9d5c8243 AK |
1637 | /* Fire a link status change interrupt to start the watchdog. */ |
1638 | wr32(E1000_ICS, E1000_ICS_LSC); | |
1639 | ||
1640 | return 0; | |
1641 | ||
1642 | err_req_irq: | |
1643 | igb_release_hw_control(adapter); | |
1644 | /* e1000_power_down_phy(adapter); */ | |
1645 | igb_free_all_rx_resources(adapter); | |
1646 | err_setup_rx: | |
1647 | igb_free_all_tx_resources(adapter); | |
1648 | err_setup_tx: | |
1649 | igb_reset(adapter); | |
1650 | ||
1651 | return err; | |
1652 | } | |
1653 | ||
1654 | /** | |
1655 | * igb_close - Disables a network interface | |
1656 | * @netdev: network interface device structure | |
1657 | * | |
1658 | * Returns 0, this is not allowed to fail | |
1659 | * | |
1660 | * The close entry point is called when an interface is de-activated | |
1661 | * by the OS. The hardware is still under the driver's control, but | |
1662 | * needs to be disabled. A global MAC reset is issued to stop the | |
1663 | * hardware, and all transmit and receive resources are freed. | |
1664 | **/ | |
1665 | static int igb_close(struct net_device *netdev) | |
1666 | { | |
1667 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1668 | ||
1669 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
1670 | igb_down(adapter); | |
1671 | ||
1672 | igb_free_irq(adapter); | |
1673 | ||
1674 | igb_free_all_tx_resources(adapter); | |
1675 | igb_free_all_rx_resources(adapter); | |
1676 | ||
1677 | /* kill manageability vlan ID if supported, but not if a vlan with | |
1678 | * the same ID is registered on the host OS (let 8021q kill it) */ | |
1679 | if ((adapter->hw.mng_cookie.status & | |
1680 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
1681 | !(adapter->vlgrp && | |
1682 | vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) | |
1683 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | /** | |
1689 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
1690 | * @adapter: board private structure | |
1691 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
1692 | * | |
1693 | * Return 0 on success, negative on failure | |
1694 | **/ | |
9d5c8243 AK |
1695 | int igb_setup_tx_resources(struct igb_adapter *adapter, |
1696 | struct igb_ring *tx_ring) | |
1697 | { | |
1698 | struct pci_dev *pdev = adapter->pdev; | |
1699 | int size; | |
1700 | ||
1701 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
1702 | tx_ring->buffer_info = vmalloc(size); | |
1703 | if (!tx_ring->buffer_info) | |
1704 | goto err; | |
1705 | memset(tx_ring->buffer_info, 0, size); | |
1706 | ||
1707 | /* round up to nearest 4K */ | |
85e8d004 | 1708 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
1709 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1710 | ||
1711 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, | |
1712 | &tx_ring->dma); | |
1713 | ||
1714 | if (!tx_ring->desc) | |
1715 | goto err; | |
1716 | ||
1717 | tx_ring->adapter = adapter; | |
1718 | tx_ring->next_to_use = 0; | |
1719 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
1720 | return 0; |
1721 | ||
1722 | err: | |
1723 | vfree(tx_ring->buffer_info); | |
1724 | dev_err(&adapter->pdev->dev, | |
1725 | "Unable to allocate memory for the transmit descriptor ring\n"); | |
1726 | return -ENOMEM; | |
1727 | } | |
1728 | ||
1729 | /** | |
1730 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
1731 | * (Descriptors) for all queues | |
1732 | * @adapter: board private structure | |
1733 | * | |
1734 | * Return 0 on success, negative on failure | |
1735 | **/ | |
1736 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
1737 | { | |
1738 | int i, err = 0; | |
661086df | 1739 | int r_idx; |
9d5c8243 AK |
1740 | |
1741 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1742 | err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
1743 | if (err) { | |
1744 | dev_err(&adapter->pdev->dev, | |
1745 | "Allocation for Tx Queue %u failed\n", i); | |
1746 | for (i--; i >= 0; i--) | |
3b644cf6 | 1747 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
1748 | break; |
1749 | } | |
1750 | } | |
1751 | ||
661086df PWJ |
1752 | for (i = 0; i < IGB_MAX_TX_QUEUES; i++) { |
1753 | r_idx = i % adapter->num_tx_queues; | |
1754 | adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; | |
eebbbdba | 1755 | } |
9d5c8243 AK |
1756 | return err; |
1757 | } | |
1758 | ||
1759 | /** | |
1760 | * igb_configure_tx - Configure transmit Unit after Reset | |
1761 | * @adapter: board private structure | |
1762 | * | |
1763 | * Configure the Tx unit of the MAC after a reset. | |
1764 | **/ | |
1765 | static void igb_configure_tx(struct igb_adapter *adapter) | |
1766 | { | |
0e014cb1 | 1767 | u64 tdba; |
9d5c8243 AK |
1768 | struct e1000_hw *hw = &adapter->hw; |
1769 | u32 tctl; | |
1770 | u32 txdctl, txctrl; | |
26bc19ec | 1771 | int i, j; |
9d5c8243 AK |
1772 | |
1773 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
73cd78f1 | 1774 | struct igb_ring *ring = &adapter->tx_ring[i]; |
26bc19ec AD |
1775 | j = ring->reg_idx; |
1776 | wr32(E1000_TDLEN(j), | |
85e8d004 | 1777 | ring->count * sizeof(union e1000_adv_tx_desc)); |
9d5c8243 | 1778 | tdba = ring->dma; |
26bc19ec | 1779 | wr32(E1000_TDBAL(j), |
73cd78f1 | 1780 | tdba & 0x00000000ffffffffULL); |
26bc19ec | 1781 | wr32(E1000_TDBAH(j), tdba >> 32); |
9d5c8243 | 1782 | |
26bc19ec AD |
1783 | ring->head = E1000_TDH(j); |
1784 | ring->tail = E1000_TDT(j); | |
9d5c8243 AK |
1785 | writel(0, hw->hw_addr + ring->tail); |
1786 | writel(0, hw->hw_addr + ring->head); | |
26bc19ec | 1787 | txdctl = rd32(E1000_TXDCTL(j)); |
9d5c8243 | 1788 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; |
26bc19ec | 1789 | wr32(E1000_TXDCTL(j), txdctl); |
9d5c8243 AK |
1790 | |
1791 | /* Turn off Relaxed Ordering on head write-backs. The | |
1792 | * writebacks MUST be delivered in order or it will | |
1793 | * completely screw up our bookeeping. | |
1794 | */ | |
26bc19ec | 1795 | txctrl = rd32(E1000_DCA_TXCTRL(j)); |
9d5c8243 | 1796 | txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; |
26bc19ec | 1797 | wr32(E1000_DCA_TXCTRL(j), txctrl); |
9d5c8243 AK |
1798 | } |
1799 | ||
9d5c8243 AK |
1800 | /* Use the default values for the Tx Inter Packet Gap (IPG) timer */ |
1801 | ||
1802 | /* Program the Transmit Control Register */ | |
1803 | ||
1804 | tctl = rd32(E1000_TCTL); | |
1805 | tctl &= ~E1000_TCTL_CT; | |
1806 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
1807 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
1808 | ||
1809 | igb_config_collision_dist(hw); | |
1810 | ||
1811 | /* Setup Transmit Descriptor Settings for eop descriptor */ | |
1812 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS; | |
1813 | ||
1814 | /* Enable transmits */ | |
1815 | tctl |= E1000_TCTL_EN; | |
1816 | ||
1817 | wr32(E1000_TCTL, tctl); | |
1818 | } | |
1819 | ||
1820 | /** | |
1821 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
1822 | * @adapter: board private structure | |
1823 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1824 | * | |
1825 | * Returns 0 on success, negative on failure | |
1826 | **/ | |
9d5c8243 AK |
1827 | int igb_setup_rx_resources(struct igb_adapter *adapter, |
1828 | struct igb_ring *rx_ring) | |
1829 | { | |
1830 | struct pci_dev *pdev = adapter->pdev; | |
1831 | int size, desc_len; | |
1832 | ||
1833 | size = sizeof(struct igb_buffer) * rx_ring->count; | |
1834 | rx_ring->buffer_info = vmalloc(size); | |
1835 | if (!rx_ring->buffer_info) | |
1836 | goto err; | |
1837 | memset(rx_ring->buffer_info, 0, size); | |
1838 | ||
1839 | desc_len = sizeof(union e1000_adv_rx_desc); | |
1840 | ||
1841 | /* Round up to nearest 4K */ | |
1842 | rx_ring->size = rx_ring->count * desc_len; | |
1843 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
1844 | ||
1845 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, | |
1846 | &rx_ring->dma); | |
1847 | ||
1848 | if (!rx_ring->desc) | |
1849 | goto err; | |
1850 | ||
1851 | rx_ring->next_to_clean = 0; | |
1852 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
1853 | |
1854 | rx_ring->adapter = adapter; | |
9d5c8243 AK |
1855 | |
1856 | return 0; | |
1857 | ||
1858 | err: | |
1859 | vfree(rx_ring->buffer_info); | |
1860 | dev_err(&adapter->pdev->dev, "Unable to allocate memory for " | |
1861 | "the receive descriptor ring\n"); | |
1862 | return -ENOMEM; | |
1863 | } | |
1864 | ||
1865 | /** | |
1866 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
1867 | * (Descriptors) for all queues | |
1868 | * @adapter: board private structure | |
1869 | * | |
1870 | * Return 0 on success, negative on failure | |
1871 | **/ | |
1872 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
1873 | { | |
1874 | int i, err = 0; | |
1875 | ||
1876 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1877 | err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
1878 | if (err) { | |
1879 | dev_err(&adapter->pdev->dev, | |
1880 | "Allocation for Rx Queue %u failed\n", i); | |
1881 | for (i--; i >= 0; i--) | |
3b644cf6 | 1882 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
1883 | break; |
1884 | } | |
1885 | } | |
1886 | ||
1887 | return err; | |
1888 | } | |
1889 | ||
1890 | /** | |
1891 | * igb_setup_rctl - configure the receive control registers | |
1892 | * @adapter: Board private structure | |
1893 | **/ | |
1894 | static void igb_setup_rctl(struct igb_adapter *adapter) | |
1895 | { | |
1896 | struct e1000_hw *hw = &adapter->hw; | |
1897 | u32 rctl; | |
1898 | u32 srrctl = 0; | |
26bc19ec | 1899 | int i, j; |
9d5c8243 AK |
1900 | |
1901 | rctl = rd32(E1000_RCTL); | |
1902 | ||
1903 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 1904 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 1905 | |
69d728ba | 1906 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 1907 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 1908 | |
87cb7e8c AK |
1909 | /* |
1910 | * enable stripping of CRC. It's unlikely this will break BMC | |
1911 | * redirection as it did with e1000. Newer features require | |
1912 | * that the HW strips the CRC. | |
73cd78f1 | 1913 | */ |
87cb7e8c | 1914 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 1915 | |
9b07f3d3 | 1916 | /* |
ec54d7d6 | 1917 | * disable store bad packets and clear size bits. |
9b07f3d3 | 1918 | */ |
ec54d7d6 | 1919 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 1920 | |
ec54d7d6 | 1921 | /* enable LPE when to prevent packets larger than max_frame_size */ |
9b07f3d3 | 1922 | rctl |= E1000_RCTL_LPE; |
b4557be2 AD |
1923 | |
1924 | /* Setup buffer sizes */ | |
1925 | switch (adapter->rx_buffer_len) { | |
1926 | case IGB_RXBUFFER_256: | |
1927 | rctl |= E1000_RCTL_SZ_256; | |
1928 | break; | |
1929 | case IGB_RXBUFFER_512: | |
1930 | rctl |= E1000_RCTL_SZ_512; | |
1931 | break; | |
1932 | default: | |
1933 | srrctl = ALIGN(adapter->rx_buffer_len, 1024) | |
1934 | >> E1000_SRRCTL_BSIZEPKT_SHIFT; | |
1935 | break; | |
9d5c8243 AK |
1936 | } |
1937 | ||
1938 | /* 82575 and greater support packet-split where the protocol | |
1939 | * header is placed in skb->data and the packet data is | |
1940 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | |
1941 | * In the case of a non-split, skb->data is linearly filled, | |
1942 | * followed by the page buffers. Therefore, skb->data is | |
1943 | * sized to hold the largest protocol header. | |
1944 | */ | |
1945 | /* allocations using alloc_page take too long for regular MTU | |
1946 | * so only enable packet split for jumbo frames */ | |
ec54d7d6 | 1947 | if (adapter->netdev->mtu > ETH_DATA_LEN) { |
9d5c8243 | 1948 | adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; |
bf36c1a0 | 1949 | srrctl |= adapter->rx_ps_hdr_size << |
9d5c8243 | 1950 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
9d5c8243 AK |
1951 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
1952 | } else { | |
1953 | adapter->rx_ps_hdr_size = 0; | |
1954 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1955 | } | |
1956 | ||
26bc19ec AD |
1957 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1958 | j = adapter->rx_ring[i].reg_idx; | |
1959 | wr32(E1000_SRRCTL(j), srrctl); | |
1960 | } | |
9d5c8243 AK |
1961 | |
1962 | wr32(E1000_RCTL, rctl); | |
1963 | } | |
1964 | ||
1965 | /** | |
1966 | * igb_configure_rx - Configure receive Unit after Reset | |
1967 | * @adapter: board private structure | |
1968 | * | |
1969 | * Configure the Rx unit of the MAC after a reset. | |
1970 | **/ | |
1971 | static void igb_configure_rx(struct igb_adapter *adapter) | |
1972 | { | |
1973 | u64 rdba; | |
1974 | struct e1000_hw *hw = &adapter->hw; | |
1975 | u32 rctl, rxcsum; | |
1976 | u32 rxdctl; | |
9107584e | 1977 | int i; |
9d5c8243 AK |
1978 | |
1979 | /* disable receives while setting up the descriptors */ | |
1980 | rctl = rd32(E1000_RCTL); | |
1981 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1982 | wrfl(); | |
1983 | mdelay(10); | |
1984 | ||
1985 | if (adapter->itr_setting > 3) | |
6eb5a7f1 | 1986 | wr32(E1000_ITR, adapter->itr); |
9d5c8243 AK |
1987 | |
1988 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1989 | * the Base and Length of the Rx Descriptor Ring */ | |
1990 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
73cd78f1 | 1991 | struct igb_ring *ring = &adapter->rx_ring[i]; |
9107584e | 1992 | int j = ring->reg_idx; |
9d5c8243 | 1993 | rdba = ring->dma; |
26bc19ec | 1994 | wr32(E1000_RDBAL(j), |
73cd78f1 | 1995 | rdba & 0x00000000ffffffffULL); |
26bc19ec AD |
1996 | wr32(E1000_RDBAH(j), rdba >> 32); |
1997 | wr32(E1000_RDLEN(j), | |
73cd78f1 | 1998 | ring->count * sizeof(union e1000_adv_rx_desc)); |
9d5c8243 | 1999 | |
26bc19ec AD |
2000 | ring->head = E1000_RDH(j); |
2001 | ring->tail = E1000_RDT(j); | |
9d5c8243 AK |
2002 | writel(0, hw->hw_addr + ring->tail); |
2003 | writel(0, hw->hw_addr + ring->head); | |
2004 | ||
26bc19ec | 2005 | rxdctl = rd32(E1000_RXDCTL(j)); |
9d5c8243 AK |
2006 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; |
2007 | rxdctl &= 0xFFF00000; | |
2008 | rxdctl |= IGB_RX_PTHRESH; | |
2009 | rxdctl |= IGB_RX_HTHRESH << 8; | |
2010 | rxdctl |= IGB_RX_WTHRESH << 16; | |
26bc19ec | 2011 | wr32(E1000_RXDCTL(j), rxdctl); |
9d5c8243 AK |
2012 | } |
2013 | ||
2014 | if (adapter->num_rx_queues > 1) { | |
2015 | u32 random[10]; | |
2016 | u32 mrqc; | |
2017 | u32 j, shift; | |
2018 | union e1000_reta { | |
2019 | u32 dword; | |
2020 | u8 bytes[4]; | |
2021 | } reta; | |
2022 | ||
2023 | get_random_bytes(&random[0], 40); | |
2024 | ||
2d064c06 AD |
2025 | if (hw->mac.type >= e1000_82576) |
2026 | shift = 0; | |
2027 | else | |
2028 | shift = 6; | |
9d5c8243 AK |
2029 | for (j = 0; j < (32 * 4); j++) { |
2030 | reta.bytes[j & 3] = | |
26bc19ec | 2031 | adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift; |
9d5c8243 AK |
2032 | if ((j & 3) == 3) |
2033 | writel(reta.dword, | |
2034 | hw->hw_addr + E1000_RETA(0) + (j & ~3)); | |
2035 | } | |
1bfaf07b | 2036 | |
9d5c8243 AK |
2037 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; |
2038 | ||
2039 | /* Fill out hash function seeds */ | |
2040 | for (j = 0; j < 10; j++) | |
2041 | array_wr32(E1000_RSSRK(0), j, random[j]); | |
2042 | ||
2043 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | |
2044 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | |
2045 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | |
2046 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | |
2047 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | |
2048 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | |
2049 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | |
2050 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
2051 | ||
2052 | ||
2053 | wr32(E1000_MRQC, mrqc); | |
2054 | ||
2055 | /* Multiqueue and raw packet checksumming are mutually | |
2056 | * exclusive. Note that this not the same as TCP/IP | |
2057 | * checksumming, which works fine. */ | |
2058 | rxcsum = rd32(E1000_RXCSUM); | |
2059 | rxcsum |= E1000_RXCSUM_PCSD; | |
2060 | wr32(E1000_RXCSUM, rxcsum); | |
2061 | } else { | |
2062 | /* Enable Receive Checksum Offload for TCP and UDP */ | |
2063 | rxcsum = rd32(E1000_RXCSUM); | |
56fbbb4e AD |
2064 | if (adapter->rx_csum) |
2065 | rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE; | |
2066 | else | |
2067 | rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE); | |
2068 | ||
9d5c8243 AK |
2069 | wr32(E1000_RXCSUM, rxcsum); |
2070 | } | |
2071 | ||
2072 | if (adapter->vlgrp) | |
2073 | wr32(E1000_RLPML, | |
2074 | adapter->max_frame_size + VLAN_TAG_SIZE); | |
2075 | else | |
2076 | wr32(E1000_RLPML, adapter->max_frame_size); | |
2077 | ||
2078 | /* Enable Receives */ | |
2079 | wr32(E1000_RCTL, rctl); | |
2080 | } | |
2081 | ||
2082 | /** | |
2083 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
2084 | * @tx_ring: Tx descriptor ring for a specific queue |
2085 | * | |
2086 | * Free all transmit software resources | |
2087 | **/ | |
68fd9910 | 2088 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2089 | { |
3b644cf6 | 2090 | struct pci_dev *pdev = tx_ring->adapter->pdev; |
9d5c8243 | 2091 | |
3b644cf6 | 2092 | igb_clean_tx_ring(tx_ring); |
9d5c8243 AK |
2093 | |
2094 | vfree(tx_ring->buffer_info); | |
2095 | tx_ring->buffer_info = NULL; | |
2096 | ||
2097 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
2098 | ||
2099 | tx_ring->desc = NULL; | |
2100 | } | |
2101 | ||
2102 | /** | |
2103 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
2104 | * @adapter: board private structure | |
2105 | * | |
2106 | * Free all transmit software resources | |
2107 | **/ | |
2108 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
2109 | { | |
2110 | int i; | |
2111 | ||
2112 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2113 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
2114 | } |
2115 | ||
2116 | static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, | |
2117 | struct igb_buffer *buffer_info) | |
2118 | { | |
2119 | if (buffer_info->dma) { | |
2120 | pci_unmap_page(adapter->pdev, | |
2121 | buffer_info->dma, | |
2122 | buffer_info->length, | |
2123 | PCI_DMA_TODEVICE); | |
2124 | buffer_info->dma = 0; | |
2125 | } | |
2126 | if (buffer_info->skb) { | |
2127 | dev_kfree_skb_any(buffer_info->skb); | |
2128 | buffer_info->skb = NULL; | |
2129 | } | |
2130 | buffer_info->time_stamp = 0; | |
73cd78f1 | 2131 | buffer_info->next_to_watch = 0; |
9d5c8243 AK |
2132 | /* buffer_info must be completely set up in the transmit path */ |
2133 | } | |
2134 | ||
2135 | /** | |
2136 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
2137 | * @tx_ring: ring to be cleaned |
2138 | **/ | |
3b644cf6 | 2139 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 2140 | { |
3b644cf6 | 2141 | struct igb_adapter *adapter = tx_ring->adapter; |
9d5c8243 AK |
2142 | struct igb_buffer *buffer_info; |
2143 | unsigned long size; | |
2144 | unsigned int i; | |
2145 | ||
2146 | if (!tx_ring->buffer_info) | |
2147 | return; | |
2148 | /* Free all the Tx ring sk_buffs */ | |
2149 | ||
2150 | for (i = 0; i < tx_ring->count; i++) { | |
2151 | buffer_info = &tx_ring->buffer_info[i]; | |
2152 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
2153 | } | |
2154 | ||
2155 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2156 | memset(tx_ring->buffer_info, 0, size); | |
2157 | ||
2158 | /* Zero out the descriptor ring */ | |
2159 | ||
2160 | memset(tx_ring->desc, 0, tx_ring->size); | |
2161 | ||
2162 | tx_ring->next_to_use = 0; | |
2163 | tx_ring->next_to_clean = 0; | |
2164 | ||
2165 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2166 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2167 | } | |
2168 | ||
2169 | /** | |
2170 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
2171 | * @adapter: board private structure | |
2172 | **/ | |
2173 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
2174 | { | |
2175 | int i; | |
2176 | ||
2177 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2178 | igb_clean_tx_ring(&adapter->tx_ring[i]); |
9d5c8243 AK |
2179 | } |
2180 | ||
2181 | /** | |
2182 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
2183 | * @rx_ring: ring to clean the resources from |
2184 | * | |
2185 | * Free all receive software resources | |
2186 | **/ | |
68fd9910 | 2187 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2188 | { |
3b644cf6 | 2189 | struct pci_dev *pdev = rx_ring->adapter->pdev; |
9d5c8243 | 2190 | |
3b644cf6 | 2191 | igb_clean_rx_ring(rx_ring); |
9d5c8243 AK |
2192 | |
2193 | vfree(rx_ring->buffer_info); | |
2194 | rx_ring->buffer_info = NULL; | |
2195 | ||
2196 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
2197 | ||
2198 | rx_ring->desc = NULL; | |
2199 | } | |
2200 | ||
2201 | /** | |
2202 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
2203 | * @adapter: board private structure | |
2204 | * | |
2205 | * Free all receive software resources | |
2206 | **/ | |
2207 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
2208 | { | |
2209 | int i; | |
2210 | ||
2211 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2212 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
2213 | } |
2214 | ||
2215 | /** | |
2216 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
2217 | * @rx_ring: ring to free buffers from |
2218 | **/ | |
3b644cf6 | 2219 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 2220 | { |
3b644cf6 | 2221 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
2222 | struct igb_buffer *buffer_info; |
2223 | struct pci_dev *pdev = adapter->pdev; | |
2224 | unsigned long size; | |
2225 | unsigned int i; | |
2226 | ||
2227 | if (!rx_ring->buffer_info) | |
2228 | return; | |
2229 | /* Free all the Rx ring sk_buffs */ | |
2230 | for (i = 0; i < rx_ring->count; i++) { | |
2231 | buffer_info = &rx_ring->buffer_info[i]; | |
2232 | if (buffer_info->dma) { | |
2233 | if (adapter->rx_ps_hdr_size) | |
2234 | pci_unmap_single(pdev, buffer_info->dma, | |
2235 | adapter->rx_ps_hdr_size, | |
2236 | PCI_DMA_FROMDEVICE); | |
2237 | else | |
2238 | pci_unmap_single(pdev, buffer_info->dma, | |
2239 | adapter->rx_buffer_len, | |
2240 | PCI_DMA_FROMDEVICE); | |
2241 | buffer_info->dma = 0; | |
2242 | } | |
2243 | ||
2244 | if (buffer_info->skb) { | |
2245 | dev_kfree_skb(buffer_info->skb); | |
2246 | buffer_info->skb = NULL; | |
2247 | } | |
2248 | if (buffer_info->page) { | |
bf36c1a0 AD |
2249 | if (buffer_info->page_dma) |
2250 | pci_unmap_page(pdev, buffer_info->page_dma, | |
2251 | PAGE_SIZE / 2, | |
2252 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
2253 | put_page(buffer_info->page); |
2254 | buffer_info->page = NULL; | |
2255 | buffer_info->page_dma = 0; | |
bf36c1a0 | 2256 | buffer_info->page_offset = 0; |
9d5c8243 AK |
2257 | } |
2258 | } | |
2259 | ||
9d5c8243 AK |
2260 | size = sizeof(struct igb_buffer) * rx_ring->count; |
2261 | memset(rx_ring->buffer_info, 0, size); | |
2262 | ||
2263 | /* Zero out the descriptor ring */ | |
2264 | memset(rx_ring->desc, 0, rx_ring->size); | |
2265 | ||
2266 | rx_ring->next_to_clean = 0; | |
2267 | rx_ring->next_to_use = 0; | |
2268 | ||
2269 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2270 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2271 | } | |
2272 | ||
2273 | /** | |
2274 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
2275 | * @adapter: board private structure | |
2276 | **/ | |
2277 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
2278 | { | |
2279 | int i; | |
2280 | ||
2281 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2282 | igb_clean_rx_ring(&adapter->rx_ring[i]); |
9d5c8243 AK |
2283 | } |
2284 | ||
2285 | /** | |
2286 | * igb_set_mac - Change the Ethernet Address of the NIC | |
2287 | * @netdev: network interface device structure | |
2288 | * @p: pointer to an address structure | |
2289 | * | |
2290 | * Returns 0 on success, negative on failure | |
2291 | **/ | |
2292 | static int igb_set_mac(struct net_device *netdev, void *p) | |
2293 | { | |
2294 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 2295 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
2296 | struct sockaddr *addr = p; |
2297 | ||
2298 | if (!is_valid_ether_addr(addr->sa_data)) | |
2299 | return -EADDRNOTAVAIL; | |
2300 | ||
2301 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 2302 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 2303 | |
28b0759c | 2304 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
9d5c8243 AK |
2305 | |
2306 | return 0; | |
2307 | } | |
2308 | ||
2309 | /** | |
2310 | * igb_set_multi - Multicast and Promiscuous mode set | |
2311 | * @netdev: network interface device structure | |
2312 | * | |
2313 | * The set_multi entry point is called whenever the multicast address | |
2314 | * list or the network interface flags are updated. This routine is | |
2315 | * responsible for configuring the hardware for proper multicast, | |
2316 | * promiscuous mode, and all-multi behavior. | |
2317 | **/ | |
2318 | static void igb_set_multi(struct net_device *netdev) | |
2319 | { | |
2320 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2321 | struct e1000_hw *hw = &adapter->hw; | |
2322 | struct e1000_mac_info *mac = &hw->mac; | |
2323 | struct dev_mc_list *mc_ptr; | |
2324 | u8 *mta_list; | |
2325 | u32 rctl; | |
2326 | int i; | |
2327 | ||
2328 | /* Check for Promiscuous and All Multicast modes */ | |
2329 | ||
2330 | rctl = rd32(E1000_RCTL); | |
2331 | ||
746b9f02 | 2332 | if (netdev->flags & IFF_PROMISC) { |
9d5c8243 | 2333 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
746b9f02 PM |
2334 | rctl &= ~E1000_RCTL_VFE; |
2335 | } else { | |
2336 | if (netdev->flags & IFF_ALLMULTI) { | |
2337 | rctl |= E1000_RCTL_MPE; | |
2338 | rctl &= ~E1000_RCTL_UPE; | |
2339 | } else | |
2340 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | |
78ed11a5 | 2341 | rctl |= E1000_RCTL_VFE; |
746b9f02 | 2342 | } |
9d5c8243 AK |
2343 | wr32(E1000_RCTL, rctl); |
2344 | ||
2345 | if (!netdev->mc_count) { | |
2346 | /* nothing to program, so clear mc list */ | |
8a900862 AD |
2347 | igb_update_mc_addr_list(hw, NULL, 0, 1, |
2348 | mac->rar_entry_count); | |
9d5c8243 AK |
2349 | return; |
2350 | } | |
2351 | ||
2352 | mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); | |
2353 | if (!mta_list) | |
2354 | return; | |
2355 | ||
2356 | /* The shared function expects a packed array of only addresses. */ | |
2357 | mc_ptr = netdev->mc_list; | |
2358 | ||
2359 | for (i = 0; i < netdev->mc_count; i++) { | |
2360 | if (!mc_ptr) | |
2361 | break; | |
2362 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | |
2363 | mc_ptr = mc_ptr->next; | |
2364 | } | |
8a900862 | 2365 | igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count); |
9d5c8243 AK |
2366 | kfree(mta_list); |
2367 | } | |
2368 | ||
2369 | /* Need to wait a few seconds after link up to get diagnostic information from | |
2370 | * the phy */ | |
2371 | static void igb_update_phy_info(unsigned long data) | |
2372 | { | |
2373 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 2374 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
2375 | } |
2376 | ||
4d6b725e AD |
2377 | /** |
2378 | * igb_has_link - check shared code for link and determine up/down | |
2379 | * @adapter: pointer to driver private info | |
2380 | **/ | |
2381 | static bool igb_has_link(struct igb_adapter *adapter) | |
2382 | { | |
2383 | struct e1000_hw *hw = &adapter->hw; | |
2384 | bool link_active = false; | |
2385 | s32 ret_val = 0; | |
2386 | ||
2387 | /* get_link_status is set on LSC (link status) interrupt or | |
2388 | * rx sequence error interrupt. get_link_status will stay | |
2389 | * false until the e1000_check_for_link establishes link | |
2390 | * for copper adapters ONLY | |
2391 | */ | |
2392 | switch (hw->phy.media_type) { | |
2393 | case e1000_media_type_copper: | |
2394 | if (hw->mac.get_link_status) { | |
2395 | ret_val = hw->mac.ops.check_for_link(hw); | |
2396 | link_active = !hw->mac.get_link_status; | |
2397 | } else { | |
2398 | link_active = true; | |
2399 | } | |
2400 | break; | |
2401 | case e1000_media_type_fiber: | |
2402 | ret_val = hw->mac.ops.check_for_link(hw); | |
2403 | link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU); | |
2404 | break; | |
2405 | case e1000_media_type_internal_serdes: | |
2406 | ret_val = hw->mac.ops.check_for_link(hw); | |
2407 | link_active = hw->mac.serdes_has_link; | |
2408 | break; | |
2409 | default: | |
2410 | case e1000_media_type_unknown: | |
2411 | break; | |
2412 | } | |
2413 | ||
2414 | return link_active; | |
2415 | } | |
2416 | ||
9d5c8243 AK |
2417 | /** |
2418 | * igb_watchdog - Timer Call-back | |
2419 | * @data: pointer to adapter cast into an unsigned long | |
2420 | **/ | |
2421 | static void igb_watchdog(unsigned long data) | |
2422 | { | |
2423 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
2424 | /* Do the rest outside of interrupt context */ | |
2425 | schedule_work(&adapter->watchdog_task); | |
2426 | } | |
2427 | ||
2428 | static void igb_watchdog_task(struct work_struct *work) | |
2429 | { | |
2430 | struct igb_adapter *adapter = container_of(work, | |
2431 | struct igb_adapter, watchdog_task); | |
2432 | struct e1000_hw *hw = &adapter->hw; | |
9d5c8243 AK |
2433 | struct net_device *netdev = adapter->netdev; |
2434 | struct igb_ring *tx_ring = adapter->tx_ring; | |
9d5c8243 | 2435 | u32 link; |
7a6ea550 | 2436 | u32 eics = 0; |
7a6ea550 | 2437 | int i; |
9d5c8243 | 2438 | |
4d6b725e AD |
2439 | link = igb_has_link(adapter); |
2440 | if ((netif_carrier_ok(netdev)) && link) | |
9d5c8243 AK |
2441 | goto link_up; |
2442 | ||
9d5c8243 AK |
2443 | if (link) { |
2444 | if (!netif_carrier_ok(netdev)) { | |
2445 | u32 ctrl; | |
2446 | hw->mac.ops.get_speed_and_duplex(&adapter->hw, | |
2447 | &adapter->link_speed, | |
2448 | &adapter->link_duplex); | |
2449 | ||
2450 | ctrl = rd32(E1000_CTRL); | |
527d47c1 AD |
2451 | /* Links status message must follow this format */ |
2452 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | |
9d5c8243 | 2453 | "Flow Control: %s\n", |
527d47c1 | 2454 | netdev->name, |
9d5c8243 AK |
2455 | adapter->link_speed, |
2456 | adapter->link_duplex == FULL_DUPLEX ? | |
2457 | "Full Duplex" : "Half Duplex", | |
2458 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & | |
2459 | E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & | |
2460 | E1000_CTRL_RFCE) ? "RX" : ((ctrl & | |
2461 | E1000_CTRL_TFCE) ? "TX" : "None"))); | |
2462 | ||
2463 | /* tweak tx_queue_len according to speed/duplex and | |
2464 | * adjust the timeout factor */ | |
2465 | netdev->tx_queue_len = adapter->tx_queue_len; | |
2466 | adapter->tx_timeout_factor = 1; | |
2467 | switch (adapter->link_speed) { | |
2468 | case SPEED_10: | |
2469 | netdev->tx_queue_len = 10; | |
2470 | adapter->tx_timeout_factor = 14; | |
2471 | break; | |
2472 | case SPEED_100: | |
2473 | netdev->tx_queue_len = 100; | |
2474 | /* maybe add some timeout factor ? */ | |
2475 | break; | |
2476 | } | |
2477 | ||
2478 | netif_carrier_on(netdev); | |
fd2ea0a7 | 2479 | netif_tx_wake_all_queues(netdev); |
9d5c8243 | 2480 | |
4b1a9877 | 2481 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
2482 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2483 | mod_timer(&adapter->phy_info_timer, | |
2484 | round_jiffies(jiffies + 2 * HZ)); | |
2485 | } | |
2486 | } else { | |
2487 | if (netif_carrier_ok(netdev)) { | |
2488 | adapter->link_speed = 0; | |
2489 | adapter->link_duplex = 0; | |
527d47c1 AD |
2490 | /* Links status message must follow this format */ |
2491 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
2492 | netdev->name); | |
9d5c8243 | 2493 | netif_carrier_off(netdev); |
fd2ea0a7 | 2494 | netif_tx_stop_all_queues(netdev); |
4b1a9877 AD |
2495 | |
2496 | /* link state has changed, schedule phy info update */ | |
9d5c8243 AK |
2497 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2498 | mod_timer(&adapter->phy_info_timer, | |
2499 | round_jiffies(jiffies + 2 * HZ)); | |
2500 | } | |
2501 | } | |
2502 | ||
2503 | link_up: | |
2504 | igb_update_stats(adapter); | |
2505 | ||
4b1a9877 | 2506 | hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; |
9d5c8243 | 2507 | adapter->tpt_old = adapter->stats.tpt; |
4b1a9877 | 2508 | hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old; |
9d5c8243 AK |
2509 | adapter->colc_old = adapter->stats.colc; |
2510 | ||
2511 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; | |
2512 | adapter->gorc_old = adapter->stats.gorc; | |
2513 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | |
2514 | adapter->gotc_old = adapter->stats.gotc; | |
2515 | ||
2516 | igb_update_adaptive(&adapter->hw); | |
2517 | ||
2518 | if (!netif_carrier_ok(netdev)) { | |
2519 | if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) { | |
2520 | /* We've lost link, so the controller stops DMA, | |
2521 | * but we've got queued Tx work that's never going | |
2522 | * to get done, so reset controller to flush Tx. | |
2523 | * (Do the reset outside of interrupt context). */ | |
2524 | adapter->tx_timeout_count++; | |
2525 | schedule_work(&adapter->reset_task); | |
2526 | } | |
2527 | } | |
2528 | ||
2529 | /* Cause software interrupt to ensure rx ring is cleaned */ | |
7a6ea550 AD |
2530 | if (adapter->msix_entries) { |
2531 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2532 | eics |= adapter->rx_ring[i].eims_value; | |
2533 | wr32(E1000_EICS, eics); | |
2534 | } else { | |
2535 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
2536 | } | |
9d5c8243 AK |
2537 | |
2538 | /* Force detection of hung controller every watchdog period */ | |
2539 | tx_ring->detect_tx_hung = true; | |
2540 | ||
2541 | /* Reset the timer */ | |
2542 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
2543 | mod_timer(&adapter->watchdog_timer, | |
2544 | round_jiffies(jiffies + 2 * HZ)); | |
2545 | } | |
2546 | ||
2547 | enum latency_range { | |
2548 | lowest_latency = 0, | |
2549 | low_latency = 1, | |
2550 | bulk_latency = 2, | |
2551 | latency_invalid = 255 | |
2552 | }; | |
2553 | ||
2554 | ||
6eb5a7f1 AD |
2555 | /** |
2556 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
2557 | * | |
2558 | * Stores a new ITR value based on strictly on packet size. This | |
2559 | * algorithm is less sophisticated than that used in igb_update_itr, | |
2560 | * due to the difficulty of synchronizing statistics across multiple | |
2561 | * receive rings. The divisors and thresholds used by this fuction | |
2562 | * were determined based on theoretical maximum wire speed and testing | |
2563 | * data, in order to minimize response time while increasing bulk | |
2564 | * throughput. | |
2565 | * This functionality is controlled by the InterruptThrottleRate module | |
2566 | * parameter (see igb_param.c) | |
2567 | * NOTE: This function is called only when operating in a multiqueue | |
2568 | * receive environment. | |
2569 | * @rx_ring: pointer to ring | |
2570 | **/ | |
2571 | static void igb_update_ring_itr(struct igb_ring *rx_ring) | |
9d5c8243 | 2572 | { |
6eb5a7f1 AD |
2573 | int new_val = rx_ring->itr_val; |
2574 | int avg_wire_size = 0; | |
2575 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 2576 | |
6eb5a7f1 AD |
2577 | if (!rx_ring->total_packets) |
2578 | goto clear_counts; /* no packets, so don't do anything */ | |
9d5c8243 | 2579 | |
6eb5a7f1 AD |
2580 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
2581 | * ints/sec - ITR timer value of 120 ticks. | |
2582 | */ | |
2583 | if (adapter->link_speed != SPEED_1000) { | |
2584 | new_val = 120; | |
2585 | goto set_itr_val; | |
9d5c8243 | 2586 | } |
6eb5a7f1 | 2587 | avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets; |
9d5c8243 | 2588 | |
6eb5a7f1 AD |
2589 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
2590 | avg_wire_size += 24; | |
2591 | ||
2592 | /* Don't starve jumbo frames */ | |
2593 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 2594 | |
6eb5a7f1 AD |
2595 | /* Give a little boost to mid-size frames */ |
2596 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
2597 | new_val = avg_wire_size / 3; | |
2598 | else | |
2599 | new_val = avg_wire_size / 2; | |
9d5c8243 | 2600 | |
6eb5a7f1 | 2601 | set_itr_val: |
9d5c8243 AK |
2602 | if (new_val != rx_ring->itr_val) { |
2603 | rx_ring->itr_val = new_val; | |
6eb5a7f1 | 2604 | rx_ring->set_itr = 1; |
9d5c8243 | 2605 | } |
6eb5a7f1 AD |
2606 | clear_counts: |
2607 | rx_ring->total_bytes = 0; | |
2608 | rx_ring->total_packets = 0; | |
9d5c8243 AK |
2609 | } |
2610 | ||
2611 | /** | |
2612 | * igb_update_itr - update the dynamic ITR value based on statistics | |
2613 | * Stores a new ITR value based on packets and byte | |
2614 | * counts during the last interrupt. The advantage of per interrupt | |
2615 | * computation is faster updates and more accurate ITR for the current | |
2616 | * traffic pattern. Constants in this function were computed | |
2617 | * based on theoretical maximum wire speed and thresholds were set based | |
2618 | * on testing data as well as attempting to minimize response time | |
2619 | * while increasing bulk throughput. | |
2620 | * this functionality is controlled by the InterruptThrottleRate module | |
2621 | * parameter (see igb_param.c) | |
2622 | * NOTE: These calculations are only valid when operating in a single- | |
2623 | * queue environment. | |
2624 | * @adapter: pointer to adapter | |
2625 | * @itr_setting: current adapter->itr | |
2626 | * @packets: the number of packets during this measurement interval | |
2627 | * @bytes: the number of bytes during this measurement interval | |
2628 | **/ | |
2629 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
2630 | int packets, int bytes) | |
2631 | { | |
2632 | unsigned int retval = itr_setting; | |
2633 | ||
2634 | if (packets == 0) | |
2635 | goto update_itr_done; | |
2636 | ||
2637 | switch (itr_setting) { | |
2638 | case lowest_latency: | |
2639 | /* handle TSO and jumbo frames */ | |
2640 | if (bytes/packets > 8000) | |
2641 | retval = bulk_latency; | |
2642 | else if ((packets < 5) && (bytes > 512)) | |
2643 | retval = low_latency; | |
2644 | break; | |
2645 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
2646 | if (bytes > 10000) { | |
2647 | /* this if handles the TSO accounting */ | |
2648 | if (bytes/packets > 8000) { | |
2649 | retval = bulk_latency; | |
2650 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
2651 | retval = bulk_latency; | |
2652 | } else if ((packets > 35)) { | |
2653 | retval = lowest_latency; | |
2654 | } | |
2655 | } else if (bytes/packets > 2000) { | |
2656 | retval = bulk_latency; | |
2657 | } else if (packets <= 2 && bytes < 512) { | |
2658 | retval = lowest_latency; | |
2659 | } | |
2660 | break; | |
2661 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
2662 | if (bytes > 25000) { | |
2663 | if (packets > 35) | |
2664 | retval = low_latency; | |
1e5c3d21 | 2665 | } else if (bytes < 1500) { |
9d5c8243 AK |
2666 | retval = low_latency; |
2667 | } | |
2668 | break; | |
2669 | } | |
2670 | ||
2671 | update_itr_done: | |
2672 | return retval; | |
2673 | } | |
2674 | ||
6eb5a7f1 | 2675 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 AK |
2676 | { |
2677 | u16 current_itr; | |
2678 | u32 new_itr = adapter->itr; | |
2679 | ||
2680 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
2681 | if (adapter->link_speed != SPEED_1000) { | |
2682 | current_itr = 0; | |
2683 | new_itr = 4000; | |
2684 | goto set_itr_now; | |
2685 | } | |
2686 | ||
2687 | adapter->rx_itr = igb_update_itr(adapter, | |
2688 | adapter->rx_itr, | |
2689 | adapter->rx_ring->total_packets, | |
2690 | adapter->rx_ring->total_bytes); | |
9d5c8243 | 2691 | |
6eb5a7f1 | 2692 | if (adapter->rx_ring->buddy) { |
9d5c8243 AK |
2693 | adapter->tx_itr = igb_update_itr(adapter, |
2694 | adapter->tx_itr, | |
2695 | adapter->tx_ring->total_packets, | |
2696 | adapter->tx_ring->total_bytes); | |
9d5c8243 AK |
2697 | current_itr = max(adapter->rx_itr, adapter->tx_itr); |
2698 | } else { | |
2699 | current_itr = adapter->rx_itr; | |
2700 | } | |
2701 | ||
6eb5a7f1 | 2702 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
73cd78f1 | 2703 | if (adapter->itr_setting == 3 && current_itr == lowest_latency) |
6eb5a7f1 AD |
2704 | current_itr = low_latency; |
2705 | ||
9d5c8243 AK |
2706 | switch (current_itr) { |
2707 | /* counts and packets in update_itr are dependent on these numbers */ | |
2708 | case lowest_latency: | |
2709 | new_itr = 70000; | |
2710 | break; | |
2711 | case low_latency: | |
2712 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2713 | break; | |
2714 | case bulk_latency: | |
2715 | new_itr = 4000; | |
2716 | break; | |
2717 | default: | |
2718 | break; | |
2719 | } | |
2720 | ||
2721 | set_itr_now: | |
6eb5a7f1 AD |
2722 | adapter->rx_ring->total_bytes = 0; |
2723 | adapter->rx_ring->total_packets = 0; | |
2724 | if (adapter->rx_ring->buddy) { | |
2725 | adapter->rx_ring->buddy->total_bytes = 0; | |
2726 | adapter->rx_ring->buddy->total_packets = 0; | |
2727 | } | |
2728 | ||
9d5c8243 AK |
2729 | if (new_itr != adapter->itr) { |
2730 | /* this attempts to bias the interrupt rate towards Bulk | |
2731 | * by adding intermediate steps when interrupt rate is | |
2732 | * increasing */ | |
2733 | new_itr = new_itr > adapter->itr ? | |
2734 | min(adapter->itr + (new_itr >> 2), new_itr) : | |
2735 | new_itr; | |
2736 | /* Don't write the value here; it resets the adapter's | |
2737 | * internal timer, and causes us to delay far longer than | |
2738 | * we should between interrupts. Instead, we write the ITR | |
2739 | * value at the beginning of the next interrupt so the timing | |
2740 | * ends up being correct. | |
2741 | */ | |
2742 | adapter->itr = new_itr; | |
6eb5a7f1 AD |
2743 | adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256); |
2744 | adapter->rx_ring->set_itr = 1; | |
9d5c8243 AK |
2745 | } |
2746 | ||
2747 | return; | |
2748 | } | |
2749 | ||
2750 | ||
2751 | #define IGB_TX_FLAGS_CSUM 0x00000001 | |
2752 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
2753 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
2754 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
33af6bcc | 2755 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 |
9d5c8243 AK |
2756 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
2757 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
2758 | ||
2759 | static inline int igb_tso_adv(struct igb_adapter *adapter, | |
2760 | struct igb_ring *tx_ring, | |
2761 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) | |
2762 | { | |
2763 | struct e1000_adv_tx_context_desc *context_desc; | |
2764 | unsigned int i; | |
2765 | int err; | |
2766 | struct igb_buffer *buffer_info; | |
2767 | u32 info = 0, tu_cmd = 0; | |
2768 | u32 mss_l4len_idx, l4len; | |
2769 | *hdr_len = 0; | |
2770 | ||
2771 | if (skb_header_cloned(skb)) { | |
2772 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2773 | if (err) | |
2774 | return err; | |
2775 | } | |
2776 | ||
2777 | l4len = tcp_hdrlen(skb); | |
2778 | *hdr_len += l4len; | |
2779 | ||
2780 | if (skb->protocol == htons(ETH_P_IP)) { | |
2781 | struct iphdr *iph = ip_hdr(skb); | |
2782 | iph->tot_len = 0; | |
2783 | iph->check = 0; | |
2784 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
2785 | iph->daddr, 0, | |
2786 | IPPROTO_TCP, | |
2787 | 0); | |
2788 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
2789 | ipv6_hdr(skb)->payload_len = 0; | |
2790 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
2791 | &ipv6_hdr(skb)->daddr, | |
2792 | 0, IPPROTO_TCP, 0); | |
2793 | } | |
2794 | ||
2795 | i = tx_ring->next_to_use; | |
2796 | ||
2797 | buffer_info = &tx_ring->buffer_info[i]; | |
2798 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2799 | /* VLAN MACLEN IPLEN */ | |
2800 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2801 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2802 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2803 | *hdr_len += skb_network_offset(skb); | |
2804 | info |= skb_network_header_len(skb); | |
2805 | *hdr_len += skb_network_header_len(skb); | |
2806 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2807 | ||
2808 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
2809 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2810 | ||
2811 | if (skb->protocol == htons(ETH_P_IP)) | |
2812 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; | |
2813 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2814 | ||
2815 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2816 | ||
2817 | /* MSS L4LEN IDX */ | |
2818 | mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); | |
2819 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | |
2820 | ||
73cd78f1 | 2821 | /* For 82575, context index must be unique per ring. */ |
7dfc16fa AD |
2822 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
2823 | mss_l4len_idx |= tx_ring->queue_index << 4; | |
9d5c8243 AK |
2824 | |
2825 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
2826 | context_desc->seqnum_seed = 0; | |
2827 | ||
2828 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2829 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2830 | buffer_info->dma = 0; |
2831 | i++; | |
2832 | if (i == tx_ring->count) | |
2833 | i = 0; | |
2834 | ||
2835 | tx_ring->next_to_use = i; | |
2836 | ||
2837 | return true; | |
2838 | } | |
2839 | ||
2840 | static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |
2841 | struct igb_ring *tx_ring, | |
2842 | struct sk_buff *skb, u32 tx_flags) | |
2843 | { | |
2844 | struct e1000_adv_tx_context_desc *context_desc; | |
2845 | unsigned int i; | |
2846 | struct igb_buffer *buffer_info; | |
2847 | u32 info = 0, tu_cmd = 0; | |
2848 | ||
2849 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | |
2850 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | |
2851 | i = tx_ring->next_to_use; | |
2852 | buffer_info = &tx_ring->buffer_info[i]; | |
2853 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2854 | ||
2855 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2856 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2857 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2858 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
2859 | info |= skb_network_header_len(skb); | |
2860 | ||
2861 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2862 | ||
2863 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2864 | ||
2865 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
44b0cda3 | 2866 | switch (skb->protocol) { |
09640e63 | 2867 | case cpu_to_be16(ETH_P_IP): |
9d5c8243 | 2868 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; |
44b0cda3 MW |
2869 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
2870 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2871 | break; | |
09640e63 | 2872 | case cpu_to_be16(ETH_P_IPV6): |
44b0cda3 MW |
2873 | /* XXX what about other V6 headers?? */ |
2874 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
2875 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2876 | break; | |
2877 | default: | |
2878 | if (unlikely(net_ratelimit())) | |
2879 | dev_warn(&adapter->pdev->dev, | |
2880 | "partial checksum but proto=%x!\n", | |
2881 | skb->protocol); | |
2882 | break; | |
2883 | } | |
9d5c8243 AK |
2884 | } |
2885 | ||
2886 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2887 | context_desc->seqnum_seed = 0; | |
7dfc16fa AD |
2888 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
2889 | context_desc->mss_l4len_idx = | |
2890 | cpu_to_le32(tx_ring->queue_index << 4); | |
265de409 AD |
2891 | else |
2892 | context_desc->mss_l4len_idx = 0; | |
9d5c8243 AK |
2893 | |
2894 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2895 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2896 | buffer_info->dma = 0; |
2897 | ||
2898 | i++; | |
2899 | if (i == tx_ring->count) | |
2900 | i = 0; | |
2901 | tx_ring->next_to_use = i; | |
2902 | ||
2903 | return true; | |
2904 | } | |
9d5c8243 AK |
2905 | return false; |
2906 | } | |
2907 | ||
2908 | #define IGB_MAX_TXD_PWR 16 | |
2909 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | |
2910 | ||
2911 | static inline int igb_tx_map_adv(struct igb_adapter *adapter, | |
0e014cb1 AD |
2912 | struct igb_ring *tx_ring, struct sk_buff *skb, |
2913 | unsigned int first) | |
9d5c8243 AK |
2914 | { |
2915 | struct igb_buffer *buffer_info; | |
2916 | unsigned int len = skb_headlen(skb); | |
2917 | unsigned int count = 0, i; | |
2918 | unsigned int f; | |
2919 | ||
2920 | i = tx_ring->next_to_use; | |
2921 | ||
2922 | buffer_info = &tx_ring->buffer_info[i]; | |
2923 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
2924 | buffer_info->length = len; | |
2925 | /* set time_stamp *before* dma to help avoid a possible race */ | |
2926 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2927 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2928 | buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len, |
2929 | PCI_DMA_TODEVICE); | |
2930 | count++; | |
2931 | i++; | |
2932 | if (i == tx_ring->count) | |
2933 | i = 0; | |
2934 | ||
2935 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
2936 | struct skb_frag_struct *frag; | |
2937 | ||
2938 | frag = &skb_shinfo(skb)->frags[f]; | |
2939 | len = frag->size; | |
2940 | ||
2941 | buffer_info = &tx_ring->buffer_info[i]; | |
2942 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
2943 | buffer_info->length = len; | |
2944 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2945 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2946 | buffer_info->dma = pci_map_page(adapter->pdev, |
2947 | frag->page, | |
2948 | frag->page_offset, | |
2949 | len, | |
2950 | PCI_DMA_TODEVICE); | |
2951 | ||
2952 | count++; | |
2953 | i++; | |
2954 | if (i == tx_ring->count) | |
2955 | i = 0; | |
2956 | } | |
2957 | ||
0e014cb1 | 2958 | i = ((i == 0) ? tx_ring->count - 1 : i - 1); |
9d5c8243 | 2959 | tx_ring->buffer_info[i].skb = skb; |
0e014cb1 | 2960 | tx_ring->buffer_info[first].next_to_watch = i; |
9d5c8243 AK |
2961 | |
2962 | return count; | |
2963 | } | |
2964 | ||
2965 | static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | |
2966 | struct igb_ring *tx_ring, | |
2967 | int tx_flags, int count, u32 paylen, | |
2968 | u8 hdr_len) | |
2969 | { | |
2970 | union e1000_adv_tx_desc *tx_desc = NULL; | |
2971 | struct igb_buffer *buffer_info; | |
2972 | u32 olinfo_status = 0, cmd_type_len; | |
2973 | unsigned int i; | |
2974 | ||
2975 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | |
2976 | E1000_ADVTXD_DCMD_DEXT); | |
2977 | ||
2978 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2979 | cmd_type_len |= E1000_ADVTXD_DCMD_VLE; | |
2980 | ||
33af6bcc PO |
2981 | if (tx_flags & IGB_TX_FLAGS_TSTAMP) |
2982 | cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP; | |
2983 | ||
9d5c8243 AK |
2984 | if (tx_flags & IGB_TX_FLAGS_TSO) { |
2985 | cmd_type_len |= E1000_ADVTXD_DCMD_TSE; | |
2986 | ||
2987 | /* insert tcp checksum */ | |
2988 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
2989 | ||
2990 | /* insert ip checksum */ | |
2991 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
2992 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
2993 | ||
2994 | } else if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
2995 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
2996 | } | |
2997 | ||
7dfc16fa AD |
2998 | if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) && |
2999 | (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | | |
3000 | IGB_TX_FLAGS_VLAN))) | |
661086df | 3001 | olinfo_status |= tx_ring->queue_index << 4; |
9d5c8243 AK |
3002 | |
3003 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | |
3004 | ||
3005 | i = tx_ring->next_to_use; | |
3006 | while (count--) { | |
3007 | buffer_info = &tx_ring->buffer_info[i]; | |
3008 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
3009 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
3010 | tx_desc->read.cmd_type_len = | |
3011 | cpu_to_le32(cmd_type_len | buffer_info->length); | |
3012 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
3013 | i++; | |
3014 | if (i == tx_ring->count) | |
3015 | i = 0; | |
3016 | } | |
3017 | ||
3018 | tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd); | |
3019 | /* Force memory writes to complete before letting h/w | |
3020 | * know there are new descriptors to fetch. (Only | |
3021 | * applicable for weak-ordered memory model archs, | |
3022 | * such as IA-64). */ | |
3023 | wmb(); | |
3024 | ||
3025 | tx_ring->next_to_use = i; | |
3026 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
3027 | /* we need this if more than one processor can write to our tail | |
3028 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
3029 | mmiowb(); | |
3030 | } | |
3031 | ||
3032 | static int __igb_maybe_stop_tx(struct net_device *netdev, | |
3033 | struct igb_ring *tx_ring, int size) | |
3034 | { | |
3035 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3036 | ||
661086df | 3037 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 3038 | |
9d5c8243 AK |
3039 | /* Herbert's original patch had: |
3040 | * smp_mb__after_netif_stop_queue(); | |
3041 | * but since that doesn't exist yet, just open code it. */ | |
3042 | smp_mb(); | |
3043 | ||
3044 | /* We need to check again in a case another CPU has just | |
3045 | * made room available. */ | |
3046 | if (IGB_DESC_UNUSED(tx_ring) < size) | |
3047 | return -EBUSY; | |
3048 | ||
3049 | /* A reprieve! */ | |
661086df | 3050 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
3051 | ++adapter->restart_queue; |
3052 | return 0; | |
3053 | } | |
3054 | ||
3055 | static int igb_maybe_stop_tx(struct net_device *netdev, | |
3056 | struct igb_ring *tx_ring, int size) | |
3057 | { | |
3058 | if (IGB_DESC_UNUSED(tx_ring) >= size) | |
3059 | return 0; | |
3060 | return __igb_maybe_stop_tx(netdev, tx_ring, size); | |
3061 | } | |
3062 | ||
9d5c8243 AK |
3063 | static int igb_xmit_frame_ring_adv(struct sk_buff *skb, |
3064 | struct net_device *netdev, | |
3065 | struct igb_ring *tx_ring) | |
3066 | { | |
3067 | struct igb_adapter *adapter = netdev_priv(netdev); | |
0e014cb1 | 3068 | unsigned int first; |
9d5c8243 | 3069 | unsigned int tx_flags = 0; |
9d5c8243 AK |
3070 | u8 hdr_len = 0; |
3071 | int tso = 0; | |
33af6bcc | 3072 | union skb_shared_tx *shtx; |
9d5c8243 | 3073 | |
9d5c8243 AK |
3074 | if (test_bit(__IGB_DOWN, &adapter->state)) { |
3075 | dev_kfree_skb_any(skb); | |
3076 | return NETDEV_TX_OK; | |
3077 | } | |
3078 | ||
3079 | if (skb->len <= 0) { | |
3080 | dev_kfree_skb_any(skb); | |
3081 | return NETDEV_TX_OK; | |
3082 | } | |
3083 | ||
9d5c8243 AK |
3084 | /* need: 1 descriptor per page, |
3085 | * + 2 desc gap to keep tail from touching head, | |
3086 | * + 1 desc for skb->data, | |
3087 | * + 1 desc for context descriptor, | |
3088 | * otherwise try next time */ | |
3089 | if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { | |
3090 | /* this is a hard error */ | |
9d5c8243 AK |
3091 | return NETDEV_TX_BUSY; |
3092 | } | |
33af6bcc PO |
3093 | |
3094 | /* | |
3095 | * TODO: check that there currently is no other packet with | |
3096 | * time stamping in the queue | |
3097 | * | |
3098 | * When doing time stamping, keep the connection to the socket | |
3099 | * a while longer: it is still needed by skb_hwtstamp_tx(), | |
3100 | * called either in igb_tx_hwtstamp() or by our caller when | |
3101 | * doing software time stamping. | |
3102 | */ | |
3103 | shtx = skb_tx(skb); | |
3104 | if (unlikely(shtx->hardware)) { | |
3105 | shtx->in_progress = 1; | |
3106 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
3107 | } else if (likely(!shtx->software)) { | |
3108 | /* | |
3109 | * TODO: can this be solved in dev.c:dev_hard_start_xmit()? | |
3110 | * There are probably unmodified driver which do something | |
3111 | * like this and thus don't work in combination with | |
3112 | * SOF_TIMESTAMPING_TX_SOFTWARE. | |
3113 | */ | |
3114 | skb_orphan(skb); | |
3115 | } | |
9d5c8243 AK |
3116 | |
3117 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | |
3118 | tx_flags |= IGB_TX_FLAGS_VLAN; | |
3119 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
3120 | } | |
3121 | ||
661086df PWJ |
3122 | if (skb->protocol == htons(ETH_P_IP)) |
3123 | tx_flags |= IGB_TX_FLAGS_IPV4; | |
3124 | ||
0e014cb1 | 3125 | first = tx_ring->next_to_use; |
9d5c8243 AK |
3126 | tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, |
3127 | &hdr_len) : 0; | |
3128 | ||
3129 | if (tso < 0) { | |
3130 | dev_kfree_skb_any(skb); | |
9d5c8243 AK |
3131 | return NETDEV_TX_OK; |
3132 | } | |
3133 | ||
3134 | if (tso) | |
3135 | tx_flags |= IGB_TX_FLAGS_TSO; | |
bc1cbd34 AD |
3136 | else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) && |
3137 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
3138 | tx_flags |= IGB_TX_FLAGS_CSUM; | |
9d5c8243 | 3139 | |
9d5c8243 | 3140 | igb_tx_queue_adv(adapter, tx_ring, tx_flags, |
0e014cb1 | 3141 | igb_tx_map_adv(adapter, tx_ring, skb, first), |
9d5c8243 AK |
3142 | skb->len, hdr_len); |
3143 | ||
3144 | netdev->trans_start = jiffies; | |
3145 | ||
3146 | /* Make sure there is space in the ring for the next send. */ | |
3147 | igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); | |
3148 | ||
9d5c8243 AK |
3149 | return NETDEV_TX_OK; |
3150 | } | |
3151 | ||
3152 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev) | |
3153 | { | |
3154 | struct igb_adapter *adapter = netdev_priv(netdev); | |
661086df PWJ |
3155 | struct igb_ring *tx_ring; |
3156 | ||
661086df | 3157 | int r_idx = 0; |
1bfaf07b | 3158 | r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); |
661086df | 3159 | tx_ring = adapter->multi_tx_table[r_idx]; |
9d5c8243 AK |
3160 | |
3161 | /* This goes back to the question of how to logically map a tx queue | |
3162 | * to a flow. Right now, performance is impacted slightly negatively | |
3163 | * if using multiple tx queues. If the stack breaks away from a | |
3164 | * single qdisc implementation, we can look at this again. */ | |
3165 | return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring)); | |
3166 | } | |
3167 | ||
3168 | /** | |
3169 | * igb_tx_timeout - Respond to a Tx Hang | |
3170 | * @netdev: network interface device structure | |
3171 | **/ | |
3172 | static void igb_tx_timeout(struct net_device *netdev) | |
3173 | { | |
3174 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3175 | struct e1000_hw *hw = &adapter->hw; | |
3176 | ||
3177 | /* Do the reset outside of interrupt context */ | |
3178 | adapter->tx_timeout_count++; | |
3179 | schedule_work(&adapter->reset_task); | |
265de409 AD |
3180 | wr32(E1000_EICS, |
3181 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
3182 | } |
3183 | ||
3184 | static void igb_reset_task(struct work_struct *work) | |
3185 | { | |
3186 | struct igb_adapter *adapter; | |
3187 | adapter = container_of(work, struct igb_adapter, reset_task); | |
3188 | ||
3189 | igb_reinit_locked(adapter); | |
3190 | } | |
3191 | ||
3192 | /** | |
3193 | * igb_get_stats - Get System Network Statistics | |
3194 | * @netdev: network interface device structure | |
3195 | * | |
3196 | * Returns the address of the device statistics structure. | |
3197 | * The statistics are actually updated from the timer callback. | |
3198 | **/ | |
73cd78f1 | 3199 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) |
9d5c8243 AK |
3200 | { |
3201 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3202 | ||
3203 | /* only return the current stats */ | |
3204 | return &adapter->net_stats; | |
3205 | } | |
3206 | ||
3207 | /** | |
3208 | * igb_change_mtu - Change the Maximum Transfer Unit | |
3209 | * @netdev: network interface device structure | |
3210 | * @new_mtu: new value for maximum frame size | |
3211 | * | |
3212 | * Returns 0 on success, negative on failure | |
3213 | **/ | |
3214 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
3215 | { | |
3216 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3217 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3218 | ||
3219 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | |
3220 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | |
3221 | dev_err(&adapter->pdev->dev, "Invalid MTU setting\n"); | |
3222 | return -EINVAL; | |
3223 | } | |
3224 | ||
3225 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 | |
3226 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { | |
3227 | dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n"); | |
3228 | return -EINVAL; | |
3229 | } | |
3230 | ||
3231 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
3232 | msleep(1); | |
73cd78f1 | 3233 | |
9d5c8243 AK |
3234 | /* igb_down has a dependency on max_frame_size */ |
3235 | adapter->max_frame_size = max_frame; | |
3236 | if (netif_running(netdev)) | |
3237 | igb_down(adapter); | |
3238 | ||
3239 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN | |
3240 | * means we reserve 2 more, this pushes us to allocate from the next | |
3241 | * larger slab size. | |
3242 | * i.e. RXBUFFER_2048 --> size-4096 slab | |
3243 | */ | |
3244 | ||
3245 | if (max_frame <= IGB_RXBUFFER_256) | |
3246 | adapter->rx_buffer_len = IGB_RXBUFFER_256; | |
3247 | else if (max_frame <= IGB_RXBUFFER_512) | |
3248 | adapter->rx_buffer_len = IGB_RXBUFFER_512; | |
3249 | else if (max_frame <= IGB_RXBUFFER_1024) | |
3250 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | |
3251 | else if (max_frame <= IGB_RXBUFFER_2048) | |
3252 | adapter->rx_buffer_len = IGB_RXBUFFER_2048; | |
3253 | else | |
bf36c1a0 AD |
3254 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 |
3255 | adapter->rx_buffer_len = IGB_RXBUFFER_16384; | |
3256 | #else | |
3257 | adapter->rx_buffer_len = PAGE_SIZE / 2; | |
3258 | #endif | |
9d5c8243 AK |
3259 | /* adjust allocation if LPE protects us, and we aren't using SBP */ |
3260 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || | |
3261 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) | |
3262 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
3263 | ||
3264 | dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n", | |
3265 | netdev->mtu, new_mtu); | |
3266 | netdev->mtu = new_mtu; | |
3267 | ||
3268 | if (netif_running(netdev)) | |
3269 | igb_up(adapter); | |
3270 | else | |
3271 | igb_reset(adapter); | |
3272 | ||
3273 | clear_bit(__IGB_RESETTING, &adapter->state); | |
3274 | ||
3275 | return 0; | |
3276 | } | |
3277 | ||
3278 | /** | |
3279 | * igb_update_stats - Update the board statistics counters | |
3280 | * @adapter: board private structure | |
3281 | **/ | |
3282 | ||
3283 | void igb_update_stats(struct igb_adapter *adapter) | |
3284 | { | |
3285 | struct e1000_hw *hw = &adapter->hw; | |
3286 | struct pci_dev *pdev = adapter->pdev; | |
3287 | u16 phy_tmp; | |
3288 | ||
3289 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
3290 | ||
3291 | /* | |
3292 | * Prevent stats update while adapter is being reset, or if the pci | |
3293 | * connection is down. | |
3294 | */ | |
3295 | if (adapter->link_speed == 0) | |
3296 | return; | |
3297 | if (pci_channel_offline(pdev)) | |
3298 | return; | |
3299 | ||
3300 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); | |
3301 | adapter->stats.gprc += rd32(E1000_GPRC); | |
3302 | adapter->stats.gorc += rd32(E1000_GORCL); | |
3303 | rd32(E1000_GORCH); /* clear GORCL */ | |
3304 | adapter->stats.bprc += rd32(E1000_BPRC); | |
3305 | adapter->stats.mprc += rd32(E1000_MPRC); | |
3306 | adapter->stats.roc += rd32(E1000_ROC); | |
3307 | ||
3308 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
3309 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
3310 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
3311 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
3312 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
3313 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
3314 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
3315 | adapter->stats.sec += rd32(E1000_SEC); | |
3316 | ||
3317 | adapter->stats.mpc += rd32(E1000_MPC); | |
3318 | adapter->stats.scc += rd32(E1000_SCC); | |
3319 | adapter->stats.ecol += rd32(E1000_ECOL); | |
3320 | adapter->stats.mcc += rd32(E1000_MCC); | |
3321 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
3322 | adapter->stats.dc += rd32(E1000_DC); | |
3323 | adapter->stats.rlec += rd32(E1000_RLEC); | |
3324 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
3325 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
3326 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
3327 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
3328 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
3329 | adapter->stats.gptc += rd32(E1000_GPTC); | |
3330 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
3331 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
3332 | adapter->stats.rnbc += rd32(E1000_RNBC); | |
3333 | adapter->stats.ruc += rd32(E1000_RUC); | |
3334 | adapter->stats.rfc += rd32(E1000_RFC); | |
3335 | adapter->stats.rjc += rd32(E1000_RJC); | |
3336 | adapter->stats.tor += rd32(E1000_TORH); | |
3337 | adapter->stats.tot += rd32(E1000_TOTH); | |
3338 | adapter->stats.tpr += rd32(E1000_TPR); | |
3339 | ||
3340 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
3341 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
3342 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
3343 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
3344 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
3345 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
3346 | ||
3347 | adapter->stats.mptc += rd32(E1000_MPTC); | |
3348 | adapter->stats.bptc += rd32(E1000_BPTC); | |
3349 | ||
3350 | /* used for adaptive IFS */ | |
3351 | ||
3352 | hw->mac.tx_packet_delta = rd32(E1000_TPT); | |
3353 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
3354 | hw->mac.collision_delta = rd32(E1000_COLC); | |
3355 | adapter->stats.colc += hw->mac.collision_delta; | |
3356 | ||
3357 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
3358 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3359 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
3360 | adapter->stats.tsctc += rd32(E1000_TSCTC); | |
3361 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
3362 | ||
3363 | adapter->stats.iac += rd32(E1000_IAC); | |
3364 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
3365 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
3366 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
3367 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
3368 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
3369 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
3370 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
3371 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
3372 | ||
3373 | /* Fill out the OS statistics structure */ | |
3374 | adapter->net_stats.multicast = adapter->stats.mprc; | |
3375 | adapter->net_stats.collisions = adapter->stats.colc; | |
3376 | ||
3377 | /* Rx Errors */ | |
3378 | ||
3379 | /* RLEC on some newer hardware can be incorrect so build | |
3380 | * our own version based on RUC and ROC */ | |
3381 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + | |
3382 | adapter->stats.crcerrs + adapter->stats.algnerrc + | |
3383 | adapter->stats.ruc + adapter->stats.roc + | |
3384 | adapter->stats.cexterr; | |
3385 | adapter->net_stats.rx_length_errors = adapter->stats.ruc + | |
3386 | adapter->stats.roc; | |
3387 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
3388 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; | |
3389 | adapter->net_stats.rx_missed_errors = adapter->stats.mpc; | |
3390 | ||
3391 | /* Tx Errors */ | |
3392 | adapter->net_stats.tx_errors = adapter->stats.ecol + | |
3393 | adapter->stats.latecol; | |
3394 | adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; | |
3395 | adapter->net_stats.tx_window_errors = adapter->stats.latecol; | |
3396 | adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; | |
3397 | ||
3398 | /* Tx Dropped needs to be maintained elsewhere */ | |
3399 | ||
3400 | /* Phy Stats */ | |
3401 | if (hw->phy.media_type == e1000_media_type_copper) { | |
3402 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 3403 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
3404 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
3405 | adapter->phy_stats.idle_errors += phy_tmp; | |
3406 | } | |
3407 | } | |
3408 | ||
3409 | /* Management Stats */ | |
3410 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
3411 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
3412 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
3413 | } | |
3414 | ||
9d5c8243 AK |
3415 | static irqreturn_t igb_msix_other(int irq, void *data) |
3416 | { | |
3417 | struct net_device *netdev = data; | |
3418 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3419 | struct e1000_hw *hw = &adapter->hw; | |
844290e5 | 3420 | u32 icr = rd32(E1000_ICR); |
9d5c8243 | 3421 | |
844290e5 | 3422 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 AD |
3423 | |
3424 | if(icr & E1000_ICR_DOUTSYNC) { | |
3425 | /* HW is reporting DMA is out of sync */ | |
3426 | adapter->stats.doosync++; | |
3427 | } | |
844290e5 PW |
3428 | if (!(icr & E1000_ICR_LSC)) |
3429 | goto no_link_interrupt; | |
3430 | hw->mac.get_link_status = 1; | |
3431 | /* guard against interrupt when we're going down */ | |
3432 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3433 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
eebbbdba | 3434 | |
9d5c8243 | 3435 | no_link_interrupt: |
dda0e083 | 3436 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); |
844290e5 | 3437 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
3438 | |
3439 | return IRQ_HANDLED; | |
3440 | } | |
3441 | ||
3442 | static irqreturn_t igb_msix_tx(int irq, void *data) | |
3443 | { | |
3444 | struct igb_ring *tx_ring = data; | |
3445 | struct igb_adapter *adapter = tx_ring->adapter; | |
3446 | struct e1000_hw *hw = &adapter->hw; | |
3447 | ||
421e02f0 | 3448 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3449 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3450 | igb_update_tx_dca(tx_ring); |
3451 | #endif | |
73cd78f1 | 3452 | |
9d5c8243 AK |
3453 | tx_ring->total_bytes = 0; |
3454 | tx_ring->total_packets = 0; | |
661086df PWJ |
3455 | |
3456 | /* auto mask will automatically reenable the interrupt when we write | |
3457 | * EICS */ | |
3b644cf6 | 3458 | if (!igb_clean_tx_irq(tx_ring)) |
9d5c8243 AK |
3459 | /* Ring was not completely cleaned, so fire another interrupt */ |
3460 | wr32(E1000_EICS, tx_ring->eims_value); | |
661086df | 3461 | else |
9d5c8243 | 3462 | wr32(E1000_EIMS, tx_ring->eims_value); |
661086df | 3463 | |
9d5c8243 AK |
3464 | return IRQ_HANDLED; |
3465 | } | |
3466 | ||
6eb5a7f1 AD |
3467 | static void igb_write_itr(struct igb_ring *ring) |
3468 | { | |
3469 | struct e1000_hw *hw = &ring->adapter->hw; | |
3470 | if ((ring->adapter->itr_setting & 3) && ring->set_itr) { | |
3471 | switch (hw->mac.type) { | |
3472 | case e1000_82576: | |
73cd78f1 | 3473 | wr32(ring->itr_register, ring->itr_val | |
6eb5a7f1 AD |
3474 | 0x80000000); |
3475 | break; | |
3476 | default: | |
73cd78f1 | 3477 | wr32(ring->itr_register, ring->itr_val | |
6eb5a7f1 AD |
3478 | (ring->itr_val << 16)); |
3479 | break; | |
3480 | } | |
3481 | ring->set_itr = 0; | |
3482 | } | |
3483 | } | |
3484 | ||
9d5c8243 AK |
3485 | static irqreturn_t igb_msix_rx(int irq, void *data) |
3486 | { | |
3487 | struct igb_ring *rx_ring = data; | |
9d5c8243 | 3488 | |
844290e5 PW |
3489 | /* Write the ITR value calculated at the end of the |
3490 | * previous interrupt. | |
3491 | */ | |
9d5c8243 | 3492 | |
6eb5a7f1 | 3493 | igb_write_itr(rx_ring); |
9d5c8243 | 3494 | |
288379f0 BH |
3495 | if (napi_schedule_prep(&rx_ring->napi)) |
3496 | __napi_schedule(&rx_ring->napi); | |
844290e5 | 3497 | |
421e02f0 | 3498 | #ifdef CONFIG_IGB_DCA |
8d253320 | 3499 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3500 | igb_update_rx_dca(rx_ring); |
3501 | #endif | |
3502 | return IRQ_HANDLED; | |
3503 | } | |
3504 | ||
421e02f0 | 3505 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
3506 | static void igb_update_rx_dca(struct igb_ring *rx_ring) |
3507 | { | |
3508 | u32 dca_rxctrl; | |
3509 | struct igb_adapter *adapter = rx_ring->adapter; | |
3510 | struct e1000_hw *hw = &adapter->hw; | |
3511 | int cpu = get_cpu(); | |
26bc19ec | 3512 | int q = rx_ring->reg_idx; |
fe4506b6 JC |
3513 | |
3514 | if (rx_ring->cpu != cpu) { | |
3515 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
2d064c06 AD |
3516 | if (hw->mac.type == e1000_82576) { |
3517 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
3518 | dca_rxctrl |= dca_get_tag(cpu) << | |
3519 | E1000_DCA_RXCTRL_CPUID_SHIFT; | |
3520 | } else { | |
3521 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | |
3522 | dca_rxctrl |= dca_get_tag(cpu); | |
3523 | } | |
fe4506b6 JC |
3524 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
3525 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
3526 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
3527 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
3528 | rx_ring->cpu = cpu; | |
3529 | } | |
3530 | put_cpu(); | |
3531 | } | |
3532 | ||
3533 | static void igb_update_tx_dca(struct igb_ring *tx_ring) | |
3534 | { | |
3535 | u32 dca_txctrl; | |
3536 | struct igb_adapter *adapter = tx_ring->adapter; | |
3537 | struct e1000_hw *hw = &adapter->hw; | |
3538 | int cpu = get_cpu(); | |
26bc19ec | 3539 | int q = tx_ring->reg_idx; |
fe4506b6 JC |
3540 | |
3541 | if (tx_ring->cpu != cpu) { | |
3542 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
2d064c06 AD |
3543 | if (hw->mac.type == e1000_82576) { |
3544 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; | |
3545 | dca_txctrl |= dca_get_tag(cpu) << | |
3546 | E1000_DCA_TXCTRL_CPUID_SHIFT; | |
3547 | } else { | |
3548 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
3549 | dca_txctrl |= dca_get_tag(cpu); | |
3550 | } | |
fe4506b6 JC |
3551 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; |
3552 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
3553 | tx_ring->cpu = cpu; | |
3554 | } | |
3555 | put_cpu(); | |
3556 | } | |
3557 | ||
3558 | static void igb_setup_dca(struct igb_adapter *adapter) | |
3559 | { | |
3560 | int i; | |
3561 | ||
7dfc16fa | 3562 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
3563 | return; |
3564 | ||
3565 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3566 | adapter->tx_ring[i].cpu = -1; | |
3567 | igb_update_tx_dca(&adapter->tx_ring[i]); | |
3568 | } | |
3569 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3570 | adapter->rx_ring[i].cpu = -1; | |
3571 | igb_update_rx_dca(&adapter->rx_ring[i]); | |
3572 | } | |
3573 | } | |
3574 | ||
3575 | static int __igb_notify_dca(struct device *dev, void *data) | |
3576 | { | |
3577 | struct net_device *netdev = dev_get_drvdata(dev); | |
3578 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3579 | struct e1000_hw *hw = &adapter->hw; | |
3580 | unsigned long event = *(unsigned long *)data; | |
3581 | ||
3582 | switch (event) { | |
3583 | case DCA_PROVIDER_ADD: | |
3584 | /* if already enabled, don't do it again */ | |
7dfc16fa | 3585 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 3586 | break; |
fe4506b6 JC |
3587 | /* Always use CB2 mode, difference is masked |
3588 | * in the CB driver. */ | |
cbd347ad | 3589 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
fe4506b6 | 3590 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 3591 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
3592 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); |
3593 | igb_setup_dca(adapter); | |
3594 | break; | |
3595 | } | |
3596 | /* Fall Through since DCA is disabled. */ | |
3597 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 3598 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
3599 | /* without this a class_device is left |
3600 | * hanging around in the sysfs model */ | |
3601 | dca_remove_requester(dev); | |
3602 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); | |
7dfc16fa | 3603 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 3604 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
3605 | } |
3606 | break; | |
3607 | } | |
bbd98fe4 | 3608 | |
fe4506b6 | 3609 | return 0; |
9d5c8243 AK |
3610 | } |
3611 | ||
fe4506b6 JC |
3612 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
3613 | void *p) | |
3614 | { | |
3615 | int ret_val; | |
3616 | ||
3617 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
3618 | __igb_notify_dca); | |
3619 | ||
3620 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
3621 | } | |
421e02f0 | 3622 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 AK |
3623 | |
3624 | /** | |
3625 | * igb_intr_msi - Interrupt Handler | |
3626 | * @irq: interrupt number | |
3627 | * @data: pointer to a network interface device structure | |
3628 | **/ | |
3629 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
3630 | { | |
3631 | struct net_device *netdev = data; | |
3632 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
3633 | struct e1000_hw *hw = &adapter->hw; |
3634 | /* read ICR disables interrupts using IAM */ | |
3635 | u32 icr = rd32(E1000_ICR); | |
3636 | ||
6eb5a7f1 | 3637 | igb_write_itr(adapter->rx_ring); |
9d5c8243 | 3638 | |
dda0e083 AD |
3639 | if(icr & E1000_ICR_DOUTSYNC) { |
3640 | /* HW is reporting DMA is out of sync */ | |
3641 | adapter->stats.doosync++; | |
3642 | } | |
3643 | ||
9d5c8243 AK |
3644 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
3645 | hw->mac.get_link_status = 1; | |
3646 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3647 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3648 | } | |
3649 | ||
288379f0 | 3650 | napi_schedule(&adapter->rx_ring[0].napi); |
9d5c8243 AK |
3651 | |
3652 | return IRQ_HANDLED; | |
3653 | } | |
3654 | ||
3655 | /** | |
4a3c6433 | 3656 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
3657 | * @irq: interrupt number |
3658 | * @data: pointer to a network interface device structure | |
3659 | **/ | |
3660 | static irqreturn_t igb_intr(int irq, void *data) | |
3661 | { | |
3662 | struct net_device *netdev = data; | |
3663 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
3664 | struct e1000_hw *hw = &adapter->hw; |
3665 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
3666 | * need for the IMC write */ | |
3667 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
3668 | if (!icr) |
3669 | return IRQ_NONE; /* Not our interrupt */ | |
3670 | ||
6eb5a7f1 | 3671 | igb_write_itr(adapter->rx_ring); |
9d5c8243 AK |
3672 | |
3673 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
3674 | * not set, then the adapter didn't send an interrupt */ | |
3675 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
3676 | return IRQ_NONE; | |
3677 | ||
dda0e083 AD |
3678 | if(icr & E1000_ICR_DOUTSYNC) { |
3679 | /* HW is reporting DMA is out of sync */ | |
3680 | adapter->stats.doosync++; | |
3681 | } | |
3682 | ||
9d5c8243 AK |
3683 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
3684 | hw->mac.get_link_status = 1; | |
3685 | /* guard against interrupt when we're going down */ | |
3686 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3687 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3688 | } | |
3689 | ||
288379f0 | 3690 | napi_schedule(&adapter->rx_ring[0].napi); |
9d5c8243 AK |
3691 | |
3692 | return IRQ_HANDLED; | |
3693 | } | |
3694 | ||
46544258 | 3695 | static inline void igb_rx_irq_enable(struct igb_ring *rx_ring) |
9d5c8243 | 3696 | { |
661086df | 3697 | struct igb_adapter *adapter = rx_ring->adapter; |
46544258 | 3698 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3699 | |
46544258 AD |
3700 | if (adapter->itr_setting & 3) { |
3701 | if (adapter->num_rx_queues == 1) | |
6eb5a7f1 | 3702 | igb_set_itr(adapter); |
46544258 AD |
3703 | else |
3704 | igb_update_ring_itr(rx_ring); | |
9d5c8243 AK |
3705 | } |
3706 | ||
46544258 AD |
3707 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
3708 | if (adapter->msix_entries) | |
3709 | wr32(E1000_EIMS, rx_ring->eims_value); | |
3710 | else | |
3711 | igb_irq_enable(adapter); | |
3712 | } | |
9d5c8243 AK |
3713 | } |
3714 | ||
46544258 AD |
3715 | /** |
3716 | * igb_poll - NAPI Rx polling callback | |
3717 | * @napi: napi polling structure | |
3718 | * @budget: count of how many packets we should handle | |
3719 | **/ | |
3720 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 AK |
3721 | { |
3722 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); | |
3723 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 AK |
3724 | struct net_device *netdev = adapter->netdev; |
3725 | int work_done = 0; | |
3726 | ||
421e02f0 | 3727 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3728 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3729 | igb_update_rx_dca(rx_ring); |
3730 | #endif | |
3b644cf6 | 3731 | igb_clean_rx_irq_adv(rx_ring, &work_done, budget); |
9d5c8243 | 3732 | |
46544258 AD |
3733 | if (rx_ring->buddy) { |
3734 | #ifdef CONFIG_IGB_DCA | |
3735 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) | |
3736 | igb_update_tx_dca(rx_ring->buddy); | |
3737 | #endif | |
3738 | if (!igb_clean_tx_irq(rx_ring->buddy)) | |
3739 | work_done = budget; | |
3740 | } | |
3741 | ||
9d5c8243 | 3742 | /* If not enough Rx work done, exit the polling mode */ |
46544258 | 3743 | if ((work_done < budget) || !netif_running(netdev)) { |
288379f0 | 3744 | napi_complete(napi); |
46544258 | 3745 | igb_rx_irq_enable(rx_ring); |
9d5c8243 AK |
3746 | } |
3747 | ||
46544258 | 3748 | return work_done; |
9d5c8243 | 3749 | } |
6d8126f9 | 3750 | |
33af6bcc PO |
3751 | /** |
3752 | * igb_hwtstamp - utility function which checks for TX time stamp | |
3753 | * @adapter: board private structure | |
3754 | * @skb: packet that was just sent | |
3755 | * | |
3756 | * If we were asked to do hardware stamping and such a time stamp is | |
3757 | * available, then it must have been for this skb here because we only | |
3758 | * allow only one such packet into the queue. | |
3759 | */ | |
3760 | static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb) | |
3761 | { | |
3762 | union skb_shared_tx *shtx = skb_tx(skb); | |
3763 | struct e1000_hw *hw = &adapter->hw; | |
3764 | ||
3765 | if (unlikely(shtx->hardware)) { | |
3766 | u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID; | |
3767 | if (valid) { | |
3768 | u64 regval = rd32(E1000_TXSTMPL); | |
3769 | u64 ns; | |
3770 | struct skb_shared_hwtstamps shhwtstamps; | |
3771 | ||
3772 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
3773 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
3774 | ns = timecounter_cyc2time(&adapter->clock, | |
3775 | regval); | |
3776 | timecompare_update(&adapter->compare, ns); | |
3777 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
3778 | shhwtstamps.syststamp = | |
3779 | timecompare_transform(&adapter->compare, ns); | |
3780 | skb_tstamp_tx(skb, &shhwtstamps); | |
3781 | } | |
3782 | ||
3783 | /* delayed orphaning: skb_tstamp_tx() needs the socket */ | |
3784 | skb_orphan(skb); | |
3785 | } | |
3786 | } | |
3787 | ||
9d5c8243 AK |
3788 | /** |
3789 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
3790 | * @adapter: board private structure | |
3791 | * returns true if ring is completely cleaned | |
3792 | **/ | |
3b644cf6 | 3793 | static bool igb_clean_tx_irq(struct igb_ring *tx_ring) |
9d5c8243 | 3794 | { |
3b644cf6 | 3795 | struct igb_adapter *adapter = tx_ring->adapter; |
3b644cf6 | 3796 | struct net_device *netdev = adapter->netdev; |
0e014cb1 | 3797 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3798 | struct igb_buffer *buffer_info; |
3799 | struct sk_buff *skb; | |
0e014cb1 | 3800 | union e1000_adv_tx_desc *tx_desc, *eop_desc; |
9d5c8243 | 3801 | unsigned int total_bytes = 0, total_packets = 0; |
0e014cb1 AD |
3802 | unsigned int i, eop, count = 0; |
3803 | bool cleaned = false; | |
9d5c8243 | 3804 | |
9d5c8243 | 3805 | i = tx_ring->next_to_clean; |
0e014cb1 AD |
3806 | eop = tx_ring->buffer_info[i].next_to_watch; |
3807 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
3808 | ||
3809 | while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) && | |
3810 | (count < tx_ring->count)) { | |
3811 | for (cleaned = false; !cleaned; count++) { | |
3812 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
9d5c8243 | 3813 | buffer_info = &tx_ring->buffer_info[i]; |
0e014cb1 | 3814 | cleaned = (i == eop); |
9d5c8243 AK |
3815 | skb = buffer_info->skb; |
3816 | ||
3817 | if (skb) { | |
3818 | unsigned int segs, bytecount; | |
3819 | /* gso_segs is currently only valid for tcp */ | |
3820 | segs = skb_shinfo(skb)->gso_segs ?: 1; | |
3821 | /* multiply data chunks by size of headers */ | |
3822 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
3823 | skb->len; | |
3824 | total_packets += segs; | |
3825 | total_bytes += bytecount; | |
33af6bcc PO |
3826 | |
3827 | igb_tx_hwtstamp(adapter, skb); | |
9d5c8243 AK |
3828 | } |
3829 | ||
3830 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
0e014cb1 | 3831 | tx_desc->wb.status = 0; |
9d5c8243 AK |
3832 | |
3833 | i++; | |
3834 | if (i == tx_ring->count) | |
3835 | i = 0; | |
9d5c8243 | 3836 | } |
0e014cb1 AD |
3837 | eop = tx_ring->buffer_info[i].next_to_watch; |
3838 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
3839 | } | |
3840 | ||
9d5c8243 AK |
3841 | tx_ring->next_to_clean = i; |
3842 | ||
fc7d345d | 3843 | if (unlikely(count && |
9d5c8243 AK |
3844 | netif_carrier_ok(netdev) && |
3845 | IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) { | |
3846 | /* Make sure that anybody stopping the queue after this | |
3847 | * sees the new next_to_clean. | |
3848 | */ | |
3849 | smp_mb(); | |
661086df PWJ |
3850 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
3851 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
3852 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
3853 | ++adapter->restart_queue; | |
3854 | } | |
9d5c8243 AK |
3855 | } |
3856 | ||
3857 | if (tx_ring->detect_tx_hung) { | |
3858 | /* Detect a transmit hang in hardware, this serializes the | |
3859 | * check with the clearing of time_stamp and movement of i */ | |
3860 | tx_ring->detect_tx_hung = false; | |
3861 | if (tx_ring->buffer_info[i].time_stamp && | |
3862 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | |
3863 | (adapter->tx_timeout_factor * HZ)) | |
3864 | && !(rd32(E1000_STATUS) & | |
3865 | E1000_STATUS_TXOFF)) { | |
3866 | ||
9d5c8243 AK |
3867 | /* detected Tx unit hang */ |
3868 | dev_err(&adapter->pdev->dev, | |
3869 | "Detected Tx Unit Hang\n" | |
2d064c06 | 3870 | " Tx Queue <%d>\n" |
9d5c8243 AK |
3871 | " TDH <%x>\n" |
3872 | " TDT <%x>\n" | |
3873 | " next_to_use <%x>\n" | |
3874 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
3875 | "buffer_info[next_to_clean]\n" |
3876 | " time_stamp <%lx>\n" | |
0e014cb1 | 3877 | " next_to_watch <%x>\n" |
9d5c8243 AK |
3878 | " jiffies <%lx>\n" |
3879 | " desc.status <%x>\n", | |
2d064c06 | 3880 | tx_ring->queue_index, |
9d5c8243 AK |
3881 | readl(adapter->hw.hw_addr + tx_ring->head), |
3882 | readl(adapter->hw.hw_addr + tx_ring->tail), | |
3883 | tx_ring->next_to_use, | |
3884 | tx_ring->next_to_clean, | |
9d5c8243 | 3885 | tx_ring->buffer_info[i].time_stamp, |
0e014cb1 | 3886 | eop, |
9d5c8243 | 3887 | jiffies, |
0e014cb1 | 3888 | eop_desc->wb.status); |
661086df | 3889 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
3890 | } |
3891 | } | |
3892 | tx_ring->total_bytes += total_bytes; | |
3893 | tx_ring->total_packets += total_packets; | |
e21ed353 AD |
3894 | tx_ring->tx_stats.bytes += total_bytes; |
3895 | tx_ring->tx_stats.packets += total_packets; | |
9d5c8243 AK |
3896 | adapter->net_stats.tx_bytes += total_bytes; |
3897 | adapter->net_stats.tx_packets += total_packets; | |
0e014cb1 | 3898 | return (count < tx_ring->count); |
9d5c8243 AK |
3899 | } |
3900 | ||
9d5c8243 AK |
3901 | /** |
3902 | * igb_receive_skb - helper function to handle rx indications | |
eebbbdba | 3903 | * @ring: pointer to receive ring receving this packet |
9d5c8243 | 3904 | * @status: descriptor status field as written by hardware |
73cd78f1 | 3905 | * @rx_desc: receive descriptor containing vlan and type information. |
9d5c8243 AK |
3906 | * @skb: pointer to sk_buff to be indicated to stack |
3907 | **/ | |
d3352520 AD |
3908 | static void igb_receive_skb(struct igb_ring *ring, u8 status, |
3909 | union e1000_adv_rx_desc * rx_desc, | |
3910 | struct sk_buff *skb) | |
3911 | { | |
3912 | struct igb_adapter * adapter = ring->adapter; | |
3913 | bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP)); | |
3914 | ||
0c8dfc83 | 3915 | skb_record_rx_queue(skb, ring->queue_index); |
5c0999b7 | 3916 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) { |
d3352520 | 3917 | if (vlan_extracted) |
5c0999b7 HX |
3918 | vlan_gro_receive(&ring->napi, adapter->vlgrp, |
3919 | le16_to_cpu(rx_desc->wb.upper.vlan), | |
3920 | skb); | |
d3352520 | 3921 | else |
5c0999b7 | 3922 | napi_gro_receive(&ring->napi, skb); |
d3352520 | 3923 | } else { |
d3352520 AD |
3924 | if (vlan_extracted) |
3925 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | |
3926 | le16_to_cpu(rx_desc->wb.upper.vlan)); | |
3927 | else | |
d3352520 | 3928 | netif_receive_skb(skb); |
d3352520 | 3929 | } |
9d5c8243 AK |
3930 | } |
3931 | ||
9d5c8243 AK |
3932 | static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, |
3933 | u32 status_err, struct sk_buff *skb) | |
3934 | { | |
3935 | skb->ip_summed = CHECKSUM_NONE; | |
3936 | ||
3937 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
3938 | if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum) | |
3939 | return; | |
3940 | /* TCP/UDP checksum error bit is set */ | |
3941 | if (status_err & | |
3942 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
3943 | /* let the stack verify checksum errors */ | |
3944 | adapter->hw_csum_err++; | |
3945 | return; | |
3946 | } | |
3947 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3948 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
3949 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3950 | ||
3951 | adapter->hw_csum_good++; | |
3952 | } | |
3953 | ||
3b644cf6 MW |
3954 | static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, |
3955 | int *work_done, int budget) | |
9d5c8243 | 3956 | { |
3b644cf6 | 3957 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 | 3958 | struct net_device *netdev = adapter->netdev; |
33af6bcc | 3959 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3960 | struct pci_dev *pdev = adapter->pdev; |
3961 | union e1000_adv_rx_desc *rx_desc , *next_rxd; | |
3962 | struct igb_buffer *buffer_info , *next_buffer; | |
3963 | struct sk_buff *skb; | |
9d5c8243 AK |
3964 | bool cleaned = false; |
3965 | int cleaned_count = 0; | |
3966 | unsigned int total_bytes = 0, total_packets = 0; | |
73cd78f1 AD |
3967 | unsigned int i; |
3968 | u32 length, hlen, staterr; | |
9d5c8243 AK |
3969 | |
3970 | i = rx_ring->next_to_clean; | |
69d3ca53 | 3971 | buffer_info = &rx_ring->buffer_info[i]; |
9d5c8243 AK |
3972 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); |
3973 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
3974 | ||
3975 | while (staterr & E1000_RXD_STAT_DD) { | |
3976 | if (*work_done >= budget) | |
3977 | break; | |
3978 | (*work_done)++; | |
9d5c8243 | 3979 | |
69d3ca53 AD |
3980 | skb = buffer_info->skb; |
3981 | prefetch(skb->data - NET_IP_ALIGN); | |
3982 | buffer_info->skb = NULL; | |
3983 | ||
3984 | i++; | |
3985 | if (i == rx_ring->count) | |
3986 | i = 0; | |
3987 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); | |
3988 | prefetch(next_rxd); | |
3989 | next_buffer = &rx_ring->buffer_info[i]; | |
9d5c8243 AK |
3990 | |
3991 | length = le16_to_cpu(rx_desc->wb.upper.length); | |
3992 | cleaned = true; | |
3993 | cleaned_count++; | |
3994 | ||
bf36c1a0 AD |
3995 | if (!adapter->rx_ps_hdr_size) { |
3996 | pci_unmap_single(pdev, buffer_info->dma, | |
3997 | adapter->rx_buffer_len + | |
3998 | NET_IP_ALIGN, | |
3999 | PCI_DMA_FROMDEVICE); | |
4000 | skb_put(skb, length); | |
4001 | goto send_up; | |
9d5c8243 AK |
4002 | } |
4003 | ||
69d3ca53 AD |
4004 | /* HW will not DMA in data larger than the given buffer, even |
4005 | * if it parses the (NFS, of course) header to be larger. In | |
4006 | * that case, it fills the header buffer and spills the rest | |
4007 | * into the page. | |
4008 | */ | |
4009 | hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | |
4010 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
4011 | if (hlen > adapter->rx_ps_hdr_size) | |
4012 | hlen = adapter->rx_ps_hdr_size; | |
4013 | ||
bf36c1a0 AD |
4014 | if (!skb_shinfo(skb)->nr_frags) { |
4015 | pci_unmap_single(pdev, buffer_info->dma, | |
73cd78f1 | 4016 | adapter->rx_ps_hdr_size + NET_IP_ALIGN, |
bf36c1a0 AD |
4017 | PCI_DMA_FROMDEVICE); |
4018 | skb_put(skb, hlen); | |
4019 | } | |
4020 | ||
4021 | if (length) { | |
9d5c8243 | 4022 | pci_unmap_page(pdev, buffer_info->page_dma, |
bf36c1a0 | 4023 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9d5c8243 | 4024 | buffer_info->page_dma = 0; |
bf36c1a0 AD |
4025 | |
4026 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++, | |
4027 | buffer_info->page, | |
4028 | buffer_info->page_offset, | |
4029 | length); | |
4030 | ||
4031 | if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) || | |
4032 | (page_count(buffer_info->page) != 1)) | |
4033 | buffer_info->page = NULL; | |
4034 | else | |
4035 | get_page(buffer_info->page); | |
9d5c8243 AK |
4036 | |
4037 | skb->len += length; | |
4038 | skb->data_len += length; | |
9d5c8243 | 4039 | |
bf36c1a0 | 4040 | skb->truesize += length; |
9d5c8243 | 4041 | } |
9d5c8243 | 4042 | |
bf36c1a0 | 4043 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
b2d56536 AD |
4044 | buffer_info->skb = next_buffer->skb; |
4045 | buffer_info->dma = next_buffer->dma; | |
4046 | next_buffer->skb = skb; | |
4047 | next_buffer->dma = 0; | |
bf36c1a0 AD |
4048 | goto next_desc; |
4049 | } | |
69d3ca53 | 4050 | send_up: |
33af6bcc PO |
4051 | /* |
4052 | * If this bit is set, then the RX registers contain | |
4053 | * the time stamp. No other packet will be time | |
4054 | * stamped until we read these registers, so read the | |
4055 | * registers to make them available again. Because | |
4056 | * only one packet can be time stamped at a time, we | |
4057 | * know that the register values must belong to this | |
4058 | * one here and therefore we don't need to compare | |
4059 | * any of the additional attributes stored for it. | |
4060 | * | |
4061 | * If nothing went wrong, then it should have a | |
4062 | * skb_shared_tx that we can turn into a | |
4063 | * skb_shared_hwtstamps. | |
4064 | * | |
4065 | * TODO: can time stamping be triggered (thus locking | |
4066 | * the registers) without the packet reaching this point | |
4067 | * here? In that case RX time stamping would get stuck. | |
4068 | * | |
4069 | * TODO: in "time stamp all packets" mode this bit is | |
4070 | * not set. Need a global flag for this mode and then | |
4071 | * always read the registers. Cannot be done without | |
4072 | * a race condition. | |
4073 | */ | |
4074 | if (unlikely(staterr & E1000_RXD_STAT_TS)) { | |
4075 | u64 regval; | |
4076 | u64 ns; | |
4077 | struct skb_shared_hwtstamps *shhwtstamps = | |
4078 | skb_hwtstamps(skb); | |
4079 | ||
4080 | WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID), | |
4081 | "igb: no RX time stamp available for time stamped packet"); | |
4082 | regval = rd32(E1000_RXSTMPL); | |
4083 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
4084 | ns = timecounter_cyc2time(&adapter->clock, regval); | |
4085 | timecompare_update(&adapter->compare, ns); | |
4086 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
4087 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
4088 | shhwtstamps->syststamp = | |
4089 | timecompare_transform(&adapter->compare, ns); | |
4090 | } | |
4091 | ||
9d5c8243 AK |
4092 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
4093 | dev_kfree_skb_irq(skb); | |
4094 | goto next_desc; | |
4095 | } | |
9d5c8243 AK |
4096 | |
4097 | total_bytes += skb->len; | |
4098 | total_packets++; | |
4099 | ||
4100 | igb_rx_checksum_adv(adapter, staterr, skb); | |
4101 | ||
4102 | skb->protocol = eth_type_trans(skb, netdev); | |
4103 | ||
d3352520 | 4104 | igb_receive_skb(rx_ring, staterr, rx_desc, skb); |
9d5c8243 | 4105 | |
9d5c8243 AK |
4106 | next_desc: |
4107 | rx_desc->wb.upper.status_error = 0; | |
4108 | ||
4109 | /* return some buffers to hardware, one at a time is too slow */ | |
4110 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
3b644cf6 | 4111 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
4112 | cleaned_count = 0; |
4113 | } | |
4114 | ||
4115 | /* use prefetched values */ | |
4116 | rx_desc = next_rxd; | |
4117 | buffer_info = next_buffer; | |
9d5c8243 AK |
4118 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
4119 | } | |
bf36c1a0 | 4120 | |
9d5c8243 AK |
4121 | rx_ring->next_to_clean = i; |
4122 | cleaned_count = IGB_DESC_UNUSED(rx_ring); | |
4123 | ||
4124 | if (cleaned_count) | |
3b644cf6 | 4125 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
4126 | |
4127 | rx_ring->total_packets += total_packets; | |
4128 | rx_ring->total_bytes += total_bytes; | |
4129 | rx_ring->rx_stats.packets += total_packets; | |
4130 | rx_ring->rx_stats.bytes += total_bytes; | |
4131 | adapter->net_stats.rx_bytes += total_bytes; | |
4132 | adapter->net_stats.rx_packets += total_packets; | |
4133 | return cleaned; | |
4134 | } | |
4135 | ||
9d5c8243 AK |
4136 | /** |
4137 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | |
4138 | * @adapter: address of board private structure | |
4139 | **/ | |
3b644cf6 | 4140 | static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, |
9d5c8243 AK |
4141 | int cleaned_count) |
4142 | { | |
3b644cf6 | 4143 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
4144 | struct net_device *netdev = adapter->netdev; |
4145 | struct pci_dev *pdev = adapter->pdev; | |
4146 | union e1000_adv_rx_desc *rx_desc; | |
4147 | struct igb_buffer *buffer_info; | |
4148 | struct sk_buff *skb; | |
4149 | unsigned int i; | |
db761762 | 4150 | int bufsz; |
9d5c8243 AK |
4151 | |
4152 | i = rx_ring->next_to_use; | |
4153 | buffer_info = &rx_ring->buffer_info[i]; | |
4154 | ||
db761762 AD |
4155 | if (adapter->rx_ps_hdr_size) |
4156 | bufsz = adapter->rx_ps_hdr_size; | |
4157 | else | |
4158 | bufsz = adapter->rx_buffer_len; | |
4159 | bufsz += NET_IP_ALIGN; | |
4160 | ||
9d5c8243 AK |
4161 | while (cleaned_count--) { |
4162 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
4163 | ||
bf36c1a0 | 4164 | if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) { |
9d5c8243 | 4165 | if (!buffer_info->page) { |
bf36c1a0 AD |
4166 | buffer_info->page = alloc_page(GFP_ATOMIC); |
4167 | if (!buffer_info->page) { | |
4168 | adapter->alloc_rx_buff_failed++; | |
4169 | goto no_buffers; | |
4170 | } | |
4171 | buffer_info->page_offset = 0; | |
4172 | } else { | |
4173 | buffer_info->page_offset ^= PAGE_SIZE / 2; | |
9d5c8243 AK |
4174 | } |
4175 | buffer_info->page_dma = | |
db761762 | 4176 | pci_map_page(pdev, buffer_info->page, |
bf36c1a0 AD |
4177 | buffer_info->page_offset, |
4178 | PAGE_SIZE / 2, | |
9d5c8243 AK |
4179 | PCI_DMA_FROMDEVICE); |
4180 | } | |
4181 | ||
4182 | if (!buffer_info->skb) { | |
9d5c8243 | 4183 | skb = netdev_alloc_skb(netdev, bufsz); |
9d5c8243 AK |
4184 | if (!skb) { |
4185 | adapter->alloc_rx_buff_failed++; | |
4186 | goto no_buffers; | |
4187 | } | |
4188 | ||
4189 | /* Make buffer alignment 2 beyond a 16 byte boundary | |
4190 | * this will result in a 16 byte aligned IP header after | |
4191 | * the 14 byte MAC header is removed | |
4192 | */ | |
4193 | skb_reserve(skb, NET_IP_ALIGN); | |
4194 | ||
4195 | buffer_info->skb = skb; | |
4196 | buffer_info->dma = pci_map_single(pdev, skb->data, | |
4197 | bufsz, | |
4198 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
4199 | } |
4200 | /* Refresh the desc even if buffer_addrs didn't change because | |
4201 | * each write-back erases this info. */ | |
4202 | if (adapter->rx_ps_hdr_size) { | |
4203 | rx_desc->read.pkt_addr = | |
4204 | cpu_to_le64(buffer_info->page_dma); | |
4205 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | |
4206 | } else { | |
4207 | rx_desc->read.pkt_addr = | |
4208 | cpu_to_le64(buffer_info->dma); | |
4209 | rx_desc->read.hdr_addr = 0; | |
4210 | } | |
4211 | ||
4212 | i++; | |
4213 | if (i == rx_ring->count) | |
4214 | i = 0; | |
4215 | buffer_info = &rx_ring->buffer_info[i]; | |
4216 | } | |
4217 | ||
4218 | no_buffers: | |
4219 | if (rx_ring->next_to_use != i) { | |
4220 | rx_ring->next_to_use = i; | |
4221 | if (i == 0) | |
4222 | i = (rx_ring->count - 1); | |
4223 | else | |
4224 | i--; | |
4225 | ||
4226 | /* Force memory writes to complete before letting h/w | |
4227 | * know there are new descriptors to fetch. (Only | |
4228 | * applicable for weak-ordered memory model archs, | |
4229 | * such as IA-64). */ | |
4230 | wmb(); | |
4231 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
4232 | } | |
4233 | } | |
4234 | ||
4235 | /** | |
4236 | * igb_mii_ioctl - | |
4237 | * @netdev: | |
4238 | * @ifreq: | |
4239 | * @cmd: | |
4240 | **/ | |
4241 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4242 | { | |
4243 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4244 | struct mii_ioctl_data *data = if_mii(ifr); | |
4245 | ||
4246 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
4247 | return -EOPNOTSUPP; | |
4248 | ||
4249 | switch (cmd) { | |
4250 | case SIOCGMIIPHY: | |
4251 | data->phy_id = adapter->hw.phy.addr; | |
4252 | break; | |
4253 | case SIOCGMIIREG: | |
4254 | if (!capable(CAP_NET_ADMIN)) | |
4255 | return -EPERM; | |
f5f4cf08 AD |
4256 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
4257 | &data->val_out)) | |
9d5c8243 AK |
4258 | return -EIO; |
4259 | break; | |
4260 | case SIOCSMIIREG: | |
4261 | default: | |
4262 | return -EOPNOTSUPP; | |
4263 | } | |
4264 | return 0; | |
4265 | } | |
4266 | ||
c6cb090b PO |
4267 | /** |
4268 | * igb_hwtstamp_ioctl - control hardware time stamping | |
4269 | * @netdev: | |
4270 | * @ifreq: | |
4271 | * @cmd: | |
4272 | * | |
33af6bcc PO |
4273 | * Outgoing time stamping can be enabled and disabled. Play nice and |
4274 | * disable it when requested, although it shouldn't case any overhead | |
4275 | * when no packet needs it. At most one packet in the queue may be | |
4276 | * marked for time stamping, otherwise it would be impossible to tell | |
4277 | * for sure to which packet the hardware time stamp belongs. | |
4278 | * | |
4279 | * Incoming time stamping has to be configured via the hardware | |
4280 | * filters. Not all combinations are supported, in particular event | |
4281 | * type has to be specified. Matching the kind of event packet is | |
4282 | * not supported, with the exception of "all V2 events regardless of | |
4283 | * level 2 or 4". | |
4284 | * | |
c6cb090b PO |
4285 | **/ |
4286 | static int igb_hwtstamp_ioctl(struct net_device *netdev, | |
4287 | struct ifreq *ifr, int cmd) | |
4288 | { | |
33af6bcc PO |
4289 | struct igb_adapter *adapter = netdev_priv(netdev); |
4290 | struct e1000_hw *hw = &adapter->hw; | |
c6cb090b | 4291 | struct hwtstamp_config config; |
33af6bcc PO |
4292 | u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; |
4293 | u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED; | |
4294 | u32 tsync_rx_ctl_type = 0; | |
4295 | u32 tsync_rx_cfg = 0; | |
4296 | int is_l4 = 0; | |
4297 | int is_l2 = 0; | |
4298 | short port = 319; /* PTP */ | |
4299 | u32 regval; | |
c6cb090b PO |
4300 | |
4301 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
4302 | return -EFAULT; | |
4303 | ||
4304 | /* reserved for future extensions */ | |
4305 | if (config.flags) | |
4306 | return -EINVAL; | |
4307 | ||
33af6bcc PO |
4308 | switch (config.tx_type) { |
4309 | case HWTSTAMP_TX_OFF: | |
4310 | tsync_tx_ctl_bit = 0; | |
4311 | break; | |
4312 | case HWTSTAMP_TX_ON: | |
4313 | tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; | |
4314 | break; | |
4315 | default: | |
4316 | return -ERANGE; | |
4317 | } | |
4318 | ||
4319 | switch (config.rx_filter) { | |
4320 | case HWTSTAMP_FILTER_NONE: | |
4321 | tsync_rx_ctl_bit = 0; | |
4322 | break; | |
4323 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
4324 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
4325 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
4326 | case HWTSTAMP_FILTER_ALL: | |
4327 | /* | |
4328 | * register TSYNCRXCFG must be set, therefore it is not | |
4329 | * possible to time stamp both Sync and Delay_Req messages | |
4330 | * => fall back to time stamping all packets | |
4331 | */ | |
4332 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL; | |
4333 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
4334 | break; | |
4335 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
4336 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | |
4337 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
4338 | is_l4 = 1; | |
4339 | break; | |
4340 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
4341 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | |
4342 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
4343 | is_l4 = 1; | |
4344 | break; | |
4345 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
4346 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
4347 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
4348 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; | |
4349 | is_l2 = 1; | |
4350 | is_l4 = 1; | |
4351 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
4352 | break; | |
4353 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
4354 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
4355 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
4356 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; | |
4357 | is_l2 = 1; | |
4358 | is_l4 = 1; | |
4359 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
4360 | break; | |
4361 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
4362 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
4363 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
4364 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2; | |
4365 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
4366 | is_l2 = 1; | |
4367 | break; | |
4368 | default: | |
4369 | return -ERANGE; | |
4370 | } | |
4371 | ||
4372 | /* enable/disable TX */ | |
4373 | regval = rd32(E1000_TSYNCTXCTL); | |
4374 | regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit; | |
4375 | wr32(E1000_TSYNCTXCTL, regval); | |
4376 | ||
4377 | /* enable/disable RX, define which PTP packets are time stamped */ | |
4378 | regval = rd32(E1000_TSYNCRXCTL); | |
4379 | regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit; | |
4380 | regval = (regval & ~0xE) | tsync_rx_ctl_type; | |
4381 | wr32(E1000_TSYNCRXCTL, regval); | |
4382 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
4383 | ||
4384 | /* | |
4385 | * Ethertype Filter Queue Filter[0][15:0] = 0x88F7 | |
4386 | * (Ethertype to filter on) | |
4387 | * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter) | |
4388 | * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping) | |
4389 | */ | |
4390 | wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0); | |
4391 | ||
4392 | /* L4 Queue Filter[0]: only filter by source and destination port */ | |
4393 | wr32(E1000_SPQF0, htons(port)); | |
4394 | wr32(E1000_IMIREXT(0), is_l4 ? | |
4395 | ((1<<12) | (1<<19) /* bypass size and control flags */) : 0); | |
4396 | wr32(E1000_IMIR(0), is_l4 ? | |
4397 | (htons(port) | |
4398 | | (0<<16) /* immediate interrupt disabled */ | |
4399 | | 0 /* (1<<17) bit cleared: do not bypass | |
4400 | destination port check */) | |
4401 | : 0); | |
4402 | wr32(E1000_FTQF0, is_l4 ? | |
4403 | (0x11 /* UDP */ | |
4404 | | (1<<15) /* VF not compared */ | |
4405 | | (1<<27) /* Enable Timestamping */ | |
4406 | | (7<<28) /* only source port filter enabled, | |
4407 | source/target address and protocol | |
4408 | masked */) | |
4409 | : ((1<<15) | (15<<28) /* all mask bits set = filter not | |
4410 | enabled */)); | |
4411 | ||
4412 | wrfl(); | |
4413 | ||
4414 | adapter->hwtstamp_config = config; | |
4415 | ||
4416 | /* clear TX/RX time stamp registers, just to be sure */ | |
4417 | regval = rd32(E1000_TXSTMPH); | |
4418 | regval = rd32(E1000_RXSTMPH); | |
c6cb090b | 4419 | |
33af6bcc PO |
4420 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
4421 | -EFAULT : 0; | |
c6cb090b PO |
4422 | } |
4423 | ||
9d5c8243 AK |
4424 | /** |
4425 | * igb_ioctl - | |
4426 | * @netdev: | |
4427 | * @ifreq: | |
4428 | * @cmd: | |
4429 | **/ | |
4430 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4431 | { | |
4432 | switch (cmd) { | |
4433 | case SIOCGMIIPHY: | |
4434 | case SIOCGMIIREG: | |
4435 | case SIOCSMIIREG: | |
4436 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b PO |
4437 | case SIOCSHWTSTAMP: |
4438 | return igb_hwtstamp_ioctl(netdev, ifr, cmd); | |
9d5c8243 AK |
4439 | default: |
4440 | return -EOPNOTSUPP; | |
4441 | } | |
4442 | } | |
4443 | ||
4444 | static void igb_vlan_rx_register(struct net_device *netdev, | |
4445 | struct vlan_group *grp) | |
4446 | { | |
4447 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4448 | struct e1000_hw *hw = &adapter->hw; | |
4449 | u32 ctrl, rctl; | |
4450 | ||
4451 | igb_irq_disable(adapter); | |
4452 | adapter->vlgrp = grp; | |
4453 | ||
4454 | if (grp) { | |
4455 | /* enable VLAN tag insert/strip */ | |
4456 | ctrl = rd32(E1000_CTRL); | |
4457 | ctrl |= E1000_CTRL_VME; | |
4458 | wr32(E1000_CTRL, ctrl); | |
4459 | ||
4460 | /* enable VLAN receive filtering */ | |
4461 | rctl = rd32(E1000_RCTL); | |
9d5c8243 AK |
4462 | rctl &= ~E1000_RCTL_CFIEN; |
4463 | wr32(E1000_RCTL, rctl); | |
4464 | igb_update_mng_vlan(adapter); | |
4465 | wr32(E1000_RLPML, | |
4466 | adapter->max_frame_size + VLAN_TAG_SIZE); | |
4467 | } else { | |
4468 | /* disable VLAN tag insert/strip */ | |
4469 | ctrl = rd32(E1000_CTRL); | |
4470 | ctrl &= ~E1000_CTRL_VME; | |
4471 | wr32(E1000_CTRL, ctrl); | |
4472 | ||
9d5c8243 AK |
4473 | if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { |
4474 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
4475 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
4476 | } | |
4477 | wr32(E1000_RLPML, | |
4478 | adapter->max_frame_size); | |
4479 | } | |
4480 | ||
4481 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4482 | igb_irq_enable(adapter); | |
4483 | } | |
4484 | ||
4485 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
4486 | { | |
4487 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4488 | struct e1000_hw *hw = &adapter->hw; | |
4489 | u32 vfta, index; | |
4490 | ||
28b0759c | 4491 | if ((hw->mng_cookie.status & |
9d5c8243 AK |
4492 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && |
4493 | (vid == adapter->mng_vlan_id)) | |
4494 | return; | |
4495 | /* add VID to filter table */ | |
4496 | index = (vid >> 5) & 0x7F; | |
4497 | vfta = array_rd32(E1000_VFTA, index); | |
4498 | vfta |= (1 << (vid & 0x1F)); | |
4499 | igb_write_vfta(&adapter->hw, index, vfta); | |
4500 | } | |
4501 | ||
4502 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
4503 | { | |
4504 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4505 | struct e1000_hw *hw = &adapter->hw; | |
4506 | u32 vfta, index; | |
4507 | ||
4508 | igb_irq_disable(adapter); | |
4509 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
4510 | ||
4511 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4512 | igb_irq_enable(adapter); | |
4513 | ||
4514 | if ((adapter->hw.mng_cookie.status & | |
4515 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
4516 | (vid == adapter->mng_vlan_id)) { | |
4517 | /* release control to f/w */ | |
4518 | igb_release_hw_control(adapter); | |
4519 | return; | |
4520 | } | |
4521 | ||
4522 | /* remove VID from filter table */ | |
4523 | index = (vid >> 5) & 0x7F; | |
4524 | vfta = array_rd32(E1000_VFTA, index); | |
4525 | vfta &= ~(1 << (vid & 0x1F)); | |
4526 | igb_write_vfta(&adapter->hw, index, vfta); | |
4527 | } | |
4528 | ||
4529 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
4530 | { | |
4531 | igb_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
4532 | ||
4533 | if (adapter->vlgrp) { | |
4534 | u16 vid; | |
4535 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
4536 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
4537 | continue; | |
4538 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
4539 | } | |
4540 | } | |
4541 | } | |
4542 | ||
4543 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |
4544 | { | |
4545 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
4546 | ||
4547 | mac->autoneg = 0; | |
4548 | ||
4549 | /* Fiber NICs only allow 1000 gbps Full duplex */ | |
4550 | if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && | |
4551 | spddplx != (SPEED_1000 + DUPLEX_FULL)) { | |
4552 | dev_err(&adapter->pdev->dev, | |
4553 | "Unsupported Speed/Duplex configuration\n"); | |
4554 | return -EINVAL; | |
4555 | } | |
4556 | ||
4557 | switch (spddplx) { | |
4558 | case SPEED_10 + DUPLEX_HALF: | |
4559 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
4560 | break; | |
4561 | case SPEED_10 + DUPLEX_FULL: | |
4562 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
4563 | break; | |
4564 | case SPEED_100 + DUPLEX_HALF: | |
4565 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
4566 | break; | |
4567 | case SPEED_100 + DUPLEX_FULL: | |
4568 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
4569 | break; | |
4570 | case SPEED_1000 + DUPLEX_FULL: | |
4571 | mac->autoneg = 1; | |
4572 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
4573 | break; | |
4574 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
4575 | default: | |
4576 | dev_err(&adapter->pdev->dev, | |
4577 | "Unsupported Speed/Duplex configuration\n"); | |
4578 | return -EINVAL; | |
4579 | } | |
4580 | return 0; | |
4581 | } | |
4582 | ||
9d5c8243 AK |
4583 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) |
4584 | { | |
4585 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4586 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4587 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 4588 | u32 ctrl, rctl, status; |
9d5c8243 AK |
4589 | u32 wufc = adapter->wol; |
4590 | #ifdef CONFIG_PM | |
4591 | int retval = 0; | |
4592 | #endif | |
4593 | ||
4594 | netif_device_detach(netdev); | |
4595 | ||
a88f10ec AD |
4596 | if (netif_running(netdev)) |
4597 | igb_close(netdev); | |
4598 | ||
4599 | igb_reset_interrupt_capability(adapter); | |
4600 | ||
4601 | igb_free_queues(adapter); | |
9d5c8243 AK |
4602 | |
4603 | #ifdef CONFIG_PM | |
4604 | retval = pci_save_state(pdev); | |
4605 | if (retval) | |
4606 | return retval; | |
4607 | #endif | |
4608 | ||
4609 | status = rd32(E1000_STATUS); | |
4610 | if (status & E1000_STATUS_LU) | |
4611 | wufc &= ~E1000_WUFC_LNKC; | |
4612 | ||
4613 | if (wufc) { | |
4614 | igb_setup_rctl(adapter); | |
4615 | igb_set_multi(netdev); | |
4616 | ||
4617 | /* turn on all-multi mode if wake on multicast is enabled */ | |
4618 | if (wufc & E1000_WUFC_MC) { | |
4619 | rctl = rd32(E1000_RCTL); | |
4620 | rctl |= E1000_RCTL_MPE; | |
4621 | wr32(E1000_RCTL, rctl); | |
4622 | } | |
4623 | ||
4624 | ctrl = rd32(E1000_CTRL); | |
4625 | /* advertise wake from D3Cold */ | |
4626 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
4627 | /* phy power management enable */ | |
4628 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
4629 | ctrl |= E1000_CTRL_ADVD3WUC; | |
4630 | wr32(E1000_CTRL, ctrl); | |
4631 | ||
9d5c8243 AK |
4632 | /* Allow time for pending master requests to run */ |
4633 | igb_disable_pcie_master(&adapter->hw); | |
4634 | ||
4635 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
4636 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
4637 | } else { |
4638 | wr32(E1000_WUC, 0); | |
4639 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
4640 | } |
4641 | ||
2d064c06 AD |
4642 | /* make sure adapter isn't asleep if manageability/wol is enabled */ |
4643 | if (wufc || adapter->en_mng_pt) { | |
9d5c8243 AK |
4644 | pci_enable_wake(pdev, PCI_D3hot, 1); |
4645 | pci_enable_wake(pdev, PCI_D3cold, 1); | |
2d064c06 AD |
4646 | } else { |
4647 | igb_shutdown_fiber_serdes_link_82575(hw); | |
4648 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4649 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 AK |
4650 | } |
4651 | ||
4652 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
4653 | * would have already happened in close and is redundant. */ | |
4654 | igb_release_hw_control(adapter); | |
4655 | ||
4656 | pci_disable_device(pdev); | |
4657 | ||
4658 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
4659 | ||
4660 | return 0; | |
4661 | } | |
4662 | ||
4663 | #ifdef CONFIG_PM | |
4664 | static int igb_resume(struct pci_dev *pdev) | |
4665 | { | |
4666 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4667 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4668 | struct e1000_hw *hw = &adapter->hw; | |
4669 | u32 err; | |
4670 | ||
4671 | pci_set_power_state(pdev, PCI_D0); | |
4672 | pci_restore_state(pdev); | |
42bfd33a | 4673 | |
aed5dec3 | 4674 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
4675 | if (err) { |
4676 | dev_err(&pdev->dev, | |
4677 | "igb: Cannot enable PCI device from suspend\n"); | |
4678 | return err; | |
4679 | } | |
4680 | pci_set_master(pdev); | |
4681 | ||
4682 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4683 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4684 | ||
a88f10ec AD |
4685 | igb_set_interrupt_capability(adapter); |
4686 | ||
4687 | if (igb_alloc_queues(adapter)) { | |
4688 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
4689 | return -ENOMEM; | |
9d5c8243 AK |
4690 | } |
4691 | ||
4692 | /* e1000_power_up_phy(adapter); */ | |
4693 | ||
4694 | igb_reset(adapter); | |
a8564f03 AD |
4695 | |
4696 | /* let the f/w know that the h/w is now under the control of the | |
4697 | * driver. */ | |
4698 | igb_get_hw_control(adapter); | |
4699 | ||
9d5c8243 AK |
4700 | wr32(E1000_WUS, ~0); |
4701 | ||
a88f10ec AD |
4702 | if (netif_running(netdev)) { |
4703 | err = igb_open(netdev); | |
4704 | if (err) | |
4705 | return err; | |
4706 | } | |
9d5c8243 AK |
4707 | |
4708 | netif_device_attach(netdev); | |
4709 | ||
9d5c8243 AK |
4710 | return 0; |
4711 | } | |
4712 | #endif | |
4713 | ||
4714 | static void igb_shutdown(struct pci_dev *pdev) | |
4715 | { | |
4716 | igb_suspend(pdev, PMSG_SUSPEND); | |
4717 | } | |
4718 | ||
4719 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4720 | /* | |
4721 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4722 | * without having to re-enable interrupts. It's not called while | |
4723 | * the interrupt routine is executing. | |
4724 | */ | |
4725 | static void igb_netpoll(struct net_device *netdev) | |
4726 | { | |
4727 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 4728 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 4729 | int i; |
9d5c8243 | 4730 | |
eebbbdba AD |
4731 | if (!adapter->msix_entries) { |
4732 | igb_irq_disable(adapter); | |
4733 | napi_schedule(&adapter->rx_ring[0].napi); | |
4734 | return; | |
4735 | } | |
9d5c8243 | 4736 | |
eebbbdba AD |
4737 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4738 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
4739 | wr32(E1000_EIMC, tx_ring->eims_value); | |
4740 | igb_clean_tx_irq(tx_ring); | |
4741 | wr32(E1000_EIMS, tx_ring->eims_value); | |
4742 | } | |
9d5c8243 | 4743 | |
eebbbdba AD |
4744 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4745 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
4746 | wr32(E1000_EIMC, rx_ring->eims_value); | |
4747 | napi_schedule(&rx_ring->napi); | |
4748 | } | |
9d5c8243 AK |
4749 | } |
4750 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
4751 | ||
4752 | /** | |
4753 | * igb_io_error_detected - called when PCI error is detected | |
4754 | * @pdev: Pointer to PCI device | |
4755 | * @state: The current pci connection state | |
4756 | * | |
4757 | * This function is called after a PCI bus error affecting | |
4758 | * this device has been detected. | |
4759 | */ | |
4760 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
4761 | pci_channel_state_t state) | |
4762 | { | |
4763 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4764 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4765 | ||
4766 | netif_device_detach(netdev); | |
4767 | ||
4768 | if (netif_running(netdev)) | |
4769 | igb_down(adapter); | |
4770 | pci_disable_device(pdev); | |
4771 | ||
4772 | /* Request a slot slot reset. */ | |
4773 | return PCI_ERS_RESULT_NEED_RESET; | |
4774 | } | |
4775 | ||
4776 | /** | |
4777 | * igb_io_slot_reset - called after the pci bus has been reset. | |
4778 | * @pdev: Pointer to PCI device | |
4779 | * | |
4780 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
4781 | * resembles the first-half of the igb_resume routine. | |
4782 | */ | |
4783 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
4784 | { | |
4785 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4786 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4787 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 4788 | pci_ers_result_t result; |
42bfd33a | 4789 | int err; |
9d5c8243 | 4790 | |
aed5dec3 | 4791 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
4792 | dev_err(&pdev->dev, |
4793 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
4794 | result = PCI_ERS_RESULT_DISCONNECT; |
4795 | } else { | |
4796 | pci_set_master(pdev); | |
4797 | pci_restore_state(pdev); | |
9d5c8243 | 4798 | |
40a914fa AD |
4799 | pci_enable_wake(pdev, PCI_D3hot, 0); |
4800 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 4801 | |
40a914fa AD |
4802 | igb_reset(adapter); |
4803 | wr32(E1000_WUS, ~0); | |
4804 | result = PCI_ERS_RESULT_RECOVERED; | |
4805 | } | |
9d5c8243 | 4806 | |
ea943d41 JK |
4807 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
4808 | if (err) { | |
4809 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
4810 | "failed 0x%0x\n", err); | |
4811 | /* non-fatal, continue */ | |
4812 | } | |
40a914fa AD |
4813 | |
4814 | return result; | |
9d5c8243 AK |
4815 | } |
4816 | ||
4817 | /** | |
4818 | * igb_io_resume - called when traffic can start flowing again. | |
4819 | * @pdev: Pointer to PCI device | |
4820 | * | |
4821 | * This callback is called when the error recovery driver tells us that | |
4822 | * its OK to resume normal operation. Implementation resembles the | |
4823 | * second-half of the igb_resume routine. | |
4824 | */ | |
4825 | static void igb_io_resume(struct pci_dev *pdev) | |
4826 | { | |
4827 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4828 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4829 | ||
9d5c8243 AK |
4830 | if (netif_running(netdev)) { |
4831 | if (igb_up(adapter)) { | |
4832 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
4833 | return; | |
4834 | } | |
4835 | } | |
4836 | ||
4837 | netif_device_attach(netdev); | |
4838 | ||
4839 | /* let the f/w know that the h/w is now under the control of the | |
4840 | * driver. */ | |
4841 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
4842 | } |
4843 | ||
4844 | /* igb_main.c */ |