projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: Temporarily mark QoS support BROKEN.
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
fe4506b6
JC		 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
9d5c8243
AK		 47#include "igb.h"
48
0024fd00 49#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 50char igb_driver_name[] = "igb";
51char igb_driver_version[] = DRV_VERSION;
52static const char igb_driver_string[] =
53 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 55
9d5c8243
AK		 56static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58};
59
60static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 79static void igb_free_tx_resources(struct igb_ring *);
80static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
fe4506b6
JC		 110#ifdef CONFIG_DCA
111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
114#endif /* CONFIG_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
9d5c8243
AK		 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
123static void igb_tx_timeout(struct net_device *);
124static void igb_reset_task(struct work_struct *);
125static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
126static void igb_vlan_rx_add_vid(struct net_device *, u16);
127static void igb_vlan_rx_kill_vid(struct net_device *, u16);
128static void igb_restore_vlan(struct igb_adapter *);
129
130static int igb_suspend(struct pci_dev *, pm_message_t);
131#ifdef CONFIG_PM
132static int igb_resume(struct pci_dev *);
133#endif
134static void igb_shutdown(struct pci_dev *);
fe4506b6
JC		 135#ifdef CONFIG_DCA
136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
9d5c8243
AK		 143
144#ifdef CONFIG_NET_POLL_CONTROLLER
145/* for netdump / net console */
146static void igb_netpoll(struct net_device *);
147#endif
148
149static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
150 pci_channel_state_t);
151static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
152static void igb_io_resume(struct pci_dev *);
153
154static struct pci_error_handlers igb_err_handler = {
155 .error_detected = igb_io_error_detected,
156 .slot_reset = igb_io_slot_reset,
157 .resume = igb_io_resume,
158};
159
160
161static struct pci_driver igb_driver = {
162 .name = igb_driver_name,
163 .id_table = igb_pci_tbl,
164 .probe = igb_probe,
165 .remove = __devexit_p(igb_remove),
166#ifdef CONFIG_PM
167 /* Power Managment Hooks */
168 .suspend = igb_suspend,
169 .resume = igb_resume,
170#endif
171 .shutdown = igb_shutdown,
172 .err_handler = &igb_err_handler
173};
174
7dfc16fa
AD		 175static int global_quad_port_a; /* global quad port a indication */
176
9d5c8243
AK		 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_VERSION);
181
182#ifdef DEBUG
183/**
184 * igb_get_hw_dev_name - return device name string
185 * used by hardware layer to print debugging information
186 **/
187char *igb_get_hw_dev_name(struct e1000_hw *hw)
188{
189 struct igb_adapter *adapter = hw->back;
190 return adapter->netdev->name;
191}
192#endif
193
194/**
195 * igb_init_module - Driver Registration Routine
196 *
197 * igb_init_module is the first routine called when the driver is
198 * loaded. All it does is register with the PCI subsystem.
199 **/
200static int __init igb_init_module(void)
201{
202 int ret;
203 printk(KERN_INFO "%s - version %s\n",
204 igb_driver_string, igb_driver_version);
205
206 printk(KERN_INFO "%s\n", igb_copyright);
207
7dfc16fa
AD		 208 global_quad_port_a = 0;
209
9d5c8243 210 ret = pci_register_driver(&igb_driver);
fe4506b6
JC		 211#ifdef CONFIG_DCA
212 dca_register_notify(&dca_notifier);
213#endif
9d5c8243
AK		 214 return ret;
215}
216
217module_init(igb_init_module);
218
219/**
220 * igb_exit_module - Driver Exit Cleanup Routine
221 *
222 * igb_exit_module is called just before the driver is removed
223 * from memory.
224 **/
225static void __exit igb_exit_module(void)
226{
fe4506b6
JC		 227#ifdef CONFIG_DCA
228 dca_unregister_notify(&dca_notifier);
229#endif
9d5c8243
AK		 230 pci_unregister_driver(&igb_driver);
231}
232
233module_exit(igb_exit_module);
234
235/**
236 * igb_alloc_queues - Allocate memory for all rings
237 * @adapter: board private structure to initialize
238 *
239 * We allocate one ring per queue at run-time since we don't know the
240 * number of queues at compile-time.
241 **/
242static int igb_alloc_queues(struct igb_adapter *adapter)
243{
244 int i;
245
246 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
247 sizeof(struct igb_ring), GFP_KERNEL);
248 if (!adapter->tx_ring)
249 return -ENOMEM;
250
251 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
252 sizeof(struct igb_ring), GFP_KERNEL);
253 if (!adapter->rx_ring) {
254 kfree(adapter->tx_ring);
255 return -ENOMEM;
256 }
257
6eb5a7f1
AD		 258 adapter->rx_ring->buddy = adapter->tx_ring;
259
661086df
PWJ		 260 for (i = 0; i < adapter->num_tx_queues; i++) {
261 struct igb_ring *ring = &(adapter->tx_ring[i]);
262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
9d5c8243
AK		 265 for (i = 0; i < adapter->num_rx_queues; i++) {
266 struct igb_ring *ring = &(adapter->rx_ring[i]);
267 ring->adapter = adapter;
844290e5 268 ring->queue_index = i;
9d5c8243
AK		 269 ring->itr_register = E1000_ITR;
270
844290e5 271 /* set a default napi handler for each rx_ring */
661086df 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 273 }
274 return 0;
275}
276
a88f10ec
AD		 277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
9d5c8243
AK		 288#define IGB_N0_QUEUE -1
289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
290 int tx_queue, int msix_vector)
291{
292 u32 msixbm = 0;
293 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
9d5c8243
AK		 298 /* The 82575 assigns vectors using a bitmask, which matches the
299 bitmask for the EICR/EIMS/EIMC registers. To assign one
300 or more queues to a vector, we write the appropriate bits
301 into the MSIXBM register for that vector. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
304 adapter->rx_ring[rx_queue].eims_value = msixbm;
305 }
306 if (tx_queue > IGB_N0_QUEUE) {
307 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
308 adapter->tx_ring[tx_queue].eims_value =
309 E1000_EICR_TX_QUEUE0 << tx_queue;
310 }
311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 312 break;
313 case e1000_82576:
314 /* Kawela uses a table-based method for assigning vectors.
315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
9d5c8243
AK		 353}
354
355/**
356 * igb_configure_msix - Configure MSI-X hardware
357 *
358 * igb_configure_msix sets up the hardware to properly
359 * generate MSI-X interrupts.
360 **/
361static void igb_configure_msix(struct igb_adapter *adapter)
362{
363 u32 tmp;
364 int i, vector = 0;
365 struct e1000_hw *hw = &adapter->hw;
366
367 adapter->eims_enable_mask = 0;
2d064c06
AD		 368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
9d5c8243
AK		 374
375 for (i = 0; i < adapter->num_tx_queues; i++) {
376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
378 adapter->eims_enable_mask |= tx_ring->eims_value;
379 if (tx_ring->itr_val)
6eb5a7f1 380 writel(tx_ring->itr_val,
9d5c8243
AK		 381 hw->hw_addr + tx_ring->itr_register);
382 else
383 writel(1, hw->hw_addr + tx_ring->itr_register);
384 }
385
386 for (i = 0; i < adapter->num_rx_queues; i++) {
387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
6eb5a7f1 388 rx_ring->buddy = 0;
9d5c8243
AK		 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
390 adapter->eims_enable_mask |= rx_ring->eims_value;
391 if (rx_ring->itr_val)
6eb5a7f1 392 writel(rx_ring->itr_val,
9d5c8243
AK		 393 hw->hw_addr + rx_ring->itr_register);
394 else
395 writel(1, hw->hw_addr + rx_ring->itr_register);
396 }
397
398
399 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 400 switch (hw->mac.type) {
401 case e1000_82575:
9d5c8243
AK		 402 array_wr32(E1000_MSIXBM(0), vector++,
403 E1000_EIMS_OTHER);
404
9d5c8243
AK		 405 tmp = rd32(E1000_CTRL_EXT);
406 /* enable MSI-X PBA support*/
407 tmp |= E1000_CTRL_EXT_PBA_CLR;
408
409 /* Auto-Mask interrupts upon ICR read. */
410 tmp |= E1000_CTRL_EXT_EIAME;
411 tmp |= E1000_CTRL_EXT_IRCA;
412
413 wr32(E1000_CTRL_EXT, tmp);
414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 415 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 416
2d064c06
AD		 417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
9d5c8243
AK		 430 wrfl();
431}
432
433/**
434 * igb_request_msix - Initialize MSI-X interrupts
435 *
436 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
437 * kernel.
438 **/
439static int igb_request_msix(struct igb_adapter *adapter)
440{
441 struct net_device *netdev = adapter->netdev;
442 int i, err = 0, vector = 0;
443
444 vector = 0;
445
446 for (i = 0; i < adapter->num_tx_queues; i++) {
447 struct igb_ring *ring = &(adapter->tx_ring[i]);
448 sprintf(ring->name, "%s-tx%d", netdev->name, i);
449 err = request_irq(adapter->msix_entries[vector].vector,
450 &igb_msix_tx, 0, ring->name,
451 &(adapter->tx_ring[i]));
452 if (err)
453 goto out;
454 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 455 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 456 vector++;
457 }
458 for (i = 0; i < adapter->num_rx_queues; i++) {
459 struct igb_ring *ring = &(adapter->rx_ring[i]);
460 if (strlen(netdev->name) < (IFNAMSIZ - 5))
461 sprintf(ring->name, "%s-rx%d", netdev->name, i);
462 else
463 memcpy(ring->name, netdev->name, IFNAMSIZ);
464 err = request_irq(adapter->msix_entries[vector].vector,
465 &igb_msix_rx, 0, ring->name,
466 &(adapter->rx_ring[i]));
467 if (err)
468 goto out;
469 ring->itr_register = E1000_EITR(0) + (vector << 2);
470 ring->itr_val = adapter->itr;
844290e5
PW		 471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 474 vector++;
475 }
476
477 err = request_irq(adapter->msix_entries[vector].vector,
478 &igb_msix_other, 0, netdev->name, netdev);
479 if (err)
480 goto out;
481
9d5c8243
AK		 482 igb_configure_msix(adapter);
483 return 0;
484out:
485 return err;
486}
487
488static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
489{
490 if (adapter->msix_entries) {
491 pci_disable_msix(adapter->pdev);
492 kfree(adapter->msix_entries);
493 adapter->msix_entries = NULL;
7dfc16fa 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 495 pci_disable_msi(adapter->pdev);
496 return;
497}
498
499
500/**
501 * igb_set_interrupt_capability - set MSI or MSI-X if supported
502 *
503 * Attempt to configure interrupts using the best available
504 * capabilities of the hardware and kernel.
505 **/
506static void igb_set_interrupt_capability(struct igb_adapter *adapter)
507{
508 int err;
509 int numvecs, i;
510
511 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
512 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
513 GFP_KERNEL);
514 if (!adapter->msix_entries)
515 goto msi_only;
516
517 for (i = 0; i < numvecs; i++)
518 adapter->msix_entries[i].entry = i;
519
520 err = pci_enable_msix(adapter->pdev,
521 adapter->msix_entries,
522 numvecs);
523 if (err == 0)
524 return;
525
526 igb_reset_interrupt_capability(adapter);
527
528 /* If we can't do MSI-X, try MSI */
529msi_only:
530 adapter->num_rx_queues = 1;
661086df 531 adapter->num_tx_queues = 1;
9d5c8243 532 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 533 adapter->flags |= IGB_FLAG_HAS_MSI;
661086df 534
661086df
PWJ		 535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
536 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
9d5c8243
AK		 537 return;
538}
539
540/**
541 * igb_request_irq - initialize interrupts
542 *
543 * Attempts to configure interrupts using the best available
544 * capabilities of the hardware and kernel.
545 **/
546static int igb_request_irq(struct igb_adapter *adapter)
547{
548 struct net_device *netdev = adapter->netdev;
549 struct e1000_hw *hw = &adapter->hw;
550 int err = 0;
551
552 if (adapter->msix_entries) {
553 err = igb_request_msix(adapter);
844290e5 554 if (!err)
9d5c8243 555 goto request_done;
9d5c8243
AK		 556 /* fall back to MSI */
557 igb_reset_interrupt_capability(adapter);
558 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 559 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 560 igb_free_all_tx_resources(adapter);
561 igb_free_all_rx_resources(adapter);
562 adapter->num_rx_queues = 1;
563 igb_alloc_queues(adapter);
844290e5 564 } else {
2d064c06
AD		 565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
9d5c8243 576 }
844290e5 577
7dfc16fa 578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
580 netdev->name, netdev);
581 if (!err)
582 goto request_done;
583 /* fall back to legacy interrupts */
584 igb_reset_interrupt_capability(adapter);
7dfc16fa 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 586 }
587
588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
589 netdev->name, netdev);
590
6cb5e577 591 if (err)
9d5c8243
AK		 592 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
593 err);
9d5c8243
AK		 594
595request_done:
596 return err;
597}
598
599static void igb_free_irq(struct igb_adapter *adapter)
600{
601 struct net_device *netdev = adapter->netdev;
602
603 if (adapter->msix_entries) {
604 int vector = 0, i;
605
606 for (i = 0; i < adapter->num_tx_queues; i++)
607 free_irq(adapter->msix_entries[vector++].vector,
608 &(adapter->tx_ring[i]));
609 for (i = 0; i < adapter->num_rx_queues; i++)
610 free_irq(adapter->msix_entries[vector++].vector,
611 &(adapter->rx_ring[i]));
612
613 free_irq(adapter->msix_entries[vector++].vector, netdev);
614 return;
615 }
616
617 free_irq(adapter->pdev->irq, netdev);
618}
619
620/**
621 * igb_irq_disable - Mask off interrupt generation on the NIC
622 * @adapter: board private structure
623 **/
624static void igb_irq_disable(struct igb_adapter *adapter)
625{
626 struct e1000_hw *hw = &adapter->hw;
627
628 if (adapter->msix_entries) {
844290e5 629 wr32(E1000_EIAM, 0);
9d5c8243
AK		 630 wr32(E1000_EIMC, ~0);
631 wr32(E1000_EIAC, 0);
632 }
844290e5
PW		 633
634 wr32(E1000_IAM, 0);
9d5c8243
AK		 635 wr32(E1000_IMC, ~0);
636 wrfl();
637 synchronize_irq(adapter->pdev->irq);
638}
639
640/**
641 * igb_irq_enable - Enable default interrupt generation settings
642 * @adapter: board private structure
643 **/
644static void igb_irq_enable(struct igb_adapter *adapter)
645{
646 struct e1000_hw *hw = &adapter->hw;
647
648 if (adapter->msix_entries) {
844290e5
PW		 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
650 wr32(E1000_EIAM, adapter->eims_enable_mask);
651 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 652 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 653 } else {
654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
9d5c8243
AK		 657}
658
659static void igb_update_mng_vlan(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 u16 vid = adapter->hw.mng_cookie.vlan_id;
663 u16 old_vid = adapter->mng_vlan_id;
664 if (adapter->vlgrp) {
665 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
666 if (adapter->hw.mng_cookie.status &
667 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
668 igb_vlan_rx_add_vid(netdev, vid);
669 adapter->mng_vlan_id = vid;
670 } else
671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
672
673 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
674 (vid != old_vid) &&
675 !vlan_group_get_device(adapter->vlgrp, old_vid))
676 igb_vlan_rx_kill_vid(netdev, old_vid);
677 } else
678 adapter->mng_vlan_id = vid;
679 }
680}
681
682/**
683 * igb_release_hw_control - release control of the h/w to f/w
684 * @adapter: address of board private structure
685 *
686 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
687 * For ASF and Pass Through versions of f/w this means that the
688 * driver is no longer loaded.
689 *
690 **/
691static void igb_release_hw_control(struct igb_adapter *adapter)
692{
693 struct e1000_hw *hw = &adapter->hw;
694 u32 ctrl_ext;
695
696 /* Let firmware take over control of h/w */
697 ctrl_ext = rd32(E1000_CTRL_EXT);
698 wr32(E1000_CTRL_EXT,
699 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
700}
701
702
703/**
704 * igb_get_hw_control - get control of the h/w from f/w
705 * @adapter: address of board private structure
706 *
707 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
708 * For ASF and Pass Through versions of f/w this means that
709 * the driver is loaded.
710 *
711 **/
712static void igb_get_hw_control(struct igb_adapter *adapter)
713{
714 struct e1000_hw *hw = &adapter->hw;
715 u32 ctrl_ext;
716
717 /* Let firmware know the driver has taken over */
718 ctrl_ext = rd32(E1000_CTRL_EXT);
719 wr32(E1000_CTRL_EXT,
720 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
721}
722
723static void igb_init_manageability(struct igb_adapter *adapter)
724{
725 struct e1000_hw *hw = &adapter->hw;
726
727 if (adapter->en_mng_pt) {
728 u32 manc2h = rd32(E1000_MANC2H);
729 u32 manc = rd32(E1000_MANC);
730
9d5c8243
AK		 731 /* enable receiving management packets to the host */
732 /* this will probably generate destination unreachable messages
733 * from the host OS, but the packets will be handled on SMBUS */
734 manc |= E1000_MANC_EN_MNG2HOST;
735#define E1000_MNG2HOST_PORT_623 (1 << 5)
736#define E1000_MNG2HOST_PORT_664 (1 << 6)
737 manc2h |= E1000_MNG2HOST_PORT_623;
738 manc2h |= E1000_MNG2HOST_PORT_664;
739 wr32(E1000_MANC2H, manc2h);
740
741 wr32(E1000_MANC, manc);
742 }
743}
744
9d5c8243
AK		 745/**
746 * igb_configure - configure the hardware for RX and TX
747 * @adapter: private board structure
748 **/
749static void igb_configure(struct igb_adapter *adapter)
750{
751 struct net_device *netdev = adapter->netdev;
752 int i;
753
754 igb_get_hw_control(adapter);
755 igb_set_multi(netdev);
756
757 igb_restore_vlan(adapter);
758 igb_init_manageability(adapter);
759
760 igb_configure_tx(adapter);
761 igb_setup_rctl(adapter);
762 igb_configure_rx(adapter);
662d7205
AD		 763
764 igb_rx_fifo_flush_82575(&adapter->hw);
765
9d5c8243
AK		 766 /* call IGB_DESC_UNUSED which always leaves
767 * at least 1 descriptor unused to make sure
768 * next_to_use != next_to_clean */
769 for (i = 0; i < adapter->num_rx_queues; i++) {
770 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 771 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 772 }
773
774
775 adapter->tx_queue_len = netdev->tx_queue_len;
776}
777
778
779/**
780 * igb_up - Open the interface and prepare it to handle traffic
781 * @adapter: board private structure
782 **/
783
784int igb_up(struct igb_adapter *adapter)
785{
786 struct e1000_hw *hw = &adapter->hw;
787 int i;
788
789 /* hardware has been reset, we need to reload some things */
790 igb_configure(adapter);
791
792 clear_bit(__IGB_DOWN, &adapter->state);
793
844290e5
PW		 794 for (i = 0; i < adapter->num_rx_queues; i++)
795 napi_enable(&adapter->rx_ring[i].napi);
796 if (adapter->msix_entries)
9d5c8243 797 igb_configure_msix(adapter);
9d5c8243
AK		 798
799 /* Clear any pending interrupts. */
800 rd32(E1000_ICR);
801 igb_irq_enable(adapter);
802
803 /* Fire a link change interrupt to start the watchdog. */
804 wr32(E1000_ICS, E1000_ICS_LSC);
805 return 0;
806}
807
808void igb_down(struct igb_adapter *adapter)
809{
810 struct e1000_hw *hw = &adapter->hw;
811 struct net_device *netdev = adapter->netdev;
812 u32 tctl, rctl;
813 int i;
814
815 /* signal that we're down so the interrupt handler does not
816 * reschedule our watchdog timer */
817 set_bit(__IGB_DOWN, &adapter->state);
818
819 /* disable receives in the hardware */
820 rctl = rd32(E1000_RCTL);
821 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
822 /* flush and sleep below */
823
824 netif_stop_queue(netdev);
661086df
PWJ		 825 for (i = 0; i < adapter->num_tx_queues; i++)
826 netif_stop_subqueue(netdev, i);
9d5c8243
AK		 827
828 /* disable transmits in the hardware */
829 tctl = rd32(E1000_TCTL);
830 tctl &= ~E1000_TCTL_EN;
831 wr32(E1000_TCTL, tctl);
832 /* flush both disables and wait for them to finish */
833 wrfl();
834 msleep(10);
835
844290e5
PW		 836 for (i = 0; i < adapter->num_rx_queues; i++)
837 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 838
9d5c8243
AK		 839 igb_irq_disable(adapter);
840
841 del_timer_sync(&adapter->watchdog_timer);
842 del_timer_sync(&adapter->phy_info_timer);
843
844 netdev->tx_queue_len = adapter->tx_queue_len;
845 netif_carrier_off(netdev);
846 adapter->link_speed = 0;
847 adapter->link_duplex = 0;
848
3023682e
JK		 849 if (!pci_channel_offline(adapter->pdev))
850 igb_reset(adapter);
9d5c8243
AK		 851 igb_clean_all_tx_rings(adapter);
852 igb_clean_all_rx_rings(adapter);
853}
854
855void igb_reinit_locked(struct igb_adapter *adapter)
856{
857 WARN_ON(in_interrupt());
858 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
859 msleep(1);
860 igb_down(adapter);
861 igb_up(adapter);
862 clear_bit(__IGB_RESETTING, &adapter->state);
863}
864
865void igb_reset(struct igb_adapter *adapter)
866{
867 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 868 struct e1000_mac_info *mac = &hw->mac;
869 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 870 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
871 u16 hwm;
872
873 /* Repartition Pba for greater than 9k mtu
874 * To take effect CTRL.RST is required.
875 */
2d064c06 876 if (mac->type != e1000_82576) {
9d5c8243 877 pba = E1000_PBA_34K;
2d064c06
AD		 878 }
879 else {
880 pba = E1000_PBA_64K;
881 }
9d5c8243 882
2d064c06
AD		 883 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
884 (mac->type < e1000_82576)) {
9d5c8243
AK		 885 /* adjust PBA for jumbo frames */
886 wr32(E1000_PBA, pba);
887
888 /* To maintain wire speed transmits, the Tx FIFO should be
889 * large enough to accommodate two full transmit packets,
890 * rounded up to the next 1KB and expressed in KB. Likewise,
891 * the Rx FIFO should be large enough to accommodate at least
892 * one full receive packet and is similarly rounded up and
893 * expressed in KB. */
894 pba = rd32(E1000_PBA);
895 /* upper 16 bits has Tx packet buffer allocation size in KB */
896 tx_space = pba >> 16;
897 /* lower 16 bits has Rx packet buffer allocation size in KB */
898 pba &= 0xffff;
899 /* the tx fifo also stores 16 bytes of information about the tx
900 * but don't include ethernet FCS because hardware appends it */
901 min_tx_space = (adapter->max_frame_size +
902 sizeof(struct e1000_tx_desc) -
903 ETH_FCS_LEN) * 2;
904 min_tx_space = ALIGN(min_tx_space, 1024);
905 min_tx_space >>= 10;
906 /* software strips receive CRC, so leave room for it */
907 min_rx_space = adapter->max_frame_size;
908 min_rx_space = ALIGN(min_rx_space, 1024);
909 min_rx_space >>= 10;
910
911 /* If current Tx allocation is less than the min Tx FIFO size,
912 * and the min Tx FIFO size is less than the current Rx FIFO
913 * allocation, take space away from current Rx allocation */
914 if (tx_space < min_tx_space &&
915 ((min_tx_space - tx_space) < pba)) {
916 pba = pba - (min_tx_space - tx_space);
917
918 /* if short on rx space, rx wins and must trump tx
919 * adjustment */
920 if (pba < min_rx_space)
921 pba = min_rx_space;
922 }
2d064c06 923 wr32(E1000_PBA, pba);
9d5c8243 924 }
9d5c8243
AK		 925
926 /* flow control settings */
927 /* The high water mark must be low enough to fit one full frame
928 * (or the size used for early receive) above it in the Rx FIFO.
929 * Set it to the lower of:
930 * - 90% of the Rx FIFO size, or
931 * - the full Rx FIFO size minus one full frame */
932 hwm = min(((pba << 10) * 9 / 10),
2d064c06 933 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 934
2d064c06
AD		 935 if (mac->type < e1000_82576) {
936 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
937 fc->low_water = fc->high_water - 8;
938 } else {
939 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
940 fc->low_water = fc->high_water - 16;
941 }
9d5c8243
AK		 942 fc->pause_time = 0xFFFF;
943 fc->send_xon = 1;
944 fc->type = fc->original_type;
945
946 /* Allow time for pending master requests to run */
947 adapter->hw.mac.ops.reset_hw(&adapter->hw);
948 wr32(E1000_WUC, 0);
949
950 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
951 dev_err(&adapter->pdev->dev, "Hardware Error\n");
952
953 igb_update_mng_vlan(adapter);
954
955 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
956 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
957
958 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 959 if (adapter->hw.phy.ops.get_phy_info)
960 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 961}
962
42bfd33a
TI		 963/**
964 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
965 * @pdev: PCI device information struct
966 *
967 * Returns true if an adapter needs ioport resources
968 **/
969static int igb_is_need_ioport(struct pci_dev *pdev)
970{
971 switch (pdev->device) {
972 /* Currently there are no adapters that need ioport resources */
973 default:
974 return false;
975 }
976}
977
9d5c8243
AK		 978/**
979 * igb_probe - Device Initialization Routine
980 * @pdev: PCI device information struct
981 * @ent: entry in igb_pci_tbl
982 *
983 * Returns 0 on success, negative on failure
984 *
985 * igb_probe initializes an adapter identified by a pci_dev structure.
986 * The OS initialization, configuring of the adapter private structure,
987 * and a hardware reset occur.
988 **/
989static int __devinit igb_probe(struct pci_dev *pdev,
990 const struct pci_device_id *ent)
991{
992 struct net_device *netdev;
993 struct igb_adapter *adapter;
994 struct e1000_hw *hw;
995 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
996 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 997 int i, err, pci_using_dac;
998 u16 eeprom_data = 0;
999 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1000 u32 part_num;
42bfd33a 1001 int bars, need_ioport;
9d5c8243 1002
42bfd33a
TI		 1003 /* do not allocate ioport bars when not needed */
1004 need_ioport = igb_is_need_ioport(pdev);
1005 if (need_ioport) {
1006 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1007 err = pci_enable_device(pdev);
1008 } else {
1009 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1010 err = pci_enable_device_mem(pdev);
1011 }
9d5c8243
AK		 1012 if (err)
1013 return err;
1014
1015 pci_using_dac = 0;
1016 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1017 if (!err) {
1018 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1019 if (!err)
1020 pci_using_dac = 1;
1021 } else {
1022 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1023 if (err) {
1024 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1025 if (err) {
1026 dev_err(&pdev->dev, "No usable DMA "
1027 "configuration, aborting\n");
1028 goto err_dma;
1029 }
1030 }
1031 }
1032
42bfd33a 1033 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1034 if (err)
1035 goto err_pci_reg;
1036
1037 pci_set_master(pdev);
c682fc23 1038 pci_save_state(pdev);
9d5c8243
AK		 1039
1040 err = -ENOMEM;
661086df 1041 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1042 if (!netdev)
1043 goto err_alloc_etherdev;
1044
1045 SET_NETDEV_DEV(netdev, &pdev->dev);
1046
1047 pci_set_drvdata(pdev, netdev);
1048 adapter = netdev_priv(netdev);
1049 adapter->netdev = netdev;
1050 adapter->pdev = pdev;
1051 hw = &adapter->hw;
1052 hw->back = adapter;
1053 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1054 adapter->bars = bars;
1055 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1056
1057 mmio_start = pci_resource_start(pdev, 0);
1058 mmio_len = pci_resource_len(pdev, 0);
1059
1060 err = -EIO;
1061 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1062 if (!adapter->hw.hw_addr)
1063 goto err_ioremap;
1064
1065 netdev->open = &igb_open;
1066 netdev->stop = &igb_close;
1067 netdev->get_stats = &igb_get_stats;
1068 netdev->set_multicast_list = &igb_set_multi;
1069 netdev->set_mac_address = &igb_set_mac;
1070 netdev->change_mtu = &igb_change_mtu;
1071 netdev->do_ioctl = &igb_ioctl;
1072 igb_set_ethtool_ops(netdev);
1073 netdev->tx_timeout = &igb_tx_timeout;
1074 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1075 netdev->vlan_rx_register = igb_vlan_rx_register;
1076 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1077 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1078#ifdef CONFIG_NET_POLL_CONTROLLER
1079 netdev->poll_controller = igb_netpoll;
1080#endif
1081 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1082
1083 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1084
1085 netdev->mem_start = mmio_start;
1086 netdev->mem_end = mmio_start + mmio_len;
1087
9d5c8243
AK		 1088 /* PCI config space info */
1089 hw->vendor_id = pdev->vendor;
1090 hw->device_id = pdev->device;
1091 hw->revision_id = pdev->revision;
1092 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1093 hw->subsystem_device_id = pdev->subsystem_device;
1094
1095 /* setup the private structure */
1096 hw->back = adapter;
1097 /* Copy the default MAC, PHY and NVM function pointers */
1098 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1099 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1100 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1101 /* Initialize skew-specific constants */
1102 err = ei->get_invariants(hw);
1103 if (err)
1104 goto err_hw_init;
1105
1106 err = igb_sw_init(adapter);
1107 if (err)
1108 goto err_sw_init;
1109
1110 igb_get_bus_info_pcie(hw);
1111
7dfc16fa
AD		 1112 /* set flags */
1113 switch (hw->mac.type) {
1114 case e1000_82576:
1115 case e1000_82575:
1116 adapter->flags |= IGB_FLAG_HAS_DCA;
1117 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1118 break;
1119 default:
1120 break;
1121 }
1122
9d5c8243
AK		 1123 hw->phy.autoneg_wait_to_complete = false;
1124 hw->mac.adaptive_ifs = true;
1125
1126 /* Copper options */
1127 if (hw->phy.media_type == e1000_media_type_copper) {
1128 hw->phy.mdix = AUTO_ALL_MODES;
1129 hw->phy.disable_polarity_correction = false;
1130 hw->phy.ms_type = e1000_ms_hw_default;
1131 }
1132
1133 if (igb_check_reset_block(hw))
1134 dev_info(&pdev->dev,
1135 "PHY reset is blocked due to SOL/IDER session.\n");
1136
1137 netdev->features = NETIF_F_SG |
1138 NETIF_F_HW_CSUM |
1139 NETIF_F_HW_VLAN_TX |
1140 NETIF_F_HW_VLAN_RX |
1141 NETIF_F_HW_VLAN_FILTER;
1142
1143 netdev->features |= NETIF_F_TSO;
9d5c8243 1144 netdev->features |= NETIF_F_TSO6;
48f29ffc 1145
d3352520
AD		 1146#ifdef CONFIG_IGB_LRO
1147 netdev->features |= NETIF_F_LRO;
1148#endif
1149
48f29ffc
JK		 1150 netdev->vlan_features |= NETIF_F_TSO;
1151 netdev->vlan_features |= NETIF_F_TSO6;
1152 netdev->vlan_features |= NETIF_F_HW_CSUM;
1153 netdev->vlan_features |= NETIF_F_SG;
1154
9d5c8243
AK		 1155 if (pci_using_dac)
1156 netdev->features |= NETIF_F_HIGHDMA;
1157
1158 netdev->features |= NETIF_F_LLTX;
1159 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1160
1161 /* before reading the NVM, reset the controller to put the device in a
1162 * known good starting state */
1163 hw->mac.ops.reset_hw(hw);
1164
1165 /* make sure the NVM is good */
1166 if (igb_validate_nvm_checksum(hw) < 0) {
1167 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1168 err = -EIO;
1169 goto err_eeprom;
1170 }
1171
1172 /* copy the MAC address out of the NVM */
1173 if (hw->mac.ops.read_mac_addr(hw))
1174 dev_err(&pdev->dev, "NVM Read Error\n");
1175
1176 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1177 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1178
1179 if (!is_valid_ether_addr(netdev->perm_addr)) {
1180 dev_err(&pdev->dev, "Invalid MAC Address\n");
1181 err = -EIO;
1182 goto err_eeprom;
1183 }
1184
1185 init_timer(&adapter->watchdog_timer);
1186 adapter->watchdog_timer.function = &igb_watchdog;
1187 adapter->watchdog_timer.data = (unsigned long) adapter;
1188
1189 init_timer(&adapter->phy_info_timer);
1190 adapter->phy_info_timer.function = &igb_update_phy_info;
1191 adapter->phy_info_timer.data = (unsigned long) adapter;
1192
1193 INIT_WORK(&adapter->reset_task, igb_reset_task);
1194 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1195
1196 /* Initialize link & ring properties that are user-changeable */
1197 adapter->tx_ring->count = 256;
1198 for (i = 0; i < adapter->num_tx_queues; i++)
1199 adapter->tx_ring[i].count = adapter->tx_ring->count;
1200 adapter->rx_ring->count = 256;
1201 for (i = 0; i < adapter->num_rx_queues; i++)
1202 adapter->rx_ring[i].count = adapter->rx_ring->count;
1203
1204 adapter->fc_autoneg = true;
1205 hw->mac.autoneg = true;
1206 hw->phy.autoneg_advertised = 0x2f;
1207
1208 hw->fc.original_type = e1000_fc_default;
1209 hw->fc.type = e1000_fc_default;
1210
1211 adapter->itr_setting = 3;
1212 adapter->itr = IGB_START_ITR;
1213
1214 igb_validate_mdi_setting(hw);
1215
1216 adapter->rx_csum = 1;
1217
1218 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1219 * enable the ACPI Magic Packet filter
1220 */
1221
1222 if (hw->bus.func == 0 ||
1223 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1224 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1225 &eeprom_data);
1226
1227 if (eeprom_data & eeprom_apme_mask)
1228 adapter->eeprom_wol |= E1000_WUFC_MAG;
1229
1230 /* now that we have the eeprom settings, apply the special cases where
1231 * the eeprom may be wrong or the board simply won't support wake on
1232 * lan on a particular port */
1233 switch (pdev->device) {
1234 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1235 adapter->eeprom_wol = 0;
1236 break;
1237 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1238 case E1000_DEV_ID_82576_FIBER:
1239 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1240 /* Wake events only supported on port A for dual fiber
1241 * regardless of eeprom setting */
1242 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1243 adapter->eeprom_wol = 0;
1244 break;
7dfc16fa
AD		 1245 case E1000_DEV_ID_82576_QUAD_COPPER:
1246 /* if quad port adapter, disable WoL on all but port A */
1247 if (global_quad_port_a != 0)
1248 adapter->eeprom_wol = 0;
1249 else
1250 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1251 /* Reset for multiple quad port adapters */
1252 if (++global_quad_port_a == 4)
1253 global_quad_port_a = 0;
1254 break;
9d5c8243
AK		 1255 }
1256
1257 /* initialize the wol settings based on the eeprom settings */
1258 adapter->wol = adapter->eeprom_wol;
1259
1260 /* reset the hardware with the new settings */
1261 igb_reset(adapter);
1262
1263 /* let the f/w know that the h/w is now under the control of the
1264 * driver. */
1265 igb_get_hw_control(adapter);
1266
1267 /* tell the stack to leave us alone until igb_open() is called */
1268 netif_carrier_off(netdev);
1269 netif_stop_queue(netdev);
661086df
PWJ		 1270 for (i = 0; i < adapter->num_tx_queues; i++)
1271 netif_stop_subqueue(netdev, i);
9d5c8243
AK		 1272
1273 strcpy(netdev->name, "eth%d");
1274 err = register_netdev(netdev);
1275 if (err)
1276 goto err_register;
1277
fe4506b6 1278#ifdef CONFIG_DCA
7dfc16fa
AD		 1279 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1280 (dca_add_requester(&pdev->dev) == 0)) {
1281 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1282 dev_info(&pdev->dev, "DCA enabled\n");
1283 /* Always use CB2 mode, difference is masked
1284 * in the CB driver. */
1285 wr32(E1000_DCA_CTRL, 2);
1286 igb_setup_dca(adapter);
1287 }
1288#endif
1289
9d5c8243
AK		 1290 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1291 /* print bus type/speed/width info */
1292 dev_info(&pdev->dev,
1293 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1294 netdev->name,
1295 ((hw->bus.speed == e1000_bus_speed_2500)
1296 ? "2.5Gb/s" : "unknown"),
1297 ((hw->bus.width == e1000_bus_width_pcie_x4)
1298 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1299 ? "Width x1" : "unknown"),
1300 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1301 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1302
1303 igb_read_part_num(hw, &part_num);
1304 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1305 (part_num >> 8), (part_num & 0xff));
1306
1307 dev_info(&pdev->dev,
1308 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1309 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1310 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1311 adapter->num_rx_queues, adapter->num_tx_queues);
1312
9d5c8243
AK		 1313 return 0;
1314
1315err_register:
1316 igb_release_hw_control(adapter);
1317err_eeprom:
1318 if (!igb_check_reset_block(hw))
1319 hw->phy.ops.reset_phy(hw);
1320
1321 if (hw->flash_address)
1322 iounmap(hw->flash_address);
1323
1324 igb_remove_device(hw);
a88f10ec 1325 igb_free_queues(adapter);
9d5c8243
AK		 1326err_sw_init:
1327err_hw_init:
1328 iounmap(hw->hw_addr);
1329err_ioremap:
1330 free_netdev(netdev);
1331err_alloc_etherdev:
42bfd33a 1332 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1333err_pci_reg:
1334err_dma:
1335 pci_disable_device(pdev);
1336 return err;
1337}
1338
1339/**
1340 * igb_remove - Device Removal Routine
1341 * @pdev: PCI device information struct
1342 *
1343 * igb_remove is called by the PCI subsystem to alert the driver
1344 * that it should release a PCI device. The could be caused by a
1345 * Hot-Plug event, or because the driver is going to be removed from
1346 * memory.
1347 **/
1348static void __devexit igb_remove(struct pci_dev *pdev)
1349{
1350 struct net_device *netdev = pci_get_drvdata(pdev);
1351 struct igb_adapter *adapter = netdev_priv(netdev);
9280fa52 1352#ifdef CONFIG_DCA
fe4506b6 1353 struct e1000_hw *hw = &adapter->hw;
9280fa52 1354#endif
9d5c8243
AK		 1355
1356 /* flush_scheduled work may reschedule our watchdog task, so
1357 * explicitly disable watchdog tasks from being rescheduled */
1358 set_bit(__IGB_DOWN, &adapter->state);
1359 del_timer_sync(&adapter->watchdog_timer);
1360 del_timer_sync(&adapter->phy_info_timer);
1361
1362 flush_scheduled_work();
1363
fe4506b6 1364#ifdef CONFIG_DCA
7dfc16fa 1365 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1366 dev_info(&pdev->dev, "DCA disabled\n");
1367 dca_remove_requester(&pdev->dev);
7dfc16fa 1368 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1369 wr32(E1000_DCA_CTRL, 1);
1370 }
1371#endif
1372
9d5c8243
AK		 1373 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1374 * would have already happened in close and is redundant. */
1375 igb_release_hw_control(adapter);
1376
1377 unregister_netdev(netdev);
1378
1379 if (!igb_check_reset_block(&adapter->hw))
1380 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1381
1382 igb_remove_device(&adapter->hw);
1383 igb_reset_interrupt_capability(adapter);
1384
a88f10ec 1385 igb_free_queues(adapter);
9d5c8243
AK		 1386
1387 iounmap(adapter->hw.hw_addr);
1388 if (adapter->hw.flash_address)
1389 iounmap(adapter->hw.flash_address);
42bfd33a 1390 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1391
1392 free_netdev(netdev);
1393
1394 pci_disable_device(pdev);
1395}
1396
1397/**
1398 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1399 * @adapter: board private structure to initialize
1400 *
1401 * igb_sw_init initializes the Adapter private data structure.
1402 * Fields are initialized based on PCI device information and
1403 * OS network device settings (MTU size).
1404 **/
1405static int __devinit igb_sw_init(struct igb_adapter *adapter)
1406{
1407 struct e1000_hw *hw = &adapter->hw;
1408 struct net_device *netdev = adapter->netdev;
1409 struct pci_dev *pdev = adapter->pdev;
1410
1411 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1412
1413 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1414 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1415 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1416 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1417
1418 /* Number of supported queues. */
1419 /* Having more queues than CPUs doesn't make sense. */
661086df 1420 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1421 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1422
661086df
PWJ		 1423 /* This call may decrease the number of queues depending on
1424 * interrupt mode. */
9d5c8243
AK		 1425 igb_set_interrupt_capability(adapter);
1426
1427 if (igb_alloc_queues(adapter)) {
1428 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1429 return -ENOMEM;
1430 }
1431
1432 /* Explicitly disable IRQ since the NIC can be in any state. */
1433 igb_irq_disable(adapter);
1434
1435 set_bit(__IGB_DOWN, &adapter->state);
1436 return 0;
1437}
1438
1439/**
1440 * igb_open - Called when a network interface is made active
1441 * @netdev: network interface device structure
1442 *
1443 * Returns 0 on success, negative value on failure
1444 *
1445 * The open entry point is called when a network interface is made
1446 * active by the system (IFF_UP). At this point all resources needed
1447 * for transmit and receive operations are allocated, the interrupt
1448 * handler is registered with the OS, the watchdog timer is started,
1449 * and the stack is notified that the interface is ready.
1450 **/
1451static int igb_open(struct net_device *netdev)
1452{
1453 struct igb_adapter *adapter = netdev_priv(netdev);
1454 struct e1000_hw *hw = &adapter->hw;
1455 int err;
1456 int i;
1457
1458 /* disallow open during test */
1459 if (test_bit(__IGB_TESTING, &adapter->state))
1460 return -EBUSY;
1461
1462 /* allocate transmit descriptors */
1463 err = igb_setup_all_tx_resources(adapter);
1464 if (err)
1465 goto err_setup_tx;
1466
1467 /* allocate receive descriptors */
1468 err = igb_setup_all_rx_resources(adapter);
1469 if (err)
1470 goto err_setup_rx;
1471
1472 /* e1000_power_up_phy(adapter); */
1473
1474 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1475 if ((adapter->hw.mng_cookie.status &
1476 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1477 igb_update_mng_vlan(adapter);
1478
1479 /* before we allocate an interrupt, we must be ready to handle it.
1480 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1481 * as soon as we call pci_request_irq, so we have to setup our
1482 * clean_rx handler before we do so. */
1483 igb_configure(adapter);
1484
1485 err = igb_request_irq(adapter);
1486 if (err)
1487 goto err_req_irq;
1488
1489 /* From here on the code is the same as igb_up() */
1490 clear_bit(__IGB_DOWN, &adapter->state);
1491
844290e5
PW		 1492 for (i = 0; i < adapter->num_rx_queues; i++)
1493 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1494
1495 /* Clear any pending interrupts. */
1496 rd32(E1000_ICR);
844290e5
PW		 1497
1498 igb_irq_enable(adapter);
1499
9d5c8243
AK		 1500 /* Fire a link status change interrupt to start the watchdog. */
1501 wr32(E1000_ICS, E1000_ICS_LSC);
1502
1503 return 0;
1504
1505err_req_irq:
1506 igb_release_hw_control(adapter);
1507 /* e1000_power_down_phy(adapter); */
1508 igb_free_all_rx_resources(adapter);
1509err_setup_rx:
1510 igb_free_all_tx_resources(adapter);
1511err_setup_tx:
1512 igb_reset(adapter);
1513
1514 return err;
1515}
1516
1517/**
1518 * igb_close - Disables a network interface
1519 * @netdev: network interface device structure
1520 *
1521 * Returns 0, this is not allowed to fail
1522 *
1523 * The close entry point is called when an interface is de-activated
1524 * by the OS. The hardware is still under the driver's control, but
1525 * needs to be disabled. A global MAC reset is issued to stop the
1526 * hardware, and all transmit and receive resources are freed.
1527 **/
1528static int igb_close(struct net_device *netdev)
1529{
1530 struct igb_adapter *adapter = netdev_priv(netdev);
1531
1532 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1533 igb_down(adapter);
1534
1535 igb_free_irq(adapter);
1536
1537 igb_free_all_tx_resources(adapter);
1538 igb_free_all_rx_resources(adapter);
1539
1540 /* kill manageability vlan ID if supported, but not if a vlan with
1541 * the same ID is registered on the host OS (let 8021q kill it) */
1542 if ((adapter->hw.mng_cookie.status &
1543 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1544 !(adapter->vlgrp &&
1545 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1546 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1547
1548 return 0;
1549}
1550
1551/**
1552 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1553 * @adapter: board private structure
1554 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1555 *
1556 * Return 0 on success, negative on failure
1557 **/
1558
1559int igb_setup_tx_resources(struct igb_adapter *adapter,
1560 struct igb_ring *tx_ring)
1561{
1562 struct pci_dev *pdev = adapter->pdev;
1563 int size;
1564
1565 size = sizeof(struct igb_buffer) * tx_ring->count;
1566 tx_ring->buffer_info = vmalloc(size);
1567 if (!tx_ring->buffer_info)
1568 goto err;
1569 memset(tx_ring->buffer_info, 0, size);
1570
1571 /* round up to nearest 4K */
1572 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1573 + sizeof(u32);
1574 tx_ring->size = ALIGN(tx_ring->size, 4096);
1575
1576 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1577 &tx_ring->dma);
1578
1579 if (!tx_ring->desc)
1580 goto err;
1581
1582 tx_ring->adapter = adapter;
1583 tx_ring->next_to_use = 0;
1584 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1585 return 0;
1586
1587err:
1588 vfree(tx_ring->buffer_info);
1589 dev_err(&adapter->pdev->dev,
1590 "Unable to allocate memory for the transmit descriptor ring\n");
1591 return -ENOMEM;
1592}
1593
1594/**
1595 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1596 * (Descriptors) for all queues
1597 * @adapter: board private structure
1598 *
1599 * Return 0 on success, negative on failure
1600 **/
1601static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1602{
1603 int i, err = 0;
661086df 1604 int r_idx;
9d5c8243
AK		 1605
1606 for (i = 0; i < adapter->num_tx_queues; i++) {
1607 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1608 if (err) {
1609 dev_err(&adapter->pdev->dev,
1610 "Allocation for Tx Queue %u failed\n", i);
1611 for (i--; i >= 0; i--)
3b644cf6 1612 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1613 break;
1614 }
1615 }
1616
661086df
PWJ		 1617 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1618 r_idx = i % adapter->num_tx_queues;
1619 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1620 }
9d5c8243
AK		 1621 return err;
1622}
1623
1624/**
1625 * igb_configure_tx - Configure transmit Unit after Reset
1626 * @adapter: board private structure
1627 *
1628 * Configure the Tx unit of the MAC after a reset.
1629 **/
1630static void igb_configure_tx(struct igb_adapter *adapter)
1631{
1632 u64 tdba, tdwba;
1633 struct e1000_hw *hw = &adapter->hw;
1634 u32 tctl;
1635 u32 txdctl, txctrl;
1636 int i;
1637
1638 for (i = 0; i < adapter->num_tx_queues; i++) {
1639 struct igb_ring *ring = &(adapter->tx_ring[i]);
1640
1641 wr32(E1000_TDLEN(i),
1642 ring->count * sizeof(struct e1000_tx_desc));
1643 tdba = ring->dma;
1644 wr32(E1000_TDBAL(i),
1645 tdba & 0x00000000ffffffffULL);
1646 wr32(E1000_TDBAH(i), tdba >> 32);
1647
1648 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1649 tdwba |= 1; /* enable head wb */
1650 wr32(E1000_TDWBAL(i),
1651 tdwba & 0x00000000ffffffffULL);
1652 wr32(E1000_TDWBAH(i), tdwba >> 32);
1653
1654 ring->head = E1000_TDH(i);
1655 ring->tail = E1000_TDT(i);
1656 writel(0, hw->hw_addr + ring->tail);
1657 writel(0, hw->hw_addr + ring->head);
1658 txdctl = rd32(E1000_TXDCTL(i));
1659 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1660 wr32(E1000_TXDCTL(i), txdctl);
1661
1662 /* Turn off Relaxed Ordering on head write-backs. The
1663 * writebacks MUST be delivered in order or it will
1664 * completely screw up our bookeeping.
1665 */
1666 txctrl = rd32(E1000_DCA_TXCTRL(i));
1667 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1668 wr32(E1000_DCA_TXCTRL(i), txctrl);
1669 }
1670
1671
1672
1673 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1674
1675 /* Program the Transmit Control Register */
1676
1677 tctl = rd32(E1000_TCTL);
1678 tctl &= ~E1000_TCTL_CT;
1679 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1680 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1681
1682 igb_config_collision_dist(hw);
1683
1684 /* Setup Transmit Descriptor Settings for eop descriptor */
1685 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1686
1687 /* Enable transmits */
1688 tctl |= E1000_TCTL_EN;
1689
1690 wr32(E1000_TCTL, tctl);
1691}
1692
1693/**
1694 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1695 * @adapter: board private structure
1696 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1697 *
1698 * Returns 0 on success, negative on failure
1699 **/
1700
1701int igb_setup_rx_resources(struct igb_adapter *adapter,
1702 struct igb_ring *rx_ring)
1703{
1704 struct pci_dev *pdev = adapter->pdev;
1705 int size, desc_len;
1706
d3352520
AD		 1707#ifdef CONFIG_IGB_LRO
1708 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1709 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1710 if (!rx_ring->lro_mgr.lro_arr)
1711 goto err;
1712 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1713#endif
1714
9d5c8243
AK		 1715 size = sizeof(struct igb_buffer) * rx_ring->count;
1716 rx_ring->buffer_info = vmalloc(size);
1717 if (!rx_ring->buffer_info)
1718 goto err;
1719 memset(rx_ring->buffer_info, 0, size);
1720
1721 desc_len = sizeof(union e1000_adv_rx_desc);
1722
1723 /* Round up to nearest 4K */
1724 rx_ring->size = rx_ring->count * desc_len;
1725 rx_ring->size = ALIGN(rx_ring->size, 4096);
1726
1727 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1728 &rx_ring->dma);
1729
1730 if (!rx_ring->desc)
1731 goto err;
1732
1733 rx_ring->next_to_clean = 0;
1734 rx_ring->next_to_use = 0;
9d5c8243
AK		 1735
1736 rx_ring->adapter = adapter;
9d5c8243
AK		 1737
1738 return 0;
1739
1740err:
d3352520
AD		 1741#ifdef CONFIG_IGB_LRO
1742 vfree(rx_ring->lro_mgr.lro_arr);
1743 rx_ring->lro_mgr.lro_arr = NULL;
1744#endif
9d5c8243
AK		 1745 vfree(rx_ring->buffer_info);
1746 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1747 "the receive descriptor ring\n");
1748 return -ENOMEM;
1749}
1750
1751/**
1752 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1753 * (Descriptors) for all queues
1754 * @adapter: board private structure
1755 *
1756 * Return 0 on success, negative on failure
1757 **/
1758static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1759{
1760 int i, err = 0;
1761
1762 for (i = 0; i < adapter->num_rx_queues; i++) {
1763 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1764 if (err) {
1765 dev_err(&adapter->pdev->dev,
1766 "Allocation for Rx Queue %u failed\n", i);
1767 for (i--; i >= 0; i--)
3b644cf6 1768 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1769 break;
1770 }
1771 }
1772
1773 return err;
1774}
1775
1776/**
1777 * igb_setup_rctl - configure the receive control registers
1778 * @adapter: Board private structure
1779 **/
1780static void igb_setup_rctl(struct igb_adapter *adapter)
1781{
1782 struct e1000_hw *hw = &adapter->hw;
1783 u32 rctl;
1784 u32 srrctl = 0;
1785 int i;
1786
1787 rctl = rd32(E1000_RCTL);
1788
1789 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1790
1791 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1792 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1793 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1794
87cb7e8c
AK		 1795 /*
1796 * enable stripping of CRC. It's unlikely this will break BMC
1797 * redirection as it did with e1000. Newer features require
1798 * that the HW strips the CRC.
9d5c8243 1799 */
87cb7e8c 1800 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1801
1802 rctl &= ~E1000_RCTL_SBP;
1803
1804 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1805 rctl &= ~E1000_RCTL_LPE;
1806 else
1807 rctl |= E1000_RCTL_LPE;
1808 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1809 /* Setup buffer sizes */
1810 rctl &= ~E1000_RCTL_SZ_4096;
1811 rctl |= E1000_RCTL_BSEX;
1812 switch (adapter->rx_buffer_len) {
1813 case IGB_RXBUFFER_256:
1814 rctl |= E1000_RCTL_SZ_256;
1815 rctl &= ~E1000_RCTL_BSEX;
1816 break;
1817 case IGB_RXBUFFER_512:
1818 rctl |= E1000_RCTL_SZ_512;
1819 rctl &= ~E1000_RCTL_BSEX;
1820 break;
1821 case IGB_RXBUFFER_1024:
1822 rctl |= E1000_RCTL_SZ_1024;
1823 rctl &= ~E1000_RCTL_BSEX;
1824 break;
1825 case IGB_RXBUFFER_2048:
1826 default:
1827 rctl |= E1000_RCTL_SZ_2048;
1828 rctl &= ~E1000_RCTL_BSEX;
1829 break;
9d5c8243
AK		 1830 }
1831 } else {
1832 rctl &= ~E1000_RCTL_BSEX;
1833 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1834 }
1835
1836 /* 82575 and greater support packet-split where the protocol
1837 * header is placed in skb->data and the packet data is
1838 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1839 * In the case of a non-split, skb->data is linearly filled,
1840 * followed by the page buffers. Therefore, skb->data is
1841 * sized to hold the largest protocol header.
1842 */
1843 /* allocations using alloc_page take too long for regular MTU
1844 * so only enable packet split for jumbo frames */
1845 if (rctl & E1000_RCTL_LPE) {
1846 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1847 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1848 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1849 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1850 } else {
1851 adapter->rx_ps_hdr_size = 0;
1852 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1853 }
1854
1855 for (i = 0; i < adapter->num_rx_queues; i++)
1856 wr32(E1000_SRRCTL(i), srrctl);
1857
1858 wr32(E1000_RCTL, rctl);
1859}
1860
1861/**
1862 * igb_configure_rx - Configure receive Unit after Reset
1863 * @adapter: board private structure
1864 *
1865 * Configure the Rx unit of the MAC after a reset.
1866 **/
1867static void igb_configure_rx(struct igb_adapter *adapter)
1868{
1869 u64 rdba;
1870 struct e1000_hw *hw = &adapter->hw;
1871 u32 rctl, rxcsum;
1872 u32 rxdctl;
1873 int i;
1874
1875 /* disable receives while setting up the descriptors */
1876 rctl = rd32(E1000_RCTL);
1877 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1878 wrfl();
1879 mdelay(10);
1880
1881 if (adapter->itr_setting > 3)
6eb5a7f1 1882 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1883
1884 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1885 * the Base and Length of the Rx Descriptor Ring */
1886 for (i = 0; i < adapter->num_rx_queues; i++) {
1887 struct igb_ring *ring = &(adapter->rx_ring[i]);
1888 rdba = ring->dma;
1889 wr32(E1000_RDBAL(i),
1890 rdba & 0x00000000ffffffffULL);
1891 wr32(E1000_RDBAH(i), rdba >> 32);
1892 wr32(E1000_RDLEN(i),
1893 ring->count * sizeof(union e1000_adv_rx_desc));
1894
1895 ring->head = E1000_RDH(i);
1896 ring->tail = E1000_RDT(i);
1897 writel(0, hw->hw_addr + ring->tail);
1898 writel(0, hw->hw_addr + ring->head);
1899
1900 rxdctl = rd32(E1000_RXDCTL(i));
1901 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1902 rxdctl &= 0xFFF00000;
1903 rxdctl |= IGB_RX_PTHRESH;
1904 rxdctl |= IGB_RX_HTHRESH << 8;
1905 rxdctl |= IGB_RX_WTHRESH << 16;
1906 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1907#ifdef CONFIG_IGB_LRO
1908 /* Intitial LRO Settings */
1909 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1910 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1911 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1912 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1913 ring->lro_mgr.dev = adapter->netdev;
1914 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1915 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1916#endif
9d5c8243
AK		 1917 }
1918
1919 if (adapter->num_rx_queues > 1) {
1920 u32 random[10];
1921 u32 mrqc;
1922 u32 j, shift;
1923 union e1000_reta {
1924 u32 dword;
1925 u8 bytes[4];
1926 } reta;
1927
1928 get_random_bytes(&random[0], 40);
1929
2d064c06
AD		 1930 if (hw->mac.type >= e1000_82576)
1931 shift = 0;
1932 else
1933 shift = 6;
9d5c8243
AK		 1934 for (j = 0; j < (32 * 4); j++) {
1935 reta.bytes[j & 3] =
1936 (j % adapter->num_rx_queues) << shift;
1937 if ((j & 3) == 3)
1938 writel(reta.dword,
1939 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1940 }
1941 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1942
1943 /* Fill out hash function seeds */
1944 for (j = 0; j < 10; j++)
1945 array_wr32(E1000_RSSRK(0), j, random[j]);
1946
1947 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1948 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1949 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1950 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1951 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1952 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1953 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1954 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1955
1956
1957 wr32(E1000_MRQC, mrqc);
1958
1959 /* Multiqueue and raw packet checksumming are mutually
1960 * exclusive. Note that this not the same as TCP/IP
1961 * checksumming, which works fine. */
1962 rxcsum = rd32(E1000_RXCSUM);
1963 rxcsum |= E1000_RXCSUM_PCSD;
1964 wr32(E1000_RXCSUM, rxcsum);
1965 } else {
1966 /* Enable Receive Checksum Offload for TCP and UDP */
1967 rxcsum = rd32(E1000_RXCSUM);
1968 if (adapter->rx_csum) {
1969 rxcsum |= E1000_RXCSUM_TUOFL;
1970
1971 /* Enable IPv4 payload checksum for UDP fragments
1972 * Must be used in conjunction with packet-split. */
1973 if (adapter->rx_ps_hdr_size)
1974 rxcsum |= E1000_RXCSUM_IPPCSE;
1975 } else {
1976 rxcsum &= ~E1000_RXCSUM_TUOFL;
1977 /* don't need to clear IPPCSE as it defaults to 0 */
1978 }
1979 wr32(E1000_RXCSUM, rxcsum);
1980 }
1981
1982 if (adapter->vlgrp)
1983 wr32(E1000_RLPML,
1984 adapter->max_frame_size + VLAN_TAG_SIZE);
1985 else
1986 wr32(E1000_RLPML, adapter->max_frame_size);
1987
1988 /* Enable Receives */
1989 wr32(E1000_RCTL, rctl);
1990}
1991
1992/**
1993 * igb_free_tx_resources - Free Tx Resources per Queue
1994 * @adapter: board private structure
1995 * @tx_ring: Tx descriptor ring for a specific queue
1996 *
1997 * Free all transmit software resources
1998 **/
3b644cf6 1999static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2000{
3b644cf6 2001 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2002
3b644cf6 2003 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2004
2005 vfree(tx_ring->buffer_info);
2006 tx_ring->buffer_info = NULL;
2007
2008 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2009
2010 tx_ring->desc = NULL;
2011}
2012
2013/**
2014 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2015 * @adapter: board private structure
2016 *
2017 * Free all transmit software resources
2018 **/
2019static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2020{
2021 int i;
2022
2023 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2024 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2025}
2026
2027static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2028 struct igb_buffer *buffer_info)
2029{
2030 if (buffer_info->dma) {
2031 pci_unmap_page(adapter->pdev,
2032 buffer_info->dma,
2033 buffer_info->length,
2034 PCI_DMA_TODEVICE);
2035 buffer_info->dma = 0;
2036 }
2037 if (buffer_info->skb) {
2038 dev_kfree_skb_any(buffer_info->skb);
2039 buffer_info->skb = NULL;
2040 }
2041 buffer_info->time_stamp = 0;
2042 /* buffer_info must be completely set up in the transmit path */
2043}
2044
2045/**
2046 * igb_clean_tx_ring - Free Tx Buffers
2047 * @adapter: board private structure
2048 * @tx_ring: ring to be cleaned
2049 **/
3b644cf6 2050static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2051{
3b644cf6 2052 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2053 struct igb_buffer *buffer_info;
2054 unsigned long size;
2055 unsigned int i;
2056
2057 if (!tx_ring->buffer_info)
2058 return;
2059 /* Free all the Tx ring sk_buffs */
2060
2061 for (i = 0; i < tx_ring->count; i++) {
2062 buffer_info = &tx_ring->buffer_info[i];
2063 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2064 }
2065
2066 size = sizeof(struct igb_buffer) * tx_ring->count;
2067 memset(tx_ring->buffer_info, 0, size);
2068
2069 /* Zero out the descriptor ring */
2070
2071 memset(tx_ring->desc, 0, tx_ring->size);
2072
2073 tx_ring->next_to_use = 0;
2074 tx_ring->next_to_clean = 0;
2075
2076 writel(0, adapter->hw.hw_addr + tx_ring->head);
2077 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2078}
2079
2080/**
2081 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2082 * @adapter: board private structure
2083 **/
2084static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2085{
2086 int i;
2087
2088 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2089 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2090}
2091
2092/**
2093 * igb_free_rx_resources - Free Rx Resources
2094 * @adapter: board private structure
2095 * @rx_ring: ring to clean the resources from
2096 *
2097 * Free all receive software resources
2098 **/
3b644cf6 2099static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2100{
3b644cf6 2101 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2102
3b644cf6 2103 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2104
2105 vfree(rx_ring->buffer_info);
2106 rx_ring->buffer_info = NULL;
2107
d3352520
AD		 2108#ifdef CONFIG_IGB_LRO
2109 vfree(rx_ring->lro_mgr.lro_arr);
2110 rx_ring->lro_mgr.lro_arr = NULL;
2111#endif
2112
9d5c8243
AK		 2113 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2114
2115 rx_ring->desc = NULL;
2116}
2117
2118/**
2119 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2120 * @adapter: board private structure
2121 *
2122 * Free all receive software resources
2123 **/
2124static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2125{
2126 int i;
2127
2128 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2129 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2130}
2131
2132/**
2133 * igb_clean_rx_ring - Free Rx Buffers per Queue
2134 * @adapter: board private structure
2135 * @rx_ring: ring to free buffers from
2136 **/
3b644cf6 2137static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2138{
3b644cf6 2139 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2140 struct igb_buffer *buffer_info;
2141 struct pci_dev *pdev = adapter->pdev;
2142 unsigned long size;
2143 unsigned int i;
2144
2145 if (!rx_ring->buffer_info)
2146 return;
2147 /* Free all the Rx ring sk_buffs */
2148 for (i = 0; i < rx_ring->count; i++) {
2149 buffer_info = &rx_ring->buffer_info[i];
2150 if (buffer_info->dma) {
2151 if (adapter->rx_ps_hdr_size)
2152 pci_unmap_single(pdev, buffer_info->dma,
2153 adapter->rx_ps_hdr_size,
2154 PCI_DMA_FROMDEVICE);
2155 else
2156 pci_unmap_single(pdev, buffer_info->dma,
2157 adapter->rx_buffer_len,
2158 PCI_DMA_FROMDEVICE);
2159 buffer_info->dma = 0;
2160 }
2161
2162 if (buffer_info->skb) {
2163 dev_kfree_skb(buffer_info->skb);
2164 buffer_info->skb = NULL;
2165 }
2166 if (buffer_info->page) {
bf36c1a0
AD		 2167 if (buffer_info->page_dma)
2168 pci_unmap_page(pdev, buffer_info->page_dma,
2169 PAGE_SIZE / 2,
2170 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2171 put_page(buffer_info->page);
2172 buffer_info->page = NULL;
2173 buffer_info->page_dma = 0;
bf36c1a0 2174 buffer_info->page_offset = 0;
9d5c8243
AK		 2175 }
2176 }
2177
9d5c8243
AK		 2178 size = sizeof(struct igb_buffer) * rx_ring->count;
2179 memset(rx_ring->buffer_info, 0, size);
2180
2181 /* Zero out the descriptor ring */
2182 memset(rx_ring->desc, 0, rx_ring->size);
2183
2184 rx_ring->next_to_clean = 0;
2185 rx_ring->next_to_use = 0;
2186
2187 writel(0, adapter->hw.hw_addr + rx_ring->head);
2188 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2189}
2190
2191/**
2192 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2193 * @adapter: board private structure
2194 **/
2195static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2196{
2197 int i;
2198
2199 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2200 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2201}
2202
2203/**
2204 * igb_set_mac - Change the Ethernet Address of the NIC
2205 * @netdev: network interface device structure
2206 * @p: pointer to an address structure
2207 *
2208 * Returns 0 on success, negative on failure
2209 **/
2210static int igb_set_mac(struct net_device *netdev, void *p)
2211{
2212 struct igb_adapter *adapter = netdev_priv(netdev);
2213 struct sockaddr *addr = p;
2214
2215 if (!is_valid_ether_addr(addr->sa_data))
2216 return -EADDRNOTAVAIL;
2217
2218 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2219 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2220
2221 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2222
2223 return 0;
2224}
2225
2226/**
2227 * igb_set_multi - Multicast and Promiscuous mode set
2228 * @netdev: network interface device structure
2229 *
2230 * The set_multi entry point is called whenever the multicast address
2231 * list or the network interface flags are updated. This routine is
2232 * responsible for configuring the hardware for proper multicast,
2233 * promiscuous mode, and all-multi behavior.
2234 **/
2235static void igb_set_multi(struct net_device *netdev)
2236{
2237 struct igb_adapter *adapter = netdev_priv(netdev);
2238 struct e1000_hw *hw = &adapter->hw;
2239 struct e1000_mac_info *mac = &hw->mac;
2240 struct dev_mc_list *mc_ptr;
2241 u8 *mta_list;
2242 u32 rctl;
2243 int i;
2244
2245 /* Check for Promiscuous and All Multicast modes */
2246
2247 rctl = rd32(E1000_RCTL);
2248
746b9f02 2249 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2250 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2251 rctl &= ~E1000_RCTL_VFE;
2252 } else {
2253 if (netdev->flags & IFF_ALLMULTI) {
2254 rctl |= E1000_RCTL_MPE;
2255 rctl &= ~E1000_RCTL_UPE;
2256 } else
2257 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2258 rctl |= E1000_RCTL_VFE;
746b9f02 2259 }
9d5c8243
AK		 2260 wr32(E1000_RCTL, rctl);
2261
2262 if (!netdev->mc_count) {
2263 /* nothing to program, so clear mc list */
2d064c06 2264 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2265 mac->rar_entry_count);
2266 return;
2267 }
2268
2269 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2270 if (!mta_list)
2271 return;
2272
2273 /* The shared function expects a packed array of only addresses. */
2274 mc_ptr = netdev->mc_list;
2275
2276 for (i = 0; i < netdev->mc_count; i++) {
2277 if (!mc_ptr)
2278 break;
2279 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2280 mc_ptr = mc_ptr->next;
2281 }
2d064c06
AD		 2282 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2283 mac->rar_entry_count);
9d5c8243
AK		 2284 kfree(mta_list);
2285}
2286
2287/* Need to wait a few seconds after link up to get diagnostic information from
2288 * the phy */
2289static void igb_update_phy_info(unsigned long data)
2290{
2291 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2292 if (adapter->hw.phy.ops.get_phy_info)
2293 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2294}
2295
2296/**
2297 * igb_watchdog - Timer Call-back
2298 * @data: pointer to adapter cast into an unsigned long
2299 **/
2300static void igb_watchdog(unsigned long data)
2301{
2302 struct igb_adapter *adapter = (struct igb_adapter *)data;
2303 /* Do the rest outside of interrupt context */
2304 schedule_work(&adapter->watchdog_task);
2305}
2306
2307static void igb_watchdog_task(struct work_struct *work)
2308{
2309 struct igb_adapter *adapter = container_of(work,
2310 struct igb_adapter, watchdog_task);
2311 struct e1000_hw *hw = &adapter->hw;
2312
2313 struct net_device *netdev = adapter->netdev;
2314 struct igb_ring *tx_ring = adapter->tx_ring;
2315 struct e1000_mac_info *mac = &adapter->hw.mac;
2316 u32 link;
2317 s32 ret_val;
661086df 2318 int i;
9d5c8243
AK		 2319
2320 if ((netif_carrier_ok(netdev)) &&
2321 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2322 goto link_up;
2323
2324 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2325 if ((ret_val == E1000_ERR_PHY) &&
2326 (hw->phy.type == e1000_phy_igp_3) &&
2327 (rd32(E1000_CTRL) &
2328 E1000_PHY_CTRL_GBE_DISABLE))
2329 dev_info(&adapter->pdev->dev,
2330 "Gigabit has been disabled, downgrading speed\n");
2331
2332 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2333 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2334 link = mac->serdes_has_link;
2335 else
2336 link = rd32(E1000_STATUS) &
2337 E1000_STATUS_LU;
2338
2339 if (link) {
2340 if (!netif_carrier_ok(netdev)) {
2341 u32 ctrl;
2342 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2343 &adapter->link_speed,
2344 &adapter->link_duplex);
2345
2346 ctrl = rd32(E1000_CTRL);
2347 dev_info(&adapter->pdev->dev,
2348 "NIC Link is Up %d Mbps %s, "
2349 "Flow Control: %s\n",
2350 adapter->link_speed,
2351 adapter->link_duplex == FULL_DUPLEX ?
2352 "Full Duplex" : "Half Duplex",
2353 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2354 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2355 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2356 E1000_CTRL_TFCE) ? "TX" : "None")));
2357
2358 /* tweak tx_queue_len according to speed/duplex and
2359 * adjust the timeout factor */
2360 netdev->tx_queue_len = adapter->tx_queue_len;
2361 adapter->tx_timeout_factor = 1;
2362 switch (adapter->link_speed) {
2363 case SPEED_10:
2364 netdev->tx_queue_len = 10;
2365 adapter->tx_timeout_factor = 14;
2366 break;
2367 case SPEED_100:
2368 netdev->tx_queue_len = 100;
2369 /* maybe add some timeout factor ? */
2370 break;
2371 }
2372
2373 netif_carrier_on(netdev);
2374 netif_wake_queue(netdev);
661086df
PWJ		 2375 for (i = 0; i < adapter->num_tx_queues; i++)
2376 netif_wake_subqueue(netdev, i);
9d5c8243
AK		 2377
2378 if (!test_bit(__IGB_DOWN, &adapter->state))
2379 mod_timer(&adapter->phy_info_timer,
2380 round_jiffies(jiffies + 2 * HZ));
2381 }
2382 } else {
2383 if (netif_carrier_ok(netdev)) {
2384 adapter->link_speed = 0;
2385 adapter->link_duplex = 0;
2386 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2387 netif_carrier_off(netdev);
2388 netif_stop_queue(netdev);
661086df
PWJ		 2389 for (i = 0; i < adapter->num_tx_queues; i++)
2390 netif_stop_subqueue(netdev, i);
9d5c8243
AK		 2391 if (!test_bit(__IGB_DOWN, &adapter->state))
2392 mod_timer(&adapter->phy_info_timer,
2393 round_jiffies(jiffies + 2 * HZ));
2394 }
2395 }
2396
2397link_up:
2398 igb_update_stats(adapter);
2399
2400 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2401 adapter->tpt_old = adapter->stats.tpt;
2402 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2403 adapter->colc_old = adapter->stats.colc;
2404
2405 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2406 adapter->gorc_old = adapter->stats.gorc;
2407 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2408 adapter->gotc_old = adapter->stats.gotc;
2409
2410 igb_update_adaptive(&adapter->hw);
2411
2412 if (!netif_carrier_ok(netdev)) {
2413 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2414 /* We've lost link, so the controller stops DMA,
2415 * but we've got queued Tx work that's never going
2416 * to get done, so reset controller to flush Tx.
2417 * (Do the reset outside of interrupt context). */
2418 adapter->tx_timeout_count++;
2419 schedule_work(&adapter->reset_task);
2420 }
2421 }
2422
2423 /* Cause software interrupt to ensure rx ring is cleaned */
2424 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2425
2426 /* Force detection of hung controller every watchdog period */
2427 tx_ring->detect_tx_hung = true;
2428
2429 /* Reset the timer */
2430 if (!test_bit(__IGB_DOWN, &adapter->state))
2431 mod_timer(&adapter->watchdog_timer,
2432 round_jiffies(jiffies + 2 * HZ));
2433}
2434
2435enum latency_range {
2436 lowest_latency = 0,
2437 low_latency = 1,
2438 bulk_latency = 2,
2439 latency_invalid = 255
2440};
2441
2442
6eb5a7f1
AD		 2443/**
2444 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2445 *
2446 * Stores a new ITR value based on strictly on packet size. This
2447 * algorithm is less sophisticated than that used in igb_update_itr,
2448 * due to the difficulty of synchronizing statistics across multiple
2449 * receive rings. The divisors and thresholds used by this fuction
2450 * were determined based on theoretical maximum wire speed and testing
2451 * data, in order to minimize response time while increasing bulk
2452 * throughput.
2453 * This functionality is controlled by the InterruptThrottleRate module
2454 * parameter (see igb_param.c)
2455 * NOTE: This function is called only when operating in a multiqueue
2456 * receive environment.
2457 * @rx_ring: pointer to ring
2458 **/
2459static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2460{
6eb5a7f1
AD		 2461 int new_val = rx_ring->itr_val;
2462 int avg_wire_size = 0;
2463 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2464
6eb5a7f1
AD		 2465 if (!rx_ring->total_packets)
2466 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2467
6eb5a7f1
AD		 2468 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2469 * ints/sec - ITR timer value of 120 ticks.
2470 */
2471 if (adapter->link_speed != SPEED_1000) {
2472 new_val = 120;
2473 goto set_itr_val;
9d5c8243 2474 }
6eb5a7f1 2475 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2476
6eb5a7f1
AD		 2477 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2478 avg_wire_size += 24;
2479
2480 /* Don't starve jumbo frames */
2481 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2482
6eb5a7f1
AD		 2483 /* Give a little boost to mid-size frames */
2484 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2485 new_val = avg_wire_size / 3;
2486 else
2487 new_val = avg_wire_size / 2;
9d5c8243 2488
6eb5a7f1 2489set_itr_val:
9d5c8243
AK		 2490 if (new_val != rx_ring->itr_val) {
2491 rx_ring->itr_val = new_val;
6eb5a7f1 2492 rx_ring->set_itr = 1;
9d5c8243 2493 }
6eb5a7f1
AD		 2494clear_counts:
2495 rx_ring->total_bytes = 0;
2496 rx_ring->total_packets = 0;
9d5c8243
AK		 2497}
2498
2499/**
2500 * igb_update_itr - update the dynamic ITR value based on statistics
2501 * Stores a new ITR value based on packets and byte
2502 * counts during the last interrupt. The advantage of per interrupt
2503 * computation is faster updates and more accurate ITR for the current
2504 * traffic pattern. Constants in this function were computed
2505 * based on theoretical maximum wire speed and thresholds were set based
2506 * on testing data as well as attempting to minimize response time
2507 * while increasing bulk throughput.
2508 * this functionality is controlled by the InterruptThrottleRate module
2509 * parameter (see igb_param.c)
2510 * NOTE: These calculations are only valid when operating in a single-
2511 * queue environment.
2512 * @adapter: pointer to adapter
2513 * @itr_setting: current adapter->itr
2514 * @packets: the number of packets during this measurement interval
2515 * @bytes: the number of bytes during this measurement interval
2516 **/
2517static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2518 int packets, int bytes)
2519{
2520 unsigned int retval = itr_setting;
2521
2522 if (packets == 0)
2523 goto update_itr_done;
2524
2525 switch (itr_setting) {
2526 case lowest_latency:
2527 /* handle TSO and jumbo frames */
2528 if (bytes/packets > 8000)
2529 retval = bulk_latency;
2530 else if ((packets < 5) && (bytes > 512))
2531 retval = low_latency;
2532 break;
2533 case low_latency: /* 50 usec aka 20000 ints/s */
2534 if (bytes > 10000) {
2535 /* this if handles the TSO accounting */
2536 if (bytes/packets > 8000) {
2537 retval = bulk_latency;
2538 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2539 retval = bulk_latency;
2540 } else if ((packets > 35)) {
2541 retval = lowest_latency;
2542 }
2543 } else if (bytes/packets > 2000) {
2544 retval = bulk_latency;
2545 } else if (packets <= 2 && bytes < 512) {
2546 retval = lowest_latency;
2547 }
2548 break;
2549 case bulk_latency: /* 250 usec aka 4000 ints/s */
2550 if (bytes > 25000) {
2551 if (packets > 35)
2552 retval = low_latency;
2553 } else if (bytes < 6000) {
2554 retval = low_latency;
2555 }
2556 break;
2557 }
2558
2559update_itr_done:
2560 return retval;
2561}
2562
6eb5a7f1 2563static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2564{
2565 u16 current_itr;
2566 u32 new_itr = adapter->itr;
2567
2568 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2569 if (adapter->link_speed != SPEED_1000) {
2570 current_itr = 0;
2571 new_itr = 4000;
2572 goto set_itr_now;
2573 }
2574
2575 adapter->rx_itr = igb_update_itr(adapter,
2576 adapter->rx_itr,
2577 adapter->rx_ring->total_packets,
2578 adapter->rx_ring->total_bytes);
9d5c8243 2579
6eb5a7f1 2580 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2581 adapter->tx_itr = igb_update_itr(adapter,
2582 adapter->tx_itr,
2583 adapter->tx_ring->total_packets,
2584 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2585
2586 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2587 } else {
2588 current_itr = adapter->rx_itr;
2589 }
2590
6eb5a7f1
AD		 2591 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2592 if (adapter->itr_setting == 3 &&
2593 current_itr == lowest_latency)
2594 current_itr = low_latency;
2595
9d5c8243
AK		 2596 switch (current_itr) {
2597 /* counts and packets in update_itr are dependent on these numbers */
2598 case lowest_latency:
2599 new_itr = 70000;
2600 break;
2601 case low_latency:
2602 new_itr = 20000; /* aka hwitr = ~200 */
2603 break;
2604 case bulk_latency:
2605 new_itr = 4000;
2606 break;
2607 default:
2608 break;
2609 }
2610
2611set_itr_now:
6eb5a7f1
AD		 2612 adapter->rx_ring->total_bytes = 0;
2613 adapter->rx_ring->total_packets = 0;
2614 if (adapter->rx_ring->buddy) {
2615 adapter->rx_ring->buddy->total_bytes = 0;
2616 adapter->rx_ring->buddy->total_packets = 0;
2617 }
2618
9d5c8243
AK		 2619 if (new_itr != adapter->itr) {
2620 /* this attempts to bias the interrupt rate towards Bulk
2621 * by adding intermediate steps when interrupt rate is
2622 * increasing */
2623 new_itr = new_itr > adapter->itr ?
2624 min(adapter->itr + (new_itr >> 2), new_itr) :
2625 new_itr;
2626 /* Don't write the value here; it resets the adapter's
2627 * internal timer, and causes us to delay far longer than
2628 * we should between interrupts. Instead, we write the ITR
2629 * value at the beginning of the next interrupt so the timing
2630 * ends up being correct.
2631 */
2632 adapter->itr = new_itr;
6eb5a7f1
AD		 2633 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2634 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2635 }
2636
2637 return;
2638}
2639
2640
2641#define IGB_TX_FLAGS_CSUM 0x00000001
2642#define IGB_TX_FLAGS_VLAN 0x00000002
2643#define IGB_TX_FLAGS_TSO 0x00000004
2644#define IGB_TX_FLAGS_IPV4 0x00000008
2645#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2646#define IGB_TX_FLAGS_VLAN_SHIFT 16
2647
2648static inline int igb_tso_adv(struct igb_adapter *adapter,
2649 struct igb_ring *tx_ring,
2650 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2651{
2652 struct e1000_adv_tx_context_desc *context_desc;
2653 unsigned int i;
2654 int err;
2655 struct igb_buffer *buffer_info;
2656 u32 info = 0, tu_cmd = 0;
2657 u32 mss_l4len_idx, l4len;
2658 *hdr_len = 0;
2659
2660 if (skb_header_cloned(skb)) {
2661 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2662 if (err)
2663 return err;
2664 }
2665
2666 l4len = tcp_hdrlen(skb);
2667 *hdr_len += l4len;
2668
2669 if (skb->protocol == htons(ETH_P_IP)) {
2670 struct iphdr *iph = ip_hdr(skb);
2671 iph->tot_len = 0;
2672 iph->check = 0;
2673 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2674 iph->daddr, 0,
2675 IPPROTO_TCP,
2676 0);
2677 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2678 ipv6_hdr(skb)->payload_len = 0;
2679 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2680 &ipv6_hdr(skb)->daddr,
2681 0, IPPROTO_TCP, 0);
2682 }
2683
2684 i = tx_ring->next_to_use;
2685
2686 buffer_info = &tx_ring->buffer_info[i];
2687 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2688 /* VLAN MACLEN IPLEN */
2689 if (tx_flags & IGB_TX_FLAGS_VLAN)
2690 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2691 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2692 *hdr_len += skb_network_offset(skb);
2693 info |= skb_network_header_len(skb);
2694 *hdr_len += skb_network_header_len(skb);
2695 context_desc->vlan_macip_lens = cpu_to_le32(info);
2696
2697 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2698 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2699
2700 if (skb->protocol == htons(ETH_P_IP))
2701 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2702 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2703
2704 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2705
2706 /* MSS L4LEN IDX */
2707 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2708 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2709
7dfc16fa
AD		 2710 /* Context index must be unique per ring. */
2711 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2712 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2713
2714 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2715 context_desc->seqnum_seed = 0;
2716
2717 buffer_info->time_stamp = jiffies;
2718 buffer_info->dma = 0;
2719 i++;
2720 if (i == tx_ring->count)
2721 i = 0;
2722
2723 tx_ring->next_to_use = i;
2724
2725 return true;
2726}
2727
2728static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2729 struct igb_ring *tx_ring,
2730 struct sk_buff *skb, u32 tx_flags)
2731{
2732 struct e1000_adv_tx_context_desc *context_desc;
2733 unsigned int i;
2734 struct igb_buffer *buffer_info;
2735 u32 info = 0, tu_cmd = 0;
2736
2737 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2738 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2739 i = tx_ring->next_to_use;
2740 buffer_info = &tx_ring->buffer_info[i];
2741 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2742
2743 if (tx_flags & IGB_TX_FLAGS_VLAN)
2744 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2745 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2746 if (skb->ip_summed == CHECKSUM_PARTIAL)
2747 info |= skb_network_header_len(skb);
2748
2749 context_desc->vlan_macip_lens = cpu_to_le32(info);
2750
2751 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2752
2753 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2754 switch (skb->protocol) {
2755 case __constant_htons(ETH_P_IP):
9d5c8243 2756 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2757 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2758 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2759 break;
2760 case __constant_htons(ETH_P_IPV6):
2761 /* XXX what about other V6 headers?? */
2762 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2763 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2764 break;
2765 default:
2766 if (unlikely(net_ratelimit()))
2767 dev_warn(&adapter->pdev->dev,
2768 "partial checksum but proto=%x!\n",
2769 skb->protocol);
2770 break;
2771 }
9d5c8243
AK		 2772 }
2773
2774 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2775 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2776 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2777 context_desc->mss_l4len_idx =
2778 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2779
2780 buffer_info->time_stamp = jiffies;
2781 buffer_info->dma = 0;
2782
2783 i++;
2784 if (i == tx_ring->count)
2785 i = 0;
2786 tx_ring->next_to_use = i;
2787
2788 return true;
2789 }
2790
2791
2792 return false;
2793}
2794
2795#define IGB_MAX_TXD_PWR 16
2796#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2797
2798static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2799 struct igb_ring *tx_ring,
2800 struct sk_buff *skb)
2801{
2802 struct igb_buffer *buffer_info;
2803 unsigned int len = skb_headlen(skb);
2804 unsigned int count = 0, i;
2805 unsigned int f;
2806
2807 i = tx_ring->next_to_use;
2808
2809 buffer_info = &tx_ring->buffer_info[i];
2810 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2811 buffer_info->length = len;
2812 /* set time_stamp *before* dma to help avoid a possible race */
2813 buffer_info->time_stamp = jiffies;
2814 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2815 PCI_DMA_TODEVICE);
2816 count++;
2817 i++;
2818 if (i == tx_ring->count)
2819 i = 0;
2820
2821 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2822 struct skb_frag_struct *frag;
2823
2824 frag = &skb_shinfo(skb)->frags[f];
2825 len = frag->size;
2826
2827 buffer_info = &tx_ring->buffer_info[i];
2828 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2829 buffer_info->length = len;
2830 buffer_info->time_stamp = jiffies;
2831 buffer_info->dma = pci_map_page(adapter->pdev,
2832 frag->page,
2833 frag->page_offset,
2834 len,
2835 PCI_DMA_TODEVICE);
2836
2837 count++;
2838 i++;
2839 if (i == tx_ring->count)
2840 i = 0;
2841 }
2842
2843 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2844 tx_ring->buffer_info[i].skb = skb;
2845
2846 return count;
2847}
2848
2849static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2850 struct igb_ring *tx_ring,
2851 int tx_flags, int count, u32 paylen,
2852 u8 hdr_len)
2853{
2854 union e1000_adv_tx_desc *tx_desc = NULL;
2855 struct igb_buffer *buffer_info;
2856 u32 olinfo_status = 0, cmd_type_len;
2857 unsigned int i;
2858
2859 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2860 E1000_ADVTXD_DCMD_DEXT);
2861
2862 if (tx_flags & IGB_TX_FLAGS_VLAN)
2863 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2864
2865 if (tx_flags & IGB_TX_FLAGS_TSO) {
2866 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2867
2868 /* insert tcp checksum */
2869 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2870
2871 /* insert ip checksum */
2872 if (tx_flags & IGB_TX_FLAGS_IPV4)
2873 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2874
2875 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2876 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2877 }
2878
7dfc16fa
AD		 2879 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2880 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2881 IGB_TX_FLAGS_VLAN)))
661086df 2882 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2883
2884 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2885
2886 i = tx_ring->next_to_use;
2887 while (count--) {
2888 buffer_info = &tx_ring->buffer_info[i];
2889 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2890 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2891 tx_desc->read.cmd_type_len =
2892 cpu_to_le32(cmd_type_len | buffer_info->length);
2893 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2894 i++;
2895 if (i == tx_ring->count)
2896 i = 0;
2897 }
2898
2899 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2900 /* Force memory writes to complete before letting h/w
2901 * know there are new descriptors to fetch. (Only
2902 * applicable for weak-ordered memory model archs,
2903 * such as IA-64). */
2904 wmb();
2905
2906 tx_ring->next_to_use = i;
2907 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2908 /* we need this if more than one processor can write to our tail
2909 * at a time, it syncronizes IO on IA64/Altix systems */
2910 mmiowb();
2911}
2912
2913static int __igb_maybe_stop_tx(struct net_device *netdev,
2914 struct igb_ring *tx_ring, int size)
2915{
2916 struct igb_adapter *adapter = netdev_priv(netdev);
2917
661086df 2918 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2919
9d5c8243
AK		 2920 /* Herbert's original patch had:
2921 * smp_mb__after_netif_stop_queue();
2922 * but since that doesn't exist yet, just open code it. */
2923 smp_mb();
2924
2925 /* We need to check again in a case another CPU has just
2926 * made room available. */
2927 if (IGB_DESC_UNUSED(tx_ring) < size)
2928 return -EBUSY;
2929
2930 /* A reprieve! */
661086df 2931 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2932 ++adapter->restart_queue;
2933 return 0;
2934}
2935
2936static int igb_maybe_stop_tx(struct net_device *netdev,
2937 struct igb_ring *tx_ring, int size)
2938{
2939 if (IGB_DESC_UNUSED(tx_ring) >= size)
2940 return 0;
2941 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2942}
2943
2944#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2945
2946static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2947 struct net_device *netdev,
2948 struct igb_ring *tx_ring)
2949{
2950 struct igb_adapter *adapter = netdev_priv(netdev);
2951 unsigned int tx_flags = 0;
2952 unsigned int len;
9d5c8243
AK		 2953 u8 hdr_len = 0;
2954 int tso = 0;
2955
2956 len = skb_headlen(skb);
2957
2958 if (test_bit(__IGB_DOWN, &adapter->state)) {
2959 dev_kfree_skb_any(skb);
2960 return NETDEV_TX_OK;
2961 }
2962
2963 if (skb->len <= 0) {
2964 dev_kfree_skb_any(skb);
2965 return NETDEV_TX_OK;
2966 }
2967
9d5c8243
AK		 2968 /* need: 1 descriptor per page,
2969 * + 2 desc gap to keep tail from touching head,
2970 * + 1 desc for skb->data,
2971 * + 1 desc for context descriptor,
2972 * otherwise try next time */
2973 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2974 /* this is a hard error */
9d5c8243
AK		 2975 return NETDEV_TX_BUSY;
2976 }
6eb5a7f1 2977 skb_orphan(skb);
9d5c8243
AK		 2978
2979 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2980 tx_flags |= IGB_TX_FLAGS_VLAN;
2981 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2982 }
2983
661086df
PWJ		 2984 if (skb->protocol == htons(ETH_P_IP))
2985 tx_flags |= IGB_TX_FLAGS_IPV4;
2986
9d5c8243
AK		 2987 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2988 &hdr_len) : 0;
2989
2990 if (tso < 0) {
2991 dev_kfree_skb_any(skb);
9d5c8243
AK		 2992 return NETDEV_TX_OK;
2993 }
2994
2995 if (tso)
2996 tx_flags |= IGB_TX_FLAGS_TSO;
2997 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2998 if (skb->ip_summed == CHECKSUM_PARTIAL)
2999 tx_flags |= IGB_TX_FLAGS_CSUM;
3000
9d5c8243
AK		 3001 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3002 igb_tx_map_adv(adapter, tx_ring, skb),
3003 skb->len, hdr_len);
3004
3005 netdev->trans_start = jiffies;
3006
3007 /* Make sure there is space in the ring for the next send. */
3008 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3009
9d5c8243
AK		 3010 return NETDEV_TX_OK;
3011}
3012
3013static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3014{
3015 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3016 struct igb_ring *tx_ring;
3017
661086df
PWJ		 3018 int r_idx = 0;
3019 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3020 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3021
3022 /* This goes back to the question of how to logically map a tx queue
3023 * to a flow. Right now, performance is impacted slightly negatively
3024 * if using multiple tx queues. If the stack breaks away from a
3025 * single qdisc implementation, we can look at this again. */
3026 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3027}
3028
3029/**
3030 * igb_tx_timeout - Respond to a Tx Hang
3031 * @netdev: network interface device structure
3032 **/
3033static void igb_tx_timeout(struct net_device *netdev)
3034{
3035 struct igb_adapter *adapter = netdev_priv(netdev);
3036 struct e1000_hw *hw = &adapter->hw;
3037
3038 /* Do the reset outside of interrupt context */
3039 adapter->tx_timeout_count++;
3040 schedule_work(&adapter->reset_task);
3041 wr32(E1000_EICS, adapter->eims_enable_mask &
3042 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3043}
3044
3045static void igb_reset_task(struct work_struct *work)
3046{
3047 struct igb_adapter *adapter;
3048 adapter = container_of(work, struct igb_adapter, reset_task);
3049
3050 igb_reinit_locked(adapter);
3051}
3052
3053/**
3054 * igb_get_stats - Get System Network Statistics
3055 * @netdev: network interface device structure
3056 *
3057 * Returns the address of the device statistics structure.
3058 * The statistics are actually updated from the timer callback.
3059 **/
3060static struct net_device_stats *
3061igb_get_stats(struct net_device *netdev)
3062{
3063 struct igb_adapter *adapter = netdev_priv(netdev);
3064
3065 /* only return the current stats */
3066 return &adapter->net_stats;
3067}
3068
3069/**
3070 * igb_change_mtu - Change the Maximum Transfer Unit
3071 * @netdev: network interface device structure
3072 * @new_mtu: new value for maximum frame size
3073 *
3074 * Returns 0 on success, negative on failure
3075 **/
3076static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3077{
3078 struct igb_adapter *adapter = netdev_priv(netdev);
3079 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3080
3081 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3082 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3083 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3084 return -EINVAL;
3085 }
3086
3087#define MAX_STD_JUMBO_FRAME_SIZE 9234
3088 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3089 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3090 return -EINVAL;
3091 }
3092
3093 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3094 msleep(1);
3095 /* igb_down has a dependency on max_frame_size */
3096 adapter->max_frame_size = max_frame;
3097 if (netif_running(netdev))
3098 igb_down(adapter);
3099
3100 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3101 * means we reserve 2 more, this pushes us to allocate from the next
3102 * larger slab size.
3103 * i.e. RXBUFFER_2048 --> size-4096 slab
3104 */
3105
3106 if (max_frame <= IGB_RXBUFFER_256)
3107 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3108 else if (max_frame <= IGB_RXBUFFER_512)
3109 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3110 else if (max_frame <= IGB_RXBUFFER_1024)
3111 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3112 else if (max_frame <= IGB_RXBUFFER_2048)
3113 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3114 else
bf36c1a0
AD		 3115#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3116 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3117#else
3118 adapter->rx_buffer_len = PAGE_SIZE / 2;
3119#endif
9d5c8243
AK		 3120 /* adjust allocation if LPE protects us, and we aren't using SBP */
3121 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3122 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3123 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3124
3125 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3126 netdev->mtu, new_mtu);
3127 netdev->mtu = new_mtu;
3128
3129 if (netif_running(netdev))
3130 igb_up(adapter);
3131 else
3132 igb_reset(adapter);
3133
3134 clear_bit(__IGB_RESETTING, &adapter->state);
3135
3136 return 0;
3137}
3138
3139/**
3140 * igb_update_stats - Update the board statistics counters
3141 * @adapter: board private structure
3142 **/
3143
3144void igb_update_stats(struct igb_adapter *adapter)
3145{
3146 struct e1000_hw *hw = &adapter->hw;
3147 struct pci_dev *pdev = adapter->pdev;
3148 u16 phy_tmp;
3149
3150#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3151
3152 /*
3153 * Prevent stats update while adapter is being reset, or if the pci
3154 * connection is down.
3155 */
3156 if (adapter->link_speed == 0)
3157 return;
3158 if (pci_channel_offline(pdev))
3159 return;
3160
3161 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3162 adapter->stats.gprc += rd32(E1000_GPRC);
3163 adapter->stats.gorc += rd32(E1000_GORCL);
3164 rd32(E1000_GORCH); /* clear GORCL */
3165 adapter->stats.bprc += rd32(E1000_BPRC);
3166 adapter->stats.mprc += rd32(E1000_MPRC);
3167 adapter->stats.roc += rd32(E1000_ROC);
3168
3169 adapter->stats.prc64 += rd32(E1000_PRC64);
3170 adapter->stats.prc127 += rd32(E1000_PRC127);
3171 adapter->stats.prc255 += rd32(E1000_PRC255);
3172 adapter->stats.prc511 += rd32(E1000_PRC511);
3173 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3174 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3175 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3176 adapter->stats.sec += rd32(E1000_SEC);
3177
3178 adapter->stats.mpc += rd32(E1000_MPC);
3179 adapter->stats.scc += rd32(E1000_SCC);
3180 adapter->stats.ecol += rd32(E1000_ECOL);
3181 adapter->stats.mcc += rd32(E1000_MCC);
3182 adapter->stats.latecol += rd32(E1000_LATECOL);
3183 adapter->stats.dc += rd32(E1000_DC);
3184 adapter->stats.rlec += rd32(E1000_RLEC);
3185 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3186 adapter->stats.xontxc += rd32(E1000_XONTXC);
3187 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3188 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3189 adapter->stats.fcruc += rd32(E1000_FCRUC);
3190 adapter->stats.gptc += rd32(E1000_GPTC);
3191 adapter->stats.gotc += rd32(E1000_GOTCL);
3192 rd32(E1000_GOTCH); /* clear GOTCL */
3193 adapter->stats.rnbc += rd32(E1000_RNBC);
3194 adapter->stats.ruc += rd32(E1000_RUC);
3195 adapter->stats.rfc += rd32(E1000_RFC);
3196 adapter->stats.rjc += rd32(E1000_RJC);
3197 adapter->stats.tor += rd32(E1000_TORH);
3198 adapter->stats.tot += rd32(E1000_TOTH);
3199 adapter->stats.tpr += rd32(E1000_TPR);
3200
3201 adapter->stats.ptc64 += rd32(E1000_PTC64);
3202 adapter->stats.ptc127 += rd32(E1000_PTC127);
3203 adapter->stats.ptc255 += rd32(E1000_PTC255);
3204 adapter->stats.ptc511 += rd32(E1000_PTC511);
3205 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3206 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3207
3208 adapter->stats.mptc += rd32(E1000_MPTC);
3209 adapter->stats.bptc += rd32(E1000_BPTC);
3210
3211 /* used for adaptive IFS */
3212
3213 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3214 adapter->stats.tpt += hw->mac.tx_packet_delta;
3215 hw->mac.collision_delta = rd32(E1000_COLC);
3216 adapter->stats.colc += hw->mac.collision_delta;
3217
3218 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3219 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3220 adapter->stats.tncrs += rd32(E1000_TNCRS);
3221 adapter->stats.tsctc += rd32(E1000_TSCTC);
3222 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3223
3224 adapter->stats.iac += rd32(E1000_IAC);
3225 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3226 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3227 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3228 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3229 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3230 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3231 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3232 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3233
3234 /* Fill out the OS statistics structure */
3235 adapter->net_stats.multicast = adapter->stats.mprc;
3236 adapter->net_stats.collisions = adapter->stats.colc;
3237
3238 /* Rx Errors */
3239
3240 /* RLEC on some newer hardware can be incorrect so build
3241 * our own version based on RUC and ROC */
3242 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3243 adapter->stats.crcerrs + adapter->stats.algnerrc +
3244 adapter->stats.ruc + adapter->stats.roc +
3245 adapter->stats.cexterr;
3246 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3247 adapter->stats.roc;
3248 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3249 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3250 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3251
3252 /* Tx Errors */
3253 adapter->net_stats.tx_errors = adapter->stats.ecol +
3254 adapter->stats.latecol;
3255 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3256 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3257 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3258
3259 /* Tx Dropped needs to be maintained elsewhere */
3260
3261 /* Phy Stats */
3262 if (hw->phy.media_type == e1000_media_type_copper) {
3263 if ((adapter->link_speed == SPEED_1000) &&
3264 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3265 &phy_tmp))) {
3266 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3267 adapter->phy_stats.idle_errors += phy_tmp;
3268 }
3269 }
3270
3271 /* Management Stats */
3272 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3273 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3274 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3275}
3276
3277
3278static irqreturn_t igb_msix_other(int irq, void *data)
3279{
3280 struct net_device *netdev = data;
3281 struct igb_adapter *adapter = netdev_priv(netdev);
3282 struct e1000_hw *hw = &adapter->hw;
844290e5 3283 u32 icr = rd32(E1000_ICR);
9d5c8243 3284
844290e5
PW		 3285 /* reading ICR causes bit 31 of EICR to be cleared */
3286 if (!(icr & E1000_ICR_LSC))
3287 goto no_link_interrupt;
3288 hw->mac.get_link_status = 1;
3289 /* guard against interrupt when we're going down */
3290 if (!test_bit(__IGB_DOWN, &adapter->state))
3291 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3292
9d5c8243
AK		 3293no_link_interrupt:
3294 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3295 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3296
3297 return IRQ_HANDLED;
3298}
3299
3300static irqreturn_t igb_msix_tx(int irq, void *data)
3301{
3302 struct igb_ring *tx_ring = data;
3303 struct igb_adapter *adapter = tx_ring->adapter;
3304 struct e1000_hw *hw = &adapter->hw;
3305
fe4506b6 3306#ifdef CONFIG_DCA
7dfc16fa 3307 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3308 igb_update_tx_dca(tx_ring);
3309#endif
9d5c8243
AK		 3310 tx_ring->total_bytes = 0;
3311 tx_ring->total_packets = 0;
661086df
PWJ		 3312
3313 /* auto mask will automatically reenable the interrupt when we write
3314 * EICS */
3b644cf6 3315 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3316 /* Ring was not completely cleaned, so fire another interrupt */
3317 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3318 else
9d5c8243 3319 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3320
9d5c8243
AK		 3321 return IRQ_HANDLED;
3322}
3323
6eb5a7f1
AD		 3324static void igb_write_itr(struct igb_ring *ring)
3325{
3326 struct e1000_hw *hw = &ring->adapter->hw;
3327 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3328 switch (hw->mac.type) {
3329 case e1000_82576:
3330 wr32(ring->itr_register,
3331 ring->itr_val |
3332 0x80000000);
3333 break;
3334 default:
3335 wr32(ring->itr_register,
3336 ring->itr_val |
3337 (ring->itr_val << 16));
3338 break;
3339 }
3340 ring->set_itr = 0;
3341 }
3342}
3343
9d5c8243
AK		 3344static irqreturn_t igb_msix_rx(int irq, void *data)
3345{
3346 struct igb_ring *rx_ring = data;
3347 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3348
844290e5
PW		 3349 /* Write the ITR value calculated at the end of the
3350 * previous interrupt.
3351 */
9d5c8243 3352
6eb5a7f1 3353 igb_write_itr(rx_ring);
9d5c8243 3354
844290e5
PW		 3355 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3356 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3357
fe4506b6 3358#ifdef CONFIG_DCA
7dfc16fa 3359 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3360 igb_update_rx_dca(rx_ring);
3361#endif
3362 return IRQ_HANDLED;
3363}
3364
3365#ifdef CONFIG_DCA
3366static void igb_update_rx_dca(struct igb_ring *rx_ring)
3367{
3368 u32 dca_rxctrl;
3369 struct igb_adapter *adapter = rx_ring->adapter;
3370 struct e1000_hw *hw = &adapter->hw;
3371 int cpu = get_cpu();
3372 int q = rx_ring - adapter->rx_ring;
3373
3374 if (rx_ring->cpu != cpu) {
3375 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3376 if (hw->mac.type == e1000_82576) {
3377 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3378 dca_rxctrl |= dca_get_tag(cpu) <<
3379 E1000_DCA_RXCTRL_CPUID_SHIFT;
3380 } else {
3381 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3382 dca_rxctrl |= dca_get_tag(cpu);
3383 }
fe4506b6
JC		 3384 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3385 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3386 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3387 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3388 rx_ring->cpu = cpu;
3389 }
3390 put_cpu();
3391}
3392
3393static void igb_update_tx_dca(struct igb_ring *tx_ring)
3394{
3395 u32 dca_txctrl;
3396 struct igb_adapter *adapter = tx_ring->adapter;
3397 struct e1000_hw *hw = &adapter->hw;
3398 int cpu = get_cpu();
3399 int q = tx_ring - adapter->tx_ring;
3400
3401 if (tx_ring->cpu != cpu) {
3402 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3403 if (hw->mac.type == e1000_82576) {
3404 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3405 dca_txctrl |= dca_get_tag(cpu) <<
3406 E1000_DCA_TXCTRL_CPUID_SHIFT;
3407 } else {
3408 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3409 dca_txctrl |= dca_get_tag(cpu);
3410 }
fe4506b6
JC		 3411 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3412 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3413 tx_ring->cpu = cpu;
3414 }
3415 put_cpu();
3416}
3417
3418static void igb_setup_dca(struct igb_adapter *adapter)
3419{
3420 int i;
3421
7dfc16fa 3422 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3423 return;
3424
3425 for (i = 0; i < adapter->num_tx_queues; i++) {
3426 adapter->tx_ring[i].cpu = -1;
3427 igb_update_tx_dca(&adapter->tx_ring[i]);
3428 }
3429 for (i = 0; i < adapter->num_rx_queues; i++) {
3430 adapter->rx_ring[i].cpu = -1;
3431 igb_update_rx_dca(&adapter->rx_ring[i]);
3432 }
3433}
3434
3435static int __igb_notify_dca(struct device *dev, void *data)
3436{
3437 struct net_device *netdev = dev_get_drvdata(dev);
3438 struct igb_adapter *adapter = netdev_priv(netdev);
3439 struct e1000_hw *hw = &adapter->hw;
3440 unsigned long event = *(unsigned long *)data;
3441
7dfc16fa
AD		 3442 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3443 goto out;
3444
fe4506b6
JC		 3445 switch (event) {
3446 case DCA_PROVIDER_ADD:
3447 /* if already enabled, don't do it again */
7dfc16fa 3448 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3449 break;
7dfc16fa 3450 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3451 /* Always use CB2 mode, difference is masked
3452 * in the CB driver. */
3453 wr32(E1000_DCA_CTRL, 2);
3454 if (dca_add_requester(dev) == 0) {
3455 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3456 igb_setup_dca(adapter);
3457 break;
3458 }
3459 /* Fall Through since DCA is disabled. */
3460 case DCA_PROVIDER_REMOVE:
7dfc16fa 3461 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3462 /* without this a class_device is left
3463 * hanging around in the sysfs model */
3464 dca_remove_requester(dev);
3465 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3466 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3467 wr32(E1000_DCA_CTRL, 1);
3468 }
3469 break;
3470 }
7dfc16fa 3471out:
fe4506b6 3472 return 0;
9d5c8243
AK		 3473}
3474
fe4506b6
JC		 3475static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3476 void *p)
3477{
3478 int ret_val;
3479
3480 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3481 __igb_notify_dca);
3482
3483 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3484}
3485#endif /* CONFIG_DCA */
9d5c8243
AK		 3486
3487/**
3488 * igb_intr_msi - Interrupt Handler
3489 * @irq: interrupt number
3490 * @data: pointer to a network interface device structure
3491 **/
3492static irqreturn_t igb_intr_msi(int irq, void *data)
3493{
3494 struct net_device *netdev = data;
3495 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3496 struct e1000_hw *hw = &adapter->hw;
3497 /* read ICR disables interrupts using IAM */
3498 u32 icr = rd32(E1000_ICR);
3499
6eb5a7f1 3500 igb_write_itr(adapter->rx_ring);
9d5c8243 3501
9d5c8243
AK		 3502 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3503 hw->mac.get_link_status = 1;
3504 if (!test_bit(__IGB_DOWN, &adapter->state))
3505 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3506 }
3507
844290e5 3508 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3509
3510 return IRQ_HANDLED;
3511}
3512
3513/**
3514 * igb_intr - Interrupt Handler
3515 * @irq: interrupt number
3516 * @data: pointer to a network interface device structure
3517 **/
3518static irqreturn_t igb_intr(int irq, void *data)
3519{
3520 struct net_device *netdev = data;
3521 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3522 struct e1000_hw *hw = &adapter->hw;
3523 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3524 * need for the IMC write */
3525 u32 icr = rd32(E1000_ICR);
3526 u32 eicr = 0;
3527 if (!icr)
3528 return IRQ_NONE; /* Not our interrupt */
3529
6eb5a7f1 3530 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3531
3532 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3533 * not set, then the adapter didn't send an interrupt */
3534 if (!(icr & E1000_ICR_INT_ASSERTED))
3535 return IRQ_NONE;
3536
3537 eicr = rd32(E1000_EICR);
3538
3539 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3540 hw->mac.get_link_status = 1;
3541 /* guard against interrupt when we're going down */
3542 if (!test_bit(__IGB_DOWN, &adapter->state))
3543 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3544 }
3545
844290e5 3546 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3547
3548 return IRQ_HANDLED;
3549}
3550
3551/**
661086df
PWJ		 3552 * igb_poll - NAPI Rx polling callback
3553 * @napi: napi polling structure
3554 * @budget: count of how many packets we should handle
9d5c8243 3555 **/
661086df 3556static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3557{
661086df
PWJ		 3558 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3559 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3560 struct net_device *netdev = adapter->netdev;
661086df 3561 int tx_clean_complete, work_done = 0;
9d5c8243 3562
661086df 3563 /* this poll routine only supports one tx and one rx queue */
fe4506b6 3564#ifdef CONFIG_DCA
7dfc16fa 3565 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3566 igb_update_tx_dca(&adapter->tx_ring[0]);
3567#endif
661086df 3568 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6
JC		 3569
3570#ifdef CONFIG_DCA
7dfc16fa 3571 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3572 igb_update_rx_dca(&adapter->rx_ring[0]);
3573#endif
661086df 3574 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3575
3576 /* If no Tx and not enough Rx work done, exit the polling mode */
3577 if ((tx_clean_complete && (work_done < budget)) ||
3578 !netif_running(netdev)) {
9d5c8243 3579 if (adapter->itr_setting & 3)
6eb5a7f1 3580 igb_set_itr(adapter);
9d5c8243
AK		 3581 netif_rx_complete(netdev, napi);
3582 if (!test_bit(__IGB_DOWN, &adapter->state))
3583 igb_irq_enable(adapter);
3584 return 0;
3585 }
3586
3587 return 1;
3588}
3589
3590static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3591{
3592 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3593 struct igb_adapter *adapter = rx_ring->adapter;
3594 struct e1000_hw *hw = &adapter->hw;
3595 struct net_device *netdev = adapter->netdev;
3596 int work_done = 0;
3597
3598 /* Keep link state information with original netdev */
3599 if (!netif_carrier_ok(netdev))
3600 goto quit_polling;
3601
fe4506b6 3602#ifdef CONFIG_DCA
7dfc16fa 3603 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3604 igb_update_rx_dca(rx_ring);
3605#endif
3b644cf6 3606 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3607
3608
3609 /* If not enough Rx work done, exit the polling mode */
3610 if ((work_done == 0) || !netif_running(netdev)) {
3611quit_polling:
3612 netif_rx_complete(netdev, napi);
3613
6eb5a7f1
AD		 3614 if (adapter->itr_setting & 3) {
3615 if (adapter->num_rx_queues == 1)
3616 igb_set_itr(adapter);
3617 else
3618 igb_update_ring_itr(rx_ring);
9d5c8243 3619 }
844290e5
PW		 3620
3621 if (!test_bit(__IGB_DOWN, &adapter->state))
3622 wr32(E1000_EIMS, rx_ring->eims_value);
3623
9d5c8243
AK		 3624 return 0;
3625 }
3626
3627 return 1;
3628}
6d8126f9
AV		 3629
3630static inline u32 get_head(struct igb_ring *tx_ring)
3631{
3632 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3633 return le32_to_cpu(*(volatile __le32 *)end);
3634}
3635
9d5c8243
AK		 3636/**
3637 * igb_clean_tx_irq - Reclaim resources after transmit completes
3638 * @adapter: board private structure
3639 * returns true if ring is completely cleaned
3640 **/
3b644cf6 3641static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3642{
3b644cf6 3643 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3644 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3645 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3646 struct e1000_tx_desc *tx_desc;
3647 struct igb_buffer *buffer_info;
3648 struct sk_buff *skb;
3649 unsigned int i;
3650 u32 head, oldhead;
3651 unsigned int count = 0;
3652 bool cleaned = false;
3653 bool retval = true;
3654 unsigned int total_bytes = 0, total_packets = 0;
3655
3656 rmb();
6d8126f9 3657 head = get_head(tx_ring);
9d5c8243
AK		 3658 i = tx_ring->next_to_clean;
3659 while (1) {
3660 while (i != head) {
3661 cleaned = true;
3662 tx_desc = E1000_TX_DESC(*tx_ring, i);
3663 buffer_info = &tx_ring->buffer_info[i];
3664 skb = buffer_info->skb;
3665
3666 if (skb) {
3667 unsigned int segs, bytecount;
3668 /* gso_segs is currently only valid for tcp */
3669 segs = skb_shinfo(skb)->gso_segs ?: 1;
3670 /* multiply data chunks by size of headers */
3671 bytecount = ((segs - 1) * skb_headlen(skb)) +
3672 skb->len;
3673 total_packets += segs;
3674 total_bytes += bytecount;
3675 }
3676
3677 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3678 tx_desc->upper.data = 0;
3679
3680 i++;
3681 if (i == tx_ring->count)
3682 i = 0;
3683
3684 count++;
3685 if (count == IGB_MAX_TX_CLEAN) {
3686 retval = false;
3687 goto done_cleaning;
3688 }
3689 }
3690 oldhead = head;
3691 rmb();
6d8126f9 3692 head = get_head(tx_ring);
9d5c8243
AK		 3693 if (head == oldhead)
3694 goto done_cleaning;
3695 } /* while (1) */
3696
3697done_cleaning:
3698 tx_ring->next_to_clean = i;
3699
3700 if (unlikely(cleaned &&
3701 netif_carrier_ok(netdev) &&
3702 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3703 /* Make sure that anybody stopping the queue after this
3704 * sees the new next_to_clean.
3705 */
3706 smp_mb();
661086df
PWJ		 3707 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3708 !(test_bit(__IGB_DOWN, &adapter->state))) {
3709 netif_wake_subqueue(netdev, tx_ring->queue_index);
3710 ++adapter->restart_queue;
3711 }
9d5c8243
AK		 3712 }
3713
3714 if (tx_ring->detect_tx_hung) {
3715 /* Detect a transmit hang in hardware, this serializes the
3716 * check with the clearing of time_stamp and movement of i */
3717 tx_ring->detect_tx_hung = false;
3718 if (tx_ring->buffer_info[i].time_stamp &&
3719 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3720 (adapter->tx_timeout_factor * HZ))
3721 && !(rd32(E1000_STATUS) &
3722 E1000_STATUS_TXOFF)) {
3723
3724 tx_desc = E1000_TX_DESC(*tx_ring, i);
3725 /* detected Tx unit hang */
3726 dev_err(&adapter->pdev->dev,
3727 "Detected Tx Unit Hang\n"
2d064c06 3728 " Tx Queue <%d>\n"
9d5c8243
AK		 3729 " TDH <%x>\n"
3730 " TDT <%x>\n"
3731 " next_to_use <%x>\n"
3732 " next_to_clean <%x>\n"
3733 " head (WB) <%x>\n"
3734 "buffer_info[next_to_clean]\n"
3735 " time_stamp <%lx>\n"
3736 " jiffies <%lx>\n"
3737 " desc.status <%x>\n",
2d064c06 3738 tx_ring->queue_index,
9d5c8243
AK		 3739 readl(adapter->hw.hw_addr + tx_ring->head),
3740 readl(adapter->hw.hw_addr + tx_ring->tail),
3741 tx_ring->next_to_use,
3742 tx_ring->next_to_clean,
3743 head,
3744 tx_ring->buffer_info[i].time_stamp,
3745 jiffies,
3746 tx_desc->upper.fields.status);
661086df 3747 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3748 }
3749 }
3750 tx_ring->total_bytes += total_bytes;
3751 tx_ring->total_packets += total_packets;
e21ed353
AD		 3752 tx_ring->tx_stats.bytes += total_bytes;
3753 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3754 adapter->net_stats.tx_bytes += total_bytes;
3755 adapter->net_stats.tx_packets += total_packets;
3756 return retval;
3757}
3758
d3352520
AD		 3759#ifdef CONFIG_IGB_LRO
3760 /**
3761 * igb_get_skb_hdr - helper function for LRO header processing
3762 * @skb: pointer to sk_buff to be added to LRO packet
3763 * @iphdr: pointer to ip header structure
3764 * @tcph: pointer to tcp header structure
3765 * @hdr_flags: pointer to header flags
3766 * @priv: pointer to the receive descriptor for the current sk_buff
3767 **/
3768static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3769 u64 *hdr_flags, void *priv)
3770{
3771 union e1000_adv_rx_desc *rx_desc = priv;
3772 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3773 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3774
3775 /* Verify that this is a valid IPv4 TCP packet */
3776 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3777 E1000_RXDADV_PKTTYPE_TCP))
3778 return -1;
3779
3780 /* Set network headers */
3781 skb_reset_network_header(skb);
3782 skb_set_transport_header(skb, ip_hdrlen(skb));
3783 *iphdr = ip_hdr(skb);
3784 *tcph = tcp_hdr(skb);
3785 *hdr_flags = LRO_IPV4 | LRO_TCP;
3786
3787 return 0;
3788
3789}
3790#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3791
3792/**
3793 * igb_receive_skb - helper function to handle rx indications
d3352520 3794 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3795 * @status: descriptor status field as written by hardware
3796 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3797 * @skb: pointer to sk_buff to be indicated to stack
3798 **/
d3352520
AD		 3799static void igb_receive_skb(struct igb_ring *ring, u8 status,
3800 union e1000_adv_rx_desc * rx_desc,
3801 struct sk_buff *skb)
3802{
3803 struct igb_adapter * adapter = ring->adapter;
3804 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3805
3806#ifdef CONFIG_IGB_LRO
3807 if (adapter->netdev->features & NETIF_F_LRO &&
3808 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3809 if (vlan_extracted)
3810 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3811 adapter->vlgrp,
3812 le16_to_cpu(rx_desc->wb.upper.vlan),
3813 rx_desc);
3814 else
3815 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3816 ring->lro_used = 1;
3817 } else {
3818#endif
3819 if (vlan_extracted)
3820 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3821 le16_to_cpu(rx_desc->wb.upper.vlan));
3822 else
3823
3824 netif_receive_skb(skb);
3825#ifdef CONFIG_IGB_LRO
3826 }
3827#endif
9d5c8243
AK		 3828}
3829
3830
3831static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3832 u32 status_err, struct sk_buff *skb)
3833{
3834 skb->ip_summed = CHECKSUM_NONE;
3835
3836 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3837 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3838 return;
3839 /* TCP/UDP checksum error bit is set */
3840 if (status_err &
3841 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3842 /* let the stack verify checksum errors */
3843 adapter->hw_csum_err++;
3844 return;
3845 }
3846 /* It must be a TCP or UDP packet with a valid checksum */
3847 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3848 skb->ip_summed = CHECKSUM_UNNECESSARY;
3849
3850 adapter->hw_csum_good++;
3851}
3852
3b644cf6
MW		 3853static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3854 int *work_done, int budget)
9d5c8243 3855{
3b644cf6 3856 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3857 struct net_device *netdev = adapter->netdev;
3858 struct pci_dev *pdev = adapter->pdev;
3859 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3860 struct igb_buffer *buffer_info , *next_buffer;
3861 struct sk_buff *skb;
bf36c1a0 3862 unsigned int i;
9d5c8243
AK		 3863 u32 length, hlen, staterr;
3864 bool cleaned = false;
3865 int cleaned_count = 0;
3866 unsigned int total_bytes = 0, total_packets = 0;
3867
3868 i = rx_ring->next_to_clean;
3869 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3870 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3871
3872 while (staterr & E1000_RXD_STAT_DD) {
3873 if (*work_done >= budget)
3874 break;
3875 (*work_done)++;
3876 buffer_info = &rx_ring->buffer_info[i];
3877
3878 /* HW will not DMA in data larger than the given buffer, even
3879 * if it parses the (NFS, of course) header to be larger. In
3880 * that case, it fills the header buffer and spills the rest
3881 * into the page.
3882 */
7deb07b1
AV		 3883 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3884 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3885 if (hlen > adapter->rx_ps_hdr_size)
3886 hlen = adapter->rx_ps_hdr_size;
3887
3888 length = le16_to_cpu(rx_desc->wb.upper.length);
3889 cleaned = true;
3890 cleaned_count++;
3891
bf36c1a0
AD		 3892 skb = buffer_info->skb;
3893 prefetch(skb->data - NET_IP_ALIGN);
3894 buffer_info->skb = NULL;
3895 if (!adapter->rx_ps_hdr_size) {
3896 pci_unmap_single(pdev, buffer_info->dma,
3897 adapter->rx_buffer_len +
3898 NET_IP_ALIGN,
3899 PCI_DMA_FROMDEVICE);
3900 skb_put(skb, length);
3901 goto send_up;
9d5c8243
AK		 3902 }
3903
bf36c1a0
AD		 3904 if (!skb_shinfo(skb)->nr_frags) {
3905 pci_unmap_single(pdev, buffer_info->dma,
3906 adapter->rx_ps_hdr_size +
3907 NET_IP_ALIGN,
3908 PCI_DMA_FROMDEVICE);
3909 skb_put(skb, hlen);
3910 }
3911
3912 if (length) {
9d5c8243 3913 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3914 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3915 buffer_info->page_dma = 0;
bf36c1a0
AD		 3916
3917 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3918 buffer_info->page,
3919 buffer_info->page_offset,
3920 length);
3921
3922 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3923 (page_count(buffer_info->page) != 1))
3924 buffer_info->page = NULL;
3925 else
3926 get_page(buffer_info->page);
9d5c8243
AK		 3927
3928 skb->len += length;
3929 skb->data_len += length;
9d5c8243 3930
bf36c1a0 3931 skb->truesize += length;
9d5c8243
AK		 3932 }
3933send_up:
9d5c8243
AK		 3934 i++;
3935 if (i == rx_ring->count)
3936 i = 0;
3937 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3938 prefetch(next_rxd);
3939 next_buffer = &rx_ring->buffer_info[i];
3940
bf36c1a0
AD		 3941 if (!(staterr & E1000_RXD_STAT_EOP)) {
3942 buffer_info->skb = xchg(&next_buffer->skb, skb);
3943 buffer_info->dma = xchg(&next_buffer->dma, 0);
3944 goto next_desc;
3945 }
3946
9d5c8243
AK		 3947 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3948 dev_kfree_skb_irq(skb);
3949 goto next_desc;
3950 }
9d5c8243
AK		 3951
3952 total_bytes += skb->len;
3953 total_packets++;
3954
3955 igb_rx_checksum_adv(adapter, staterr, skb);
3956
3957 skb->protocol = eth_type_trans(skb, netdev);
3958
d3352520 3959 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243
AK		 3960
3961 netdev->last_rx = jiffies;
3962
3963next_desc:
3964 rx_desc->wb.upper.status_error = 0;
3965
3966 /* return some buffers to hardware, one at a time is too slow */
3967 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3968 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3969 cleaned_count = 0;
3970 }
3971
3972 /* use prefetched values */
3973 rx_desc = next_rxd;
3974 buffer_info = next_buffer;
3975
3976 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3977 }
bf36c1a0 3978
9d5c8243
AK		 3979 rx_ring->next_to_clean = i;
3980 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3981
d3352520
AD		 3982#ifdef CONFIG_IGB_LRO
3983 if (rx_ring->lro_used) {
3984 lro_flush_all(&rx_ring->lro_mgr);
3985 rx_ring->lro_used = 0;
3986 }
3987#endif
3988
9d5c8243 3989 if (cleaned_count)
3b644cf6 3990 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3991
3992 rx_ring->total_packets += total_packets;
3993 rx_ring->total_bytes += total_bytes;
3994 rx_ring->rx_stats.packets += total_packets;
3995 rx_ring->rx_stats.bytes += total_bytes;
3996 adapter->net_stats.rx_bytes += total_bytes;
3997 adapter->net_stats.rx_packets += total_packets;
3998 return cleaned;
3999}
4000
4001
4002/**
4003 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4004 * @adapter: address of board private structure
4005 **/
3b644cf6 4006static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4007 int cleaned_count)
4008{
3b644cf6 4009 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4010 struct net_device *netdev = adapter->netdev;
4011 struct pci_dev *pdev = adapter->pdev;
4012 union e1000_adv_rx_desc *rx_desc;
4013 struct igb_buffer *buffer_info;
4014 struct sk_buff *skb;
4015 unsigned int i;
4016
4017 i = rx_ring->next_to_use;
4018 buffer_info = &rx_ring->buffer_info[i];
4019
4020 while (cleaned_count--) {
4021 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4022
bf36c1a0 4023 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4024 if (!buffer_info->page) {
bf36c1a0
AD		 4025 buffer_info->page = alloc_page(GFP_ATOMIC);
4026 if (!buffer_info->page) {
4027 adapter->alloc_rx_buff_failed++;
4028 goto no_buffers;
4029 }
4030 buffer_info->page_offset = 0;
4031 } else {
4032 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4033 }
4034 buffer_info->page_dma =
4035 pci_map_page(pdev,
4036 buffer_info->page,
bf36c1a0
AD		 4037 buffer_info->page_offset,
4038 PAGE_SIZE / 2,
9d5c8243
AK		 4039 PCI_DMA_FROMDEVICE);
4040 }
4041
4042 if (!buffer_info->skb) {
4043 int bufsz;
4044
4045 if (adapter->rx_ps_hdr_size)
4046 bufsz = adapter->rx_ps_hdr_size;
4047 else
4048 bufsz = adapter->rx_buffer_len;
4049 bufsz += NET_IP_ALIGN;
4050 skb = netdev_alloc_skb(netdev, bufsz);
4051
4052 if (!skb) {
4053 adapter->alloc_rx_buff_failed++;
4054 goto no_buffers;
4055 }
4056
4057 /* Make buffer alignment 2 beyond a 16 byte boundary
4058 * this will result in a 16 byte aligned IP header after
4059 * the 14 byte MAC header is removed
4060 */
4061 skb_reserve(skb, NET_IP_ALIGN);
4062
4063 buffer_info->skb = skb;
4064 buffer_info->dma = pci_map_single(pdev, skb->data,
4065 bufsz,
4066 PCI_DMA_FROMDEVICE);
4067
4068 }
4069 /* Refresh the desc even if buffer_addrs didn't change because
4070 * each write-back erases this info. */
4071 if (adapter->rx_ps_hdr_size) {
4072 rx_desc->read.pkt_addr =
4073 cpu_to_le64(buffer_info->page_dma);
4074 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4075 } else {
4076 rx_desc->read.pkt_addr =
4077 cpu_to_le64(buffer_info->dma);
4078 rx_desc->read.hdr_addr = 0;
4079 }
4080
4081 i++;
4082 if (i == rx_ring->count)
4083 i = 0;
4084 buffer_info = &rx_ring->buffer_info[i];
4085 }
4086
4087no_buffers:
4088 if (rx_ring->next_to_use != i) {
4089 rx_ring->next_to_use = i;
4090 if (i == 0)
4091 i = (rx_ring->count - 1);
4092 else
4093 i--;
4094
4095 /* Force memory writes to complete before letting h/w
4096 * know there are new descriptors to fetch. (Only
4097 * applicable for weak-ordered memory model archs,
4098 * such as IA-64). */
4099 wmb();
4100 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4101 }
4102}
4103
4104/**
4105 * igb_mii_ioctl -
4106 * @netdev:
4107 * @ifreq:
4108 * @cmd:
4109 **/
4110static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4111{
4112 struct igb_adapter *adapter = netdev_priv(netdev);
4113 struct mii_ioctl_data *data = if_mii(ifr);
4114
4115 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4116 return -EOPNOTSUPP;
4117
4118 switch (cmd) {
4119 case SIOCGMIIPHY:
4120 data->phy_id = adapter->hw.phy.addr;
4121 break;
4122 case SIOCGMIIREG:
4123 if (!capable(CAP_NET_ADMIN))
4124 return -EPERM;
4125 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4126 data->reg_num
4127 & 0x1F, &data->val_out))
4128 return -EIO;
4129 break;
4130 case SIOCSMIIREG:
4131 default:
4132 return -EOPNOTSUPP;
4133 }
4134 return 0;
4135}
4136
4137/**
4138 * igb_ioctl -
4139 * @netdev:
4140 * @ifreq:
4141 * @cmd:
4142 **/
4143static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4144{
4145 switch (cmd) {
4146 case SIOCGMIIPHY:
4147 case SIOCGMIIREG:
4148 case SIOCSMIIREG:
4149 return igb_mii_ioctl(netdev, ifr, cmd);
4150 default:
4151 return -EOPNOTSUPP;
4152 }
4153}
4154
4155static void igb_vlan_rx_register(struct net_device *netdev,
4156 struct vlan_group *grp)
4157{
4158 struct igb_adapter *adapter = netdev_priv(netdev);
4159 struct e1000_hw *hw = &adapter->hw;
4160 u32 ctrl, rctl;
4161
4162 igb_irq_disable(adapter);
4163 adapter->vlgrp = grp;
4164
4165 if (grp) {
4166 /* enable VLAN tag insert/strip */
4167 ctrl = rd32(E1000_CTRL);
4168 ctrl |= E1000_CTRL_VME;
4169 wr32(E1000_CTRL, ctrl);
4170
4171 /* enable VLAN receive filtering */
4172 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4173 rctl &= ~E1000_RCTL_CFIEN;
4174 wr32(E1000_RCTL, rctl);
4175 igb_update_mng_vlan(adapter);
4176 wr32(E1000_RLPML,
4177 adapter->max_frame_size + VLAN_TAG_SIZE);
4178 } else {
4179 /* disable VLAN tag insert/strip */
4180 ctrl = rd32(E1000_CTRL);
4181 ctrl &= ~E1000_CTRL_VME;
4182 wr32(E1000_CTRL, ctrl);
4183
9d5c8243
AK		 4184 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4185 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4186 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4187 }
4188 wr32(E1000_RLPML,
4189 adapter->max_frame_size);
4190 }
4191
4192 if (!test_bit(__IGB_DOWN, &adapter->state))
4193 igb_irq_enable(adapter);
4194}
4195
4196static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4197{
4198 struct igb_adapter *adapter = netdev_priv(netdev);
4199 struct e1000_hw *hw = &adapter->hw;
4200 u32 vfta, index;
4201
4202 if ((adapter->hw.mng_cookie.status &
4203 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4204 (vid == adapter->mng_vlan_id))
4205 return;
4206 /* add VID to filter table */
4207 index = (vid >> 5) & 0x7F;
4208 vfta = array_rd32(E1000_VFTA, index);
4209 vfta |= (1 << (vid & 0x1F));
4210 igb_write_vfta(&adapter->hw, index, vfta);
4211}
4212
4213static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4214{
4215 struct igb_adapter *adapter = netdev_priv(netdev);
4216 struct e1000_hw *hw = &adapter->hw;
4217 u32 vfta, index;
4218
4219 igb_irq_disable(adapter);
4220 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4221
4222 if (!test_bit(__IGB_DOWN, &adapter->state))
4223 igb_irq_enable(adapter);
4224
4225 if ((adapter->hw.mng_cookie.status &
4226 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4227 (vid == adapter->mng_vlan_id)) {
4228 /* release control to f/w */
4229 igb_release_hw_control(adapter);
4230 return;
4231 }
4232
4233 /* remove VID from filter table */
4234 index = (vid >> 5) & 0x7F;
4235 vfta = array_rd32(E1000_VFTA, index);
4236 vfta &= ~(1 << (vid & 0x1F));
4237 igb_write_vfta(&adapter->hw, index, vfta);
4238}
4239
4240static void igb_restore_vlan(struct igb_adapter *adapter)
4241{
4242 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4243
4244 if (adapter->vlgrp) {
4245 u16 vid;
4246 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4247 if (!vlan_group_get_device(adapter->vlgrp, vid))
4248 continue;
4249 igb_vlan_rx_add_vid(adapter->netdev, vid);
4250 }
4251 }
4252}
4253
4254int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4255{
4256 struct e1000_mac_info *mac = &adapter->hw.mac;
4257
4258 mac->autoneg = 0;
4259
4260 /* Fiber NICs only allow 1000 gbps Full duplex */
4261 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4262 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4263 dev_err(&adapter->pdev->dev,
4264 "Unsupported Speed/Duplex configuration\n");
4265 return -EINVAL;
4266 }
4267
4268 switch (spddplx) {
4269 case SPEED_10 + DUPLEX_HALF:
4270 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4271 break;
4272 case SPEED_10 + DUPLEX_FULL:
4273 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4274 break;
4275 case SPEED_100 + DUPLEX_HALF:
4276 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4277 break;
4278 case SPEED_100 + DUPLEX_FULL:
4279 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4280 break;
4281 case SPEED_1000 + DUPLEX_FULL:
4282 mac->autoneg = 1;
4283 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4284 break;
4285 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4286 default:
4287 dev_err(&adapter->pdev->dev,
4288 "Unsupported Speed/Duplex configuration\n");
4289 return -EINVAL;
4290 }
4291 return 0;
4292}
4293
4294
4295static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4296{
4297 struct net_device *netdev = pci_get_drvdata(pdev);
4298 struct igb_adapter *adapter = netdev_priv(netdev);
4299 struct e1000_hw *hw = &adapter->hw;
2d064c06 4300 u32 ctrl, rctl, status;
9d5c8243
AK		 4301 u32 wufc = adapter->wol;
4302#ifdef CONFIG_PM
4303 int retval = 0;
4304#endif
4305
4306 netif_device_detach(netdev);
4307
a88f10ec
AD		 4308 if (netif_running(netdev))
4309 igb_close(netdev);
4310
4311 igb_reset_interrupt_capability(adapter);
4312
4313 igb_free_queues(adapter);
9d5c8243
AK		 4314
4315#ifdef CONFIG_PM
4316 retval = pci_save_state(pdev);
4317 if (retval)
4318 return retval;
4319#endif
4320
4321 status = rd32(E1000_STATUS);
4322 if (status & E1000_STATUS_LU)
4323 wufc &= ~E1000_WUFC_LNKC;
4324
4325 if (wufc) {
4326 igb_setup_rctl(adapter);
4327 igb_set_multi(netdev);
4328
4329 /* turn on all-multi mode if wake on multicast is enabled */
4330 if (wufc & E1000_WUFC_MC) {
4331 rctl = rd32(E1000_RCTL);
4332 rctl |= E1000_RCTL_MPE;
4333 wr32(E1000_RCTL, rctl);
4334 }
4335
4336 ctrl = rd32(E1000_CTRL);
4337 /* advertise wake from D3Cold */
4338 #define E1000_CTRL_ADVD3WUC 0x00100000
4339 /* phy power management enable */
4340 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4341 ctrl |= E1000_CTRL_ADVD3WUC;
4342 wr32(E1000_CTRL, ctrl);
4343
9d5c8243
AK		 4344 /* Allow time for pending master requests to run */
4345 igb_disable_pcie_master(&adapter->hw);
4346
4347 wr32(E1000_WUC, E1000_WUC_PME_EN);
4348 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4349 } else {
4350 wr32(E1000_WUC, 0);
4351 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4352 }
4353
2d064c06
AD		 4354 /* make sure adapter isn't asleep if manageability/wol is enabled */
4355 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4356 pci_enable_wake(pdev, PCI_D3hot, 1);
4357 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4358 } else {
4359 igb_shutdown_fiber_serdes_link_82575(hw);
4360 pci_enable_wake(pdev, PCI_D3hot, 0);
4361 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4362 }
4363
4364 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4365 * would have already happened in close and is redundant. */
4366 igb_release_hw_control(adapter);
4367
4368 pci_disable_device(pdev);
4369
4370 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4371
4372 return 0;
4373}
4374
4375#ifdef CONFIG_PM
4376static int igb_resume(struct pci_dev *pdev)
4377{
4378 struct net_device *netdev = pci_get_drvdata(pdev);
4379 struct igb_adapter *adapter = netdev_priv(netdev);
4380 struct e1000_hw *hw = &adapter->hw;
4381 u32 err;
4382
4383 pci_set_power_state(pdev, PCI_D0);
4384 pci_restore_state(pdev);
42bfd33a
TI		 4385
4386 if (adapter->need_ioport)
4387 err = pci_enable_device(pdev);
4388 else
4389 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4390 if (err) {
4391 dev_err(&pdev->dev,
4392 "igb: Cannot enable PCI device from suspend\n");
4393 return err;
4394 }
4395 pci_set_master(pdev);
4396
4397 pci_enable_wake(pdev, PCI_D3hot, 0);
4398 pci_enable_wake(pdev, PCI_D3cold, 0);
4399
a88f10ec
AD		 4400 igb_set_interrupt_capability(adapter);
4401
4402 if (igb_alloc_queues(adapter)) {
4403 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4404 return -ENOMEM;
9d5c8243
AK		 4405 }
4406
4407 /* e1000_power_up_phy(adapter); */
4408
4409 igb_reset(adapter);
4410 wr32(E1000_WUS, ~0);
4411
a88f10ec
AD		 4412 if (netif_running(netdev)) {
4413 err = igb_open(netdev);
4414 if (err)
4415 return err;
4416 }
9d5c8243
AK		 4417
4418 netif_device_attach(netdev);
4419
4420 /* let the f/w know that the h/w is now under the control of the
4421 * driver. */
4422 igb_get_hw_control(adapter);
4423
4424 return 0;
4425}
4426#endif
4427
4428static void igb_shutdown(struct pci_dev *pdev)
4429{
4430 igb_suspend(pdev, PMSG_SUSPEND);
4431}
4432
4433#ifdef CONFIG_NET_POLL_CONTROLLER
4434/*
4435 * Polling 'interrupt' - used by things like netconsole to send skbs
4436 * without having to re-enable interrupts. It's not called while
4437 * the interrupt routine is executing.
4438 */
4439static void igb_netpoll(struct net_device *netdev)
4440{
4441 struct igb_adapter *adapter = netdev_priv(netdev);
4442 int i;
4443 int work_done = 0;
4444
4445 igb_irq_disable(adapter);
7dfc16fa
AD		 4446 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4447
9d5c8243 4448 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4449 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4450
4451 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4452 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4453 &work_done,
4454 adapter->rx_ring[i].napi.weight);
4455
7dfc16fa 4456 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4457 igb_irq_enable(adapter);
4458}
4459#endif /* CONFIG_NET_POLL_CONTROLLER */
4460
4461/**
4462 * igb_io_error_detected - called when PCI error is detected
4463 * @pdev: Pointer to PCI device
4464 * @state: The current pci connection state
4465 *
4466 * This function is called after a PCI bus error affecting
4467 * this device has been detected.
4468 */
4469static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4470 pci_channel_state_t state)
4471{
4472 struct net_device *netdev = pci_get_drvdata(pdev);
4473 struct igb_adapter *adapter = netdev_priv(netdev);
4474
4475 netif_device_detach(netdev);
4476
4477 if (netif_running(netdev))
4478 igb_down(adapter);
4479 pci_disable_device(pdev);
4480
4481 /* Request a slot slot reset. */
4482 return PCI_ERS_RESULT_NEED_RESET;
4483}
4484
4485/**
4486 * igb_io_slot_reset - called after the pci bus has been reset.
4487 * @pdev: Pointer to PCI device
4488 *
4489 * Restart the card from scratch, as if from a cold-boot. Implementation
4490 * resembles the first-half of the igb_resume routine.
4491 */
4492static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4493{
4494 struct net_device *netdev = pci_get_drvdata(pdev);
4495 struct igb_adapter *adapter = netdev_priv(netdev);
4496 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4497 int err;
9d5c8243 4498
42bfd33a
TI		 4499 if (adapter->need_ioport)
4500 err = pci_enable_device(pdev);
4501 else
4502 err = pci_enable_device_mem(pdev);
4503 if (err) {
9d5c8243
AK		 4504 dev_err(&pdev->dev,
4505 "Cannot re-enable PCI device after reset.\n");
4506 return PCI_ERS_RESULT_DISCONNECT;
4507 }
4508 pci_set_master(pdev);
c682fc23 4509 pci_restore_state(pdev);
9d5c8243
AK		 4510
4511 pci_enable_wake(pdev, PCI_D3hot, 0);
4512 pci_enable_wake(pdev, PCI_D3cold, 0);
4513
4514 igb_reset(adapter);
4515 wr32(E1000_WUS, ~0);
4516
4517 return PCI_ERS_RESULT_RECOVERED;
4518}
4519
4520/**
4521 * igb_io_resume - called when traffic can start flowing again.
4522 * @pdev: Pointer to PCI device
4523 *
4524 * This callback is called when the error recovery driver tells us that
4525 * its OK to resume normal operation. Implementation resembles the
4526 * second-half of the igb_resume routine.
4527 */
4528static void igb_io_resume(struct pci_dev *pdev)
4529{
4530 struct net_device *netdev = pci_get_drvdata(pdev);
4531 struct igb_adapter *adapter = netdev_priv(netdev);
4532
4533 igb_init_manageability(adapter);
4534
4535 if (netif_running(netdev)) {
4536 if (igb_up(adapter)) {
4537 dev_err(&pdev->dev, "igb_up failed after reset\n");
4538 return;
4539 }
4540 }
4541
4542 netif_device_attach(netdev);
4543
4544 /* let the f/w know that the h/w is now under the control of the
4545 * driver. */
4546 igb_get_hw_control(adapter);
4547
4548}
4549
4550/* igb_main.c */
Linux kernel - Deliverables
This page took 0.330149 seconds and 5 git commands to generate.