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igb: remove unecessary q_vector declarations and remove itr_shift
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
55cac248 52#define DRV_VERSION "2.1.0-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
a3aa1884 63static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
55cac248
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
2d064c06 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
79 /* required last entry */
80 {0, }
81};
82
83MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
84
85void igb_reset(struct igb_adapter *);
86static int igb_setup_all_tx_resources(struct igb_adapter *);
87static int igb_setup_all_rx_resources(struct igb_adapter *);
88static void igb_free_all_tx_resources(struct igb_adapter *);
89static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 90static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 91void igb_update_stats(struct igb_adapter *);
92static int igb_probe(struct pci_dev *, const struct pci_device_id *);
93static void __devexit igb_remove(struct pci_dev *pdev);
94static int igb_sw_init(struct igb_adapter *);
95static int igb_open(struct net_device *);
96static int igb_close(struct net_device *);
97static void igb_configure_tx(struct igb_adapter *);
98static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 99static void igb_clean_all_tx_rings(struct igb_adapter *);
100static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 101static void igb_clean_tx_ring(struct igb_ring *);
102static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 103static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 104static void igb_update_phy_info(unsigned long);
105static void igb_watchdog(unsigned long);
106static void igb_watchdog_task(struct work_struct *);
b1a436c3 107static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
9d5c8243
AK		 108static struct net_device_stats *igb_get_stats(struct net_device *);
109static int igb_change_mtu(struct net_device *, int);
110static int igb_set_mac(struct net_device *, void *);
68d480c4 111static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 112static irqreturn_t igb_intr(int irq, void *);
113static irqreturn_t igb_intr_msi(int irq, void *);
114static irqreturn_t igb_msix_other(int irq, void *);
047e0030 115static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
047e0030 117static void igb_update_dca(struct igb_q_vector *);
fe4506b6 118static void igb_setup_dca(struct igb_adapter *);
421e02f0 119#endif /* CONFIG_IGB_DCA */
047e0030 120static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 121static int igb_poll(struct napi_struct *, int);
047e0030 122static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
26ad9178 130static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 131static void igb_ping_all_vfs(struct igb_adapter *);
132static void igb_msg_task(struct igb_adapter *);
4ae196df 133static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 134static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 135static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 136static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
137static int igb_ndo_set_vf_vlan(struct net_device *netdev,
138 int vf, u16 vlan, u8 qos);
139static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
140static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
141 struct ifla_vf_info *ivi);
9d5c8243 142
9d5c8243 143#ifdef CONFIG_PM
3fe7c4c9 144static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 145static int igb_resume(struct pci_dev *);
146#endif
147static void igb_shutdown(struct pci_dev *);
421e02f0 148#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 149static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
150static struct notifier_block dca_notifier = {
151 .notifier_call = igb_notify_dca,
152 .next = NULL,
153 .priority = 0
154};
155#endif
9d5c8243
AK		 156#ifdef CONFIG_NET_POLL_CONTROLLER
157/* for netdump / net console */
158static void igb_netpoll(struct net_device *);
159#endif
37680117 160#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 161static unsigned int max_vfs = 0;
162module_param(max_vfs, uint, 0);
163MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
164 "per physical function");
165#endif /* CONFIG_PCI_IOV */
166
9d5c8243
AK		 167static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
168 pci_channel_state_t);
169static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
170static void igb_io_resume(struct pci_dev *);
171
172static struct pci_error_handlers igb_err_handler = {
173 .error_detected = igb_io_error_detected,
174 .slot_reset = igb_io_slot_reset,
175 .resume = igb_io_resume,
176};
177
178
179static struct pci_driver igb_driver = {
180 .name = igb_driver_name,
181 .id_table = igb_pci_tbl,
182 .probe = igb_probe,
183 .remove = __devexit_p(igb_remove),
184#ifdef CONFIG_PM
185 /* Power Managment Hooks */
186 .suspend = igb_suspend,
187 .resume = igb_resume,
188#endif
189 .shutdown = igb_shutdown,
190 .err_handler = &igb_err_handler
191};
192
193MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
194MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
195MODULE_LICENSE("GPL");
196MODULE_VERSION(DRV_VERSION);
197
38c845c7
PO		 198/**
199 * igb_read_clock - read raw cycle counter (to be used by time counter)
200 */
201static cycle_t igb_read_clock(const struct cyclecounter *tc)
202{
203 struct igb_adapter *adapter =
204 container_of(tc, struct igb_adapter, cycles);
205 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 206 u64 stamp = 0;
207 int shift = 0;
38c845c7 208
55cac248
AD		 209 /*
210 * The timestamp latches on lowest register read. For the 82580
211 * the lowest register is SYSTIMR instead of SYSTIML. However we never
212 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
213 */
214 if (hw->mac.type == e1000_82580) {
215 stamp = rd32(E1000_SYSTIMR) >> 8;
216 shift = IGB_82580_TSYNC_SHIFT;
217 }
218
c5b9bd5e
AD		 219 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
220 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 221 return stamp;
222}
223
9d5c8243
AK		 224#ifdef DEBUG
225/**
226 * igb_get_hw_dev_name - return device name string
227 * used by hardware layer to print debugging information
228 **/
229char *igb_get_hw_dev_name(struct e1000_hw *hw)
230{
231 struct igb_adapter *adapter = hw->back;
232 return adapter->netdev->name;
233}
38c845c7
PO		 234
235/**
236 * igb_get_time_str - format current NIC and system time as string
237 */
238static char *igb_get_time_str(struct igb_adapter *adapter,
239 char buffer[160])
240{
241 cycle_t hw = adapter->cycles.read(&adapter->cycles);
242 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
243 struct timespec sys;
244 struct timespec delta;
245 getnstimeofday(&sys);
246
247 delta = timespec_sub(nic, sys);
248
249 sprintf(buffer,
33af6bcc
PO		 250 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
251 hw,
38c845c7
PO		 252 (long)nic.tv_sec, nic.tv_nsec,
253 (long)sys.tv_sec, sys.tv_nsec,
254 (long)delta.tv_sec, delta.tv_nsec);
255
256 return buffer;
257}
9d5c8243
AK		 258#endif
259
260/**
261 * igb_init_module - Driver Registration Routine
262 *
263 * igb_init_module is the first routine called when the driver is
264 * loaded. All it does is register with the PCI subsystem.
265 **/
266static int __init igb_init_module(void)
267{
268 int ret;
269 printk(KERN_INFO "%s - version %s\n",
270 igb_driver_string, igb_driver_version);
271
272 printk(KERN_INFO "%s\n", igb_copyright);
273
421e02f0 274#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 275 dca_register_notify(&dca_notifier);
276#endif
bbd98fe4 277 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 278 return ret;
279}
280
281module_init(igb_init_module);
282
283/**
284 * igb_exit_module - Driver Exit Cleanup Routine
285 *
286 * igb_exit_module is called just before the driver is removed
287 * from memory.
288 **/
289static void __exit igb_exit_module(void)
290{
421e02f0 291#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 292 dca_unregister_notify(&dca_notifier);
293#endif
9d5c8243
AK		 294 pci_unregister_driver(&igb_driver);
295}
296
297module_exit(igb_exit_module);
298
26bc19ec
AD		 299#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
300/**
301 * igb_cache_ring_register - Descriptor ring to register mapping
302 * @adapter: board private structure to initialize
303 *
304 * Once we know the feature-set enabled for the device, we'll cache
305 * the register offset the descriptor ring is assigned to.
306 **/
307static void igb_cache_ring_register(struct igb_adapter *adapter)
308{
ee1b9f06 309 int i = 0, j = 0;
047e0030 310 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 311
312 switch (adapter->hw.mac.type) {
313 case e1000_82576:
314 /* The queues are allocated for virtualization such that VF 0
315 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
316 * In order to avoid collision we start at the first free queue
317 * and continue consuming queues in the same sequence
318 */
ee1b9f06 319 if (adapter->vfs_allocated_count) {
a99955fc 320 for (; i < adapter->rss_queues; i++)
ee1b9f06
AD		 321 adapter->rx_ring[i].reg_idx = rbase_offset +
322 Q_IDX_82576(i);
a99955fc 323 for (; j < adapter->rss_queues; j++)
ee1b9f06
AD		 324 adapter->tx_ring[j].reg_idx = rbase_offset +
325 Q_IDX_82576(j);
326 }
26bc19ec 327 case e1000_82575:
55cac248 328 case e1000_82580:
26bc19ec 329 default:
ee1b9f06
AD		 330 for (; i < adapter->num_rx_queues; i++)
331 adapter->rx_ring[i].reg_idx = rbase_offset + i;
332 for (; j < adapter->num_tx_queues; j++)
333 adapter->tx_ring[j].reg_idx = rbase_offset + j;
26bc19ec
AD		 334 break;
335 }
336}
337
047e0030
AD		 338static void igb_free_queues(struct igb_adapter *adapter)
339{
340 kfree(adapter->tx_ring);
341 kfree(adapter->rx_ring);
342
343 adapter->tx_ring = NULL;
344 adapter->rx_ring = NULL;
345
346 adapter->num_rx_queues = 0;
347 adapter->num_tx_queues = 0;
348}
349
9d5c8243
AK		 350/**
351 * igb_alloc_queues - Allocate memory for all rings
352 * @adapter: board private structure to initialize
353 *
354 * We allocate one ring per queue at run-time since we don't know the
355 * number of queues at compile-time.
356 **/
357static int igb_alloc_queues(struct igb_adapter *adapter)
358{
359 int i;
360
361 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
362 sizeof(struct igb_ring), GFP_KERNEL);
363 if (!adapter->tx_ring)
047e0030 364 goto err;
9d5c8243
AK		 365
366 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
367 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 368 if (!adapter->rx_ring)
369 goto err;
6eb5a7f1 370
661086df
PWJ		 371 for (i = 0; i < adapter->num_tx_queues; i++) {
372 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 373 ring->count = adapter->tx_ring_count;
661086df 374 ring->queue_index = i;
80785298 375 ring->pdev = adapter->pdev;
e694e964 376 ring->netdev = adapter->netdev;
85ad76b2
AD		 377 /* For 82575, context index must be unique per ring. */
378 if (adapter->hw.mac.type == e1000_82575)
379 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
661086df 380 }
85ad76b2 381
9d5c8243
AK		 382 for (i = 0; i < adapter->num_rx_queues; i++) {
383 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 384 ring->count = adapter->rx_ring_count;
844290e5 385 ring->queue_index = i;
80785298 386 ring->pdev = adapter->pdev;
e694e964 387 ring->netdev = adapter->netdev;
4c844851 388 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 389 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
390 /* set flag indicating ring supports SCTP checksum offload */
391 if (adapter->hw.mac.type >= e1000_82576)
392 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
9d5c8243 393 }
26bc19ec
AD		 394
395 igb_cache_ring_register(adapter);
9d5c8243 396
047e0030 397 return 0;
a88f10ec 398
047e0030
AD		 399err:
400 igb_free_queues(adapter);
d1a8c9e1 401
047e0030 402 return -ENOMEM;
a88f10ec
AD		 403}
404
9d5c8243 405#define IGB_N0_QUEUE -1
047e0030 406static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 407{
408 u32 msixbm = 0;
047e0030 409 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 410 struct e1000_hw *hw = &adapter->hw;
2d064c06 411 u32 ivar, index;
047e0030
AD		 412 int rx_queue = IGB_N0_QUEUE;
413 int tx_queue = IGB_N0_QUEUE;
414
415 if (q_vector->rx_ring)
416 rx_queue = q_vector->rx_ring->reg_idx;
417 if (q_vector->tx_ring)
418 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 419
420 switch (hw->mac.type) {
421 case e1000_82575:
9d5c8243
AK		 422 /* The 82575 assigns vectors using a bitmask, which matches the
423 bitmask for the EICR/EIMS/EIMC registers. To assign one
424 or more queues to a vector, we write the appropriate bits
425 into the MSIXBM register for that vector. */
047e0030 426 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 427 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 428 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 429 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 430 if (!adapter->msix_entries && msix_vector == 0)
431 msixbm |= E1000_EIMS_OTHER;
9d5c8243 432 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 433 q_vector->eims_value = msixbm;
2d064c06
AD		 434 break;
435 case e1000_82576:
26bc19ec 436 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 437 Each queue has a single entry in the table to which we write
438 a vector number along with a "valid" bit. Sadly, the layout
439 of the table is somewhat counterintuitive. */
440 if (rx_queue > IGB_N0_QUEUE) {
047e0030 441 index = (rx_queue & 0x7);
2d064c06 442 ivar = array_rd32(E1000_IVAR0, index);
047e0030 443 if (rx_queue < 8) {
26bc19ec
AD		 444 /* vector goes into low byte of register */
445 ivar = ivar & 0xFFFFFF00;
446 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 447 } else {
448 /* vector goes into third byte of register */
449 ivar = ivar & 0xFF00FFFF;
450 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 451 }
2d064c06
AD		 452 array_wr32(E1000_IVAR0, index, ivar);
453 }
454 if (tx_queue > IGB_N0_QUEUE) {
047e0030 455 index = (tx_queue & 0x7);
2d064c06 456 ivar = array_rd32(E1000_IVAR0, index);
047e0030 457 if (tx_queue < 8) {
26bc19ec
AD		 458 /* vector goes into second byte of register */
459 ivar = ivar & 0xFFFF00FF;
460 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 461 } else {
462 /* vector goes into high byte of register */
463 ivar = ivar & 0x00FFFFFF;
464 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 465 }
2d064c06
AD		 466 array_wr32(E1000_IVAR0, index, ivar);
467 }
047e0030 468 q_vector->eims_value = 1 << msix_vector;
2d064c06 469 break;
55cac248
AD		 470 case e1000_82580:
471 /* 82580 uses the same table-based approach as 82576 but has fewer
472 entries as a result we carry over for queues greater than 4. */
473 if (rx_queue > IGB_N0_QUEUE) {
474 index = (rx_queue >> 1);
475 ivar = array_rd32(E1000_IVAR0, index);
476 if (rx_queue & 0x1) {
477 /* vector goes into third byte of register */
478 ivar = ivar & 0xFF00FFFF;
479 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
480 } else {
481 /* vector goes into low byte of register */
482 ivar = ivar & 0xFFFFFF00;
483 ivar |= msix_vector | E1000_IVAR_VALID;
484 }
485 array_wr32(E1000_IVAR0, index, ivar);
486 }
487 if (tx_queue > IGB_N0_QUEUE) {
488 index = (tx_queue >> 1);
489 ivar = array_rd32(E1000_IVAR0, index);
490 if (tx_queue & 0x1) {
491 /* vector goes into high byte of register */
492 ivar = ivar & 0x00FFFFFF;
493 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
494 } else {
495 /* vector goes into second byte of register */
496 ivar = ivar & 0xFFFF00FF;
497 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
498 }
499 array_wr32(E1000_IVAR0, index, ivar);
500 }
501 q_vector->eims_value = 1 << msix_vector;
502 break;
2d064c06
AD		 503 default:
504 BUG();
505 break;
506 }
26b39276
AD		 507
508 /* add q_vector eims value to global eims_enable_mask */
509 adapter->eims_enable_mask |= q_vector->eims_value;
510
511 /* configure q_vector to set itr on first interrupt */
512 q_vector->set_itr = 1;
9d5c8243
AK		 513}
514
515/**
516 * igb_configure_msix - Configure MSI-X hardware
517 *
518 * igb_configure_msix sets up the hardware to properly
519 * generate MSI-X interrupts.
520 **/
521static void igb_configure_msix(struct igb_adapter *adapter)
522{
523 u32 tmp;
524 int i, vector = 0;
525 struct e1000_hw *hw = &adapter->hw;
526
527 adapter->eims_enable_mask = 0;
9d5c8243
AK		 528
529 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 530 switch (hw->mac.type) {
531 case e1000_82575:
9d5c8243
AK		 532 tmp = rd32(E1000_CTRL_EXT);
533 /* enable MSI-X PBA support*/
534 tmp |= E1000_CTRL_EXT_PBA_CLR;
535
536 /* Auto-Mask interrupts upon ICR read. */
537 tmp |= E1000_CTRL_EXT_EIAME;
538 tmp |= E1000_CTRL_EXT_IRCA;
539
540 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 541
542 /* enable msix_other interrupt */
543 array_wr32(E1000_MSIXBM(0), vector++,
544 E1000_EIMS_OTHER);
844290e5 545 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 546
2d064c06
AD		 547 break;
548
549 case e1000_82576:
55cac248 550 case e1000_82580:
047e0030
AD		 551 /* Turn on MSI-X capability first, or our settings
552 * won't stick. And it will take days to debug. */
553 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
554 E1000_GPIE_PBA | E1000_GPIE_EIAME |
555 E1000_GPIE_NSICR);
556
557 /* enable msix_other interrupt */
558 adapter->eims_other = 1 << vector;
2d064c06 559 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 560
047e0030 561 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 562 break;
563 default:
564 /* do nothing, since nothing else supports MSI-X */
565 break;
566 } /* switch (hw->mac.type) */
047e0030
AD		 567
568 adapter->eims_enable_mask |= adapter->eims_other;
569
26b39276
AD		 570 for (i = 0; i < adapter->num_q_vectors; i++)
571 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 572
9d5c8243
AK		 573 wrfl();
574}
575
576/**
577 * igb_request_msix - Initialize MSI-X interrupts
578 *
579 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
580 * kernel.
581 **/
582static int igb_request_msix(struct igb_adapter *adapter)
583{
584 struct net_device *netdev = adapter->netdev;
047e0030 585 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 586 int i, err = 0, vector = 0;
587
047e0030 588 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 589 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 590 if (err)
591 goto out;
592 vector++;
593
594 for (i = 0; i < adapter->num_q_vectors; i++) {
595 struct igb_q_vector *q_vector = adapter->q_vector[i];
596
597 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
598
599 if (q_vector->rx_ring && q_vector->tx_ring)
600 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
601 q_vector->rx_ring->queue_index);
602 else if (q_vector->tx_ring)
603 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
604 q_vector->tx_ring->queue_index);
605 else if (q_vector->rx_ring)
606 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
607 q_vector->rx_ring->queue_index);
9d5c8243 608 else
047e0030
AD		 609 sprintf(q_vector->name, "%s-unused", netdev->name);
610
9d5c8243 611 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 612 igb_msix_ring, 0, q_vector->name,
047e0030 613 q_vector);
9d5c8243
AK		 614 if (err)
615 goto out;
9d5c8243
AK		 616 vector++;
617 }
618
9d5c8243
AK		 619 igb_configure_msix(adapter);
620 return 0;
621out:
622 return err;
623}
624
625static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
626{
627 if (adapter->msix_entries) {
628 pci_disable_msix(adapter->pdev);
629 kfree(adapter->msix_entries);
630 adapter->msix_entries = NULL;
047e0030 631 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 632 pci_disable_msi(adapter->pdev);
047e0030 633 }
9d5c8243
AK		 634}
635
047e0030
AD		 636/**
637 * igb_free_q_vectors - Free memory allocated for interrupt vectors
638 * @adapter: board private structure to initialize
639 *
640 * This function frees the memory allocated to the q_vectors. In addition if
641 * NAPI is enabled it will delete any references to the NAPI struct prior
642 * to freeing the q_vector.
643 **/
644static void igb_free_q_vectors(struct igb_adapter *adapter)
645{
646 int v_idx;
647
648 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
649 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
650 adapter->q_vector[v_idx] = NULL;
651 netif_napi_del(&q_vector->napi);
652 kfree(q_vector);
653 }
654 adapter->num_q_vectors = 0;
655}
656
657/**
658 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
659 *
660 * This function resets the device so that it has 0 rx queues, tx queues, and
661 * MSI-X interrupts allocated.
662 */
663static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
664{
665 igb_free_queues(adapter);
666 igb_free_q_vectors(adapter);
667 igb_reset_interrupt_capability(adapter);
668}
9d5c8243
AK		 669
670/**
671 * igb_set_interrupt_capability - set MSI or MSI-X if supported
672 *
673 * Attempt to configure interrupts using the best available
674 * capabilities of the hardware and kernel.
675 **/
676static void igb_set_interrupt_capability(struct igb_adapter *adapter)
677{
678 int err;
679 int numvecs, i;
680
83b7180d 681 /* Number of supported queues. */
a99955fc
AD		 682 adapter->num_rx_queues = adapter->rss_queues;
683 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 684
047e0030
AD		 685 /* start with one vector for every rx queue */
686 numvecs = adapter->num_rx_queues;
687
688 /* if tx handler is seperate add 1 for every tx queue */
a99955fc
AD		 689 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
690 numvecs += adapter->num_tx_queues;
047e0030
AD		 691
692 /* store the number of vectors reserved for queues */
693 adapter->num_q_vectors = numvecs;
694
695 /* add 1 vector for link status interrupts */
696 numvecs++;
9d5c8243
AK		 697 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
698 GFP_KERNEL);
699 if (!adapter->msix_entries)
700 goto msi_only;
701
702 for (i = 0; i < numvecs; i++)
703 adapter->msix_entries[i].entry = i;
704
705 err = pci_enable_msix(adapter->pdev,
706 adapter->msix_entries,
707 numvecs);
708 if (err == 0)
34a20e89 709 goto out;
9d5c8243
AK		 710
711 igb_reset_interrupt_capability(adapter);
712
713 /* If we can't do MSI-X, try MSI */
714msi_only:
2a3abf6d
AD		 715#ifdef CONFIG_PCI_IOV
716 /* disable SR-IOV for non MSI-X configurations */
717 if (adapter->vf_data) {
718 struct e1000_hw *hw = &adapter->hw;
719 /* disable iov and allow time for transactions to clear */
720 pci_disable_sriov(adapter->pdev);
721 msleep(500);
722
723 kfree(adapter->vf_data);
724 adapter->vf_data = NULL;
725 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
726 msleep(100);
727 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
728 }
729#endif
4fc82adf 730 adapter->vfs_allocated_count = 0;
a99955fc 731 adapter->rss_queues = 1;
4fc82adf 732 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 733 adapter->num_rx_queues = 1;
661086df 734 adapter->num_tx_queues = 1;
047e0030 735 adapter->num_q_vectors = 1;
9d5c8243 736 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 737 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 738out:
661086df 739 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 740 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 741 return;
742}
743
047e0030
AD		 744/**
745 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
746 * @adapter: board private structure to initialize
747 *
748 * We allocate one q_vector per queue interrupt. If allocation fails we
749 * return -ENOMEM.
750 **/
751static int igb_alloc_q_vectors(struct igb_adapter *adapter)
752{
753 struct igb_q_vector *q_vector;
754 struct e1000_hw *hw = &adapter->hw;
755 int v_idx;
756
757 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
758 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
759 if (!q_vector)
760 goto err_out;
761 q_vector->adapter = adapter;
047e0030
AD		 762 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
763 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 764 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
765 adapter->q_vector[v_idx] = q_vector;
766 }
767 return 0;
768
769err_out:
770 while (v_idx) {
771 v_idx--;
772 q_vector = adapter->q_vector[v_idx];
773 netif_napi_del(&q_vector->napi);
774 kfree(q_vector);
775 adapter->q_vector[v_idx] = NULL;
776 }
777 return -ENOMEM;
778}
779
780static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
781 int ring_idx, int v_idx)
782{
783 struct igb_q_vector *q_vector;
784
785 q_vector = adapter->q_vector[v_idx];
786 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
787 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 788 q_vector->itr_val = adapter->rx_itr_setting;
789 if (q_vector->itr_val && q_vector->itr_val <= 3)
790 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 791}
792
793static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
794 int ring_idx, int v_idx)
795{
796 struct igb_q_vector *q_vector;
797
798 q_vector = adapter->q_vector[v_idx];
799 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
800 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 801 q_vector->itr_val = adapter->tx_itr_setting;
802 if (q_vector->itr_val && q_vector->itr_val <= 3)
803 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 804}
805
806/**
807 * igb_map_ring_to_vector - maps allocated queues to vectors
808 *
809 * This function maps the recently allocated queues to vectors.
810 **/
811static int igb_map_ring_to_vector(struct igb_adapter *adapter)
812{
813 int i;
814 int v_idx = 0;
815
816 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
817 (adapter->num_q_vectors < adapter->num_tx_queues))
818 return -ENOMEM;
819
820 if (adapter->num_q_vectors >=
821 (adapter->num_rx_queues + adapter->num_tx_queues)) {
822 for (i = 0; i < adapter->num_rx_queues; i++)
823 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
824 for (i = 0; i < adapter->num_tx_queues; i++)
825 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
826 } else {
827 for (i = 0; i < adapter->num_rx_queues; i++) {
828 if (i < adapter->num_tx_queues)
829 igb_map_tx_ring_to_vector(adapter, i, v_idx);
830 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
831 }
832 for (; i < adapter->num_tx_queues; i++)
833 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
834 }
835 return 0;
836}
837
838/**
839 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
840 *
841 * This function initializes the interrupts and allocates all of the queues.
842 **/
843static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
844{
845 struct pci_dev *pdev = adapter->pdev;
846 int err;
847
848 igb_set_interrupt_capability(adapter);
849
850 err = igb_alloc_q_vectors(adapter);
851 if (err) {
852 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
853 goto err_alloc_q_vectors;
854 }
855
856 err = igb_alloc_queues(adapter);
857 if (err) {
858 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
859 goto err_alloc_queues;
860 }
861
862 err = igb_map_ring_to_vector(adapter);
863 if (err) {
864 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
865 goto err_map_queues;
866 }
867
868
869 return 0;
870err_map_queues:
871 igb_free_queues(adapter);
872err_alloc_queues:
873 igb_free_q_vectors(adapter);
874err_alloc_q_vectors:
875 igb_reset_interrupt_capability(adapter);
876 return err;
877}
878
9d5c8243
AK		 879/**
880 * igb_request_irq - initialize interrupts
881 *
882 * Attempts to configure interrupts using the best available
883 * capabilities of the hardware and kernel.
884 **/
885static int igb_request_irq(struct igb_adapter *adapter)
886{
887 struct net_device *netdev = adapter->netdev;
047e0030 888 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 889 int err = 0;
890
891 if (adapter->msix_entries) {
892 err = igb_request_msix(adapter);
844290e5 893 if (!err)
9d5c8243 894 goto request_done;
9d5c8243 895 /* fall back to MSI */
047e0030 896 igb_clear_interrupt_scheme(adapter);
9d5c8243 897 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 898 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 899 igb_free_all_tx_resources(adapter);
900 igb_free_all_rx_resources(adapter);
047e0030 901 adapter->num_tx_queues = 1;
9d5c8243 902 adapter->num_rx_queues = 1;
047e0030
AD		 903 adapter->num_q_vectors = 1;
904 err = igb_alloc_q_vectors(adapter);
905 if (err) {
906 dev_err(&pdev->dev,
907 "Unable to allocate memory for vectors\n");
908 goto request_done;
909 }
910 err = igb_alloc_queues(adapter);
911 if (err) {
912 dev_err(&pdev->dev,
913 "Unable to allocate memory for queues\n");
914 igb_free_q_vectors(adapter);
915 goto request_done;
916 }
917 igb_setup_all_tx_resources(adapter);
918 igb_setup_all_rx_resources(adapter);
844290e5 919 } else {
feeb2721 920 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 921 }
844290e5 922
7dfc16fa 923 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 924 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 925 netdev->name, adapter);
9d5c8243
AK		 926 if (!err)
927 goto request_done;
047e0030 928
9d5c8243
AK		 929 /* fall back to legacy interrupts */
930 igb_reset_interrupt_capability(adapter);
7dfc16fa 931 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 932 }
933
a0607fd3 934 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 935 netdev->name, adapter);
9d5c8243 936
6cb5e577 937 if (err)
9d5c8243
AK		 938 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
939 err);
9d5c8243
AK		 940
941request_done:
942 return err;
943}
944
945static void igb_free_irq(struct igb_adapter *adapter)
946{
9d5c8243
AK		 947 if (adapter->msix_entries) {
948 int vector = 0, i;
949
047e0030 950 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 951
047e0030
AD		 952 for (i = 0; i < adapter->num_q_vectors; i++) {
953 struct igb_q_vector *q_vector = adapter->q_vector[i];
954 free_irq(adapter->msix_entries[vector++].vector,
955 q_vector);
956 }
957 } else {
958 free_irq(adapter->pdev->irq, adapter);
9d5c8243 959 }
9d5c8243
AK		 960}
961
962/**
963 * igb_irq_disable - Mask off interrupt generation on the NIC
964 * @adapter: board private structure
965 **/
966static void igb_irq_disable(struct igb_adapter *adapter)
967{
968 struct e1000_hw *hw = &adapter->hw;
969
25568a53
AD		 970 /*
971 * we need to be careful when disabling interrupts. The VFs are also
972 * mapped into these registers and so clearing the bits can cause
973 * issues on the VF drivers so we only need to clear what we set
974 */
9d5c8243 975 if (adapter->msix_entries) {
2dfd1212
AD		 976 u32 regval = rd32(E1000_EIAM);
977 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
978 wr32(E1000_EIMC, adapter->eims_enable_mask);
979 regval = rd32(E1000_EIAC);
980 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 981 }
844290e5
PW		 982
983 wr32(E1000_IAM, 0);
9d5c8243
AK		 984 wr32(E1000_IMC, ~0);
985 wrfl();
986 synchronize_irq(adapter->pdev->irq);
987}
988
989/**
990 * igb_irq_enable - Enable default interrupt generation settings
991 * @adapter: board private structure
992 **/
993static void igb_irq_enable(struct igb_adapter *adapter)
994{
995 struct e1000_hw *hw = &adapter->hw;
996
997 if (adapter->msix_entries) {
25568a53 998 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 999 u32 regval = rd32(E1000_EIAC);
1000 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1001 regval = rd32(E1000_EIAM);
1002 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1003 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1004 if (adapter->vfs_allocated_count) {
4ae196df 1005 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1006 ims |= E1000_IMS_VMMB;
1007 }
55cac248
AD		 1008 if (adapter->hw.mac.type == e1000_82580)
1009 ims |= E1000_IMS_DRSTA;
1010
25568a53 1011 wr32(E1000_IMS, ims);
844290e5 1012 } else {
55cac248
AD		 1013 wr32(E1000_IMS, IMS_ENABLE_MASK |
1014 E1000_IMS_DRSTA);
1015 wr32(E1000_IAM, IMS_ENABLE_MASK |
1016 E1000_IMS_DRSTA);
844290e5 1017 }
9d5c8243
AK		 1018}
1019
1020static void igb_update_mng_vlan(struct igb_adapter *adapter)
1021{
51466239 1022 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1023 u16 vid = adapter->hw.mng_cookie.vlan_id;
1024 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1025
1026 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1027 /* add VID to filter table */
1028 igb_vfta_set(hw, vid, true);
1029 adapter->mng_vlan_id = vid;
1030 } else {
1031 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1032 }
1033
1034 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1035 (vid != old_vid) &&
1036 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1037 /* remove VID from filter table */
1038 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1039 }
1040}
1041
1042/**
1043 * igb_release_hw_control - release control of the h/w to f/w
1044 * @adapter: address of board private structure
1045 *
1046 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1047 * For ASF and Pass Through versions of f/w this means that the
1048 * driver is no longer loaded.
1049 *
1050 **/
1051static void igb_release_hw_control(struct igb_adapter *adapter)
1052{
1053 struct e1000_hw *hw = &adapter->hw;
1054 u32 ctrl_ext;
1055
1056 /* Let firmware take over control of h/w */
1057 ctrl_ext = rd32(E1000_CTRL_EXT);
1058 wr32(E1000_CTRL_EXT,
1059 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1060}
1061
9d5c8243
AK		 1062/**
1063 * igb_get_hw_control - get control of the h/w from f/w
1064 * @adapter: address of board private structure
1065 *
1066 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1067 * For ASF and Pass Through versions of f/w this means that
1068 * the driver is loaded.
1069 *
1070 **/
1071static void igb_get_hw_control(struct igb_adapter *adapter)
1072{
1073 struct e1000_hw *hw = &adapter->hw;
1074 u32 ctrl_ext;
1075
1076 /* Let firmware know the driver has taken over */
1077 ctrl_ext = rd32(E1000_CTRL_EXT);
1078 wr32(E1000_CTRL_EXT,
1079 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1080}
1081
9d5c8243
AK		 1082/**
1083 * igb_configure - configure the hardware for RX and TX
1084 * @adapter: private board structure
1085 **/
1086static void igb_configure(struct igb_adapter *adapter)
1087{
1088 struct net_device *netdev = adapter->netdev;
1089 int i;
1090
1091 igb_get_hw_control(adapter);
ff41f8dc 1092 igb_set_rx_mode(netdev);
9d5c8243
AK		 1093
1094 igb_restore_vlan(adapter);
9d5c8243 1095
85b430b4 1096 igb_setup_tctl(adapter);
06cf2666 1097 igb_setup_mrqc(adapter);
9d5c8243 1098 igb_setup_rctl(adapter);
85b430b4
AD		 1099
1100 igb_configure_tx(adapter);
9d5c8243 1101 igb_configure_rx(adapter);
662d7205
AD		 1102
1103 igb_rx_fifo_flush_82575(&adapter->hw);
1104
c493ea45 1105 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1106 * at least 1 descriptor unused to make sure
1107 * next_to_use != next_to_clean */
1108 for (i = 0; i < adapter->num_rx_queues; i++) {
1109 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1110 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1111 }
1112
1113
1114 adapter->tx_queue_len = netdev->tx_queue_len;
1115}
1116
1117
1118/**
1119 * igb_up - Open the interface and prepare it to handle traffic
1120 * @adapter: board private structure
1121 **/
9d5c8243
AK		 1122int igb_up(struct igb_adapter *adapter)
1123{
1124 struct e1000_hw *hw = &adapter->hw;
1125 int i;
1126
1127 /* hardware has been reset, we need to reload some things */
1128 igb_configure(adapter);
1129
1130 clear_bit(__IGB_DOWN, &adapter->state);
1131
047e0030
AD		 1132 for (i = 0; i < adapter->num_q_vectors; i++) {
1133 struct igb_q_vector *q_vector = adapter->q_vector[i];
1134 napi_enable(&q_vector->napi);
1135 }
844290e5 1136 if (adapter->msix_entries)
9d5c8243 1137 igb_configure_msix(adapter);
feeb2721
AD		 1138 else
1139 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1140
1141 /* Clear any pending interrupts. */
1142 rd32(E1000_ICR);
1143 igb_irq_enable(adapter);
1144
d4960307
AD		 1145 /* notify VFs that reset has been completed */
1146 if (adapter->vfs_allocated_count) {
1147 u32 reg_data = rd32(E1000_CTRL_EXT);
1148 reg_data |= E1000_CTRL_EXT_PFRSTD;
1149 wr32(E1000_CTRL_EXT, reg_data);
1150 }
1151
4cb9be7a
JB		 1152 netif_tx_start_all_queues(adapter->netdev);
1153
25568a53
AD		 1154 /* start the watchdog. */
1155 hw->mac.get_link_status = 1;
1156 schedule_work(&adapter->watchdog_task);
1157
9d5c8243
AK		 1158 return 0;
1159}
1160
1161void igb_down(struct igb_adapter *adapter)
1162{
9d5c8243 1163 struct net_device *netdev = adapter->netdev;
330a6d6a 1164 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1165 u32 tctl, rctl;
1166 int i;
1167
1168 /* signal that we're down so the interrupt handler does not
1169 * reschedule our watchdog timer */
1170 set_bit(__IGB_DOWN, &adapter->state);
1171
1172 /* disable receives in the hardware */
1173 rctl = rd32(E1000_RCTL);
1174 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1175 /* flush and sleep below */
1176
fd2ea0a7 1177 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1178
1179 /* disable transmits in the hardware */
1180 tctl = rd32(E1000_TCTL);
1181 tctl &= ~E1000_TCTL_EN;
1182 wr32(E1000_TCTL, tctl);
1183 /* flush both disables and wait for them to finish */
1184 wrfl();
1185 msleep(10);
1186
047e0030
AD		 1187 for (i = 0; i < adapter->num_q_vectors; i++) {
1188 struct igb_q_vector *q_vector = adapter->q_vector[i];
1189 napi_disable(&q_vector->napi);
1190 }
9d5c8243 1191
9d5c8243
AK		 1192 igb_irq_disable(adapter);
1193
1194 del_timer_sync(&adapter->watchdog_timer);
1195 del_timer_sync(&adapter->phy_info_timer);
1196
1197 netdev->tx_queue_len = adapter->tx_queue_len;
1198 netif_carrier_off(netdev);
04fe6358
AD		 1199
1200 /* record the stats before reset*/
1201 igb_update_stats(adapter);
1202
9d5c8243
AK		 1203 adapter->link_speed = 0;
1204 adapter->link_duplex = 0;
1205
3023682e
JK		 1206 if (!pci_channel_offline(adapter->pdev))
1207 igb_reset(adapter);
9d5c8243
AK		 1208 igb_clean_all_tx_rings(adapter);
1209 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1210#ifdef CONFIG_IGB_DCA
1211
1212 /* since we reset the hardware DCA settings were cleared */
1213 igb_setup_dca(adapter);
1214#endif
9d5c8243
AK		 1215}
1216
1217void igb_reinit_locked(struct igb_adapter *adapter)
1218{
1219 WARN_ON(in_interrupt());
1220 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1221 msleep(1);
1222 igb_down(adapter);
1223 igb_up(adapter);
1224 clear_bit(__IGB_RESETTING, &adapter->state);
1225}
1226
1227void igb_reset(struct igb_adapter *adapter)
1228{
090b1795 1229 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1230 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1231 struct e1000_mac_info *mac = &hw->mac;
1232 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1233 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1234 u16 hwm;
1235
1236 /* Repartition Pba for greater than 9k mtu
1237 * To take effect CTRL.RST is required.
1238 */
fa4dfae0 1239 switch (mac->type) {
55cac248
AD		 1240 case e1000_82580:
1241 pba = rd32(E1000_RXPBS);
1242 pba = igb_rxpbs_adjust_82580(pba);
1243 break;
fa4dfae0 1244 case e1000_82576:
d249be54
AD		 1245 pba = rd32(E1000_RXPBS);
1246 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1247 break;
1248 case e1000_82575:
1249 default:
1250 pba = E1000_PBA_34K;
1251 break;
2d064c06 1252 }
9d5c8243 1253
2d064c06
AD		 1254 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1255 (mac->type < e1000_82576)) {
9d5c8243
AK		 1256 /* adjust PBA for jumbo frames */
1257 wr32(E1000_PBA, pba);
1258
1259 /* To maintain wire speed transmits, the Tx FIFO should be
1260 * large enough to accommodate two full transmit packets,
1261 * rounded up to the next 1KB and expressed in KB. Likewise,
1262 * the Rx FIFO should be large enough to accommodate at least
1263 * one full receive packet and is similarly rounded up and
1264 * expressed in KB. */
1265 pba = rd32(E1000_PBA);
1266 /* upper 16 bits has Tx packet buffer allocation size in KB */
1267 tx_space = pba >> 16;
1268 /* lower 16 bits has Rx packet buffer allocation size in KB */
1269 pba &= 0xffff;
1270 /* the tx fifo also stores 16 bytes of information about the tx
1271 * but don't include ethernet FCS because hardware appends it */
1272 min_tx_space = (adapter->max_frame_size +
85e8d004 1273 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1274 ETH_FCS_LEN) * 2;
1275 min_tx_space = ALIGN(min_tx_space, 1024);
1276 min_tx_space >>= 10;
1277 /* software strips receive CRC, so leave room for it */
1278 min_rx_space = adapter->max_frame_size;
1279 min_rx_space = ALIGN(min_rx_space, 1024);
1280 min_rx_space >>= 10;
1281
1282 /* If current Tx allocation is less than the min Tx FIFO size,
1283 * and the min Tx FIFO size is less than the current Rx FIFO
1284 * allocation, take space away from current Rx allocation */
1285 if (tx_space < min_tx_space &&
1286 ((min_tx_space - tx_space) < pba)) {
1287 pba = pba - (min_tx_space - tx_space);
1288
1289 /* if short on rx space, rx wins and must trump tx
1290 * adjustment */
1291 if (pba < min_rx_space)
1292 pba = min_rx_space;
1293 }
2d064c06 1294 wr32(E1000_PBA, pba);
9d5c8243 1295 }
9d5c8243
AK		 1296
1297 /* flow control settings */
1298 /* The high water mark must be low enough to fit one full frame
1299 * (or the size used for early receive) above it in the Rx FIFO.
1300 * Set it to the lower of:
1301 * - 90% of the Rx FIFO size, or
1302 * - the full Rx FIFO size minus one full frame */
1303 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1304 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1305
d405ea3e
AD		 1306 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1307 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1308 fc->pause_time = 0xFFFF;
1309 fc->send_xon = 1;
0cce119a 1310 fc->current_mode = fc->requested_mode;
9d5c8243 1311
4ae196df
AD		 1312 /* disable receive for all VFs and wait one second */
1313 if (adapter->vfs_allocated_count) {
1314 int i;
1315 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
f2ca0dbe 1316 adapter->vf_data[i].flags = 0;
4ae196df
AD		 1317
1318 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1319 igb_ping_all_vfs(adapter);
4ae196df
AD		 1320
1321 /* disable transmits and receives */
1322 wr32(E1000_VFRE, 0);
1323 wr32(E1000_VFTE, 0);
1324 }
1325
9d5c8243 1326 /* Allow time for pending master requests to run */
330a6d6a 1327 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1328 wr32(E1000_WUC, 0);
1329
330a6d6a 1330 if (hw->mac.ops.init_hw(hw))
090b1795 1331 dev_err(&pdev->dev, "Hardware Error\n");
9d5c8243 1332
55cac248
AD		 1333 if (hw->mac.type == e1000_82580) {
1334 u32 reg = rd32(E1000_PCIEMISC);
1335 wr32(E1000_PCIEMISC,
1336 reg & ~E1000_PCIEMISC_LX_DECISION);
1337 }
9d5c8243
AK		 1338 igb_update_mng_vlan(adapter);
1339
1340 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1341 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1342
330a6d6a
AD		 1343 igb_reset_adaptive(hw);
1344 igb_get_phy_info(hw);
9d5c8243
AK		 1345}
1346
2e5c6922 1347static const struct net_device_ops igb_netdev_ops = {
559e9c49 1348 .ndo_open = igb_open,
2e5c6922 1349 .ndo_stop = igb_close,
00829823 1350 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1351 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1352 .ndo_set_rx_mode = igb_set_rx_mode,
1353 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1354 .ndo_set_mac_address = igb_set_mac,
1355 .ndo_change_mtu = igb_change_mtu,
1356 .ndo_do_ioctl = igb_ioctl,
1357 .ndo_tx_timeout = igb_tx_timeout,
1358 .ndo_validate_addr = eth_validate_addr,
1359 .ndo_vlan_rx_register = igb_vlan_rx_register,
1360 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1361 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1362 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1363 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1364 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1365 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1366#ifdef CONFIG_NET_POLL_CONTROLLER
1367 .ndo_poll_controller = igb_netpoll,
1368#endif
1369};
1370
9d5c8243
AK		 1371/**
1372 * igb_probe - Device Initialization Routine
1373 * @pdev: PCI device information struct
1374 * @ent: entry in igb_pci_tbl
1375 *
1376 * Returns 0 on success, negative on failure
1377 *
1378 * igb_probe initializes an adapter identified by a pci_dev structure.
1379 * The OS initialization, configuring of the adapter private structure,
1380 * and a hardware reset occur.
1381 **/
1382static int __devinit igb_probe(struct pci_dev *pdev,
1383 const struct pci_device_id *ent)
1384{
1385 struct net_device *netdev;
1386 struct igb_adapter *adapter;
1387 struct e1000_hw *hw;
4337e993
AD		 1388 u16 eeprom_data = 0;
1389 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1390 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1391 unsigned long mmio_start, mmio_len;
2d6a5e95 1392 int err, pci_using_dac;
9d5c8243
AK		 1393 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1394 u32 part_num;
1395
aed5dec3 1396 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1397 if (err)
1398 return err;
1399
1400 pci_using_dac = 0;
6a35528a 1401 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1402 if (!err) {
6a35528a 1403 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1404 if (!err)
1405 pci_using_dac = 1;
1406 } else {
284901a9 1407 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1408 if (err) {
284901a9 1409 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1410 if (err) {
1411 dev_err(&pdev->dev, "No usable DMA "
1412 "configuration, aborting\n");
1413 goto err_dma;
1414 }
1415 }
1416 }
1417
aed5dec3
AD		 1418 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1419 IORESOURCE_MEM),
1420 igb_driver_name);
9d5c8243
AK		 1421 if (err)
1422 goto err_pci_reg;
1423
19d5afd4 1424 pci_enable_pcie_error_reporting(pdev);
40a914fa 1425
9d5c8243 1426 pci_set_master(pdev);
c682fc23 1427 pci_save_state(pdev);
9d5c8243
AK		 1428
1429 err = -ENOMEM;
1bfaf07b
AD		 1430 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1431 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1432 if (!netdev)
1433 goto err_alloc_etherdev;
1434
1435 SET_NETDEV_DEV(netdev, &pdev->dev);
1436
1437 pci_set_drvdata(pdev, netdev);
1438 adapter = netdev_priv(netdev);
1439 adapter->netdev = netdev;
1440 adapter->pdev = pdev;
1441 hw = &adapter->hw;
1442 hw->back = adapter;
1443 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1444
1445 mmio_start = pci_resource_start(pdev, 0);
1446 mmio_len = pci_resource_len(pdev, 0);
1447
1448 err = -EIO;
28b0759c
AD		 1449 hw->hw_addr = ioremap(mmio_start, mmio_len);
1450 if (!hw->hw_addr)
9d5c8243
AK		 1451 goto err_ioremap;
1452
2e5c6922 1453 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1454 igb_set_ethtool_ops(netdev);
9d5c8243 1455 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1456
1457 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1458
1459 netdev->mem_start = mmio_start;
1460 netdev->mem_end = mmio_start + mmio_len;
1461
9d5c8243
AK		 1462 /* PCI config space info */
1463 hw->vendor_id = pdev->vendor;
1464 hw->device_id = pdev->device;
1465 hw->revision_id = pdev->revision;
1466 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1467 hw->subsystem_device_id = pdev->subsystem_device;
1468
9d5c8243
AK		 1469 /* Copy the default MAC, PHY and NVM function pointers */
1470 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1471 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1472 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1473 /* Initialize skew-specific constants */
1474 err = ei->get_invariants(hw);
1475 if (err)
450c87c8 1476 goto err_sw_init;
9d5c8243 1477
450c87c8 1478 /* setup the private structure */
9d5c8243
AK		 1479 err = igb_sw_init(adapter);
1480 if (err)
1481 goto err_sw_init;
1482
1483 igb_get_bus_info_pcie(hw);
1484
1485 hw->phy.autoneg_wait_to_complete = false;
1486 hw->mac.adaptive_ifs = true;
1487
1488 /* Copper options */
1489 if (hw->phy.media_type == e1000_media_type_copper) {
1490 hw->phy.mdix = AUTO_ALL_MODES;
1491 hw->phy.disable_polarity_correction = false;
1492 hw->phy.ms_type = e1000_ms_hw_default;
1493 }
1494
1495 if (igb_check_reset_block(hw))
1496 dev_info(&pdev->dev,
1497 "PHY reset is blocked due to SOL/IDER session.\n");
1498
1499 netdev->features = NETIF_F_SG |
7d8eb29e 1500 NETIF_F_IP_CSUM |
9d5c8243
AK		 1501 NETIF_F_HW_VLAN_TX |
1502 NETIF_F_HW_VLAN_RX |
1503 NETIF_F_HW_VLAN_FILTER;
1504
7d8eb29e 1505 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1506 netdev->features |= NETIF_F_TSO;
9d5c8243 1507 netdev->features |= NETIF_F_TSO6;
5c0999b7 1508 netdev->features |= NETIF_F_GRO;
d3352520 1509
48f29ffc
JK		 1510 netdev->vlan_features |= NETIF_F_TSO;
1511 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1512 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1513 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1514 netdev->vlan_features |= NETIF_F_SG;
1515
9d5c8243
AK		 1516 if (pci_using_dac)
1517 netdev->features |= NETIF_F_HIGHDMA;
1518
5b043fb0 1519 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1520 netdev->features |= NETIF_F_SCTP_CSUM;
1521
330a6d6a 1522 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1523
1524 /* before reading the NVM, reset the controller to put the device in a
1525 * known good starting state */
1526 hw->mac.ops.reset_hw(hw);
1527
1528 /* make sure the NVM is good */
1529 if (igb_validate_nvm_checksum(hw) < 0) {
1530 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1531 err = -EIO;
1532 goto err_eeprom;
1533 }
1534
1535 /* copy the MAC address out of the NVM */
1536 if (hw->mac.ops.read_mac_addr(hw))
1537 dev_err(&pdev->dev, "NVM Read Error\n");
1538
1539 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1540 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1541
1542 if (!is_valid_ether_addr(netdev->perm_addr)) {
1543 dev_err(&pdev->dev, "Invalid MAC Address\n");
1544 err = -EIO;
1545 goto err_eeprom;
1546 }
1547
0e340485
AD		 1548 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1549 (unsigned long) adapter);
1550 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1551 (unsigned long) adapter);
9d5c8243
AK		 1552
1553 INIT_WORK(&adapter->reset_task, igb_reset_task);
1554 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1555
450c87c8 1556 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1557 adapter->fc_autoneg = true;
1558 hw->mac.autoneg = true;
1559 hw->phy.autoneg_advertised = 0x2f;
1560
0cce119a
AD		 1561 hw->fc.requested_mode = e1000_fc_default;
1562 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1563
9d5c8243
AK		 1564 igb_validate_mdi_setting(hw);
1565
9d5c8243
AK		 1566 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1567 * enable the ACPI Magic Packet filter
1568 */
1569
a2cf8b6c 1570 if (hw->bus.func == 0)
312c75ae 1571 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1572 else if (hw->mac.type == e1000_82580)
1573 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1574 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1575 &eeprom_data);
a2cf8b6c
AD		 1576 else if (hw->bus.func == 1)
1577 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1578
1579 if (eeprom_data & eeprom_apme_mask)
1580 adapter->eeprom_wol |= E1000_WUFC_MAG;
1581
1582 /* now that we have the eeprom settings, apply the special cases where
1583 * the eeprom may be wrong or the board simply won't support wake on
1584 * lan on a particular port */
1585 switch (pdev->device) {
1586 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1587 adapter->eeprom_wol = 0;
1588 break;
1589 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1590 case E1000_DEV_ID_82576_FIBER:
1591 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1592 /* Wake events only supported on port A for dual fiber
1593 * regardless of eeprom setting */
1594 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1595 adapter->eeprom_wol = 0;
1596 break;
c8ea5ea9
AD		 1597 case E1000_DEV_ID_82576_QUAD_COPPER:
1598 /* if quad port adapter, disable WoL on all but port A */
1599 if (global_quad_port_a != 0)
1600 adapter->eeprom_wol = 0;
1601 else
1602 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1603 /* Reset for multiple quad port adapters */
1604 if (++global_quad_port_a == 4)
1605 global_quad_port_a = 0;
1606 break;
9d5c8243
AK		 1607 }
1608
1609 /* initialize the wol settings based on the eeprom settings */
1610 adapter->wol = adapter->eeprom_wol;
e1b86d84 1611 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1612
1613 /* reset the hardware with the new settings */
1614 igb_reset(adapter);
1615
1616 /* let the f/w know that the h/w is now under the control of the
1617 * driver. */
1618 igb_get_hw_control(adapter);
1619
9d5c8243
AK		 1620 strcpy(netdev->name, "eth%d");
1621 err = register_netdev(netdev);
1622 if (err)
1623 goto err_register;
1624
b168dfc5
JB		 1625 /* carrier off reporting is important to ethtool even BEFORE open */
1626 netif_carrier_off(netdev);
1627
421e02f0 1628#ifdef CONFIG_IGB_DCA
bbd98fe4 1629 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1630 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1631 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1632 igb_setup_dca(adapter);
1633 }
fe4506b6 1634
38c845c7 1635#endif
9d5c8243
AK		 1636 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1637 /* print bus type/speed/width info */
7c510e4b 1638 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 1639 netdev->name,
559e9c49
AD		 1640 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1641 "unknown"),
59c3de89
AD		 1642 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1643 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1644 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1645 "unknown"),
7c510e4b 1646 netdev->dev_addr);
9d5c8243
AK		 1647
1648 igb_read_part_num(hw, &part_num);
1649 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1650 (part_num >> 8), (part_num & 0xff));
1651
1652 dev_info(&pdev->dev,
1653 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1654 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1655 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1656 adapter->num_rx_queues, adapter->num_tx_queues);
1657
9d5c8243
AK		 1658 return 0;
1659
1660err_register:
1661 igb_release_hw_control(adapter);
1662err_eeprom:
1663 if (!igb_check_reset_block(hw))
f5f4cf08 1664 igb_reset_phy(hw);
9d5c8243
AK		 1665
1666 if (hw->flash_address)
1667 iounmap(hw->flash_address);
9d5c8243 1668err_sw_init:
047e0030 1669 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1670 iounmap(hw->hw_addr);
1671err_ioremap:
1672 free_netdev(netdev);
1673err_alloc_etherdev:
559e9c49
AD		 1674 pci_release_selected_regions(pdev,
1675 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 1676err_pci_reg:
1677err_dma:
1678 pci_disable_device(pdev);
1679 return err;
1680}
1681
1682/**
1683 * igb_remove - Device Removal Routine
1684 * @pdev: PCI device information struct
1685 *
1686 * igb_remove is called by the PCI subsystem to alert the driver
1687 * that it should release a PCI device. The could be caused by a
1688 * Hot-Plug event, or because the driver is going to be removed from
1689 * memory.
1690 **/
1691static void __devexit igb_remove(struct pci_dev *pdev)
1692{
1693 struct net_device *netdev = pci_get_drvdata(pdev);
1694 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1695 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1696
1697 /* flush_scheduled work may reschedule our watchdog task, so
1698 * explicitly disable watchdog tasks from being rescheduled */
1699 set_bit(__IGB_DOWN, &adapter->state);
1700 del_timer_sync(&adapter->watchdog_timer);
1701 del_timer_sync(&adapter->phy_info_timer);
1702
1703 flush_scheduled_work();
1704
421e02f0 1705#ifdef CONFIG_IGB_DCA
7dfc16fa 1706 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1707 dev_info(&pdev->dev, "DCA disabled\n");
1708 dca_remove_requester(&pdev->dev);
7dfc16fa 1709 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1710 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1711 }
1712#endif
1713
9d5c8243
AK		 1714 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1715 * would have already happened in close and is redundant. */
1716 igb_release_hw_control(adapter);
1717
1718 unregister_netdev(netdev);
1719
330a6d6a
AD		 1720 if (!igb_check_reset_block(hw))
1721 igb_reset_phy(hw);
9d5c8243 1722
047e0030 1723 igb_clear_interrupt_scheme(adapter);
9d5c8243 1724
37680117
AD		 1725#ifdef CONFIG_PCI_IOV
1726 /* reclaim resources allocated to VFs */
1727 if (adapter->vf_data) {
1728 /* disable iov and allow time for transactions to clear */
1729 pci_disable_sriov(pdev);
1730 msleep(500);
1731
1732 kfree(adapter->vf_data);
1733 adapter->vf_data = NULL;
1734 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1735 msleep(100);
1736 dev_info(&pdev->dev, "IOV Disabled\n");
1737 }
1738#endif
559e9c49 1739
28b0759c
AD		 1740 iounmap(hw->hw_addr);
1741 if (hw->flash_address)
1742 iounmap(hw->flash_address);
559e9c49
AD		 1743 pci_release_selected_regions(pdev,
1744 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 1745
1746 free_netdev(netdev);
1747
19d5afd4 1748 pci_disable_pcie_error_reporting(pdev);
40a914fa 1749
9d5c8243
AK		 1750 pci_disable_device(pdev);
1751}
1752
a6b623e0
AD		 1753/**
1754 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
1755 * @adapter: board private structure to initialize
1756 *
1757 * This function initializes the vf specific data storage and then attempts to
1758 * allocate the VFs. The reason for ordering it this way is because it is much
1759 * mor expensive time wise to disable SR-IOV than it is to allocate and free
1760 * the memory for the VFs.
1761 **/
1762static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
1763{
1764#ifdef CONFIG_PCI_IOV
1765 struct pci_dev *pdev = adapter->pdev;
1766
1767 if (adapter->vfs_allocated_count > 7)
1768 adapter->vfs_allocated_count = 7;
1769
1770 if (adapter->vfs_allocated_count) {
1771 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
1772 sizeof(struct vf_data_storage),
1773 GFP_KERNEL);
1774 /* if allocation failed then we do not support SR-IOV */
1775 if (!adapter->vf_data) {
1776 adapter->vfs_allocated_count = 0;
1777 dev_err(&pdev->dev, "Unable to allocate memory for VF "
1778 "Data Storage\n");
1779 }
1780 }
1781
1782 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
1783 kfree(adapter->vf_data);
1784 adapter->vf_data = NULL;
1785#endif /* CONFIG_PCI_IOV */
1786 adapter->vfs_allocated_count = 0;
1787#ifdef CONFIG_PCI_IOV
1788 } else {
1789 unsigned char mac_addr[ETH_ALEN];
1790 int i;
1791 dev_info(&pdev->dev, "%d vfs allocated\n",
1792 adapter->vfs_allocated_count);
1793 for (i = 0; i < adapter->vfs_allocated_count; i++) {
1794 random_ether_addr(mac_addr);
1795 igb_set_vf_mac(adapter, i, mac_addr);
1796 }
1797 }
1798#endif /* CONFIG_PCI_IOV */
1799}
1800
115f459a
AD		 1801
1802/**
1803 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
1804 * @adapter: board private structure to initialize
1805 *
1806 * igb_init_hw_timer initializes the function pointer and values for the hw
1807 * timer found in hardware.
1808 **/
1809static void igb_init_hw_timer(struct igb_adapter *adapter)
1810{
1811 struct e1000_hw *hw = &adapter->hw;
1812
1813 switch (hw->mac.type) {
55cac248
AD		 1814 case e1000_82580:
1815 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1816 adapter->cycles.read = igb_read_clock;
1817 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1818 adapter->cycles.mult = 1;
1819 /*
1820 * The 82580 timesync updates the system timer every 8ns by 8ns
1821 * and the value cannot be shifted. Instead we need to shift
1822 * the registers to generate a 64bit timer value. As a result
1823 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
1824 * 24 in order to generate a larger value for synchronization.
1825 */
1826 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
1827 /* disable system timer temporarily by setting bit 31 */
1828 wr32(E1000_TSAUXC, 0x80000000);
1829 wrfl();
1830
1831 /* Set registers so that rollover occurs soon to test this. */
1832 wr32(E1000_SYSTIMR, 0x00000000);
1833 wr32(E1000_SYSTIML, 0x80000000);
1834 wr32(E1000_SYSTIMH, 0x000000FF);
1835 wrfl();
1836
1837 /* enable system timer by clearing bit 31 */
1838 wr32(E1000_TSAUXC, 0x0);
1839 wrfl();
1840
1841 timecounter_init(&adapter->clock,
1842 &adapter->cycles,
1843 ktime_to_ns(ktime_get_real()));
1844 /*
1845 * Synchronize our NIC clock against system wall clock. NIC
1846 * time stamp reading requires ~3us per sample, each sample
1847 * was pretty stable even under load => only require 10
1848 * samples for each offset comparison.
1849 */
1850 memset(&adapter->compare, 0, sizeof(adapter->compare));
1851 adapter->compare.source = &adapter->clock;
1852 adapter->compare.target = ktime_get_real;
1853 adapter->compare.num_samples = 10;
1854 timecompare_update(&adapter->compare, 0);
1855 break;
115f459a
AD		 1856 case e1000_82576:
1857 /*
1858 * Initialize hardware timer: we keep it running just in case
1859 * that some program needs it later on.
1860 */
1861 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1862 adapter->cycles.read = igb_read_clock;
1863 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1864 adapter->cycles.mult = 1;
1865 /**
1866 * Scale the NIC clock cycle by a large factor so that
1867 * relatively small clock corrections can be added or
1868 * substracted at each clock tick. The drawbacks of a large
1869 * factor are a) that the clock register overflows more quickly
1870 * (not such a big deal) and b) that the increment per tick has
1871 * to fit into 24 bits. As a result we need to use a shift of
1872 * 19 so we can fit a value of 16 into the TIMINCA register.
1873 */
1874 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
1875 wr32(E1000_TIMINCA,
1876 (1 << E1000_TIMINCA_16NS_SHIFT) |
1877 (16 << IGB_82576_TSYNC_SHIFT));
1878
1879 /* Set registers so that rollover occurs soon to test this. */
1880 wr32(E1000_SYSTIML, 0x00000000);
1881 wr32(E1000_SYSTIMH, 0xFF800000);
1882 wrfl();
1883
1884 timecounter_init(&adapter->clock,
1885 &adapter->cycles,
1886 ktime_to_ns(ktime_get_real()));
1887 /*
1888 * Synchronize our NIC clock against system wall clock. NIC
1889 * time stamp reading requires ~3us per sample, each sample
1890 * was pretty stable even under load => only require 10
1891 * samples for each offset comparison.
1892 */
1893 memset(&adapter->compare, 0, sizeof(adapter->compare));
1894 adapter->compare.source = &adapter->clock;
1895 adapter->compare.target = ktime_get_real;
1896 adapter->compare.num_samples = 10;
1897 timecompare_update(&adapter->compare, 0);
1898 break;
1899 case e1000_82575:
1900 /* 82575 does not support timesync */
1901 default:
1902 break;
1903 }
1904
1905}
1906
9d5c8243
AK		 1907/**
1908 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1909 * @adapter: board private structure to initialize
1910 *
1911 * igb_sw_init initializes the Adapter private data structure.
1912 * Fields are initialized based on PCI device information and
1913 * OS network device settings (MTU size).
1914 **/
1915static int __devinit igb_sw_init(struct igb_adapter *adapter)
1916{
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct net_device *netdev = adapter->netdev;
1919 struct pci_dev *pdev = adapter->pdev;
1920
1921 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1922
68fd9910
AD		 1923 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1924 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 1925 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
1926 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
1927
9d5c8243
AK		 1928 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1929 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1930
a6b623e0
AD		 1931#ifdef CONFIG_PCI_IOV
1932 if (hw->mac.type == e1000_82576)
1933 adapter->vfs_allocated_count = max_vfs;
1934
1935#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 1936 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1937
1938 /*
1939 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
1940 * then we should combine the queues into a queue pair in order to
1941 * conserve interrupts due to limited supply
1942 */
1943 if ((adapter->rss_queues > 4) ||
1944 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
1945 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1946
a6b623e0 1947 /* This call may decrease the number of queues */
047e0030 1948 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1949 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1950 return -ENOMEM;
1951 }
1952
115f459a 1953 igb_init_hw_timer(adapter);
a6b623e0
AD		 1954 igb_probe_vfs(adapter);
1955
9d5c8243
AK		 1956 /* Explicitly disable IRQ since the NIC can be in any state. */
1957 igb_irq_disable(adapter);
1958
1959 set_bit(__IGB_DOWN, &adapter->state);
1960 return 0;
1961}
1962
1963/**
1964 * igb_open - Called when a network interface is made active
1965 * @netdev: network interface device structure
1966 *
1967 * Returns 0 on success, negative value on failure
1968 *
1969 * The open entry point is called when a network interface is made
1970 * active by the system (IFF_UP). At this point all resources needed
1971 * for transmit and receive operations are allocated, the interrupt
1972 * handler is registered with the OS, the watchdog timer is started,
1973 * and the stack is notified that the interface is ready.
1974 **/
1975static int igb_open(struct net_device *netdev)
1976{
1977 struct igb_adapter *adapter = netdev_priv(netdev);
1978 struct e1000_hw *hw = &adapter->hw;
1979 int err;
1980 int i;
1981
1982 /* disallow open during test */
1983 if (test_bit(__IGB_TESTING, &adapter->state))
1984 return -EBUSY;
1985
b168dfc5
JB		 1986 netif_carrier_off(netdev);
1987
9d5c8243
AK		 1988 /* allocate transmit descriptors */
1989 err = igb_setup_all_tx_resources(adapter);
1990 if (err)
1991 goto err_setup_tx;
1992
1993 /* allocate receive descriptors */
1994 err = igb_setup_all_rx_resources(adapter);
1995 if (err)
1996 goto err_setup_rx;
1997
1998 /* e1000_power_up_phy(adapter); */
1999
9d5c8243
AK		 2000 /* before we allocate an interrupt, we must be ready to handle it.
2001 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2002 * as soon as we call pci_request_irq, so we have to setup our
2003 * clean_rx handler before we do so. */
2004 igb_configure(adapter);
2005
2006 err = igb_request_irq(adapter);
2007 if (err)
2008 goto err_req_irq;
2009
2010 /* From here on the code is the same as igb_up() */
2011 clear_bit(__IGB_DOWN, &adapter->state);
2012
047e0030
AD		 2013 for (i = 0; i < adapter->num_q_vectors; i++) {
2014 struct igb_q_vector *q_vector = adapter->q_vector[i];
2015 napi_enable(&q_vector->napi);
2016 }
9d5c8243
AK		 2017
2018 /* Clear any pending interrupts. */
2019 rd32(E1000_ICR);
844290e5
PW		 2020
2021 igb_irq_enable(adapter);
2022
d4960307
AD		 2023 /* notify VFs that reset has been completed */
2024 if (adapter->vfs_allocated_count) {
2025 u32 reg_data = rd32(E1000_CTRL_EXT);
2026 reg_data |= E1000_CTRL_EXT_PFRSTD;
2027 wr32(E1000_CTRL_EXT, reg_data);
2028 }
2029
d55b53ff
JK		 2030 netif_tx_start_all_queues(netdev);
2031
25568a53
AD		 2032 /* start the watchdog. */
2033 hw->mac.get_link_status = 1;
2034 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2035
2036 return 0;
2037
2038err_req_irq:
2039 igb_release_hw_control(adapter);
2040 /* e1000_power_down_phy(adapter); */
2041 igb_free_all_rx_resources(adapter);
2042err_setup_rx:
2043 igb_free_all_tx_resources(adapter);
2044err_setup_tx:
2045 igb_reset(adapter);
2046
2047 return err;
2048}
2049
2050/**
2051 * igb_close - Disables a network interface
2052 * @netdev: network interface device structure
2053 *
2054 * Returns 0, this is not allowed to fail
2055 *
2056 * The close entry point is called when an interface is de-activated
2057 * by the OS. The hardware is still under the driver's control, but
2058 * needs to be disabled. A global MAC reset is issued to stop the
2059 * hardware, and all transmit and receive resources are freed.
2060 **/
2061static int igb_close(struct net_device *netdev)
2062{
2063 struct igb_adapter *adapter = netdev_priv(netdev);
2064
2065 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2066 igb_down(adapter);
2067
2068 igb_free_irq(adapter);
2069
2070 igb_free_all_tx_resources(adapter);
2071 igb_free_all_rx_resources(adapter);
2072
9d5c8243
AK		 2073 return 0;
2074}
2075
2076/**
2077 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2078 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2079 *
2080 * Return 0 on success, negative on failure
2081 **/
80785298 2082int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2083{
80785298 2084 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 2085 int size;
2086
2087 size = sizeof(struct igb_buffer) * tx_ring->count;
2088 tx_ring->buffer_info = vmalloc(size);
2089 if (!tx_ring->buffer_info)
2090 goto err;
2091 memset(tx_ring->buffer_info, 0, size);
2092
2093 /* round up to nearest 4K */
85e8d004 2094 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2095 tx_ring->size = ALIGN(tx_ring->size, 4096);
2096
439705e1
AD		 2097 tx_ring->desc = pci_alloc_consistent(pdev,
2098 tx_ring->size,
9d5c8243
AK		 2099 &tx_ring->dma);
2100
2101 if (!tx_ring->desc)
2102 goto err;
2103
9d5c8243
AK		 2104 tx_ring->next_to_use = 0;
2105 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2106 return 0;
2107
2108err:
2109 vfree(tx_ring->buffer_info);
047e0030 2110 dev_err(&pdev->dev,
9d5c8243
AK		 2111 "Unable to allocate memory for the transmit descriptor ring\n");
2112 return -ENOMEM;
2113}
2114
2115/**
2116 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2117 * (Descriptors) for all queues
2118 * @adapter: board private structure
2119 *
2120 * Return 0 on success, negative on failure
2121 **/
2122static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2123{
439705e1 2124 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2125 int i, err = 0;
2126
2127 for (i = 0; i < adapter->num_tx_queues; i++) {
80785298 2128 err = igb_setup_tx_resources(&adapter->tx_ring[i]);
9d5c8243 2129 if (err) {
439705e1 2130 dev_err(&pdev->dev,
9d5c8243
AK		 2131 "Allocation for Tx Queue %u failed\n", i);
2132 for (i--; i >= 0; i--)
3b644cf6 2133 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2134 break;
2135 }
2136 }
2137
a99955fc 2138 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2139 int r_idx = i % adapter->num_tx_queues;
661086df 2140 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2141 }
9d5c8243
AK		 2142 return err;
2143}
2144
2145/**
85b430b4
AD		 2146 * igb_setup_tctl - configure the transmit control registers
2147 * @adapter: Board private structure
9d5c8243 2148 **/
d7ee5b3a 2149void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2150{
9d5c8243
AK		 2151 struct e1000_hw *hw = &adapter->hw;
2152 u32 tctl;
9d5c8243 2153
85b430b4
AD		 2154 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2155 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2156
2157 /* Program the Transmit Control Register */
9d5c8243
AK		 2158 tctl = rd32(E1000_TCTL);
2159 tctl &= ~E1000_TCTL_CT;
2160 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2161 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2162
2163 igb_config_collision_dist(hw);
2164
9d5c8243
AK		 2165 /* Enable transmits */
2166 tctl |= E1000_TCTL_EN;
2167
2168 wr32(E1000_TCTL, tctl);
2169}
2170
85b430b4
AD		 2171/**
2172 * igb_configure_tx_ring - Configure transmit ring after Reset
2173 * @adapter: board private structure
2174 * @ring: tx ring to configure
2175 *
2176 * Configure a transmit ring after a reset.
2177 **/
d7ee5b3a
AD		 2178void igb_configure_tx_ring(struct igb_adapter *adapter,
2179 struct igb_ring *ring)
85b430b4
AD		 2180{
2181 struct e1000_hw *hw = &adapter->hw;
2182 u32 txdctl;
2183 u64 tdba = ring->dma;
2184 int reg_idx = ring->reg_idx;
2185
2186 /* disable the queue */
2187 txdctl = rd32(E1000_TXDCTL(reg_idx));
2188 wr32(E1000_TXDCTL(reg_idx),
2189 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2190 wrfl();
2191 mdelay(10);
2192
2193 wr32(E1000_TDLEN(reg_idx),
2194 ring->count * sizeof(union e1000_adv_tx_desc));
2195 wr32(E1000_TDBAL(reg_idx),
2196 tdba & 0x00000000ffffffffULL);
2197 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2198
fce99e34
AD		 2199 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2200 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2201 writel(0, ring->head);
2202 writel(0, ring->tail);
85b430b4
AD		 2203
2204 txdctl |= IGB_TX_PTHRESH;
2205 txdctl |= IGB_TX_HTHRESH << 8;
2206 txdctl |= IGB_TX_WTHRESH << 16;
2207
2208 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2209 wr32(E1000_TXDCTL(reg_idx), txdctl);
2210}
2211
2212/**
2213 * igb_configure_tx - Configure transmit Unit after Reset
2214 * @adapter: board private structure
2215 *
2216 * Configure the Tx unit of the MAC after a reset.
2217 **/
2218static void igb_configure_tx(struct igb_adapter *adapter)
2219{
2220 int i;
2221
2222 for (i = 0; i < adapter->num_tx_queues; i++)
2223 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
85b430b4
AD		 2224}
2225
9d5c8243
AK		 2226/**
2227 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2228 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2229 *
2230 * Returns 0 on success, negative on failure
2231 **/
80785298 2232int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2233{
80785298 2234 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2235 int size, desc_len;
2236
2237 size = sizeof(struct igb_buffer) * rx_ring->count;
2238 rx_ring->buffer_info = vmalloc(size);
2239 if (!rx_ring->buffer_info)
2240 goto err;
2241 memset(rx_ring->buffer_info, 0, size);
2242
2243 desc_len = sizeof(union e1000_adv_rx_desc);
2244
2245 /* Round up to nearest 4K */
2246 rx_ring->size = rx_ring->count * desc_len;
2247 rx_ring->size = ALIGN(rx_ring->size, 4096);
2248
2249 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2250 &rx_ring->dma);
2251
2252 if (!rx_ring->desc)
2253 goto err;
2254
2255 rx_ring->next_to_clean = 0;
2256 rx_ring->next_to_use = 0;
9d5c8243 2257
9d5c8243
AK		 2258 return 0;
2259
2260err:
2261 vfree(rx_ring->buffer_info);
439705e1 2262 rx_ring->buffer_info = NULL;
80785298 2263 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2264 "the receive descriptor ring\n");
2265 return -ENOMEM;
2266}
2267
2268/**
2269 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2270 * (Descriptors) for all queues
2271 * @adapter: board private structure
2272 *
2273 * Return 0 on success, negative on failure
2274 **/
2275static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2276{
439705e1 2277 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2278 int i, err = 0;
2279
2280 for (i = 0; i < adapter->num_rx_queues; i++) {
80785298 2281 err = igb_setup_rx_resources(&adapter->rx_ring[i]);
9d5c8243 2282 if (err) {
439705e1 2283 dev_err(&pdev->dev,
9d5c8243
AK		 2284 "Allocation for Rx Queue %u failed\n", i);
2285 for (i--; i >= 0; i--)
3b644cf6 2286 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2287 break;
2288 }
2289 }
2290
2291 return err;
2292}
2293
06cf2666
AD		 2294/**
2295 * igb_setup_mrqc - configure the multiple receive queue control registers
2296 * @adapter: Board private structure
2297 **/
2298static void igb_setup_mrqc(struct igb_adapter *adapter)
2299{
2300 struct e1000_hw *hw = &adapter->hw;
2301 u32 mrqc, rxcsum;
2302 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2303 union e1000_reta {
2304 u32 dword;
2305 u8 bytes[4];
2306 } reta;
2307 static const u8 rsshash[40] = {
2308 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2309 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2310 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2311 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2312
2313 /* Fill out hash function seeds */
2314 for (j = 0; j < 10; j++) {
2315 u32 rsskey = rsshash[(j * 4)];
2316 rsskey |= rsshash[(j * 4) + 1] << 8;
2317 rsskey |= rsshash[(j * 4) + 2] << 16;
2318 rsskey |= rsshash[(j * 4) + 3] << 24;
2319 array_wr32(E1000_RSSRK(0), j, rsskey);
2320 }
2321
a99955fc 2322 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2323
2324 if (adapter->vfs_allocated_count) {
2325 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2326 switch (hw->mac.type) {
55cac248
AD		 2327 case e1000_82580:
2328 num_rx_queues = 1;
2329 shift = 0;
2330 break;
06cf2666
AD		 2331 case e1000_82576:
2332 shift = 3;
2333 num_rx_queues = 2;
2334 break;
2335 case e1000_82575:
2336 shift = 2;
2337 shift2 = 6;
2338 default:
2339 break;
2340 }
2341 } else {
2342 if (hw->mac.type == e1000_82575)
2343 shift = 6;
2344 }
2345
2346 for (j = 0; j < (32 * 4); j++) {
2347 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2348 if (shift2)
2349 reta.bytes[j & 3] |= num_rx_queues << shift2;
2350 if ((j & 3) == 3)
2351 wr32(E1000_RETA(j >> 2), reta.dword);
2352 }
2353
2354 /*
2355 * Disable raw packet checksumming so that RSS hash is placed in
2356 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2357 * offloads as they are enabled by default
2358 */
2359 rxcsum = rd32(E1000_RXCSUM);
2360 rxcsum |= E1000_RXCSUM_PCSD;
2361
2362 if (adapter->hw.mac.type >= e1000_82576)
2363 /* Enable Receive Checksum Offload for SCTP */
2364 rxcsum |= E1000_RXCSUM_CRCOFL;
2365
2366 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2367 wr32(E1000_RXCSUM, rxcsum);
2368
2369 /* If VMDq is enabled then we set the appropriate mode for that, else
2370 * we default to RSS so that an RSS hash is calculated per packet even
2371 * if we are only using one queue */
2372 if (adapter->vfs_allocated_count) {
2373 if (hw->mac.type > e1000_82575) {
2374 /* Set the default pool for the PF's first queue */
2375 u32 vtctl = rd32(E1000_VT_CTL);
2376 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2377 E1000_VT_CTL_DISABLE_DEF_POOL);
2378 vtctl |= adapter->vfs_allocated_count <<
2379 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2380 wr32(E1000_VT_CTL, vtctl);
2381 }
a99955fc 2382 if (adapter->rss_queues > 1)
06cf2666
AD		 2383 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2384 else
2385 mrqc = E1000_MRQC_ENABLE_VMDQ;
2386 } else {
2387 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2388 }
2389 igb_vmm_control(adapter);
2390
2391 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2392 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2393 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2394 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2395 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2396 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2397 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2398 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2399
2400 wr32(E1000_MRQC, mrqc);
2401}
2402
9d5c8243
AK		 2403/**
2404 * igb_setup_rctl - configure the receive control registers
2405 * @adapter: Board private structure
2406 **/
d7ee5b3a 2407void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2408{
2409 struct e1000_hw *hw = &adapter->hw;
2410 u32 rctl;
9d5c8243
AK		 2411
2412 rctl = rd32(E1000_RCTL);
2413
2414 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2415 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2416
69d728ba 2417 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2418 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2419
87cb7e8c
AK		 2420 /*
2421 * enable stripping of CRC. It's unlikely this will break BMC
2422 * redirection as it did with e1000. Newer features require
2423 * that the HW strips the CRC.
73cd78f1 2424 */
87cb7e8c 2425 rctl |= E1000_RCTL_SECRC;
9d5c8243 2426
559e9c49 2427 /* disable store bad packets and clear size bits. */
ec54d7d6 2428 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2429
6ec43fe6
AD		 2430 /* enable LPE to prevent packets larger than max_frame_size */
2431 rctl |= E1000_RCTL_LPE;
9d5c8243 2432
952f72a8
AD		 2433 /* disable queue 0 to prevent tail write w/o re-config */
2434 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2435
e1739522
AD		 2436 /* Attention!!! For SR-IOV PF driver operations you must enable
2437 * queue drop for all VF and PF queues to prevent head of line blocking
2438 * if an un-trusted VF does not provide descriptors to hardware.
2439 */
2440 if (adapter->vfs_allocated_count) {
e1739522
AD		 2441 /* set all queue drop enable bits */
2442 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2443 }
2444
9d5c8243
AK		 2445 wr32(E1000_RCTL, rctl);
2446}
2447
7d5753f0
AD		 2448static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2449 int vfn)
2450{
2451 struct e1000_hw *hw = &adapter->hw;
2452 u32 vmolr;
2453
2454 /* if it isn't the PF check to see if VFs are enabled and
2455 * increase the size to support vlan tags */
2456 if (vfn < adapter->vfs_allocated_count &&
2457 adapter->vf_data[vfn].vlans_enabled)
2458 size += VLAN_TAG_SIZE;
2459
2460 vmolr = rd32(E1000_VMOLR(vfn));
2461 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2462 vmolr |= size | E1000_VMOLR_LPE;
2463 wr32(E1000_VMOLR(vfn), vmolr);
2464
2465 return 0;
2466}
2467
e1739522
AD		 2468/**
2469 * igb_rlpml_set - set maximum receive packet size
2470 * @adapter: board private structure
2471 *
2472 * Configure maximum receivable packet size.
2473 **/
2474static void igb_rlpml_set(struct igb_adapter *adapter)
2475{
2476 u32 max_frame_size = adapter->max_frame_size;
2477 struct e1000_hw *hw = &adapter->hw;
2478 u16 pf_id = adapter->vfs_allocated_count;
2479
2480 if (adapter->vlgrp)
2481 max_frame_size += VLAN_TAG_SIZE;
2482
2483 /* if vfs are enabled we set RLPML to the largest possible request
2484 * size and set the VMOLR RLPML to the size we need */
2485 if (pf_id) {
2486 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2487 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2488 }
2489
2490 wr32(E1000_RLPML, max_frame_size);
2491}
2492
8151d294
WM		 2493static inline void igb_set_vmolr(struct igb_adapter *adapter,
2494 int vfn, bool aupe)
7d5753f0
AD		 2495{
2496 struct e1000_hw *hw = &adapter->hw;
2497 u32 vmolr;
2498
2499 /*
2500 * This register exists only on 82576 and newer so if we are older then
2501 * we should exit and do nothing
2502 */
2503 if (hw->mac.type < e1000_82576)
2504 return;
2505
2506 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2507 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2508 if (aupe)
2509 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2510 else
2511 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2512
2513 /* clear all bits that might not be set */
2514 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2515
a99955fc 2516 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2517 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2518 /*
2519 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2520 * multicast packets
2521 */
2522 if (vfn <= adapter->vfs_allocated_count)
2523 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2524
2525 wr32(E1000_VMOLR(vfn), vmolr);
2526}
2527
85b430b4
AD		 2528/**
2529 * igb_configure_rx_ring - Configure a receive ring after Reset
2530 * @adapter: board private structure
2531 * @ring: receive ring to be configured
2532 *
2533 * Configure the Rx unit of the MAC after a reset.
2534 **/
d7ee5b3a
AD		 2535void igb_configure_rx_ring(struct igb_adapter *adapter,
2536 struct igb_ring *ring)
85b430b4
AD		 2537{
2538 struct e1000_hw *hw = &adapter->hw;
2539 u64 rdba = ring->dma;
2540 int reg_idx = ring->reg_idx;
952f72a8 2541 u32 srrctl, rxdctl;
85b430b4
AD		 2542
2543 /* disable the queue */
2544 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2545 wr32(E1000_RXDCTL(reg_idx),
2546 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2547
2548 /* Set DMA base address registers */
2549 wr32(E1000_RDBAL(reg_idx),
2550 rdba & 0x00000000ffffffffULL);
2551 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2552 wr32(E1000_RDLEN(reg_idx),
2553 ring->count * sizeof(union e1000_adv_rx_desc));
2554
2555 /* initialize head and tail */
fce99e34
AD		 2556 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2557 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2558 writel(0, ring->head);
2559 writel(0, ring->tail);
85b430b4 2560
952f72a8 2561 /* set descriptor configuration */
4c844851
AD		 2562 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2563 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2564 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2565#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2566 srrctl |= IGB_RXBUFFER_16384 >>
2567 E1000_SRRCTL_BSIZEPKT_SHIFT;
2568#else
2569 srrctl |= (PAGE_SIZE / 2) >>
2570 E1000_SRRCTL_BSIZEPKT_SHIFT;
2571#endif
2572 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2573 } else {
4c844851 2574 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2575 E1000_SRRCTL_BSIZEPKT_SHIFT;
2576 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2577 }
2578
2579 wr32(E1000_SRRCTL(reg_idx), srrctl);
2580
7d5753f0 2581 /* set filtering for VMDQ pools */
8151d294 2582 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 2583
85b430b4
AD		 2584 /* enable receive descriptor fetching */
2585 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2586 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2587 rxdctl &= 0xFFF00000;
2588 rxdctl |= IGB_RX_PTHRESH;
2589 rxdctl |= IGB_RX_HTHRESH << 8;
2590 rxdctl |= IGB_RX_WTHRESH << 16;
2591 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2592}
2593
9d5c8243
AK		 2594/**
2595 * igb_configure_rx - Configure receive Unit after Reset
2596 * @adapter: board private structure
2597 *
2598 * Configure the Rx unit of the MAC after a reset.
2599 **/
2600static void igb_configure_rx(struct igb_adapter *adapter)
2601{
9107584e 2602 int i;
9d5c8243 2603
68d480c4
AD		 2604 /* set UTA to appropriate mode */
2605 igb_set_uta(adapter);
2606
26ad9178
AD		 2607 /* set the correct pool for the PF default MAC address in entry 0 */
2608 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2609 adapter->vfs_allocated_count);
2610
06cf2666
AD		 2611 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2612 * the Base and Length of the Rx Descriptor Ring */
2613 for (i = 0; i < adapter->num_rx_queues; i++)
2614 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2615}
2616
2617/**
2618 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2619 * @tx_ring: Tx descriptor ring for a specific queue
2620 *
2621 * Free all transmit software resources
2622 **/
68fd9910 2623void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2624{
3b644cf6 2625 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2626
2627 vfree(tx_ring->buffer_info);
2628 tx_ring->buffer_info = NULL;
2629
439705e1
AD		 2630 /* if not set, then don't free */
2631 if (!tx_ring->desc)
2632 return;
2633
80785298
AD		 2634 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2635 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2636
2637 tx_ring->desc = NULL;
2638}
2639
2640/**
2641 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2642 * @adapter: board private structure
2643 *
2644 * Free all transmit software resources
2645 **/
2646static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2647{
2648 int i;
2649
2650 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2651 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2652}
2653
b1a436c3
AD		 2654void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
2655 struct igb_buffer *buffer_info)
9d5c8243 2656{
6366ad33
AD		 2657 if (buffer_info->dma) {
2658 if (buffer_info->mapped_as_page)
2659 pci_unmap_page(tx_ring->pdev,
2660 buffer_info->dma,
2661 buffer_info->length,
2662 PCI_DMA_TODEVICE);
2663 else
2664 pci_unmap_single(tx_ring->pdev,
2665 buffer_info->dma,
2666 buffer_info->length,
2667 PCI_DMA_TODEVICE);
2668 buffer_info->dma = 0;
2669 }
9d5c8243
AK		 2670 if (buffer_info->skb) {
2671 dev_kfree_skb_any(buffer_info->skb);
2672 buffer_info->skb = NULL;
2673 }
2674 buffer_info->time_stamp = 0;
6366ad33
AD		 2675 buffer_info->length = 0;
2676 buffer_info->next_to_watch = 0;
2677 buffer_info->mapped_as_page = false;
9d5c8243
AK		 2678}
2679
2680/**
2681 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2682 * @tx_ring: ring to be cleaned
2683 **/
3b644cf6 2684static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2685{
2686 struct igb_buffer *buffer_info;
2687 unsigned long size;
2688 unsigned int i;
2689
2690 if (!tx_ring->buffer_info)
2691 return;
2692 /* Free all the Tx ring sk_buffs */
2693
2694 for (i = 0; i < tx_ring->count; i++) {
2695 buffer_info = &tx_ring->buffer_info[i];
80785298 2696 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2697 }
2698
2699 size = sizeof(struct igb_buffer) * tx_ring->count;
2700 memset(tx_ring->buffer_info, 0, size);
2701
2702 /* Zero out the descriptor ring */
9d5c8243
AK		 2703 memset(tx_ring->desc, 0, tx_ring->size);
2704
2705 tx_ring->next_to_use = 0;
2706 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2707}
2708
2709/**
2710 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2711 * @adapter: board private structure
2712 **/
2713static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2714{
2715 int i;
2716
2717 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2718 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2719}
2720
2721/**
2722 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2723 * @rx_ring: ring to clean the resources from
2724 *
2725 * Free all receive software resources
2726 **/
68fd9910 2727void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2728{
3b644cf6 2729 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2730
2731 vfree(rx_ring->buffer_info);
2732 rx_ring->buffer_info = NULL;
2733
439705e1
AD		 2734 /* if not set, then don't free */
2735 if (!rx_ring->desc)
2736 return;
2737
80785298
AD		 2738 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2739 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2740
2741 rx_ring->desc = NULL;
2742}
2743
2744/**
2745 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2746 * @adapter: board private structure
2747 *
2748 * Free all receive software resources
2749 **/
2750static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2751{
2752 int i;
2753
2754 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2755 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2756}
2757
2758/**
2759 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2760 * @rx_ring: ring to free buffers from
2761 **/
3b644cf6 2762static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 2763{
2764 struct igb_buffer *buffer_info;
9d5c8243
AK		 2765 unsigned long size;
2766 unsigned int i;
2767
2768 if (!rx_ring->buffer_info)
2769 return;
439705e1 2770
9d5c8243
AK		 2771 /* Free all the Rx ring sk_buffs */
2772 for (i = 0; i < rx_ring->count; i++) {
2773 buffer_info = &rx_ring->buffer_info[i];
2774 if (buffer_info->dma) {
80785298
AD		 2775 pci_unmap_single(rx_ring->pdev,
2776 buffer_info->dma,
4c844851 2777 rx_ring->rx_buffer_len,
6ec43fe6 2778 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2779 buffer_info->dma = 0;
2780 }
2781
2782 if (buffer_info->skb) {
2783 dev_kfree_skb(buffer_info->skb);
2784 buffer_info->skb = NULL;
2785 }
6ec43fe6 2786 if (buffer_info->page_dma) {
80785298
AD		 2787 pci_unmap_page(rx_ring->pdev,
2788 buffer_info->page_dma,
6ec43fe6
AD		 2789 PAGE_SIZE / 2,
2790 PCI_DMA_FROMDEVICE);
2791 buffer_info->page_dma = 0;
2792 }
9d5c8243 2793 if (buffer_info->page) {
9d5c8243
AK		 2794 put_page(buffer_info->page);
2795 buffer_info->page = NULL;
bf36c1a0 2796 buffer_info->page_offset = 0;
9d5c8243
AK		 2797 }
2798 }
2799
9d5c8243
AK		 2800 size = sizeof(struct igb_buffer) * rx_ring->count;
2801 memset(rx_ring->buffer_info, 0, size);
2802
2803 /* Zero out the descriptor ring */
2804 memset(rx_ring->desc, 0, rx_ring->size);
2805
2806 rx_ring->next_to_clean = 0;
2807 rx_ring->next_to_use = 0;
9d5c8243
AK		 2808}
2809
2810/**
2811 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2812 * @adapter: board private structure
2813 **/
2814static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2815{
2816 int i;
2817
2818 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2819 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2820}
2821
2822/**
2823 * igb_set_mac - Change the Ethernet Address of the NIC
2824 * @netdev: network interface device structure
2825 * @p: pointer to an address structure
2826 *
2827 * Returns 0 on success, negative on failure
2828 **/
2829static int igb_set_mac(struct net_device *netdev, void *p)
2830{
2831 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2832 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2833 struct sockaddr *addr = p;
2834
2835 if (!is_valid_ether_addr(addr->sa_data))
2836 return -EADDRNOTAVAIL;
2837
2838 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2839 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2840
26ad9178
AD		 2841 /* set the correct pool for the new PF MAC address in entry 0 */
2842 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2843 adapter->vfs_allocated_count);
e1739522 2844
9d5c8243
AK		 2845 return 0;
2846}
2847
2848/**
68d480c4 2849 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2850 * @netdev: network interface device structure
2851 *
68d480c4
AD		 2852 * Writes multicast address list to the MTA hash table.
2853 * Returns: -ENOMEM on failure
2854 * 0 on no addresses written
2855 * X on writing X addresses to MTA
9d5c8243 2856 **/
68d480c4 2857static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2858{
2859 struct igb_adapter *adapter = netdev_priv(netdev);
2860 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2861 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2862 u8 *mta_list;
2863 u32 vmolr = 0;
9d5c8243
AK		 2864 int i;
2865
4cd24eaf 2866 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 2867 /* nothing to program, so clear mc list */
2868 igb_update_mc_addr_list(hw, NULL, 0);
2869 igb_restore_vf_multicasts(adapter);
2870 return 0;
2871 }
9d5c8243 2872
4cd24eaf 2873 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 2874 if (!mta_list)
2875 return -ENOMEM;
ff41f8dc 2876
68d480c4
AD		 2877 /* set vmolr receive overflow multicast bit */
2878 vmolr |= E1000_VMOLR_ROMPE;
2879
2880 /* The shared function expects a packed array of only addresses. */
2881 mc_ptr = netdev->mc_list;
2882
4cd24eaf 2883 for (i = 0; i < netdev_mc_count(netdev); i++) {
68d480c4
AD		 2884 if (!mc_ptr)
2885 break;
2886 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2887 mc_ptr = mc_ptr->next;
746b9f02 2888 }
68d480c4
AD		 2889 igb_update_mc_addr_list(hw, mta_list, i);
2890 kfree(mta_list);
2891
4cd24eaf 2892 return netdev_mc_count(netdev);
68d480c4
AD		 2893}
2894
2895/**
2896 * igb_write_uc_addr_list - write unicast addresses to RAR table
2897 * @netdev: network interface device structure
2898 *
2899 * Writes unicast address list to the RAR table.
2900 * Returns: -ENOMEM on failure/insufficient address space
2901 * 0 on no addresses written
2902 * X on writing X addresses to the RAR table
2903 **/
2904static int igb_write_uc_addr_list(struct net_device *netdev)
2905{
2906 struct igb_adapter *adapter = netdev_priv(netdev);
2907 struct e1000_hw *hw = &adapter->hw;
2908 unsigned int vfn = adapter->vfs_allocated_count;
2909 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2910 int count = 0;
2911
2912 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 2913 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 2914 return -ENOMEM;
9d5c8243 2915
32e7bfc4 2916 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 2917 struct netdev_hw_addr *ha;
32e7bfc4
JP		 2918
2919 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 2920 if (!rar_entries)
2921 break;
26ad9178
AD		 2922 igb_rar_set_qsel(adapter, ha->addr,
2923 rar_entries--,
68d480c4
AD		 2924 vfn);
2925 count++;
ff41f8dc
AD		 2926 }
2927 }
2928 /* write the addresses in reverse order to avoid write combining */
2929 for (; rar_entries > 0 ; rar_entries--) {
2930 wr32(E1000_RAH(rar_entries), 0);
2931 wr32(E1000_RAL(rar_entries), 0);
2932 }
2933 wrfl();
2934
68d480c4
AD		 2935 return count;
2936}
2937
2938/**
2939 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2940 * @netdev: network interface device structure
2941 *
2942 * The set_rx_mode entry point is called whenever the unicast or multicast
2943 * address lists or the network interface flags are updated. This routine is
2944 * responsible for configuring the hardware for proper unicast, multicast,
2945 * promiscuous mode, and all-multi behavior.
2946 **/
2947static void igb_set_rx_mode(struct net_device *netdev)
2948{
2949 struct igb_adapter *adapter = netdev_priv(netdev);
2950 struct e1000_hw *hw = &adapter->hw;
2951 unsigned int vfn = adapter->vfs_allocated_count;
2952 u32 rctl, vmolr = 0;
2953 int count;
2954
2955 /* Check for Promiscuous and All Multicast modes */
2956 rctl = rd32(E1000_RCTL);
2957
2958 /* clear the effected bits */
2959 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2960
2961 if (netdev->flags & IFF_PROMISC) {
2962 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2963 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2964 } else {
2965 if (netdev->flags & IFF_ALLMULTI) {
2966 rctl |= E1000_RCTL_MPE;
2967 vmolr |= E1000_VMOLR_MPME;
2968 } else {
2969 /*
2970 * Write addresses to the MTA, if the attempt fails
2971 * then we should just turn on promiscous mode so
2972 * that we can at least receive multicast traffic
2973 */
2974 count = igb_write_mc_addr_list(netdev);
2975 if (count < 0) {
2976 rctl |= E1000_RCTL_MPE;
2977 vmolr |= E1000_VMOLR_MPME;
2978 } else if (count) {
2979 vmolr |= E1000_VMOLR_ROMPE;
2980 }
2981 }
2982 /*
2983 * Write addresses to available RAR registers, if there is not
2984 * sufficient space to store all the addresses then enable
2985 * unicast promiscous mode
2986 */
2987 count = igb_write_uc_addr_list(netdev);
2988 if (count < 0) {
2989 rctl |= E1000_RCTL_UPE;
2990 vmolr |= E1000_VMOLR_ROPE;
2991 }
2992 rctl |= E1000_RCTL_VFE;
28fc06f5 2993 }
68d480c4 2994 wr32(E1000_RCTL, rctl);
28fc06f5 2995
68d480c4
AD		 2996 /*
2997 * In order to support SR-IOV and eventually VMDq it is necessary to set
2998 * the VMOLR to enable the appropriate modes. Without this workaround
2999 * we will have issues with VLAN tag stripping not being done for frames
3000 * that are only arriving because we are the default pool
3001 */
3002 if (hw->mac.type < e1000_82576)
28fc06f5 3003 return;
9d5c8243 3004
68d480c4
AD		 3005 vmolr |= rd32(E1000_VMOLR(vfn)) &
3006 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3007 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3008 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3009}
3010
3011/* Need to wait a few seconds after link up to get diagnostic information from
3012 * the phy */
3013static void igb_update_phy_info(unsigned long data)
3014{
3015 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3016 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3017}
3018
4d6b725e
AD		 3019/**
3020 * igb_has_link - check shared code for link and determine up/down
3021 * @adapter: pointer to driver private info
3022 **/
3023static bool igb_has_link(struct igb_adapter *adapter)
3024{
3025 struct e1000_hw *hw = &adapter->hw;
3026 bool link_active = false;
3027 s32 ret_val = 0;
3028
3029 /* get_link_status is set on LSC (link status) interrupt or
3030 * rx sequence error interrupt. get_link_status will stay
3031 * false until the e1000_check_for_link establishes link
3032 * for copper adapters ONLY
3033 */
3034 switch (hw->phy.media_type) {
3035 case e1000_media_type_copper:
3036 if (hw->mac.get_link_status) {
3037 ret_val = hw->mac.ops.check_for_link(hw);
3038 link_active = !hw->mac.get_link_status;
3039 } else {
3040 link_active = true;
3041 }
3042 break;
4d6b725e
AD		 3043 case e1000_media_type_internal_serdes:
3044 ret_val = hw->mac.ops.check_for_link(hw);
3045 link_active = hw->mac.serdes_has_link;
3046 break;
3047 default:
3048 case e1000_media_type_unknown:
3049 break;
3050 }
3051
3052 return link_active;
3053}
3054
9d5c8243
AK		 3055/**
3056 * igb_watchdog - Timer Call-back
3057 * @data: pointer to adapter cast into an unsigned long
3058 **/
3059static void igb_watchdog(unsigned long data)
3060{
3061 struct igb_adapter *adapter = (struct igb_adapter *)data;
3062 /* Do the rest outside of interrupt context */
3063 schedule_work(&adapter->watchdog_task);
3064}
3065
3066static void igb_watchdog_task(struct work_struct *work)
3067{
3068 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3069 struct igb_adapter,
3070 watchdog_task);
9d5c8243 3071 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3072 struct net_device *netdev = adapter->netdev;
9d5c8243 3073 u32 link;
7a6ea550 3074 int i;
9d5c8243 3075
4d6b725e 3076 link = igb_has_link(adapter);
9d5c8243
AK		 3077 if (link) {
3078 if (!netif_carrier_ok(netdev)) {
3079 u32 ctrl;
330a6d6a
AD		 3080 hw->mac.ops.get_speed_and_duplex(hw,
3081 &adapter->link_speed,
3082 &adapter->link_duplex);
9d5c8243
AK		 3083
3084 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3085 /* Links status message must follow this format */
3086 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3087 "Flow Control: %s\n",
559e9c49
AD		 3088 netdev->name,
3089 adapter->link_speed,
3090 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3091 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3092 ((ctrl & E1000_CTRL_TFCE) &&
3093 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3094 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3095 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243
AK		 3096
3097 /* tweak tx_queue_len according to speed/duplex and
3098 * adjust the timeout factor */
3099 netdev->tx_queue_len = adapter->tx_queue_len;
3100 adapter->tx_timeout_factor = 1;
3101 switch (adapter->link_speed) {
3102 case SPEED_10:
3103 netdev->tx_queue_len = 10;
3104 adapter->tx_timeout_factor = 14;
3105 break;
3106 case SPEED_100:
3107 netdev->tx_queue_len = 100;
3108 /* maybe add some timeout factor ? */
3109 break;
3110 }
3111
3112 netif_carrier_on(netdev);
9d5c8243 3113
4ae196df
AD		 3114 igb_ping_all_vfs(adapter);
3115
4b1a9877 3116 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3117 if (!test_bit(__IGB_DOWN, &adapter->state))
3118 mod_timer(&adapter->phy_info_timer,
3119 round_jiffies(jiffies + 2 * HZ));
3120 }
3121 } else {
3122 if (netif_carrier_ok(netdev)) {
3123 adapter->link_speed = 0;
3124 adapter->link_duplex = 0;
527d47c1
AD		 3125 /* Links status message must follow this format */
3126 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3127 netdev->name);
9d5c8243 3128 netif_carrier_off(netdev);
4b1a9877 3129
4ae196df
AD		 3130 igb_ping_all_vfs(adapter);
3131
4b1a9877 3132 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3133 if (!test_bit(__IGB_DOWN, &adapter->state))
3134 mod_timer(&adapter->phy_info_timer,
3135 round_jiffies(jiffies + 2 * HZ));
3136 }
3137 }
3138
9d5c8243 3139 igb_update_stats(adapter);
645a3abd 3140 igb_update_adaptive(hw);
9d5c8243 3141
dbabb065
AD		 3142 for (i = 0; i < adapter->num_tx_queues; i++) {
3143 struct igb_ring *tx_ring = &adapter->tx_ring[i];
3144 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3145 /* We've lost link, so the controller stops DMA,
3146 * but we've got queued Tx work that's never going
3147 * to get done, so reset controller to flush Tx.
3148 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3149 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3150 adapter->tx_timeout_count++;
3151 schedule_work(&adapter->reset_task);
3152 /* return immediately since reset is imminent */
3153 return;
3154 }
9d5c8243 3155 }
9d5c8243 3156
dbabb065
AD		 3157 /* Force detection of hung controller every watchdog period */
3158 tx_ring->detect_tx_hung = true;
3159 }
f7ba205e 3160
9d5c8243 3161 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3162 if (adapter->msix_entries) {
047e0030
AD		 3163 u32 eics = 0;
3164 for (i = 0; i < adapter->num_q_vectors; i++) {
3165 struct igb_q_vector *q_vector = adapter->q_vector[i];
3166 eics |= q_vector->eims_value;
3167 }
7a6ea550
AD		 3168 wr32(E1000_EICS, eics);
3169 } else {
3170 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3171 }
9d5c8243 3172
9d5c8243
AK		 3173 /* Reset the timer */
3174 if (!test_bit(__IGB_DOWN, &adapter->state))
3175 mod_timer(&adapter->watchdog_timer,
3176 round_jiffies(jiffies + 2 * HZ));
3177}
3178
3179enum latency_range {
3180 lowest_latency = 0,
3181 low_latency = 1,
3182 bulk_latency = 2,
3183 latency_invalid = 255
3184};
3185
6eb5a7f1
AD		 3186/**
3187 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3188 *
3189 * Stores a new ITR value based on strictly on packet size. This
3190 * algorithm is less sophisticated than that used in igb_update_itr,
3191 * due to the difficulty of synchronizing statistics across multiple
3192 * receive rings. The divisors and thresholds used by this fuction
3193 * were determined based on theoretical maximum wire speed and testing
3194 * data, in order to minimize response time while increasing bulk
3195 * throughput.
3196 * This functionality is controlled by the InterruptThrottleRate module
3197 * parameter (see igb_param.c)
3198 * NOTE: This function is called only when operating in a multiqueue
3199 * receive environment.
047e0030 3200 * @q_vector: pointer to q_vector
6eb5a7f1 3201 **/
047e0030 3202static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3203{
047e0030 3204 int new_val = q_vector->itr_val;
6eb5a7f1 3205 int avg_wire_size = 0;
047e0030 3206 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3207
6eb5a7f1
AD		 3208 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3209 * ints/sec - ITR timer value of 120 ticks.
3210 */
3211 if (adapter->link_speed != SPEED_1000) {
047e0030 3212 new_val = 976;
6eb5a7f1 3213 goto set_itr_val;
9d5c8243 3214 }
047e0030
AD		 3215
3216 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3217 struct igb_ring *ring = q_vector->rx_ring;
3218 avg_wire_size = ring->total_bytes / ring->total_packets;
3219 }
3220
3221 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3222 struct igb_ring *ring = q_vector->tx_ring;
3223 avg_wire_size = max_t(u32, avg_wire_size,
3224 (ring->total_bytes /
3225 ring->total_packets));
3226 }
3227
3228 /* if avg_wire_size isn't set no work was done */
3229 if (!avg_wire_size)
3230 goto clear_counts;
9d5c8243 3231
6eb5a7f1
AD		 3232 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3233 avg_wire_size += 24;
3234
3235 /* Don't starve jumbo frames */
3236 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3237
6eb5a7f1
AD		 3238 /* Give a little boost to mid-size frames */
3239 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3240 new_val = avg_wire_size / 3;
3241 else
3242 new_val = avg_wire_size / 2;
9d5c8243 3243
6eb5a7f1 3244set_itr_val:
047e0030
AD		 3245 if (new_val != q_vector->itr_val) {
3246 q_vector->itr_val = new_val;
3247 q_vector->set_itr = 1;
9d5c8243 3248 }
6eb5a7f1 3249clear_counts:
047e0030
AD		 3250 if (q_vector->rx_ring) {
3251 q_vector->rx_ring->total_bytes = 0;
3252 q_vector->rx_ring->total_packets = 0;
3253 }
3254 if (q_vector->tx_ring) {
3255 q_vector->tx_ring->total_bytes = 0;
3256 q_vector->tx_ring->total_packets = 0;
3257 }
9d5c8243
AK		 3258}
3259
3260/**
3261 * igb_update_itr - update the dynamic ITR value based on statistics
3262 * Stores a new ITR value based on packets and byte
3263 * counts during the last interrupt. The advantage of per interrupt
3264 * computation is faster updates and more accurate ITR for the current
3265 * traffic pattern. Constants in this function were computed
3266 * based on theoretical maximum wire speed and thresholds were set based
3267 * on testing data as well as attempting to minimize response time
3268 * while increasing bulk throughput.
3269 * this functionality is controlled by the InterruptThrottleRate module
3270 * parameter (see igb_param.c)
3271 * NOTE: These calculations are only valid when operating in a single-
3272 * queue environment.
3273 * @adapter: pointer to adapter
047e0030 3274 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3275 * @packets: the number of packets during this measurement interval
3276 * @bytes: the number of bytes during this measurement interval
3277 **/
3278static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3279 int packets, int bytes)
3280{
3281 unsigned int retval = itr_setting;
3282
3283 if (packets == 0)
3284 goto update_itr_done;
3285
3286 switch (itr_setting) {
3287 case lowest_latency:
3288 /* handle TSO and jumbo frames */
3289 if (bytes/packets > 8000)
3290 retval = bulk_latency;
3291 else if ((packets < 5) && (bytes > 512))
3292 retval = low_latency;
3293 break;
3294 case low_latency: /* 50 usec aka 20000 ints/s */
3295 if (bytes > 10000) {
3296 /* this if handles the TSO accounting */
3297 if (bytes/packets > 8000) {
3298 retval = bulk_latency;
3299 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3300 retval = bulk_latency;
3301 } else if ((packets > 35)) {
3302 retval = lowest_latency;
3303 }
3304 } else if (bytes/packets > 2000) {
3305 retval = bulk_latency;
3306 } else if (packets <= 2 && bytes < 512) {
3307 retval = lowest_latency;
3308 }
3309 break;
3310 case bulk_latency: /* 250 usec aka 4000 ints/s */
3311 if (bytes > 25000) {
3312 if (packets > 35)
3313 retval = low_latency;
1e5c3d21 3314 } else if (bytes < 1500) {
9d5c8243
AK		 3315 retval = low_latency;
3316 }
3317 break;
3318 }
3319
3320update_itr_done:
3321 return retval;
3322}
3323
6eb5a7f1 3324static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3325{
047e0030 3326 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3327 u16 current_itr;
047e0030 3328 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3329
3330 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3331 if (adapter->link_speed != SPEED_1000) {
3332 current_itr = 0;
3333 new_itr = 4000;
3334 goto set_itr_now;
3335 }
3336
3337 adapter->rx_itr = igb_update_itr(adapter,
3338 adapter->rx_itr,
3339 adapter->rx_ring->total_packets,
3340 adapter->rx_ring->total_bytes);
9d5c8243 3341
047e0030
AD		 3342 adapter->tx_itr = igb_update_itr(adapter,
3343 adapter->tx_itr,
3344 adapter->tx_ring->total_packets,
3345 adapter->tx_ring->total_bytes);
3346 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3347
6eb5a7f1 3348 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3349 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3350 current_itr = low_latency;
3351
9d5c8243
AK		 3352 switch (current_itr) {
3353 /* counts and packets in update_itr are dependent on these numbers */
3354 case lowest_latency:
78b1f607 3355 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3356 break;
3357 case low_latency:
78b1f607 3358 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3359 break;
3360 case bulk_latency:
78b1f607 3361 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3362 break;
3363 default:
3364 break;
3365 }
3366
3367set_itr_now:
6eb5a7f1
AD		 3368 adapter->rx_ring->total_bytes = 0;
3369 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3370 adapter->tx_ring->total_bytes = 0;
3371 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3372
047e0030 3373 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3374 /* this attempts to bias the interrupt rate towards Bulk
3375 * by adding intermediate steps when interrupt rate is
3376 * increasing */
047e0030
AD		 3377 new_itr = new_itr > q_vector->itr_val ?
3378 max((new_itr * q_vector->itr_val) /
3379 (new_itr + (q_vector->itr_val >> 2)),
3380 new_itr) :
9d5c8243
AK		 3381 new_itr;
3382 /* Don't write the value here; it resets the adapter's
3383 * internal timer, and causes us to delay far longer than
3384 * we should between interrupts. Instead, we write the ITR
3385 * value at the beginning of the next interrupt so the timing
3386 * ends up being correct.
3387 */
047e0030
AD		 3388 q_vector->itr_val = new_itr;
3389 q_vector->set_itr = 1;
9d5c8243
AK		 3390 }
3391
3392 return;
3393}
3394
9d5c8243
AK		 3395#define IGB_TX_FLAGS_CSUM 0x00000001
3396#define IGB_TX_FLAGS_VLAN 0x00000002
3397#define IGB_TX_FLAGS_TSO 0x00000004
3398#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3399#define IGB_TX_FLAGS_TSTAMP 0x00000010
3400#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3401#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3402
85ad76b2 3403static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3404 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3405{
3406 struct e1000_adv_tx_context_desc *context_desc;
3407 unsigned int i;
3408 int err;
3409 struct igb_buffer *buffer_info;
3410 u32 info = 0, tu_cmd = 0;
3411 u32 mss_l4len_idx, l4len;
3412 *hdr_len = 0;
3413
3414 if (skb_header_cloned(skb)) {
3415 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3416 if (err)
3417 return err;
3418 }
3419
3420 l4len = tcp_hdrlen(skb);
3421 *hdr_len += l4len;
3422
3423 if (skb->protocol == htons(ETH_P_IP)) {
3424 struct iphdr *iph = ip_hdr(skb);
3425 iph->tot_len = 0;
3426 iph->check = 0;
3427 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3428 iph->daddr, 0,
3429 IPPROTO_TCP,
3430 0);
8e1e8a47 3431 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3432 ipv6_hdr(skb)->payload_len = 0;
3433 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3434 &ipv6_hdr(skb)->daddr,
3435 0, IPPROTO_TCP, 0);
3436 }
3437
3438 i = tx_ring->next_to_use;
3439
3440 buffer_info = &tx_ring->buffer_info[i];
3441 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3442 /* VLAN MACLEN IPLEN */
3443 if (tx_flags & IGB_TX_FLAGS_VLAN)
3444 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3445 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3446 *hdr_len += skb_network_offset(skb);
3447 info |= skb_network_header_len(skb);
3448 *hdr_len += skb_network_header_len(skb);
3449 context_desc->vlan_macip_lens = cpu_to_le32(info);
3450
3451 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3452 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3453
3454 if (skb->protocol == htons(ETH_P_IP))
3455 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3456 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3457
3458 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3459
3460 /* MSS L4LEN IDX */
3461 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3462 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3463
73cd78f1 3464 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3465 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3466 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3467
3468 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3469 context_desc->seqnum_seed = 0;
3470
3471 buffer_info->time_stamp = jiffies;
0e014cb1 3472 buffer_info->next_to_watch = i;
9d5c8243
AK		 3473 buffer_info->dma = 0;
3474 i++;
3475 if (i == tx_ring->count)
3476 i = 0;
3477
3478 tx_ring->next_to_use = i;
3479
3480 return true;
3481}
3482
85ad76b2
AD		 3483static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3484 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3485{
3486 struct e1000_adv_tx_context_desc *context_desc;
80785298 3487 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3488 struct igb_buffer *buffer_info;
3489 u32 info = 0, tu_cmd = 0;
80785298 3490 unsigned int i;
9d5c8243
AK		 3491
3492 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3493 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3494 i = tx_ring->next_to_use;
3495 buffer_info = &tx_ring->buffer_info[i];
3496 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3497
3498 if (tx_flags & IGB_TX_FLAGS_VLAN)
3499 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3500
9d5c8243
AK		 3501 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3502 if (skb->ip_summed == CHECKSUM_PARTIAL)
3503 info |= skb_network_header_len(skb);
3504
3505 context_desc->vlan_macip_lens = cpu_to_le32(info);
3506
3507 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3508
3509 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3510 __be16 protocol;
3511
3512 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3513 const struct vlan_ethhdr *vhdr =
3514 (const struct vlan_ethhdr*)skb->data;
3515
3516 protocol = vhdr->h_vlan_encapsulated_proto;
3517 } else {
3518 protocol = skb->protocol;
3519 }
3520
3521 switch (protocol) {
09640e63 3522 case cpu_to_be16(ETH_P_IP):
9d5c8243 3523 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3524 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3525 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3526 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3527 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3528 break;
09640e63 3529 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3530 /* XXX what about other V6 headers?? */
3531 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3532 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3533 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3534 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3535 break;
3536 default:
3537 if (unlikely(net_ratelimit()))
80785298 3538 dev_warn(&pdev->dev,
44b0cda3
MW		 3539 "partial checksum but proto=%x!\n",
3540 skb->protocol);
3541 break;
3542 }
9d5c8243
AK		 3543 }
3544
3545 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3546 context_desc->seqnum_seed = 0;
85ad76b2 3547 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3548 context_desc->mss_l4len_idx =
85ad76b2 3549 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3550
3551 buffer_info->time_stamp = jiffies;
0e014cb1 3552 buffer_info->next_to_watch = i;
9d5c8243
AK		 3553 buffer_info->dma = 0;
3554
3555 i++;
3556 if (i == tx_ring->count)
3557 i = 0;
3558 tx_ring->next_to_use = i;
3559
3560 return true;
3561 }
9d5c8243
AK		 3562 return false;
3563}
3564
3565#define IGB_MAX_TXD_PWR 16
3566#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3567
80785298 3568static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3569 unsigned int first)
9d5c8243
AK		 3570{
3571 struct igb_buffer *buffer_info;
80785298 3572 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3573 unsigned int len = skb_headlen(skb);
3574 unsigned int count = 0, i;
3575 unsigned int f;
3576
3577 i = tx_ring->next_to_use;
3578
3579 buffer_info = &tx_ring->buffer_info[i];
3580 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3581 buffer_info->length = len;
3582 /* set time_stamp *before* dma to help avoid a possible race */
3583 buffer_info->time_stamp = jiffies;
0e014cb1 3584 buffer_info->next_to_watch = i;
6366ad33
AD		 3585 buffer_info->dma = pci_map_single(pdev, skb->data, len,
3586 PCI_DMA_TODEVICE);
3587 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3588 goto dma_error;
9d5c8243
AK		 3589
3590 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3591 struct skb_frag_struct *frag;
3592
8581145f 3593 count++;
65689fef
AD		 3594 i++;
3595 if (i == tx_ring->count)
3596 i = 0;
3597
9d5c8243
AK		 3598 frag = &skb_shinfo(skb)->frags[f];
3599 len = frag->size;
3600
3601 buffer_info = &tx_ring->buffer_info[i];
3602 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3603 buffer_info->length = len;
3604 buffer_info->time_stamp = jiffies;
0e014cb1 3605 buffer_info->next_to_watch = i;
6366ad33
AD		 3606 buffer_info->mapped_as_page = true;
3607 buffer_info->dma = pci_map_page(pdev,
3608 frag->page,
3609 frag->page_offset,
3610 len,
3611 PCI_DMA_TODEVICE);
3612 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3613 goto dma_error;
3614
9d5c8243
AK		 3615 }
3616
9d5c8243 3617 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3618 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3619
cdfd01fc 3620 return ++count;
6366ad33
AD		 3621
3622dma_error:
3623 dev_err(&pdev->dev, "TX DMA map failed\n");
3624
3625 /* clear timestamp and dma mappings for failed buffer_info mapping */
3626 buffer_info->dma = 0;
3627 buffer_info->time_stamp = 0;
3628 buffer_info->length = 0;
3629 buffer_info->next_to_watch = 0;
3630 buffer_info->mapped_as_page = false;
3631 count--;
3632
3633 /* clear timestamp and dma mappings for remaining portion of packet */
3634 while (count >= 0) {
3635 count--;
3636 i--;
3637 if (i < 0)
3638 i += tx_ring->count;
3639 buffer_info = &tx_ring->buffer_info[i];
3640 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3641 }
3642
3643 return 0;
9d5c8243
AK		 3644}
3645
85ad76b2 3646static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3647 int tx_flags, int count, u32 paylen,
3648 u8 hdr_len)
3649{
cdfd01fc 3650 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 3651 struct igb_buffer *buffer_info;
3652 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 3653 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 3654
3655 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3656 E1000_ADVTXD_DCMD_DEXT);
3657
3658 if (tx_flags & IGB_TX_FLAGS_VLAN)
3659 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3660
33af6bcc
PO		 3661 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3662 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3663
9d5c8243
AK		 3664 if (tx_flags & IGB_TX_FLAGS_TSO) {
3665 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3666
3667 /* insert tcp checksum */
3668 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3669
3670 /* insert ip checksum */
3671 if (tx_flags & IGB_TX_FLAGS_IPV4)
3672 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3673
3674 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3675 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3676 }
3677
85ad76b2
AD		 3678 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3679 (tx_flags & (IGB_TX_FLAGS_CSUM |
3680 IGB_TX_FLAGS_TSO |
7dfc16fa 3681 IGB_TX_FLAGS_VLAN)))
85ad76b2 3682 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3683
3684 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3685
cdfd01fc 3686 do {
9d5c8243
AK		 3687 buffer_info = &tx_ring->buffer_info[i];
3688 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3689 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3690 tx_desc->read.cmd_type_len =
3691 cpu_to_le32(cmd_type_len | buffer_info->length);
3692 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 3693 count--;
9d5c8243
AK		 3694 i++;
3695 if (i == tx_ring->count)
3696 i = 0;
cdfd01fc 3697 } while (count > 0);
9d5c8243 3698
85ad76b2 3699 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 3700 /* Force memory writes to complete before letting h/w
3701 * know there are new descriptors to fetch. (Only
3702 * applicable for weak-ordered memory model archs,
3703 * such as IA-64). */
3704 wmb();
3705
3706 tx_ring->next_to_use = i;
fce99e34 3707 writel(i, tx_ring->tail);
9d5c8243
AK		 3708 /* we need this if more than one processor can write to our tail
3709 * at a time, it syncronizes IO on IA64/Altix systems */
3710 mmiowb();
3711}
3712
e694e964 3713static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3714{
e694e964
AD		 3715 struct net_device *netdev = tx_ring->netdev;
3716
661086df 3717 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3718
9d5c8243
AK		 3719 /* Herbert's original patch had:
3720 * smp_mb__after_netif_stop_queue();
3721 * but since that doesn't exist yet, just open code it. */
3722 smp_mb();
3723
3724 /* We need to check again in a case another CPU has just
3725 * made room available. */
c493ea45 3726 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3727 return -EBUSY;
3728
3729 /* A reprieve! */
661086df 3730 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 3731 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 3732 return 0;
3733}
3734
e694e964 3735static int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3736{
c493ea45 3737 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 3738 return 0;
e694e964 3739 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 3740}
3741
b1a436c3
AD		 3742netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3743 struct igb_ring *tx_ring)
9d5c8243 3744{
e694e964 3745 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
0e014cb1 3746 unsigned int first;
9d5c8243 3747 unsigned int tx_flags = 0;
9d5c8243 3748 u8 hdr_len = 0;
cdfd01fc 3749 int tso = 0, count;
c5b9bd5e 3750 union skb_shared_tx *shtx = skb_tx(skb);
9d5c8243 3751
9d5c8243
AK		 3752 /* need: 1 descriptor per page,
3753 * + 2 desc gap to keep tail from touching head,
3754 * + 1 desc for skb->data,
3755 * + 1 desc for context descriptor,
3756 * otherwise try next time */
e694e964 3757 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 3758 /* this is a hard error */
9d5c8243
AK		 3759 return NETDEV_TX_BUSY;
3760 }
33af6bcc 3761
33af6bcc
PO		 3762 if (unlikely(shtx->hardware)) {
3763 shtx->in_progress = 1;
3764 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3765 }
9d5c8243 3766
cdfd01fc 3767 if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
9d5c8243
AK		 3768 tx_flags |= IGB_TX_FLAGS_VLAN;
3769 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3770 }
3771
661086df
PWJ		 3772 if (skb->protocol == htons(ETH_P_IP))
3773 tx_flags |= IGB_TX_FLAGS_IPV4;
3774
0e014cb1 3775 first = tx_ring->next_to_use;
85ad76b2
AD		 3776 if (skb_is_gso(skb)) {
3777 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 3778
85ad76b2
AD		 3779 if (tso < 0) {
3780 dev_kfree_skb_any(skb);
3781 return NETDEV_TX_OK;
3782 }
9d5c8243
AK		 3783 }
3784
3785 if (tso)
3786 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 3787 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 3788 (skb->ip_summed == CHECKSUM_PARTIAL))
3789 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3790
65689fef 3791 /*
cdfd01fc 3792 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 3793 * has occured and we need to rewind the descriptor queue
3794 */
80785298 3795 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 3796 if (!count) {
65689fef
AD		 3797 dev_kfree_skb_any(skb);
3798 tx_ring->buffer_info[first].time_stamp = 0;
3799 tx_ring->next_to_use = first;
85ad76b2 3800 return NETDEV_TX_OK;
65689fef 3801 }
9d5c8243 3802
85ad76b2
AD		 3803 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3804
3805 /* Make sure there is space in the ring for the next send. */
e694e964 3806 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 3807
9d5c8243
AK		 3808 return NETDEV_TX_OK;
3809}
3810
3b29a56d
SH		 3811static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3812 struct net_device *netdev)
9d5c8243
AK		 3813{
3814 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 3815 struct igb_ring *tx_ring;
661086df 3816 int r_idx = 0;
b1a436c3
AD		 3817
3818 if (test_bit(__IGB_DOWN, &adapter->state)) {
3819 dev_kfree_skb_any(skb);
3820 return NETDEV_TX_OK;
3821 }
3822
3823 if (skb->len <= 0) {
3824 dev_kfree_skb_any(skb);
3825 return NETDEV_TX_OK;
3826 }
3827
1bfaf07b 3828 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3829 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3830
3831 /* This goes back to the question of how to logically map a tx queue
3832 * to a flow. Right now, performance is impacted slightly negatively
3833 * if using multiple tx queues. If the stack breaks away from a
3834 * single qdisc implementation, we can look at this again. */
e694e964 3835 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 3836}
3837
3838/**
3839 * igb_tx_timeout - Respond to a Tx Hang
3840 * @netdev: network interface device structure
3841 **/
3842static void igb_tx_timeout(struct net_device *netdev)
3843{
3844 struct igb_adapter *adapter = netdev_priv(netdev);
3845 struct e1000_hw *hw = &adapter->hw;
3846
3847 /* Do the reset outside of interrupt context */
3848 adapter->tx_timeout_count++;
f7ba205e 3849
55cac248
AD		 3850 if (hw->mac.type == e1000_82580)
3851 hw->dev_spec._82575.global_device_reset = true;
3852
9d5c8243 3853 schedule_work(&adapter->reset_task);
265de409
AD		 3854 wr32(E1000_EICS,
3855 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3856}
3857
3858static void igb_reset_task(struct work_struct *work)
3859{
3860 struct igb_adapter *adapter;
3861 adapter = container_of(work, struct igb_adapter, reset_task);
3862
3863 igb_reinit_locked(adapter);
3864}
3865
3866/**
3867 * igb_get_stats - Get System Network Statistics
3868 * @netdev: network interface device structure
3869 *
3870 * Returns the address of the device statistics structure.
3871 * The statistics are actually updated from the timer callback.
3872 **/
73cd78f1 3873static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3874{
9d5c8243 3875 /* only return the current stats */
8d24e933 3876 return &netdev->stats;
9d5c8243
AK		 3877}
3878
3879/**
3880 * igb_change_mtu - Change the Maximum Transfer Unit
3881 * @netdev: network interface device structure
3882 * @new_mtu: new value for maximum frame size
3883 *
3884 * Returns 0 on success, negative on failure
3885 **/
3886static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3887{
3888 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 3889 struct pci_dev *pdev = adapter->pdev;
9d5c8243 3890 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 3891 u32 rx_buffer_len, i;
9d5c8243 3892
c809d227 3893 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 3894 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 3895 return -EINVAL;
3896 }
3897
9d5c8243 3898 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 3899 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 3900 return -EINVAL;
3901 }
3902
3903 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3904 msleep(1);
73cd78f1 3905
9d5c8243
AK		 3906 /* igb_down has a dependency on max_frame_size */
3907 adapter->max_frame_size = max_frame;
559e9c49 3908
9d5c8243
AK		 3909 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3910 * means we reserve 2 more, this pushes us to allocate from the next
3911 * larger slab size.
3912 * i.e. RXBUFFER_2048 --> size-4096 slab
3913 */
3914
7d95b717 3915 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 3916 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3917 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 3918 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 3919 else
4c844851
AD		 3920 rx_buffer_len = IGB_RXBUFFER_128;
3921
3922 if (netif_running(netdev))
3923 igb_down(adapter);
9d5c8243 3924
090b1795 3925 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 3926 netdev->mtu, new_mtu);
3927 netdev->mtu = new_mtu;
3928
4c844851
AD		 3929 for (i = 0; i < adapter->num_rx_queues; i++)
3930 adapter->rx_ring[i].rx_buffer_len = rx_buffer_len;
3931
9d5c8243
AK		 3932 if (netif_running(netdev))
3933 igb_up(adapter);
3934 else
3935 igb_reset(adapter);
3936
3937 clear_bit(__IGB_RESETTING, &adapter->state);
3938
3939 return 0;
3940}
3941
3942/**
3943 * igb_update_stats - Update the board statistics counters
3944 * @adapter: board private structure
3945 **/
3946
3947void igb_update_stats(struct igb_adapter *adapter)
3948{
128e45eb 3949 struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
9d5c8243
AK		 3950 struct e1000_hw *hw = &adapter->hw;
3951 struct pci_dev *pdev = adapter->pdev;
3f9c0164 3952 u32 rnbc;
9d5c8243 3953 u16 phy_tmp;
3f9c0164
AD		 3954 int i;
3955 u64 bytes, packets;
9d5c8243
AK		 3956
3957#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3958
3959 /*
3960 * Prevent stats update while adapter is being reset, or if the pci
3961 * connection is down.
3962 */
3963 if (adapter->link_speed == 0)
3964 return;
3965 if (pci_channel_offline(pdev))
3966 return;
3967
3f9c0164
AD		 3968 bytes = 0;
3969 packets = 0;
3970 for (i = 0; i < adapter->num_rx_queues; i++) {
3971 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3972 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
128e45eb 3973 net_stats->rx_fifo_errors += rqdpc_tmp;
3f9c0164
AD		 3974 bytes += adapter->rx_ring[i].rx_stats.bytes;
3975 packets += adapter->rx_ring[i].rx_stats.packets;
3976 }
3977
128e45eb
AD		 3978 net_stats->rx_bytes = bytes;
3979 net_stats->rx_packets = packets;
3f9c0164
AD		 3980
3981 bytes = 0;
3982 packets = 0;
3983 for (i = 0; i < adapter->num_tx_queues; i++) {
3984 bytes += adapter->tx_ring[i].tx_stats.bytes;
3985 packets += adapter->tx_ring[i].tx_stats.packets;
3986 }
128e45eb
AD		 3987 net_stats->tx_bytes = bytes;
3988 net_stats->tx_packets = packets;
3f9c0164
AD		 3989
3990 /* read stats registers */
9d5c8243
AK		 3991 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3992 adapter->stats.gprc += rd32(E1000_GPRC);
3993 adapter->stats.gorc += rd32(E1000_GORCL);
3994 rd32(E1000_GORCH); /* clear GORCL */
3995 adapter->stats.bprc += rd32(E1000_BPRC);
3996 adapter->stats.mprc += rd32(E1000_MPRC);
3997 adapter->stats.roc += rd32(E1000_ROC);
3998
3999 adapter->stats.prc64 += rd32(E1000_PRC64);
4000 adapter->stats.prc127 += rd32(E1000_PRC127);
4001 adapter->stats.prc255 += rd32(E1000_PRC255);
4002 adapter->stats.prc511 += rd32(E1000_PRC511);
4003 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4004 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4005 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4006 adapter->stats.sec += rd32(E1000_SEC);
4007
4008 adapter->stats.mpc += rd32(E1000_MPC);
4009 adapter->stats.scc += rd32(E1000_SCC);
4010 adapter->stats.ecol += rd32(E1000_ECOL);
4011 adapter->stats.mcc += rd32(E1000_MCC);
4012 adapter->stats.latecol += rd32(E1000_LATECOL);
4013 adapter->stats.dc += rd32(E1000_DC);
4014 adapter->stats.rlec += rd32(E1000_RLEC);
4015 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4016 adapter->stats.xontxc += rd32(E1000_XONTXC);
4017 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4018 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4019 adapter->stats.fcruc += rd32(E1000_FCRUC);
4020 adapter->stats.gptc += rd32(E1000_GPTC);
4021 adapter->stats.gotc += rd32(E1000_GOTCL);
4022 rd32(E1000_GOTCH); /* clear GOTCL */
3f9c0164
AD		 4023 rnbc = rd32(E1000_RNBC);
4024 adapter->stats.rnbc += rnbc;
128e45eb 4025 net_stats->rx_fifo_errors += rnbc;
9d5c8243
AK		 4026 adapter->stats.ruc += rd32(E1000_RUC);
4027 adapter->stats.rfc += rd32(E1000_RFC);
4028 adapter->stats.rjc += rd32(E1000_RJC);
4029 adapter->stats.tor += rd32(E1000_TORH);
4030 adapter->stats.tot += rd32(E1000_TOTH);
4031 adapter->stats.tpr += rd32(E1000_TPR);
4032
4033 adapter->stats.ptc64 += rd32(E1000_PTC64);
4034 adapter->stats.ptc127 += rd32(E1000_PTC127);
4035 adapter->stats.ptc255 += rd32(E1000_PTC255);
4036 adapter->stats.ptc511 += rd32(E1000_PTC511);
4037 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4038 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4039
4040 adapter->stats.mptc += rd32(E1000_MPTC);
4041 adapter->stats.bptc += rd32(E1000_BPTC);
4042
4043 /* used for adaptive IFS */
9d5c8243
AK		 4044 hw->mac.tx_packet_delta = rd32(E1000_TPT);
4045 adapter->stats.tpt += hw->mac.tx_packet_delta;
4046 hw->mac.collision_delta = rd32(E1000_COLC);
4047 adapter->stats.colc += hw->mac.collision_delta;
4048
4049 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4050 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4051 adapter->stats.tncrs += rd32(E1000_TNCRS);
4052 adapter->stats.tsctc += rd32(E1000_TSCTC);
4053 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4054
4055 adapter->stats.iac += rd32(E1000_IAC);
4056 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4057 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4058 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4059 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4060 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4061 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4062 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4063 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4064
4065 /* Fill out the OS statistics structure */
128e45eb
AD		 4066 net_stats->multicast = adapter->stats.mprc;
4067 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4068
4069 /* Rx Errors */
4070
4071 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4072 * our own version based on RUC and ROC */
128e45eb 4073 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4074 adapter->stats.crcerrs + adapter->stats.algnerrc +
4075 adapter->stats.ruc + adapter->stats.roc +
4076 adapter->stats.cexterr;
128e45eb
AD		 4077 net_stats->rx_length_errors = adapter->stats.ruc +
4078 adapter->stats.roc;
4079 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4080 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4081 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4082
4083 /* Tx Errors */
128e45eb
AD		 4084 net_stats->tx_errors = adapter->stats.ecol +
4085 adapter->stats.latecol;
4086 net_stats->tx_aborted_errors = adapter->stats.ecol;
4087 net_stats->tx_window_errors = adapter->stats.latecol;
4088 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4089
4090 /* Tx Dropped needs to be maintained elsewhere */
4091
4092 /* Phy Stats */
4093 if (hw->phy.media_type == e1000_media_type_copper) {
4094 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4095 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4096 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4097 adapter->phy_stats.idle_errors += phy_tmp;
4098 }
4099 }
4100
4101 /* Management Stats */
4102 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4103 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4104 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4105}
4106
9d5c8243
AK		 4107static irqreturn_t igb_msix_other(int irq, void *data)
4108{
047e0030 4109 struct igb_adapter *adapter = data;
9d5c8243 4110 struct e1000_hw *hw = &adapter->hw;
844290e5 4111 u32 icr = rd32(E1000_ICR);
844290e5 4112 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4113
7f081d40
AD		 4114 if (icr & E1000_ICR_DRSTA)
4115 schedule_work(&adapter->reset_task);
4116
047e0030 4117 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4118 /* HW is reporting DMA is out of sync */
4119 adapter->stats.doosync++;
4120 }
eebbbdba 4121
4ae196df
AD		 4122 /* Check for a mailbox event */
4123 if (icr & E1000_ICR_VMMB)
4124 igb_msg_task(adapter);
4125
4126 if (icr & E1000_ICR_LSC) {
4127 hw->mac.get_link_status = 1;
4128 /* guard against interrupt when we're going down */
4129 if (!test_bit(__IGB_DOWN, &adapter->state))
4130 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4131 }
4132
25568a53
AD		 4133 if (adapter->vfs_allocated_count)
4134 wr32(E1000_IMS, E1000_IMS_LSC |
4135 E1000_IMS_VMMB |
4136 E1000_IMS_DOUTSYNC);
4137 else
4138 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4139 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4140
4141 return IRQ_HANDLED;
4142}
4143
047e0030 4144static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4145{
26b39276 4146 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4147 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4148
047e0030
AD		 4149 if (!q_vector->set_itr)
4150 return;
73cd78f1 4151
047e0030
AD		 4152 if (!itr_val)
4153 itr_val = 0x4;
661086df 4154
26b39276
AD		 4155 if (adapter->hw.mac.type == e1000_82575)
4156 itr_val |= itr_val << 16;
661086df 4157 else
047e0030 4158 itr_val |= 0x8000000;
661086df 4159
047e0030
AD		 4160 writel(itr_val, q_vector->itr_register);
4161 q_vector->set_itr = 0;
6eb5a7f1
AD		 4162}
4163
047e0030 4164static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4165{
047e0030 4166 struct igb_q_vector *q_vector = data;
9d5c8243 4167
047e0030
AD		 4168 /* Write the ITR value calculated from the previous interrupt. */
4169 igb_write_itr(q_vector);
9d5c8243 4170
047e0030 4171 napi_schedule(&q_vector->napi);
844290e5 4172
047e0030 4173 return IRQ_HANDLED;
fe4506b6
JC		 4174}
4175
421e02f0 4176#ifdef CONFIG_IGB_DCA
047e0030 4177static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4178{
047e0030 4179 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4180 struct e1000_hw *hw = &adapter->hw;
4181 int cpu = get_cpu();
fe4506b6 4182
047e0030
AD		 4183 if (q_vector->cpu == cpu)
4184 goto out_no_update;
4185
4186 if (q_vector->tx_ring) {
4187 int q = q_vector->tx_ring->reg_idx;
4188 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4189 if (hw->mac.type == e1000_82575) {
4190 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4191 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4192 } else {
047e0030
AD		 4193 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4194 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4195 E1000_DCA_TXCTRL_CPUID_SHIFT;
4196 }
4197 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4198 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4199 }
4200 if (q_vector->rx_ring) {
4201 int q = q_vector->rx_ring->reg_idx;
4202 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4203 if (hw->mac.type == e1000_82575) {
2d064c06 4204 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4205 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4206 } else {
4207 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4208 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4209 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4210 }
fe4506b6
JC		 4211 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4212 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4213 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4214 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4215 }
047e0030
AD		 4216 q_vector->cpu = cpu;
4217out_no_update:
fe4506b6
JC		 4218 put_cpu();
4219}
4220
4221static void igb_setup_dca(struct igb_adapter *adapter)
4222{
7e0e99ef 4223 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4224 int i;
4225
7dfc16fa 4226 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4227 return;
4228
7e0e99ef
AD		 4229 /* Always use CB2 mode, difference is masked in the CB driver. */
4230 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4231
047e0030 4232 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4233 adapter->q_vector[i]->cpu = -1;
4234 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4235 }
4236}
4237
4238static int __igb_notify_dca(struct device *dev, void *data)
4239{
4240 struct net_device *netdev = dev_get_drvdata(dev);
4241 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4242 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4243 struct e1000_hw *hw = &adapter->hw;
4244 unsigned long event = *(unsigned long *)data;
4245
4246 switch (event) {
4247 case DCA_PROVIDER_ADD:
4248 /* if already enabled, don't do it again */
7dfc16fa 4249 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4250 break;
fe4506b6 4251 if (dca_add_requester(dev) == 0) {
bbd98fe4 4252 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4253 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4254 igb_setup_dca(adapter);
4255 break;
4256 }
4257 /* Fall Through since DCA is disabled. */
4258 case DCA_PROVIDER_REMOVE:
7dfc16fa 4259 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4260 /* without this a class_device is left
047e0030 4261 * hanging around in the sysfs model */
fe4506b6 4262 dca_remove_requester(dev);
090b1795 4263 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4264 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4265 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4266 }
4267 break;
4268 }
bbd98fe4 4269
fe4506b6 4270 return 0;
9d5c8243
AK		 4271}
4272
fe4506b6
JC		 4273static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4274 void *p)
4275{
4276 int ret_val;
4277
4278 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4279 __igb_notify_dca);
4280
4281 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4282}
421e02f0 4283#endif /* CONFIG_IGB_DCA */
9d5c8243 4284
4ae196df
AD		 4285static void igb_ping_all_vfs(struct igb_adapter *adapter)
4286{
4287 struct e1000_hw *hw = &adapter->hw;
4288 u32 ping;
4289 int i;
4290
4291 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4292 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4293 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4294 ping |= E1000_VT_MSGTYPE_CTS;
4295 igb_write_mbx(hw, &ping, 1, i);
4296 }
4297}
4298
7d5753f0
AD		 4299static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4300{
4301 struct e1000_hw *hw = &adapter->hw;
4302 u32 vmolr = rd32(E1000_VMOLR(vf));
4303 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4304
4305 vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
4306 IGB_VF_FLAG_MULTI_PROMISC);
4307 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4308
4309 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4310 vmolr |= E1000_VMOLR_MPME;
4311 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4312 } else {
4313 /*
4314 * if we have hashes and we are clearing a multicast promisc
4315 * flag we need to write the hashes to the MTA as this step
4316 * was previously skipped
4317 */
4318 if (vf_data->num_vf_mc_hashes > 30) {
4319 vmolr |= E1000_VMOLR_MPME;
4320 } else if (vf_data->num_vf_mc_hashes) {
4321 int j;
4322 vmolr |= E1000_VMOLR_ROMPE;
4323 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4324 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4325 }
4326 }
4327
4328 wr32(E1000_VMOLR(vf), vmolr);
4329
4330 /* there are flags left unprocessed, likely not supported */
4331 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4332 return -EINVAL;
4333
4334 return 0;
4335
4336}
4337
4ae196df
AD		 4338static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4339 u32 *msgbuf, u32 vf)
4340{
4341 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4342 u16 *hash_list = (u16 *)&msgbuf[1];
4343 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4344 int i;
4345
7d5753f0 4346 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4347 * to this VF for later use to restore when the PF multi cast
4348 * list changes
4349 */
4350 vf_data->num_vf_mc_hashes = n;
4351
7d5753f0
AD		 4352 /* only up to 30 hash values supported */
4353 if (n > 30)
4354 n = 30;
4355
4356 /* store the hashes for later use */
4ae196df 4357 for (i = 0; i < n; i++)
a419aef8 4358 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4359
4360 /* Flush and reset the mta with the new values */
ff41f8dc 4361 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4362
4363 return 0;
4364}
4365
4366static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4367{
4368 struct e1000_hw *hw = &adapter->hw;
4369 struct vf_data_storage *vf_data;
4370 int i, j;
4371
4372 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4373 u32 vmolr = rd32(E1000_VMOLR(i));
4374 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4375
4ae196df 4376 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4377
4378 if ((vf_data->num_vf_mc_hashes > 30) ||
4379 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4380 vmolr |= E1000_VMOLR_MPME;
4381 } else if (vf_data->num_vf_mc_hashes) {
4382 vmolr |= E1000_VMOLR_ROMPE;
4383 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4384 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4385 }
4386 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4387 }
4388}
4389
4390static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4391{
4392 struct e1000_hw *hw = &adapter->hw;
4393 u32 pool_mask, reg, vid;
4394 int i;
4395
4396 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4397
4398 /* Find the vlan filter for this id */
4399 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4400 reg = rd32(E1000_VLVF(i));
4401
4402 /* remove the vf from the pool */
4403 reg &= ~pool_mask;
4404
4405 /* if pool is empty then remove entry from vfta */
4406 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4407 (reg & E1000_VLVF_VLANID_ENABLE)) {
4408 reg = 0;
4409 vid = reg & E1000_VLVF_VLANID_MASK;
4410 igb_vfta_set(hw, vid, false);
4411 }
4412
4413 wr32(E1000_VLVF(i), reg);
4414 }
ae641bdc
AD		 4415
4416 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4417}
4418
4419static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4420{
4421 struct e1000_hw *hw = &adapter->hw;
4422 u32 reg, i;
4423
51466239
AD		 4424 /* The vlvf table only exists on 82576 hardware and newer */
4425 if (hw->mac.type < e1000_82576)
4426 return -1;
4427
4428 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4429 if (!adapter->vfs_allocated_count)
4430 return -1;
4431
4432 /* Find the vlan filter for this id */
4433 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4434 reg = rd32(E1000_VLVF(i));
4435 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4436 vid == (reg & E1000_VLVF_VLANID_MASK))
4437 break;
4438 }
4439
4440 if (add) {
4441 if (i == E1000_VLVF_ARRAY_SIZE) {
4442 /* Did not find a matching VLAN ID entry that was
4443 * enabled. Search for a free filter entry, i.e.
4444 * one without the enable bit set
4445 */
4446 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4447 reg = rd32(E1000_VLVF(i));
4448 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4449 break;
4450 }
4451 }
4452 if (i < E1000_VLVF_ARRAY_SIZE) {
4453 /* Found an enabled/available entry */
4454 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4455
4456 /* if !enabled we need to set this up in vfta */
4457 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 4458 /* add VID to filter table */
4459 igb_vfta_set(hw, vid, true);
4ae196df
AD		 4460 reg |= E1000_VLVF_VLANID_ENABLE;
4461 }
cad6d05f
AD		 4462 reg &= ~E1000_VLVF_VLANID_MASK;
4463 reg |= vid;
4ae196df 4464 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4465
4466 /* do not modify RLPML for PF devices */
4467 if (vf >= adapter->vfs_allocated_count)
4468 return 0;
4469
4470 if (!adapter->vf_data[vf].vlans_enabled) {
4471 u32 size;
4472 reg = rd32(E1000_VMOLR(vf));
4473 size = reg & E1000_VMOLR_RLPML_MASK;
4474 size += 4;
4475 reg &= ~E1000_VMOLR_RLPML_MASK;
4476 reg |= size;
4477 wr32(E1000_VMOLR(vf), reg);
4478 }
ae641bdc 4479
51466239 4480 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 4481 return 0;
4482 }
4483 } else {
4484 if (i < E1000_VLVF_ARRAY_SIZE) {
4485 /* remove vf from the pool */
4486 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4487 /* if pool is empty then remove entry from vfta */
4488 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4489 reg = 0;
4490 igb_vfta_set(hw, vid, false);
4491 }
4492 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4493
4494 /* do not modify RLPML for PF devices */
4495 if (vf >= adapter->vfs_allocated_count)
4496 return 0;
4497
4498 adapter->vf_data[vf].vlans_enabled--;
4499 if (!adapter->vf_data[vf].vlans_enabled) {
4500 u32 size;
4501 reg = rd32(E1000_VMOLR(vf));
4502 size = reg & E1000_VMOLR_RLPML_MASK;
4503 size -= 4;
4504 reg &= ~E1000_VMOLR_RLPML_MASK;
4505 reg |= size;
4506 wr32(E1000_VMOLR(vf), reg);
4507 }
4ae196df
AD		 4508 }
4509 }
8151d294
WM		 4510 return 0;
4511}
4512
4513static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4514{
4515 struct e1000_hw *hw = &adapter->hw;
4516
4517 if (vid)
4518 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4519 else
4520 wr32(E1000_VMVIR(vf), 0);
4521}
4522
4523static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4524 int vf, u16 vlan, u8 qos)
4525{
4526 int err = 0;
4527 struct igb_adapter *adapter = netdev_priv(netdev);
4528
4529 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
4530 return -EINVAL;
4531 if (vlan || qos) {
4532 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
4533 if (err)
4534 goto out;
4535 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
4536 igb_set_vmolr(adapter, vf, !vlan);
4537 adapter->vf_data[vf].pf_vlan = vlan;
4538 adapter->vf_data[vf].pf_qos = qos;
4539 dev_info(&adapter->pdev->dev,
4540 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
4541 if (test_bit(__IGB_DOWN, &adapter->state)) {
4542 dev_warn(&adapter->pdev->dev,
4543 "The VF VLAN has been set,"
4544 " but the PF device is not up.\n");
4545 dev_warn(&adapter->pdev->dev,
4546 "Bring the PF device up before"
4547 " attempting to use the VF device.\n");
4548 }
4549 } else {
4550 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
4551 false, vf);
4552 igb_set_vmvir(adapter, vlan, vf);
4553 igb_set_vmolr(adapter, vf, true);
4554 adapter->vf_data[vf].pf_vlan = 0;
4555 adapter->vf_data[vf].pf_qos = 0;
4556 }
4557out:
4558 return err;
4ae196df
AD		 4559}
4560
4561static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4562{
4563 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4564 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4565
4566 return igb_vlvf_set(adapter, vid, add, vf);
4567}
4568
f2ca0dbe 4569static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 4570{
8151d294
WM		 4571 /* clear flags */
4572 adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
f2ca0dbe 4573 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 4574
4575 /* reset offloads to defaults */
8151d294 4576 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 4577
4578 /* reset vlans for device */
4579 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 4580 if (adapter->vf_data[vf].pf_vlan)
4581 igb_ndo_set_vf_vlan(adapter->netdev, vf,
4582 adapter->vf_data[vf].pf_vlan,
4583 adapter->vf_data[vf].pf_qos);
4584 else
4585 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 4586
4587 /* reset multicast table array for vf */
4588 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4589
4590 /* Flush and reset the mta with the new values */
ff41f8dc 4591 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4592}
4593
f2ca0dbe
AD		 4594static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4595{
4596 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4597
4598 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 4599 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
4600 random_ether_addr(vf_mac);
f2ca0dbe
AD		 4601
4602 /* process remaining reset events */
4603 igb_vf_reset(adapter, vf);
4604}
4605
4606static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 4607{
4608 struct e1000_hw *hw = &adapter->hw;
4609 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4610 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4611 u32 reg, msgbuf[3];
4612 u8 *addr = (u8 *)(&msgbuf[1]);
4613
4614 /* process all the same items cleared in a function level reset */
f2ca0dbe 4615 igb_vf_reset(adapter, vf);
4ae196df
AD		 4616
4617 /* set vf mac address */
26ad9178 4618 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4619
4620 /* enable transmit and receive for vf */
4621 reg = rd32(E1000_VFTE);
4622 wr32(E1000_VFTE, reg | (1 << vf));
4623 reg = rd32(E1000_VFRE);
4624 wr32(E1000_VFRE, reg | (1 << vf));
4625
f2ca0dbe 4626 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4ae196df
AD		 4627
4628 /* reply to reset with ack and vf mac address */
4629 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4630 memcpy(addr, vf_mac, 6);
4631 igb_write_mbx(hw, msgbuf, 3, vf);
4632}
4633
4634static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4635{
f2ca0dbe
AD		 4636 unsigned char *addr = (char *)&msg[1];
4637 int err = -1;
4ae196df 4638
f2ca0dbe
AD		 4639 if (is_valid_ether_addr(addr))
4640 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 4641
f2ca0dbe 4642 return err;
4ae196df
AD		 4643}
4644
4645static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4646{
4647 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4648 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4649 u32 msg = E1000_VT_MSGTYPE_NACK;
4650
4651 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 4652 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
4653 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 4654 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 4655 vf_data->last_nack = jiffies;
4ae196df
AD		 4656 }
4657}
4658
f2ca0dbe 4659static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 4660{
f2ca0dbe
AD		 4661 struct pci_dev *pdev = adapter->pdev;
4662 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 4663 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4664 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4665 s32 retval;
4666
f2ca0dbe 4667 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 4668
fef45f4c
AD		 4669 if (retval) {
4670 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 4671 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 4672 vf_data->flags &= ~IGB_VF_FLAG_CTS;
4673 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4674 return;
4675 goto out;
4676 }
4ae196df
AD		 4677
4678 /* this is a message we already processed, do nothing */
4679 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 4680 return;
4ae196df
AD		 4681
4682 /*
4683 * until the vf completes a reset it should not be
4684 * allowed to start any configuration.
4685 */
4686
4687 if (msgbuf[0] == E1000_VF_RESET) {
4688 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 4689 return;
4ae196df
AD		 4690 }
4691
f2ca0dbe 4692 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 4693 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4694 return;
4695 retval = -1;
4696 goto out;
4ae196df
AD		 4697 }
4698
4699 switch ((msgbuf[0] & 0xFFFF)) {
4700 case E1000_VF_SET_MAC_ADDR:
4701 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4702 break;
7d5753f0
AD		 4703 case E1000_VF_SET_PROMISC:
4704 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
4705 break;
4ae196df
AD		 4706 case E1000_VF_SET_MULTICAST:
4707 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4708 break;
4709 case E1000_VF_SET_LPE:
4710 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4711 break;
4712 case E1000_VF_SET_VLAN:
8151d294
WM		 4713 if (adapter->vf_data[vf].pf_vlan)
4714 retval = -1;
4715 else
4716 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 4717 break;
4718 default:
090b1795 4719 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 4720 retval = -1;
4721 break;
4722 }
4723
fef45f4c
AD		 4724 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4725out:
4ae196df
AD		 4726 /* notify the VF of the results of what it sent us */
4727 if (retval)
4728 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4729 else
4730 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4731
4ae196df 4732 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 4733}
4ae196df 4734
f2ca0dbe
AD		 4735static void igb_msg_task(struct igb_adapter *adapter)
4736{
4737 struct e1000_hw *hw = &adapter->hw;
4738 u32 vf;
4739
4740 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4741 /* process any reset requests */
4742 if (!igb_check_for_rst(hw, vf))
4743 igb_vf_reset_event(adapter, vf);
4744
4745 /* process any messages pending */
4746 if (!igb_check_for_msg(hw, vf))
4747 igb_rcv_msg_from_vf(adapter, vf);
4748
4749 /* process any acks */
4750 if (!igb_check_for_ack(hw, vf))
4751 igb_rcv_ack_from_vf(adapter, vf);
4752 }
4ae196df
AD		 4753}
4754
68d480c4
AD		 4755/**
4756 * igb_set_uta - Set unicast filter table address
4757 * @adapter: board private structure
4758 *
4759 * The unicast table address is a register array of 32-bit registers.
4760 * The table is meant to be used in a way similar to how the MTA is used
4761 * however due to certain limitations in the hardware it is necessary to
4762 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4763 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4764 **/
4765static void igb_set_uta(struct igb_adapter *adapter)
4766{
4767 struct e1000_hw *hw = &adapter->hw;
4768 int i;
4769
4770 /* The UTA table only exists on 82576 hardware and newer */
4771 if (hw->mac.type < e1000_82576)
4772 return;
4773
4774 /* we only need to do this if VMDq is enabled */
4775 if (!adapter->vfs_allocated_count)
4776 return;
4777
4778 for (i = 0; i < hw->mac.uta_reg_count; i++)
4779 array_wr32(E1000_UTA, i, ~0);
4780}
4781
9d5c8243
AK		 4782/**
4783 * igb_intr_msi - Interrupt Handler
4784 * @irq: interrupt number
4785 * @data: pointer to a network interface device structure
4786 **/
4787static irqreturn_t igb_intr_msi(int irq, void *data)
4788{
047e0030
AD		 4789 struct igb_adapter *adapter = data;
4790 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4791 struct e1000_hw *hw = &adapter->hw;
4792 /* read ICR disables interrupts using IAM */
4793 u32 icr = rd32(E1000_ICR);
4794
047e0030 4795 igb_write_itr(q_vector);
9d5c8243 4796
7f081d40
AD		 4797 if (icr & E1000_ICR_DRSTA)
4798 schedule_work(&adapter->reset_task);
4799
047e0030 4800 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4801 /* HW is reporting DMA is out of sync */
4802 adapter->stats.doosync++;
4803 }
4804
9d5c8243
AK		 4805 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4806 hw->mac.get_link_status = 1;
4807 if (!test_bit(__IGB_DOWN, &adapter->state))
4808 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4809 }
4810
047e0030 4811 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4812
4813 return IRQ_HANDLED;
4814}
4815
4816/**
4a3c6433 4817 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4818 * @irq: interrupt number
4819 * @data: pointer to a network interface device structure
4820 **/
4821static irqreturn_t igb_intr(int irq, void *data)
4822{
047e0030
AD		 4823 struct igb_adapter *adapter = data;
4824 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4825 struct e1000_hw *hw = &adapter->hw;
4826 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4827 * need for the IMC write */
4828 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4829 if (!icr)
4830 return IRQ_NONE; /* Not our interrupt */
4831
047e0030 4832 igb_write_itr(q_vector);
9d5c8243
AK		 4833
4834 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4835 * not set, then the adapter didn't send an interrupt */
4836 if (!(icr & E1000_ICR_INT_ASSERTED))
4837 return IRQ_NONE;
4838
7f081d40
AD		 4839 if (icr & E1000_ICR_DRSTA)
4840 schedule_work(&adapter->reset_task);
4841
047e0030 4842 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4843 /* HW is reporting DMA is out of sync */
4844 adapter->stats.doosync++;
4845 }
4846
9d5c8243
AK		 4847 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4848 hw->mac.get_link_status = 1;
4849 /* guard against interrupt when we're going down */
4850 if (!test_bit(__IGB_DOWN, &adapter->state))
4851 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4852 }
4853
047e0030 4854 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4855
4856 return IRQ_HANDLED;
4857}
4858
047e0030 4859static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4860{
047e0030 4861 struct igb_adapter *adapter = q_vector->adapter;
46544258 4862 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4863
4fc82adf
AD		 4864 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
4865 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 4866 if (!adapter->msix_entries)
6eb5a7f1 4867 igb_set_itr(adapter);
46544258 4868 else
047e0030 4869 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4870 }
4871
46544258
AD		 4872 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4873 if (adapter->msix_entries)
047e0030 4874 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4875 else
4876 igb_irq_enable(adapter);
4877 }
9d5c8243
AK		 4878}
4879
46544258
AD		 4880/**
4881 * igb_poll - NAPI Rx polling callback
4882 * @napi: napi polling structure
4883 * @budget: count of how many packets we should handle
4884 **/
4885static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4886{
047e0030
AD		 4887 struct igb_q_vector *q_vector = container_of(napi,
4888 struct igb_q_vector,
4889 napi);
4890 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4891
421e02f0 4892#ifdef CONFIG_IGB_DCA
047e0030
AD		 4893 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4894 igb_update_dca(q_vector);
fe4506b6 4895#endif
047e0030
AD		 4896 if (q_vector->tx_ring)
4897 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4898
047e0030
AD		 4899 if (q_vector->rx_ring)
4900 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4901
4902 if (!tx_clean_complete)
4903 work_done = budget;
46544258 4904
9d5c8243 4905 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4906 if (work_done < budget) {
288379f0 4907 napi_complete(napi);
047e0030 4908 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4909 }
4910
46544258 4911 return work_done;
9d5c8243 4912}
6d8126f9 4913
33af6bcc 4914/**
c5b9bd5e 4915 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 4916 * @adapter: board private structure
c5b9bd5e
AD		 4917 * @shhwtstamps: timestamp structure to update
4918 * @regval: unsigned 64bit system time value.
4919 *
4920 * We need to convert the system time value stored in the RX/TXSTMP registers
4921 * into a hwtstamp which can be used by the upper level timestamping functions
4922 */
4923static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
4924 struct skb_shared_hwtstamps *shhwtstamps,
4925 u64 regval)
4926{
4927 u64 ns;
4928
55cac248
AD		 4929 /*
4930 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
4931 * 24 to match clock shift we setup earlier.
4932 */
4933 if (adapter->hw.mac.type == e1000_82580)
4934 regval <<= IGB_82580_TSYNC_SHIFT;
4935
c5b9bd5e
AD		 4936 ns = timecounter_cyc2time(&adapter->clock, regval);
4937 timecompare_update(&adapter->compare, ns);
4938 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
4939 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4940 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
4941}
4942
4943/**
4944 * igb_tx_hwtstamp - utility function which checks for TX time stamp
4945 * @q_vector: pointer to q_vector containing needed info
33af6bcc
PO		 4946 * @skb: packet that was just sent
4947 *
4948 * If we were asked to do hardware stamping and such a time stamp is
4949 * available, then it must have been for this skb here because we only
4950 * allow only one such packet into the queue.
4951 */
c5b9bd5e 4952static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
33af6bcc 4953{
c5b9bd5e 4954 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc
PO		 4955 union skb_shared_tx *shtx = skb_tx(skb);
4956 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 4957 struct skb_shared_hwtstamps shhwtstamps;
4958 u64 regval;
33af6bcc 4959
c5b9bd5e
AD		 4960 /* if skb does not support hw timestamp or TX stamp not valid exit */
4961 if (likely(!shtx->hardware) ||
4962 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
4963 return;
4964
4965 regval = rd32(E1000_TXSTMPL);
4966 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4967
4968 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
4969 skb_tstamp_tx(skb, &shhwtstamps);
33af6bcc
PO		 4970}
4971
9d5c8243
AK		 4972/**
4973 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4974 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4975 * returns true if ring is completely cleaned
4976 **/
047e0030 4977static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4978{
047e0030
AD		 4979 struct igb_adapter *adapter = q_vector->adapter;
4980 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 4981 struct net_device *netdev = tx_ring->netdev;
0e014cb1 4982 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4983 struct igb_buffer *buffer_info;
4984 struct sk_buff *skb;
0e014cb1 4985 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4986 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4987 unsigned int i, eop, count = 0;
4988 bool cleaned = false;
9d5c8243 4989
9d5c8243 4990 i = tx_ring->next_to_clean;
0e014cb1
AD		 4991 eop = tx_ring->buffer_info[i].next_to_watch;
4992 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4993
4994 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4995 (count < tx_ring->count)) {
4996 for (cleaned = false; !cleaned; count++) {
4997 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4998 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4999 cleaned = (i == eop);
9d5c8243
AK		 5000 skb = buffer_info->skb;
5001
5002 if (skb) {
5003 unsigned int segs, bytecount;
5004 /* gso_segs is currently only valid for tcp */
5005 segs = skb_shinfo(skb)->gso_segs ?: 1;
5006 /* multiply data chunks by size of headers */
5007 bytecount = ((segs - 1) * skb_headlen(skb)) +
5008 skb->len;
5009 total_packets += segs;
5010 total_bytes += bytecount;
33af6bcc 5011
c5b9bd5e 5012 igb_tx_hwtstamp(q_vector, skb);
9d5c8243
AK		 5013 }
5014
80785298 5015 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5016 tx_desc->wb.status = 0;
9d5c8243
AK		 5017
5018 i++;
5019 if (i == tx_ring->count)
5020 i = 0;
9d5c8243 5021 }
0e014cb1
AD		 5022 eop = tx_ring->buffer_info[i].next_to_watch;
5023 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5024 }
5025
9d5c8243
AK		 5026 tx_ring->next_to_clean = i;
5027
fc7d345d 5028 if (unlikely(count &&
9d5c8243 5029 netif_carrier_ok(netdev) &&
c493ea45 5030 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5031 /* Make sure that anybody stopping the queue after this
5032 * sees the new next_to_clean.
5033 */
5034 smp_mb();
661086df
PWJ		 5035 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5036 !(test_bit(__IGB_DOWN, &adapter->state))) {
5037 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 5038 tx_ring->tx_stats.restart_queue++;
661086df 5039 }
9d5c8243
AK		 5040 }
5041
5042 if (tx_ring->detect_tx_hung) {
5043 /* Detect a transmit hang in hardware, this serializes the
5044 * check with the clearing of time_stamp and movement of i */
5045 tx_ring->detect_tx_hung = false;
5046 if (tx_ring->buffer_info[i].time_stamp &&
5047 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5048 (adapter->tx_timeout_factor * HZ)) &&
5049 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5050
9d5c8243 5051 /* detected Tx unit hang */
80785298 5052 dev_err(&tx_ring->pdev->dev,
9d5c8243 5053 "Detected Tx Unit Hang\n"
2d064c06 5054 " Tx Queue <%d>\n"
9d5c8243
AK		 5055 " TDH <%x>\n"
5056 " TDT <%x>\n"
5057 " next_to_use <%x>\n"
5058 " next_to_clean <%x>\n"
9d5c8243
AK		 5059 "buffer_info[next_to_clean]\n"
5060 " time_stamp <%lx>\n"
0e014cb1 5061 " next_to_watch <%x>\n"
9d5c8243
AK		 5062 " jiffies <%lx>\n"
5063 " desc.status <%x>\n",
2d064c06 5064 tx_ring->queue_index,
fce99e34
AD		 5065 readl(tx_ring->head),
5066 readl(tx_ring->tail),
9d5c8243
AK		 5067 tx_ring->next_to_use,
5068 tx_ring->next_to_clean,
f7ba205e 5069 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5070 eop,
9d5c8243 5071 jiffies,
0e014cb1 5072 eop_desc->wb.status);
661086df 5073 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5074 }
5075 }
5076 tx_ring->total_bytes += total_bytes;
5077 tx_ring->total_packets += total_packets;
e21ed353
AD		 5078 tx_ring->tx_stats.bytes += total_bytes;
5079 tx_ring->tx_stats.packets += total_packets;
0e014cb1 5080 return (count < tx_ring->count);
9d5c8243
AK		 5081}
5082
9d5c8243
AK		 5083/**
5084 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5085 * @q_vector: structure containing interrupt and ring information
5086 * @skb: packet to send up
5087 * @vlan_tag: vlan tag for packet
9d5c8243 5088 **/
047e0030
AD		 5089static void igb_receive_skb(struct igb_q_vector *q_vector,
5090 struct sk_buff *skb,
5091 u16 vlan_tag)
5092{
5093 struct igb_adapter *adapter = q_vector->adapter;
5094
5095 if (vlan_tag)
5096 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5097 vlan_tag, skb);
182ff8df 5098 else
047e0030 5099 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5100}
5101
04a5fcaa 5102static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5103 u32 status_err, struct sk_buff *skb)
5104{
5105 skb->ip_summed = CHECKSUM_NONE;
5106
5107 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5108 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5109 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5110 return;
85ad76b2 5111
9d5c8243
AK		 5112 /* TCP/UDP checksum error bit is set */
5113 if (status_err &
5114 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5115 /*
5116 * work around errata with sctp packets where the TCPE aka
5117 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5118 * packets, (aka let the stack check the crc32c)
5119 */
85ad76b2
AD		 5120 if ((skb->len == 60) &&
5121 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 5122 ring->rx_stats.csum_err++;
85ad76b2 5123
9d5c8243 5124 /* let the stack verify checksum errors */
9d5c8243
AK		 5125 return;
5126 }
5127 /* It must be a TCP or UDP packet with a valid checksum */
5128 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5129 skb->ip_summed = CHECKSUM_UNNECESSARY;
5130
85ad76b2 5131 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5132}
5133
c5b9bd5e
AD		 5134static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
5135 struct sk_buff *skb)
5136{
5137 struct igb_adapter *adapter = q_vector->adapter;
5138 struct e1000_hw *hw = &adapter->hw;
5139 u64 regval;
5140
5141 /*
5142 * If this bit is set, then the RX registers contain the time stamp. No
5143 * other packet will be time stamped until we read these registers, so
5144 * read the registers to make them available again. Because only one
5145 * packet can be time stamped at a time, we know that the register
5146 * values must belong to this one here and therefore we don't need to
5147 * compare any of the additional attributes stored for it.
5148 *
5149 * If nothing went wrong, then it should have a skb_shared_tx that we
5150 * can turn into a skb_shared_hwtstamps.
5151 */
5152 if (likely(!(staterr & E1000_RXDADV_STAT_TS)))
5153 return;
5154 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5155 return;
5156
5157 regval = rd32(E1000_RXSTMPL);
5158 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5159
5160 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5161}
4c844851 5162static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5163 union e1000_adv_rx_desc *rx_desc)
5164{
5165 /* HW will not DMA in data larger than the given buffer, even if it
5166 * parses the (NFS, of course) header to be larger. In that case, it
5167 * fills the header buffer and spills the rest into the page.
5168 */
5169 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5170 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5171 if (hlen > rx_ring->rx_buffer_len)
5172 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5173 return hlen;
5174}
5175
047e0030
AD		 5176static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5177 int *work_done, int budget)
9d5c8243 5178{
047e0030 5179 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5180 struct net_device *netdev = rx_ring->netdev;
80785298 5181 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 5182 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5183 struct igb_buffer *buffer_info , *next_buffer;
5184 struct sk_buff *skb;
9d5c8243
AK		 5185 bool cleaned = false;
5186 int cleaned_count = 0;
d1eff350 5187 int current_node = numa_node_id();
9d5c8243 5188 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5189 unsigned int i;
2d94d8ab
AD		 5190 u32 staterr;
5191 u16 length;
047e0030 5192 u16 vlan_tag;
9d5c8243
AK		 5193
5194 i = rx_ring->next_to_clean;
69d3ca53 5195 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5196 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5197 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5198
5199 while (staterr & E1000_RXD_STAT_DD) {
5200 if (*work_done >= budget)
5201 break;
5202 (*work_done)++;
9d5c8243 5203
69d3ca53
AD		 5204 skb = buffer_info->skb;
5205 prefetch(skb->data - NET_IP_ALIGN);
5206 buffer_info->skb = NULL;
5207
5208 i++;
5209 if (i == rx_ring->count)
5210 i = 0;
42d0781a 5211
69d3ca53
AD		 5212 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5213 prefetch(next_rxd);
5214 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5215
5216 length = le16_to_cpu(rx_desc->wb.upper.length);
5217 cleaned = true;
5218 cleaned_count++;
5219
2d94d8ab 5220 if (buffer_info->dma) {
bf36c1a0 5221 pci_unmap_single(pdev, buffer_info->dma,
4c844851 5222 rx_ring->rx_buffer_len,
bf36c1a0 5223 PCI_DMA_FROMDEVICE);
91615f76 5224 buffer_info->dma = 0;
4c844851 5225 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5226 skb_put(skb, length);
5227 goto send_up;
5228 }
4c844851 5229 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5230 }
5231
5232 if (length) {
9d5c8243 5233 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 5234 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 5235 buffer_info->page_dma = 0;
bf36c1a0
AD		 5236
5237 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
5238 buffer_info->page,
5239 buffer_info->page_offset,
5240 length);
5241
d1eff350
AD		 5242 if ((page_count(buffer_info->page) != 1) ||
5243 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5244 buffer_info->page = NULL;
5245 else
5246 get_page(buffer_info->page);
9d5c8243
AK		 5247
5248 skb->len += length;
5249 skb->data_len += length;
bf36c1a0 5250 skb->truesize += length;
9d5c8243 5251 }
9d5c8243 5252
bf36c1a0 5253 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5254 buffer_info->skb = next_buffer->skb;
5255 buffer_info->dma = next_buffer->dma;
5256 next_buffer->skb = skb;
5257 next_buffer->dma = 0;
bf36c1a0
AD		 5258 goto next_desc;
5259 }
69d3ca53 5260send_up:
9d5c8243
AK		 5261 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5262 dev_kfree_skb_irq(skb);
5263 goto next_desc;
5264 }
9d5c8243 5265
c5b9bd5e 5266 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5267 total_bytes += skb->len;
5268 total_packets++;
5269
85ad76b2 5270 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5271
5272 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5273 skb_record_rx_queue(skb, rx_ring->queue_index);
5274
5275 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5276 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5277
047e0030 5278 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5279
9d5c8243
AK		 5280next_desc:
5281 rx_desc->wb.upper.status_error = 0;
5282
5283 /* return some buffers to hardware, one at a time is too slow */
5284 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5285 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5286 cleaned_count = 0;
5287 }
5288
5289 /* use prefetched values */
5290 rx_desc = next_rxd;
5291 buffer_info = next_buffer;
9d5c8243
AK		 5292 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5293 }
bf36c1a0 5294
9d5c8243 5295 rx_ring->next_to_clean = i;
c493ea45 5296 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5297
5298 if (cleaned_count)
3b644cf6 5299 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5300
5301 rx_ring->total_packets += total_packets;
5302 rx_ring->total_bytes += total_bytes;
5303 rx_ring->rx_stats.packets += total_packets;
5304 rx_ring->rx_stats.bytes += total_bytes;
9d5c8243
AK		 5305 return cleaned;
5306}
5307
9d5c8243
AK		 5308/**
5309 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5310 * @adapter: address of board private structure
5311 **/
d7ee5b3a 5312void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5313{
e694e964 5314 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5315 union e1000_adv_rx_desc *rx_desc;
5316 struct igb_buffer *buffer_info;
5317 struct sk_buff *skb;
5318 unsigned int i;
db761762 5319 int bufsz;
9d5c8243
AK		 5320
5321 i = rx_ring->next_to_use;
5322 buffer_info = &rx_ring->buffer_info[i];
5323
4c844851 5324 bufsz = rx_ring->rx_buffer_len;
db761762 5325
9d5c8243
AK		 5326 while (cleaned_count--) {
5327 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5328
6ec43fe6 5329 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5330 if (!buffer_info->page) {
42d0781a 5331 buffer_info->page = netdev_alloc_page(netdev);
bf36c1a0 5332 if (!buffer_info->page) {
04a5fcaa 5333 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5334 goto no_buffers;
5335 }
5336 buffer_info->page_offset = 0;
5337 } else {
5338 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5339 }
5340 buffer_info->page_dma =
80785298 5341 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5342 buffer_info->page_offset,
5343 PAGE_SIZE / 2,
9d5c8243 5344 PCI_DMA_FROMDEVICE);
42d0781a
AD		 5345 if (pci_dma_mapping_error(rx_ring->pdev,
5346 buffer_info->page_dma)) {
5347 buffer_info->page_dma = 0;
5348 rx_ring->rx_stats.alloc_failed++;
5349 goto no_buffers;
5350 }
9d5c8243
AK		 5351 }
5352
42d0781a
AD		 5353 skb = buffer_info->skb;
5354 if (!skb) {
89d71a66 5355 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5356 if (!skb) {
04a5fcaa 5357 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5358 goto no_buffers;
5359 }
5360
9d5c8243 5361 buffer_info->skb = skb;
42d0781a
AD		 5362 }
5363 if (!buffer_info->dma) {
80785298
AD		 5364 buffer_info->dma = pci_map_single(rx_ring->pdev,
5365 skb->data,
9d5c8243
AK		 5366 bufsz,
5367 PCI_DMA_FROMDEVICE);
42d0781a
AD		 5368 if (pci_dma_mapping_error(rx_ring->pdev,
5369 buffer_info->dma)) {
5370 buffer_info->dma = 0;
5371 rx_ring->rx_stats.alloc_failed++;
5372 goto no_buffers;
5373 }
9d5c8243
AK		 5374 }
5375 /* Refresh the desc even if buffer_addrs didn't change because
5376 * each write-back erases this info. */
6ec43fe6 5377 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5378 rx_desc->read.pkt_addr =
5379 cpu_to_le64(buffer_info->page_dma);
5380 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5381 } else {
42d0781a 5382 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5383 rx_desc->read.hdr_addr = 0;
5384 }
5385
5386 i++;
5387 if (i == rx_ring->count)
5388 i = 0;
5389 buffer_info = &rx_ring->buffer_info[i];
5390 }
5391
5392no_buffers:
5393 if (rx_ring->next_to_use != i) {
5394 rx_ring->next_to_use = i;
5395 if (i == 0)
5396 i = (rx_ring->count - 1);
5397 else
5398 i--;
5399
5400 /* Force memory writes to complete before letting h/w
5401 * know there are new descriptors to fetch. (Only
5402 * applicable for weak-ordered memory model archs,
5403 * such as IA-64). */
5404 wmb();
fce99e34 5405 writel(i, rx_ring->tail);
9d5c8243
AK		 5406 }
5407}
5408
5409/**
5410 * igb_mii_ioctl -
5411 * @netdev:
5412 * @ifreq:
5413 * @cmd:
5414 **/
5415static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5416{
5417 struct igb_adapter *adapter = netdev_priv(netdev);
5418 struct mii_ioctl_data *data = if_mii(ifr);
5419
5420 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5421 return -EOPNOTSUPP;
5422
5423 switch (cmd) {
5424 case SIOCGMIIPHY:
5425 data->phy_id = adapter->hw.phy.addr;
5426 break;
5427 case SIOCGMIIREG:
f5f4cf08
AD		 5428 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5429 &data->val_out))
9d5c8243
AK		 5430 return -EIO;
5431 break;
5432 case SIOCSMIIREG:
5433 default:
5434 return -EOPNOTSUPP;
5435 }
5436 return 0;
5437}
5438
c6cb090b
PO		 5439/**
5440 * igb_hwtstamp_ioctl - control hardware time stamping
5441 * @netdev:
5442 * @ifreq:
5443 * @cmd:
5444 *
33af6bcc
PO		 5445 * Outgoing time stamping can be enabled and disabled. Play nice and
5446 * disable it when requested, although it shouldn't case any overhead
5447 * when no packet needs it. At most one packet in the queue may be
5448 * marked for time stamping, otherwise it would be impossible to tell
5449 * for sure to which packet the hardware time stamp belongs.
5450 *
5451 * Incoming time stamping has to be configured via the hardware
5452 * filters. Not all combinations are supported, in particular event
5453 * type has to be specified. Matching the kind of event packet is
5454 * not supported, with the exception of "all V2 events regardless of
5455 * level 2 or 4".
5456 *
c6cb090b
PO		 5457 **/
5458static int igb_hwtstamp_ioctl(struct net_device *netdev,
5459 struct ifreq *ifr, int cmd)
5460{
33af6bcc
PO		 5461 struct igb_adapter *adapter = netdev_priv(netdev);
5462 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5463 struct hwtstamp_config config;
c5b9bd5e
AD		 5464 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5465 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5466 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5467 bool is_l4 = false;
5468 bool is_l2 = false;
33af6bcc 5469 u32 regval;
c6cb090b
PO		 5470
5471 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5472 return -EFAULT;
5473
5474 /* reserved for future extensions */
5475 if (config.flags)
5476 return -EINVAL;
5477
33af6bcc
PO		 5478 switch (config.tx_type) {
5479 case HWTSTAMP_TX_OFF:
c5b9bd5e 5480 tsync_tx_ctl = 0;
33af6bcc 5481 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5482 break;
5483 default:
5484 return -ERANGE;
5485 }
5486
5487 switch (config.rx_filter) {
5488 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5489 tsync_rx_ctl = 0;
33af6bcc
PO		 5490 break;
5491 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5492 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5493 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5494 case HWTSTAMP_FILTER_ALL:
5495 /*
5496 * register TSYNCRXCFG must be set, therefore it is not
5497 * possible to time stamp both Sync and Delay_Req messages
5498 * => fall back to time stamping all packets
5499 */
c5b9bd5e 5500 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 5501 config.rx_filter = HWTSTAMP_FILTER_ALL;
5502 break;
5503 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 5504 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5505 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 5506 is_l4 = true;
33af6bcc
PO		 5507 break;
5508 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 5509 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5510 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 5511 is_l4 = true;
33af6bcc
PO		 5512 break;
5513 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5514 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 5515 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5516 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 5517 is_l2 = true;
5518 is_l4 = true;
33af6bcc
PO		 5519 config.rx_filter = HWTSTAMP_FILTER_SOME;
5520 break;
5521 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 5523 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5524 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 5525 is_l2 = true;
5526 is_l4 = true;
33af6bcc
PO		 5527 config.rx_filter = HWTSTAMP_FILTER_SOME;
5528 break;
5529 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5530 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5531 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 5532 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 5533 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 5534 is_l2 = true;
33af6bcc
PO		 5535 break;
5536 default:
5537 return -ERANGE;
5538 }
5539
c5b9bd5e
AD		 5540 if (hw->mac.type == e1000_82575) {
5541 if (tsync_rx_ctl | tsync_tx_ctl)
5542 return -EINVAL;
5543 return 0;
5544 }
5545
33af6bcc
PO		 5546 /* enable/disable TX */
5547 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 5548 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5549 regval |= tsync_tx_ctl;
33af6bcc
PO		 5550 wr32(E1000_TSYNCTXCTL, regval);
5551
c5b9bd5e 5552 /* enable/disable RX */
33af6bcc 5553 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 5554 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5555 regval |= tsync_rx_ctl;
33af6bcc 5556 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 5557
c5b9bd5e
AD		 5558 /* define which PTP packets are time stamped */
5559 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 5560
c5b9bd5e
AD		 5561 /* define ethertype filter for timestamped packets */
5562 if (is_l2)
5563 wr32(E1000_ETQF(3),
5564 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5565 E1000_ETQF_1588 | /* enable timestamping */
5566 ETH_P_1588)); /* 1588 eth protocol type */
5567 else
5568 wr32(E1000_ETQF(3), 0);
5569
5570#define PTP_PORT 319
5571 /* L4 Queue Filter[3]: filter by destination port and protocol */
5572 if (is_l4) {
5573 u32 ftqf = (IPPROTO_UDP /* UDP */
5574 | E1000_FTQF_VF_BP /* VF not compared */
5575 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5576 | E1000_FTQF_MASK); /* mask all inputs */
5577 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5578
5579 wr32(E1000_IMIR(3), htons(PTP_PORT));
5580 wr32(E1000_IMIREXT(3),
5581 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5582 if (hw->mac.type == e1000_82576) {
5583 /* enable source port check */
5584 wr32(E1000_SPQF(3), htons(PTP_PORT));
5585 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5586 }
5587 wr32(E1000_FTQF(3), ftqf);
5588 } else {
5589 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5590 }
33af6bcc
PO		 5591 wrfl();
5592
5593 adapter->hwtstamp_config = config;
5594
5595 /* clear TX/RX time stamp registers, just to be sure */
5596 regval = rd32(E1000_TXSTMPH);
5597 regval = rd32(E1000_RXSTMPH);
c6cb090b 5598
33af6bcc
PO		 5599 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5600 -EFAULT : 0;
c6cb090b
PO		 5601}
5602
9d5c8243
AK		 5603/**
5604 * igb_ioctl -
5605 * @netdev:
5606 * @ifreq:
5607 * @cmd:
5608 **/
5609static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5610{
5611 switch (cmd) {
5612 case SIOCGMIIPHY:
5613 case SIOCGMIIREG:
5614 case SIOCSMIIREG:
5615 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5616 case SIOCSHWTSTAMP:
5617 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5618 default:
5619 return -EOPNOTSUPP;
5620 }
5621}
5622
009bc06e
AD		 5623s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5624{
5625 struct igb_adapter *adapter = hw->back;
5626 u16 cap_offset;
5627
5628 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5629 if (!cap_offset)
5630 return -E1000_ERR_CONFIG;
5631
5632 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5633
5634 return 0;
5635}
5636
5637s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5638{
5639 struct igb_adapter *adapter = hw->back;
5640 u16 cap_offset;
5641
5642 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5643 if (!cap_offset)
5644 return -E1000_ERR_CONFIG;
5645
5646 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5647
5648 return 0;
5649}
5650
9d5c8243
AK		 5651static void igb_vlan_rx_register(struct net_device *netdev,
5652 struct vlan_group *grp)
5653{
5654 struct igb_adapter *adapter = netdev_priv(netdev);
5655 struct e1000_hw *hw = &adapter->hw;
5656 u32 ctrl, rctl;
5657
5658 igb_irq_disable(adapter);
5659 adapter->vlgrp = grp;
5660
5661 if (grp) {
5662 /* enable VLAN tag insert/strip */
5663 ctrl = rd32(E1000_CTRL);
5664 ctrl |= E1000_CTRL_VME;
5665 wr32(E1000_CTRL, ctrl);
5666
51466239 5667 /* Disable CFI check */
9d5c8243 5668 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5669 rctl &= ~E1000_RCTL_CFIEN;
5670 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 5671 } else {
5672 /* disable VLAN tag insert/strip */
5673 ctrl = rd32(E1000_CTRL);
5674 ctrl &= ~E1000_CTRL_VME;
5675 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 5676 }
5677
e1739522
AD		 5678 igb_rlpml_set(adapter);
5679
9d5c8243
AK		 5680 if (!test_bit(__IGB_DOWN, &adapter->state))
5681 igb_irq_enable(adapter);
5682}
5683
5684static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5685{
5686 struct igb_adapter *adapter = netdev_priv(netdev);
5687 struct e1000_hw *hw = &adapter->hw;
4ae196df 5688 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5689
51466239
AD		 5690 /* attempt to add filter to vlvf array */
5691 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 5692
51466239
AD		 5693 /* add the filter since PF can receive vlans w/o entry in vlvf */
5694 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 5695}
5696
5697static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5698{
5699 struct igb_adapter *adapter = netdev_priv(netdev);
5700 struct e1000_hw *hw = &adapter->hw;
4ae196df 5701 int pf_id = adapter->vfs_allocated_count;
51466239 5702 s32 err;
9d5c8243
AK		 5703
5704 igb_irq_disable(adapter);
5705 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5706
5707 if (!test_bit(__IGB_DOWN, &adapter->state))
5708 igb_irq_enable(adapter);
5709
51466239
AD		 5710 /* remove vlan from VLVF table array */
5711 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 5712
51466239
AD		 5713 /* if vid was not present in VLVF just remove it from table */
5714 if (err)
4ae196df 5715 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5716}
5717
5718static void igb_restore_vlan(struct igb_adapter *adapter)
5719{
5720 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5721
5722 if (adapter->vlgrp) {
5723 u16 vid;
5724 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5725 if (!vlan_group_get_device(adapter->vlgrp, vid))
5726 continue;
5727 igb_vlan_rx_add_vid(adapter->netdev, vid);
5728 }
5729 }
5730}
5731
5732int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5733{
090b1795 5734 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 5735 struct e1000_mac_info *mac = &adapter->hw.mac;
5736
5737 mac->autoneg = 0;
5738
9d5c8243
AK		 5739 switch (spddplx) {
5740 case SPEED_10 + DUPLEX_HALF:
5741 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5742 break;
5743 case SPEED_10 + DUPLEX_FULL:
5744 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5745 break;
5746 case SPEED_100 + DUPLEX_HALF:
5747 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5748 break;
5749 case SPEED_100 + DUPLEX_FULL:
5750 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5751 break;
5752 case SPEED_1000 + DUPLEX_FULL:
5753 mac->autoneg = 1;
5754 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5755 break;
5756 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5757 default:
090b1795 5758 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 5759 return -EINVAL;
5760 }
5761 return 0;
5762}
5763
3fe7c4c9 5764static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5765{
5766 struct net_device *netdev = pci_get_drvdata(pdev);
5767 struct igb_adapter *adapter = netdev_priv(netdev);
5768 struct e1000_hw *hw = &adapter->hw;
2d064c06 5769 u32 ctrl, rctl, status;
9d5c8243
AK		 5770 u32 wufc = adapter->wol;
5771#ifdef CONFIG_PM
5772 int retval = 0;
5773#endif
5774
5775 netif_device_detach(netdev);
5776
a88f10ec
AD		 5777 if (netif_running(netdev))
5778 igb_close(netdev);
5779
047e0030 5780 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5781
5782#ifdef CONFIG_PM
5783 retval = pci_save_state(pdev);
5784 if (retval)
5785 return retval;
5786#endif
5787
5788 status = rd32(E1000_STATUS);
5789 if (status & E1000_STATUS_LU)
5790 wufc &= ~E1000_WUFC_LNKC;
5791
5792 if (wufc) {
5793 igb_setup_rctl(adapter);
ff41f8dc 5794 igb_set_rx_mode(netdev);
9d5c8243
AK		 5795
5796 /* turn on all-multi mode if wake on multicast is enabled */
5797 if (wufc & E1000_WUFC_MC) {
5798 rctl = rd32(E1000_RCTL);
5799 rctl |= E1000_RCTL_MPE;
5800 wr32(E1000_RCTL, rctl);
5801 }
5802
5803 ctrl = rd32(E1000_CTRL);
5804 /* advertise wake from D3Cold */
5805 #define E1000_CTRL_ADVD3WUC 0x00100000
5806 /* phy power management enable */
5807 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5808 ctrl |= E1000_CTRL_ADVD3WUC;
5809 wr32(E1000_CTRL, ctrl);
5810
9d5c8243 5811 /* Allow time for pending master requests to run */
330a6d6a 5812 igb_disable_pcie_master(hw);
9d5c8243
AK		 5813
5814 wr32(E1000_WUC, E1000_WUC_PME_EN);
5815 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5816 } else {
5817 wr32(E1000_WUC, 0);
5818 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5819 }
5820
3fe7c4c9
RW		 5821 *enable_wake = wufc || adapter->en_mng_pt;
5822 if (!*enable_wake)
2fb02a26 5823 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5824
5825 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5826 * would have already happened in close and is redundant. */
5827 igb_release_hw_control(adapter);
5828
5829 pci_disable_device(pdev);
5830
9d5c8243
AK		 5831 return 0;
5832}
5833
5834#ifdef CONFIG_PM
3fe7c4c9
RW		 5835static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5836{
5837 int retval;
5838 bool wake;
5839
5840 retval = __igb_shutdown(pdev, &wake);
5841 if (retval)
5842 return retval;
5843
5844 if (wake) {
5845 pci_prepare_to_sleep(pdev);
5846 } else {
5847 pci_wake_from_d3(pdev, false);
5848 pci_set_power_state(pdev, PCI_D3hot);
5849 }
5850
5851 return 0;
5852}
5853
9d5c8243
AK		 5854static int igb_resume(struct pci_dev *pdev)
5855{
5856 struct net_device *netdev = pci_get_drvdata(pdev);
5857 struct igb_adapter *adapter = netdev_priv(netdev);
5858 struct e1000_hw *hw = &adapter->hw;
5859 u32 err;
5860
5861 pci_set_power_state(pdev, PCI_D0);
5862 pci_restore_state(pdev);
42bfd33a 5863
aed5dec3 5864 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5865 if (err) {
5866 dev_err(&pdev->dev,
5867 "igb: Cannot enable PCI device from suspend\n");
5868 return err;
5869 }
5870 pci_set_master(pdev);
5871
5872 pci_enable_wake(pdev, PCI_D3hot, 0);
5873 pci_enable_wake(pdev, PCI_D3cold, 0);
5874
047e0030 5875 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5876 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5877 return -ENOMEM;
9d5c8243
AK		 5878 }
5879
5880 /* e1000_power_up_phy(adapter); */
5881
5882 igb_reset(adapter);
a8564f03
AD		 5883
5884 /* let the f/w know that the h/w is now under the control of the
5885 * driver. */
5886 igb_get_hw_control(adapter);
5887
9d5c8243
AK		 5888 wr32(E1000_WUS, ~0);
5889
a88f10ec
AD		 5890 if (netif_running(netdev)) {
5891 err = igb_open(netdev);
5892 if (err)
5893 return err;
5894 }
9d5c8243
AK		 5895
5896 netif_device_attach(netdev);
5897
9d5c8243
AK		 5898 return 0;
5899}
5900#endif
5901
5902static void igb_shutdown(struct pci_dev *pdev)
5903{
3fe7c4c9
RW		 5904 bool wake;
5905
5906 __igb_shutdown(pdev, &wake);
5907
5908 if (system_state == SYSTEM_POWER_OFF) {
5909 pci_wake_from_d3(pdev, wake);
5910 pci_set_power_state(pdev, PCI_D3hot);
5911 }
9d5c8243
AK		 5912}
5913
5914#ifdef CONFIG_NET_POLL_CONTROLLER
5915/*
5916 * Polling 'interrupt' - used by things like netconsole to send skbs
5917 * without having to re-enable interrupts. It's not called while
5918 * the interrupt routine is executing.
5919 */
5920static void igb_netpoll(struct net_device *netdev)
5921{
5922 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5923 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5924 int i;
9d5c8243 5925
eebbbdba 5926 if (!adapter->msix_entries) {
047e0030 5927 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5928 igb_irq_disable(adapter);
047e0030 5929 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5930 return;
5931 }
9d5c8243 5932
047e0030
AD		 5933 for (i = 0; i < adapter->num_q_vectors; i++) {
5934 struct igb_q_vector *q_vector = adapter->q_vector[i];
5935 wr32(E1000_EIMC, q_vector->eims_value);
5936 napi_schedule(&q_vector->napi);
eebbbdba 5937 }
9d5c8243
AK		 5938}
5939#endif /* CONFIG_NET_POLL_CONTROLLER */
5940
5941/**
5942 * igb_io_error_detected - called when PCI error is detected
5943 * @pdev: Pointer to PCI device
5944 * @state: The current pci connection state
5945 *
5946 * This function is called after a PCI bus error affecting
5947 * this device has been detected.
5948 */
5949static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5950 pci_channel_state_t state)
5951{
5952 struct net_device *netdev = pci_get_drvdata(pdev);
5953 struct igb_adapter *adapter = netdev_priv(netdev);
5954
5955 netif_device_detach(netdev);
5956
59ed6eec
AD		 5957 if (state == pci_channel_io_perm_failure)
5958 return PCI_ERS_RESULT_DISCONNECT;
5959
9d5c8243
AK		 5960 if (netif_running(netdev))
5961 igb_down(adapter);
5962 pci_disable_device(pdev);
5963
5964 /* Request a slot slot reset. */
5965 return PCI_ERS_RESULT_NEED_RESET;
5966}
5967
5968/**
5969 * igb_io_slot_reset - called after the pci bus has been reset.
5970 * @pdev: Pointer to PCI device
5971 *
5972 * Restart the card from scratch, as if from a cold-boot. Implementation
5973 * resembles the first-half of the igb_resume routine.
5974 */
5975static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5976{
5977 struct net_device *netdev = pci_get_drvdata(pdev);
5978 struct igb_adapter *adapter = netdev_priv(netdev);
5979 struct e1000_hw *hw = &adapter->hw;
40a914fa 5980 pci_ers_result_t result;
42bfd33a 5981 int err;
9d5c8243 5982
aed5dec3 5983 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5984 dev_err(&pdev->dev,
5985 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5986 result = PCI_ERS_RESULT_DISCONNECT;
5987 } else {
5988 pci_set_master(pdev);
5989 pci_restore_state(pdev);
9d5c8243 5990
40a914fa
AD		 5991 pci_enable_wake(pdev, PCI_D3hot, 0);
5992 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5993
40a914fa
AD		 5994 igb_reset(adapter);
5995 wr32(E1000_WUS, ~0);
5996 result = PCI_ERS_RESULT_RECOVERED;
5997 }
9d5c8243 5998
ea943d41
JK		 5999 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6000 if (err) {
6001 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6002 "failed 0x%0x\n", err);
6003 /* non-fatal, continue */
6004 }
40a914fa
AD		 6005
6006 return result;
9d5c8243
AK		 6007}
6008
6009/**
6010 * igb_io_resume - called when traffic can start flowing again.
6011 * @pdev: Pointer to PCI device
6012 *
6013 * This callback is called when the error recovery driver tells us that
6014 * its OK to resume normal operation. Implementation resembles the
6015 * second-half of the igb_resume routine.
6016 */
6017static void igb_io_resume(struct pci_dev *pdev)
6018{
6019 struct net_device *netdev = pci_get_drvdata(pdev);
6020 struct igb_adapter *adapter = netdev_priv(netdev);
6021
9d5c8243
AK		 6022 if (netif_running(netdev)) {
6023 if (igb_up(adapter)) {
6024 dev_err(&pdev->dev, "igb_up failed after reset\n");
6025 return;
6026 }
6027 }
6028
6029 netif_device_attach(netdev);
6030
6031 /* let the f/w know that the h/w is now under the control of the
6032 * driver. */
6033 igb_get_hw_control(adapter);
9d5c8243
AK		 6034}
6035
26ad9178
AD		 6036static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6037 u8 qsel)
6038{
6039 u32 rar_low, rar_high;
6040 struct e1000_hw *hw = &adapter->hw;
6041
6042 /* HW expects these in little endian so we reverse the byte order
6043 * from network order (big endian) to little endian
6044 */
6045 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6046 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6047 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6048
6049 /* Indicate to hardware the Address is Valid. */
6050 rar_high |= E1000_RAH_AV;
6051
6052 if (hw->mac.type == e1000_82575)
6053 rar_high |= E1000_RAH_POOL_1 * qsel;
6054 else
6055 rar_high |= E1000_RAH_POOL_1 << qsel;
6056
6057 wr32(E1000_RAL(index), rar_low);
6058 wrfl();
6059 wr32(E1000_RAH(index), rar_high);
6060 wrfl();
6061}
6062
4ae196df
AD		 6063static int igb_set_vf_mac(struct igb_adapter *adapter,
6064 int vf, unsigned char *mac_addr)
6065{
6066 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6067 /* VF MAC addresses start at end of receive addresses and moves
6068 * torwards the first, as a result a collision should not be possible */
6069 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6070
37680117 6071 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6072
26ad9178 6073 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6074
6075 return 0;
6076}
6077
8151d294
WM		 6078static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6079{
6080 struct igb_adapter *adapter = netdev_priv(netdev);
6081 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6082 return -EINVAL;
6083 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6084 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6085 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6086 " change effective.");
6087 if (test_bit(__IGB_DOWN, &adapter->state)) {
6088 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6089 " but the PF device is not up.\n");
6090 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6091 " attempting to use the VF device.\n");
6092 }
6093 return igb_set_vf_mac(adapter, vf, mac);
6094}
6095
6096static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6097{
6098 return -EOPNOTSUPP;
6099}
6100
6101static int igb_ndo_get_vf_config(struct net_device *netdev,
6102 int vf, struct ifla_vf_info *ivi)
6103{
6104 struct igb_adapter *adapter = netdev_priv(netdev);
6105 if (vf >= adapter->vfs_allocated_count)
6106 return -EINVAL;
6107 ivi->vf = vf;
6108 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6109 ivi->tx_rate = 0;
6110 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6111 ivi->qos = adapter->vf_data[vf].pf_qos;
6112 return 0;
6113}
6114
4ae196df
AD		 6115static void igb_vmm_control(struct igb_adapter *adapter)
6116{
6117 struct e1000_hw *hw = &adapter->hw;
10d8e907 6118 u32 reg;
4ae196df 6119
d4960307
AD		 6120 /* replication is not supported for 82575 */
6121 if (hw->mac.type == e1000_82575)
4ae196df
AD		 6122 return;
6123
10d8e907
AD		 6124 /* enable replication vlan tag stripping */
6125 reg = rd32(E1000_RPLOLR);
6126 reg |= E1000_RPLOLR_STRVLAN;
6127 wr32(E1000_RPLOLR, reg);
6128
6129 /* notify HW that the MAC is adding vlan tags */
6130 reg = rd32(E1000_DTXCTL);
6131 reg |= E1000_DTXCTL_VLAN_ADDED;
6132 wr32(E1000_DTXCTL, reg);
6133
d4960307
AD		 6134 if (adapter->vfs_allocated_count) {
6135 igb_vmdq_set_loopback_pf(hw, true);
6136 igb_vmdq_set_replication_pf(hw, true);
6137 } else {
6138 igb_vmdq_set_loopback_pf(hw, false);
6139 igb_vmdq_set_replication_pf(hw, false);
6140 }
4ae196df
AD		 6141}
6142
9d5c8243 6143/* igb_main.c */
Linux kernel - Deliverables
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