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igb: fix init on 82575 with MNG enabled
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
44
45#include "igb.h"
46
47#define DRV_VERSION "1.0.8-k2"
48char igb_driver_name[] = "igb";
49char igb_driver_version[] = DRV_VERSION;
50static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver";
52static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
53
54
55static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info,
57};
58
59static struct pci_device_id igb_pci_tbl[] = {
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
63 /* required last entry */
64 {0, }
65};
66
67MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
68
69void igb_reset(struct igb_adapter *);
70static int igb_setup_all_tx_resources(struct igb_adapter *);
71static int igb_setup_all_rx_resources(struct igb_adapter *);
72static void igb_free_all_tx_resources(struct igb_adapter *);
73static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 74static void igb_free_tx_resources(struct igb_ring *);
75static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 76void igb_update_stats(struct igb_adapter *);
77static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78static void __devexit igb_remove(struct pci_dev *pdev);
79static int igb_sw_init(struct igb_adapter *);
80static int igb_open(struct net_device *);
81static int igb_close(struct net_device *);
82static void igb_configure_tx(struct igb_adapter *);
83static void igb_configure_rx(struct igb_adapter *);
84static void igb_setup_rctl(struct igb_adapter *);
85static void igb_clean_all_tx_rings(struct igb_adapter *);
86static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 87static void igb_clean_tx_ring(struct igb_ring *);
88static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 89static void igb_set_multi(struct net_device *);
90static void igb_update_phy_info(unsigned long);
91static void igb_watchdog(unsigned long);
92static void igb_watchdog_task(struct work_struct *);
93static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
94 struct igb_ring *);
95static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
96static struct net_device_stats *igb_get_stats(struct net_device *);
97static int igb_change_mtu(struct net_device *, int);
98static int igb_set_mac(struct net_device *, void *);
99static irqreturn_t igb_intr(int irq, void *);
100static irqreturn_t igb_intr_msi(int irq, void *);
101static irqreturn_t igb_msix_other(int irq, void *);
102static irqreturn_t igb_msix_rx(int irq, void *);
103static irqreturn_t igb_msix_tx(int irq, void *);
104static int igb_clean_rx_ring_msix(struct napi_struct *, int);
3b644cf6 105static bool igb_clean_tx_irq(struct igb_ring *);
9d5c8243 106static int igb_clean(struct napi_struct *, int);
3b644cf6
MW		 107static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
108static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 109static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
110static void igb_tx_timeout(struct net_device *);
111static void igb_reset_task(struct work_struct *);
112static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
113static void igb_vlan_rx_add_vid(struct net_device *, u16);
114static void igb_vlan_rx_kill_vid(struct net_device *, u16);
115static void igb_restore_vlan(struct igb_adapter *);
116
117static int igb_suspend(struct pci_dev *, pm_message_t);
118#ifdef CONFIG_PM
119static int igb_resume(struct pci_dev *);
120#endif
121static void igb_shutdown(struct pci_dev *);
122
123#ifdef CONFIG_NET_POLL_CONTROLLER
124/* for netdump / net console */
125static void igb_netpoll(struct net_device *);
126#endif
127
128static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
129 pci_channel_state_t);
130static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
131static void igb_io_resume(struct pci_dev *);
132
133static struct pci_error_handlers igb_err_handler = {
134 .error_detected = igb_io_error_detected,
135 .slot_reset = igb_io_slot_reset,
136 .resume = igb_io_resume,
137};
138
139
140static struct pci_driver igb_driver = {
141 .name = igb_driver_name,
142 .id_table = igb_pci_tbl,
143 .probe = igb_probe,
144 .remove = __devexit_p(igb_remove),
145#ifdef CONFIG_PM
146 /* Power Managment Hooks */
147 .suspend = igb_suspend,
148 .resume = igb_resume,
149#endif
150 .shutdown = igb_shutdown,
151 .err_handler = &igb_err_handler
152};
153
154MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
155MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
156MODULE_LICENSE("GPL");
157MODULE_VERSION(DRV_VERSION);
158
159#ifdef DEBUG
160/**
161 * igb_get_hw_dev_name - return device name string
162 * used by hardware layer to print debugging information
163 **/
164char *igb_get_hw_dev_name(struct e1000_hw *hw)
165{
166 struct igb_adapter *adapter = hw->back;
167 return adapter->netdev->name;
168}
169#endif
170
171/**
172 * igb_init_module - Driver Registration Routine
173 *
174 * igb_init_module is the first routine called when the driver is
175 * loaded. All it does is register with the PCI subsystem.
176 **/
177static int __init igb_init_module(void)
178{
179 int ret;
180 printk(KERN_INFO "%s - version %s\n",
181 igb_driver_string, igb_driver_version);
182
183 printk(KERN_INFO "%s\n", igb_copyright);
184
185 ret = pci_register_driver(&igb_driver);
186 return ret;
187}
188
189module_init(igb_init_module);
190
191/**
192 * igb_exit_module - Driver Exit Cleanup Routine
193 *
194 * igb_exit_module is called just before the driver is removed
195 * from memory.
196 **/
197static void __exit igb_exit_module(void)
198{
199 pci_unregister_driver(&igb_driver);
200}
201
202module_exit(igb_exit_module);
203
204/**
205 * igb_alloc_queues - Allocate memory for all rings
206 * @adapter: board private structure to initialize
207 *
208 * We allocate one ring per queue at run-time since we don't know the
209 * number of queues at compile-time.
210 **/
211static int igb_alloc_queues(struct igb_adapter *adapter)
212{
213 int i;
214
215 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
216 sizeof(struct igb_ring), GFP_KERNEL);
217 if (!adapter->tx_ring)
218 return -ENOMEM;
219
220 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
221 sizeof(struct igb_ring), GFP_KERNEL);
222 if (!adapter->rx_ring) {
223 kfree(adapter->tx_ring);
224 return -ENOMEM;
225 }
226
227 for (i = 0; i < adapter->num_rx_queues; i++) {
228 struct igb_ring *ring = &(adapter->rx_ring[i]);
229 ring->adapter = adapter;
230 ring->itr_register = E1000_ITR;
231
232 if (!ring->napi.poll)
233 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
234 adapter->napi.weight /
235 adapter->num_rx_queues);
236 }
237 return 0;
238}
239
240#define IGB_N0_QUEUE -1
241static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
242 int tx_queue, int msix_vector)
243{
244 u32 msixbm = 0;
245 struct e1000_hw *hw = &adapter->hw;
246 /* The 82575 assigns vectors using a bitmask, which matches the
247 bitmask for the EICR/EIMS/EIMC registers. To assign one
248 or more queues to a vector, we write the appropriate bits
249 into the MSIXBM register for that vector. */
250 if (rx_queue > IGB_N0_QUEUE) {
251 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
252 adapter->rx_ring[rx_queue].eims_value = msixbm;
253 }
254 if (tx_queue > IGB_N0_QUEUE) {
255 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
256 adapter->tx_ring[tx_queue].eims_value =
257 E1000_EICR_TX_QUEUE0 << tx_queue;
258 }
259 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
260}
261
262/**
263 * igb_configure_msix - Configure MSI-X hardware
264 *
265 * igb_configure_msix sets up the hardware to properly
266 * generate MSI-X interrupts.
267 **/
268static void igb_configure_msix(struct igb_adapter *adapter)
269{
270 u32 tmp;
271 int i, vector = 0;
272 struct e1000_hw *hw = &adapter->hw;
273
274 adapter->eims_enable_mask = 0;
275
276 for (i = 0; i < adapter->num_tx_queues; i++) {
277 struct igb_ring *tx_ring = &adapter->tx_ring[i];
278 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
279 adapter->eims_enable_mask |= tx_ring->eims_value;
280 if (tx_ring->itr_val)
281 writel(1000000000 / (tx_ring->itr_val * 256),
282 hw->hw_addr + tx_ring->itr_register);
283 else
284 writel(1, hw->hw_addr + tx_ring->itr_register);
285 }
286
287 for (i = 0; i < adapter->num_rx_queues; i++) {
288 struct igb_ring *rx_ring = &adapter->rx_ring[i];
289 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
290 adapter->eims_enable_mask |= rx_ring->eims_value;
291 if (rx_ring->itr_val)
292 writel(1000000000 / (rx_ring->itr_val * 256),
293 hw->hw_addr + rx_ring->itr_register);
294 else
295 writel(1, hw->hw_addr + rx_ring->itr_register);
296 }
297
298
299 /* set vector for other causes, i.e. link changes */
300 array_wr32(E1000_MSIXBM(0), vector++,
301 E1000_EIMS_OTHER);
302
303 /* disable IAM for ICR interrupt bits */
304 wr32(E1000_IAM, 0);
305
306 tmp = rd32(E1000_CTRL_EXT);
307 /* enable MSI-X PBA support*/
308 tmp |= E1000_CTRL_EXT_PBA_CLR;
309
310 /* Auto-Mask interrupts upon ICR read. */
311 tmp |= E1000_CTRL_EXT_EIAME;
312 tmp |= E1000_CTRL_EXT_IRCA;
313
314 wr32(E1000_CTRL_EXT, tmp);
315 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
316
317 wrfl();
318}
319
320/**
321 * igb_request_msix - Initialize MSI-X interrupts
322 *
323 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
324 * kernel.
325 **/
326static int igb_request_msix(struct igb_adapter *adapter)
327{
328 struct net_device *netdev = adapter->netdev;
329 int i, err = 0, vector = 0;
330
331 vector = 0;
332
333 for (i = 0; i < adapter->num_tx_queues; i++) {
334 struct igb_ring *ring = &(adapter->tx_ring[i]);
335 sprintf(ring->name, "%s-tx%d", netdev->name, i);
336 err = request_irq(adapter->msix_entries[vector].vector,
337 &igb_msix_tx, 0, ring->name,
338 &(adapter->tx_ring[i]));
339 if (err)
340 goto out;
341 ring->itr_register = E1000_EITR(0) + (vector << 2);
342 ring->itr_val = adapter->itr;
343 vector++;
344 }
345 for (i = 0; i < adapter->num_rx_queues; i++) {
346 struct igb_ring *ring = &(adapter->rx_ring[i]);
347 if (strlen(netdev->name) < (IFNAMSIZ - 5))
348 sprintf(ring->name, "%s-rx%d", netdev->name, i);
349 else
350 memcpy(ring->name, netdev->name, IFNAMSIZ);
351 err = request_irq(adapter->msix_entries[vector].vector,
352 &igb_msix_rx, 0, ring->name,
353 &(adapter->rx_ring[i]));
354 if (err)
355 goto out;
356 ring->itr_register = E1000_EITR(0) + (vector << 2);
357 ring->itr_val = adapter->itr;
358 vector++;
359 }
360
361 err = request_irq(adapter->msix_entries[vector].vector,
362 &igb_msix_other, 0, netdev->name, netdev);
363 if (err)
364 goto out;
365
366 adapter->napi.poll = igb_clean_rx_ring_msix;
367 for (i = 0; i < adapter->num_rx_queues; i++)
368 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
369 igb_configure_msix(adapter);
370 return 0;
371out:
372 return err;
373}
374
375static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
376{
377 if (adapter->msix_entries) {
378 pci_disable_msix(adapter->pdev);
379 kfree(adapter->msix_entries);
380 adapter->msix_entries = NULL;
381 } else if (adapter->msi_enabled)
382 pci_disable_msi(adapter->pdev);
383 return;
384}
385
386
387/**
388 * igb_set_interrupt_capability - set MSI or MSI-X if supported
389 *
390 * Attempt to configure interrupts using the best available
391 * capabilities of the hardware and kernel.
392 **/
393static void igb_set_interrupt_capability(struct igb_adapter *adapter)
394{
395 int err;
396 int numvecs, i;
397
398 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
399 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
400 GFP_KERNEL);
401 if (!adapter->msix_entries)
402 goto msi_only;
403
404 for (i = 0; i < numvecs; i++)
405 adapter->msix_entries[i].entry = i;
406
407 err = pci_enable_msix(adapter->pdev,
408 adapter->msix_entries,
409 numvecs);
410 if (err == 0)
411 return;
412
413 igb_reset_interrupt_capability(adapter);
414
415 /* If we can't do MSI-X, try MSI */
416msi_only:
417 adapter->num_rx_queues = 1;
418 if (!pci_enable_msi(adapter->pdev))
419 adapter->msi_enabled = 1;
420 return;
421}
422
423/**
424 * igb_request_irq - initialize interrupts
425 *
426 * Attempts to configure interrupts using the best available
427 * capabilities of the hardware and kernel.
428 **/
429static int igb_request_irq(struct igb_adapter *adapter)
430{
431 struct net_device *netdev = adapter->netdev;
432 struct e1000_hw *hw = &adapter->hw;
433 int err = 0;
434
435 if (adapter->msix_entries) {
436 err = igb_request_msix(adapter);
437 if (!err) {
9d5c8243 438 /* enable IAM, auto-mask,
6cb5e577 439 * DO NOT USE EIAM or IAM in legacy mode */
9d5c8243
AK		 440 wr32(E1000_IAM, IMS_ENABLE_MASK);
441 goto request_done;
442 }
443 /* fall back to MSI */
444 igb_reset_interrupt_capability(adapter);
445 if (!pci_enable_msi(adapter->pdev))
446 adapter->msi_enabled = 1;
447 igb_free_all_tx_resources(adapter);
448 igb_free_all_rx_resources(adapter);
449 adapter->num_rx_queues = 1;
450 igb_alloc_queues(adapter);
451 }
452 if (adapter->msi_enabled) {
453 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
454 netdev->name, netdev);
455 if (!err)
456 goto request_done;
457 /* fall back to legacy interrupts */
458 igb_reset_interrupt_capability(adapter);
459 adapter->msi_enabled = 0;
460 }
461
462 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
463 netdev->name, netdev);
464
6cb5e577 465 if (err)
9d5c8243
AK		 466 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
467 err);
9d5c8243
AK		 468
469request_done:
470 return err;
471}
472
473static void igb_free_irq(struct igb_adapter *adapter)
474{
475 struct net_device *netdev = adapter->netdev;
476
477 if (adapter->msix_entries) {
478 int vector = 0, i;
479
480 for (i = 0; i < adapter->num_tx_queues; i++)
481 free_irq(adapter->msix_entries[vector++].vector,
482 &(adapter->tx_ring[i]));
483 for (i = 0; i < adapter->num_rx_queues; i++)
484 free_irq(adapter->msix_entries[vector++].vector,
485 &(adapter->rx_ring[i]));
486
487 free_irq(adapter->msix_entries[vector++].vector, netdev);
488 return;
489 }
490
491 free_irq(adapter->pdev->irq, netdev);
492}
493
494/**
495 * igb_irq_disable - Mask off interrupt generation on the NIC
496 * @adapter: board private structure
497 **/
498static void igb_irq_disable(struct igb_adapter *adapter)
499{
500 struct e1000_hw *hw = &adapter->hw;
501
502 if (adapter->msix_entries) {
503 wr32(E1000_EIMC, ~0);
504 wr32(E1000_EIAC, 0);
505 }
506 wr32(E1000_IMC, ~0);
507 wrfl();
508 synchronize_irq(adapter->pdev->irq);
509}
510
511/**
512 * igb_irq_enable - Enable default interrupt generation settings
513 * @adapter: board private structure
514 **/
515static void igb_irq_enable(struct igb_adapter *adapter)
516{
517 struct e1000_hw *hw = &adapter->hw;
518
519 if (adapter->msix_entries) {
520 wr32(E1000_EIMS,
521 adapter->eims_enable_mask);
522 wr32(E1000_EIAC,
523 adapter->eims_enable_mask);
524 wr32(E1000_IMS, E1000_IMS_LSC);
525 } else
526 wr32(E1000_IMS, IMS_ENABLE_MASK);
527}
528
529static void igb_update_mng_vlan(struct igb_adapter *adapter)
530{
531 struct net_device *netdev = adapter->netdev;
532 u16 vid = adapter->hw.mng_cookie.vlan_id;
533 u16 old_vid = adapter->mng_vlan_id;
534 if (adapter->vlgrp) {
535 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
536 if (adapter->hw.mng_cookie.status &
537 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
538 igb_vlan_rx_add_vid(netdev, vid);
539 adapter->mng_vlan_id = vid;
540 } else
541 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
542
543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
544 (vid != old_vid) &&
545 !vlan_group_get_device(adapter->vlgrp, old_vid))
546 igb_vlan_rx_kill_vid(netdev, old_vid);
547 } else
548 adapter->mng_vlan_id = vid;
549 }
550}
551
552/**
553 * igb_release_hw_control - release control of the h/w to f/w
554 * @adapter: address of board private structure
555 *
556 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
557 * For ASF and Pass Through versions of f/w this means that the
558 * driver is no longer loaded.
559 *
560 **/
561static void igb_release_hw_control(struct igb_adapter *adapter)
562{
563 struct e1000_hw *hw = &adapter->hw;
564 u32 ctrl_ext;
565
566 /* Let firmware take over control of h/w */
567 ctrl_ext = rd32(E1000_CTRL_EXT);
568 wr32(E1000_CTRL_EXT,
569 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
570}
571
572
573/**
574 * igb_get_hw_control - get control of the h/w from f/w
575 * @adapter: address of board private structure
576 *
577 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
578 * For ASF and Pass Through versions of f/w this means that
579 * the driver is loaded.
580 *
581 **/
582static void igb_get_hw_control(struct igb_adapter *adapter)
583{
584 struct e1000_hw *hw = &adapter->hw;
585 u32 ctrl_ext;
586
587 /* Let firmware know the driver has taken over */
588 ctrl_ext = rd32(E1000_CTRL_EXT);
589 wr32(E1000_CTRL_EXT,
590 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
591}
592
593static void igb_init_manageability(struct igb_adapter *adapter)
594{
595 struct e1000_hw *hw = &adapter->hw;
596
597 if (adapter->en_mng_pt) {
598 u32 manc2h = rd32(E1000_MANC2H);
599 u32 manc = rd32(E1000_MANC);
600
9d5c8243
AK		 601 /* enable receiving management packets to the host */
602 /* this will probably generate destination unreachable messages
603 * from the host OS, but the packets will be handled on SMBUS */
604 manc |= E1000_MANC_EN_MNG2HOST;
605#define E1000_MNG2HOST_PORT_623 (1 << 5)
606#define E1000_MNG2HOST_PORT_664 (1 << 6)
607 manc2h |= E1000_MNG2HOST_PORT_623;
608 manc2h |= E1000_MNG2HOST_PORT_664;
609 wr32(E1000_MANC2H, manc2h);
610
611 wr32(E1000_MANC, manc);
612 }
613}
614
9d5c8243
AK		 615/**
616 * igb_configure - configure the hardware for RX and TX
617 * @adapter: private board structure
618 **/
619static void igb_configure(struct igb_adapter *adapter)
620{
621 struct net_device *netdev = adapter->netdev;
622 int i;
623
624 igb_get_hw_control(adapter);
625 igb_set_multi(netdev);
626
627 igb_restore_vlan(adapter);
628 igb_init_manageability(adapter);
629
630 igb_configure_tx(adapter);
631 igb_setup_rctl(adapter);
632 igb_configure_rx(adapter);
662d7205
AD		 633
634 igb_rx_fifo_flush_82575(&adapter->hw);
635
9d5c8243
AK		 636 /* call IGB_DESC_UNUSED which always leaves
637 * at least 1 descriptor unused to make sure
638 * next_to_use != next_to_clean */
639 for (i = 0; i < adapter->num_rx_queues; i++) {
640 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 641 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 642 }
643
644
645 adapter->tx_queue_len = netdev->tx_queue_len;
646}
647
648
649/**
650 * igb_up - Open the interface and prepare it to handle traffic
651 * @adapter: board private structure
652 **/
653
654int igb_up(struct igb_adapter *adapter)
655{
656 struct e1000_hw *hw = &adapter->hw;
657 int i;
658
659 /* hardware has been reset, we need to reload some things */
660 igb_configure(adapter);
661
662 clear_bit(__IGB_DOWN, &adapter->state);
663
664 napi_enable(&adapter->napi);
665
666 if (adapter->msix_entries) {
667 for (i = 0; i < adapter->num_rx_queues; i++)
668 napi_enable(&adapter->rx_ring[i].napi);
669 igb_configure_msix(adapter);
670 }
671
672 /* Clear any pending interrupts. */
673 rd32(E1000_ICR);
674 igb_irq_enable(adapter);
675
676 /* Fire a link change interrupt to start the watchdog. */
677 wr32(E1000_ICS, E1000_ICS_LSC);
678 return 0;
679}
680
681void igb_down(struct igb_adapter *adapter)
682{
683 struct e1000_hw *hw = &adapter->hw;
684 struct net_device *netdev = adapter->netdev;
685 u32 tctl, rctl;
686 int i;
687
688 /* signal that we're down so the interrupt handler does not
689 * reschedule our watchdog timer */
690 set_bit(__IGB_DOWN, &adapter->state);
691
692 /* disable receives in the hardware */
693 rctl = rd32(E1000_RCTL);
694 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
695 /* flush and sleep below */
696
697 netif_stop_queue(netdev);
698
699 /* disable transmits in the hardware */
700 tctl = rd32(E1000_TCTL);
701 tctl &= ~E1000_TCTL_EN;
702 wr32(E1000_TCTL, tctl);
703 /* flush both disables and wait for them to finish */
704 wrfl();
705 msleep(10);
706
707 napi_disable(&adapter->napi);
708
709 if (adapter->msix_entries)
710 for (i = 0; i < adapter->num_rx_queues; i++)
711 napi_disable(&adapter->rx_ring[i].napi);
712 igb_irq_disable(adapter);
713
714 del_timer_sync(&adapter->watchdog_timer);
715 del_timer_sync(&adapter->phy_info_timer);
716
717 netdev->tx_queue_len = adapter->tx_queue_len;
718 netif_carrier_off(netdev);
719 adapter->link_speed = 0;
720 adapter->link_duplex = 0;
721
3023682e
JK		 722 if (!pci_channel_offline(adapter->pdev))
723 igb_reset(adapter);
9d5c8243
AK		 724 igb_clean_all_tx_rings(adapter);
725 igb_clean_all_rx_rings(adapter);
726}
727
728void igb_reinit_locked(struct igb_adapter *adapter)
729{
730 WARN_ON(in_interrupt());
731 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
732 msleep(1);
733 igb_down(adapter);
734 igb_up(adapter);
735 clear_bit(__IGB_RESETTING, &adapter->state);
736}
737
738void igb_reset(struct igb_adapter *adapter)
739{
740 struct e1000_hw *hw = &adapter->hw;
741 struct e1000_fc_info *fc = &adapter->hw.fc;
742 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
743 u16 hwm;
744
745 /* Repartition Pba for greater than 9k mtu
746 * To take effect CTRL.RST is required.
747 */
748 pba = E1000_PBA_34K;
749
750 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
751 /* adjust PBA for jumbo frames */
752 wr32(E1000_PBA, pba);
753
754 /* To maintain wire speed transmits, the Tx FIFO should be
755 * large enough to accommodate two full transmit packets,
756 * rounded up to the next 1KB and expressed in KB. Likewise,
757 * the Rx FIFO should be large enough to accommodate at least
758 * one full receive packet and is similarly rounded up and
759 * expressed in KB. */
760 pba = rd32(E1000_PBA);
761 /* upper 16 bits has Tx packet buffer allocation size in KB */
762 tx_space = pba >> 16;
763 /* lower 16 bits has Rx packet buffer allocation size in KB */
764 pba &= 0xffff;
765 /* the tx fifo also stores 16 bytes of information about the tx
766 * but don't include ethernet FCS because hardware appends it */
767 min_tx_space = (adapter->max_frame_size +
768 sizeof(struct e1000_tx_desc) -
769 ETH_FCS_LEN) * 2;
770 min_tx_space = ALIGN(min_tx_space, 1024);
771 min_tx_space >>= 10;
772 /* software strips receive CRC, so leave room for it */
773 min_rx_space = adapter->max_frame_size;
774 min_rx_space = ALIGN(min_rx_space, 1024);
775 min_rx_space >>= 10;
776
777 /* If current Tx allocation is less than the min Tx FIFO size,
778 * and the min Tx FIFO size is less than the current Rx FIFO
779 * allocation, take space away from current Rx allocation */
780 if (tx_space < min_tx_space &&
781 ((min_tx_space - tx_space) < pba)) {
782 pba = pba - (min_tx_space - tx_space);
783
784 /* if short on rx space, rx wins and must trump tx
785 * adjustment */
786 if (pba < min_rx_space)
787 pba = min_rx_space;
788 }
789 }
790 wr32(E1000_PBA, pba);
791
792 /* flow control settings */
793 /* The high water mark must be low enough to fit one full frame
794 * (or the size used for early receive) above it in the Rx FIFO.
795 * Set it to the lower of:
796 * - 90% of the Rx FIFO size, or
797 * - the full Rx FIFO size minus one full frame */
798 hwm = min(((pba << 10) * 9 / 10),
799 ((pba << 10) - adapter->max_frame_size));
800
801 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
802 fc->low_water = fc->high_water - 8;
803 fc->pause_time = 0xFFFF;
804 fc->send_xon = 1;
805 fc->type = fc->original_type;
806
807 /* Allow time for pending master requests to run */
808 adapter->hw.mac.ops.reset_hw(&adapter->hw);
809 wr32(E1000_WUC, 0);
810
811 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
812 dev_err(&adapter->pdev->dev, "Hardware Error\n");
813
814 igb_update_mng_vlan(adapter);
815
816 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
817 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
818
819 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 820 if (adapter->hw.phy.ops.get_phy_info)
821 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 822}
823
42bfd33a
TI		 824/**
825 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
826 * @pdev: PCI device information struct
827 *
828 * Returns true if an adapter needs ioport resources
829 **/
830static int igb_is_need_ioport(struct pci_dev *pdev)
831{
832 switch (pdev->device) {
833 /* Currently there are no adapters that need ioport resources */
834 default:
835 return false;
836 }
837}
838
9d5c8243
AK		 839/**
840 * igb_probe - Device Initialization Routine
841 * @pdev: PCI device information struct
842 * @ent: entry in igb_pci_tbl
843 *
844 * Returns 0 on success, negative on failure
845 *
846 * igb_probe initializes an adapter identified by a pci_dev structure.
847 * The OS initialization, configuring of the adapter private structure,
848 * and a hardware reset occur.
849 **/
850static int __devinit igb_probe(struct pci_dev *pdev,
851 const struct pci_device_id *ent)
852{
853 struct net_device *netdev;
854 struct igb_adapter *adapter;
855 struct e1000_hw *hw;
856 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
857 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 858 int i, err, pci_using_dac;
859 u16 eeprom_data = 0;
860 u16 eeprom_apme_mask = IGB_EEPROM_APME;
861 u32 part_num;
42bfd33a 862 int bars, need_ioport;
9d5c8243 863
42bfd33a
TI		 864 /* do not allocate ioport bars when not needed */
865 need_ioport = igb_is_need_ioport(pdev);
866 if (need_ioport) {
867 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
868 err = pci_enable_device(pdev);
869 } else {
870 bars = pci_select_bars(pdev, IORESOURCE_MEM);
871 err = pci_enable_device_mem(pdev);
872 }
9d5c8243
AK		 873 if (err)
874 return err;
875
876 pci_using_dac = 0;
877 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
878 if (!err) {
879 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
880 if (!err)
881 pci_using_dac = 1;
882 } else {
883 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
884 if (err) {
885 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
886 if (err) {
887 dev_err(&pdev->dev, "No usable DMA "
888 "configuration, aborting\n");
889 goto err_dma;
890 }
891 }
892 }
893
42bfd33a 894 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 895 if (err)
896 goto err_pci_reg;
897
898 pci_set_master(pdev);
c682fc23 899 pci_save_state(pdev);
9d5c8243
AK		 900
901 err = -ENOMEM;
902 netdev = alloc_etherdev(sizeof(struct igb_adapter));
903 if (!netdev)
904 goto err_alloc_etherdev;
905
906 SET_NETDEV_DEV(netdev, &pdev->dev);
907
908 pci_set_drvdata(pdev, netdev);
909 adapter = netdev_priv(netdev);
910 adapter->netdev = netdev;
911 adapter->pdev = pdev;
912 hw = &adapter->hw;
913 hw->back = adapter;
914 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 915 adapter->bars = bars;
916 adapter->need_ioport = need_ioport;
9d5c8243
AK		 917
918 mmio_start = pci_resource_start(pdev, 0);
919 mmio_len = pci_resource_len(pdev, 0);
920
921 err = -EIO;
922 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
923 if (!adapter->hw.hw_addr)
924 goto err_ioremap;
925
926 netdev->open = &igb_open;
927 netdev->stop = &igb_close;
928 netdev->get_stats = &igb_get_stats;
929 netdev->set_multicast_list = &igb_set_multi;
930 netdev->set_mac_address = &igb_set_mac;
931 netdev->change_mtu = &igb_change_mtu;
932 netdev->do_ioctl = &igb_ioctl;
933 igb_set_ethtool_ops(netdev);
934 netdev->tx_timeout = &igb_tx_timeout;
935 netdev->watchdog_timeo = 5 * HZ;
936 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
937 netdev->vlan_rx_register = igb_vlan_rx_register;
938 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
939 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
940#ifdef CONFIG_NET_POLL_CONTROLLER
941 netdev->poll_controller = igb_netpoll;
942#endif
943 netdev->hard_start_xmit = &igb_xmit_frame_adv;
944
945 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
946
947 netdev->mem_start = mmio_start;
948 netdev->mem_end = mmio_start + mmio_len;
949
9d5c8243
AK		 950 /* PCI config space info */
951 hw->vendor_id = pdev->vendor;
952 hw->device_id = pdev->device;
953 hw->revision_id = pdev->revision;
954 hw->subsystem_vendor_id = pdev->subsystem_vendor;
955 hw->subsystem_device_id = pdev->subsystem_device;
956
957 /* setup the private structure */
958 hw->back = adapter;
959 /* Copy the default MAC, PHY and NVM function pointers */
960 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
961 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
962 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
963 /* Initialize skew-specific constants */
964 err = ei->get_invariants(hw);
965 if (err)
966 goto err_hw_init;
967
968 err = igb_sw_init(adapter);
969 if (err)
970 goto err_sw_init;
971
972 igb_get_bus_info_pcie(hw);
973
974 hw->phy.autoneg_wait_to_complete = false;
975 hw->mac.adaptive_ifs = true;
976
977 /* Copper options */
978 if (hw->phy.media_type == e1000_media_type_copper) {
979 hw->phy.mdix = AUTO_ALL_MODES;
980 hw->phy.disable_polarity_correction = false;
981 hw->phy.ms_type = e1000_ms_hw_default;
982 }
983
984 if (igb_check_reset_block(hw))
985 dev_info(&pdev->dev,
986 "PHY reset is blocked due to SOL/IDER session.\n");
987
988 netdev->features = NETIF_F_SG |
989 NETIF_F_HW_CSUM |
990 NETIF_F_HW_VLAN_TX |
991 NETIF_F_HW_VLAN_RX |
992 NETIF_F_HW_VLAN_FILTER;
993
994 netdev->features |= NETIF_F_TSO;
9d5c8243 995 netdev->features |= NETIF_F_TSO6;
48f29ffc
JK		 996
997 netdev->vlan_features |= NETIF_F_TSO;
998 netdev->vlan_features |= NETIF_F_TSO6;
999 netdev->vlan_features |= NETIF_F_HW_CSUM;
1000 netdev->vlan_features |= NETIF_F_SG;
1001
9d5c8243
AK		 1002 if (pci_using_dac)
1003 netdev->features |= NETIF_F_HIGHDMA;
1004
1005 netdev->features |= NETIF_F_LLTX;
1006 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1007
1008 /* before reading the NVM, reset the controller to put the device in a
1009 * known good starting state */
1010 hw->mac.ops.reset_hw(hw);
1011
1012 /* make sure the NVM is good */
1013 if (igb_validate_nvm_checksum(hw) < 0) {
1014 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1015 err = -EIO;
1016 goto err_eeprom;
1017 }
1018
1019 /* copy the MAC address out of the NVM */
1020 if (hw->mac.ops.read_mac_addr(hw))
1021 dev_err(&pdev->dev, "NVM Read Error\n");
1022
1023 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1024 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1025
1026 if (!is_valid_ether_addr(netdev->perm_addr)) {
1027 dev_err(&pdev->dev, "Invalid MAC Address\n");
1028 err = -EIO;
1029 goto err_eeprom;
1030 }
1031
1032 init_timer(&adapter->watchdog_timer);
1033 adapter->watchdog_timer.function = &igb_watchdog;
1034 adapter->watchdog_timer.data = (unsigned long) adapter;
1035
1036 init_timer(&adapter->phy_info_timer);
1037 adapter->phy_info_timer.function = &igb_update_phy_info;
1038 adapter->phy_info_timer.data = (unsigned long) adapter;
1039
1040 INIT_WORK(&adapter->reset_task, igb_reset_task);
1041 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1042
1043 /* Initialize link & ring properties that are user-changeable */
1044 adapter->tx_ring->count = 256;
1045 for (i = 0; i < adapter->num_tx_queues; i++)
1046 adapter->tx_ring[i].count = adapter->tx_ring->count;
1047 adapter->rx_ring->count = 256;
1048 for (i = 0; i < adapter->num_rx_queues; i++)
1049 adapter->rx_ring[i].count = adapter->rx_ring->count;
1050
1051 adapter->fc_autoneg = true;
1052 hw->mac.autoneg = true;
1053 hw->phy.autoneg_advertised = 0x2f;
1054
1055 hw->fc.original_type = e1000_fc_default;
1056 hw->fc.type = e1000_fc_default;
1057
1058 adapter->itr_setting = 3;
1059 adapter->itr = IGB_START_ITR;
1060
1061 igb_validate_mdi_setting(hw);
1062
1063 adapter->rx_csum = 1;
1064
1065 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1066 * enable the ACPI Magic Packet filter
1067 */
1068
1069 if (hw->bus.func == 0 ||
1070 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1071 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1072 &eeprom_data);
1073
1074 if (eeprom_data & eeprom_apme_mask)
1075 adapter->eeprom_wol |= E1000_WUFC_MAG;
1076
1077 /* now that we have the eeprom settings, apply the special cases where
1078 * the eeprom may be wrong or the board simply won't support wake on
1079 * lan on a particular port */
1080 switch (pdev->device) {
1081 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1082 adapter->eeprom_wol = 0;
1083 break;
1084 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1085 /* Wake events only supported on port A for dual fiber
1086 * regardless of eeprom setting */
1087 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1088 adapter->eeprom_wol = 0;
1089 break;
1090 }
1091
1092 /* initialize the wol settings based on the eeprom settings */
1093 adapter->wol = adapter->eeprom_wol;
1094
1095 /* reset the hardware with the new settings */
1096 igb_reset(adapter);
1097
1098 /* let the f/w know that the h/w is now under the control of the
1099 * driver. */
1100 igb_get_hw_control(adapter);
1101
1102 /* tell the stack to leave us alone until igb_open() is called */
1103 netif_carrier_off(netdev);
1104 netif_stop_queue(netdev);
1105
1106 strcpy(netdev->name, "eth%d");
1107 err = register_netdev(netdev);
1108 if (err)
1109 goto err_register;
1110
1111 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1112 /* print bus type/speed/width info */
1113 dev_info(&pdev->dev,
1114 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1115 netdev->name,
1116 ((hw->bus.speed == e1000_bus_speed_2500)
1117 ? "2.5Gb/s" : "unknown"),
1118 ((hw->bus.width == e1000_bus_width_pcie_x4)
1119 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1120 ? "Width x1" : "unknown"),
1121 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1122 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1123
1124 igb_read_part_num(hw, &part_num);
1125 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1126 (part_num >> 8), (part_num & 0xff));
1127
1128 dev_info(&pdev->dev,
1129 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1130 adapter->msix_entries ? "MSI-X" :
1131 adapter->msi_enabled ? "MSI" : "legacy",
1132 adapter->num_rx_queues, adapter->num_tx_queues);
1133
9d5c8243
AK		 1134 return 0;
1135
1136err_register:
1137 igb_release_hw_control(adapter);
1138err_eeprom:
1139 if (!igb_check_reset_block(hw))
1140 hw->phy.ops.reset_phy(hw);
1141
1142 if (hw->flash_address)
1143 iounmap(hw->flash_address);
1144
1145 igb_remove_device(hw);
1146 kfree(adapter->tx_ring);
1147 kfree(adapter->rx_ring);
1148err_sw_init:
1149err_hw_init:
1150 iounmap(hw->hw_addr);
1151err_ioremap:
1152 free_netdev(netdev);
1153err_alloc_etherdev:
42bfd33a 1154 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1155err_pci_reg:
1156err_dma:
1157 pci_disable_device(pdev);
1158 return err;
1159}
1160
1161/**
1162 * igb_remove - Device Removal Routine
1163 * @pdev: PCI device information struct
1164 *
1165 * igb_remove is called by the PCI subsystem to alert the driver
1166 * that it should release a PCI device. The could be caused by a
1167 * Hot-Plug event, or because the driver is going to be removed from
1168 * memory.
1169 **/
1170static void __devexit igb_remove(struct pci_dev *pdev)
1171{
1172 struct net_device *netdev = pci_get_drvdata(pdev);
1173 struct igb_adapter *adapter = netdev_priv(netdev);
1174
1175 /* flush_scheduled work may reschedule our watchdog task, so
1176 * explicitly disable watchdog tasks from being rescheduled */
1177 set_bit(__IGB_DOWN, &adapter->state);
1178 del_timer_sync(&adapter->watchdog_timer);
1179 del_timer_sync(&adapter->phy_info_timer);
1180
1181 flush_scheduled_work();
1182
9d5c8243
AK		 1183 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1184 * would have already happened in close and is redundant. */
1185 igb_release_hw_control(adapter);
1186
1187 unregister_netdev(netdev);
1188
1189 if (!igb_check_reset_block(&adapter->hw))
1190 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1191
1192 igb_remove_device(&adapter->hw);
1193 igb_reset_interrupt_capability(adapter);
1194
1195 kfree(adapter->tx_ring);
1196 kfree(adapter->rx_ring);
1197
1198 iounmap(adapter->hw.hw_addr);
1199 if (adapter->hw.flash_address)
1200 iounmap(adapter->hw.flash_address);
42bfd33a 1201 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1202
1203 free_netdev(netdev);
1204
1205 pci_disable_device(pdev);
1206}
1207
1208/**
1209 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1210 * @adapter: board private structure to initialize
1211 *
1212 * igb_sw_init initializes the Adapter private data structure.
1213 * Fields are initialized based on PCI device information and
1214 * OS network device settings (MTU size).
1215 **/
1216static int __devinit igb_sw_init(struct igb_adapter *adapter)
1217{
1218 struct e1000_hw *hw = &adapter->hw;
1219 struct net_device *netdev = adapter->netdev;
1220 struct pci_dev *pdev = adapter->pdev;
1221
1222 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1223
1224 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1225 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1226 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1227 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1228
1229 /* Number of supported queues. */
1230 /* Having more queues than CPUs doesn't make sense. */
1231 adapter->num_tx_queues = 1;
1232 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1233
1234 igb_set_interrupt_capability(adapter);
1235
1236 if (igb_alloc_queues(adapter)) {
1237 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1238 return -ENOMEM;
1239 }
1240
1241 /* Explicitly disable IRQ since the NIC can be in any state. */
1242 igb_irq_disable(adapter);
1243
1244 set_bit(__IGB_DOWN, &adapter->state);
1245 return 0;
1246}
1247
1248/**
1249 * igb_open - Called when a network interface is made active
1250 * @netdev: network interface device structure
1251 *
1252 * Returns 0 on success, negative value on failure
1253 *
1254 * The open entry point is called when a network interface is made
1255 * active by the system (IFF_UP). At this point all resources needed
1256 * for transmit and receive operations are allocated, the interrupt
1257 * handler is registered with the OS, the watchdog timer is started,
1258 * and the stack is notified that the interface is ready.
1259 **/
1260static int igb_open(struct net_device *netdev)
1261{
1262 struct igb_adapter *adapter = netdev_priv(netdev);
1263 struct e1000_hw *hw = &adapter->hw;
1264 int err;
1265 int i;
1266
1267 /* disallow open during test */
1268 if (test_bit(__IGB_TESTING, &adapter->state))
1269 return -EBUSY;
1270
1271 /* allocate transmit descriptors */
1272 err = igb_setup_all_tx_resources(adapter);
1273 if (err)
1274 goto err_setup_tx;
1275
1276 /* allocate receive descriptors */
1277 err = igb_setup_all_rx_resources(adapter);
1278 if (err)
1279 goto err_setup_rx;
1280
1281 /* e1000_power_up_phy(adapter); */
1282
1283 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1284 if ((adapter->hw.mng_cookie.status &
1285 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1286 igb_update_mng_vlan(adapter);
1287
1288 /* before we allocate an interrupt, we must be ready to handle it.
1289 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1290 * as soon as we call pci_request_irq, so we have to setup our
1291 * clean_rx handler before we do so. */
1292 igb_configure(adapter);
1293
1294 err = igb_request_irq(adapter);
1295 if (err)
1296 goto err_req_irq;
1297
1298 /* From here on the code is the same as igb_up() */
1299 clear_bit(__IGB_DOWN, &adapter->state);
1300
1301 napi_enable(&adapter->napi);
1302 if (adapter->msix_entries)
1303 for (i = 0; i < adapter->num_rx_queues; i++)
1304 napi_enable(&adapter->rx_ring[i].napi);
1305
1306 igb_irq_enable(adapter);
1307
1308 /* Clear any pending interrupts. */
1309 rd32(E1000_ICR);
1310 /* Fire a link status change interrupt to start the watchdog. */
1311 wr32(E1000_ICS, E1000_ICS_LSC);
1312
1313 return 0;
1314
1315err_req_irq:
1316 igb_release_hw_control(adapter);
1317 /* e1000_power_down_phy(adapter); */
1318 igb_free_all_rx_resources(adapter);
1319err_setup_rx:
1320 igb_free_all_tx_resources(adapter);
1321err_setup_tx:
1322 igb_reset(adapter);
1323
1324 return err;
1325}
1326
1327/**
1328 * igb_close - Disables a network interface
1329 * @netdev: network interface device structure
1330 *
1331 * Returns 0, this is not allowed to fail
1332 *
1333 * The close entry point is called when an interface is de-activated
1334 * by the OS. The hardware is still under the driver's control, but
1335 * needs to be disabled. A global MAC reset is issued to stop the
1336 * hardware, and all transmit and receive resources are freed.
1337 **/
1338static int igb_close(struct net_device *netdev)
1339{
1340 struct igb_adapter *adapter = netdev_priv(netdev);
1341
1342 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1343 igb_down(adapter);
1344
1345 igb_free_irq(adapter);
1346
1347 igb_free_all_tx_resources(adapter);
1348 igb_free_all_rx_resources(adapter);
1349
1350 /* kill manageability vlan ID if supported, but not if a vlan with
1351 * the same ID is registered on the host OS (let 8021q kill it) */
1352 if ((adapter->hw.mng_cookie.status &
1353 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1354 !(adapter->vlgrp &&
1355 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1356 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1357
1358 return 0;
1359}
1360
1361/**
1362 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1363 * @adapter: board private structure
1364 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1365 *
1366 * Return 0 on success, negative on failure
1367 **/
1368
1369int igb_setup_tx_resources(struct igb_adapter *adapter,
1370 struct igb_ring *tx_ring)
1371{
1372 struct pci_dev *pdev = adapter->pdev;
1373 int size;
1374
1375 size = sizeof(struct igb_buffer) * tx_ring->count;
1376 tx_ring->buffer_info = vmalloc(size);
1377 if (!tx_ring->buffer_info)
1378 goto err;
1379 memset(tx_ring->buffer_info, 0, size);
1380
1381 /* round up to nearest 4K */
1382 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1383 + sizeof(u32);
1384 tx_ring->size = ALIGN(tx_ring->size, 4096);
1385
1386 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1387 &tx_ring->dma);
1388
1389 if (!tx_ring->desc)
1390 goto err;
1391
1392 tx_ring->adapter = adapter;
1393 tx_ring->next_to_use = 0;
1394 tx_ring->next_to_clean = 0;
1395 spin_lock_init(&tx_ring->tx_clean_lock);
1396 spin_lock_init(&tx_ring->tx_lock);
1397 return 0;
1398
1399err:
1400 vfree(tx_ring->buffer_info);
1401 dev_err(&adapter->pdev->dev,
1402 "Unable to allocate memory for the transmit descriptor ring\n");
1403 return -ENOMEM;
1404}
1405
1406/**
1407 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1408 * (Descriptors) for all queues
1409 * @adapter: board private structure
1410 *
1411 * Return 0 on success, negative on failure
1412 **/
1413static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1414{
1415 int i, err = 0;
1416
1417 for (i = 0; i < adapter->num_tx_queues; i++) {
1418 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1419 if (err) {
1420 dev_err(&adapter->pdev->dev,
1421 "Allocation for Tx Queue %u failed\n", i);
1422 for (i--; i >= 0; i--)
3b644cf6 1423 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1424 break;
1425 }
1426 }
1427
1428 return err;
1429}
1430
1431/**
1432 * igb_configure_tx - Configure transmit Unit after Reset
1433 * @adapter: board private structure
1434 *
1435 * Configure the Tx unit of the MAC after a reset.
1436 **/
1437static void igb_configure_tx(struct igb_adapter *adapter)
1438{
1439 u64 tdba, tdwba;
1440 struct e1000_hw *hw = &adapter->hw;
1441 u32 tctl;
1442 u32 txdctl, txctrl;
1443 int i;
1444
1445 for (i = 0; i < adapter->num_tx_queues; i++) {
1446 struct igb_ring *ring = &(adapter->tx_ring[i]);
1447
1448 wr32(E1000_TDLEN(i),
1449 ring->count * sizeof(struct e1000_tx_desc));
1450 tdba = ring->dma;
1451 wr32(E1000_TDBAL(i),
1452 tdba & 0x00000000ffffffffULL);
1453 wr32(E1000_TDBAH(i), tdba >> 32);
1454
1455 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1456 tdwba |= 1; /* enable head wb */
1457 wr32(E1000_TDWBAL(i),
1458 tdwba & 0x00000000ffffffffULL);
1459 wr32(E1000_TDWBAH(i), tdwba >> 32);
1460
1461 ring->head = E1000_TDH(i);
1462 ring->tail = E1000_TDT(i);
1463 writel(0, hw->hw_addr + ring->tail);
1464 writel(0, hw->hw_addr + ring->head);
1465 txdctl = rd32(E1000_TXDCTL(i));
1466 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1467 wr32(E1000_TXDCTL(i), txdctl);
1468
1469 /* Turn off Relaxed Ordering on head write-backs. The
1470 * writebacks MUST be delivered in order or it will
1471 * completely screw up our bookeeping.
1472 */
1473 txctrl = rd32(E1000_DCA_TXCTRL(i));
1474 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1475 wr32(E1000_DCA_TXCTRL(i), txctrl);
1476 }
1477
1478
1479
1480 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1481
1482 /* Program the Transmit Control Register */
1483
1484 tctl = rd32(E1000_TCTL);
1485 tctl &= ~E1000_TCTL_CT;
1486 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1487 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1488
1489 igb_config_collision_dist(hw);
1490
1491 /* Setup Transmit Descriptor Settings for eop descriptor */
1492 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1493
1494 /* Enable transmits */
1495 tctl |= E1000_TCTL_EN;
1496
1497 wr32(E1000_TCTL, tctl);
1498}
1499
1500/**
1501 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1502 * @adapter: board private structure
1503 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1504 *
1505 * Returns 0 on success, negative on failure
1506 **/
1507
1508int igb_setup_rx_resources(struct igb_adapter *adapter,
1509 struct igb_ring *rx_ring)
1510{
1511 struct pci_dev *pdev = adapter->pdev;
1512 int size, desc_len;
1513
1514 size = sizeof(struct igb_buffer) * rx_ring->count;
1515 rx_ring->buffer_info = vmalloc(size);
1516 if (!rx_ring->buffer_info)
1517 goto err;
1518 memset(rx_ring->buffer_info, 0, size);
1519
1520 desc_len = sizeof(union e1000_adv_rx_desc);
1521
1522 /* Round up to nearest 4K */
1523 rx_ring->size = rx_ring->count * desc_len;
1524 rx_ring->size = ALIGN(rx_ring->size, 4096);
1525
1526 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1527 &rx_ring->dma);
1528
1529 if (!rx_ring->desc)
1530 goto err;
1531
1532 rx_ring->next_to_clean = 0;
1533 rx_ring->next_to_use = 0;
1534 rx_ring->pending_skb = NULL;
1535
1536 rx_ring->adapter = adapter;
1537 /* FIXME: do we want to setup ring->napi->poll here? */
1538 rx_ring->napi.poll = adapter->napi.poll;
1539
1540 return 0;
1541
1542err:
1543 vfree(rx_ring->buffer_info);
1544 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1545 "the receive descriptor ring\n");
1546 return -ENOMEM;
1547}
1548
1549/**
1550 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1551 * (Descriptors) for all queues
1552 * @adapter: board private structure
1553 *
1554 * Return 0 on success, negative on failure
1555 **/
1556static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1557{
1558 int i, err = 0;
1559
1560 for (i = 0; i < adapter->num_rx_queues; i++) {
1561 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1562 if (err) {
1563 dev_err(&adapter->pdev->dev,
1564 "Allocation for Rx Queue %u failed\n", i);
1565 for (i--; i >= 0; i--)
3b644cf6 1566 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1567 break;
1568 }
1569 }
1570
1571 return err;
1572}
1573
1574/**
1575 * igb_setup_rctl - configure the receive control registers
1576 * @adapter: Board private structure
1577 **/
1578static void igb_setup_rctl(struct igb_adapter *adapter)
1579{
1580 struct e1000_hw *hw = &adapter->hw;
1581 u32 rctl;
1582 u32 srrctl = 0;
1583 int i;
1584
1585 rctl = rd32(E1000_RCTL);
1586
1587 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1588
1589 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1590 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1591 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1592
1593 /* disable the stripping of CRC because it breaks
1594 * BMC firmware connected over SMBUS
1595 rctl |= E1000_RCTL_SECRC;
1596 */
1597
1598 rctl &= ~E1000_RCTL_SBP;
1599
1600 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1601 rctl &= ~E1000_RCTL_LPE;
1602 else
1603 rctl |= E1000_RCTL_LPE;
1604 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1605 /* Setup buffer sizes */
1606 rctl &= ~E1000_RCTL_SZ_4096;
1607 rctl |= E1000_RCTL_BSEX;
1608 switch (adapter->rx_buffer_len) {
1609 case IGB_RXBUFFER_256:
1610 rctl |= E1000_RCTL_SZ_256;
1611 rctl &= ~E1000_RCTL_BSEX;
1612 break;
1613 case IGB_RXBUFFER_512:
1614 rctl |= E1000_RCTL_SZ_512;
1615 rctl &= ~E1000_RCTL_BSEX;
1616 break;
1617 case IGB_RXBUFFER_1024:
1618 rctl |= E1000_RCTL_SZ_1024;
1619 rctl &= ~E1000_RCTL_BSEX;
1620 break;
1621 case IGB_RXBUFFER_2048:
1622 default:
1623 rctl |= E1000_RCTL_SZ_2048;
1624 rctl &= ~E1000_RCTL_BSEX;
1625 break;
1626 case IGB_RXBUFFER_4096:
1627 rctl |= E1000_RCTL_SZ_4096;
1628 break;
1629 case IGB_RXBUFFER_8192:
1630 rctl |= E1000_RCTL_SZ_8192;
1631 break;
1632 case IGB_RXBUFFER_16384:
1633 rctl |= E1000_RCTL_SZ_16384;
1634 break;
1635 }
1636 } else {
1637 rctl &= ~E1000_RCTL_BSEX;
1638 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1639 }
1640
1641 /* 82575 and greater support packet-split where the protocol
1642 * header is placed in skb->data and the packet data is
1643 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1644 * In the case of a non-split, skb->data is linearly filled,
1645 * followed by the page buffers. Therefore, skb->data is
1646 * sized to hold the largest protocol header.
1647 */
1648 /* allocations using alloc_page take too long for regular MTU
1649 * so only enable packet split for jumbo frames */
1650 if (rctl & E1000_RCTL_LPE) {
1651 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1652 srrctl = adapter->rx_ps_hdr_size <<
1653 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1654 /* buffer size is ALWAYS one page */
1655 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1656 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1657 } else {
1658 adapter->rx_ps_hdr_size = 0;
1659 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1660 }
1661
1662 for (i = 0; i < adapter->num_rx_queues; i++)
1663 wr32(E1000_SRRCTL(i), srrctl);
1664
1665 wr32(E1000_RCTL, rctl);
1666}
1667
1668/**
1669 * igb_configure_rx - Configure receive Unit after Reset
1670 * @adapter: board private structure
1671 *
1672 * Configure the Rx unit of the MAC after a reset.
1673 **/
1674static void igb_configure_rx(struct igb_adapter *adapter)
1675{
1676 u64 rdba;
1677 struct e1000_hw *hw = &adapter->hw;
1678 u32 rctl, rxcsum;
1679 u32 rxdctl;
1680 int i;
1681
1682 /* disable receives while setting up the descriptors */
1683 rctl = rd32(E1000_RCTL);
1684 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1685 wrfl();
1686 mdelay(10);
1687
1688 if (adapter->itr_setting > 3)
1689 wr32(E1000_ITR,
1690 1000000000 / (adapter->itr * 256));
1691
1692 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1693 * the Base and Length of the Rx Descriptor Ring */
1694 for (i = 0; i < adapter->num_rx_queues; i++) {
1695 struct igb_ring *ring = &(adapter->rx_ring[i]);
1696 rdba = ring->dma;
1697 wr32(E1000_RDBAL(i),
1698 rdba & 0x00000000ffffffffULL);
1699 wr32(E1000_RDBAH(i), rdba >> 32);
1700 wr32(E1000_RDLEN(i),
1701 ring->count * sizeof(union e1000_adv_rx_desc));
1702
1703 ring->head = E1000_RDH(i);
1704 ring->tail = E1000_RDT(i);
1705 writel(0, hw->hw_addr + ring->tail);
1706 writel(0, hw->hw_addr + ring->head);
1707
1708 rxdctl = rd32(E1000_RXDCTL(i));
1709 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1710 rxdctl &= 0xFFF00000;
1711 rxdctl |= IGB_RX_PTHRESH;
1712 rxdctl |= IGB_RX_HTHRESH << 8;
1713 rxdctl |= IGB_RX_WTHRESH << 16;
1714 wr32(E1000_RXDCTL(i), rxdctl);
1715 }
1716
1717 if (adapter->num_rx_queues > 1) {
1718 u32 random[10];
1719 u32 mrqc;
1720 u32 j, shift;
1721 union e1000_reta {
1722 u32 dword;
1723 u8 bytes[4];
1724 } reta;
1725
1726 get_random_bytes(&random[0], 40);
1727
1728 shift = 6;
1729 for (j = 0; j < (32 * 4); j++) {
1730 reta.bytes[j & 3] =
1731 (j % adapter->num_rx_queues) << shift;
1732 if ((j & 3) == 3)
1733 writel(reta.dword,
1734 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1735 }
1736 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1737
1738 /* Fill out hash function seeds */
1739 for (j = 0; j < 10; j++)
1740 array_wr32(E1000_RSSRK(0), j, random[j]);
1741
1742 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1743 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1744 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1745 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1746 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1747 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1748 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1749 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1750
1751
1752 wr32(E1000_MRQC, mrqc);
1753
1754 /* Multiqueue and raw packet checksumming are mutually
1755 * exclusive. Note that this not the same as TCP/IP
1756 * checksumming, which works fine. */
1757 rxcsum = rd32(E1000_RXCSUM);
1758 rxcsum |= E1000_RXCSUM_PCSD;
1759 wr32(E1000_RXCSUM, rxcsum);
1760 } else {
1761 /* Enable Receive Checksum Offload for TCP and UDP */
1762 rxcsum = rd32(E1000_RXCSUM);
1763 if (adapter->rx_csum) {
1764 rxcsum |= E1000_RXCSUM_TUOFL;
1765
1766 /* Enable IPv4 payload checksum for UDP fragments
1767 * Must be used in conjunction with packet-split. */
1768 if (adapter->rx_ps_hdr_size)
1769 rxcsum |= E1000_RXCSUM_IPPCSE;
1770 } else {
1771 rxcsum &= ~E1000_RXCSUM_TUOFL;
1772 /* don't need to clear IPPCSE as it defaults to 0 */
1773 }
1774 wr32(E1000_RXCSUM, rxcsum);
1775 }
1776
1777 if (adapter->vlgrp)
1778 wr32(E1000_RLPML,
1779 adapter->max_frame_size + VLAN_TAG_SIZE);
1780 else
1781 wr32(E1000_RLPML, adapter->max_frame_size);
1782
1783 /* Enable Receives */
1784 wr32(E1000_RCTL, rctl);
1785}
1786
1787/**
1788 * igb_free_tx_resources - Free Tx Resources per Queue
1789 * @adapter: board private structure
1790 * @tx_ring: Tx descriptor ring for a specific queue
1791 *
1792 * Free all transmit software resources
1793 **/
3b644cf6 1794static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1795{
3b644cf6 1796 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1797
3b644cf6 1798 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1799
1800 vfree(tx_ring->buffer_info);
1801 tx_ring->buffer_info = NULL;
1802
1803 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1804
1805 tx_ring->desc = NULL;
1806}
1807
1808/**
1809 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1810 * @adapter: board private structure
1811 *
1812 * Free all transmit software resources
1813 **/
1814static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1815{
1816 int i;
1817
1818 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1819 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1820}
1821
1822static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1823 struct igb_buffer *buffer_info)
1824{
1825 if (buffer_info->dma) {
1826 pci_unmap_page(adapter->pdev,
1827 buffer_info->dma,
1828 buffer_info->length,
1829 PCI_DMA_TODEVICE);
1830 buffer_info->dma = 0;
1831 }
1832 if (buffer_info->skb) {
1833 dev_kfree_skb_any(buffer_info->skb);
1834 buffer_info->skb = NULL;
1835 }
1836 buffer_info->time_stamp = 0;
1837 /* buffer_info must be completely set up in the transmit path */
1838}
1839
1840/**
1841 * igb_clean_tx_ring - Free Tx Buffers
1842 * @adapter: board private structure
1843 * @tx_ring: ring to be cleaned
1844 **/
3b644cf6 1845static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 1846{
3b644cf6 1847 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 1848 struct igb_buffer *buffer_info;
1849 unsigned long size;
1850 unsigned int i;
1851
1852 if (!tx_ring->buffer_info)
1853 return;
1854 /* Free all the Tx ring sk_buffs */
1855
1856 for (i = 0; i < tx_ring->count; i++) {
1857 buffer_info = &tx_ring->buffer_info[i];
1858 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1859 }
1860
1861 size = sizeof(struct igb_buffer) * tx_ring->count;
1862 memset(tx_ring->buffer_info, 0, size);
1863
1864 /* Zero out the descriptor ring */
1865
1866 memset(tx_ring->desc, 0, tx_ring->size);
1867
1868 tx_ring->next_to_use = 0;
1869 tx_ring->next_to_clean = 0;
1870
1871 writel(0, adapter->hw.hw_addr + tx_ring->head);
1872 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1873}
1874
1875/**
1876 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1877 * @adapter: board private structure
1878 **/
1879static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1880{
1881 int i;
1882
1883 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1884 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 1885}
1886
1887/**
1888 * igb_free_rx_resources - Free Rx Resources
1889 * @adapter: board private structure
1890 * @rx_ring: ring to clean the resources from
1891 *
1892 * Free all receive software resources
1893 **/
3b644cf6 1894static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 1895{
3b644cf6 1896 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 1897
3b644cf6 1898 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 1899
1900 vfree(rx_ring->buffer_info);
1901 rx_ring->buffer_info = NULL;
1902
1903 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1904
1905 rx_ring->desc = NULL;
1906}
1907
1908/**
1909 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1910 * @adapter: board private structure
1911 *
1912 * Free all receive software resources
1913 **/
1914static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1915{
1916 int i;
1917
1918 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 1919 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1920}
1921
1922/**
1923 * igb_clean_rx_ring - Free Rx Buffers per Queue
1924 * @adapter: board private structure
1925 * @rx_ring: ring to free buffers from
1926 **/
3b644cf6 1927static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 1928{
3b644cf6 1929 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 1930 struct igb_buffer *buffer_info;
1931 struct pci_dev *pdev = adapter->pdev;
1932 unsigned long size;
1933 unsigned int i;
1934
1935 if (!rx_ring->buffer_info)
1936 return;
1937 /* Free all the Rx ring sk_buffs */
1938 for (i = 0; i < rx_ring->count; i++) {
1939 buffer_info = &rx_ring->buffer_info[i];
1940 if (buffer_info->dma) {
1941 if (adapter->rx_ps_hdr_size)
1942 pci_unmap_single(pdev, buffer_info->dma,
1943 adapter->rx_ps_hdr_size,
1944 PCI_DMA_FROMDEVICE);
1945 else
1946 pci_unmap_single(pdev, buffer_info->dma,
1947 adapter->rx_buffer_len,
1948 PCI_DMA_FROMDEVICE);
1949 buffer_info->dma = 0;
1950 }
1951
1952 if (buffer_info->skb) {
1953 dev_kfree_skb(buffer_info->skb);
1954 buffer_info->skb = NULL;
1955 }
1956 if (buffer_info->page) {
1957 pci_unmap_page(pdev, buffer_info->page_dma,
1958 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1959 put_page(buffer_info->page);
1960 buffer_info->page = NULL;
1961 buffer_info->page_dma = 0;
1962 }
1963 }
1964
1965 /* there also may be some cached data from a chained receive */
1966 if (rx_ring->pending_skb) {
1967 dev_kfree_skb(rx_ring->pending_skb);
1968 rx_ring->pending_skb = NULL;
1969 }
1970
1971 size = sizeof(struct igb_buffer) * rx_ring->count;
1972 memset(rx_ring->buffer_info, 0, size);
1973
1974 /* Zero out the descriptor ring */
1975 memset(rx_ring->desc, 0, rx_ring->size);
1976
1977 rx_ring->next_to_clean = 0;
1978 rx_ring->next_to_use = 0;
1979
1980 writel(0, adapter->hw.hw_addr + rx_ring->head);
1981 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1982}
1983
1984/**
1985 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1986 * @adapter: board private structure
1987 **/
1988static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1989{
1990 int i;
1991
1992 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 1993 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 1994}
1995
1996/**
1997 * igb_set_mac - Change the Ethernet Address of the NIC
1998 * @netdev: network interface device structure
1999 * @p: pointer to an address structure
2000 *
2001 * Returns 0 on success, negative on failure
2002 **/
2003static int igb_set_mac(struct net_device *netdev, void *p)
2004{
2005 struct igb_adapter *adapter = netdev_priv(netdev);
2006 struct sockaddr *addr = p;
2007
2008 if (!is_valid_ether_addr(addr->sa_data))
2009 return -EADDRNOTAVAIL;
2010
2011 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2012 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2013
2014 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2015
2016 return 0;
2017}
2018
2019/**
2020 * igb_set_multi - Multicast and Promiscuous mode set
2021 * @netdev: network interface device structure
2022 *
2023 * The set_multi entry point is called whenever the multicast address
2024 * list or the network interface flags are updated. This routine is
2025 * responsible for configuring the hardware for proper multicast,
2026 * promiscuous mode, and all-multi behavior.
2027 **/
2028static void igb_set_multi(struct net_device *netdev)
2029{
2030 struct igb_adapter *adapter = netdev_priv(netdev);
2031 struct e1000_hw *hw = &adapter->hw;
2032 struct e1000_mac_info *mac = &hw->mac;
2033 struct dev_mc_list *mc_ptr;
2034 u8 *mta_list;
2035 u32 rctl;
2036 int i;
2037
2038 /* Check for Promiscuous and All Multicast modes */
2039
2040 rctl = rd32(E1000_RCTL);
2041
2042 if (netdev->flags & IFF_PROMISC)
2043 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2044 else if (netdev->flags & IFF_ALLMULTI) {
2045 rctl |= E1000_RCTL_MPE;
2046 rctl &= ~E1000_RCTL_UPE;
2047 } else
2048 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2049
2050 wr32(E1000_RCTL, rctl);
2051
2052 if (!netdev->mc_count) {
2053 /* nothing to program, so clear mc list */
2054 igb_update_mc_addr_list(hw, NULL, 0, 1,
2055 mac->rar_entry_count);
2056 return;
2057 }
2058
2059 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2060 if (!mta_list)
2061 return;
2062
2063 /* The shared function expects a packed array of only addresses. */
2064 mc_ptr = netdev->mc_list;
2065
2066 for (i = 0; i < netdev->mc_count; i++) {
2067 if (!mc_ptr)
2068 break;
2069 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2070 mc_ptr = mc_ptr->next;
2071 }
2072 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2073 kfree(mta_list);
2074}
2075
2076/* Need to wait a few seconds after link up to get diagnostic information from
2077 * the phy */
2078static void igb_update_phy_info(unsigned long data)
2079{
2080 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2081 if (adapter->hw.phy.ops.get_phy_info)
2082 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2083}
2084
2085/**
2086 * igb_watchdog - Timer Call-back
2087 * @data: pointer to adapter cast into an unsigned long
2088 **/
2089static void igb_watchdog(unsigned long data)
2090{
2091 struct igb_adapter *adapter = (struct igb_adapter *)data;
2092 /* Do the rest outside of interrupt context */
2093 schedule_work(&adapter->watchdog_task);
2094}
2095
2096static void igb_watchdog_task(struct work_struct *work)
2097{
2098 struct igb_adapter *adapter = container_of(work,
2099 struct igb_adapter, watchdog_task);
2100 struct e1000_hw *hw = &adapter->hw;
2101
2102 struct net_device *netdev = adapter->netdev;
2103 struct igb_ring *tx_ring = adapter->tx_ring;
2104 struct e1000_mac_info *mac = &adapter->hw.mac;
2105 u32 link;
2106 s32 ret_val;
2107
2108 if ((netif_carrier_ok(netdev)) &&
2109 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2110 goto link_up;
2111
2112 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2113 if ((ret_val == E1000_ERR_PHY) &&
2114 (hw->phy.type == e1000_phy_igp_3) &&
2115 (rd32(E1000_CTRL) &
2116 E1000_PHY_CTRL_GBE_DISABLE))
2117 dev_info(&adapter->pdev->dev,
2118 "Gigabit has been disabled, downgrading speed\n");
2119
2120 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2121 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2122 link = mac->serdes_has_link;
2123 else
2124 link = rd32(E1000_STATUS) &
2125 E1000_STATUS_LU;
2126
2127 if (link) {
2128 if (!netif_carrier_ok(netdev)) {
2129 u32 ctrl;
2130 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2131 &adapter->link_speed,
2132 &adapter->link_duplex);
2133
2134 ctrl = rd32(E1000_CTRL);
2135 dev_info(&adapter->pdev->dev,
2136 "NIC Link is Up %d Mbps %s, "
2137 "Flow Control: %s\n",
2138 adapter->link_speed,
2139 adapter->link_duplex == FULL_DUPLEX ?
2140 "Full Duplex" : "Half Duplex",
2141 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2142 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2143 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2144 E1000_CTRL_TFCE) ? "TX" : "None")));
2145
2146 /* tweak tx_queue_len according to speed/duplex and
2147 * adjust the timeout factor */
2148 netdev->tx_queue_len = adapter->tx_queue_len;
2149 adapter->tx_timeout_factor = 1;
2150 switch (adapter->link_speed) {
2151 case SPEED_10:
2152 netdev->tx_queue_len = 10;
2153 adapter->tx_timeout_factor = 14;
2154 break;
2155 case SPEED_100:
2156 netdev->tx_queue_len = 100;
2157 /* maybe add some timeout factor ? */
2158 break;
2159 }
2160
2161 netif_carrier_on(netdev);
2162 netif_wake_queue(netdev);
2163
2164 if (!test_bit(__IGB_DOWN, &adapter->state))
2165 mod_timer(&adapter->phy_info_timer,
2166 round_jiffies(jiffies + 2 * HZ));
2167 }
2168 } else {
2169 if (netif_carrier_ok(netdev)) {
2170 adapter->link_speed = 0;
2171 adapter->link_duplex = 0;
2172 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2173 netif_carrier_off(netdev);
2174 netif_stop_queue(netdev);
2175 if (!test_bit(__IGB_DOWN, &adapter->state))
2176 mod_timer(&adapter->phy_info_timer,
2177 round_jiffies(jiffies + 2 * HZ));
2178 }
2179 }
2180
2181link_up:
2182 igb_update_stats(adapter);
2183
2184 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2185 adapter->tpt_old = adapter->stats.tpt;
2186 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2187 adapter->colc_old = adapter->stats.colc;
2188
2189 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2190 adapter->gorc_old = adapter->stats.gorc;
2191 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2192 adapter->gotc_old = adapter->stats.gotc;
2193
2194 igb_update_adaptive(&adapter->hw);
2195
2196 if (!netif_carrier_ok(netdev)) {
2197 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2198 /* We've lost link, so the controller stops DMA,
2199 * but we've got queued Tx work that's never going
2200 * to get done, so reset controller to flush Tx.
2201 * (Do the reset outside of interrupt context). */
2202 adapter->tx_timeout_count++;
2203 schedule_work(&adapter->reset_task);
2204 }
2205 }
2206
2207 /* Cause software interrupt to ensure rx ring is cleaned */
2208 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2209
2210 /* Force detection of hung controller every watchdog period */
2211 tx_ring->detect_tx_hung = true;
2212
2213 /* Reset the timer */
2214 if (!test_bit(__IGB_DOWN, &adapter->state))
2215 mod_timer(&adapter->watchdog_timer,
2216 round_jiffies(jiffies + 2 * HZ));
2217}
2218
2219enum latency_range {
2220 lowest_latency = 0,
2221 low_latency = 1,
2222 bulk_latency = 2,
2223 latency_invalid = 255
2224};
2225
2226
2227static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2228 struct igb_ring *rx_ring)
2229{
2230 struct e1000_hw *hw = &adapter->hw;
2231 int new_val;
2232
2233 new_val = rx_ring->itr_val / 2;
2234 if (new_val < IGB_MIN_DYN_ITR)
2235 new_val = IGB_MIN_DYN_ITR;
2236
2237 if (new_val != rx_ring->itr_val) {
2238 rx_ring->itr_val = new_val;
2239 wr32(rx_ring->itr_register,
2240 1000000000 / (new_val * 256));
2241 }
2242}
2243
2244static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2245 struct igb_ring *rx_ring)
2246{
2247 struct e1000_hw *hw = &adapter->hw;
2248 int new_val;
2249
2250 new_val = rx_ring->itr_val * 2;
2251 if (new_val > IGB_MAX_DYN_ITR)
2252 new_val = IGB_MAX_DYN_ITR;
2253
2254 if (new_val != rx_ring->itr_val) {
2255 rx_ring->itr_val = new_val;
2256 wr32(rx_ring->itr_register,
2257 1000000000 / (new_val * 256));
2258 }
2259}
2260
2261/**
2262 * igb_update_itr - update the dynamic ITR value based on statistics
2263 * Stores a new ITR value based on packets and byte
2264 * counts during the last interrupt. The advantage of per interrupt
2265 * computation is faster updates and more accurate ITR for the current
2266 * traffic pattern. Constants in this function were computed
2267 * based on theoretical maximum wire speed and thresholds were set based
2268 * on testing data as well as attempting to minimize response time
2269 * while increasing bulk throughput.
2270 * this functionality is controlled by the InterruptThrottleRate module
2271 * parameter (see igb_param.c)
2272 * NOTE: These calculations are only valid when operating in a single-
2273 * queue environment.
2274 * @adapter: pointer to adapter
2275 * @itr_setting: current adapter->itr
2276 * @packets: the number of packets during this measurement interval
2277 * @bytes: the number of bytes during this measurement interval
2278 **/
2279static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2280 int packets, int bytes)
2281{
2282 unsigned int retval = itr_setting;
2283
2284 if (packets == 0)
2285 goto update_itr_done;
2286
2287 switch (itr_setting) {
2288 case lowest_latency:
2289 /* handle TSO and jumbo frames */
2290 if (bytes/packets > 8000)
2291 retval = bulk_latency;
2292 else if ((packets < 5) && (bytes > 512))
2293 retval = low_latency;
2294 break;
2295 case low_latency: /* 50 usec aka 20000 ints/s */
2296 if (bytes > 10000) {
2297 /* this if handles the TSO accounting */
2298 if (bytes/packets > 8000) {
2299 retval = bulk_latency;
2300 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2301 retval = bulk_latency;
2302 } else if ((packets > 35)) {
2303 retval = lowest_latency;
2304 }
2305 } else if (bytes/packets > 2000) {
2306 retval = bulk_latency;
2307 } else if (packets <= 2 && bytes < 512) {
2308 retval = lowest_latency;
2309 }
2310 break;
2311 case bulk_latency: /* 250 usec aka 4000 ints/s */
2312 if (bytes > 25000) {
2313 if (packets > 35)
2314 retval = low_latency;
2315 } else if (bytes < 6000) {
2316 retval = low_latency;
2317 }
2318 break;
2319 }
2320
2321update_itr_done:
2322 return retval;
2323}
2324
2325static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2326 int rx_only)
2327{
2328 u16 current_itr;
2329 u32 new_itr = adapter->itr;
2330
2331 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2332 if (adapter->link_speed != SPEED_1000) {
2333 current_itr = 0;
2334 new_itr = 4000;
2335 goto set_itr_now;
2336 }
2337
2338 adapter->rx_itr = igb_update_itr(adapter,
2339 adapter->rx_itr,
2340 adapter->rx_ring->total_packets,
2341 adapter->rx_ring->total_bytes);
2342 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2343 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2344 adapter->rx_itr = low_latency;
2345
2346 if (!rx_only) {
2347 adapter->tx_itr = igb_update_itr(adapter,
2348 adapter->tx_itr,
2349 adapter->tx_ring->total_packets,
2350 adapter->tx_ring->total_bytes);
2351 /* conservative mode (itr 3) eliminates the
2352 * lowest_latency setting */
2353 if (adapter->itr_setting == 3 &&
2354 adapter->tx_itr == lowest_latency)
2355 adapter->tx_itr = low_latency;
2356
2357 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2358 } else {
2359 current_itr = adapter->rx_itr;
2360 }
2361
2362 switch (current_itr) {
2363 /* counts and packets in update_itr are dependent on these numbers */
2364 case lowest_latency:
2365 new_itr = 70000;
2366 break;
2367 case low_latency:
2368 new_itr = 20000; /* aka hwitr = ~200 */
2369 break;
2370 case bulk_latency:
2371 new_itr = 4000;
2372 break;
2373 default:
2374 break;
2375 }
2376
2377set_itr_now:
2378 if (new_itr != adapter->itr) {
2379 /* this attempts to bias the interrupt rate towards Bulk
2380 * by adding intermediate steps when interrupt rate is
2381 * increasing */
2382 new_itr = new_itr > adapter->itr ?
2383 min(adapter->itr + (new_itr >> 2), new_itr) :
2384 new_itr;
2385 /* Don't write the value here; it resets the adapter's
2386 * internal timer, and causes us to delay far longer than
2387 * we should between interrupts. Instead, we write the ITR
2388 * value at the beginning of the next interrupt so the timing
2389 * ends up being correct.
2390 */
2391 adapter->itr = new_itr;
2392 adapter->set_itr = 1;
2393 }
2394
2395 return;
2396}
2397
2398
2399#define IGB_TX_FLAGS_CSUM 0x00000001
2400#define IGB_TX_FLAGS_VLAN 0x00000002
2401#define IGB_TX_FLAGS_TSO 0x00000004
2402#define IGB_TX_FLAGS_IPV4 0x00000008
2403#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2404#define IGB_TX_FLAGS_VLAN_SHIFT 16
2405
2406static inline int igb_tso_adv(struct igb_adapter *adapter,
2407 struct igb_ring *tx_ring,
2408 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2409{
2410 struct e1000_adv_tx_context_desc *context_desc;
2411 unsigned int i;
2412 int err;
2413 struct igb_buffer *buffer_info;
2414 u32 info = 0, tu_cmd = 0;
2415 u32 mss_l4len_idx, l4len;
2416 *hdr_len = 0;
2417
2418 if (skb_header_cloned(skb)) {
2419 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2420 if (err)
2421 return err;
2422 }
2423
2424 l4len = tcp_hdrlen(skb);
2425 *hdr_len += l4len;
2426
2427 if (skb->protocol == htons(ETH_P_IP)) {
2428 struct iphdr *iph = ip_hdr(skb);
2429 iph->tot_len = 0;
2430 iph->check = 0;
2431 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2432 iph->daddr, 0,
2433 IPPROTO_TCP,
2434 0);
2435 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2436 ipv6_hdr(skb)->payload_len = 0;
2437 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2438 &ipv6_hdr(skb)->daddr,
2439 0, IPPROTO_TCP, 0);
2440 }
2441
2442 i = tx_ring->next_to_use;
2443
2444 buffer_info = &tx_ring->buffer_info[i];
2445 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2446 /* VLAN MACLEN IPLEN */
2447 if (tx_flags & IGB_TX_FLAGS_VLAN)
2448 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2449 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2450 *hdr_len += skb_network_offset(skb);
2451 info |= skb_network_header_len(skb);
2452 *hdr_len += skb_network_header_len(skb);
2453 context_desc->vlan_macip_lens = cpu_to_le32(info);
2454
2455 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2456 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2457
2458 if (skb->protocol == htons(ETH_P_IP))
2459 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2460 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2461
2462 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2463
2464 /* MSS L4LEN IDX */
2465 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2466 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2467
2468 /* Context index must be unique per ring. Luckily, so is the interrupt
2469 * mask value. */
2470 mss_l4len_idx |= tx_ring->eims_value >> 4;
2471
2472 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2473 context_desc->seqnum_seed = 0;
2474
2475 buffer_info->time_stamp = jiffies;
2476 buffer_info->dma = 0;
2477 i++;
2478 if (i == tx_ring->count)
2479 i = 0;
2480
2481 tx_ring->next_to_use = i;
2482
2483 return true;
2484}
2485
2486static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2487 struct igb_ring *tx_ring,
2488 struct sk_buff *skb, u32 tx_flags)
2489{
2490 struct e1000_adv_tx_context_desc *context_desc;
2491 unsigned int i;
2492 struct igb_buffer *buffer_info;
2493 u32 info = 0, tu_cmd = 0;
2494
2495 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2496 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2497 i = tx_ring->next_to_use;
2498 buffer_info = &tx_ring->buffer_info[i];
2499 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2500
2501 if (tx_flags & IGB_TX_FLAGS_VLAN)
2502 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2503 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2504 if (skb->ip_summed == CHECKSUM_PARTIAL)
2505 info |= skb_network_header_len(skb);
2506
2507 context_desc->vlan_macip_lens = cpu_to_le32(info);
2508
2509 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2510
2511 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2512 switch (skb->protocol) {
2513 case __constant_htons(ETH_P_IP):
9d5c8243 2514 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2515 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2516 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2517 break;
2518 case __constant_htons(ETH_P_IPV6):
2519 /* XXX what about other V6 headers?? */
2520 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2521 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2522 break;
2523 default:
2524 if (unlikely(net_ratelimit()))
2525 dev_warn(&adapter->pdev->dev,
2526 "partial checksum but proto=%x!\n",
2527 skb->protocol);
2528 break;
2529 }
9d5c8243
AK		 2530 }
2531
2532 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2533 context_desc->seqnum_seed = 0;
2534 context_desc->mss_l4len_idx =
2535 cpu_to_le32(tx_ring->eims_value >> 4);
2536
2537 buffer_info->time_stamp = jiffies;
2538 buffer_info->dma = 0;
2539
2540 i++;
2541 if (i == tx_ring->count)
2542 i = 0;
2543 tx_ring->next_to_use = i;
2544
2545 return true;
2546 }
2547
2548
2549 return false;
2550}
2551
2552#define IGB_MAX_TXD_PWR 16
2553#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2554
2555static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2556 struct igb_ring *tx_ring,
2557 struct sk_buff *skb)
2558{
2559 struct igb_buffer *buffer_info;
2560 unsigned int len = skb_headlen(skb);
2561 unsigned int count = 0, i;
2562 unsigned int f;
2563
2564 i = tx_ring->next_to_use;
2565
2566 buffer_info = &tx_ring->buffer_info[i];
2567 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2568 buffer_info->length = len;
2569 /* set time_stamp *before* dma to help avoid a possible race */
2570 buffer_info->time_stamp = jiffies;
2571 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2572 PCI_DMA_TODEVICE);
2573 count++;
2574 i++;
2575 if (i == tx_ring->count)
2576 i = 0;
2577
2578 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2579 struct skb_frag_struct *frag;
2580
2581 frag = &skb_shinfo(skb)->frags[f];
2582 len = frag->size;
2583
2584 buffer_info = &tx_ring->buffer_info[i];
2585 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2586 buffer_info->length = len;
2587 buffer_info->time_stamp = jiffies;
2588 buffer_info->dma = pci_map_page(adapter->pdev,
2589 frag->page,
2590 frag->page_offset,
2591 len,
2592 PCI_DMA_TODEVICE);
2593
2594 count++;
2595 i++;
2596 if (i == tx_ring->count)
2597 i = 0;
2598 }
2599
2600 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2601 tx_ring->buffer_info[i].skb = skb;
2602
2603 return count;
2604}
2605
2606static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2607 struct igb_ring *tx_ring,
2608 int tx_flags, int count, u32 paylen,
2609 u8 hdr_len)
2610{
2611 union e1000_adv_tx_desc *tx_desc = NULL;
2612 struct igb_buffer *buffer_info;
2613 u32 olinfo_status = 0, cmd_type_len;
2614 unsigned int i;
2615
2616 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2617 E1000_ADVTXD_DCMD_DEXT);
2618
2619 if (tx_flags & IGB_TX_FLAGS_VLAN)
2620 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2621
2622 if (tx_flags & IGB_TX_FLAGS_TSO) {
2623 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2624
2625 /* insert tcp checksum */
2626 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2627
2628 /* insert ip checksum */
2629 if (tx_flags & IGB_TX_FLAGS_IPV4)
2630 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2631
2632 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2633 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2634 }
2635
2636 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2637 IGB_TX_FLAGS_VLAN))
2638 olinfo_status |= tx_ring->eims_value >> 4;
2639
2640 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2641
2642 i = tx_ring->next_to_use;
2643 while (count--) {
2644 buffer_info = &tx_ring->buffer_info[i];
2645 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2646 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2647 tx_desc->read.cmd_type_len =
2648 cpu_to_le32(cmd_type_len | buffer_info->length);
2649 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2650 i++;
2651 if (i == tx_ring->count)
2652 i = 0;
2653 }
2654
2655 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2656 /* Force memory writes to complete before letting h/w
2657 * know there are new descriptors to fetch. (Only
2658 * applicable for weak-ordered memory model archs,
2659 * such as IA-64). */
2660 wmb();
2661
2662 tx_ring->next_to_use = i;
2663 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2664 /* we need this if more than one processor can write to our tail
2665 * at a time, it syncronizes IO on IA64/Altix systems */
2666 mmiowb();
2667}
2668
2669static int __igb_maybe_stop_tx(struct net_device *netdev,
2670 struct igb_ring *tx_ring, int size)
2671{
2672 struct igb_adapter *adapter = netdev_priv(netdev);
2673
2674 netif_stop_queue(netdev);
2675 /* Herbert's original patch had:
2676 * smp_mb__after_netif_stop_queue();
2677 * but since that doesn't exist yet, just open code it. */
2678 smp_mb();
2679
2680 /* We need to check again in a case another CPU has just
2681 * made room available. */
2682 if (IGB_DESC_UNUSED(tx_ring) < size)
2683 return -EBUSY;
2684
2685 /* A reprieve! */
2686 netif_start_queue(netdev);
2687 ++adapter->restart_queue;
2688 return 0;
2689}
2690
2691static int igb_maybe_stop_tx(struct net_device *netdev,
2692 struct igb_ring *tx_ring, int size)
2693{
2694 if (IGB_DESC_UNUSED(tx_ring) >= size)
2695 return 0;
2696 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2697}
2698
2699#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2700
2701static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2702 struct net_device *netdev,
2703 struct igb_ring *tx_ring)
2704{
2705 struct igb_adapter *adapter = netdev_priv(netdev);
2706 unsigned int tx_flags = 0;
2707 unsigned int len;
2708 unsigned long irq_flags;
2709 u8 hdr_len = 0;
2710 int tso = 0;
2711
2712 len = skb_headlen(skb);
2713
2714 if (test_bit(__IGB_DOWN, &adapter->state)) {
2715 dev_kfree_skb_any(skb);
2716 return NETDEV_TX_OK;
2717 }
2718
2719 if (skb->len <= 0) {
2720 dev_kfree_skb_any(skb);
2721 return NETDEV_TX_OK;
2722 }
2723
2724 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2725 /* Collision - tell upper layer to requeue */
2726 return NETDEV_TX_LOCKED;
2727
2728 /* need: 1 descriptor per page,
2729 * + 2 desc gap to keep tail from touching head,
2730 * + 1 desc for skb->data,
2731 * + 1 desc for context descriptor,
2732 * otherwise try next time */
2733 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2734 /* this is a hard error */
2735 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2736 return NETDEV_TX_BUSY;
2737 }
2738
2739 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2740 tx_flags |= IGB_TX_FLAGS_VLAN;
2741 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2742 }
2743
2744 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2745 &hdr_len) : 0;
2746
2747 if (tso < 0) {
2748 dev_kfree_skb_any(skb);
2749 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2750 return NETDEV_TX_OK;
2751 }
2752
2753 if (tso)
2754 tx_flags |= IGB_TX_FLAGS_TSO;
2755 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2756 if (skb->ip_summed == CHECKSUM_PARTIAL)
2757 tx_flags |= IGB_TX_FLAGS_CSUM;
2758
2759 if (skb->protocol == htons(ETH_P_IP))
2760 tx_flags |= IGB_TX_FLAGS_IPV4;
2761
2762 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2763 igb_tx_map_adv(adapter, tx_ring, skb),
2764 skb->len, hdr_len);
2765
2766 netdev->trans_start = jiffies;
2767
2768 /* Make sure there is space in the ring for the next send. */
2769 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2770
2771 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2772 return NETDEV_TX_OK;
2773}
2774
2775static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2776{
2777 struct igb_adapter *adapter = netdev_priv(netdev);
2778 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2779
2780 /* This goes back to the question of how to logically map a tx queue
2781 * to a flow. Right now, performance is impacted slightly negatively
2782 * if using multiple tx queues. If the stack breaks away from a
2783 * single qdisc implementation, we can look at this again. */
2784 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2785}
2786
2787/**
2788 * igb_tx_timeout - Respond to a Tx Hang
2789 * @netdev: network interface device structure
2790 **/
2791static void igb_tx_timeout(struct net_device *netdev)
2792{
2793 struct igb_adapter *adapter = netdev_priv(netdev);
2794 struct e1000_hw *hw = &adapter->hw;
2795
2796 /* Do the reset outside of interrupt context */
2797 adapter->tx_timeout_count++;
2798 schedule_work(&adapter->reset_task);
2799 wr32(E1000_EICS, adapter->eims_enable_mask &
2800 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2801}
2802
2803static void igb_reset_task(struct work_struct *work)
2804{
2805 struct igb_adapter *adapter;
2806 adapter = container_of(work, struct igb_adapter, reset_task);
2807
2808 igb_reinit_locked(adapter);
2809}
2810
2811/**
2812 * igb_get_stats - Get System Network Statistics
2813 * @netdev: network interface device structure
2814 *
2815 * Returns the address of the device statistics structure.
2816 * The statistics are actually updated from the timer callback.
2817 **/
2818static struct net_device_stats *
2819igb_get_stats(struct net_device *netdev)
2820{
2821 struct igb_adapter *adapter = netdev_priv(netdev);
2822
2823 /* only return the current stats */
2824 return &adapter->net_stats;
2825}
2826
2827/**
2828 * igb_change_mtu - Change the Maximum Transfer Unit
2829 * @netdev: network interface device structure
2830 * @new_mtu: new value for maximum frame size
2831 *
2832 * Returns 0 on success, negative on failure
2833 **/
2834static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2835{
2836 struct igb_adapter *adapter = netdev_priv(netdev);
2837 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2838
2839 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2840 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2841 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2842 return -EINVAL;
2843 }
2844
2845#define MAX_STD_JUMBO_FRAME_SIZE 9234
2846 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2847 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2848 return -EINVAL;
2849 }
2850
2851 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2852 msleep(1);
2853 /* igb_down has a dependency on max_frame_size */
2854 adapter->max_frame_size = max_frame;
2855 if (netif_running(netdev))
2856 igb_down(adapter);
2857
2858 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2859 * means we reserve 2 more, this pushes us to allocate from the next
2860 * larger slab size.
2861 * i.e. RXBUFFER_2048 --> size-4096 slab
2862 */
2863
2864 if (max_frame <= IGB_RXBUFFER_256)
2865 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2866 else if (max_frame <= IGB_RXBUFFER_512)
2867 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2868 else if (max_frame <= IGB_RXBUFFER_1024)
2869 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2870 else if (max_frame <= IGB_RXBUFFER_2048)
2871 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2872 else
2873 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2874 /* adjust allocation if LPE protects us, and we aren't using SBP */
2875 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2876 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2877 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2878
2879 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2880 netdev->mtu, new_mtu);
2881 netdev->mtu = new_mtu;
2882
2883 if (netif_running(netdev))
2884 igb_up(adapter);
2885 else
2886 igb_reset(adapter);
2887
2888 clear_bit(__IGB_RESETTING, &adapter->state);
2889
2890 return 0;
2891}
2892
2893/**
2894 * igb_update_stats - Update the board statistics counters
2895 * @adapter: board private structure
2896 **/
2897
2898void igb_update_stats(struct igb_adapter *adapter)
2899{
2900 struct e1000_hw *hw = &adapter->hw;
2901 struct pci_dev *pdev = adapter->pdev;
2902 u16 phy_tmp;
2903
2904#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2905
2906 /*
2907 * Prevent stats update while adapter is being reset, or if the pci
2908 * connection is down.
2909 */
2910 if (adapter->link_speed == 0)
2911 return;
2912 if (pci_channel_offline(pdev))
2913 return;
2914
2915 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2916 adapter->stats.gprc += rd32(E1000_GPRC);
2917 adapter->stats.gorc += rd32(E1000_GORCL);
2918 rd32(E1000_GORCH); /* clear GORCL */
2919 adapter->stats.bprc += rd32(E1000_BPRC);
2920 adapter->stats.mprc += rd32(E1000_MPRC);
2921 adapter->stats.roc += rd32(E1000_ROC);
2922
2923 adapter->stats.prc64 += rd32(E1000_PRC64);
2924 adapter->stats.prc127 += rd32(E1000_PRC127);
2925 adapter->stats.prc255 += rd32(E1000_PRC255);
2926 adapter->stats.prc511 += rd32(E1000_PRC511);
2927 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2928 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2929 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2930 adapter->stats.sec += rd32(E1000_SEC);
2931
2932 adapter->stats.mpc += rd32(E1000_MPC);
2933 adapter->stats.scc += rd32(E1000_SCC);
2934 adapter->stats.ecol += rd32(E1000_ECOL);
2935 adapter->stats.mcc += rd32(E1000_MCC);
2936 adapter->stats.latecol += rd32(E1000_LATECOL);
2937 adapter->stats.dc += rd32(E1000_DC);
2938 adapter->stats.rlec += rd32(E1000_RLEC);
2939 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2940 adapter->stats.xontxc += rd32(E1000_XONTXC);
2941 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2942 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2943 adapter->stats.fcruc += rd32(E1000_FCRUC);
2944 adapter->stats.gptc += rd32(E1000_GPTC);
2945 adapter->stats.gotc += rd32(E1000_GOTCL);
2946 rd32(E1000_GOTCH); /* clear GOTCL */
2947 adapter->stats.rnbc += rd32(E1000_RNBC);
2948 adapter->stats.ruc += rd32(E1000_RUC);
2949 adapter->stats.rfc += rd32(E1000_RFC);
2950 adapter->stats.rjc += rd32(E1000_RJC);
2951 adapter->stats.tor += rd32(E1000_TORH);
2952 adapter->stats.tot += rd32(E1000_TOTH);
2953 adapter->stats.tpr += rd32(E1000_TPR);
2954
2955 adapter->stats.ptc64 += rd32(E1000_PTC64);
2956 adapter->stats.ptc127 += rd32(E1000_PTC127);
2957 adapter->stats.ptc255 += rd32(E1000_PTC255);
2958 adapter->stats.ptc511 += rd32(E1000_PTC511);
2959 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2960 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2961
2962 adapter->stats.mptc += rd32(E1000_MPTC);
2963 adapter->stats.bptc += rd32(E1000_BPTC);
2964
2965 /* used for adaptive IFS */
2966
2967 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2968 adapter->stats.tpt += hw->mac.tx_packet_delta;
2969 hw->mac.collision_delta = rd32(E1000_COLC);
2970 adapter->stats.colc += hw->mac.collision_delta;
2971
2972 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2973 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2974 adapter->stats.tncrs += rd32(E1000_TNCRS);
2975 adapter->stats.tsctc += rd32(E1000_TSCTC);
2976 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2977
2978 adapter->stats.iac += rd32(E1000_IAC);
2979 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2980 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2981 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2982 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2983 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2984 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2985 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2986 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2987
2988 /* Fill out the OS statistics structure */
2989 adapter->net_stats.multicast = adapter->stats.mprc;
2990 adapter->net_stats.collisions = adapter->stats.colc;
2991
2992 /* Rx Errors */
2993
2994 /* RLEC on some newer hardware can be incorrect so build
2995 * our own version based on RUC and ROC */
2996 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2997 adapter->stats.crcerrs + adapter->stats.algnerrc +
2998 adapter->stats.ruc + adapter->stats.roc +
2999 adapter->stats.cexterr;
3000 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3001 adapter->stats.roc;
3002 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3003 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3004 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3005
3006 /* Tx Errors */
3007 adapter->net_stats.tx_errors = adapter->stats.ecol +
3008 adapter->stats.latecol;
3009 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3010 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3011 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3012
3013 /* Tx Dropped needs to be maintained elsewhere */
3014
3015 /* Phy Stats */
3016 if (hw->phy.media_type == e1000_media_type_copper) {
3017 if ((adapter->link_speed == SPEED_1000) &&
3018 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3019 &phy_tmp))) {
3020 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3021 adapter->phy_stats.idle_errors += phy_tmp;
3022 }
3023 }
3024
3025 /* Management Stats */
3026 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3027 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3028 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3029}
3030
3031
3032static irqreturn_t igb_msix_other(int irq, void *data)
3033{
3034 struct net_device *netdev = data;
3035 struct igb_adapter *adapter = netdev_priv(netdev);
3036 struct e1000_hw *hw = &adapter->hw;
3037 u32 eicr;
3038 /* disable interrupts from the "other" bit, avoid re-entry */
3039 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3040
3041 eicr = rd32(E1000_EICR);
3042
3043 if (eicr & E1000_EIMS_OTHER) {
3044 u32 icr = rd32(E1000_ICR);
3045 /* reading ICR causes bit 31 of EICR to be cleared */
3046 if (!(icr & E1000_ICR_LSC))
3047 goto no_link_interrupt;
3048 hw->mac.get_link_status = 1;
3049 /* guard against interrupt when we're going down */
3050 if (!test_bit(__IGB_DOWN, &adapter->state))
3051 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3052 }
3053
3054no_link_interrupt:
3055 wr32(E1000_IMS, E1000_IMS_LSC);
3056 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3057
3058 return IRQ_HANDLED;
3059}
3060
3061static irqreturn_t igb_msix_tx(int irq, void *data)
3062{
3063 struct igb_ring *tx_ring = data;
3064 struct igb_adapter *adapter = tx_ring->adapter;
3065 struct e1000_hw *hw = &adapter->hw;
3066
3067 if (!tx_ring->itr_val)
3068 wr32(E1000_EIMC, tx_ring->eims_value);
3069
3070 tx_ring->total_bytes = 0;
3071 tx_ring->total_packets = 0;
3b644cf6 3072 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3073 /* Ring was not completely cleaned, so fire another interrupt */
3074 wr32(E1000_EICS, tx_ring->eims_value);
3075
3076 if (!tx_ring->itr_val)
3077 wr32(E1000_EIMS, tx_ring->eims_value);
3078 return IRQ_HANDLED;
3079}
3080
3081static irqreturn_t igb_msix_rx(int irq, void *data)
3082{
3083 struct igb_ring *rx_ring = data;
3084 struct igb_adapter *adapter = rx_ring->adapter;
3085 struct e1000_hw *hw = &adapter->hw;
3086
3087 if (!rx_ring->itr_val)
3088 wr32(E1000_EIMC, rx_ring->eims_value);
3089
3090 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3091 rx_ring->total_bytes = 0;
3092 rx_ring->total_packets = 0;
3093 rx_ring->no_itr_adjust = 0;
3094 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3095 } else {
3096 if (!rx_ring->no_itr_adjust) {
3097 igb_lower_rx_eitr(adapter, rx_ring);
3098 rx_ring->no_itr_adjust = 1;
3099 }
3100 }
3101
3102 return IRQ_HANDLED;
3103}
3104
3105
3106/**
3107 * igb_intr_msi - Interrupt Handler
3108 * @irq: interrupt number
3109 * @data: pointer to a network interface device structure
3110 **/
3111static irqreturn_t igb_intr_msi(int irq, void *data)
3112{
3113 struct net_device *netdev = data;
3114 struct igb_adapter *adapter = netdev_priv(netdev);
3115 struct napi_struct *napi = &adapter->napi;
3116 struct e1000_hw *hw = &adapter->hw;
3117 /* read ICR disables interrupts using IAM */
3118 u32 icr = rd32(E1000_ICR);
3119
3120 /* Write the ITR value calculated at the end of the
3121 * previous interrupt.
3122 */
3123 if (adapter->set_itr) {
3124 wr32(E1000_ITR,
3125 1000000000 / (adapter->itr * 256));
3126 adapter->set_itr = 0;
3127 }
3128
3129 /* read ICR disables interrupts using IAM */
3130 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3131 hw->mac.get_link_status = 1;
3132 if (!test_bit(__IGB_DOWN, &adapter->state))
3133 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3134 }
3135
3136 if (netif_rx_schedule_prep(netdev, napi)) {
3137 adapter->tx_ring->total_bytes = 0;
3138 adapter->tx_ring->total_packets = 0;
3139 adapter->rx_ring->total_bytes = 0;
3140 adapter->rx_ring->total_packets = 0;
3141 __netif_rx_schedule(netdev, napi);
3142 }
3143
3144 return IRQ_HANDLED;
3145}
3146
3147/**
3148 * igb_intr - Interrupt Handler
3149 * @irq: interrupt number
3150 * @data: pointer to a network interface device structure
3151 **/
3152static irqreturn_t igb_intr(int irq, void *data)
3153{
3154 struct net_device *netdev = data;
3155 struct igb_adapter *adapter = netdev_priv(netdev);
3156 struct napi_struct *napi = &adapter->napi;
3157 struct e1000_hw *hw = &adapter->hw;
3158 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3159 * need for the IMC write */
3160 u32 icr = rd32(E1000_ICR);
3161 u32 eicr = 0;
3162 if (!icr)
3163 return IRQ_NONE; /* Not our interrupt */
3164
3165 /* Write the ITR value calculated at the end of the
3166 * previous interrupt.
3167 */
3168 if (adapter->set_itr) {
3169 wr32(E1000_ITR,
3170 1000000000 / (adapter->itr * 256));
3171 adapter->set_itr = 0;
3172 }
3173
3174 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3175 * not set, then the adapter didn't send an interrupt */
3176 if (!(icr & E1000_ICR_INT_ASSERTED))
3177 return IRQ_NONE;
3178
3179 eicr = rd32(E1000_EICR);
3180
3181 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3182 hw->mac.get_link_status = 1;
3183 /* guard against interrupt when we're going down */
3184 if (!test_bit(__IGB_DOWN, &adapter->state))
3185 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3186 }
3187
3188 if (netif_rx_schedule_prep(netdev, napi)) {
3189 adapter->tx_ring->total_bytes = 0;
3190 adapter->rx_ring->total_bytes = 0;
3191 adapter->tx_ring->total_packets = 0;
3192 adapter->rx_ring->total_packets = 0;
3193 __netif_rx_schedule(netdev, napi);
3194 }
3195
3196 return IRQ_HANDLED;
3197}
3198
3199/**
3200 * igb_clean - NAPI Rx polling callback
3201 * @adapter: board private structure
3202 **/
3203static int igb_clean(struct napi_struct *napi, int budget)
3204{
3205 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3206 napi);
3207 struct net_device *netdev = adapter->netdev;
3208 int tx_clean_complete = 1, work_done = 0;
3209 int i;
3210
3211 /* Must NOT use netdev_priv macro here. */
3212 adapter = netdev->priv;
3213
3214 /* Keep link state information with original netdev */
3215 if (!netif_carrier_ok(netdev))
3216 goto quit_polling;
3217
3218 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3219 * being cleaned by multiple cpus simultaneously. A failure obtaining
3220 * the lock means tx_ring[i] is currently being cleaned anyway. */
3221 for (i = 0; i < adapter->num_tx_queues; i++) {
3222 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3b644cf6 3223 tx_clean_complete &= igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 3224 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3225 }
3226 }
3227
3228 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 3229 igb_clean_rx_irq_adv(&adapter->rx_ring[i], &work_done,
9d5c8243
AK		 3230 adapter->rx_ring[i].napi.weight);
3231
3232 /* If no Tx and not enough Rx work done, exit the polling mode */
3233 if ((tx_clean_complete && (work_done < budget)) ||
3234 !netif_running(netdev)) {
3235quit_polling:
3236 if (adapter->itr_setting & 3)
3237 igb_set_itr(adapter, E1000_ITR, false);
3238 netif_rx_complete(netdev, napi);
3239 if (!test_bit(__IGB_DOWN, &adapter->state))
3240 igb_irq_enable(adapter);
3241 return 0;
3242 }
3243
3244 return 1;
3245}
3246
3247static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3248{
3249 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3250 struct igb_adapter *adapter = rx_ring->adapter;
3251 struct e1000_hw *hw = &adapter->hw;
3252 struct net_device *netdev = adapter->netdev;
3253 int work_done = 0;
3254
3255 /* Keep link state information with original netdev */
3256 if (!netif_carrier_ok(netdev))
3257 goto quit_polling;
3258
3b644cf6 3259 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3260
3261
3262 /* If not enough Rx work done, exit the polling mode */
3263 if ((work_done == 0) || !netif_running(netdev)) {
3264quit_polling:
3265 netif_rx_complete(netdev, napi);
3266
3267 wr32(E1000_EIMS, rx_ring->eims_value);
3268 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3269 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3270 int mean_size = rx_ring->total_bytes /
3271 rx_ring->total_packets;
3272 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3273 igb_raise_rx_eitr(adapter, rx_ring);
3274 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3275 igb_lower_rx_eitr(adapter, rx_ring);
3276 }
3277 return 0;
3278 }
3279
3280 return 1;
3281}
6d8126f9
AV		 3282
3283static inline u32 get_head(struct igb_ring *tx_ring)
3284{
3285 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3286 return le32_to_cpu(*(volatile __le32 *)end);
3287}
3288
9d5c8243
AK		 3289/**
3290 * igb_clean_tx_irq - Reclaim resources after transmit completes
3291 * @adapter: board private structure
3292 * returns true if ring is completely cleaned
3293 **/
3b644cf6 3294static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3295{
3b644cf6 3296 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3297 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3298 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3299 struct e1000_tx_desc *tx_desc;
3300 struct igb_buffer *buffer_info;
3301 struct sk_buff *skb;
3302 unsigned int i;
3303 u32 head, oldhead;
3304 unsigned int count = 0;
3305 bool cleaned = false;
3306 bool retval = true;
3307 unsigned int total_bytes = 0, total_packets = 0;
3308
3309 rmb();
6d8126f9 3310 head = get_head(tx_ring);
9d5c8243
AK		 3311 i = tx_ring->next_to_clean;
3312 while (1) {
3313 while (i != head) {
3314 cleaned = true;
3315 tx_desc = E1000_TX_DESC(*tx_ring, i);
3316 buffer_info = &tx_ring->buffer_info[i];
3317 skb = buffer_info->skb;
3318
3319 if (skb) {
3320 unsigned int segs, bytecount;
3321 /* gso_segs is currently only valid for tcp */
3322 segs = skb_shinfo(skb)->gso_segs ?: 1;
3323 /* multiply data chunks by size of headers */
3324 bytecount = ((segs - 1) * skb_headlen(skb)) +
3325 skb->len;
3326 total_packets += segs;
3327 total_bytes += bytecount;
3328 }
3329
3330 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3331 tx_desc->upper.data = 0;
3332
3333 i++;
3334 if (i == tx_ring->count)
3335 i = 0;
3336
3337 count++;
3338 if (count == IGB_MAX_TX_CLEAN) {
3339 retval = false;
3340 goto done_cleaning;
3341 }
3342 }
3343 oldhead = head;
3344 rmb();
6d8126f9 3345 head = get_head(tx_ring);
9d5c8243
AK		 3346 if (head == oldhead)
3347 goto done_cleaning;
3348 } /* while (1) */
3349
3350done_cleaning:
3351 tx_ring->next_to_clean = i;
3352
3353 if (unlikely(cleaned &&
3354 netif_carrier_ok(netdev) &&
3355 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3356 /* Make sure that anybody stopping the queue after this
3357 * sees the new next_to_clean.
3358 */
3359 smp_mb();
3360 if (netif_queue_stopped(netdev) &&
3361 !(test_bit(__IGB_DOWN, &adapter->state))) {
3362 netif_wake_queue(netdev);
3363 ++adapter->restart_queue;
3364 }
3365 }
3366
3367 if (tx_ring->detect_tx_hung) {
3368 /* Detect a transmit hang in hardware, this serializes the
3369 * check with the clearing of time_stamp and movement of i */
3370 tx_ring->detect_tx_hung = false;
3371 if (tx_ring->buffer_info[i].time_stamp &&
3372 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3373 (adapter->tx_timeout_factor * HZ))
3374 && !(rd32(E1000_STATUS) &
3375 E1000_STATUS_TXOFF)) {
3376
3377 tx_desc = E1000_TX_DESC(*tx_ring, i);
3378 /* detected Tx unit hang */
3379 dev_err(&adapter->pdev->dev,
3380 "Detected Tx Unit Hang\n"
3381 " Tx Queue <%lu>\n"
3382 " TDH <%x>\n"
3383 " TDT <%x>\n"
3384 " next_to_use <%x>\n"
3385 " next_to_clean <%x>\n"
3386 " head (WB) <%x>\n"
3387 "buffer_info[next_to_clean]\n"
3388 " time_stamp <%lx>\n"
3389 " jiffies <%lx>\n"
3390 " desc.status <%x>\n",
3391 (unsigned long)((tx_ring - adapter->tx_ring) /
3392 sizeof(struct igb_ring)),
3393 readl(adapter->hw.hw_addr + tx_ring->head),
3394 readl(adapter->hw.hw_addr + tx_ring->tail),
3395 tx_ring->next_to_use,
3396 tx_ring->next_to_clean,
3397 head,
3398 tx_ring->buffer_info[i].time_stamp,
3399 jiffies,
3400 tx_desc->upper.fields.status);
3401 netif_stop_queue(netdev);
3402 }
3403 }
3404 tx_ring->total_bytes += total_bytes;
3405 tx_ring->total_packets += total_packets;
3406 adapter->net_stats.tx_bytes += total_bytes;
3407 adapter->net_stats.tx_packets += total_packets;
3408 return retval;
3409}
3410
3411
3412/**
3413 * igb_receive_skb - helper function to handle rx indications
3414 * @adapter: board private structure
3415 * @status: descriptor status field as written by hardware
3416 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3417 * @skb: pointer to sk_buff to be indicated to stack
3418 **/
6d8126f9 3419static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
9d5c8243
AK		 3420 struct sk_buff *skb)
3421{
3422 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3423 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3424 le16_to_cpu(vlan) &
3425 E1000_RXD_SPC_VLAN_MASK);
3426 else
3427 netif_receive_skb(skb);
3428}
3429
3430
3431static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3432 u32 status_err, struct sk_buff *skb)
3433{
3434 skb->ip_summed = CHECKSUM_NONE;
3435
3436 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3437 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3438 return;
3439 /* TCP/UDP checksum error bit is set */
3440 if (status_err &
3441 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3442 /* let the stack verify checksum errors */
3443 adapter->hw_csum_err++;
3444 return;
3445 }
3446 /* It must be a TCP or UDP packet with a valid checksum */
3447 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3448 skb->ip_summed = CHECKSUM_UNNECESSARY;
3449
3450 adapter->hw_csum_good++;
3451}
3452
3b644cf6
MW		 3453static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3454 int *work_done, int budget)
9d5c8243 3455{
3b644cf6 3456 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3457 struct net_device *netdev = adapter->netdev;
3458 struct pci_dev *pdev = adapter->pdev;
3459 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3460 struct igb_buffer *buffer_info , *next_buffer;
3461 struct sk_buff *skb;
3462 unsigned int i, j;
3463 u32 length, hlen, staterr;
3464 bool cleaned = false;
3465 int cleaned_count = 0;
3466 unsigned int total_bytes = 0, total_packets = 0;
3467
3468 i = rx_ring->next_to_clean;
3469 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3471
3472 while (staterr & E1000_RXD_STAT_DD) {
3473 if (*work_done >= budget)
3474 break;
3475 (*work_done)++;
3476 buffer_info = &rx_ring->buffer_info[i];
3477
3478 /* HW will not DMA in data larger than the given buffer, even
3479 * if it parses the (NFS, of course) header to be larger. In
3480 * that case, it fills the header buffer and spills the rest
3481 * into the page.
3482 */
7deb07b1
AV		 3483 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3484 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3485 if (hlen > adapter->rx_ps_hdr_size)
3486 hlen = adapter->rx_ps_hdr_size;
3487
3488 length = le16_to_cpu(rx_desc->wb.upper.length);
3489 cleaned = true;
3490 cleaned_count++;
3491
3492 if (rx_ring->pending_skb != NULL) {
3493 skb = rx_ring->pending_skb;
3494 rx_ring->pending_skb = NULL;
3495 j = rx_ring->pending_skb_page;
3496 } else {
3497 skb = buffer_info->skb;
3498 prefetch(skb->data - NET_IP_ALIGN);
3499 buffer_info->skb = NULL;
3500 if (hlen) {
3501 pci_unmap_single(pdev, buffer_info->dma,
3502 adapter->rx_ps_hdr_size +
3503 NET_IP_ALIGN,
3504 PCI_DMA_FROMDEVICE);
3505 skb_put(skb, hlen);
3506 } else {
3507 pci_unmap_single(pdev, buffer_info->dma,
3508 adapter->rx_buffer_len +
3509 NET_IP_ALIGN,
3510 PCI_DMA_FROMDEVICE);
3511 skb_put(skb, length);
3512 goto send_up;
3513 }
3514 j = 0;
3515 }
3516
3517 while (length) {
3518 pci_unmap_page(pdev, buffer_info->page_dma,
3519 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3520 buffer_info->page_dma = 0;
3521 skb_fill_page_desc(skb, j, buffer_info->page,
3522 0, length);
3523 buffer_info->page = NULL;
3524
3525 skb->len += length;
3526 skb->data_len += length;
3527 skb->truesize += length;
3528 rx_desc->wb.upper.status_error = 0;
3529 if (staterr & E1000_RXD_STAT_EOP)
3530 break;
3531
3532 j++;
3533 cleaned_count++;
3534 i++;
3535 if (i == rx_ring->count)
3536 i = 0;
3537
3538 buffer_info = &rx_ring->buffer_info[i];
3539 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3540 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3541 length = le16_to_cpu(rx_desc->wb.upper.length);
3542 if (!(staterr & E1000_RXD_STAT_DD)) {
3543 rx_ring->pending_skb = skb;
3544 rx_ring->pending_skb_page = j;
3545 goto out;
3546 }
3547 }
3548send_up:
3549 pskb_trim(skb, skb->len - 4);
3550 i++;
3551 if (i == rx_ring->count)
3552 i = 0;
3553 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3554 prefetch(next_rxd);
3555 next_buffer = &rx_ring->buffer_info[i];
3556
3557 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3558 dev_kfree_skb_irq(skb);
3559 goto next_desc;
3560 }
3561 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3562
3563 total_bytes += skb->len;
3564 total_packets++;
3565
3566 igb_rx_checksum_adv(adapter, staterr, skb);
3567
3568 skb->protocol = eth_type_trans(skb, netdev);
3569
3570 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3571
3572 netdev->last_rx = jiffies;
3573
3574next_desc:
3575 rx_desc->wb.upper.status_error = 0;
3576
3577 /* return some buffers to hardware, one at a time is too slow */
3578 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3579 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3580 cleaned_count = 0;
3581 }
3582
3583 /* use prefetched values */
3584 rx_desc = next_rxd;
3585 buffer_info = next_buffer;
3586
3587 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3588 }
3589out:
3590 rx_ring->next_to_clean = i;
3591 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3592
3593 if (cleaned_count)
3b644cf6 3594 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3595
3596 rx_ring->total_packets += total_packets;
3597 rx_ring->total_bytes += total_bytes;
3598 rx_ring->rx_stats.packets += total_packets;
3599 rx_ring->rx_stats.bytes += total_bytes;
3600 adapter->net_stats.rx_bytes += total_bytes;
3601 adapter->net_stats.rx_packets += total_packets;
3602 return cleaned;
3603}
3604
3605
3606/**
3607 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3608 * @adapter: address of board private structure
3609 **/
3b644cf6 3610static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3611 int cleaned_count)
3612{
3b644cf6 3613 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3614 struct net_device *netdev = adapter->netdev;
3615 struct pci_dev *pdev = adapter->pdev;
3616 union e1000_adv_rx_desc *rx_desc;
3617 struct igb_buffer *buffer_info;
3618 struct sk_buff *skb;
3619 unsigned int i;
3620
3621 i = rx_ring->next_to_use;
3622 buffer_info = &rx_ring->buffer_info[i];
3623
3624 while (cleaned_count--) {
3625 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3626
3627 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3628 buffer_info->page = alloc_page(GFP_ATOMIC);
3629 if (!buffer_info->page) {
3630 adapter->alloc_rx_buff_failed++;
3631 goto no_buffers;
3632 }
3633 buffer_info->page_dma =
3634 pci_map_page(pdev,
3635 buffer_info->page,
3636 0, PAGE_SIZE,
3637 PCI_DMA_FROMDEVICE);
3638 }
3639
3640 if (!buffer_info->skb) {
3641 int bufsz;
3642
3643 if (adapter->rx_ps_hdr_size)
3644 bufsz = adapter->rx_ps_hdr_size;
3645 else
3646 bufsz = adapter->rx_buffer_len;
3647 bufsz += NET_IP_ALIGN;
3648 skb = netdev_alloc_skb(netdev, bufsz);
3649
3650 if (!skb) {
3651 adapter->alloc_rx_buff_failed++;
3652 goto no_buffers;
3653 }
3654
3655 /* Make buffer alignment 2 beyond a 16 byte boundary
3656 * this will result in a 16 byte aligned IP header after
3657 * the 14 byte MAC header is removed
3658 */
3659 skb_reserve(skb, NET_IP_ALIGN);
3660
3661 buffer_info->skb = skb;
3662 buffer_info->dma = pci_map_single(pdev, skb->data,
3663 bufsz,
3664 PCI_DMA_FROMDEVICE);
3665
3666 }
3667 /* Refresh the desc even if buffer_addrs didn't change because
3668 * each write-back erases this info. */
3669 if (adapter->rx_ps_hdr_size) {
3670 rx_desc->read.pkt_addr =
3671 cpu_to_le64(buffer_info->page_dma);
3672 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3673 } else {
3674 rx_desc->read.pkt_addr =
3675 cpu_to_le64(buffer_info->dma);
3676 rx_desc->read.hdr_addr = 0;
3677 }
3678
3679 i++;
3680 if (i == rx_ring->count)
3681 i = 0;
3682 buffer_info = &rx_ring->buffer_info[i];
3683 }
3684
3685no_buffers:
3686 if (rx_ring->next_to_use != i) {
3687 rx_ring->next_to_use = i;
3688 if (i == 0)
3689 i = (rx_ring->count - 1);
3690 else
3691 i--;
3692
3693 /* Force memory writes to complete before letting h/w
3694 * know there are new descriptors to fetch. (Only
3695 * applicable for weak-ordered memory model archs,
3696 * such as IA-64). */
3697 wmb();
3698 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3699 }
3700}
3701
3702/**
3703 * igb_mii_ioctl -
3704 * @netdev:
3705 * @ifreq:
3706 * @cmd:
3707 **/
3708static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3709{
3710 struct igb_adapter *adapter = netdev_priv(netdev);
3711 struct mii_ioctl_data *data = if_mii(ifr);
3712
3713 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3714 return -EOPNOTSUPP;
3715
3716 switch (cmd) {
3717 case SIOCGMIIPHY:
3718 data->phy_id = adapter->hw.phy.addr;
3719 break;
3720 case SIOCGMIIREG:
3721 if (!capable(CAP_NET_ADMIN))
3722 return -EPERM;
3723 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3724 data->reg_num
3725 & 0x1F, &data->val_out))
3726 return -EIO;
3727 break;
3728 case SIOCSMIIREG:
3729 default:
3730 return -EOPNOTSUPP;
3731 }
3732 return 0;
3733}
3734
3735/**
3736 * igb_ioctl -
3737 * @netdev:
3738 * @ifreq:
3739 * @cmd:
3740 **/
3741static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3742{
3743 switch (cmd) {
3744 case SIOCGMIIPHY:
3745 case SIOCGMIIREG:
3746 case SIOCSMIIREG:
3747 return igb_mii_ioctl(netdev, ifr, cmd);
3748 default:
3749 return -EOPNOTSUPP;
3750 }
3751}
3752
3753static void igb_vlan_rx_register(struct net_device *netdev,
3754 struct vlan_group *grp)
3755{
3756 struct igb_adapter *adapter = netdev_priv(netdev);
3757 struct e1000_hw *hw = &adapter->hw;
3758 u32 ctrl, rctl;
3759
3760 igb_irq_disable(adapter);
3761 adapter->vlgrp = grp;
3762
3763 if (grp) {
3764 /* enable VLAN tag insert/strip */
3765 ctrl = rd32(E1000_CTRL);
3766 ctrl |= E1000_CTRL_VME;
3767 wr32(E1000_CTRL, ctrl);
3768
3769 /* enable VLAN receive filtering */
3770 rctl = rd32(E1000_RCTL);
3771 rctl |= E1000_RCTL_VFE;
3772 rctl &= ~E1000_RCTL_CFIEN;
3773 wr32(E1000_RCTL, rctl);
3774 igb_update_mng_vlan(adapter);
3775 wr32(E1000_RLPML,
3776 adapter->max_frame_size + VLAN_TAG_SIZE);
3777 } else {
3778 /* disable VLAN tag insert/strip */
3779 ctrl = rd32(E1000_CTRL);
3780 ctrl &= ~E1000_CTRL_VME;
3781 wr32(E1000_CTRL, ctrl);
3782
3783 /* disable VLAN filtering */
3784 rctl = rd32(E1000_RCTL);
3785 rctl &= ~E1000_RCTL_VFE;
3786 wr32(E1000_RCTL, rctl);
3787 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3788 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3789 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3790 }
3791 wr32(E1000_RLPML,
3792 adapter->max_frame_size);
3793 }
3794
3795 if (!test_bit(__IGB_DOWN, &adapter->state))
3796 igb_irq_enable(adapter);
3797}
3798
3799static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3800{
3801 struct igb_adapter *adapter = netdev_priv(netdev);
3802 struct e1000_hw *hw = &adapter->hw;
3803 u32 vfta, index;
3804
3805 if ((adapter->hw.mng_cookie.status &
3806 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3807 (vid == adapter->mng_vlan_id))
3808 return;
3809 /* add VID to filter table */
3810 index = (vid >> 5) & 0x7F;
3811 vfta = array_rd32(E1000_VFTA, index);
3812 vfta |= (1 << (vid & 0x1F));
3813 igb_write_vfta(&adapter->hw, index, vfta);
3814}
3815
3816static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3817{
3818 struct igb_adapter *adapter = netdev_priv(netdev);
3819 struct e1000_hw *hw = &adapter->hw;
3820 u32 vfta, index;
3821
3822 igb_irq_disable(adapter);
3823 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3824
3825 if (!test_bit(__IGB_DOWN, &adapter->state))
3826 igb_irq_enable(adapter);
3827
3828 if ((adapter->hw.mng_cookie.status &
3829 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3830 (vid == adapter->mng_vlan_id)) {
3831 /* release control to f/w */
3832 igb_release_hw_control(adapter);
3833 return;
3834 }
3835
3836 /* remove VID from filter table */
3837 index = (vid >> 5) & 0x7F;
3838 vfta = array_rd32(E1000_VFTA, index);
3839 vfta &= ~(1 << (vid & 0x1F));
3840 igb_write_vfta(&adapter->hw, index, vfta);
3841}
3842
3843static void igb_restore_vlan(struct igb_adapter *adapter)
3844{
3845 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3846
3847 if (adapter->vlgrp) {
3848 u16 vid;
3849 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3850 if (!vlan_group_get_device(adapter->vlgrp, vid))
3851 continue;
3852 igb_vlan_rx_add_vid(adapter->netdev, vid);
3853 }
3854 }
3855}
3856
3857int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3858{
3859 struct e1000_mac_info *mac = &adapter->hw.mac;
3860
3861 mac->autoneg = 0;
3862
3863 /* Fiber NICs only allow 1000 gbps Full duplex */
3864 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3865 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3866 dev_err(&adapter->pdev->dev,
3867 "Unsupported Speed/Duplex configuration\n");
3868 return -EINVAL;
3869 }
3870
3871 switch (spddplx) {
3872 case SPEED_10 + DUPLEX_HALF:
3873 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3874 break;
3875 case SPEED_10 + DUPLEX_FULL:
3876 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3877 break;
3878 case SPEED_100 + DUPLEX_HALF:
3879 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3880 break;
3881 case SPEED_100 + DUPLEX_FULL:
3882 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3883 break;
3884 case SPEED_1000 + DUPLEX_FULL:
3885 mac->autoneg = 1;
3886 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3887 break;
3888 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3889 default:
3890 dev_err(&adapter->pdev->dev,
3891 "Unsupported Speed/Duplex configuration\n");
3892 return -EINVAL;
3893 }
3894 return 0;
3895}
3896
3897
3898static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3899{
3900 struct net_device *netdev = pci_get_drvdata(pdev);
3901 struct igb_adapter *adapter = netdev_priv(netdev);
3902 struct e1000_hw *hw = &adapter->hw;
3903 u32 ctrl, ctrl_ext, rctl, status;
3904 u32 wufc = adapter->wol;
3905#ifdef CONFIG_PM
3906 int retval = 0;
3907#endif
3908
3909 netif_device_detach(netdev);
3910
3911 if (netif_running(netdev)) {
3912 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3913 igb_down(adapter);
3914 igb_free_irq(adapter);
3915 }
3916
3917#ifdef CONFIG_PM
3918 retval = pci_save_state(pdev);
3919 if (retval)
3920 return retval;
3921#endif
3922
3923 status = rd32(E1000_STATUS);
3924 if (status & E1000_STATUS_LU)
3925 wufc &= ~E1000_WUFC_LNKC;
3926
3927 if (wufc) {
3928 igb_setup_rctl(adapter);
3929 igb_set_multi(netdev);
3930
3931 /* turn on all-multi mode if wake on multicast is enabled */
3932 if (wufc & E1000_WUFC_MC) {
3933 rctl = rd32(E1000_RCTL);
3934 rctl |= E1000_RCTL_MPE;
3935 wr32(E1000_RCTL, rctl);
3936 }
3937
3938 ctrl = rd32(E1000_CTRL);
3939 /* advertise wake from D3Cold */
3940 #define E1000_CTRL_ADVD3WUC 0x00100000
3941 /* phy power management enable */
3942 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3943 ctrl |= E1000_CTRL_ADVD3WUC;
3944 wr32(E1000_CTRL, ctrl);
3945
3946 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3947 adapter->hw.phy.media_type ==
3948 e1000_media_type_internal_serdes) {
3949 /* keep the laser running in D3 */
3950 ctrl_ext = rd32(E1000_CTRL_EXT);
3951 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3952 wr32(E1000_CTRL_EXT, ctrl_ext);
3953 }
3954
3955 /* Allow time for pending master requests to run */
3956 igb_disable_pcie_master(&adapter->hw);
3957
3958 wr32(E1000_WUC, E1000_WUC_PME_EN);
3959 wr32(E1000_WUFC, wufc);
3960 pci_enable_wake(pdev, PCI_D3hot, 1);
3961 pci_enable_wake(pdev, PCI_D3cold, 1);
3962 } else {
3963 wr32(E1000_WUC, 0);
3964 wr32(E1000_WUFC, 0);
3965 pci_enable_wake(pdev, PCI_D3hot, 0);
3966 pci_enable_wake(pdev, PCI_D3cold, 0);
3967 }
3968
9d5c8243
AK		 3969 /* make sure adapter isn't asleep if manageability is enabled */
3970 if (adapter->en_mng_pt) {
3971 pci_enable_wake(pdev, PCI_D3hot, 1);
3972 pci_enable_wake(pdev, PCI_D3cold, 1);
3973 }
3974
3975 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3976 * would have already happened in close and is redundant. */
3977 igb_release_hw_control(adapter);
3978
3979 pci_disable_device(pdev);
3980
3981 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3982
3983 return 0;
3984}
3985
3986#ifdef CONFIG_PM
3987static int igb_resume(struct pci_dev *pdev)
3988{
3989 struct net_device *netdev = pci_get_drvdata(pdev);
3990 struct igb_adapter *adapter = netdev_priv(netdev);
3991 struct e1000_hw *hw = &adapter->hw;
3992 u32 err;
3993
3994 pci_set_power_state(pdev, PCI_D0);
3995 pci_restore_state(pdev);
42bfd33a
TI		 3996
3997 if (adapter->need_ioport)
3998 err = pci_enable_device(pdev);
3999 else
4000 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4001 if (err) {
4002 dev_err(&pdev->dev,
4003 "igb: Cannot enable PCI device from suspend\n");
4004 return err;
4005 }
4006 pci_set_master(pdev);
4007
4008 pci_enable_wake(pdev, PCI_D3hot, 0);
4009 pci_enable_wake(pdev, PCI_D3cold, 0);
4010
4011 if (netif_running(netdev)) {
4012 err = igb_request_irq(adapter);
4013 if (err)
4014 return err;
4015 }
4016
4017 /* e1000_power_up_phy(adapter); */
4018
4019 igb_reset(adapter);
4020 wr32(E1000_WUS, ~0);
4021
4022 igb_init_manageability(adapter);
4023
4024 if (netif_running(netdev))
4025 igb_up(adapter);
4026
4027 netif_device_attach(netdev);
4028
4029 /* let the f/w know that the h/w is now under the control of the
4030 * driver. */
4031 igb_get_hw_control(adapter);
4032
4033 return 0;
4034}
4035#endif
4036
4037static void igb_shutdown(struct pci_dev *pdev)
4038{
4039 igb_suspend(pdev, PMSG_SUSPEND);
4040}
4041
4042#ifdef CONFIG_NET_POLL_CONTROLLER
4043/*
4044 * Polling 'interrupt' - used by things like netconsole to send skbs
4045 * without having to re-enable interrupts. It's not called while
4046 * the interrupt routine is executing.
4047 */
4048static void igb_netpoll(struct net_device *netdev)
4049{
4050 struct igb_adapter *adapter = netdev_priv(netdev);
4051 int i;
4052 int work_done = 0;
4053
4054 igb_irq_disable(adapter);
4055 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4056 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4057
4058 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4059 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4060 &work_done,
4061 adapter->rx_ring[i].napi.weight);
4062
4063 igb_irq_enable(adapter);
4064}
4065#endif /* CONFIG_NET_POLL_CONTROLLER */
4066
4067/**
4068 * igb_io_error_detected - called when PCI error is detected
4069 * @pdev: Pointer to PCI device
4070 * @state: The current pci connection state
4071 *
4072 * This function is called after a PCI bus error affecting
4073 * this device has been detected.
4074 */
4075static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4076 pci_channel_state_t state)
4077{
4078 struct net_device *netdev = pci_get_drvdata(pdev);
4079 struct igb_adapter *adapter = netdev_priv(netdev);
4080
4081 netif_device_detach(netdev);
4082
4083 if (netif_running(netdev))
4084 igb_down(adapter);
4085 pci_disable_device(pdev);
4086
4087 /* Request a slot slot reset. */
4088 return PCI_ERS_RESULT_NEED_RESET;
4089}
4090
4091/**
4092 * igb_io_slot_reset - called after the pci bus has been reset.
4093 * @pdev: Pointer to PCI device
4094 *
4095 * Restart the card from scratch, as if from a cold-boot. Implementation
4096 * resembles the first-half of the igb_resume routine.
4097 */
4098static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4099{
4100 struct net_device *netdev = pci_get_drvdata(pdev);
4101 struct igb_adapter *adapter = netdev_priv(netdev);
4102 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4103 int err;
9d5c8243 4104
42bfd33a
TI		 4105 if (adapter->need_ioport)
4106 err = pci_enable_device(pdev);
4107 else
4108 err = pci_enable_device_mem(pdev);
4109 if (err) {
9d5c8243
AK		 4110 dev_err(&pdev->dev,
4111 "Cannot re-enable PCI device after reset.\n");
4112 return PCI_ERS_RESULT_DISCONNECT;
4113 }
4114 pci_set_master(pdev);
c682fc23 4115 pci_restore_state(pdev);
9d5c8243
AK		 4116
4117 pci_enable_wake(pdev, PCI_D3hot, 0);
4118 pci_enable_wake(pdev, PCI_D3cold, 0);
4119
4120 igb_reset(adapter);
4121 wr32(E1000_WUS, ~0);
4122
4123 return PCI_ERS_RESULT_RECOVERED;
4124}
4125
4126/**
4127 * igb_io_resume - called when traffic can start flowing again.
4128 * @pdev: Pointer to PCI device
4129 *
4130 * This callback is called when the error recovery driver tells us that
4131 * its OK to resume normal operation. Implementation resembles the
4132 * second-half of the igb_resume routine.
4133 */
4134static void igb_io_resume(struct pci_dev *pdev)
4135{
4136 struct net_device *netdev = pci_get_drvdata(pdev);
4137 struct igb_adapter *adapter = netdev_priv(netdev);
4138
4139 igb_init_manageability(adapter);
4140
4141 if (netif_running(netdev)) {
4142 if (igb_up(adapter)) {
4143 dev_err(&pdev->dev, "igb_up failed after reset\n");
4144 return;
4145 }
4146 }
4147
4148 netif_device_attach(netdev);
4149
4150 /* let the f/w know that the h/w is now under the control of the
4151 * driver. */
4152 igb_get_hw_control(adapter);
4153
4154}
4155
4156/* igb_main.c */
Linux kernel - Deliverables
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