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igb: remove rx_ps_hdr_len
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
85b430b4 93static void igb_setup_tctl(struct igb_adapter *);
9d5c8243
AK		 94static void igb_setup_rctl(struct igb_adapter *);
95static void igb_clean_all_tx_rings(struct igb_adapter *);
96static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 97static void igb_clean_tx_ring(struct igb_ring *);
98static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 99static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 100static void igb_update_phy_info(unsigned long);
101static void igb_watchdog(unsigned long);
102static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 103static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
104 struct net_device *,
105 struct igb_ring *);
106static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
107 struct net_device *);
9d5c8243
AK		 108static struct net_device_stats *igb_get_stats(struct net_device *);
109static int igb_change_mtu(struct net_device *, int);
110static int igb_set_mac(struct net_device *, void *);
68d480c4 111static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 112static irqreturn_t igb_intr(int irq, void *);
113static irqreturn_t igb_intr_msi(int irq, void *);
114static irqreturn_t igb_msix_other(int irq, void *);
047e0030 115static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
047e0030 117static void igb_update_dca(struct igb_q_vector *);
fe4506b6 118static void igb_setup_dca(struct igb_adapter *);
421e02f0 119#endif /* CONFIG_IGB_DCA */
047e0030 120static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 121static int igb_poll(struct napi_struct *, int);
047e0030 122static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
3b644cf6 123static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 124static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
125static void igb_tx_timeout(struct net_device *);
126static void igb_reset_task(struct work_struct *);
127static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
128static void igb_vlan_rx_add_vid(struct net_device *, u16);
129static void igb_vlan_rx_kill_vid(struct net_device *, u16);
130static void igb_restore_vlan(struct igb_adapter *);
26ad9178 131static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 132static void igb_ping_all_vfs(struct igb_adapter *);
133static void igb_msg_task(struct igb_adapter *);
134static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 135static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 136static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
137static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 138
c8159b2d
ED		 139static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
140{
141 u32 reg_data;
142
143 reg_data = rd32(E1000_VMOLR(vfn));
144 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
ae641bdc
AD		 157 /* if it isn't the PF check to see if VFs are enabled and
158 * increase the size to support vlan tags */
159 if (vfn < adapter->vfs_allocated_count &&
160 adapter->vf_data[vfn].vlans_enabled)
161 size += VLAN_TAG_SIZE;
162
c8159b2d
ED		 163 vmolr = rd32(E1000_VMOLR(vfn));
164 vmolr &= ~E1000_VMOLR_RLPML_MASK;
165 vmolr |= size | E1000_VMOLR_LPE;
166 wr32(E1000_VMOLR(vfn), vmolr);
167
168 return 0;
169}
170
9d5c8243 171#ifdef CONFIG_PM
3fe7c4c9 172static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 173static int igb_resume(struct pci_dev *);
174#endif
175static void igb_shutdown(struct pci_dev *);
421e02f0 176#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 177static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
178static struct notifier_block dca_notifier = {
179 .notifier_call = igb_notify_dca,
180 .next = NULL,
181 .priority = 0
182};
183#endif
9d5c8243
AK		 184#ifdef CONFIG_NET_POLL_CONTROLLER
185/* for netdump / net console */
186static void igb_netpoll(struct net_device *);
187#endif
37680117 188#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 189static unsigned int max_vfs = 0;
190module_param(max_vfs, uint, 0);
191MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
192 "per physical function");
193#endif /* CONFIG_PCI_IOV */
194
9d5c8243
AK		 195static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
196 pci_channel_state_t);
197static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
198static void igb_io_resume(struct pci_dev *);
199
200static struct pci_error_handlers igb_err_handler = {
201 .error_detected = igb_io_error_detected,
202 .slot_reset = igb_io_slot_reset,
203 .resume = igb_io_resume,
204};
205
206
207static struct pci_driver igb_driver = {
208 .name = igb_driver_name,
209 .id_table = igb_pci_tbl,
210 .probe = igb_probe,
211 .remove = __devexit_p(igb_remove),
212#ifdef CONFIG_PM
213 /* Power Managment Hooks */
214 .suspend = igb_suspend,
215 .resume = igb_resume,
216#endif
217 .shutdown = igb_shutdown,
218 .err_handler = &igb_err_handler
219};
220
7dfc16fa
AD		 221static int global_quad_port_a; /* global quad port a indication */
222
9d5c8243
AK		 223MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
224MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
225MODULE_LICENSE("GPL");
226MODULE_VERSION(DRV_VERSION);
227
38c845c7
PO		 228/**
229 * Scale the NIC clock cycle by a large factor so that
230 * relatively small clock corrections can be added or
231 * substracted at each clock tick. The drawbacks of a
232 * large factor are a) that the clock register overflows
233 * more quickly (not such a big deal) and b) that the
234 * increment per tick has to fit into 24 bits.
235 *
236 * Note that
237 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
238 * IGB_TSYNC_SCALE
239 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
240 *
241 * The base scale factor is intentionally a power of two
242 * so that the division in %struct timecounter can be done with
243 * a shift.
244 */
245#define IGB_TSYNC_SHIFT (19)
246#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
247
248/**
249 * The duration of one clock cycle of the NIC.
250 *
251 * @todo This hard-coded value is part of the specification and might change
252 * in future hardware revisions. Add revision check.
253 */
254#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
255
256#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
257# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
258#endif
259
260/**
261 * igb_read_clock - read raw cycle counter (to be used by time counter)
262 */
263static cycle_t igb_read_clock(const struct cyclecounter *tc)
264{
265 struct igb_adapter *adapter =
266 container_of(tc, struct igb_adapter, cycles);
267 struct e1000_hw *hw = &adapter->hw;
268 u64 stamp;
269
270 stamp = rd32(E1000_SYSTIML);
271 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
272
273 return stamp;
274}
275
9d5c8243
AK		 276#ifdef DEBUG
277/**
278 * igb_get_hw_dev_name - return device name string
279 * used by hardware layer to print debugging information
280 **/
281char *igb_get_hw_dev_name(struct e1000_hw *hw)
282{
283 struct igb_adapter *adapter = hw->back;
284 return adapter->netdev->name;
285}
38c845c7
PO		 286
287/**
288 * igb_get_time_str - format current NIC and system time as string
289 */
290static char *igb_get_time_str(struct igb_adapter *adapter,
291 char buffer[160])
292{
293 cycle_t hw = adapter->cycles.read(&adapter->cycles);
294 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
295 struct timespec sys;
296 struct timespec delta;
297 getnstimeofday(&sys);
298
299 delta = timespec_sub(nic, sys);
300
301 sprintf(buffer,
33af6bcc
PO		 302 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
303 hw,
38c845c7
PO		 304 (long)nic.tv_sec, nic.tv_nsec,
305 (long)sys.tv_sec, sys.tv_nsec,
306 (long)delta.tv_sec, delta.tv_nsec);
307
308 return buffer;
309}
9d5c8243
AK		 310#endif
311
c493ea45
AD		 312/**
313 * igb_desc_unused - calculate if we have unused descriptors
314 **/
315static int igb_desc_unused(struct igb_ring *ring)
316{
317 if (ring->next_to_clean > ring->next_to_use)
318 return ring->next_to_clean - ring->next_to_use - 1;
319
320 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
321}
322
9d5c8243
AK		 323/**
324 * igb_init_module - Driver Registration Routine
325 *
326 * igb_init_module is the first routine called when the driver is
327 * loaded. All it does is register with the PCI subsystem.
328 **/
329static int __init igb_init_module(void)
330{
331 int ret;
332 printk(KERN_INFO "%s - version %s\n",
333 igb_driver_string, igb_driver_version);
334
335 printk(KERN_INFO "%s\n", igb_copyright);
336
7dfc16fa
AD		 337 global_quad_port_a = 0;
338
421e02f0 339#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 340 dca_register_notify(&dca_notifier);
341#endif
bbd98fe4
AD		 342
343 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 344 return ret;
345}
346
347module_init(igb_init_module);
348
349/**
350 * igb_exit_module - Driver Exit Cleanup Routine
351 *
352 * igb_exit_module is called just before the driver is removed
353 * from memory.
354 **/
355static void __exit igb_exit_module(void)
356{
421e02f0 357#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 358 dca_unregister_notify(&dca_notifier);
359#endif
9d5c8243
AK		 360 pci_unregister_driver(&igb_driver);
361}
362
363module_exit(igb_exit_module);
364
26bc19ec
AD		 365#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
366/**
367 * igb_cache_ring_register - Descriptor ring to register mapping
368 * @adapter: board private structure to initialize
369 *
370 * Once we know the feature-set enabled for the device, we'll cache
371 * the register offset the descriptor ring is assigned to.
372 **/
373static void igb_cache_ring_register(struct igb_adapter *adapter)
374{
375 int i;
047e0030 376 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 377
378 switch (adapter->hw.mac.type) {
379 case e1000_82576:
380 /* The queues are allocated for virtualization such that VF 0
381 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
382 * In order to avoid collision we start at the first free queue
383 * and continue consuming queues in the same sequence
384 */
385 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 386 adapter->rx_ring[i].reg_idx = rbase_offset +
387 Q_IDX_82576(i);
26bc19ec 388 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 389 adapter->tx_ring[i].reg_idx = rbase_offset +
390 Q_IDX_82576(i);
26bc19ec
AD		 391 break;
392 case e1000_82575:
393 default:
394 for (i = 0; i < adapter->num_rx_queues; i++)
395 adapter->rx_ring[i].reg_idx = i;
396 for (i = 0; i < adapter->num_tx_queues; i++)
397 adapter->tx_ring[i].reg_idx = i;
398 break;
399 }
400}
401
047e0030
AD		 402static void igb_free_queues(struct igb_adapter *adapter)
403{
404 kfree(adapter->tx_ring);
405 kfree(adapter->rx_ring);
406
407 adapter->tx_ring = NULL;
408 adapter->rx_ring = NULL;
409
410 adapter->num_rx_queues = 0;
411 adapter->num_tx_queues = 0;
412}
413
9d5c8243
AK		 414/**
415 * igb_alloc_queues - Allocate memory for all rings
416 * @adapter: board private structure to initialize
417 *
418 * We allocate one ring per queue at run-time since we don't know the
419 * number of queues at compile-time.
420 **/
421static int igb_alloc_queues(struct igb_adapter *adapter)
422{
423 int i;
424
425 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
426 sizeof(struct igb_ring), GFP_KERNEL);
427 if (!adapter->tx_ring)
047e0030 428 goto err;
9d5c8243
AK		 429
430 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
431 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 432 if (!adapter->rx_ring)
433 goto err;
6eb5a7f1 434
661086df
PWJ		 435 for (i = 0; i < adapter->num_tx_queues; i++) {
436 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 437 ring->count = adapter->tx_ring_count;
661086df
PWJ		 438 ring->queue_index = i;
439 }
9d5c8243
AK		 440 for (i = 0; i < adapter->num_rx_queues; i++) {
441 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 442 ring->count = adapter->rx_ring_count;
844290e5 443 ring->queue_index = i;
9d5c8243 444 }
26bc19ec
AD		 445
446 igb_cache_ring_register(adapter);
9d5c8243 447
047e0030 448 return 0;
a88f10ec 449
047e0030
AD		 450err:
451 igb_free_queues(adapter);
d1a8c9e1 452
047e0030 453 return -ENOMEM;
a88f10ec
AD		 454}
455
9d5c8243 456#define IGB_N0_QUEUE -1
047e0030 457static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 458{
459 u32 msixbm = 0;
047e0030 460 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 461 struct e1000_hw *hw = &adapter->hw;
2d064c06 462 u32 ivar, index;
047e0030
AD		 463 int rx_queue = IGB_N0_QUEUE;
464 int tx_queue = IGB_N0_QUEUE;
465
466 if (q_vector->rx_ring)
467 rx_queue = q_vector->rx_ring->reg_idx;
468 if (q_vector->tx_ring)
469 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 470
471 switch (hw->mac.type) {
472 case e1000_82575:
9d5c8243
AK		 473 /* The 82575 assigns vectors using a bitmask, which matches the
474 bitmask for the EICR/EIMS/EIMC registers. To assign one
475 or more queues to a vector, we write the appropriate bits
476 into the MSIXBM register for that vector. */
047e0030 477 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 478 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 479 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 480 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 481 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 482 q_vector->eims_value = msixbm;
2d064c06
AD		 483 break;
484 case e1000_82576:
26bc19ec 485 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 486 Each queue has a single entry in the table to which we write
487 a vector number along with a "valid" bit. Sadly, the layout
488 of the table is somewhat counterintuitive. */
489 if (rx_queue > IGB_N0_QUEUE) {
047e0030 490 index = (rx_queue & 0x7);
2d064c06 491 ivar = array_rd32(E1000_IVAR0, index);
047e0030 492 if (rx_queue < 8) {
26bc19ec
AD		 493 /* vector goes into low byte of register */
494 ivar = ivar & 0xFFFFFF00;
495 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 496 } else {
497 /* vector goes into third byte of register */
498 ivar = ivar & 0xFF00FFFF;
499 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 500 }
2d064c06
AD		 501 array_wr32(E1000_IVAR0, index, ivar);
502 }
503 if (tx_queue > IGB_N0_QUEUE) {
047e0030 504 index = (tx_queue & 0x7);
2d064c06 505 ivar = array_rd32(E1000_IVAR0, index);
047e0030 506 if (tx_queue < 8) {
26bc19ec
AD		 507 /* vector goes into second byte of register */
508 ivar = ivar & 0xFFFF00FF;
509 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 510 } else {
511 /* vector goes into high byte of register */
512 ivar = ivar & 0x00FFFFFF;
513 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 514 }
2d064c06
AD		 515 array_wr32(E1000_IVAR0, index, ivar);
516 }
047e0030 517 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 518 break;
519 default:
520 BUG();
521 break;
522 }
9d5c8243
AK		 523}
524
525/**
526 * igb_configure_msix - Configure MSI-X hardware
527 *
528 * igb_configure_msix sets up the hardware to properly
529 * generate MSI-X interrupts.
530 **/
531static void igb_configure_msix(struct igb_adapter *adapter)
532{
533 u32 tmp;
534 int i, vector = 0;
535 struct e1000_hw *hw = &adapter->hw;
536
537 adapter->eims_enable_mask = 0;
9d5c8243
AK		 538
539 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 540 switch (hw->mac.type) {
541 case e1000_82575:
9d5c8243
AK		 542 tmp = rd32(E1000_CTRL_EXT);
543 /* enable MSI-X PBA support*/
544 tmp |= E1000_CTRL_EXT_PBA_CLR;
545
546 /* Auto-Mask interrupts upon ICR read. */
547 tmp |= E1000_CTRL_EXT_EIAME;
548 tmp |= E1000_CTRL_EXT_IRCA;
549
550 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 551
552 /* enable msix_other interrupt */
553 array_wr32(E1000_MSIXBM(0), vector++,
554 E1000_EIMS_OTHER);
844290e5 555 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 556
2d064c06
AD		 557 break;
558
559 case e1000_82576:
047e0030
AD		 560 /* Turn on MSI-X capability first, or our settings
561 * won't stick. And it will take days to debug. */
562 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
563 E1000_GPIE_PBA | E1000_GPIE_EIAME |
564 E1000_GPIE_NSICR);
565
566 /* enable msix_other interrupt */
567 adapter->eims_other = 1 << vector;
2d064c06 568 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 569
047e0030 570 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 571 break;
572 default:
573 /* do nothing, since nothing else supports MSI-X */
574 break;
575 } /* switch (hw->mac.type) */
047e0030
AD		 576
577 adapter->eims_enable_mask |= adapter->eims_other;
578
579 for (i = 0; i < adapter->num_q_vectors; i++) {
580 struct igb_q_vector *q_vector = adapter->q_vector[i];
581 igb_assign_vector(q_vector, vector++);
582 adapter->eims_enable_mask |= q_vector->eims_value;
583 }
584
9d5c8243
AK		 585 wrfl();
586}
587
588/**
589 * igb_request_msix - Initialize MSI-X interrupts
590 *
591 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
592 * kernel.
593 **/
594static int igb_request_msix(struct igb_adapter *adapter)
595{
596 struct net_device *netdev = adapter->netdev;
047e0030 597 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 598 int i, err = 0, vector = 0;
599
047e0030
AD		 600 err = request_irq(adapter->msix_entries[vector].vector,
601 &igb_msix_other, 0, netdev->name, adapter);
602 if (err)
603 goto out;
604 vector++;
605
606 for (i = 0; i < adapter->num_q_vectors; i++) {
607 struct igb_q_vector *q_vector = adapter->q_vector[i];
608
609 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
610
611 if (q_vector->rx_ring && q_vector->tx_ring)
612 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
613 q_vector->rx_ring->queue_index);
614 else if (q_vector->tx_ring)
615 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
616 q_vector->tx_ring->queue_index);
617 else if (q_vector->rx_ring)
618 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
619 q_vector->rx_ring->queue_index);
9d5c8243 620 else
047e0030
AD		 621 sprintf(q_vector->name, "%s-unused", netdev->name);
622
9d5c8243 623 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 624 &igb_msix_ring, 0, q_vector->name,
625 q_vector);
9d5c8243
AK		 626 if (err)
627 goto out;
9d5c8243
AK		 628 vector++;
629 }
630
9d5c8243
AK		 631 igb_configure_msix(adapter);
632 return 0;
633out:
634 return err;
635}
636
637static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
638{
639 if (adapter->msix_entries) {
640 pci_disable_msix(adapter->pdev);
641 kfree(adapter->msix_entries);
642 adapter->msix_entries = NULL;
047e0030 643 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 644 pci_disable_msi(adapter->pdev);
047e0030 645 }
9d5c8243
AK		 646}
647
047e0030
AD		 648/**
649 * igb_free_q_vectors - Free memory allocated for interrupt vectors
650 * @adapter: board private structure to initialize
651 *
652 * This function frees the memory allocated to the q_vectors. In addition if
653 * NAPI is enabled it will delete any references to the NAPI struct prior
654 * to freeing the q_vector.
655 **/
656static void igb_free_q_vectors(struct igb_adapter *adapter)
657{
658 int v_idx;
659
660 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
661 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
662 adapter->q_vector[v_idx] = NULL;
663 netif_napi_del(&q_vector->napi);
664 kfree(q_vector);
665 }
666 adapter->num_q_vectors = 0;
667}
668
669/**
670 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
671 *
672 * This function resets the device so that it has 0 rx queues, tx queues, and
673 * MSI-X interrupts allocated.
674 */
675static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
676{
677 igb_free_queues(adapter);
678 igb_free_q_vectors(adapter);
679 igb_reset_interrupt_capability(adapter);
680}
9d5c8243
AK		 681
682/**
683 * igb_set_interrupt_capability - set MSI or MSI-X if supported
684 *
685 * Attempt to configure interrupts using the best available
686 * capabilities of the hardware and kernel.
687 **/
688static void igb_set_interrupt_capability(struct igb_adapter *adapter)
689{
690 int err;
691 int numvecs, i;
692
83b7180d 693 /* Number of supported queues. */
83b7180d
AD		 694 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
695 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
696
047e0030
AD		 697 /* start with one vector for every rx queue */
698 numvecs = adapter->num_rx_queues;
699
700 /* if tx handler is seperate add 1 for every tx queue */
701 numvecs += adapter->num_tx_queues;
702
703 /* store the number of vectors reserved for queues */
704 adapter->num_q_vectors = numvecs;
705
706 /* add 1 vector for link status interrupts */
707 numvecs++;
9d5c8243
AK		 708 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
709 GFP_KERNEL);
710 if (!adapter->msix_entries)
711 goto msi_only;
712
713 for (i = 0; i < numvecs; i++)
714 adapter->msix_entries[i].entry = i;
715
716 err = pci_enable_msix(adapter->pdev,
717 adapter->msix_entries,
718 numvecs);
719 if (err == 0)
34a20e89 720 goto out;
9d5c8243
AK		 721
722 igb_reset_interrupt_capability(adapter);
723
724 /* If we can't do MSI-X, try MSI */
725msi_only:
2a3abf6d
AD		 726#ifdef CONFIG_PCI_IOV
727 /* disable SR-IOV for non MSI-X configurations */
728 if (adapter->vf_data) {
729 struct e1000_hw *hw = &adapter->hw;
730 /* disable iov and allow time for transactions to clear */
731 pci_disable_sriov(adapter->pdev);
732 msleep(500);
733
734 kfree(adapter->vf_data);
735 adapter->vf_data = NULL;
736 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
737 msleep(100);
738 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
739 }
740#endif
9d5c8243 741 adapter->num_rx_queues = 1;
661086df 742 adapter->num_tx_queues = 1;
047e0030 743 adapter->num_q_vectors = 1;
9d5c8243 744 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 745 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 746out:
661086df 747 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 748 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 749 return;
750}
751
047e0030
AD		 752/**
753 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
754 * @adapter: board private structure to initialize
755 *
756 * We allocate one q_vector per queue interrupt. If allocation fails we
757 * return -ENOMEM.
758 **/
759static int igb_alloc_q_vectors(struct igb_adapter *adapter)
760{
761 struct igb_q_vector *q_vector;
762 struct e1000_hw *hw = &adapter->hw;
763 int v_idx;
764
765 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
766 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
767 if (!q_vector)
768 goto err_out;
769 q_vector->adapter = adapter;
770 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
771 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
772 q_vector->itr_val = IGB_START_ITR;
773 q_vector->set_itr = 1;
774 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
775 adapter->q_vector[v_idx] = q_vector;
776 }
777 return 0;
778
779err_out:
780 while (v_idx) {
781 v_idx--;
782 q_vector = adapter->q_vector[v_idx];
783 netif_napi_del(&q_vector->napi);
784 kfree(q_vector);
785 adapter->q_vector[v_idx] = NULL;
786 }
787 return -ENOMEM;
788}
789
790static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
791 int ring_idx, int v_idx)
792{
793 struct igb_q_vector *q_vector;
794
795 q_vector = adapter->q_vector[v_idx];
796 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
797 q_vector->rx_ring->q_vector = q_vector;
798 q_vector->itr_val = adapter->itr;
799}
800
801static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
802 int ring_idx, int v_idx)
803{
804 struct igb_q_vector *q_vector;
805
806 q_vector = adapter->q_vector[v_idx];
807 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
808 q_vector->tx_ring->q_vector = q_vector;
809 q_vector->itr_val = adapter->itr;
810}
811
812/**
813 * igb_map_ring_to_vector - maps allocated queues to vectors
814 *
815 * This function maps the recently allocated queues to vectors.
816 **/
817static int igb_map_ring_to_vector(struct igb_adapter *adapter)
818{
819 int i;
820 int v_idx = 0;
821
822 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
823 (adapter->num_q_vectors < adapter->num_tx_queues))
824 return -ENOMEM;
825
826 if (adapter->num_q_vectors >=
827 (adapter->num_rx_queues + adapter->num_tx_queues)) {
828 for (i = 0; i < adapter->num_rx_queues; i++)
829 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
830 for (i = 0; i < adapter->num_tx_queues; i++)
831 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
832 } else {
833 for (i = 0; i < adapter->num_rx_queues; i++) {
834 if (i < adapter->num_tx_queues)
835 igb_map_tx_ring_to_vector(adapter, i, v_idx);
836 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
837 }
838 for (; i < adapter->num_tx_queues; i++)
839 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
840 }
841 return 0;
842}
843
844/**
845 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
846 *
847 * This function initializes the interrupts and allocates all of the queues.
848 **/
849static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
850{
851 struct pci_dev *pdev = adapter->pdev;
852 int err;
853
854 igb_set_interrupt_capability(adapter);
855
856 err = igb_alloc_q_vectors(adapter);
857 if (err) {
858 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
859 goto err_alloc_q_vectors;
860 }
861
862 err = igb_alloc_queues(adapter);
863 if (err) {
864 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
865 goto err_alloc_queues;
866 }
867
868 err = igb_map_ring_to_vector(adapter);
869 if (err) {
870 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
871 goto err_map_queues;
872 }
873
874
875 return 0;
876err_map_queues:
877 igb_free_queues(adapter);
878err_alloc_queues:
879 igb_free_q_vectors(adapter);
880err_alloc_q_vectors:
881 igb_reset_interrupt_capability(adapter);
882 return err;
883}
884
9d5c8243
AK		 885/**
886 * igb_request_irq - initialize interrupts
887 *
888 * Attempts to configure interrupts using the best available
889 * capabilities of the hardware and kernel.
890 **/
891static int igb_request_irq(struct igb_adapter *adapter)
892{
893 struct net_device *netdev = adapter->netdev;
047e0030 894 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 895 struct e1000_hw *hw = &adapter->hw;
896 int err = 0;
897
898 if (adapter->msix_entries) {
899 err = igb_request_msix(adapter);
844290e5 900 if (!err)
9d5c8243 901 goto request_done;
9d5c8243 902 /* fall back to MSI */
047e0030 903 igb_clear_interrupt_scheme(adapter);
9d5c8243 904 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 905 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 906 igb_free_all_tx_resources(adapter);
907 igb_free_all_rx_resources(adapter);
047e0030 908 adapter->num_tx_queues = 1;
9d5c8243 909 adapter->num_rx_queues = 1;
047e0030
AD		 910 adapter->num_q_vectors = 1;
911 err = igb_alloc_q_vectors(adapter);
912 if (err) {
913 dev_err(&pdev->dev,
914 "Unable to allocate memory for vectors\n");
915 goto request_done;
916 }
917 err = igb_alloc_queues(adapter);
918 if (err) {
919 dev_err(&pdev->dev,
920 "Unable to allocate memory for queues\n");
921 igb_free_q_vectors(adapter);
922 goto request_done;
923 }
924 igb_setup_all_tx_resources(adapter);
925 igb_setup_all_rx_resources(adapter);
844290e5 926 } else {
2d064c06
AD		 927 switch (hw->mac.type) {
928 case e1000_82575:
929 wr32(E1000_MSIXBM(0),
047e0030
AD		 930 (E1000_EICR_RX_QUEUE0 |
931 E1000_EICR_TX_QUEUE0 |
932 E1000_EIMS_OTHER));
2d064c06
AD		 933 break;
934 case e1000_82576:
935 wr32(E1000_IVAR0, E1000_IVAR_VALID);
936 break;
937 default:
938 break;
939 }
9d5c8243 940 }
844290e5 941
7dfc16fa 942 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 943 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 944 netdev->name, adapter);
9d5c8243
AK		 945 if (!err)
946 goto request_done;
047e0030 947
9d5c8243
AK		 948 /* fall back to legacy interrupts */
949 igb_reset_interrupt_capability(adapter);
7dfc16fa 950 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 951 }
952
953 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 954 netdev->name, adapter);
9d5c8243 955
6cb5e577 956 if (err)
9d5c8243
AK		 957 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
958 err);
9d5c8243
AK		 959
960request_done:
961 return err;
962}
963
964static void igb_free_irq(struct igb_adapter *adapter)
965{
9d5c8243
AK		 966 if (adapter->msix_entries) {
967 int vector = 0, i;
968
047e0030 969 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 970
047e0030
AD		 971 for (i = 0; i < adapter->num_q_vectors; i++) {
972 struct igb_q_vector *q_vector = adapter->q_vector[i];
973 free_irq(adapter->msix_entries[vector++].vector,
974 q_vector);
975 }
976 } else {
977 free_irq(adapter->pdev->irq, adapter);
9d5c8243 978 }
9d5c8243
AK		 979}
980
981/**
982 * igb_irq_disable - Mask off interrupt generation on the NIC
983 * @adapter: board private structure
984 **/
985static void igb_irq_disable(struct igb_adapter *adapter)
986{
987 struct e1000_hw *hw = &adapter->hw;
988
989 if (adapter->msix_entries) {
2dfd1212
AD		 990 u32 regval = rd32(E1000_EIAM);
991 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
992 wr32(E1000_EIMC, adapter->eims_enable_mask);
993 regval = rd32(E1000_EIAC);
994 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 995 }
844290e5
PW		 996
997 wr32(E1000_IAM, 0);
9d5c8243
AK		 998 wr32(E1000_IMC, ~0);
999 wrfl();
1000 synchronize_irq(adapter->pdev->irq);
1001}
1002
1003/**
1004 * igb_irq_enable - Enable default interrupt generation settings
1005 * @adapter: board private structure
1006 **/
1007static void igb_irq_enable(struct igb_adapter *adapter)
1008{
1009 struct e1000_hw *hw = &adapter->hw;
1010
1011 if (adapter->msix_entries) {
2dfd1212
AD		 1012 u32 regval = rd32(E1000_EIAC);
1013 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1014 regval = rd32(E1000_EIAM);
1015 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1016 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 1017 if (adapter->vfs_allocated_count)
1018 wr32(E1000_MBVFIMR, 0xFF);
1019 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
1020 E1000_IMS_DOUTSYNC));
844290e5
PW		 1021 } else {
1022 wr32(E1000_IMS, IMS_ENABLE_MASK);
1023 wr32(E1000_IAM, IMS_ENABLE_MASK);
1024 }
9d5c8243
AK		 1025}
1026
1027static void igb_update_mng_vlan(struct igb_adapter *adapter)
1028{
1029 struct net_device *netdev = adapter->netdev;
1030 u16 vid = adapter->hw.mng_cookie.vlan_id;
1031 u16 old_vid = adapter->mng_vlan_id;
1032 if (adapter->vlgrp) {
1033 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
1034 if (adapter->hw.mng_cookie.status &
1035 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1036 igb_vlan_rx_add_vid(netdev, vid);
1037 adapter->mng_vlan_id = vid;
1038 } else
1039 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1040
1041 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1042 (vid != old_vid) &&
1043 !vlan_group_get_device(adapter->vlgrp, old_vid))
1044 igb_vlan_rx_kill_vid(netdev, old_vid);
1045 } else
1046 adapter->mng_vlan_id = vid;
1047 }
1048}
1049
1050/**
1051 * igb_release_hw_control - release control of the h/w to f/w
1052 * @adapter: address of board private structure
1053 *
1054 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1055 * For ASF and Pass Through versions of f/w this means that the
1056 * driver is no longer loaded.
1057 *
1058 **/
1059static void igb_release_hw_control(struct igb_adapter *adapter)
1060{
1061 struct e1000_hw *hw = &adapter->hw;
1062 u32 ctrl_ext;
1063
1064 /* Let firmware take over control of h/w */
1065 ctrl_ext = rd32(E1000_CTRL_EXT);
1066 wr32(E1000_CTRL_EXT,
1067 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1068}
1069
1070
1071/**
1072 * igb_get_hw_control - get control of the h/w from f/w
1073 * @adapter: address of board private structure
1074 *
1075 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1076 * For ASF and Pass Through versions of f/w this means that
1077 * the driver is loaded.
1078 *
1079 **/
1080static void igb_get_hw_control(struct igb_adapter *adapter)
1081{
1082 struct e1000_hw *hw = &adapter->hw;
1083 u32 ctrl_ext;
1084
1085 /* Let firmware know the driver has taken over */
1086 ctrl_ext = rd32(E1000_CTRL_EXT);
1087 wr32(E1000_CTRL_EXT,
1088 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1089}
1090
9d5c8243
AK		 1091/**
1092 * igb_configure - configure the hardware for RX and TX
1093 * @adapter: private board structure
1094 **/
1095static void igb_configure(struct igb_adapter *adapter)
1096{
1097 struct net_device *netdev = adapter->netdev;
1098 int i;
1099
1100 igb_get_hw_control(adapter);
ff41f8dc 1101 igb_set_rx_mode(netdev);
9d5c8243
AK		 1102
1103 igb_restore_vlan(adapter);
9d5c8243 1104
85b430b4 1105 igb_setup_tctl(adapter);
9d5c8243 1106 igb_setup_rctl(adapter);
85b430b4
AD		 1107
1108 igb_configure_tx(adapter);
9d5c8243 1109 igb_configure_rx(adapter);
662d7205
AD		 1110
1111 igb_rx_fifo_flush_82575(&adapter->hw);
1112
c493ea45 1113 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1114 * at least 1 descriptor unused to make sure
1115 * next_to_use != next_to_clean */
1116 for (i = 0; i < adapter->num_rx_queues; i++) {
1117 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1118 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1119 }
1120
1121
1122 adapter->tx_queue_len = netdev->tx_queue_len;
1123}
1124
1125
1126/**
1127 * igb_up - Open the interface and prepare it to handle traffic
1128 * @adapter: board private structure
1129 **/
1130
1131int igb_up(struct igb_adapter *adapter)
1132{
1133 struct e1000_hw *hw = &adapter->hw;
1134 int i;
1135
1136 /* hardware has been reset, we need to reload some things */
1137 igb_configure(adapter);
1138
1139 clear_bit(__IGB_DOWN, &adapter->state);
1140
047e0030
AD		 1141 for (i = 0; i < adapter->num_q_vectors; i++) {
1142 struct igb_q_vector *q_vector = adapter->q_vector[i];
1143 napi_enable(&q_vector->napi);
1144 }
844290e5 1145 if (adapter->msix_entries)
9d5c8243 1146 igb_configure_msix(adapter);
9d5c8243 1147
4ae196df 1148 igb_vmm_control(adapter);
e1739522
AD		 1149 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1150
9d5c8243
AK		 1151 /* Clear any pending interrupts. */
1152 rd32(E1000_ICR);
1153 igb_irq_enable(adapter);
1154
4cb9be7a
JB		 1155 netif_tx_start_all_queues(adapter->netdev);
1156
9d5c8243
AK		 1157 /* Fire a link change interrupt to start the watchdog. */
1158 wr32(E1000_ICS, E1000_ICS_LSC);
1159 return 0;
1160}
1161
1162void igb_down(struct igb_adapter *adapter)
1163{
1164 struct e1000_hw *hw = &adapter->hw;
1165 struct net_device *netdev = adapter->netdev;
1166 u32 tctl, rctl;
1167 int i;
1168
1169 /* signal that we're down so the interrupt handler does not
1170 * reschedule our watchdog timer */
1171 set_bit(__IGB_DOWN, &adapter->state);
1172
1173 /* disable receives in the hardware */
1174 rctl = rd32(E1000_RCTL);
1175 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1176 /* flush and sleep below */
1177
fd2ea0a7 1178 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1179
1180 /* disable transmits in the hardware */
1181 tctl = rd32(E1000_TCTL);
1182 tctl &= ~E1000_TCTL_EN;
1183 wr32(E1000_TCTL, tctl);
1184 /* flush both disables and wait for them to finish */
1185 wrfl();
1186 msleep(10);
1187
047e0030
AD		 1188 for (i = 0; i < adapter->num_q_vectors; i++) {
1189 struct igb_q_vector *q_vector = adapter->q_vector[i];
1190 napi_disable(&q_vector->napi);
1191 }
9d5c8243 1192
9d5c8243
AK		 1193 igb_irq_disable(adapter);
1194
1195 del_timer_sync(&adapter->watchdog_timer);
1196 del_timer_sync(&adapter->phy_info_timer);
1197
1198 netdev->tx_queue_len = adapter->tx_queue_len;
1199 netif_carrier_off(netdev);
04fe6358
AD		 1200
1201 /* record the stats before reset*/
1202 igb_update_stats(adapter);
1203
9d5c8243
AK		 1204 adapter->link_speed = 0;
1205 adapter->link_duplex = 0;
1206
3023682e
JK		 1207 if (!pci_channel_offline(adapter->pdev))
1208 igb_reset(adapter);
9d5c8243
AK		 1209 igb_clean_all_tx_rings(adapter);
1210 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1211#ifdef CONFIG_IGB_DCA
1212
1213 /* since we reset the hardware DCA settings were cleared */
1214 igb_setup_dca(adapter);
1215#endif
9d5c8243
AK		 1216}
1217
1218void igb_reinit_locked(struct igb_adapter *adapter)
1219{
1220 WARN_ON(in_interrupt());
1221 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1222 msleep(1);
1223 igb_down(adapter);
1224 igb_up(adapter);
1225 clear_bit(__IGB_RESETTING, &adapter->state);
1226}
1227
1228void igb_reset(struct igb_adapter *adapter)
1229{
1230 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1231 struct e1000_mac_info *mac = &hw->mac;
1232 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1233 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1234 u16 hwm;
1235
1236 /* Repartition Pba for greater than 9k mtu
1237 * To take effect CTRL.RST is required.
1238 */
fa4dfae0
AD		 1239 switch (mac->type) {
1240 case e1000_82576:
2d064c06 1241 pba = E1000_PBA_64K;
fa4dfae0
AD		 1242 break;
1243 case e1000_82575:
1244 default:
1245 pba = E1000_PBA_34K;
1246 break;
2d064c06 1247 }
9d5c8243 1248
2d064c06
AD		 1249 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1250 (mac->type < e1000_82576)) {
9d5c8243
AK		 1251 /* adjust PBA for jumbo frames */
1252 wr32(E1000_PBA, pba);
1253
1254 /* To maintain wire speed transmits, the Tx FIFO should be
1255 * large enough to accommodate two full transmit packets,
1256 * rounded up to the next 1KB and expressed in KB. Likewise,
1257 * the Rx FIFO should be large enough to accommodate at least
1258 * one full receive packet and is similarly rounded up and
1259 * expressed in KB. */
1260 pba = rd32(E1000_PBA);
1261 /* upper 16 bits has Tx packet buffer allocation size in KB */
1262 tx_space = pba >> 16;
1263 /* lower 16 bits has Rx packet buffer allocation size in KB */
1264 pba &= 0xffff;
1265 /* the tx fifo also stores 16 bytes of information about the tx
1266 * but don't include ethernet FCS because hardware appends it */
1267 min_tx_space = (adapter->max_frame_size +
85e8d004 1268 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1269 ETH_FCS_LEN) * 2;
1270 min_tx_space = ALIGN(min_tx_space, 1024);
1271 min_tx_space >>= 10;
1272 /* software strips receive CRC, so leave room for it */
1273 min_rx_space = adapter->max_frame_size;
1274 min_rx_space = ALIGN(min_rx_space, 1024);
1275 min_rx_space >>= 10;
1276
1277 /* If current Tx allocation is less than the min Tx FIFO size,
1278 * and the min Tx FIFO size is less than the current Rx FIFO
1279 * allocation, take space away from current Rx allocation */
1280 if (tx_space < min_tx_space &&
1281 ((min_tx_space - tx_space) < pba)) {
1282 pba = pba - (min_tx_space - tx_space);
1283
1284 /* if short on rx space, rx wins and must trump tx
1285 * adjustment */
1286 if (pba < min_rx_space)
1287 pba = min_rx_space;
1288 }
2d064c06 1289 wr32(E1000_PBA, pba);
9d5c8243 1290 }
9d5c8243
AK		 1291
1292 /* flow control settings */
1293 /* The high water mark must be low enough to fit one full frame
1294 * (or the size used for early receive) above it in the Rx FIFO.
1295 * Set it to the lower of:
1296 * - 90% of the Rx FIFO size, or
1297 * - the full Rx FIFO size minus one full frame */
1298 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1299 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1300
2d064c06
AD		 1301 if (mac->type < e1000_82576) {
1302 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1303 fc->low_water = fc->high_water - 8;
1304 } else {
1305 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1306 fc->low_water = fc->high_water - 16;
1307 }
9d5c8243
AK		 1308 fc->pause_time = 0xFFFF;
1309 fc->send_xon = 1;
0cce119a 1310 fc->current_mode = fc->requested_mode;
9d5c8243 1311
4ae196df
AD		 1312 /* disable receive for all VFs and wait one second */
1313 if (adapter->vfs_allocated_count) {
1314 int i;
1315 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1316 adapter->vf_data[i].clear_to_send = false;
1317
1318 /* ping all the active vfs to let them know we are going down */
1319 igb_ping_all_vfs(adapter);
1320
1321 /* disable transmits and receives */
1322 wr32(E1000_VFRE, 0);
1323 wr32(E1000_VFTE, 0);
1324 }
1325
9d5c8243
AK		 1326 /* Allow time for pending master requests to run */
1327 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1328 wr32(E1000_WUC, 0);
1329
1330 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1331 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1332
1333 igb_update_mng_vlan(adapter);
1334
1335 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1336 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1337
1338 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1339 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1340}
1341
2e5c6922
SH		 1342static const struct net_device_ops igb_netdev_ops = {
1343 .ndo_open = igb_open,
1344 .ndo_stop = igb_close,
00829823 1345 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1346 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1347 .ndo_set_rx_mode = igb_set_rx_mode,
1348 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1349 .ndo_set_mac_address = igb_set_mac,
1350 .ndo_change_mtu = igb_change_mtu,
1351 .ndo_do_ioctl = igb_ioctl,
1352 .ndo_tx_timeout = igb_tx_timeout,
1353 .ndo_validate_addr = eth_validate_addr,
1354 .ndo_vlan_rx_register = igb_vlan_rx_register,
1355 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1356 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1357#ifdef CONFIG_NET_POLL_CONTROLLER
1358 .ndo_poll_controller = igb_netpoll,
1359#endif
1360};
1361
9d5c8243
AK		 1362/**
1363 * igb_probe - Device Initialization Routine
1364 * @pdev: PCI device information struct
1365 * @ent: entry in igb_pci_tbl
1366 *
1367 * Returns 0 on success, negative on failure
1368 *
1369 * igb_probe initializes an adapter identified by a pci_dev structure.
1370 * The OS initialization, configuring of the adapter private structure,
1371 * and a hardware reset occur.
1372 **/
1373static int __devinit igb_probe(struct pci_dev *pdev,
1374 const struct pci_device_id *ent)
1375{
1376 struct net_device *netdev;
1377 struct igb_adapter *adapter;
1378 struct e1000_hw *hw;
1379 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1380 unsigned long mmio_start, mmio_len;
2d6a5e95 1381 int err, pci_using_dac;
682337fe 1382 u16 eeprom_data = 0;
9d5c8243
AK		 1383 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1384 u32 part_num;
1385
aed5dec3 1386 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1387 if (err)
1388 return err;
1389
1390 pci_using_dac = 0;
6a35528a 1391 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1392 if (!err) {
6a35528a 1393 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1394 if (!err)
1395 pci_using_dac = 1;
1396 } else {
284901a9 1397 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1398 if (err) {
284901a9 1399 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1400 if (err) {
1401 dev_err(&pdev->dev, "No usable DMA "
1402 "configuration, aborting\n");
1403 goto err_dma;
1404 }
1405 }
1406 }
1407
aed5dec3
AD		 1408 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1409 IORESOURCE_MEM),
1410 igb_driver_name);
9d5c8243
AK		 1411 if (err)
1412 goto err_pci_reg;
1413
19d5afd4 1414 pci_enable_pcie_error_reporting(pdev);
40a914fa 1415
9d5c8243 1416 pci_set_master(pdev);
c682fc23 1417 pci_save_state(pdev);
9d5c8243
AK		 1418
1419 err = -ENOMEM;
1bfaf07b
AD		 1420 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1421 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1422 if (!netdev)
1423 goto err_alloc_etherdev;
1424
1425 SET_NETDEV_DEV(netdev, &pdev->dev);
1426
1427 pci_set_drvdata(pdev, netdev);
1428 adapter = netdev_priv(netdev);
1429 adapter->netdev = netdev;
1430 adapter->pdev = pdev;
1431 hw = &adapter->hw;
1432 hw->back = adapter;
1433 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1434
1435 mmio_start = pci_resource_start(pdev, 0);
1436 mmio_len = pci_resource_len(pdev, 0);
1437
1438 err = -EIO;
28b0759c
AD		 1439 hw->hw_addr = ioremap(mmio_start, mmio_len);
1440 if (!hw->hw_addr)
9d5c8243
AK		 1441 goto err_ioremap;
1442
2e5c6922 1443 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1444 igb_set_ethtool_ops(netdev);
9d5c8243 1445 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1446
1447 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1448
1449 netdev->mem_start = mmio_start;
1450 netdev->mem_end = mmio_start + mmio_len;
1451
9d5c8243
AK		 1452 /* PCI config space info */
1453 hw->vendor_id = pdev->vendor;
1454 hw->device_id = pdev->device;
1455 hw->revision_id = pdev->revision;
1456 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1457 hw->subsystem_device_id = pdev->subsystem_device;
1458
1459 /* setup the private structure */
1460 hw->back = adapter;
1461 /* Copy the default MAC, PHY and NVM function pointers */
1462 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1463 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1464 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1465 /* Initialize skew-specific constants */
1466 err = ei->get_invariants(hw);
1467 if (err)
450c87c8 1468 goto err_sw_init;
9d5c8243 1469
2a3abf6d
AD		 1470#ifdef CONFIG_PCI_IOV
1471 /* since iov functionality isn't critical to base device function we
1472 * can accept failure. If it fails we don't allow iov to be enabled */
1473 if (hw->mac.type == e1000_82576) {
1474 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1475 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1476 int i;
1477 unsigned char mac_addr[ETH_ALEN];
1478
9ca046d5 1479 if (num_vfs) {
2a3abf6d
AD		 1480 adapter->vf_data = kcalloc(num_vfs,
1481 sizeof(struct vf_data_storage),
1482 GFP_KERNEL);
9ca046d5
AD		 1483 if (!adapter->vf_data) {
1484 dev_err(&pdev->dev,
1485 "Could not allocate VF private data - "
1486 "IOV enable failed\n");
2a3abf6d 1487 } else {
9ca046d5
AD		 1488 err = pci_enable_sriov(pdev, num_vfs);
1489 if (!err) {
1490 adapter->vfs_allocated_count = num_vfs;
1491 dev_info(&pdev->dev,
1492 "%d vfs allocated\n",
1493 num_vfs);
1494 for (i = 0;
1495 i < adapter->vfs_allocated_count;
1496 i++) {
1497 random_ether_addr(mac_addr);
1498 igb_set_vf_mac(adapter, i,
1499 mac_addr);
1500 }
1501 } else {
1502 kfree(adapter->vf_data);
1503 adapter->vf_data = NULL;
1504 }
2a3abf6d
AD		 1505 }
1506 }
1507 }
1508
1509#endif
450c87c8 1510 /* setup the private structure */
9d5c8243
AK		 1511 err = igb_sw_init(adapter);
1512 if (err)
1513 goto err_sw_init;
1514
1515 igb_get_bus_info_pcie(hw);
1516
7dfc16fa
AD		 1517 /* set flags */
1518 switch (hw->mac.type) {
7dfc16fa 1519 case e1000_82575:
7dfc16fa
AD		 1520 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1521 break;
bbd98fe4 1522 case e1000_82576:
7dfc16fa
AD		 1523 default:
1524 break;
1525 }
1526
9d5c8243
AK		 1527 hw->phy.autoneg_wait_to_complete = false;
1528 hw->mac.adaptive_ifs = true;
1529
1530 /* Copper options */
1531 if (hw->phy.media_type == e1000_media_type_copper) {
1532 hw->phy.mdix = AUTO_ALL_MODES;
1533 hw->phy.disable_polarity_correction = false;
1534 hw->phy.ms_type = e1000_ms_hw_default;
1535 }
1536
1537 if (igb_check_reset_block(hw))
1538 dev_info(&pdev->dev,
1539 "PHY reset is blocked due to SOL/IDER session.\n");
1540
1541 netdev->features = NETIF_F_SG |
7d8eb29e 1542 NETIF_F_IP_CSUM |
9d5c8243
AK		 1543 NETIF_F_HW_VLAN_TX |
1544 NETIF_F_HW_VLAN_RX |
1545 NETIF_F_HW_VLAN_FILTER;
1546
7d8eb29e 1547 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1548 netdev->features |= NETIF_F_TSO;
9d5c8243 1549 netdev->features |= NETIF_F_TSO6;
48f29ffc 1550
5c0999b7 1551 netdev->features |= NETIF_F_GRO;
d3352520 1552
48f29ffc
JK		 1553 netdev->vlan_features |= NETIF_F_TSO;
1554 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1555 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1556 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1557 netdev->vlan_features |= NETIF_F_SG;
1558
9d5c8243
AK		 1559 if (pci_using_dac)
1560 netdev->features |= NETIF_F_HIGHDMA;
1561
b9473560
JB		 1562 if (adapter->hw.mac.type == e1000_82576)
1563 netdev->features |= NETIF_F_SCTP_CSUM;
1564
9d5c8243
AK		 1565 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1566
1567 /* before reading the NVM, reset the controller to put the device in a
1568 * known good starting state */
1569 hw->mac.ops.reset_hw(hw);
1570
1571 /* make sure the NVM is good */
1572 if (igb_validate_nvm_checksum(hw) < 0) {
1573 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1574 err = -EIO;
1575 goto err_eeprom;
1576 }
1577
1578 /* copy the MAC address out of the NVM */
1579 if (hw->mac.ops.read_mac_addr(hw))
1580 dev_err(&pdev->dev, "NVM Read Error\n");
1581
1582 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1583 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1584
1585 if (!is_valid_ether_addr(netdev->perm_addr)) {
1586 dev_err(&pdev->dev, "Invalid MAC Address\n");
1587 err = -EIO;
1588 goto err_eeprom;
1589 }
1590
0e340485
AD		 1591 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1592 (unsigned long) adapter);
1593 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1594 (unsigned long) adapter);
9d5c8243
AK		 1595
1596 INIT_WORK(&adapter->reset_task, igb_reset_task);
1597 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1598
450c87c8 1599 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1600 adapter->fc_autoneg = true;
1601 hw->mac.autoneg = true;
1602 hw->phy.autoneg_advertised = 0x2f;
1603
0cce119a
AD		 1604 hw->fc.requested_mode = e1000_fc_default;
1605 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1606
cbd347ad 1607 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1608 adapter->itr = IGB_START_ITR;
1609
1610 igb_validate_mdi_setting(hw);
1611
9d5c8243
AK		 1612 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1613 * enable the ACPI Magic Packet filter
1614 */
1615
a2cf8b6c 1616 if (hw->bus.func == 0)
312c75ae 1617 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1618 else if (hw->bus.func == 1)
1619 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1620
1621 if (eeprom_data & eeprom_apme_mask)
1622 adapter->eeprom_wol |= E1000_WUFC_MAG;
1623
1624 /* now that we have the eeprom settings, apply the special cases where
1625 * the eeprom may be wrong or the board simply won't support wake on
1626 * lan on a particular port */
1627 switch (pdev->device) {
1628 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1629 adapter->eeprom_wol = 0;
1630 break;
1631 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1632 case E1000_DEV_ID_82576_FIBER:
1633 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1634 /* Wake events only supported on port A for dual fiber
1635 * regardless of eeprom setting */
1636 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1637 adapter->eeprom_wol = 0;
1638 break;
c8ea5ea9
AD		 1639 case E1000_DEV_ID_82576_QUAD_COPPER:
1640 /* if quad port adapter, disable WoL on all but port A */
1641 if (global_quad_port_a != 0)
1642 adapter->eeprom_wol = 0;
1643 else
1644 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1645 /* Reset for multiple quad port adapters */
1646 if (++global_quad_port_a == 4)
1647 global_quad_port_a = 0;
1648 break;
9d5c8243
AK		 1649 }
1650
1651 /* initialize the wol settings based on the eeprom settings */
1652 adapter->wol = adapter->eeprom_wol;
e1b86d84 1653 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1654
1655 /* reset the hardware with the new settings */
1656 igb_reset(adapter);
1657
1658 /* let the f/w know that the h/w is now under the control of the
1659 * driver. */
1660 igb_get_hw_control(adapter);
1661
9d5c8243
AK		 1662 strcpy(netdev->name, "eth%d");
1663 err = register_netdev(netdev);
1664 if (err)
1665 goto err_register;
1666
b168dfc5
JB		 1667 /* carrier off reporting is important to ethtool even BEFORE open */
1668 netif_carrier_off(netdev);
1669
421e02f0 1670#ifdef CONFIG_IGB_DCA
bbd98fe4 1671 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1672 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1673 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1674 igb_setup_dca(adapter);
1675 }
1676#endif
1677
38c845c7
PO		 1678 /*
1679 * Initialize hardware timer: we keep it running just in case
1680 * that some program needs it later on.
1681 */
1682 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1683 adapter->cycles.read = igb_read_clock;
1684 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1685 adapter->cycles.mult = 1;
1686 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1687 wr32(E1000_TIMINCA,
1688 (1<<24) |
1689 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1690#if 0
1691 /*
1692 * Avoid rollover while we initialize by resetting the time counter.
1693 */
1694 wr32(E1000_SYSTIML, 0x00000000);
1695 wr32(E1000_SYSTIMH, 0x00000000);
1696#else
1697 /*
1698 * Set registers so that rollover occurs soon to test this.
1699 */
1700 wr32(E1000_SYSTIML, 0x00000000);
1701 wr32(E1000_SYSTIMH, 0xFF800000);
1702#endif
1703 wrfl();
1704 timecounter_init(&adapter->clock,
1705 &adapter->cycles,
1706 ktime_to_ns(ktime_get_real()));
1707
33af6bcc
PO		 1708 /*
1709 * Synchronize our NIC clock against system wall clock. NIC
1710 * time stamp reading requires ~3us per sample, each sample
1711 * was pretty stable even under load => only require 10
1712 * samples for each offset comparison.
1713 */
1714 memset(&adapter->compare, 0, sizeof(adapter->compare));
1715 adapter->compare.source = &adapter->clock;
1716 adapter->compare.target = ktime_get_real;
1717 adapter->compare.num_samples = 10;
1718 timecompare_update(&adapter->compare, 0);
1719
38c845c7
PO		 1720#ifdef DEBUG
1721 {
1722 char buffer[160];
1723 printk(KERN_DEBUG
1724 "igb: %s: hw %p initialized timer\n",
1725 igb_get_time_str(adapter, buffer),
1726 &adapter->hw);
1727 }
1728#endif
1729
9d5c8243
AK		 1730 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1731 /* print bus type/speed/width info */
7c510e4b 1732 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1733 netdev->name,
1734 ((hw->bus.speed == e1000_bus_speed_2500)
1735 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1736 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1737 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1738 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1739 "unknown"),
7c510e4b 1740 netdev->dev_addr);
9d5c8243
AK		 1741
1742 igb_read_part_num(hw, &part_num);
1743 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1744 (part_num >> 8), (part_num & 0xff));
1745
1746 dev_info(&pdev->dev,
1747 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1748 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1749 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1750 adapter->num_rx_queues, adapter->num_tx_queues);
1751
9d5c8243
AK		 1752 return 0;
1753
1754err_register:
1755 igb_release_hw_control(adapter);
1756err_eeprom:
1757 if (!igb_check_reset_block(hw))
f5f4cf08 1758 igb_reset_phy(hw);
9d5c8243
AK		 1759
1760 if (hw->flash_address)
1761 iounmap(hw->flash_address);
9d5c8243 1762err_sw_init:
047e0030 1763 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1764 iounmap(hw->hw_addr);
1765err_ioremap:
1766 free_netdev(netdev);
1767err_alloc_etherdev:
aed5dec3
AD		 1768 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1769 IORESOURCE_MEM));
9d5c8243
AK		 1770err_pci_reg:
1771err_dma:
1772 pci_disable_device(pdev);
1773 return err;
1774}
1775
1776/**
1777 * igb_remove - Device Removal Routine
1778 * @pdev: PCI device information struct
1779 *
1780 * igb_remove is called by the PCI subsystem to alert the driver
1781 * that it should release a PCI device. The could be caused by a
1782 * Hot-Plug event, or because the driver is going to be removed from
1783 * memory.
1784 **/
1785static void __devexit igb_remove(struct pci_dev *pdev)
1786{
1787 struct net_device *netdev = pci_get_drvdata(pdev);
1788 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1789 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1790
1791 /* flush_scheduled work may reschedule our watchdog task, so
1792 * explicitly disable watchdog tasks from being rescheduled */
1793 set_bit(__IGB_DOWN, &adapter->state);
1794 del_timer_sync(&adapter->watchdog_timer);
1795 del_timer_sync(&adapter->phy_info_timer);
1796
1797 flush_scheduled_work();
1798
421e02f0 1799#ifdef CONFIG_IGB_DCA
7dfc16fa 1800 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1801 dev_info(&pdev->dev, "DCA disabled\n");
1802 dca_remove_requester(&pdev->dev);
7dfc16fa 1803 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1804 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1805 }
1806#endif
1807
9d5c8243
AK		 1808 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1809 * would have already happened in close and is redundant. */
1810 igb_release_hw_control(adapter);
1811
1812 unregister_netdev(netdev);
1813
f5f4cf08
AD		 1814 if (!igb_check_reset_block(&adapter->hw))
1815 igb_reset_phy(&adapter->hw);
9d5c8243 1816
047e0030 1817 igb_clear_interrupt_scheme(adapter);
9d5c8243 1818
37680117
AD		 1819#ifdef CONFIG_PCI_IOV
1820 /* reclaim resources allocated to VFs */
1821 if (adapter->vf_data) {
1822 /* disable iov and allow time for transactions to clear */
1823 pci_disable_sriov(pdev);
1824 msleep(500);
1825
1826 kfree(adapter->vf_data);
1827 adapter->vf_data = NULL;
1828 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1829 msleep(100);
1830 dev_info(&pdev->dev, "IOV Disabled\n");
1831 }
1832#endif
28b0759c
AD		 1833 iounmap(hw->hw_addr);
1834 if (hw->flash_address)
1835 iounmap(hw->flash_address);
aed5dec3
AD		 1836 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1837 IORESOURCE_MEM));
9d5c8243
AK		 1838
1839 free_netdev(netdev);
1840
19d5afd4 1841 pci_disable_pcie_error_reporting(pdev);
40a914fa 1842
9d5c8243
AK		 1843 pci_disable_device(pdev);
1844}
1845
1846/**
1847 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1848 * @adapter: board private structure to initialize
1849 *
1850 * igb_sw_init initializes the Adapter private data structure.
1851 * Fields are initialized based on PCI device information and
1852 * OS network device settings (MTU size).
1853 **/
1854static int __devinit igb_sw_init(struct igb_adapter *adapter)
1855{
1856 struct e1000_hw *hw = &adapter->hw;
1857 struct net_device *netdev = adapter->netdev;
1858 struct pci_dev *pdev = adapter->pdev;
1859
1860 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1861
68fd9910
AD		 1862 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1863 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243 1864 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9d5c8243
AK		 1865 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1866 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1867
661086df
PWJ		 1868 /* This call may decrease the number of queues depending on
1869 * interrupt mode. */
047e0030 1870 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1871 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1872 return -ENOMEM;
1873 }
1874
1875 /* Explicitly disable IRQ since the NIC can be in any state. */
1876 igb_irq_disable(adapter);
1877
1878 set_bit(__IGB_DOWN, &adapter->state);
1879 return 0;
1880}
1881
1882/**
1883 * igb_open - Called when a network interface is made active
1884 * @netdev: network interface device structure
1885 *
1886 * Returns 0 on success, negative value on failure
1887 *
1888 * The open entry point is called when a network interface is made
1889 * active by the system (IFF_UP). At this point all resources needed
1890 * for transmit and receive operations are allocated, the interrupt
1891 * handler is registered with the OS, the watchdog timer is started,
1892 * and the stack is notified that the interface is ready.
1893 **/
1894static int igb_open(struct net_device *netdev)
1895{
1896 struct igb_adapter *adapter = netdev_priv(netdev);
1897 struct e1000_hw *hw = &adapter->hw;
1898 int err;
1899 int i;
1900
1901 /* disallow open during test */
1902 if (test_bit(__IGB_TESTING, &adapter->state))
1903 return -EBUSY;
1904
b168dfc5
JB		 1905 netif_carrier_off(netdev);
1906
9d5c8243
AK		 1907 /* allocate transmit descriptors */
1908 err = igb_setup_all_tx_resources(adapter);
1909 if (err)
1910 goto err_setup_tx;
1911
1912 /* allocate receive descriptors */
1913 err = igb_setup_all_rx_resources(adapter);
1914 if (err)
1915 goto err_setup_rx;
1916
1917 /* e1000_power_up_phy(adapter); */
1918
1919 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1920 if ((adapter->hw.mng_cookie.status &
1921 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1922 igb_update_mng_vlan(adapter);
1923
1924 /* before we allocate an interrupt, we must be ready to handle it.
1925 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1926 * as soon as we call pci_request_irq, so we have to setup our
1927 * clean_rx handler before we do so. */
1928 igb_configure(adapter);
1929
4ae196df 1930 igb_vmm_control(adapter);
e1739522
AD		 1931 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1932
9d5c8243
AK		 1933 err = igb_request_irq(adapter);
1934 if (err)
1935 goto err_req_irq;
1936
1937 /* From here on the code is the same as igb_up() */
1938 clear_bit(__IGB_DOWN, &adapter->state);
1939
047e0030
AD		 1940 for (i = 0; i < adapter->num_q_vectors; i++) {
1941 struct igb_q_vector *q_vector = adapter->q_vector[i];
1942 napi_enable(&q_vector->napi);
1943 }
9d5c8243
AK		 1944
1945 /* Clear any pending interrupts. */
1946 rd32(E1000_ICR);
844290e5
PW		 1947
1948 igb_irq_enable(adapter);
1949
d55b53ff
JK		 1950 netif_tx_start_all_queues(netdev);
1951
9d5c8243
AK		 1952 /* Fire a link status change interrupt to start the watchdog. */
1953 wr32(E1000_ICS, E1000_ICS_LSC);
1954
1955 return 0;
1956
1957err_req_irq:
1958 igb_release_hw_control(adapter);
1959 /* e1000_power_down_phy(adapter); */
1960 igb_free_all_rx_resources(adapter);
1961err_setup_rx:
1962 igb_free_all_tx_resources(adapter);
1963err_setup_tx:
1964 igb_reset(adapter);
1965
1966 return err;
1967}
1968
1969/**
1970 * igb_close - Disables a network interface
1971 * @netdev: network interface device structure
1972 *
1973 * Returns 0, this is not allowed to fail
1974 *
1975 * The close entry point is called when an interface is de-activated
1976 * by the OS. The hardware is still under the driver's control, but
1977 * needs to be disabled. A global MAC reset is issued to stop the
1978 * hardware, and all transmit and receive resources are freed.
1979 **/
1980static int igb_close(struct net_device *netdev)
1981{
1982 struct igb_adapter *adapter = netdev_priv(netdev);
1983
1984 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1985 igb_down(adapter);
1986
1987 igb_free_irq(adapter);
1988
1989 igb_free_all_tx_resources(adapter);
1990 igb_free_all_rx_resources(adapter);
1991
1992 /* kill manageability vlan ID if supported, but not if a vlan with
1993 * the same ID is registered on the host OS (let 8021q kill it) */
1994 if ((adapter->hw.mng_cookie.status &
1995 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1996 !(adapter->vlgrp &&
1997 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1998 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1999
2000 return 0;
2001}
2002
2003/**
2004 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2005 * @adapter: board private structure
2006 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2007 *
2008 * Return 0 on success, negative on failure
2009 **/
9d5c8243
AK		 2010int igb_setup_tx_resources(struct igb_adapter *adapter,
2011 struct igb_ring *tx_ring)
2012{
2013 struct pci_dev *pdev = adapter->pdev;
2014 int size;
2015
2016 size = sizeof(struct igb_buffer) * tx_ring->count;
2017 tx_ring->buffer_info = vmalloc(size);
2018 if (!tx_ring->buffer_info)
2019 goto err;
2020 memset(tx_ring->buffer_info, 0, size);
2021
2022 /* round up to nearest 4K */
85e8d004 2023 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2024 tx_ring->size = ALIGN(tx_ring->size, 4096);
2025
2026 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2027 &tx_ring->dma);
2028
2029 if (!tx_ring->desc)
2030 goto err;
2031
9d5c8243
AK		 2032 tx_ring->next_to_use = 0;
2033 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2034 return 0;
2035
2036err:
2037 vfree(tx_ring->buffer_info);
047e0030 2038 dev_err(&pdev->dev,
9d5c8243
AK		 2039 "Unable to allocate memory for the transmit descriptor ring\n");
2040 return -ENOMEM;
2041}
2042
2043/**
2044 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2045 * (Descriptors) for all queues
2046 * @adapter: board private structure
2047 *
2048 * Return 0 on success, negative on failure
2049 **/
2050static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2051{
2052 int i, err = 0;
661086df 2053 int r_idx;
9d5c8243
AK		 2054
2055 for (i = 0; i < adapter->num_tx_queues; i++) {
2056 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2057 if (err) {
2058 dev_err(&adapter->pdev->dev,
2059 "Allocation for Tx Queue %u failed\n", i);
2060 for (i--; i >= 0; i--)
3b644cf6 2061 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2062 break;
2063 }
2064 }
2065
661086df
PWJ		 2066 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2067 r_idx = i % adapter->num_tx_queues;
2068 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2069 }
9d5c8243
AK		 2070 return err;
2071}
2072
2073/**
85b430b4
AD		 2074 * igb_setup_tctl - configure the transmit control registers
2075 * @adapter: Board private structure
9d5c8243 2076 **/
85b430b4 2077static void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2078{
9d5c8243
AK		 2079 struct e1000_hw *hw = &adapter->hw;
2080 u32 tctl;
9d5c8243 2081
85b430b4
AD		 2082 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2083 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2084
2085 /* Program the Transmit Control Register */
9d5c8243
AK		 2086 tctl = rd32(E1000_TCTL);
2087 tctl &= ~E1000_TCTL_CT;
2088 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2089 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2090
2091 igb_config_collision_dist(hw);
2092
9d5c8243
AK		 2093 /* Enable transmits */
2094 tctl |= E1000_TCTL_EN;
2095
2096 wr32(E1000_TCTL, tctl);
2097}
2098
85b430b4
AD		 2099/**
2100 * igb_configure_tx_ring - Configure transmit ring after Reset
2101 * @adapter: board private structure
2102 * @ring: tx ring to configure
2103 *
2104 * Configure a transmit ring after a reset.
2105 **/
2106static void igb_configure_tx_ring(struct igb_adapter *adapter,
2107 struct igb_ring *ring)
2108{
2109 struct e1000_hw *hw = &adapter->hw;
2110 u32 txdctl;
2111 u64 tdba = ring->dma;
2112 int reg_idx = ring->reg_idx;
2113
2114 /* disable the queue */
2115 txdctl = rd32(E1000_TXDCTL(reg_idx));
2116 wr32(E1000_TXDCTL(reg_idx),
2117 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2118 wrfl();
2119 mdelay(10);
2120
2121 wr32(E1000_TDLEN(reg_idx),
2122 ring->count * sizeof(union e1000_adv_tx_desc));
2123 wr32(E1000_TDBAL(reg_idx),
2124 tdba & 0x00000000ffffffffULL);
2125 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2126
2127 ring->head = E1000_TDH(reg_idx);
2128 ring->tail = E1000_TDT(reg_idx);
2129 writel(0, hw->hw_addr + ring->tail);
2130 writel(0, hw->hw_addr + ring->head);
2131
2132 txdctl |= IGB_TX_PTHRESH;
2133 txdctl |= IGB_TX_HTHRESH << 8;
2134 txdctl |= IGB_TX_WTHRESH << 16;
2135
2136 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2137 wr32(E1000_TXDCTL(reg_idx), txdctl);
2138}
2139
2140/**
2141 * igb_configure_tx - Configure transmit Unit after Reset
2142 * @adapter: board private structure
2143 *
2144 * Configure the Tx unit of the MAC after a reset.
2145 **/
2146static void igb_configure_tx(struct igb_adapter *adapter)
2147{
2148 int i;
2149
2150 for (i = 0; i < adapter->num_tx_queues; i++)
2151 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
2152
2153 /* Setup Transmit Descriptor Settings for eop descriptor */
2154 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
2155}
2156
9d5c8243
AK		 2157/**
2158 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2159 * @adapter: board private structure
2160 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2161 *
2162 * Returns 0 on success, negative on failure
2163 **/
9d5c8243
AK		 2164int igb_setup_rx_resources(struct igb_adapter *adapter,
2165 struct igb_ring *rx_ring)
2166{
2167 struct pci_dev *pdev = adapter->pdev;
2168 int size, desc_len;
2169
2170 size = sizeof(struct igb_buffer) * rx_ring->count;
2171 rx_ring->buffer_info = vmalloc(size);
2172 if (!rx_ring->buffer_info)
2173 goto err;
2174 memset(rx_ring->buffer_info, 0, size);
2175
2176 desc_len = sizeof(union e1000_adv_rx_desc);
2177
2178 /* Round up to nearest 4K */
2179 rx_ring->size = rx_ring->count * desc_len;
2180 rx_ring->size = ALIGN(rx_ring->size, 4096);
2181
2182 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2183 &rx_ring->dma);
2184
2185 if (!rx_ring->desc)
2186 goto err;
2187
2188 rx_ring->next_to_clean = 0;
2189 rx_ring->next_to_use = 0;
9d5c8243 2190
9d5c8243
AK		 2191 return 0;
2192
2193err:
2194 vfree(rx_ring->buffer_info);
2195 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2196 "the receive descriptor ring\n");
2197 return -ENOMEM;
2198}
2199
2200/**
2201 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2202 * (Descriptors) for all queues
2203 * @adapter: board private structure
2204 *
2205 * Return 0 on success, negative on failure
2206 **/
2207static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2208{
2209 int i, err = 0;
2210
2211 for (i = 0; i < adapter->num_rx_queues; i++) {
2212 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2213 if (err) {
2214 dev_err(&adapter->pdev->dev,
2215 "Allocation for Rx Queue %u failed\n", i);
2216 for (i--; i >= 0; i--)
3b644cf6 2217 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2218 break;
2219 }
2220 }
2221
2222 return err;
2223}
2224
2225/**
2226 * igb_setup_rctl - configure the receive control registers
2227 * @adapter: Board private structure
2228 **/
2229static void igb_setup_rctl(struct igb_adapter *adapter)
2230{
2231 struct e1000_hw *hw = &adapter->hw;
2232 u32 rctl;
2233 u32 srrctl = 0;
77a22941 2234 int i;
9d5c8243
AK		 2235
2236 rctl = rd32(E1000_RCTL);
2237
2238 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2239 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2240
69d728ba 2241 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2242 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2243
87cb7e8c
AK		 2244 /*
2245 * enable stripping of CRC. It's unlikely this will break BMC
2246 * redirection as it did with e1000. Newer features require
2247 * that the HW strips the CRC.
73cd78f1 2248 */
87cb7e8c 2249 rctl |= E1000_RCTL_SECRC;
9d5c8243 2250
9b07f3d3 2251 /*
ec54d7d6 2252 * disable store bad packets and clear size bits.
9b07f3d3 2253 */
ec54d7d6 2254 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2255
6ec43fe6
AD		 2256 /* enable LPE to prevent packets larger than max_frame_size */
2257 rctl |= E1000_RCTL_LPE;
9d5c8243
AK		 2258
2259 /* 82575 and greater support packet-split where the protocol
2260 * header is placed in skb->data and the packet data is
2261 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2262 * In the case of a non-split, skb->data is linearly filled,
2263 * followed by the page buffers. Therefore, skb->data is
2264 * sized to hold the largest protocol header.
2265 */
2266 /* allocations using alloc_page take too long for regular MTU
2267 * so only enable packet split for jumbo frames */
6ec43fe6
AD		 2268 if (adapter->rx_buffer_len < IGB_RXBUFFER_1024) {
2269 srrctl = ALIGN(adapter->rx_buffer_len, 64) <<
2270 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2271#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2272 srrctl |= IGB_RXBUFFER_16384 >>
2273 E1000_SRRCTL_BSIZEPKT_SHIFT;
2274#else
2275 srrctl |= (PAGE_SIZE / 2) >>
2276 E1000_SRRCTL_BSIZEPKT_SHIFT;
2277#endif
9d5c8243
AK		 2278 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2279 } else {
6ec43fe6
AD		 2280 srrctl = ALIGN(adapter->rx_buffer_len, 1024) >>
2281 E1000_SRRCTL_BSIZEPKT_SHIFT;
9d5c8243
AK		 2282 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2283 }
2284
e1739522
AD		 2285 /* Attention!!! For SR-IOV PF driver operations you must enable
2286 * queue drop for all VF and PF queues to prevent head of line blocking
2287 * if an un-trusted VF does not provide descriptors to hardware.
2288 */
2289 if (adapter->vfs_allocated_count) {
2290 u32 vmolr;
2291
e1739522
AD		 2292 /* set all queue drop enable bits */
2293 wr32(E1000_QDE, ALL_QUEUES);
2294 srrctl |= E1000_SRRCTL_DROP_EN;
2295
2296 /* disable queue 0 to prevent tail write w/o re-config */
2297 wr32(E1000_RXDCTL(0), 0);
2298
77a22941 2299 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2300 if (rctl & E1000_RCTL_LPE)
2301 vmolr |= E1000_VMOLR_LPE;
77a22941 2302 if (adapter->num_rx_queues > 1)
e1739522 2303 vmolr |= E1000_VMOLR_RSSE;
77a22941 2304 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2305 }
2306
26bc19ec 2307 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2308 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2309 wr32(E1000_SRRCTL(j), srrctl);
2310 }
9d5c8243
AK		 2311
2312 wr32(E1000_RCTL, rctl);
2313}
2314
e1739522
AD		 2315/**
2316 * igb_rlpml_set - set maximum receive packet size
2317 * @adapter: board private structure
2318 *
2319 * Configure maximum receivable packet size.
2320 **/
2321static void igb_rlpml_set(struct igb_adapter *adapter)
2322{
2323 u32 max_frame_size = adapter->max_frame_size;
2324 struct e1000_hw *hw = &adapter->hw;
2325 u16 pf_id = adapter->vfs_allocated_count;
2326
2327 if (adapter->vlgrp)
2328 max_frame_size += VLAN_TAG_SIZE;
2329
2330 /* if vfs are enabled we set RLPML to the largest possible request
2331 * size and set the VMOLR RLPML to the size we need */
2332 if (pf_id) {
2333 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2334 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2335 }
2336
2337 wr32(E1000_RLPML, max_frame_size);
2338}
2339
2340/**
2341 * igb_configure_vt_default_pool - Configure VT default pool
2342 * @adapter: board private structure
2343 *
2344 * Configure the default pool
2345 **/
2346static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2347{
2348 struct e1000_hw *hw = &adapter->hw;
2349 u16 pf_id = adapter->vfs_allocated_count;
2350 u32 vtctl;
2351
2352 /* not in sr-iov mode - do nothing */
2353 if (!pf_id)
2354 return;
2355
2356 vtctl = rd32(E1000_VT_CTL);
2357 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2358 E1000_VT_CTL_DISABLE_DEF_POOL);
2359 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2360 wr32(E1000_VT_CTL, vtctl);
2361}
2362
85b430b4
AD		 2363/**
2364 * igb_configure_rx_ring - Configure a receive ring after Reset
2365 * @adapter: board private structure
2366 * @ring: receive ring to be configured
2367 *
2368 * Configure the Rx unit of the MAC after a reset.
2369 **/
2370static void igb_configure_rx_ring(struct igb_adapter *adapter,
2371 struct igb_ring *ring)
2372{
2373 struct e1000_hw *hw = &adapter->hw;
2374 u64 rdba = ring->dma;
2375 int reg_idx = ring->reg_idx;
2376 u32 rxdctl;
2377
2378 /* disable the queue */
2379 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2380 wr32(E1000_RXDCTL(reg_idx),
2381 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2382
2383 /* Set DMA base address registers */
2384 wr32(E1000_RDBAL(reg_idx),
2385 rdba & 0x00000000ffffffffULL);
2386 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2387 wr32(E1000_RDLEN(reg_idx),
2388 ring->count * sizeof(union e1000_adv_rx_desc));
2389
2390 /* initialize head and tail */
2391 ring->head = E1000_RDH(reg_idx);
2392 ring->tail = E1000_RDT(reg_idx);
2393 writel(0, hw->hw_addr + ring->head);
2394 writel(0, hw->hw_addr + ring->tail);
2395
2396 /* enable receive descriptor fetching */
2397 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2398 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2399 rxdctl &= 0xFFF00000;
2400 rxdctl |= IGB_RX_PTHRESH;
2401 rxdctl |= IGB_RX_HTHRESH << 8;
2402 rxdctl |= IGB_RX_WTHRESH << 16;
2403 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2404}
2405
9d5c8243
AK		 2406/**
2407 * igb_configure_rx - Configure receive Unit after Reset
2408 * @adapter: board private structure
2409 *
2410 * Configure the Rx unit of the MAC after a reset.
2411 **/
2412static void igb_configure_rx(struct igb_adapter *adapter)
2413{
9d5c8243
AK		 2414 struct e1000_hw *hw = &adapter->hw;
2415 u32 rctl, rxcsum;
9107584e 2416 int i;
9d5c8243
AK		 2417
2418 /* disable receives while setting up the descriptors */
2419 rctl = rd32(E1000_RCTL);
2420 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2421 wrfl();
2422 mdelay(10);
2423
2424 if (adapter->itr_setting > 3)
6eb5a7f1 2425 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2426
2427 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2428 * the Base and Length of the Rx Descriptor Ring */
85b430b4
AD		 2429 for (i = 0; i < adapter->num_rx_queues; i++)
2430 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2431
2432 if (adapter->num_rx_queues > 1) {
2433 u32 random[10];
2434 u32 mrqc;
2435 u32 j, shift;
2436 union e1000_reta {
2437 u32 dword;
2438 u8 bytes[4];
2439 } reta;
2440
2441 get_random_bytes(&random[0], 40);
2442
2d064c06
AD		 2443 if (hw->mac.type >= e1000_82576)
2444 shift = 0;
2445 else
2446 shift = 6;
9d5c8243
AK		 2447 for (j = 0; j < (32 * 4); j++) {
2448 reta.bytes[j & 3] =
26bc19ec 2449 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2450 if ((j & 3) == 3)
2451 writel(reta.dword,
2452 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2453 }
e1739522
AD		 2454 if (adapter->vfs_allocated_count)
2455 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2456 else
2457 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2458
2459 /* Fill out hash function seeds */
2460 for (j = 0; j < 10; j++)
2461 array_wr32(E1000_RSSRK(0), j, random[j]);
2462
2463 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2464 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2465 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2466 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2467 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2468 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2469 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2470 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2471
9d5c8243 2472 wr32(E1000_MRQC, mrqc);
2844f797 2473 } else if (adapter->vfs_allocated_count) {
e1739522 2474 /* Enable multi-queue for sr-iov */
2844f797 2475 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2476 }
2477
2844f797
AD		 2478 /* Enable Receive Checksum Offload for TCP and UDP */
2479 rxcsum = rd32(E1000_RXCSUM);
2480 /* Disable raw packet checksumming */
2481 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2482
2483 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2484 /* Enable Receive Checksum Offload for SCTP */
2485 rxcsum |= E1000_RXCSUM_CRCOFL;
2486
7beb0146 2487 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2488 wr32(E1000_RXCSUM, rxcsum);
2489
e1739522
AD		 2490 /* Set the default pool for the PF's first queue */
2491 igb_configure_vt_default_pool(adapter);
2492
68d480c4
AD		 2493 /* set UTA to appropriate mode */
2494 igb_set_uta(adapter);
2495
26ad9178
AD		 2496 /* set the correct pool for the PF default MAC address in entry 0 */
2497 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2498 adapter->vfs_allocated_count);
2499
e1739522 2500 igb_rlpml_set(adapter);
9d5c8243
AK		 2501
2502 /* Enable Receives */
2503 wr32(E1000_RCTL, rctl);
2504}
2505
2506/**
2507 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2508 * @tx_ring: Tx descriptor ring for a specific queue
2509 *
2510 * Free all transmit software resources
2511 **/
68fd9910 2512void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2513{
047e0030 2514 struct pci_dev *pdev = tx_ring->q_vector->adapter->pdev;
9d5c8243 2515
3b644cf6 2516 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2517
2518 vfree(tx_ring->buffer_info);
2519 tx_ring->buffer_info = NULL;
2520
2521 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2522
2523 tx_ring->desc = NULL;
2524}
2525
2526/**
2527 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2528 * @adapter: board private structure
2529 *
2530 * Free all transmit software resources
2531 **/
2532static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2533{
2534 int i;
2535
2536 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2537 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2538}
2539
2540static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2541 struct igb_buffer *buffer_info)
2542{
65689fef 2543 buffer_info->dma = 0;
9d5c8243 2544 if (buffer_info->skb) {
65689fef
AD		 2545 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2546 DMA_TO_DEVICE);
9d5c8243
AK		 2547 dev_kfree_skb_any(buffer_info->skb);
2548 buffer_info->skb = NULL;
2549 }
2550 buffer_info->time_stamp = 0;
2551 /* buffer_info must be completely set up in the transmit path */
2552}
2553
2554/**
2555 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2556 * @tx_ring: ring to be cleaned
2557 **/
3b644cf6 2558static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2559{
047e0030 2560 struct igb_adapter *adapter = tx_ring->q_vector->adapter;
9d5c8243
AK		 2561 struct igb_buffer *buffer_info;
2562 unsigned long size;
2563 unsigned int i;
2564
2565 if (!tx_ring->buffer_info)
2566 return;
2567 /* Free all the Tx ring sk_buffs */
2568
2569 for (i = 0; i < tx_ring->count; i++) {
2570 buffer_info = &tx_ring->buffer_info[i];
2571 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2572 }
2573
2574 size = sizeof(struct igb_buffer) * tx_ring->count;
2575 memset(tx_ring->buffer_info, 0, size);
2576
2577 /* Zero out the descriptor ring */
2578
2579 memset(tx_ring->desc, 0, tx_ring->size);
2580
2581 tx_ring->next_to_use = 0;
2582 tx_ring->next_to_clean = 0;
2583
2584 writel(0, adapter->hw.hw_addr + tx_ring->head);
2585 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2586}
2587
2588/**
2589 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2590 * @adapter: board private structure
2591 **/
2592static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2593{
2594 int i;
2595
2596 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2597 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2598}
2599
2600/**
2601 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2602 * @rx_ring: ring to clean the resources from
2603 *
2604 * Free all receive software resources
2605 **/
68fd9910 2606void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2607{
047e0030 2608 struct pci_dev *pdev = rx_ring->q_vector->adapter->pdev;
9d5c8243 2609
3b644cf6 2610 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2611
2612 vfree(rx_ring->buffer_info);
2613 rx_ring->buffer_info = NULL;
2614
2615 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2616
2617 rx_ring->desc = NULL;
2618}
2619
2620/**
2621 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2622 * @adapter: board private structure
2623 *
2624 * Free all receive software resources
2625 **/
2626static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2627{
2628 int i;
2629
2630 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2631 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2632}
2633
2634/**
2635 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2636 * @rx_ring: ring to free buffers from
2637 **/
3b644cf6 2638static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2639{
047e0030 2640 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243
AK		 2641 struct igb_buffer *buffer_info;
2642 struct pci_dev *pdev = adapter->pdev;
2643 unsigned long size;
2644 unsigned int i;
2645
2646 if (!rx_ring->buffer_info)
2647 return;
2648 /* Free all the Rx ring sk_buffs */
2649 for (i = 0; i < rx_ring->count; i++) {
2650 buffer_info = &rx_ring->buffer_info[i];
2651 if (buffer_info->dma) {
6ec43fe6
AD		 2652 pci_unmap_single(pdev, buffer_info->dma,
2653 adapter->rx_buffer_len,
2654 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2655 buffer_info->dma = 0;
2656 }
2657
2658 if (buffer_info->skb) {
2659 dev_kfree_skb(buffer_info->skb);
2660 buffer_info->skb = NULL;
2661 }
6ec43fe6
AD		 2662 if (buffer_info->page_dma) {
2663 pci_unmap_page(pdev, buffer_info->page_dma,
2664 PAGE_SIZE / 2,
2665 PCI_DMA_FROMDEVICE);
2666 buffer_info->page_dma = 0;
2667 }
9d5c8243 2668 if (buffer_info->page) {
9d5c8243
AK		 2669 put_page(buffer_info->page);
2670 buffer_info->page = NULL;
bf36c1a0 2671 buffer_info->page_offset = 0;
9d5c8243
AK		 2672 }
2673 }
2674
9d5c8243
AK		 2675 size = sizeof(struct igb_buffer) * rx_ring->count;
2676 memset(rx_ring->buffer_info, 0, size);
2677
2678 /* Zero out the descriptor ring */
2679 memset(rx_ring->desc, 0, rx_ring->size);
2680
2681 rx_ring->next_to_clean = 0;
2682 rx_ring->next_to_use = 0;
2683
2684 writel(0, adapter->hw.hw_addr + rx_ring->head);
2685 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2686}
2687
2688/**
2689 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2690 * @adapter: board private structure
2691 **/
2692static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2693{
2694 int i;
2695
2696 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2697 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2698}
2699
2700/**
2701 * igb_set_mac - Change the Ethernet Address of the NIC
2702 * @netdev: network interface device structure
2703 * @p: pointer to an address structure
2704 *
2705 * Returns 0 on success, negative on failure
2706 **/
2707static int igb_set_mac(struct net_device *netdev, void *p)
2708{
2709 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2710 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2711 struct sockaddr *addr = p;
2712
2713 if (!is_valid_ether_addr(addr->sa_data))
2714 return -EADDRNOTAVAIL;
2715
2716 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2717 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2718
26ad9178
AD		 2719 /* set the correct pool for the new PF MAC address in entry 0 */
2720 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2721 adapter->vfs_allocated_count);
e1739522 2722
9d5c8243
AK		 2723 return 0;
2724}
2725
2726/**
68d480c4 2727 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2728 * @netdev: network interface device structure
2729 *
68d480c4
AD		 2730 * Writes multicast address list to the MTA hash table.
2731 * Returns: -ENOMEM on failure
2732 * 0 on no addresses written
2733 * X on writing X addresses to MTA
9d5c8243 2734 **/
68d480c4 2735static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2736{
2737 struct igb_adapter *adapter = netdev_priv(netdev);
2738 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2739 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2740 u8 *mta_list;
2741 u32 vmolr = 0;
9d5c8243
AK		 2742 int i;
2743
68d480c4
AD		 2744 if (!netdev->mc_count) {
2745 /* nothing to program, so clear mc list */
2746 igb_update_mc_addr_list(hw, NULL, 0);
2747 igb_restore_vf_multicasts(adapter);
2748 return 0;
2749 }
9d5c8243 2750
68d480c4
AD		 2751 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2752 if (!mta_list)
2753 return -ENOMEM;
ff41f8dc 2754
68d480c4
AD		 2755 /* set vmolr receive overflow multicast bit */
2756 vmolr |= E1000_VMOLR_ROMPE;
2757
2758 /* The shared function expects a packed array of only addresses. */
2759 mc_ptr = netdev->mc_list;
2760
2761 for (i = 0; i < netdev->mc_count; i++) {
2762 if (!mc_ptr)
2763 break;
2764 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2765 mc_ptr = mc_ptr->next;
746b9f02 2766 }
68d480c4
AD		 2767 igb_update_mc_addr_list(hw, mta_list, i);
2768 kfree(mta_list);
2769
2770 return netdev->mc_count;
2771}
2772
2773/**
2774 * igb_write_uc_addr_list - write unicast addresses to RAR table
2775 * @netdev: network interface device structure
2776 *
2777 * Writes unicast address list to the RAR table.
2778 * Returns: -ENOMEM on failure/insufficient address space
2779 * 0 on no addresses written
2780 * X on writing X addresses to the RAR table
2781 **/
2782static int igb_write_uc_addr_list(struct net_device *netdev)
2783{
2784 struct igb_adapter *adapter = netdev_priv(netdev);
2785 struct e1000_hw *hw = &adapter->hw;
2786 unsigned int vfn = adapter->vfs_allocated_count;
2787 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2788 int count = 0;
2789
2790 /* return ENOMEM indicating insufficient memory for addresses */
2791 if (netdev->uc.count > rar_entries)
2792 return -ENOMEM;
9d5c8243 2793
ff41f8dc
AD		 2794 if (netdev->uc.count && rar_entries) {
2795 struct netdev_hw_addr *ha;
2796 list_for_each_entry(ha, &netdev->uc.list, list) {
2797 if (!rar_entries)
2798 break;
26ad9178
AD		 2799 igb_rar_set_qsel(adapter, ha->addr,
2800 rar_entries--,
68d480c4
AD		 2801 vfn);
2802 count++;
ff41f8dc
AD		 2803 }
2804 }
2805 /* write the addresses in reverse order to avoid write combining */
2806 for (; rar_entries > 0 ; rar_entries--) {
2807 wr32(E1000_RAH(rar_entries), 0);
2808 wr32(E1000_RAL(rar_entries), 0);
2809 }
2810 wrfl();
2811
68d480c4
AD		 2812 return count;
2813}
2814
2815/**
2816 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2817 * @netdev: network interface device structure
2818 *
2819 * The set_rx_mode entry point is called whenever the unicast or multicast
2820 * address lists or the network interface flags are updated. This routine is
2821 * responsible for configuring the hardware for proper unicast, multicast,
2822 * promiscuous mode, and all-multi behavior.
2823 **/
2824static void igb_set_rx_mode(struct net_device *netdev)
2825{
2826 struct igb_adapter *adapter = netdev_priv(netdev);
2827 struct e1000_hw *hw = &adapter->hw;
2828 unsigned int vfn = adapter->vfs_allocated_count;
2829 u32 rctl, vmolr = 0;
2830 int count;
2831
2832 /* Check for Promiscuous and All Multicast modes */
2833 rctl = rd32(E1000_RCTL);
2834
2835 /* clear the effected bits */
2836 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2837
2838 if (netdev->flags & IFF_PROMISC) {
2839 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2840 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2841 } else {
2842 if (netdev->flags & IFF_ALLMULTI) {
2843 rctl |= E1000_RCTL_MPE;
2844 vmolr |= E1000_VMOLR_MPME;
2845 } else {
2846 /*
2847 * Write addresses to the MTA, if the attempt fails
2848 * then we should just turn on promiscous mode so
2849 * that we can at least receive multicast traffic
2850 */
2851 count = igb_write_mc_addr_list(netdev);
2852 if (count < 0) {
2853 rctl |= E1000_RCTL_MPE;
2854 vmolr |= E1000_VMOLR_MPME;
2855 } else if (count) {
2856 vmolr |= E1000_VMOLR_ROMPE;
2857 }
2858 }
2859 /*
2860 * Write addresses to available RAR registers, if there is not
2861 * sufficient space to store all the addresses then enable
2862 * unicast promiscous mode
2863 */
2864 count = igb_write_uc_addr_list(netdev);
2865 if (count < 0) {
2866 rctl |= E1000_RCTL_UPE;
2867 vmolr |= E1000_VMOLR_ROPE;
2868 }
2869 rctl |= E1000_RCTL_VFE;
28fc06f5 2870 }
68d480c4 2871 wr32(E1000_RCTL, rctl);
28fc06f5 2872
68d480c4
AD		 2873 /*
2874 * In order to support SR-IOV and eventually VMDq it is necessary to set
2875 * the VMOLR to enable the appropriate modes. Without this workaround
2876 * we will have issues with VLAN tag stripping not being done for frames
2877 * that are only arriving because we are the default pool
2878 */
2879 if (hw->mac.type < e1000_82576)
28fc06f5 2880 return;
9d5c8243 2881
68d480c4
AD		 2882 vmolr |= rd32(E1000_VMOLR(vfn)) &
2883 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2884 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2885 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2886}
2887
2888/* Need to wait a few seconds after link up to get diagnostic information from
2889 * the phy */
2890static void igb_update_phy_info(unsigned long data)
2891{
2892 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2893 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2894}
2895
4d6b725e
AD		 2896/**
2897 * igb_has_link - check shared code for link and determine up/down
2898 * @adapter: pointer to driver private info
2899 **/
2900static bool igb_has_link(struct igb_adapter *adapter)
2901{
2902 struct e1000_hw *hw = &adapter->hw;
2903 bool link_active = false;
2904 s32 ret_val = 0;
2905
2906 /* get_link_status is set on LSC (link status) interrupt or
2907 * rx sequence error interrupt. get_link_status will stay
2908 * false until the e1000_check_for_link establishes link
2909 * for copper adapters ONLY
2910 */
2911 switch (hw->phy.media_type) {
2912 case e1000_media_type_copper:
2913 if (hw->mac.get_link_status) {
2914 ret_val = hw->mac.ops.check_for_link(hw);
2915 link_active = !hw->mac.get_link_status;
2916 } else {
2917 link_active = true;
2918 }
2919 break;
4d6b725e
AD		 2920 case e1000_media_type_internal_serdes:
2921 ret_val = hw->mac.ops.check_for_link(hw);
2922 link_active = hw->mac.serdes_has_link;
2923 break;
2924 default:
2925 case e1000_media_type_unknown:
2926 break;
2927 }
2928
2929 return link_active;
2930}
2931
9d5c8243
AK		 2932/**
2933 * igb_watchdog - Timer Call-back
2934 * @data: pointer to adapter cast into an unsigned long
2935 **/
2936static void igb_watchdog(unsigned long data)
2937{
2938 struct igb_adapter *adapter = (struct igb_adapter *)data;
2939 /* Do the rest outside of interrupt context */
2940 schedule_work(&adapter->watchdog_task);
2941}
2942
2943static void igb_watchdog_task(struct work_struct *work)
2944{
2945 struct igb_adapter *adapter = container_of(work,
2946 struct igb_adapter, watchdog_task);
2947 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2948 struct net_device *netdev = adapter->netdev;
2949 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2950 u32 link;
7a6ea550 2951 int i;
9d5c8243 2952
4d6b725e
AD		 2953 link = igb_has_link(adapter);
2954 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2955 goto link_up;
2956
9d5c8243
AK		 2957 if (link) {
2958 if (!netif_carrier_ok(netdev)) {
2959 u32 ctrl;
2960 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2961 &adapter->link_speed,
2962 &adapter->link_duplex);
2963
2964 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2965 /* Links status message must follow this format */
2966 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2967 "Flow Control: %s\n",
527d47c1 2968 netdev->name,
9d5c8243
AK		 2969 adapter->link_speed,
2970 adapter->link_duplex == FULL_DUPLEX ?
2971 "Full Duplex" : "Half Duplex",
2972 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2973 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2974 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2975 E1000_CTRL_TFCE) ? "TX" : "None")));
2976
2977 /* tweak tx_queue_len according to speed/duplex and
2978 * adjust the timeout factor */
2979 netdev->tx_queue_len = adapter->tx_queue_len;
2980 adapter->tx_timeout_factor = 1;
2981 switch (adapter->link_speed) {
2982 case SPEED_10:
2983 netdev->tx_queue_len = 10;
2984 adapter->tx_timeout_factor = 14;
2985 break;
2986 case SPEED_100:
2987 netdev->tx_queue_len = 100;
2988 /* maybe add some timeout factor ? */
2989 break;
2990 }
2991
2992 netif_carrier_on(netdev);
9d5c8243 2993
4ae196df
AD		 2994 igb_ping_all_vfs(adapter);
2995
4b1a9877 2996 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2997 if (!test_bit(__IGB_DOWN, &adapter->state))
2998 mod_timer(&adapter->phy_info_timer,
2999 round_jiffies(jiffies + 2 * HZ));
3000 }
3001 } else {
3002 if (netif_carrier_ok(netdev)) {
3003 adapter->link_speed = 0;
3004 adapter->link_duplex = 0;
527d47c1
AD		 3005 /* Links status message must follow this format */
3006 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3007 netdev->name);
9d5c8243 3008 netif_carrier_off(netdev);
4b1a9877 3009
4ae196df
AD		 3010 igb_ping_all_vfs(adapter);
3011
4b1a9877 3012 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3013 if (!test_bit(__IGB_DOWN, &adapter->state))
3014 mod_timer(&adapter->phy_info_timer,
3015 round_jiffies(jiffies + 2 * HZ));
3016 }
3017 }
3018
3019link_up:
3020 igb_update_stats(adapter);
3021
4b1a9877 3022 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 3023 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 3024 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 3025 adapter->colc_old = adapter->stats.colc;
3026
3027 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
3028 adapter->gorc_old = adapter->stats.gorc;
3029 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
3030 adapter->gotc_old = adapter->stats.gotc;
3031
3032 igb_update_adaptive(&adapter->hw);
3033
3034 if (!netif_carrier_ok(netdev)) {
c493ea45 3035 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 3036 /* We've lost link, so the controller stops DMA,
3037 * but we've got queued Tx work that's never going
3038 * to get done, so reset controller to flush Tx.
3039 * (Do the reset outside of interrupt context). */
3040 adapter->tx_timeout_count++;
3041 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 3042 /* return immediately since reset is imminent */
3043 return;
9d5c8243
AK		 3044 }
3045 }
3046
3047 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3048 if (adapter->msix_entries) {
047e0030
AD		 3049 u32 eics = 0;
3050 for (i = 0; i < adapter->num_q_vectors; i++) {
3051 struct igb_q_vector *q_vector = adapter->q_vector[i];
3052 eics |= q_vector->eims_value;
3053 }
7a6ea550
AD		 3054 wr32(E1000_EICS, eics);
3055 } else {
3056 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3057 }
9d5c8243
AK		 3058
3059 /* Force detection of hung controller every watchdog period */
3060 tx_ring->detect_tx_hung = true;
3061
3062 /* Reset the timer */
3063 if (!test_bit(__IGB_DOWN, &adapter->state))
3064 mod_timer(&adapter->watchdog_timer,
3065 round_jiffies(jiffies + 2 * HZ));
3066}
3067
3068enum latency_range {
3069 lowest_latency = 0,
3070 low_latency = 1,
3071 bulk_latency = 2,
3072 latency_invalid = 255
3073};
3074
3075
6eb5a7f1
AD		 3076/**
3077 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3078 *
3079 * Stores a new ITR value based on strictly on packet size. This
3080 * algorithm is less sophisticated than that used in igb_update_itr,
3081 * due to the difficulty of synchronizing statistics across multiple
3082 * receive rings. The divisors and thresholds used by this fuction
3083 * were determined based on theoretical maximum wire speed and testing
3084 * data, in order to minimize response time while increasing bulk
3085 * throughput.
3086 * This functionality is controlled by the InterruptThrottleRate module
3087 * parameter (see igb_param.c)
3088 * NOTE: This function is called only when operating in a multiqueue
3089 * receive environment.
047e0030 3090 * @q_vector: pointer to q_vector
6eb5a7f1 3091 **/
047e0030 3092static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3093{
047e0030 3094 int new_val = q_vector->itr_val;
6eb5a7f1 3095 int avg_wire_size = 0;
047e0030 3096 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3097
6eb5a7f1
AD		 3098 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3099 * ints/sec - ITR timer value of 120 ticks.
3100 */
3101 if (adapter->link_speed != SPEED_1000) {
047e0030 3102 new_val = 976;
6eb5a7f1 3103 goto set_itr_val;
9d5c8243 3104 }
047e0030
AD		 3105
3106 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3107 struct igb_ring *ring = q_vector->rx_ring;
3108 avg_wire_size = ring->total_bytes / ring->total_packets;
3109 }
3110
3111 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3112 struct igb_ring *ring = q_vector->tx_ring;
3113 avg_wire_size = max_t(u32, avg_wire_size,
3114 (ring->total_bytes /
3115 ring->total_packets));
3116 }
3117
3118 /* if avg_wire_size isn't set no work was done */
3119 if (!avg_wire_size)
3120 goto clear_counts;
9d5c8243 3121
6eb5a7f1
AD		 3122 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3123 avg_wire_size += 24;
3124
3125 /* Don't starve jumbo frames */
3126 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3127
6eb5a7f1
AD		 3128 /* Give a little boost to mid-size frames */
3129 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3130 new_val = avg_wire_size / 3;
3131 else
3132 new_val = avg_wire_size / 2;
9d5c8243 3133
6eb5a7f1 3134set_itr_val:
047e0030
AD		 3135 if (new_val != q_vector->itr_val) {
3136 q_vector->itr_val = new_val;
3137 q_vector->set_itr = 1;
9d5c8243 3138 }
6eb5a7f1 3139clear_counts:
047e0030
AD		 3140 if (q_vector->rx_ring) {
3141 q_vector->rx_ring->total_bytes = 0;
3142 q_vector->rx_ring->total_packets = 0;
3143 }
3144 if (q_vector->tx_ring) {
3145 q_vector->tx_ring->total_bytes = 0;
3146 q_vector->tx_ring->total_packets = 0;
3147 }
9d5c8243
AK		 3148}
3149
3150/**
3151 * igb_update_itr - update the dynamic ITR value based on statistics
3152 * Stores a new ITR value based on packets and byte
3153 * counts during the last interrupt. The advantage of per interrupt
3154 * computation is faster updates and more accurate ITR for the current
3155 * traffic pattern. Constants in this function were computed
3156 * based on theoretical maximum wire speed and thresholds were set based
3157 * on testing data as well as attempting to minimize response time
3158 * while increasing bulk throughput.
3159 * this functionality is controlled by the InterruptThrottleRate module
3160 * parameter (see igb_param.c)
3161 * NOTE: These calculations are only valid when operating in a single-
3162 * queue environment.
3163 * @adapter: pointer to adapter
047e0030 3164 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3165 * @packets: the number of packets during this measurement interval
3166 * @bytes: the number of bytes during this measurement interval
3167 **/
3168static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3169 int packets, int bytes)
3170{
3171 unsigned int retval = itr_setting;
3172
3173 if (packets == 0)
3174 goto update_itr_done;
3175
3176 switch (itr_setting) {
3177 case lowest_latency:
3178 /* handle TSO and jumbo frames */
3179 if (bytes/packets > 8000)
3180 retval = bulk_latency;
3181 else if ((packets < 5) && (bytes > 512))
3182 retval = low_latency;
3183 break;
3184 case low_latency: /* 50 usec aka 20000 ints/s */
3185 if (bytes > 10000) {
3186 /* this if handles the TSO accounting */
3187 if (bytes/packets > 8000) {
3188 retval = bulk_latency;
3189 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3190 retval = bulk_latency;
3191 } else if ((packets > 35)) {
3192 retval = lowest_latency;
3193 }
3194 } else if (bytes/packets > 2000) {
3195 retval = bulk_latency;
3196 } else if (packets <= 2 && bytes < 512) {
3197 retval = lowest_latency;
3198 }
3199 break;
3200 case bulk_latency: /* 250 usec aka 4000 ints/s */
3201 if (bytes > 25000) {
3202 if (packets > 35)
3203 retval = low_latency;
1e5c3d21 3204 } else if (bytes < 1500) {
9d5c8243
AK		 3205 retval = low_latency;
3206 }
3207 break;
3208 }
3209
3210update_itr_done:
3211 return retval;
3212}
3213
6eb5a7f1 3214static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3215{
047e0030 3216 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3217 u16 current_itr;
047e0030 3218 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3219
3220 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3221 if (adapter->link_speed != SPEED_1000) {
3222 current_itr = 0;
3223 new_itr = 4000;
3224 goto set_itr_now;
3225 }
3226
3227 adapter->rx_itr = igb_update_itr(adapter,
3228 adapter->rx_itr,
3229 adapter->rx_ring->total_packets,
3230 adapter->rx_ring->total_bytes);
9d5c8243 3231
047e0030
AD		 3232 adapter->tx_itr = igb_update_itr(adapter,
3233 adapter->tx_itr,
3234 adapter->tx_ring->total_packets,
3235 adapter->tx_ring->total_bytes);
3236 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3237
6eb5a7f1 3238 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3239 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3240 current_itr = low_latency;
3241
9d5c8243
AK		 3242 switch (current_itr) {
3243 /* counts and packets in update_itr are dependent on these numbers */
3244 case lowest_latency:
78b1f607 3245 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3246 break;
3247 case low_latency:
78b1f607 3248 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3249 break;
3250 case bulk_latency:
78b1f607 3251 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3252 break;
3253 default:
3254 break;
3255 }
3256
3257set_itr_now:
6eb5a7f1
AD		 3258 adapter->rx_ring->total_bytes = 0;
3259 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3260 adapter->tx_ring->total_bytes = 0;
3261 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3262
047e0030 3263 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3264 /* this attempts to bias the interrupt rate towards Bulk
3265 * by adding intermediate steps when interrupt rate is
3266 * increasing */
047e0030
AD		 3267 new_itr = new_itr > q_vector->itr_val ?
3268 max((new_itr * q_vector->itr_val) /
3269 (new_itr + (q_vector->itr_val >> 2)),
3270 new_itr) :
9d5c8243
AK		 3271 new_itr;
3272 /* Don't write the value here; it resets the adapter's
3273 * internal timer, and causes us to delay far longer than
3274 * we should between interrupts. Instead, we write the ITR
3275 * value at the beginning of the next interrupt so the timing
3276 * ends up being correct.
3277 */
047e0030
AD		 3278 q_vector->itr_val = new_itr;
3279 q_vector->set_itr = 1;
9d5c8243
AK		 3280 }
3281
3282 return;
3283}
3284
9d5c8243
AK		 3285#define IGB_TX_FLAGS_CSUM 0x00000001
3286#define IGB_TX_FLAGS_VLAN 0x00000002
3287#define IGB_TX_FLAGS_TSO 0x00000004
3288#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3289#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3290#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3291#define IGB_TX_FLAGS_VLAN_SHIFT 16
3292
3293static inline int igb_tso_adv(struct igb_adapter *adapter,
3294 struct igb_ring *tx_ring,
3295 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3296{
3297 struct e1000_adv_tx_context_desc *context_desc;
3298 unsigned int i;
3299 int err;
3300 struct igb_buffer *buffer_info;
3301 u32 info = 0, tu_cmd = 0;
3302 u32 mss_l4len_idx, l4len;
3303 *hdr_len = 0;
3304
3305 if (skb_header_cloned(skb)) {
3306 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3307 if (err)
3308 return err;
3309 }
3310
3311 l4len = tcp_hdrlen(skb);
3312 *hdr_len += l4len;
3313
3314 if (skb->protocol == htons(ETH_P_IP)) {
3315 struct iphdr *iph = ip_hdr(skb);
3316 iph->tot_len = 0;
3317 iph->check = 0;
3318 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3319 iph->daddr, 0,
3320 IPPROTO_TCP,
3321 0);
3322 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3323 ipv6_hdr(skb)->payload_len = 0;
3324 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3325 &ipv6_hdr(skb)->daddr,
3326 0, IPPROTO_TCP, 0);
3327 }
3328
3329 i = tx_ring->next_to_use;
3330
3331 buffer_info = &tx_ring->buffer_info[i];
3332 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3333 /* VLAN MACLEN IPLEN */
3334 if (tx_flags & IGB_TX_FLAGS_VLAN)
3335 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3336 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3337 *hdr_len += skb_network_offset(skb);
3338 info |= skb_network_header_len(skb);
3339 *hdr_len += skb_network_header_len(skb);
3340 context_desc->vlan_macip_lens = cpu_to_le32(info);
3341
3342 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3343 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3344
3345 if (skb->protocol == htons(ETH_P_IP))
3346 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3347 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3348
3349 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3350
3351 /* MSS L4LEN IDX */
3352 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3353 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3354
73cd78f1 3355 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3356 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3357 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3358
3359 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3360 context_desc->seqnum_seed = 0;
3361
3362 buffer_info->time_stamp = jiffies;
0e014cb1 3363 buffer_info->next_to_watch = i;
9d5c8243
AK		 3364 buffer_info->dma = 0;
3365 i++;
3366 if (i == tx_ring->count)
3367 i = 0;
3368
3369 tx_ring->next_to_use = i;
3370
3371 return true;
3372}
3373
3374static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3375 struct igb_ring *tx_ring,
3376 struct sk_buff *skb, u32 tx_flags)
3377{
3378 struct e1000_adv_tx_context_desc *context_desc;
3379 unsigned int i;
3380 struct igb_buffer *buffer_info;
3381 u32 info = 0, tu_cmd = 0;
3382
3383 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3384 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3385 i = tx_ring->next_to_use;
3386 buffer_info = &tx_ring->buffer_info[i];
3387 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3388
3389 if (tx_flags & IGB_TX_FLAGS_VLAN)
3390 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3391 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3392 if (skb->ip_summed == CHECKSUM_PARTIAL)
3393 info |= skb_network_header_len(skb);
3394
3395 context_desc->vlan_macip_lens = cpu_to_le32(info);
3396
3397 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3398
3399 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3400 __be16 protocol;
3401
3402 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3403 const struct vlan_ethhdr *vhdr =
3404 (const struct vlan_ethhdr*)skb->data;
3405
3406 protocol = vhdr->h_vlan_encapsulated_proto;
3407 } else {
3408 protocol = skb->protocol;
3409 }
3410
3411 switch (protocol) {
09640e63 3412 case cpu_to_be16(ETH_P_IP):
9d5c8243 3413 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3414 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3415 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3416 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3417 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3418 break;
09640e63 3419 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3420 /* XXX what about other V6 headers?? */
3421 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3422 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3423 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3424 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3425 break;
3426 default:
3427 if (unlikely(net_ratelimit()))
3428 dev_warn(&adapter->pdev->dev,
3429 "partial checksum but proto=%x!\n",
3430 skb->protocol);
3431 break;
3432 }
9d5c8243
AK		 3433 }
3434
3435 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3436 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3437 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3438 context_desc->mss_l4len_idx =
3439 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3440 else
3441 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3442
3443 buffer_info->time_stamp = jiffies;
0e014cb1 3444 buffer_info->next_to_watch = i;
9d5c8243
AK		 3445 buffer_info->dma = 0;
3446
3447 i++;
3448 if (i == tx_ring->count)
3449 i = 0;
3450 tx_ring->next_to_use = i;
3451
3452 return true;
3453 }
9d5c8243
AK		 3454 return false;
3455}
3456
3457#define IGB_MAX_TXD_PWR 16
3458#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3459
3460static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3461 struct igb_ring *tx_ring, struct sk_buff *skb,
3462 unsigned int first)
9d5c8243
AK		 3463{
3464 struct igb_buffer *buffer_info;
3465 unsigned int len = skb_headlen(skb);
3466 unsigned int count = 0, i;
3467 unsigned int f;
65689fef 3468 dma_addr_t *map;
9d5c8243
AK		 3469
3470 i = tx_ring->next_to_use;
3471
65689fef
AD		 3472 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3473 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3474 return 0;
3475 }
3476
3477 map = skb_shinfo(skb)->dma_maps;
3478
9d5c8243
AK		 3479 buffer_info = &tx_ring->buffer_info[i];
3480 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3481 buffer_info->length = len;
3482 /* set time_stamp *before* dma to help avoid a possible race */
3483 buffer_info->time_stamp = jiffies;
0e014cb1 3484 buffer_info->next_to_watch = i;
042a53a9 3485 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3486
3487 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3488 struct skb_frag_struct *frag;
3489
65689fef
AD		 3490 i++;
3491 if (i == tx_ring->count)
3492 i = 0;
3493
9d5c8243
AK		 3494 frag = &skb_shinfo(skb)->frags[f];
3495 len = frag->size;
3496
3497 buffer_info = &tx_ring->buffer_info[i];
3498 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3499 buffer_info->length = len;
3500 buffer_info->time_stamp = jiffies;
0e014cb1 3501 buffer_info->next_to_watch = i;
65689fef 3502 buffer_info->dma = map[count];
9d5c8243 3503 count++;
9d5c8243
AK		 3504 }
3505
9d5c8243 3506 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3507 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3508
042a53a9 3509 return count + 1;
9d5c8243
AK		 3510}
3511
3512static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3513 struct igb_ring *tx_ring,
3514 int tx_flags, int count, u32 paylen,
3515 u8 hdr_len)
3516{
3517 union e1000_adv_tx_desc *tx_desc = NULL;
3518 struct igb_buffer *buffer_info;
3519 u32 olinfo_status = 0, cmd_type_len;
3520 unsigned int i;
3521
3522 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3523 E1000_ADVTXD_DCMD_DEXT);
3524
3525 if (tx_flags & IGB_TX_FLAGS_VLAN)
3526 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3527
33af6bcc
PO		 3528 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3529 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3530
9d5c8243
AK		 3531 if (tx_flags & IGB_TX_FLAGS_TSO) {
3532 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3533
3534 /* insert tcp checksum */
3535 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3536
3537 /* insert ip checksum */
3538 if (tx_flags & IGB_TX_FLAGS_IPV4)
3539 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3540
3541 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3542 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3543 }
3544
7dfc16fa
AD		 3545 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3546 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3547 IGB_TX_FLAGS_VLAN)))
661086df 3548 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3549
3550 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3551
3552 i = tx_ring->next_to_use;
3553 while (count--) {
3554 buffer_info = &tx_ring->buffer_info[i];
3555 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3556 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3557 tx_desc->read.cmd_type_len =
3558 cpu_to_le32(cmd_type_len | buffer_info->length);
3559 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3560 i++;
3561 if (i == tx_ring->count)
3562 i = 0;
3563 }
3564
3565 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3566 /* Force memory writes to complete before letting h/w
3567 * know there are new descriptors to fetch. (Only
3568 * applicable for weak-ordered memory model archs,
3569 * such as IA-64). */
3570 wmb();
3571
3572 tx_ring->next_to_use = i;
3573 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3574 /* we need this if more than one processor can write to our tail
3575 * at a time, it syncronizes IO on IA64/Altix systems */
3576 mmiowb();
3577}
3578
3579static int __igb_maybe_stop_tx(struct net_device *netdev,
3580 struct igb_ring *tx_ring, int size)
3581{
3582 struct igb_adapter *adapter = netdev_priv(netdev);
3583
661086df 3584 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3585
9d5c8243
AK		 3586 /* Herbert's original patch had:
3587 * smp_mb__after_netif_stop_queue();
3588 * but since that doesn't exist yet, just open code it. */
3589 smp_mb();
3590
3591 /* We need to check again in a case another CPU has just
3592 * made room available. */
c493ea45 3593 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3594 return -EBUSY;
3595
3596 /* A reprieve! */
661086df 3597 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3598 ++adapter->restart_queue;
3599 return 0;
3600}
3601
3602static int igb_maybe_stop_tx(struct net_device *netdev,
3603 struct igb_ring *tx_ring, int size)
3604{
c493ea45 3605 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3606 return 0;
3607 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3608}
3609
3b29a56d
SH		 3610static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3611 struct net_device *netdev,
3612 struct igb_ring *tx_ring)
9d5c8243
AK		 3613{
3614 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3615 unsigned int first;
9d5c8243 3616 unsigned int tx_flags = 0;
9d5c8243 3617 u8 hdr_len = 0;
65689fef 3618 int count = 0;
9d5c8243 3619 int tso = 0;
33af6bcc 3620 union skb_shared_tx *shtx;
9d5c8243 3621
9d5c8243
AK		 3622 if (test_bit(__IGB_DOWN, &adapter->state)) {
3623 dev_kfree_skb_any(skb);
3624 return NETDEV_TX_OK;
3625 }
3626
3627 if (skb->len <= 0) {
3628 dev_kfree_skb_any(skb);
3629 return NETDEV_TX_OK;
3630 }
3631
9d5c8243
AK		 3632 /* need: 1 descriptor per page,
3633 * + 2 desc gap to keep tail from touching head,
3634 * + 1 desc for skb->data,
3635 * + 1 desc for context descriptor,
3636 * otherwise try next time */
3637 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3638 /* this is a hard error */
9d5c8243
AK		 3639 return NETDEV_TX_BUSY;
3640 }
33af6bcc
PO		 3641
3642 /*
3643 * TODO: check that there currently is no other packet with
3644 * time stamping in the queue
3645 *
3646 * When doing time stamping, keep the connection to the socket
3647 * a while longer: it is still needed by skb_hwtstamp_tx(),
3648 * called either in igb_tx_hwtstamp() or by our caller when
3649 * doing software time stamping.
3650 */
3651 shtx = skb_tx(skb);
3652 if (unlikely(shtx->hardware)) {
3653 shtx->in_progress = 1;
3654 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3655 }
9d5c8243
AK		 3656
3657 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3658 tx_flags |= IGB_TX_FLAGS_VLAN;
3659 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3660 }
3661
661086df
PWJ		 3662 if (skb->protocol == htons(ETH_P_IP))
3663 tx_flags |= IGB_TX_FLAGS_IPV4;
3664
0e014cb1 3665 first = tx_ring->next_to_use;
9d5c8243
AK		 3666 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3667 &hdr_len) : 0;
3668
3669 if (tso < 0) {
3670 dev_kfree_skb_any(skb);
9d5c8243
AK		 3671 return NETDEV_TX_OK;
3672 }
3673
3674 if (tso)
3675 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3676 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3677 (skb->ip_summed == CHECKSUM_PARTIAL))
3678 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3679
65689fef
AD		 3680 /*
3681 * count reflects descriptors mapped, if 0 then mapping error
3682 * has occured and we need to rewind the descriptor queue
3683 */
3684 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3685
3686 if (count) {
3687 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3688 skb->len, hdr_len);
65689fef
AD		 3689 /* Make sure there is space in the ring for the next send. */
3690 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3691 } else {
3692 dev_kfree_skb_any(skb);
3693 tx_ring->buffer_info[first].time_stamp = 0;
3694 tx_ring->next_to_use = first;
3695 }
9d5c8243 3696
9d5c8243
AK		 3697 return NETDEV_TX_OK;
3698}
3699
3b29a56d
SH		 3700static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3701 struct net_device *netdev)
9d5c8243
AK		 3702{
3703 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3704 struct igb_ring *tx_ring;
3705
661086df 3706 int r_idx = 0;
1bfaf07b 3707 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3708 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3709
3710 /* This goes back to the question of how to logically map a tx queue
3711 * to a flow. Right now, performance is impacted slightly negatively
3712 * if using multiple tx queues. If the stack breaks away from a
3713 * single qdisc implementation, we can look at this again. */
3b29a56d 3714 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3715}
3716
3717/**
3718 * igb_tx_timeout - Respond to a Tx Hang
3719 * @netdev: network interface device structure
3720 **/
3721static void igb_tx_timeout(struct net_device *netdev)
3722{
3723 struct igb_adapter *adapter = netdev_priv(netdev);
3724 struct e1000_hw *hw = &adapter->hw;
3725
3726 /* Do the reset outside of interrupt context */
3727 adapter->tx_timeout_count++;
3728 schedule_work(&adapter->reset_task);
265de409
AD		 3729 wr32(E1000_EICS,
3730 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3731}
3732
3733static void igb_reset_task(struct work_struct *work)
3734{
3735 struct igb_adapter *adapter;
3736 adapter = container_of(work, struct igb_adapter, reset_task);
3737
3738 igb_reinit_locked(adapter);
3739}
3740
3741/**
3742 * igb_get_stats - Get System Network Statistics
3743 * @netdev: network interface device structure
3744 *
3745 * Returns the address of the device statistics structure.
3746 * The statistics are actually updated from the timer callback.
3747 **/
73cd78f1 3748static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3749{
9d5c8243 3750 /* only return the current stats */
8d24e933 3751 return &netdev->stats;
9d5c8243
AK		 3752}
3753
3754/**
3755 * igb_change_mtu - Change the Maximum Transfer Unit
3756 * @netdev: network interface device structure
3757 * @new_mtu: new value for maximum frame size
3758 *
3759 * Returns 0 on success, negative on failure
3760 **/
3761static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3762{
3763 struct igb_adapter *adapter = netdev_priv(netdev);
3764 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3765
3766 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3767 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3768 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3769 return -EINVAL;
3770 }
3771
9d5c8243
AK		 3772 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3773 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3774 return -EINVAL;
3775 }
3776
3777 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3778 msleep(1);
73cd78f1 3779
9d5c8243
AK		 3780 /* igb_down has a dependency on max_frame_size */
3781 adapter->max_frame_size = max_frame;
3782 if (netif_running(netdev))
3783 igb_down(adapter);
3784
3785 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3786 * means we reserve 2 more, this pushes us to allocate from the next
3787 * larger slab size.
3788 * i.e. RXBUFFER_2048 --> size-4096 slab
3789 */
3790
7d95b717 3791 if (max_frame <= IGB_RXBUFFER_1024)
9d5c8243 3792 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3793 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
9d5c8243 3794 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6
AD		 3795 else
3796 adapter->rx_buffer_len = IGB_RXBUFFER_128;
9d5c8243
AK		 3797
3798 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3799 netdev->mtu, new_mtu);
3800 netdev->mtu = new_mtu;
3801
3802 if (netif_running(netdev))
3803 igb_up(adapter);
3804 else
3805 igb_reset(adapter);
3806
3807 clear_bit(__IGB_RESETTING, &adapter->state);
3808
3809 return 0;
3810}
3811
3812/**
3813 * igb_update_stats - Update the board statistics counters
3814 * @adapter: board private structure
3815 **/
3816
3817void igb_update_stats(struct igb_adapter *adapter)
3818{
8d24e933 3819 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3820 struct e1000_hw *hw = &adapter->hw;
3821 struct pci_dev *pdev = adapter->pdev;
3822 u16 phy_tmp;
3823
3824#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3825
3826 /*
3827 * Prevent stats update while adapter is being reset, or if the pci
3828 * connection is down.
3829 */
3830 if (adapter->link_speed == 0)
3831 return;
3832 if (pci_channel_offline(pdev))
3833 return;
3834
3835 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3836 adapter->stats.gprc += rd32(E1000_GPRC);
3837 adapter->stats.gorc += rd32(E1000_GORCL);
3838 rd32(E1000_GORCH); /* clear GORCL */
3839 adapter->stats.bprc += rd32(E1000_BPRC);
3840 adapter->stats.mprc += rd32(E1000_MPRC);
3841 adapter->stats.roc += rd32(E1000_ROC);
3842
3843 adapter->stats.prc64 += rd32(E1000_PRC64);
3844 adapter->stats.prc127 += rd32(E1000_PRC127);
3845 adapter->stats.prc255 += rd32(E1000_PRC255);
3846 adapter->stats.prc511 += rd32(E1000_PRC511);
3847 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3848 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3849 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3850 adapter->stats.sec += rd32(E1000_SEC);
3851
3852 adapter->stats.mpc += rd32(E1000_MPC);
3853 adapter->stats.scc += rd32(E1000_SCC);
3854 adapter->stats.ecol += rd32(E1000_ECOL);
3855 adapter->stats.mcc += rd32(E1000_MCC);
3856 adapter->stats.latecol += rd32(E1000_LATECOL);
3857 adapter->stats.dc += rd32(E1000_DC);
3858 adapter->stats.rlec += rd32(E1000_RLEC);
3859 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3860 adapter->stats.xontxc += rd32(E1000_XONTXC);
3861 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3862 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3863 adapter->stats.fcruc += rd32(E1000_FCRUC);
3864 adapter->stats.gptc += rd32(E1000_GPTC);
3865 adapter->stats.gotc += rd32(E1000_GOTCL);
3866 rd32(E1000_GOTCH); /* clear GOTCL */
3867 adapter->stats.rnbc += rd32(E1000_RNBC);
3868 adapter->stats.ruc += rd32(E1000_RUC);
3869 adapter->stats.rfc += rd32(E1000_RFC);
3870 adapter->stats.rjc += rd32(E1000_RJC);
3871 adapter->stats.tor += rd32(E1000_TORH);
3872 adapter->stats.tot += rd32(E1000_TOTH);
3873 adapter->stats.tpr += rd32(E1000_TPR);
3874
3875 adapter->stats.ptc64 += rd32(E1000_PTC64);
3876 adapter->stats.ptc127 += rd32(E1000_PTC127);
3877 adapter->stats.ptc255 += rd32(E1000_PTC255);
3878 adapter->stats.ptc511 += rd32(E1000_PTC511);
3879 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3880 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3881
3882 adapter->stats.mptc += rd32(E1000_MPTC);
3883 adapter->stats.bptc += rd32(E1000_BPTC);
3884
3885 /* used for adaptive IFS */
3886
3887 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3888 adapter->stats.tpt += hw->mac.tx_packet_delta;
3889 hw->mac.collision_delta = rd32(E1000_COLC);
3890 adapter->stats.colc += hw->mac.collision_delta;
3891
3892 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3893 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3894 adapter->stats.tncrs += rd32(E1000_TNCRS);
3895 adapter->stats.tsctc += rd32(E1000_TSCTC);
3896 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3897
3898 adapter->stats.iac += rd32(E1000_IAC);
3899 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3900 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3901 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3902 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3903 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3904 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3905 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3906 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3907
3908 /* Fill out the OS statistics structure */
8d24e933
AK		 3909 netdev->stats.multicast = adapter->stats.mprc;
3910 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3911
3912 /* Rx Errors */
3913
8c0ab70a
JDB		 3914 if (hw->mac.type != e1000_82575) {
3915 u32 rqdpc_tmp;
3ea73afa 3916 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3917 int i;
3918 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3919 * Queue Drop Packet Count) stats only gets incremented, if
3920 * the DROP_EN but it set (in the SRRCTL register for that
3921 * queue). If DROP_EN bit is NOT set, then the some what
3922 * equivalent count is stored in RNBC (not per queue basis).
3923 * Also note the drop count is due to lack of available
3924 * descriptors.
3925 */
3926 for (i = 0; i < adapter->num_rx_queues; i++) {
3927 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3928 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3929 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3930 }
8d24e933 3931 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3932 }
3933
3ea73afa
JDB		 3934 /* Note RNBC (Receive No Buffers Count) is an not an exact
3935 * drop count as the hardware FIFO might save the day. Thats
3936 * one of the reason for saving it in rx_fifo_errors, as its
3937 * potentially not a true drop.
3938 */
8d24e933 3939 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3940
9d5c8243 3941 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3942 * our own version based on RUC and ROC */
8d24e933 3943 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3944 adapter->stats.crcerrs + adapter->stats.algnerrc +
3945 adapter->stats.ruc + adapter->stats.roc +
3946 adapter->stats.cexterr;
8d24e933 3947 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3948 adapter->stats.roc;
8d24e933
AK		 3949 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3950 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3951 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3952
3953 /* Tx Errors */
8d24e933 3954 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3955 adapter->stats.latecol;
8d24e933
AK		 3956 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3957 netdev->stats.tx_window_errors = adapter->stats.latecol;
3958 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3959
3960 /* Tx Dropped needs to be maintained elsewhere */
3961
3962 /* Phy Stats */
3963 if (hw->phy.media_type == e1000_media_type_copper) {
3964 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3965 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3966 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3967 adapter->phy_stats.idle_errors += phy_tmp;
3968 }
3969 }
3970
3971 /* Management Stats */
3972 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3973 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3974 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3975}
3976
9d5c8243
AK		 3977static irqreturn_t igb_msix_other(int irq, void *data)
3978{
047e0030 3979 struct igb_adapter *adapter = data;
9d5c8243 3980 struct e1000_hw *hw = &adapter->hw;
844290e5 3981 u32 icr = rd32(E1000_ICR);
844290e5 3982 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3983
047e0030 3984 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3985 /* HW is reporting DMA is out of sync */
3986 adapter->stats.doosync++;
3987 }
eebbbdba 3988
4ae196df
AD		 3989 /* Check for a mailbox event */
3990 if (icr & E1000_ICR_VMMB)
3991 igb_msg_task(adapter);
3992
3993 if (icr & E1000_ICR_LSC) {
3994 hw->mac.get_link_status = 1;
3995 /* guard against interrupt when we're going down */
3996 if (!test_bit(__IGB_DOWN, &adapter->state))
3997 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3998 }
3999
4000 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 4001 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4002
4003 return IRQ_HANDLED;
4004}
4005
047e0030 4006static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4007{
047e0030 4008 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4009
047e0030
AD		 4010 if (!q_vector->set_itr)
4011 return;
73cd78f1 4012
047e0030
AD		 4013 if (!itr_val)
4014 itr_val = 0x4;
661086df 4015
047e0030
AD		 4016 if (q_vector->itr_shift)
4017 itr_val |= itr_val << q_vector->itr_shift;
661086df 4018 else
047e0030 4019 itr_val |= 0x8000000;
661086df 4020
047e0030
AD		 4021 writel(itr_val, q_vector->itr_register);
4022 q_vector->set_itr = 0;
6eb5a7f1
AD		 4023}
4024
047e0030 4025static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4026{
047e0030 4027 struct igb_q_vector *q_vector = data;
9d5c8243 4028
047e0030
AD		 4029 /* Write the ITR value calculated from the previous interrupt. */
4030 igb_write_itr(q_vector);
9d5c8243 4031
047e0030 4032 napi_schedule(&q_vector->napi);
844290e5 4033
047e0030 4034 return IRQ_HANDLED;
fe4506b6
JC		 4035}
4036
421e02f0 4037#ifdef CONFIG_IGB_DCA
047e0030 4038static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4039{
047e0030 4040 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4041 struct e1000_hw *hw = &adapter->hw;
4042 int cpu = get_cpu();
fe4506b6 4043
047e0030
AD		 4044 if (q_vector->cpu == cpu)
4045 goto out_no_update;
4046
4047 if (q_vector->tx_ring) {
4048 int q = q_vector->tx_ring->reg_idx;
4049 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4050 if (hw->mac.type == e1000_82575) {
4051 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4052 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4053 } else {
047e0030
AD		 4054 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4055 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4056 E1000_DCA_TXCTRL_CPUID_SHIFT;
4057 }
4058 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4059 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4060 }
4061 if (q_vector->rx_ring) {
4062 int q = q_vector->rx_ring->reg_idx;
4063 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4064 if (hw->mac.type == e1000_82575) {
2d064c06 4065 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4066 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4067 } else {
4068 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4069 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4070 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4071 }
fe4506b6
JC		 4072 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4073 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4074 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4075 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4076 }
047e0030
AD		 4077 q_vector->cpu = cpu;
4078out_no_update:
fe4506b6
JC		 4079 put_cpu();
4080}
4081
4082static void igb_setup_dca(struct igb_adapter *adapter)
4083{
7e0e99ef 4084 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4085 int i;
4086
7dfc16fa 4087 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4088 return;
4089
7e0e99ef
AD		 4090 /* Always use CB2 mode, difference is masked in the CB driver. */
4091 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4092
047e0030
AD		 4093 for (i = 0; i < adapter->num_q_vectors; i++) {
4094 struct igb_q_vector *q_vector = adapter->q_vector[i];
4095 q_vector->cpu = -1;
4096 igb_update_dca(q_vector);
fe4506b6
JC		 4097 }
4098}
4099
4100static int __igb_notify_dca(struct device *dev, void *data)
4101{
4102 struct net_device *netdev = dev_get_drvdata(dev);
4103 struct igb_adapter *adapter = netdev_priv(netdev);
4104 struct e1000_hw *hw = &adapter->hw;
4105 unsigned long event = *(unsigned long *)data;
4106
4107 switch (event) {
4108 case DCA_PROVIDER_ADD:
4109 /* if already enabled, don't do it again */
7dfc16fa 4110 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4111 break;
fe4506b6
JC		 4112 /* Always use CB2 mode, difference is masked
4113 * in the CB driver. */
cbd347ad 4114 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4115 if (dca_add_requester(dev) == 0) {
bbd98fe4 4116 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4117 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4118 igb_setup_dca(adapter);
4119 break;
4120 }
4121 /* Fall Through since DCA is disabled. */
4122 case DCA_PROVIDER_REMOVE:
7dfc16fa 4123 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4124 /* without this a class_device is left
047e0030 4125 * hanging around in the sysfs model */
fe4506b6
JC		 4126 dca_remove_requester(dev);
4127 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4128 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4129 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4130 }
4131 break;
4132 }
bbd98fe4 4133
fe4506b6 4134 return 0;
9d5c8243
AK		 4135}
4136
fe4506b6
JC		 4137static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4138 void *p)
4139{
4140 int ret_val;
4141
4142 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4143 __igb_notify_dca);
4144
4145 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4146}
421e02f0 4147#endif /* CONFIG_IGB_DCA */
9d5c8243 4148
4ae196df
AD		 4149static void igb_ping_all_vfs(struct igb_adapter *adapter)
4150{
4151 struct e1000_hw *hw = &adapter->hw;
4152 u32 ping;
4153 int i;
4154
4155 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4156 ping = E1000_PF_CONTROL_MSG;
4157 if (adapter->vf_data[i].clear_to_send)
4158 ping |= E1000_VT_MSGTYPE_CTS;
4159 igb_write_mbx(hw, &ping, 1, i);
4160 }
4161}
4162
4163static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4164 u32 *msgbuf, u32 vf)
4165{
4166 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4167 u16 *hash_list = (u16 *)&msgbuf[1];
4168 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4169 int i;
4170
4171 /* only up to 30 hash values supported */
4172 if (n > 30)
4173 n = 30;
4174
4175 /* salt away the number of multi cast addresses assigned
4176 * to this VF for later use to restore when the PF multi cast
4177 * list changes
4178 */
4179 vf_data->num_vf_mc_hashes = n;
4180
4181 /* VFs are limited to using the MTA hash table for their multicast
4182 * addresses */
4183 for (i = 0; i < n; i++)
a419aef8 4184 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4185
4186 /* Flush and reset the mta with the new values */
ff41f8dc 4187 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4188
4189 return 0;
4190}
4191
4192static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4193{
4194 struct e1000_hw *hw = &adapter->hw;
4195 struct vf_data_storage *vf_data;
4196 int i, j;
4197
4198 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4199 vf_data = &adapter->vf_data[i];
75f4f382 4200 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4201 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4202 }
4203}
4204
4205static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4206{
4207 struct e1000_hw *hw = &adapter->hw;
4208 u32 pool_mask, reg, vid;
4209 int i;
4210
4211 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4212
4213 /* Find the vlan filter for this id */
4214 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4215 reg = rd32(E1000_VLVF(i));
4216
4217 /* remove the vf from the pool */
4218 reg &= ~pool_mask;
4219
4220 /* if pool is empty then remove entry from vfta */
4221 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4222 (reg & E1000_VLVF_VLANID_ENABLE)) {
4223 reg = 0;
4224 vid = reg & E1000_VLVF_VLANID_MASK;
4225 igb_vfta_set(hw, vid, false);
4226 }
4227
4228 wr32(E1000_VLVF(i), reg);
4229 }
ae641bdc
AD		 4230
4231 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4232}
4233
4234static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4235{
4236 struct e1000_hw *hw = &adapter->hw;
4237 u32 reg, i;
4238
4239 /* It is an error to call this function when VFs are not enabled */
4240 if (!adapter->vfs_allocated_count)
4241 return -1;
4242
4243 /* Find the vlan filter for this id */
4244 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4245 reg = rd32(E1000_VLVF(i));
4246 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4247 vid == (reg & E1000_VLVF_VLANID_MASK))
4248 break;
4249 }
4250
4251 if (add) {
4252 if (i == E1000_VLVF_ARRAY_SIZE) {
4253 /* Did not find a matching VLAN ID entry that was
4254 * enabled. Search for a free filter entry, i.e.
4255 * one without the enable bit set
4256 */
4257 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4258 reg = rd32(E1000_VLVF(i));
4259 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4260 break;
4261 }
4262 }
4263 if (i < E1000_VLVF_ARRAY_SIZE) {
4264 /* Found an enabled/available entry */
4265 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4266
4267 /* if !enabled we need to set this up in vfta */
4268 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4269 /* add VID to filter table, if bit already set
4270 * PF must have added it outside of table */
4271 if (igb_vfta_set(hw, vid, true))
4272 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4273 adapter->vfs_allocated_count);
4ae196df
AD		 4274 reg |= E1000_VLVF_VLANID_ENABLE;
4275 }
cad6d05f
AD		 4276 reg &= ~E1000_VLVF_VLANID_MASK;
4277 reg |= vid;
4ae196df
AD		 4278
4279 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4280
4281 /* do not modify RLPML for PF devices */
4282 if (vf >= adapter->vfs_allocated_count)
4283 return 0;
4284
4285 if (!adapter->vf_data[vf].vlans_enabled) {
4286 u32 size;
4287 reg = rd32(E1000_VMOLR(vf));
4288 size = reg & E1000_VMOLR_RLPML_MASK;
4289 size += 4;
4290 reg &= ~E1000_VMOLR_RLPML_MASK;
4291 reg |= size;
4292 wr32(E1000_VMOLR(vf), reg);
4293 }
4294 adapter->vf_data[vf].vlans_enabled++;
4295
4ae196df
AD		 4296 return 0;
4297 }
4298 } else {
4299 if (i < E1000_VLVF_ARRAY_SIZE) {
4300 /* remove vf from the pool */
4301 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4302 /* if pool is empty then remove entry from vfta */
4303 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4304 reg = 0;
4305 igb_vfta_set(hw, vid, false);
4306 }
4307 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4308
4309 /* do not modify RLPML for PF devices */
4310 if (vf >= adapter->vfs_allocated_count)
4311 return 0;
4312
4313 adapter->vf_data[vf].vlans_enabled--;
4314 if (!adapter->vf_data[vf].vlans_enabled) {
4315 u32 size;
4316 reg = rd32(E1000_VMOLR(vf));
4317 size = reg & E1000_VMOLR_RLPML_MASK;
4318 size -= 4;
4319 reg &= ~E1000_VMOLR_RLPML_MASK;
4320 reg |= size;
4321 wr32(E1000_VMOLR(vf), reg);
4322 }
4ae196df
AD		 4323 return 0;
4324 }
4325 }
4326 return -1;
4327}
4328
4329static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4330{
4331 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4332 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4333
4334 return igb_vlvf_set(adapter, vid, add, vf);
4335}
4336
4337static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4338{
4339 struct e1000_hw *hw = &adapter->hw;
4340
4341 /* disable mailbox functionality for vf */
4342 adapter->vf_data[vf].clear_to_send = false;
4343
4344 /* reset offloads to defaults */
4345 igb_set_vmolr(hw, vf);
4346
4347 /* reset vlans for device */
4348 igb_clear_vf_vfta(adapter, vf);
4349
4350 /* reset multicast table array for vf */
4351 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4352
4353 /* Flush and reset the mta with the new values */
ff41f8dc 4354 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4355}
4356
4357static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4358{
4359 struct e1000_hw *hw = &adapter->hw;
4360 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4361 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4362 u32 reg, msgbuf[3];
4363 u8 *addr = (u8 *)(&msgbuf[1]);
4364
4365 /* process all the same items cleared in a function level reset */
4366 igb_vf_reset_event(adapter, vf);
4367
4368 /* set vf mac address */
26ad9178 4369 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4370
4371 /* enable transmit and receive for vf */
4372 reg = rd32(E1000_VFTE);
4373 wr32(E1000_VFTE, reg | (1 << vf));
4374 reg = rd32(E1000_VFRE);
4375 wr32(E1000_VFRE, reg | (1 << vf));
4376
4377 /* enable mailbox functionality for vf */
4378 adapter->vf_data[vf].clear_to_send = true;
4379
4380 /* reply to reset with ack and vf mac address */
4381 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4382 memcpy(addr, vf_mac, 6);
4383 igb_write_mbx(hw, msgbuf, 3, vf);
4384}
4385
4386static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4387{
4388 unsigned char *addr = (char *)&msg[1];
4389 int err = -1;
4390
4391 if (is_valid_ether_addr(addr))
4392 err = igb_set_vf_mac(adapter, vf, addr);
4393
4394 return err;
4395
4396}
4397
4398static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4399{
4400 struct e1000_hw *hw = &adapter->hw;
4401 u32 msg = E1000_VT_MSGTYPE_NACK;
4402
4403 /* if device isn't clear to send it shouldn't be reading either */
4404 if (!adapter->vf_data[vf].clear_to_send)
4405 igb_write_mbx(hw, &msg, 1, vf);
4406}
4407
4408
4409static void igb_msg_task(struct igb_adapter *adapter)
4410{
4411 struct e1000_hw *hw = &adapter->hw;
4412 u32 vf;
4413
4414 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4415 /* process any reset requests */
4416 if (!igb_check_for_rst(hw, vf)) {
4417 adapter->vf_data[vf].clear_to_send = false;
4418 igb_vf_reset_event(adapter, vf);
4419 }
4420
4421 /* process any messages pending */
4422 if (!igb_check_for_msg(hw, vf))
4423 igb_rcv_msg_from_vf(adapter, vf);
4424
4425 /* process any acks */
4426 if (!igb_check_for_ack(hw, vf))
4427 igb_rcv_ack_from_vf(adapter, vf);
4428
4429 }
4430}
4431
4432static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4433{
4434 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4435 u32 msgbuf[mbx_size];
4436 struct e1000_hw *hw = &adapter->hw;
4437 s32 retval;
4438
4439 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4440
4441 if (retval)
4442 dev_err(&adapter->pdev->dev,
4443 "Error receiving message from VF\n");
4444
4445 /* this is a message we already processed, do nothing */
4446 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4447 return retval;
4448
4449 /*
4450 * until the vf completes a reset it should not be
4451 * allowed to start any configuration.
4452 */
4453
4454 if (msgbuf[0] == E1000_VF_RESET) {
4455 igb_vf_reset_msg(adapter, vf);
4456
4457 return retval;
4458 }
4459
4460 if (!adapter->vf_data[vf].clear_to_send) {
4461 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4462 igb_write_mbx(hw, msgbuf, 1, vf);
4463 return retval;
4464 }
4465
4466 switch ((msgbuf[0] & 0xFFFF)) {
4467 case E1000_VF_SET_MAC_ADDR:
4468 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4469 break;
4470 case E1000_VF_SET_MULTICAST:
4471 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4472 break;
4473 case E1000_VF_SET_LPE:
4474 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4475 break;
4476 case E1000_VF_SET_VLAN:
4477 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4478 break;
4479 default:
4480 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4481 retval = -1;
4482 break;
4483 }
4484
4485 /* notify the VF of the results of what it sent us */
4486 if (retval)
4487 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4488 else
4489 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4490
4491 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4492
4493 igb_write_mbx(hw, msgbuf, 1, vf);
4494
4495 return retval;
4496}
4497
68d480c4
AD		 4498/**
4499 * igb_set_uta - Set unicast filter table address
4500 * @adapter: board private structure
4501 *
4502 * The unicast table address is a register array of 32-bit registers.
4503 * The table is meant to be used in a way similar to how the MTA is used
4504 * however due to certain limitations in the hardware it is necessary to
4505 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4506 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4507 **/
4508static void igb_set_uta(struct igb_adapter *adapter)
4509{
4510 struct e1000_hw *hw = &adapter->hw;
4511 int i;
4512
4513 /* The UTA table only exists on 82576 hardware and newer */
4514 if (hw->mac.type < e1000_82576)
4515 return;
4516
4517 /* we only need to do this if VMDq is enabled */
4518 if (!adapter->vfs_allocated_count)
4519 return;
4520
4521 for (i = 0; i < hw->mac.uta_reg_count; i++)
4522 array_wr32(E1000_UTA, i, ~0);
4523}
4524
9d5c8243
AK		 4525/**
4526 * igb_intr_msi - Interrupt Handler
4527 * @irq: interrupt number
4528 * @data: pointer to a network interface device structure
4529 **/
4530static irqreturn_t igb_intr_msi(int irq, void *data)
4531{
047e0030
AD		 4532 struct igb_adapter *adapter = data;
4533 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4534 struct e1000_hw *hw = &adapter->hw;
4535 /* read ICR disables interrupts using IAM */
4536 u32 icr = rd32(E1000_ICR);
4537
047e0030 4538 igb_write_itr(q_vector);
9d5c8243 4539
047e0030 4540 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4541 /* HW is reporting DMA is out of sync */
4542 adapter->stats.doosync++;
4543 }
4544
9d5c8243
AK		 4545 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4546 hw->mac.get_link_status = 1;
4547 if (!test_bit(__IGB_DOWN, &adapter->state))
4548 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4549 }
4550
047e0030 4551 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4552
4553 return IRQ_HANDLED;
4554}
4555
4556/**
4a3c6433 4557 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4558 * @irq: interrupt number
4559 * @data: pointer to a network interface device structure
4560 **/
4561static irqreturn_t igb_intr(int irq, void *data)
4562{
047e0030
AD		 4563 struct igb_adapter *adapter = data;
4564 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4565 struct e1000_hw *hw = &adapter->hw;
4566 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4567 * need for the IMC write */
4568 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4569 if (!icr)
4570 return IRQ_NONE; /* Not our interrupt */
4571
047e0030 4572 igb_write_itr(q_vector);
9d5c8243
AK		 4573
4574 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4575 * not set, then the adapter didn't send an interrupt */
4576 if (!(icr & E1000_ICR_INT_ASSERTED))
4577 return IRQ_NONE;
4578
047e0030 4579 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4580 /* HW is reporting DMA is out of sync */
4581 adapter->stats.doosync++;
4582 }
4583
9d5c8243
AK		 4584 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4585 hw->mac.get_link_status = 1;
4586 /* guard against interrupt when we're going down */
4587 if (!test_bit(__IGB_DOWN, &adapter->state))
4588 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4589 }
4590
047e0030 4591 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4592
4593 return IRQ_HANDLED;
4594}
4595
047e0030 4596static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4597{
047e0030 4598 struct igb_adapter *adapter = q_vector->adapter;
46544258 4599 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4600
46544258 4601 if (adapter->itr_setting & 3) {
047e0030 4602 if (!adapter->msix_entries)
6eb5a7f1 4603 igb_set_itr(adapter);
46544258 4604 else
047e0030 4605 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4606 }
4607
46544258
AD		 4608 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4609 if (adapter->msix_entries)
047e0030 4610 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4611 else
4612 igb_irq_enable(adapter);
4613 }
9d5c8243
AK		 4614}
4615
46544258
AD		 4616/**
4617 * igb_poll - NAPI Rx polling callback
4618 * @napi: napi polling structure
4619 * @budget: count of how many packets we should handle
4620 **/
4621static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4622{
047e0030
AD		 4623 struct igb_q_vector *q_vector = container_of(napi,
4624 struct igb_q_vector,
4625 napi);
4626 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4627
421e02f0 4628#ifdef CONFIG_IGB_DCA
047e0030
AD		 4629 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4630 igb_update_dca(q_vector);
fe4506b6 4631#endif
047e0030
AD		 4632 if (q_vector->tx_ring)
4633 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4634
047e0030
AD		 4635 if (q_vector->rx_ring)
4636 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4637
4638 if (!tx_clean_complete)
4639 work_done = budget;
46544258 4640
9d5c8243 4641 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4642 if (work_done < budget) {
288379f0 4643 napi_complete(napi);
047e0030 4644 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4645 }
4646
46544258 4647 return work_done;
9d5c8243 4648}
6d8126f9 4649
33af6bcc
PO		 4650/**
4651 * igb_hwtstamp - utility function which checks for TX time stamp
4652 * @adapter: board private structure
4653 * @skb: packet that was just sent
4654 *
4655 * If we were asked to do hardware stamping and such a time stamp is
4656 * available, then it must have been for this skb here because we only
4657 * allow only one such packet into the queue.
4658 */
4659static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4660{
4661 union skb_shared_tx *shtx = skb_tx(skb);
4662 struct e1000_hw *hw = &adapter->hw;
4663
4664 if (unlikely(shtx->hardware)) {
4665 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4666 if (valid) {
4667 u64 regval = rd32(E1000_TXSTMPL);
4668 u64 ns;
4669 struct skb_shared_hwtstamps shhwtstamps;
4670
4671 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4672 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4673 ns = timecounter_cyc2time(&adapter->clock,
4674 regval);
4675 timecompare_update(&adapter->compare, ns);
4676 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4677 shhwtstamps.syststamp =
4678 timecompare_transform(&adapter->compare, ns);
4679 skb_tstamp_tx(skb, &shhwtstamps);
4680 }
33af6bcc
PO		 4681 }
4682}
4683
9d5c8243
AK		 4684/**
4685 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4686 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4687 * returns true if ring is completely cleaned
4688 **/
047e0030 4689static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4690{
047e0030
AD		 4691 struct igb_adapter *adapter = q_vector->adapter;
4692 struct igb_ring *tx_ring = q_vector->tx_ring;
3b644cf6 4693 struct net_device *netdev = adapter->netdev;
0e014cb1 4694 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4695 struct igb_buffer *buffer_info;
4696 struct sk_buff *skb;
0e014cb1 4697 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4698 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4699 unsigned int i, eop, count = 0;
4700 bool cleaned = false;
9d5c8243 4701
9d5c8243 4702 i = tx_ring->next_to_clean;
0e014cb1
AD		 4703 eop = tx_ring->buffer_info[i].next_to_watch;
4704 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4705
4706 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4707 (count < tx_ring->count)) {
4708 for (cleaned = false; !cleaned; count++) {
4709 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4710 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4711 cleaned = (i == eop);
9d5c8243
AK		 4712 skb = buffer_info->skb;
4713
4714 if (skb) {
4715 unsigned int segs, bytecount;
4716 /* gso_segs is currently only valid for tcp */
4717 segs = skb_shinfo(skb)->gso_segs ?: 1;
4718 /* multiply data chunks by size of headers */
4719 bytecount = ((segs - 1) * skb_headlen(skb)) +
4720 skb->len;
4721 total_packets += segs;
4722 total_bytes += bytecount;
33af6bcc
PO		 4723
4724 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4725 }
4726
4727 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4728 tx_desc->wb.status = 0;
9d5c8243
AK		 4729
4730 i++;
4731 if (i == tx_ring->count)
4732 i = 0;
9d5c8243 4733 }
0e014cb1
AD		 4734 eop = tx_ring->buffer_info[i].next_to_watch;
4735 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4736 }
4737
9d5c8243
AK		 4738 tx_ring->next_to_clean = i;
4739
fc7d345d 4740 if (unlikely(count &&
9d5c8243 4741 netif_carrier_ok(netdev) &&
c493ea45 4742 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4743 /* Make sure that anybody stopping the queue after this
4744 * sees the new next_to_clean.
4745 */
4746 smp_mb();
661086df
PWJ		 4747 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4748 !(test_bit(__IGB_DOWN, &adapter->state))) {
4749 netif_wake_subqueue(netdev, tx_ring->queue_index);
4750 ++adapter->restart_queue;
4751 }
9d5c8243
AK		 4752 }
4753
4754 if (tx_ring->detect_tx_hung) {
4755 /* Detect a transmit hang in hardware, this serializes the
4756 * check with the clearing of time_stamp and movement of i */
4757 tx_ring->detect_tx_hung = false;
4758 if (tx_ring->buffer_info[i].time_stamp &&
4759 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4760 (adapter->tx_timeout_factor * HZ))
4761 && !(rd32(E1000_STATUS) &
4762 E1000_STATUS_TXOFF)) {
4763
9d5c8243
AK		 4764 /* detected Tx unit hang */
4765 dev_err(&adapter->pdev->dev,
4766 "Detected Tx Unit Hang\n"
2d064c06 4767 " Tx Queue <%d>\n"
9d5c8243
AK		 4768 " TDH <%x>\n"
4769 " TDT <%x>\n"
4770 " next_to_use <%x>\n"
4771 " next_to_clean <%x>\n"
9d5c8243
AK		 4772 "buffer_info[next_to_clean]\n"
4773 " time_stamp <%lx>\n"
0e014cb1 4774 " next_to_watch <%x>\n"
9d5c8243
AK		 4775 " jiffies <%lx>\n"
4776 " desc.status <%x>\n",
2d064c06 4777 tx_ring->queue_index,
9d5c8243
AK		 4778 readl(adapter->hw.hw_addr + tx_ring->head),
4779 readl(adapter->hw.hw_addr + tx_ring->tail),
4780 tx_ring->next_to_use,
4781 tx_ring->next_to_clean,
9d5c8243 4782 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4783 eop,
9d5c8243 4784 jiffies,
0e014cb1 4785 eop_desc->wb.status);
661086df 4786 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4787 }
4788 }
4789 tx_ring->total_bytes += total_bytes;
4790 tx_ring->total_packets += total_packets;
e21ed353
AD		 4791 tx_ring->tx_stats.bytes += total_bytes;
4792 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4793 netdev->stats.tx_bytes += total_bytes;
4794 netdev->stats.tx_packets += total_packets;
0e014cb1 4795 return (count < tx_ring->count);
9d5c8243
AK		 4796}
4797
9d5c8243
AK		 4798/**
4799 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4800 * @q_vector: structure containing interrupt and ring information
4801 * @skb: packet to send up
4802 * @vlan_tag: vlan tag for packet
9d5c8243 4803 **/
047e0030
AD		 4804static void igb_receive_skb(struct igb_q_vector *q_vector,
4805 struct sk_buff *skb,
4806 u16 vlan_tag)
4807{
4808 struct igb_adapter *adapter = q_vector->adapter;
4809
4810 if (vlan_tag)
4811 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4812 vlan_tag, skb);
182ff8df 4813 else
047e0030 4814 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4815}
4816
9d5c8243
AK		 4817static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4818 u32 status_err, struct sk_buff *skb)
4819{
4820 skb->ip_summed = CHECKSUM_NONE;
4821
4822 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4823 if ((status_err & E1000_RXD_STAT_IXSM) ||
4824 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4825 return;
4826 /* TCP/UDP checksum error bit is set */
4827 if (status_err &
4828 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4829 /*
4830 * work around errata with sctp packets where the TCPE aka
4831 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4832 * packets, (aka let the stack check the crc32c)
4833 */
4834 if (!((adapter->hw.mac.type == e1000_82576) &&
4835 (skb->len == 60)))
4836 adapter->hw_csum_err++;
9d5c8243 4837 /* let the stack verify checksum errors */
9d5c8243
AK		 4838 return;
4839 }
4840 /* It must be a TCP or UDP packet with a valid checksum */
4841 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4842 skb->ip_summed = CHECKSUM_UNNECESSARY;
4843
b9473560 4844 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4845}
4846
2d94d8ab
AD		 4847static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4848 union e1000_adv_rx_desc *rx_desc)
4849{
4850 /* HW will not DMA in data larger than the given buffer, even if it
4851 * parses the (NFS, of course) header to be larger. In that case, it
4852 * fills the header buffer and spills the rest into the page.
4853 */
4854 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4855 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
6ec43fe6
AD		 4856 if (hlen > adapter->rx_buffer_len)
4857 hlen = adapter->rx_buffer_len;
2d94d8ab
AD		 4858 return hlen;
4859}
4860
047e0030
AD		 4861static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4862 int *work_done, int budget)
9d5c8243 4863{
047e0030 4864 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 4865 struct net_device *netdev = adapter->netdev;
047e0030 4866 struct igb_ring *rx_ring = q_vector->rx_ring;
33af6bcc 4867 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4868 struct pci_dev *pdev = adapter->pdev;
4869 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4870 struct igb_buffer *buffer_info , *next_buffer;
4871 struct sk_buff *skb;
9d5c8243
AK		 4872 bool cleaned = false;
4873 int cleaned_count = 0;
4874 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4875 unsigned int i;
2d94d8ab
AD		 4876 u32 staterr;
4877 u16 length;
047e0030 4878 u16 vlan_tag;
9d5c8243
AK		 4879
4880 i = rx_ring->next_to_clean;
69d3ca53 4881 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4882 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4883 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4884
4885 while (staterr & E1000_RXD_STAT_DD) {
4886 if (*work_done >= budget)
4887 break;
4888 (*work_done)++;
9d5c8243 4889
69d3ca53
AD		 4890 skb = buffer_info->skb;
4891 prefetch(skb->data - NET_IP_ALIGN);
4892 buffer_info->skb = NULL;
4893
4894 i++;
4895 if (i == rx_ring->count)
4896 i = 0;
4897 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4898 prefetch(next_rxd);
4899 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4900
4901 length = le16_to_cpu(rx_desc->wb.upper.length);
4902 cleaned = true;
4903 cleaned_count++;
4904
2d94d8ab 4905 if (buffer_info->dma) {
bf36c1a0 4906 pci_unmap_single(pdev, buffer_info->dma,
6ec43fe6 4907 adapter->rx_buffer_len,
bf36c1a0 4908 PCI_DMA_FROMDEVICE);
91615f76 4909 buffer_info->dma = 0;
6ec43fe6
AD		 4910 if (adapter->rx_buffer_len >= IGB_RXBUFFER_1024) {
4911 skb_put(skb, length);
4912 goto send_up;
4913 }
4914 skb_put(skb, igb_get_hlen(adapter, rx_desc));
bf36c1a0
AD		 4915 }
4916
4917 if (length) {
9d5c8243 4918 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4919 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4920 buffer_info->page_dma = 0;
bf36c1a0
AD		 4921
4922 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4923 buffer_info->page,
4924 buffer_info->page_offset,
4925 length);
4926
6ec43fe6 4927 if (page_count(buffer_info->page) != 1)
bf36c1a0
AD		 4928 buffer_info->page = NULL;
4929 else
4930 get_page(buffer_info->page);
9d5c8243
AK		 4931
4932 skb->len += length;
4933 skb->data_len += length;
9d5c8243 4934
bf36c1a0 4935 skb->truesize += length;
9d5c8243 4936 }
9d5c8243 4937
bf36c1a0 4938 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4939 buffer_info->skb = next_buffer->skb;
4940 buffer_info->dma = next_buffer->dma;
4941 next_buffer->skb = skb;
4942 next_buffer->dma = 0;
bf36c1a0
AD		 4943 goto next_desc;
4944 }
69d3ca53 4945send_up:
33af6bcc
PO		 4946 /*
4947 * If this bit is set, then the RX registers contain
4948 * the time stamp. No other packet will be time
4949 * stamped until we read these registers, so read the
4950 * registers to make them available again. Because
4951 * only one packet can be time stamped at a time, we
4952 * know that the register values must belong to this
4953 * one here and therefore we don't need to compare
4954 * any of the additional attributes stored for it.
4955 *
4956 * If nothing went wrong, then it should have a
4957 * skb_shared_tx that we can turn into a
4958 * skb_shared_hwtstamps.
4959 *
4960 * TODO: can time stamping be triggered (thus locking
4961 * the registers) without the packet reaching this point
4962 * here? In that case RX time stamping would get stuck.
4963 *
4964 * TODO: in "time stamp all packets" mode this bit is
4965 * not set. Need a global flag for this mode and then
4966 * always read the registers. Cannot be done without
4967 * a race condition.
4968 */
4969 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4970 u64 regval;
4971 u64 ns;
4972 struct skb_shared_hwtstamps *shhwtstamps =
4973 skb_hwtstamps(skb);
4974
4975 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4976 "igb: no RX time stamp available for time stamped packet");
4977 regval = rd32(E1000_RXSTMPL);
4978 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4979 ns = timecounter_cyc2time(&adapter->clock, regval);
4980 timecompare_update(&adapter->compare, ns);
4981 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4982 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4983 shhwtstamps->syststamp =
4984 timecompare_transform(&adapter->compare, ns);
4985 }
4986
9d5c8243
AK		 4987 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4988 dev_kfree_skb_irq(skb);
4989 goto next_desc;
4990 }
9d5c8243
AK		 4991
4992 total_bytes += skb->len;
4993 total_packets++;
4994
4995 igb_rx_checksum_adv(adapter, staterr, skb);
4996
4997 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 4998 skb_record_rx_queue(skb, rx_ring->queue_index);
4999
5000 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5001 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5002
047e0030 5003 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5004
9d5c8243
AK		 5005next_desc:
5006 rx_desc->wb.upper.status_error = 0;
5007
5008 /* return some buffers to hardware, one at a time is too slow */
5009 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5010 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5011 cleaned_count = 0;
5012 }
5013
5014 /* use prefetched values */
5015 rx_desc = next_rxd;
5016 buffer_info = next_buffer;
9d5c8243
AK		 5017 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5018 }
bf36c1a0 5019
9d5c8243 5020 rx_ring->next_to_clean = i;
c493ea45 5021 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5022
5023 if (cleaned_count)
3b644cf6 5024 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5025
5026 rx_ring->total_packets += total_packets;
5027 rx_ring->total_bytes += total_bytes;
5028 rx_ring->rx_stats.packets += total_packets;
5029 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5030 netdev->stats.rx_bytes += total_bytes;
5031 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5032 return cleaned;
5033}
5034
9d5c8243
AK		 5035/**
5036 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5037 * @adapter: address of board private structure
5038 **/
3b644cf6 5039static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 5040 int cleaned_count)
5041{
047e0030 5042 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243
AK		 5043 struct net_device *netdev = adapter->netdev;
5044 struct pci_dev *pdev = adapter->pdev;
5045 union e1000_adv_rx_desc *rx_desc;
5046 struct igb_buffer *buffer_info;
5047 struct sk_buff *skb;
5048 unsigned int i;
db761762 5049 int bufsz;
9d5c8243
AK		 5050
5051 i = rx_ring->next_to_use;
5052 buffer_info = &rx_ring->buffer_info[i];
5053
6ec43fe6 5054 bufsz = adapter->rx_buffer_len;
db761762 5055
9d5c8243
AK		 5056 while (cleaned_count--) {
5057 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5058
6ec43fe6 5059 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5060 if (!buffer_info->page) {
bf36c1a0
AD		 5061 buffer_info->page = alloc_page(GFP_ATOMIC);
5062 if (!buffer_info->page) {
5063 adapter->alloc_rx_buff_failed++;
5064 goto no_buffers;
5065 }
5066 buffer_info->page_offset = 0;
5067 } else {
5068 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5069 }
5070 buffer_info->page_dma =
db761762 5071 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 5072 buffer_info->page_offset,
5073 PAGE_SIZE / 2,
9d5c8243
AK		 5074 PCI_DMA_FROMDEVICE);
5075 }
5076
5077 if (!buffer_info->skb) {
89d71a66 5078 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243
AK		 5079 if (!skb) {
5080 adapter->alloc_rx_buff_failed++;
5081 goto no_buffers;
5082 }
5083
9d5c8243
AK		 5084 buffer_info->skb = skb;
5085 buffer_info->dma = pci_map_single(pdev, skb->data,
5086 bufsz,
5087 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5088 }
5089 /* Refresh the desc even if buffer_addrs didn't change because
5090 * each write-back erases this info. */
6ec43fe6 5091 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5092 rx_desc->read.pkt_addr =
5093 cpu_to_le64(buffer_info->page_dma);
5094 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5095 } else {
5096 rx_desc->read.pkt_addr =
5097 cpu_to_le64(buffer_info->dma);
5098 rx_desc->read.hdr_addr = 0;
5099 }
5100
5101 i++;
5102 if (i == rx_ring->count)
5103 i = 0;
5104 buffer_info = &rx_ring->buffer_info[i];
5105 }
5106
5107no_buffers:
5108 if (rx_ring->next_to_use != i) {
5109 rx_ring->next_to_use = i;
5110 if (i == 0)
5111 i = (rx_ring->count - 1);
5112 else
5113 i--;
5114
5115 /* Force memory writes to complete before letting h/w
5116 * know there are new descriptors to fetch. (Only
5117 * applicable for weak-ordered memory model archs,
5118 * such as IA-64). */
5119 wmb();
5120 writel(i, adapter->hw.hw_addr + rx_ring->tail);
5121 }
5122}
5123
5124/**
5125 * igb_mii_ioctl -
5126 * @netdev:
5127 * @ifreq:
5128 * @cmd:
5129 **/
5130static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5131{
5132 struct igb_adapter *adapter = netdev_priv(netdev);
5133 struct mii_ioctl_data *data = if_mii(ifr);
5134
5135 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5136 return -EOPNOTSUPP;
5137
5138 switch (cmd) {
5139 case SIOCGMIIPHY:
5140 data->phy_id = adapter->hw.phy.addr;
5141 break;
5142 case SIOCGMIIREG:
f5f4cf08
AD		 5143 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5144 &data->val_out))
9d5c8243
AK		 5145 return -EIO;
5146 break;
5147 case SIOCSMIIREG:
5148 default:
5149 return -EOPNOTSUPP;
5150 }
5151 return 0;
5152}
5153
c6cb090b
PO		 5154/**
5155 * igb_hwtstamp_ioctl - control hardware time stamping
5156 * @netdev:
5157 * @ifreq:
5158 * @cmd:
5159 *
33af6bcc
PO		 5160 * Outgoing time stamping can be enabled and disabled. Play nice and
5161 * disable it when requested, although it shouldn't case any overhead
5162 * when no packet needs it. At most one packet in the queue may be
5163 * marked for time stamping, otherwise it would be impossible to tell
5164 * for sure to which packet the hardware time stamp belongs.
5165 *
5166 * Incoming time stamping has to be configured via the hardware
5167 * filters. Not all combinations are supported, in particular event
5168 * type has to be specified. Matching the kind of event packet is
5169 * not supported, with the exception of "all V2 events regardless of
5170 * level 2 or 4".
5171 *
c6cb090b
PO		 5172 **/
5173static int igb_hwtstamp_ioctl(struct net_device *netdev,
5174 struct ifreq *ifr, int cmd)
5175{
33af6bcc
PO		 5176 struct igb_adapter *adapter = netdev_priv(netdev);
5177 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5178 struct hwtstamp_config config;
33af6bcc
PO		 5179 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5180 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5181 u32 tsync_rx_ctl_type = 0;
5182 u32 tsync_rx_cfg = 0;
5183 int is_l4 = 0;
5184 int is_l2 = 0;
5185 short port = 319; /* PTP */
5186 u32 regval;
c6cb090b
PO		 5187
5188 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5189 return -EFAULT;
5190
5191 /* reserved for future extensions */
5192 if (config.flags)
5193 return -EINVAL;
5194
33af6bcc
PO		 5195 switch (config.tx_type) {
5196 case HWTSTAMP_TX_OFF:
5197 tsync_tx_ctl_bit = 0;
5198 break;
5199 case HWTSTAMP_TX_ON:
5200 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5201 break;
5202 default:
5203 return -ERANGE;
5204 }
5205
5206 switch (config.rx_filter) {
5207 case HWTSTAMP_FILTER_NONE:
5208 tsync_rx_ctl_bit = 0;
5209 break;
5210 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5211 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5212 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5213 case HWTSTAMP_FILTER_ALL:
5214 /*
5215 * register TSYNCRXCFG must be set, therefore it is not
5216 * possible to time stamp both Sync and Delay_Req messages
5217 * => fall back to time stamping all packets
5218 */
5219 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5220 config.rx_filter = HWTSTAMP_FILTER_ALL;
5221 break;
5222 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5223 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5224 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5225 is_l4 = 1;
5226 break;
5227 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5228 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5229 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5230 is_l4 = 1;
5231 break;
5232 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5233 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5234 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5235 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5236 is_l2 = 1;
5237 is_l4 = 1;
5238 config.rx_filter = HWTSTAMP_FILTER_SOME;
5239 break;
5240 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5241 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5242 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5243 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5244 is_l2 = 1;
5245 is_l4 = 1;
5246 config.rx_filter = HWTSTAMP_FILTER_SOME;
5247 break;
5248 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5249 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5250 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5251 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5252 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5253 is_l2 = 1;
5254 break;
5255 default:
5256 return -ERANGE;
5257 }
5258
5259 /* enable/disable TX */
5260 regval = rd32(E1000_TSYNCTXCTL);
5261 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5262 wr32(E1000_TSYNCTXCTL, regval);
5263
5264 /* enable/disable RX, define which PTP packets are time stamped */
5265 regval = rd32(E1000_TSYNCRXCTL);
5266 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5267 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5268 wr32(E1000_TSYNCRXCTL, regval);
5269 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5270
5271 /*
5272 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5273 * (Ethertype to filter on)
5274 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5275 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5276 */
5277 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5278
5279 /* L4 Queue Filter[0]: only filter by source and destination port */
5280 wr32(E1000_SPQF0, htons(port));
5281 wr32(E1000_IMIREXT(0), is_l4 ?
5282 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5283 wr32(E1000_IMIR(0), is_l4 ?
5284 (htons(port)
5285 | (0<<16) /* immediate interrupt disabled */
5286 | 0 /* (1<<17) bit cleared: do not bypass
5287 destination port check */)
5288 : 0);
5289 wr32(E1000_FTQF0, is_l4 ?
5290 (0x11 /* UDP */
5291 | (1<<15) /* VF not compared */
5292 | (1<<27) /* Enable Timestamping */
5293 | (7<<28) /* only source port filter enabled,
5294 source/target address and protocol
5295 masked */)
5296 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5297 enabled */));
5298
5299 wrfl();
5300
5301 adapter->hwtstamp_config = config;
5302
5303 /* clear TX/RX time stamp registers, just to be sure */
5304 regval = rd32(E1000_TXSTMPH);
5305 regval = rd32(E1000_RXSTMPH);
c6cb090b 5306
33af6bcc
PO		 5307 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5308 -EFAULT : 0;
c6cb090b
PO		 5309}
5310
9d5c8243
AK		 5311/**
5312 * igb_ioctl -
5313 * @netdev:
5314 * @ifreq:
5315 * @cmd:
5316 **/
5317static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5318{
5319 switch (cmd) {
5320 case SIOCGMIIPHY:
5321 case SIOCGMIIREG:
5322 case SIOCSMIIREG:
5323 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5324 case SIOCSHWTSTAMP:
5325 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5326 default:
5327 return -EOPNOTSUPP;
5328 }
5329}
5330
009bc06e
AD		 5331s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5332{
5333 struct igb_adapter *adapter = hw->back;
5334 u16 cap_offset;
5335
5336 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5337 if (!cap_offset)
5338 return -E1000_ERR_CONFIG;
5339
5340 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5341
5342 return 0;
5343}
5344
5345s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5346{
5347 struct igb_adapter *adapter = hw->back;
5348 u16 cap_offset;
5349
5350 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5351 if (!cap_offset)
5352 return -E1000_ERR_CONFIG;
5353
5354 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5355
5356 return 0;
5357}
5358
9d5c8243
AK		 5359static void igb_vlan_rx_register(struct net_device *netdev,
5360 struct vlan_group *grp)
5361{
5362 struct igb_adapter *adapter = netdev_priv(netdev);
5363 struct e1000_hw *hw = &adapter->hw;
5364 u32 ctrl, rctl;
5365
5366 igb_irq_disable(adapter);
5367 adapter->vlgrp = grp;
5368
5369 if (grp) {
5370 /* enable VLAN tag insert/strip */
5371 ctrl = rd32(E1000_CTRL);
5372 ctrl |= E1000_CTRL_VME;
5373 wr32(E1000_CTRL, ctrl);
5374
5375 /* enable VLAN receive filtering */
5376 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5377 rctl &= ~E1000_RCTL_CFIEN;
5378 wr32(E1000_RCTL, rctl);
5379 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5380 } else {
5381 /* disable VLAN tag insert/strip */
5382 ctrl = rd32(E1000_CTRL);
5383 ctrl &= ~E1000_CTRL_VME;
5384 wr32(E1000_CTRL, ctrl);
5385
9d5c8243
AK		 5386 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5387 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5388 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5389 }
9d5c8243
AK		 5390 }
5391
e1739522
AD		 5392 igb_rlpml_set(adapter);
5393
9d5c8243
AK		 5394 if (!test_bit(__IGB_DOWN, &adapter->state))
5395 igb_irq_enable(adapter);
5396}
5397
5398static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5399{
5400 struct igb_adapter *adapter = netdev_priv(netdev);
5401 struct e1000_hw *hw = &adapter->hw;
4ae196df 5402 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5403
28b0759c 5404 if ((hw->mng_cookie.status &
9d5c8243
AK		 5405 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5406 (vid == adapter->mng_vlan_id))
5407 return;
4ae196df
AD		 5408
5409 /* add vid to vlvf if sr-iov is enabled,
5410 * if that fails add directly to filter table */
5411 if (igb_vlvf_set(adapter, vid, true, pf_id))
5412 igb_vfta_set(hw, vid, true);
5413
9d5c8243
AK		 5414}
5415
5416static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5417{
5418 struct igb_adapter *adapter = netdev_priv(netdev);
5419 struct e1000_hw *hw = &adapter->hw;
4ae196df 5420 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5421
5422 igb_irq_disable(adapter);
5423 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5424
5425 if (!test_bit(__IGB_DOWN, &adapter->state))
5426 igb_irq_enable(adapter);
5427
5428 if ((adapter->hw.mng_cookie.status &
5429 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5430 (vid == adapter->mng_vlan_id)) {
5431 /* release control to f/w */
5432 igb_release_hw_control(adapter);
5433 return;
5434 }
5435
4ae196df
AD		 5436 /* remove vid from vlvf if sr-iov is enabled,
5437 * if not in vlvf remove from vfta */
5438 if (igb_vlvf_set(adapter, vid, false, pf_id))
5439 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5440}
5441
5442static void igb_restore_vlan(struct igb_adapter *adapter)
5443{
5444 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5445
5446 if (adapter->vlgrp) {
5447 u16 vid;
5448 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5449 if (!vlan_group_get_device(adapter->vlgrp, vid))
5450 continue;
5451 igb_vlan_rx_add_vid(adapter->netdev, vid);
5452 }
5453 }
5454}
5455
5456int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5457{
5458 struct e1000_mac_info *mac = &adapter->hw.mac;
5459
5460 mac->autoneg = 0;
5461
9d5c8243
AK		 5462 switch (spddplx) {
5463 case SPEED_10 + DUPLEX_HALF:
5464 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5465 break;
5466 case SPEED_10 + DUPLEX_FULL:
5467 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5468 break;
5469 case SPEED_100 + DUPLEX_HALF:
5470 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5471 break;
5472 case SPEED_100 + DUPLEX_FULL:
5473 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5474 break;
5475 case SPEED_1000 + DUPLEX_FULL:
5476 mac->autoneg = 1;
5477 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5478 break;
5479 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5480 default:
5481 dev_err(&adapter->pdev->dev,
5482 "Unsupported Speed/Duplex configuration\n");
5483 return -EINVAL;
5484 }
5485 return 0;
5486}
5487
3fe7c4c9 5488static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5489{
5490 struct net_device *netdev = pci_get_drvdata(pdev);
5491 struct igb_adapter *adapter = netdev_priv(netdev);
5492 struct e1000_hw *hw = &adapter->hw;
2d064c06 5493 u32 ctrl, rctl, status;
9d5c8243
AK		 5494 u32 wufc = adapter->wol;
5495#ifdef CONFIG_PM
5496 int retval = 0;
5497#endif
5498
5499 netif_device_detach(netdev);
5500
a88f10ec
AD		 5501 if (netif_running(netdev))
5502 igb_close(netdev);
5503
047e0030 5504 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5505
5506#ifdef CONFIG_PM
5507 retval = pci_save_state(pdev);
5508 if (retval)
5509 return retval;
5510#endif
5511
5512 status = rd32(E1000_STATUS);
5513 if (status & E1000_STATUS_LU)
5514 wufc &= ~E1000_WUFC_LNKC;
5515
5516 if (wufc) {
5517 igb_setup_rctl(adapter);
ff41f8dc 5518 igb_set_rx_mode(netdev);
9d5c8243
AK		 5519
5520 /* turn on all-multi mode if wake on multicast is enabled */
5521 if (wufc & E1000_WUFC_MC) {
5522 rctl = rd32(E1000_RCTL);
5523 rctl |= E1000_RCTL_MPE;
5524 wr32(E1000_RCTL, rctl);
5525 }
5526
5527 ctrl = rd32(E1000_CTRL);
5528 /* advertise wake from D3Cold */
5529 #define E1000_CTRL_ADVD3WUC 0x00100000
5530 /* phy power management enable */
5531 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5532 ctrl |= E1000_CTRL_ADVD3WUC;
5533 wr32(E1000_CTRL, ctrl);
5534
9d5c8243
AK		 5535 /* Allow time for pending master requests to run */
5536 igb_disable_pcie_master(&adapter->hw);
5537
5538 wr32(E1000_WUC, E1000_WUC_PME_EN);
5539 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5540 } else {
5541 wr32(E1000_WUC, 0);
5542 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5543 }
5544
3fe7c4c9
RW		 5545 *enable_wake = wufc || adapter->en_mng_pt;
5546 if (!*enable_wake)
2fb02a26 5547 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5548
5549 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5550 * would have already happened in close and is redundant. */
5551 igb_release_hw_control(adapter);
5552
5553 pci_disable_device(pdev);
5554
9d5c8243
AK		 5555 return 0;
5556}
5557
5558#ifdef CONFIG_PM
3fe7c4c9
RW		 5559static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5560{
5561 int retval;
5562 bool wake;
5563
5564 retval = __igb_shutdown(pdev, &wake);
5565 if (retval)
5566 return retval;
5567
5568 if (wake) {
5569 pci_prepare_to_sleep(pdev);
5570 } else {
5571 pci_wake_from_d3(pdev, false);
5572 pci_set_power_state(pdev, PCI_D3hot);
5573 }
5574
5575 return 0;
5576}
5577
9d5c8243
AK		 5578static int igb_resume(struct pci_dev *pdev)
5579{
5580 struct net_device *netdev = pci_get_drvdata(pdev);
5581 struct igb_adapter *adapter = netdev_priv(netdev);
5582 struct e1000_hw *hw = &adapter->hw;
5583 u32 err;
5584
5585 pci_set_power_state(pdev, PCI_D0);
5586 pci_restore_state(pdev);
42bfd33a 5587
aed5dec3 5588 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5589 if (err) {
5590 dev_err(&pdev->dev,
5591 "igb: Cannot enable PCI device from suspend\n");
5592 return err;
5593 }
5594 pci_set_master(pdev);
5595
5596 pci_enable_wake(pdev, PCI_D3hot, 0);
5597 pci_enable_wake(pdev, PCI_D3cold, 0);
5598
047e0030 5599 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5600 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5601 return -ENOMEM;
9d5c8243
AK		 5602 }
5603
5604 /* e1000_power_up_phy(adapter); */
5605
5606 igb_reset(adapter);
a8564f03
AD		 5607
5608 /* let the f/w know that the h/w is now under the control of the
5609 * driver. */
5610 igb_get_hw_control(adapter);
5611
9d5c8243
AK		 5612 wr32(E1000_WUS, ~0);
5613
a88f10ec
AD		 5614 if (netif_running(netdev)) {
5615 err = igb_open(netdev);
5616 if (err)
5617 return err;
5618 }
9d5c8243
AK		 5619
5620 netif_device_attach(netdev);
5621
9d5c8243
AK		 5622 return 0;
5623}
5624#endif
5625
5626static void igb_shutdown(struct pci_dev *pdev)
5627{
3fe7c4c9
RW		 5628 bool wake;
5629
5630 __igb_shutdown(pdev, &wake);
5631
5632 if (system_state == SYSTEM_POWER_OFF) {
5633 pci_wake_from_d3(pdev, wake);
5634 pci_set_power_state(pdev, PCI_D3hot);
5635 }
9d5c8243
AK		 5636}
5637
5638#ifdef CONFIG_NET_POLL_CONTROLLER
5639/*
5640 * Polling 'interrupt' - used by things like netconsole to send skbs
5641 * without having to re-enable interrupts. It's not called while
5642 * the interrupt routine is executing.
5643 */
5644static void igb_netpoll(struct net_device *netdev)
5645{
5646 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5647 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5648 int i;
9d5c8243 5649
eebbbdba 5650 if (!adapter->msix_entries) {
047e0030 5651 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5652 igb_irq_disable(adapter);
047e0030 5653 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5654 return;
5655 }
9d5c8243 5656
047e0030
AD		 5657 for (i = 0; i < adapter->num_q_vectors; i++) {
5658 struct igb_q_vector *q_vector = adapter->q_vector[i];
5659 wr32(E1000_EIMC, q_vector->eims_value);
5660 napi_schedule(&q_vector->napi);
eebbbdba 5661 }
9d5c8243
AK		 5662}
5663#endif /* CONFIG_NET_POLL_CONTROLLER */
5664
5665/**
5666 * igb_io_error_detected - called when PCI error is detected
5667 * @pdev: Pointer to PCI device
5668 * @state: The current pci connection state
5669 *
5670 * This function is called after a PCI bus error affecting
5671 * this device has been detected.
5672 */
5673static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5674 pci_channel_state_t state)
5675{
5676 struct net_device *netdev = pci_get_drvdata(pdev);
5677 struct igb_adapter *adapter = netdev_priv(netdev);
5678
5679 netif_device_detach(netdev);
5680
59ed6eec
AD		 5681 if (state == pci_channel_io_perm_failure)
5682 return PCI_ERS_RESULT_DISCONNECT;
5683
9d5c8243
AK		 5684 if (netif_running(netdev))
5685 igb_down(adapter);
5686 pci_disable_device(pdev);
5687
5688 /* Request a slot slot reset. */
5689 return PCI_ERS_RESULT_NEED_RESET;
5690}
5691
5692/**
5693 * igb_io_slot_reset - called after the pci bus has been reset.
5694 * @pdev: Pointer to PCI device
5695 *
5696 * Restart the card from scratch, as if from a cold-boot. Implementation
5697 * resembles the first-half of the igb_resume routine.
5698 */
5699static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5700{
5701 struct net_device *netdev = pci_get_drvdata(pdev);
5702 struct igb_adapter *adapter = netdev_priv(netdev);
5703 struct e1000_hw *hw = &adapter->hw;
40a914fa 5704 pci_ers_result_t result;
42bfd33a 5705 int err;
9d5c8243 5706
aed5dec3 5707 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5708 dev_err(&pdev->dev,
5709 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5710 result = PCI_ERS_RESULT_DISCONNECT;
5711 } else {
5712 pci_set_master(pdev);
5713 pci_restore_state(pdev);
9d5c8243 5714
40a914fa
AD		 5715 pci_enable_wake(pdev, PCI_D3hot, 0);
5716 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5717
40a914fa
AD		 5718 igb_reset(adapter);
5719 wr32(E1000_WUS, ~0);
5720 result = PCI_ERS_RESULT_RECOVERED;
5721 }
9d5c8243 5722
ea943d41
JK		 5723 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5724 if (err) {
5725 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5726 "failed 0x%0x\n", err);
5727 /* non-fatal, continue */
5728 }
40a914fa
AD		 5729
5730 return result;
9d5c8243
AK		 5731}
5732
5733/**
5734 * igb_io_resume - called when traffic can start flowing again.
5735 * @pdev: Pointer to PCI device
5736 *
5737 * This callback is called when the error recovery driver tells us that
5738 * its OK to resume normal operation. Implementation resembles the
5739 * second-half of the igb_resume routine.
5740 */
5741static void igb_io_resume(struct pci_dev *pdev)
5742{
5743 struct net_device *netdev = pci_get_drvdata(pdev);
5744 struct igb_adapter *adapter = netdev_priv(netdev);
5745
9d5c8243
AK		 5746 if (netif_running(netdev)) {
5747 if (igb_up(adapter)) {
5748 dev_err(&pdev->dev, "igb_up failed after reset\n");
5749 return;
5750 }
5751 }
5752
5753 netif_device_attach(netdev);
5754
5755 /* let the f/w know that the h/w is now under the control of the
5756 * driver. */
5757 igb_get_hw_control(adapter);
9d5c8243
AK		 5758}
5759
26ad9178
AD		 5760static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5761 u8 qsel)
5762{
5763 u32 rar_low, rar_high;
5764 struct e1000_hw *hw = &adapter->hw;
5765
5766 /* HW expects these in little endian so we reverse the byte order
5767 * from network order (big endian) to little endian
5768 */
5769 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5770 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5771 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5772
5773 /* Indicate to hardware the Address is Valid. */
5774 rar_high |= E1000_RAH_AV;
5775
5776 if (hw->mac.type == e1000_82575)
5777 rar_high |= E1000_RAH_POOL_1 * qsel;
5778 else
5779 rar_high |= E1000_RAH_POOL_1 << qsel;
5780
5781 wr32(E1000_RAL(index), rar_low);
5782 wrfl();
5783 wr32(E1000_RAH(index), rar_high);
5784 wrfl();
5785}
5786
4ae196df
AD		 5787static int igb_set_vf_mac(struct igb_adapter *adapter,
5788 int vf, unsigned char *mac_addr)
5789{
5790 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5791 /* VF MAC addresses start at end of receive addresses and moves
5792 * torwards the first, as a result a collision should not be possible */
5793 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5794
37680117 5795 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5796
26ad9178 5797 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5798
5799 return 0;
5800}
5801
5802static void igb_vmm_control(struct igb_adapter *adapter)
5803{
5804 struct e1000_hw *hw = &adapter->hw;
5805 u32 reg_data;
5806
5807 if (!adapter->vfs_allocated_count)
5808 return;
5809
5810 /* VF's need PF reset indication before they
5811 * can send/receive mail */
5812 reg_data = rd32(E1000_CTRL_EXT);
5813 reg_data |= E1000_CTRL_EXT_PFRSTD;
5814 wr32(E1000_CTRL_EXT, reg_data);
5815
5816 igb_vmdq_set_loopback_pf(hw, true);
5817 igb_vmdq_set_replication_pf(hw, true);
5818}
5819
9d5c8243 5820/* igb_main.c */
Linux kernel - Deliverables
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