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igb: misc whitespace/formatting cleanups
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
71 {0, }
72};
73
74MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
75
76void igb_reset(struct igb_adapter *);
77static int igb_setup_all_tx_resources(struct igb_adapter *);
78static int igb_setup_all_rx_resources(struct igb_adapter *);
79static void igb_free_all_tx_resources(struct igb_adapter *);
80static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 110#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
421e02f0 114#endif /* CONFIG_IGB_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 119static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
120static void igb_tx_timeout(struct net_device *);
121static void igb_reset_task(struct work_struct *);
122static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
123static void igb_vlan_rx_add_vid(struct net_device *, u16);
124static void igb_vlan_rx_kill_vid(struct net_device *, u16);
125static void igb_restore_vlan(struct igb_adapter *);
126
127static int igb_suspend(struct pci_dev *, pm_message_t);
128#ifdef CONFIG_PM
129static int igb_resume(struct pci_dev *);
130#endif
131static void igb_shutdown(struct pci_dev *);
421e02f0 132#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 133static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
134static struct notifier_block dca_notifier = {
135 .notifier_call = igb_notify_dca,
136 .next = NULL,
137 .priority = 0
138};
139#endif
9d5c8243
AK		 140
141#ifdef CONFIG_NET_POLL_CONTROLLER
142/* for netdump / net console */
143static void igb_netpoll(struct net_device *);
144#endif
145
146static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
147 pci_channel_state_t);
148static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
149static void igb_io_resume(struct pci_dev *);
150
151static struct pci_error_handlers igb_err_handler = {
152 .error_detected = igb_io_error_detected,
153 .slot_reset = igb_io_slot_reset,
154 .resume = igb_io_resume,
155};
156
157
158static struct pci_driver igb_driver = {
159 .name = igb_driver_name,
160 .id_table = igb_pci_tbl,
161 .probe = igb_probe,
162 .remove = __devexit_p(igb_remove),
163#ifdef CONFIG_PM
164 /* Power Managment Hooks */
165 .suspend = igb_suspend,
166 .resume = igb_resume,
167#endif
168 .shutdown = igb_shutdown,
169 .err_handler = &igb_err_handler
170};
171
7dfc16fa
AD		 172static int global_quad_port_a; /* global quad port a indication */
173
9d5c8243
AK		 174MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
175MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
176MODULE_LICENSE("GPL");
177MODULE_VERSION(DRV_VERSION);
178
38c845c7
PO		 179/**
180 * Scale the NIC clock cycle by a large factor so that
181 * relatively small clock corrections can be added or
182 * substracted at each clock tick. The drawbacks of a
183 * large factor are a) that the clock register overflows
184 * more quickly (not such a big deal) and b) that the
185 * increment per tick has to fit into 24 bits.
186 *
187 * Note that
188 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
189 * IGB_TSYNC_SCALE
190 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
191 *
192 * The base scale factor is intentionally a power of two
193 * so that the division in %struct timecounter can be done with
194 * a shift.
195 */
196#define IGB_TSYNC_SHIFT (19)
197#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
198
199/**
200 * The duration of one clock cycle of the NIC.
201 *
202 * @todo This hard-coded value is part of the specification and might change
203 * in future hardware revisions. Add revision check.
204 */
205#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
206
207#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
208# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
209#endif
210
211/**
212 * igb_read_clock - read raw cycle counter (to be used by time counter)
213 */
214static cycle_t igb_read_clock(const struct cyclecounter *tc)
215{
216 struct igb_adapter *adapter =
217 container_of(tc, struct igb_adapter, cycles);
218 struct e1000_hw *hw = &adapter->hw;
219 u64 stamp;
220
221 stamp = rd32(E1000_SYSTIML);
222 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
223
224 return stamp;
225}
226
9d5c8243
AK		 227#ifdef DEBUG
228/**
229 * igb_get_hw_dev_name - return device name string
230 * used by hardware layer to print debugging information
231 **/
232char *igb_get_hw_dev_name(struct e1000_hw *hw)
233{
234 struct igb_adapter *adapter = hw->back;
235 return adapter->netdev->name;
236}
38c845c7
PO		 237
238/**
239 * igb_get_time_str - format current NIC and system time as string
240 */
241static char *igb_get_time_str(struct igb_adapter *adapter,
242 char buffer[160])
243{
244 cycle_t hw = adapter->cycles.read(&adapter->cycles);
245 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
246 struct timespec sys;
247 struct timespec delta;
248 getnstimeofday(&sys);
249
250 delta = timespec_sub(nic, sys);
251
252 sprintf(buffer,
33af6bcc
PO		 253 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
254 hw,
38c845c7
PO		 255 (long)nic.tv_sec, nic.tv_nsec,
256 (long)sys.tv_sec, sys.tv_nsec,
257 (long)delta.tv_sec, delta.tv_nsec);
258
259 return buffer;
260}
9d5c8243
AK		 261#endif
262
263/**
264 * igb_init_module - Driver Registration Routine
265 *
266 * igb_init_module is the first routine called when the driver is
267 * loaded. All it does is register with the PCI subsystem.
268 **/
269static int __init igb_init_module(void)
270{
271 int ret;
272 printk(KERN_INFO "%s - version %s\n",
273 igb_driver_string, igb_driver_version);
274
275 printk(KERN_INFO "%s\n", igb_copyright);
276
7dfc16fa
AD		 277 global_quad_port_a = 0;
278
421e02f0 279#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 280 dca_register_notify(&dca_notifier);
281#endif
bbd98fe4
AD		 282
283 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 284 return ret;
285}
286
287module_init(igb_init_module);
288
289/**
290 * igb_exit_module - Driver Exit Cleanup Routine
291 *
292 * igb_exit_module is called just before the driver is removed
293 * from memory.
294 **/
295static void __exit igb_exit_module(void)
296{
421e02f0 297#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 298 dca_unregister_notify(&dca_notifier);
299#endif
9d5c8243
AK		 300 pci_unregister_driver(&igb_driver);
301}
302
303module_exit(igb_exit_module);
304
26bc19ec
AD		 305#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
306/**
307 * igb_cache_ring_register - Descriptor ring to register mapping
308 * @adapter: board private structure to initialize
309 *
310 * Once we know the feature-set enabled for the device, we'll cache
311 * the register offset the descriptor ring is assigned to.
312 **/
313static void igb_cache_ring_register(struct igb_adapter *adapter)
314{
315 int i;
316
317 switch (adapter->hw.mac.type) {
318 case e1000_82576:
319 /* The queues are allocated for virtualization such that VF 0
320 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
321 * In order to avoid collision we start at the first free queue
322 * and continue consuming queues in the same sequence
323 */
324 for (i = 0; i < adapter->num_rx_queues; i++)
325 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
326 for (i = 0; i < adapter->num_tx_queues; i++)
327 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
328 break;
329 case e1000_82575:
330 default:
331 for (i = 0; i < adapter->num_rx_queues; i++)
332 adapter->rx_ring[i].reg_idx = i;
333 for (i = 0; i < adapter->num_tx_queues; i++)
334 adapter->tx_ring[i].reg_idx = i;
335 break;
336 }
337}
338
9d5c8243
AK		 339/**
340 * igb_alloc_queues - Allocate memory for all rings
341 * @adapter: board private structure to initialize
342 *
343 * We allocate one ring per queue at run-time since we don't know the
344 * number of queues at compile-time.
345 **/
346static int igb_alloc_queues(struct igb_adapter *adapter)
347{
348 int i;
349
350 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
351 sizeof(struct igb_ring), GFP_KERNEL);
352 if (!adapter->tx_ring)
353 return -ENOMEM;
354
355 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
356 sizeof(struct igb_ring), GFP_KERNEL);
357 if (!adapter->rx_ring) {
358 kfree(adapter->tx_ring);
359 return -ENOMEM;
360 }
361
6eb5a7f1
AD		 362 adapter->rx_ring->buddy = adapter->tx_ring;
363
661086df
PWJ		 364 for (i = 0; i < adapter->num_tx_queues; i++) {
365 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 366 ring->count = adapter->tx_ring_count;
661086df
PWJ		 367 ring->adapter = adapter;
368 ring->queue_index = i;
369 }
9d5c8243
AK		 370 for (i = 0; i < adapter->num_rx_queues; i++) {
371 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 372 ring->count = adapter->rx_ring_count;
9d5c8243 373 ring->adapter = adapter;
844290e5 374 ring->queue_index = i;
9d5c8243
AK		 375 ring->itr_register = E1000_ITR;
376
844290e5 377 /* set a default napi handler for each rx_ring */
661086df 378 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 379 }
26bc19ec
AD		 380
381 igb_cache_ring_register(adapter);
9d5c8243
AK		 382 return 0;
383}
384
a88f10ec
AD		 385static void igb_free_queues(struct igb_adapter *adapter)
386{
387 int i;
388
389 for (i = 0; i < adapter->num_rx_queues; i++)
390 netif_napi_del(&adapter->rx_ring[i].napi);
391
392 kfree(adapter->tx_ring);
393 kfree(adapter->rx_ring);
394}
395
9d5c8243
AK		 396#define IGB_N0_QUEUE -1
397static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
398 int tx_queue, int msix_vector)
399{
400 u32 msixbm = 0;
401 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 402 u32 ivar, index;
403
404 switch (hw->mac.type) {
405 case e1000_82575:
9d5c8243
AK		 406 /* The 82575 assigns vectors using a bitmask, which matches the
407 bitmask for the EICR/EIMS/EIMC registers. To assign one
408 or more queues to a vector, we write the appropriate bits
409 into the MSIXBM register for that vector. */
410 if (rx_queue > IGB_N0_QUEUE) {
411 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
412 adapter->rx_ring[rx_queue].eims_value = msixbm;
413 }
414 if (tx_queue > IGB_N0_QUEUE) {
415 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
416 adapter->tx_ring[tx_queue].eims_value =
417 E1000_EICR_TX_QUEUE0 << tx_queue;
418 }
419 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 420 break;
421 case e1000_82576:
26bc19ec 422 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 423 Each queue has a single entry in the table to which we write
424 a vector number along with a "valid" bit. Sadly, the layout
425 of the table is somewhat counterintuitive. */
426 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 427 index = (rx_queue >> 1);
2d064c06 428 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 429 if (rx_queue & 0x1) {
2d064c06
AD		 430 /* vector goes into third byte of register */
431 ivar = ivar & 0xFF00FFFF;
432 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 433 } else {
434 /* vector goes into low byte of register */
435 ivar = ivar & 0xFFFFFF00;
436 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 437 }
438 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
439 array_wr32(E1000_IVAR0, index, ivar);
440 }
441 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 442 index = (tx_queue >> 1);
2d064c06 443 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 444 if (tx_queue & 0x1) {
2d064c06
AD		 445 /* vector goes into high byte of register */
446 ivar = ivar & 0x00FFFFFF;
447 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 448 } else {
449 /* vector goes into second byte of register */
450 ivar = ivar & 0xFFFF00FF;
451 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 452 }
453 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
454 array_wr32(E1000_IVAR0, index, ivar);
455 }
456 break;
457 default:
458 BUG();
459 break;
460 }
9d5c8243
AK		 461}
462
463/**
464 * igb_configure_msix - Configure MSI-X hardware
465 *
466 * igb_configure_msix sets up the hardware to properly
467 * generate MSI-X interrupts.
468 **/
469static void igb_configure_msix(struct igb_adapter *adapter)
470{
471 u32 tmp;
472 int i, vector = 0;
473 struct e1000_hw *hw = &adapter->hw;
474
475 adapter->eims_enable_mask = 0;
2d064c06
AD		 476 if (hw->mac.type == e1000_82576)
477 /* Turn on MSI-X capability first, or our settings
478 * won't stick. And it will take days to debug. */
479 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 480 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 481 E1000_GPIE_NSICR);
9d5c8243
AK		 482
483 for (i = 0; i < adapter->num_tx_queues; i++) {
484 struct igb_ring *tx_ring = &adapter->tx_ring[i];
485 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
486 adapter->eims_enable_mask |= tx_ring->eims_value;
487 if (tx_ring->itr_val)
6eb5a7f1 488 writel(tx_ring->itr_val,
9d5c8243
AK		 489 hw->hw_addr + tx_ring->itr_register);
490 else
491 writel(1, hw->hw_addr + tx_ring->itr_register);
492 }
493
494 for (i = 0; i < adapter->num_rx_queues; i++) {
495 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 496 rx_ring->buddy = NULL;
9d5c8243
AK		 497 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
498 adapter->eims_enable_mask |= rx_ring->eims_value;
499 if (rx_ring->itr_val)
6eb5a7f1 500 writel(rx_ring->itr_val,
9d5c8243
AK		 501 hw->hw_addr + rx_ring->itr_register);
502 else
503 writel(1, hw->hw_addr + rx_ring->itr_register);
504 }
505
506
507 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 508 switch (hw->mac.type) {
509 case e1000_82575:
9d5c8243
AK		 510 array_wr32(E1000_MSIXBM(0), vector++,
511 E1000_EIMS_OTHER);
512
9d5c8243
AK		 513 tmp = rd32(E1000_CTRL_EXT);
514 /* enable MSI-X PBA support*/
515 tmp |= E1000_CTRL_EXT_PBA_CLR;
516
517 /* Auto-Mask interrupts upon ICR read. */
518 tmp |= E1000_CTRL_EXT_EIAME;
519 tmp |= E1000_CTRL_EXT_IRCA;
520
521 wr32(E1000_CTRL_EXT, tmp);
522 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 523 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 524
2d064c06
AD		 525 break;
526
527 case e1000_82576:
528 tmp = (vector++ | E1000_IVAR_VALID) << 8;
529 wr32(E1000_IVAR_MISC, tmp);
530
531 adapter->eims_enable_mask = (1 << (vector)) - 1;
532 adapter->eims_other = 1 << (vector - 1);
533 break;
534 default:
535 /* do nothing, since nothing else supports MSI-X */
536 break;
537 } /* switch (hw->mac.type) */
9d5c8243
AK		 538 wrfl();
539}
540
541/**
542 * igb_request_msix - Initialize MSI-X interrupts
543 *
544 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
545 * kernel.
546 **/
547static int igb_request_msix(struct igb_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 int i, err = 0, vector = 0;
551
552 vector = 0;
553
554 for (i = 0; i < adapter->num_tx_queues; i++) {
555 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 556 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 557 err = request_irq(adapter->msix_entries[vector].vector,
558 &igb_msix_tx, 0, ring->name,
559 &(adapter->tx_ring[i]));
560 if (err)
561 goto out;
562 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 563 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 564 vector++;
565 }
566 for (i = 0; i < adapter->num_rx_queues; i++) {
567 struct igb_ring *ring = &(adapter->rx_ring[i]);
568 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 569 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 570 else
571 memcpy(ring->name, netdev->name, IFNAMSIZ);
572 err = request_irq(adapter->msix_entries[vector].vector,
573 &igb_msix_rx, 0, ring->name,
574 &(adapter->rx_ring[i]));
575 if (err)
576 goto out;
577 ring->itr_register = E1000_EITR(0) + (vector << 2);
578 ring->itr_val = adapter->itr;
844290e5
PW		 579 /* overwrite the poll routine for MSIX, we've already done
580 * netif_napi_add */
581 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 582 vector++;
583 }
584
585 err = request_irq(adapter->msix_entries[vector].vector,
586 &igb_msix_other, 0, netdev->name, netdev);
587 if (err)
588 goto out;
589
9d5c8243
AK		 590 igb_configure_msix(adapter);
591 return 0;
592out:
593 return err;
594}
595
596static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
597{
598 if (adapter->msix_entries) {
599 pci_disable_msix(adapter->pdev);
600 kfree(adapter->msix_entries);
601 adapter->msix_entries = NULL;
7dfc16fa 602 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 603 pci_disable_msi(adapter->pdev);
604 return;
605}
606
607
608/**
609 * igb_set_interrupt_capability - set MSI or MSI-X if supported
610 *
611 * Attempt to configure interrupts using the best available
612 * capabilities of the hardware and kernel.
613 **/
614static void igb_set_interrupt_capability(struct igb_adapter *adapter)
615{
616 int err;
617 int numvecs, i;
618
83b7180d
AD		 619 /* Number of supported queues. */
620 /* Having more queues than CPUs doesn't make sense. */
621 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
622 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
623
9d5c8243
AK		 624 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
625 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
626 GFP_KERNEL);
627 if (!adapter->msix_entries)
628 goto msi_only;
629
630 for (i = 0; i < numvecs; i++)
631 adapter->msix_entries[i].entry = i;
632
633 err = pci_enable_msix(adapter->pdev,
634 adapter->msix_entries,
635 numvecs);
636 if (err == 0)
34a20e89 637 goto out;
9d5c8243
AK		 638
639 igb_reset_interrupt_capability(adapter);
640
641 /* If we can't do MSI-X, try MSI */
642msi_only:
643 adapter->num_rx_queues = 1;
661086df 644 adapter->num_tx_queues = 1;
9d5c8243 645 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 646 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 647out:
661086df 648 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 649 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 650 return;
651}
652
653/**
654 * igb_request_irq - initialize interrupts
655 *
656 * Attempts to configure interrupts using the best available
657 * capabilities of the hardware and kernel.
658 **/
659static int igb_request_irq(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 struct e1000_hw *hw = &adapter->hw;
663 int err = 0;
664
665 if (adapter->msix_entries) {
666 err = igb_request_msix(adapter);
844290e5 667 if (!err)
9d5c8243 668 goto request_done;
9d5c8243
AK		 669 /* fall back to MSI */
670 igb_reset_interrupt_capability(adapter);
671 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 672 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 673 igb_free_all_tx_resources(adapter);
674 igb_free_all_rx_resources(adapter);
675 adapter->num_rx_queues = 1;
676 igb_alloc_queues(adapter);
844290e5 677 } else {
2d064c06
AD		 678 switch (hw->mac.type) {
679 case e1000_82575:
680 wr32(E1000_MSIXBM(0),
681 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
682 break;
683 case e1000_82576:
684 wr32(E1000_IVAR0, E1000_IVAR_VALID);
685 break;
686 default:
687 break;
688 }
9d5c8243 689 }
844290e5 690
7dfc16fa 691 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 692 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
693 netdev->name, netdev);
694 if (!err)
695 goto request_done;
696 /* fall back to legacy interrupts */
697 igb_reset_interrupt_capability(adapter);
7dfc16fa 698 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 699 }
700
701 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
702 netdev->name, netdev);
703
6cb5e577 704 if (err)
9d5c8243
AK		 705 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
706 err);
9d5c8243
AK		 707
708request_done:
709 return err;
710}
711
712static void igb_free_irq(struct igb_adapter *adapter)
713{
714 struct net_device *netdev = adapter->netdev;
715
716 if (adapter->msix_entries) {
717 int vector = 0, i;
718
719 for (i = 0; i < adapter->num_tx_queues; i++)
720 free_irq(adapter->msix_entries[vector++].vector,
721 &(adapter->tx_ring[i]));
722 for (i = 0; i < adapter->num_rx_queues; i++)
723 free_irq(adapter->msix_entries[vector++].vector,
724 &(adapter->rx_ring[i]));
725
726 free_irq(adapter->msix_entries[vector++].vector, netdev);
727 return;
728 }
729
730 free_irq(adapter->pdev->irq, netdev);
731}
732
733/**
734 * igb_irq_disable - Mask off interrupt generation on the NIC
735 * @adapter: board private structure
736 **/
737static void igb_irq_disable(struct igb_adapter *adapter)
738{
739 struct e1000_hw *hw = &adapter->hw;
740
741 if (adapter->msix_entries) {
844290e5 742 wr32(E1000_EIAM, 0);
9d5c8243
AK		 743 wr32(E1000_EIMC, ~0);
744 wr32(E1000_EIAC, 0);
745 }
844290e5
PW		 746
747 wr32(E1000_IAM, 0);
9d5c8243
AK		 748 wr32(E1000_IMC, ~0);
749 wrfl();
750 synchronize_irq(adapter->pdev->irq);
751}
752
753/**
754 * igb_irq_enable - Enable default interrupt generation settings
755 * @adapter: board private structure
756 **/
757static void igb_irq_enable(struct igb_adapter *adapter)
758{
759 struct e1000_hw *hw = &adapter->hw;
760
761 if (adapter->msix_entries) {
844290e5
PW		 762 wr32(E1000_EIAC, adapter->eims_enable_mask);
763 wr32(E1000_EIAM, adapter->eims_enable_mask);
764 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 765 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 766 } else {
767 wr32(E1000_IMS, IMS_ENABLE_MASK);
768 wr32(E1000_IAM, IMS_ENABLE_MASK);
769 }
9d5c8243
AK		 770}
771
772static void igb_update_mng_vlan(struct igb_adapter *adapter)
773{
774 struct net_device *netdev = adapter->netdev;
775 u16 vid = adapter->hw.mng_cookie.vlan_id;
776 u16 old_vid = adapter->mng_vlan_id;
777 if (adapter->vlgrp) {
778 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
779 if (adapter->hw.mng_cookie.status &
780 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
781 igb_vlan_rx_add_vid(netdev, vid);
782 adapter->mng_vlan_id = vid;
783 } else
784 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
785
786 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
787 (vid != old_vid) &&
788 !vlan_group_get_device(adapter->vlgrp, old_vid))
789 igb_vlan_rx_kill_vid(netdev, old_vid);
790 } else
791 adapter->mng_vlan_id = vid;
792 }
793}
794
795/**
796 * igb_release_hw_control - release control of the h/w to f/w
797 * @adapter: address of board private structure
798 *
799 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
800 * For ASF and Pass Through versions of f/w this means that the
801 * driver is no longer loaded.
802 *
803 **/
804static void igb_release_hw_control(struct igb_adapter *adapter)
805{
806 struct e1000_hw *hw = &adapter->hw;
807 u32 ctrl_ext;
808
809 /* Let firmware take over control of h/w */
810 ctrl_ext = rd32(E1000_CTRL_EXT);
811 wr32(E1000_CTRL_EXT,
812 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
813}
814
815
816/**
817 * igb_get_hw_control - get control of the h/w from f/w
818 * @adapter: address of board private structure
819 *
820 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
821 * For ASF and Pass Through versions of f/w this means that
822 * the driver is loaded.
823 *
824 **/
825static void igb_get_hw_control(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 u32 ctrl_ext;
829
830 /* Let firmware know the driver has taken over */
831 ctrl_ext = rd32(E1000_CTRL_EXT);
832 wr32(E1000_CTRL_EXT,
833 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
834}
835
9d5c8243
AK		 836/**
837 * igb_configure - configure the hardware for RX and TX
838 * @adapter: private board structure
839 **/
840static void igb_configure(struct igb_adapter *adapter)
841{
842 struct net_device *netdev = adapter->netdev;
843 int i;
844
845 igb_get_hw_control(adapter);
846 igb_set_multi(netdev);
847
848 igb_restore_vlan(adapter);
9d5c8243
AK		 849
850 igb_configure_tx(adapter);
851 igb_setup_rctl(adapter);
852 igb_configure_rx(adapter);
662d7205
AD		 853
854 igb_rx_fifo_flush_82575(&adapter->hw);
855
9d5c8243
AK		 856 /* call IGB_DESC_UNUSED which always leaves
857 * at least 1 descriptor unused to make sure
858 * next_to_use != next_to_clean */
859 for (i = 0; i < adapter->num_rx_queues; i++) {
860 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 861 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 862 }
863
864
865 adapter->tx_queue_len = netdev->tx_queue_len;
866}
867
868
869/**
870 * igb_up - Open the interface and prepare it to handle traffic
871 * @adapter: board private structure
872 **/
873
874int igb_up(struct igb_adapter *adapter)
875{
876 struct e1000_hw *hw = &adapter->hw;
877 int i;
878
879 /* hardware has been reset, we need to reload some things */
880 igb_configure(adapter);
881
882 clear_bit(__IGB_DOWN, &adapter->state);
883
844290e5
PW		 884 for (i = 0; i < adapter->num_rx_queues; i++)
885 napi_enable(&adapter->rx_ring[i].napi);
886 if (adapter->msix_entries)
9d5c8243 887 igb_configure_msix(adapter);
9d5c8243
AK		 888
889 /* Clear any pending interrupts. */
890 rd32(E1000_ICR);
891 igb_irq_enable(adapter);
892
893 /* Fire a link change interrupt to start the watchdog. */
894 wr32(E1000_ICS, E1000_ICS_LSC);
895 return 0;
896}
897
898void igb_down(struct igb_adapter *adapter)
899{
900 struct e1000_hw *hw = &adapter->hw;
901 struct net_device *netdev = adapter->netdev;
902 u32 tctl, rctl;
903 int i;
904
905 /* signal that we're down so the interrupt handler does not
906 * reschedule our watchdog timer */
907 set_bit(__IGB_DOWN, &adapter->state);
908
909 /* disable receives in the hardware */
910 rctl = rd32(E1000_RCTL);
911 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
912 /* flush and sleep below */
913
fd2ea0a7 914 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 915
916 /* disable transmits in the hardware */
917 tctl = rd32(E1000_TCTL);
918 tctl &= ~E1000_TCTL_EN;
919 wr32(E1000_TCTL, tctl);
920 /* flush both disables and wait for them to finish */
921 wrfl();
922 msleep(10);
923
844290e5
PW		 924 for (i = 0; i < adapter->num_rx_queues; i++)
925 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 926
9d5c8243
AK		 927 igb_irq_disable(adapter);
928
929 del_timer_sync(&adapter->watchdog_timer);
930 del_timer_sync(&adapter->phy_info_timer);
931
932 netdev->tx_queue_len = adapter->tx_queue_len;
933 netif_carrier_off(netdev);
04fe6358
AD		 934
935 /* record the stats before reset*/
936 igb_update_stats(adapter);
937
9d5c8243
AK		 938 adapter->link_speed = 0;
939 adapter->link_duplex = 0;
940
3023682e
JK		 941 if (!pci_channel_offline(adapter->pdev))
942 igb_reset(adapter);
9d5c8243
AK		 943 igb_clean_all_tx_rings(adapter);
944 igb_clean_all_rx_rings(adapter);
945}
946
947void igb_reinit_locked(struct igb_adapter *adapter)
948{
949 WARN_ON(in_interrupt());
950 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
951 msleep(1);
952 igb_down(adapter);
953 igb_up(adapter);
954 clear_bit(__IGB_RESETTING, &adapter->state);
955}
956
957void igb_reset(struct igb_adapter *adapter)
958{
959 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 960 struct e1000_mac_info *mac = &hw->mac;
961 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 962 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
963 u16 hwm;
964
965 /* Repartition Pba for greater than 9k mtu
966 * To take effect CTRL.RST is required.
967 */
fa4dfae0
AD		 968 switch (mac->type) {
969 case e1000_82576:
2d064c06 970 pba = E1000_PBA_64K;
fa4dfae0
AD		 971 break;
972 case e1000_82575:
973 default:
974 pba = E1000_PBA_34K;
975 break;
2d064c06 976 }
9d5c8243 977
2d064c06
AD		 978 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
979 (mac->type < e1000_82576)) {
9d5c8243
AK		 980 /* adjust PBA for jumbo frames */
981 wr32(E1000_PBA, pba);
982
983 /* To maintain wire speed transmits, the Tx FIFO should be
984 * large enough to accommodate two full transmit packets,
985 * rounded up to the next 1KB and expressed in KB. Likewise,
986 * the Rx FIFO should be large enough to accommodate at least
987 * one full receive packet and is similarly rounded up and
988 * expressed in KB. */
989 pba = rd32(E1000_PBA);
990 /* upper 16 bits has Tx packet buffer allocation size in KB */
991 tx_space = pba >> 16;
992 /* lower 16 bits has Rx packet buffer allocation size in KB */
993 pba &= 0xffff;
994 /* the tx fifo also stores 16 bytes of information about the tx
995 * but don't include ethernet FCS because hardware appends it */
996 min_tx_space = (adapter->max_frame_size +
997 sizeof(struct e1000_tx_desc) -
998 ETH_FCS_LEN) * 2;
999 min_tx_space = ALIGN(min_tx_space, 1024);
1000 min_tx_space >>= 10;
1001 /* software strips receive CRC, so leave room for it */
1002 min_rx_space = adapter->max_frame_size;
1003 min_rx_space = ALIGN(min_rx_space, 1024);
1004 min_rx_space >>= 10;
1005
1006 /* If current Tx allocation is less than the min Tx FIFO size,
1007 * and the min Tx FIFO size is less than the current Rx FIFO
1008 * allocation, take space away from current Rx allocation */
1009 if (tx_space < min_tx_space &&
1010 ((min_tx_space - tx_space) < pba)) {
1011 pba = pba - (min_tx_space - tx_space);
1012
1013 /* if short on rx space, rx wins and must trump tx
1014 * adjustment */
1015 if (pba < min_rx_space)
1016 pba = min_rx_space;
1017 }
2d064c06 1018 wr32(E1000_PBA, pba);
9d5c8243 1019 }
9d5c8243
AK		 1020
1021 /* flow control settings */
1022 /* The high water mark must be low enough to fit one full frame
1023 * (or the size used for early receive) above it in the Rx FIFO.
1024 * Set it to the lower of:
1025 * - 90% of the Rx FIFO size, or
1026 * - the full Rx FIFO size minus one full frame */
1027 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1028 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1029
2d064c06
AD		 1030 if (mac->type < e1000_82576) {
1031 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1032 fc->low_water = fc->high_water - 8;
1033 } else {
1034 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1035 fc->low_water = fc->high_water - 16;
1036 }
9d5c8243
AK		 1037 fc->pause_time = 0xFFFF;
1038 fc->send_xon = 1;
1039 fc->type = fc->original_type;
1040
1041 /* Allow time for pending master requests to run */
1042 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1043 wr32(E1000_WUC, 0);
1044
1045 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1046 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1047
1048 igb_update_mng_vlan(adapter);
1049
1050 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1051 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1052
1053 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1054 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1055}
1056
2e5c6922
SH		 1057static const struct net_device_ops igb_netdev_ops = {
1058 .ndo_open = igb_open,
1059 .ndo_stop = igb_close,
00829823 1060 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1061 .ndo_get_stats = igb_get_stats,
1062 .ndo_set_multicast_list = igb_set_multi,
1063 .ndo_set_mac_address = igb_set_mac,
1064 .ndo_change_mtu = igb_change_mtu,
1065 .ndo_do_ioctl = igb_ioctl,
1066 .ndo_tx_timeout = igb_tx_timeout,
1067 .ndo_validate_addr = eth_validate_addr,
1068 .ndo_vlan_rx_register = igb_vlan_rx_register,
1069 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1070 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1071#ifdef CONFIG_NET_POLL_CONTROLLER
1072 .ndo_poll_controller = igb_netpoll,
1073#endif
1074};
1075
9d5c8243
AK		 1076/**
1077 * igb_probe - Device Initialization Routine
1078 * @pdev: PCI device information struct
1079 * @ent: entry in igb_pci_tbl
1080 *
1081 * Returns 0 on success, negative on failure
1082 *
1083 * igb_probe initializes an adapter identified by a pci_dev structure.
1084 * The OS initialization, configuring of the adapter private structure,
1085 * and a hardware reset occur.
1086 **/
1087static int __devinit igb_probe(struct pci_dev *pdev,
1088 const struct pci_device_id *ent)
1089{
1090 struct net_device *netdev;
1091 struct igb_adapter *adapter;
1092 struct e1000_hw *hw;
c54106bb 1093 struct pci_dev *us_dev;
9d5c8243
AK		 1094 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1095 unsigned long mmio_start, mmio_len;
450c87c8 1096 int err, pci_using_dac, pos;
c54106bb 1097 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1098 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1099 u32 part_num;
1100
aed5dec3 1101 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1102 if (err)
1103 return err;
1104
1105 pci_using_dac = 0;
1106 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1107 if (!err) {
1108 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1109 if (!err)
1110 pci_using_dac = 1;
1111 } else {
1112 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1113 if (err) {
1114 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1115 if (err) {
1116 dev_err(&pdev->dev, "No usable DMA "
1117 "configuration, aborting\n");
1118 goto err_dma;
1119 }
1120 }
1121 }
1122
c54106bb
AD		 1123 /* 82575 requires that the pci-e link partner disable the L0s state */
1124 switch (pdev->device) {
1125 case E1000_DEV_ID_82575EB_COPPER:
1126 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1127 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1128 us_dev = pdev->bus->self;
1129 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1130 if (pos) {
1131 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1132 &state);
1133 state &= ~PCIE_LINK_STATE_L0S;
1134 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1135 state);
ac450208
BH		 1136 dev_info(&pdev->dev,
1137 "Disabling ASPM L0s upstream switch port %s\n",
1138 pci_name(us_dev));
c54106bb
AD		 1139 }
1140 default:
1141 break;
1142 }
1143
aed5dec3
AD		 1144 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1145 IORESOURCE_MEM),
1146 igb_driver_name);
9d5c8243
AK		 1147 if (err)
1148 goto err_pci_reg;
1149
ea943d41
JK		 1150 err = pci_enable_pcie_error_reporting(pdev);
1151 if (err) {
1152 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1153 "0x%x\n", err);
1154 /* non-fatal, continue */
1155 }
40a914fa 1156
9d5c8243 1157 pci_set_master(pdev);
c682fc23 1158 pci_save_state(pdev);
9d5c8243
AK		 1159
1160 err = -ENOMEM;
661086df 1161 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1162 if (!netdev)
1163 goto err_alloc_etherdev;
1164
1165 SET_NETDEV_DEV(netdev, &pdev->dev);
1166
1167 pci_set_drvdata(pdev, netdev);
1168 adapter = netdev_priv(netdev);
1169 adapter->netdev = netdev;
1170 adapter->pdev = pdev;
1171 hw = &adapter->hw;
1172 hw->back = adapter;
1173 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1174
1175 mmio_start = pci_resource_start(pdev, 0);
1176 mmio_len = pci_resource_len(pdev, 0);
1177
1178 err = -EIO;
28b0759c
AD		 1179 hw->hw_addr = ioremap(mmio_start, mmio_len);
1180 if (!hw->hw_addr)
9d5c8243
AK		 1181 goto err_ioremap;
1182
2e5c6922 1183 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1184 igb_set_ethtool_ops(netdev);
9d5c8243 1185 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1186
1187 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1188
1189 netdev->mem_start = mmio_start;
1190 netdev->mem_end = mmio_start + mmio_len;
1191
9d5c8243
AK		 1192 /* PCI config space info */
1193 hw->vendor_id = pdev->vendor;
1194 hw->device_id = pdev->device;
1195 hw->revision_id = pdev->revision;
1196 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1197 hw->subsystem_device_id = pdev->subsystem_device;
1198
1199 /* setup the private structure */
1200 hw->back = adapter;
1201 /* Copy the default MAC, PHY and NVM function pointers */
1202 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1203 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1204 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1205 /* Initialize skew-specific constants */
1206 err = ei->get_invariants(hw);
1207 if (err)
450c87c8 1208 goto err_sw_init;
9d5c8243 1209
450c87c8 1210 /* setup the private structure */
9d5c8243
AK		 1211 err = igb_sw_init(adapter);
1212 if (err)
1213 goto err_sw_init;
1214
1215 igb_get_bus_info_pcie(hw);
1216
7dfc16fa
AD		 1217 /* set flags */
1218 switch (hw->mac.type) {
7dfc16fa 1219 case e1000_82575:
7dfc16fa
AD		 1220 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1221 break;
bbd98fe4 1222 case e1000_82576:
7dfc16fa
AD		 1223 default:
1224 break;
1225 }
1226
9d5c8243
AK		 1227 hw->phy.autoneg_wait_to_complete = false;
1228 hw->mac.adaptive_ifs = true;
1229
1230 /* Copper options */
1231 if (hw->phy.media_type == e1000_media_type_copper) {
1232 hw->phy.mdix = AUTO_ALL_MODES;
1233 hw->phy.disable_polarity_correction = false;
1234 hw->phy.ms_type = e1000_ms_hw_default;
1235 }
1236
1237 if (igb_check_reset_block(hw))
1238 dev_info(&pdev->dev,
1239 "PHY reset is blocked due to SOL/IDER session.\n");
1240
1241 netdev->features = NETIF_F_SG |
7d8eb29e 1242 NETIF_F_IP_CSUM |
9d5c8243
AK		 1243 NETIF_F_HW_VLAN_TX |
1244 NETIF_F_HW_VLAN_RX |
1245 NETIF_F_HW_VLAN_FILTER;
1246
7d8eb29e 1247 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1248 netdev->features |= NETIF_F_TSO;
9d5c8243 1249 netdev->features |= NETIF_F_TSO6;
48f29ffc 1250
d3352520 1251#ifdef CONFIG_IGB_LRO
5c0999b7 1252 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1253#endif
1254
48f29ffc
JK		 1255 netdev->vlan_features |= NETIF_F_TSO;
1256 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1257 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1258 netdev->vlan_features |= NETIF_F_SG;
1259
9d5c8243
AK		 1260 if (pci_using_dac)
1261 netdev->features |= NETIF_F_HIGHDMA;
1262
9d5c8243
AK		 1263 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1264
1265 /* before reading the NVM, reset the controller to put the device in a
1266 * known good starting state */
1267 hw->mac.ops.reset_hw(hw);
1268
1269 /* make sure the NVM is good */
1270 if (igb_validate_nvm_checksum(hw) < 0) {
1271 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1272 err = -EIO;
1273 goto err_eeprom;
1274 }
1275
1276 /* copy the MAC address out of the NVM */
1277 if (hw->mac.ops.read_mac_addr(hw))
1278 dev_err(&pdev->dev, "NVM Read Error\n");
1279
1280 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1281 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1282
1283 if (!is_valid_ether_addr(netdev->perm_addr)) {
1284 dev_err(&pdev->dev, "Invalid MAC Address\n");
1285 err = -EIO;
1286 goto err_eeprom;
1287 }
1288
1289 init_timer(&adapter->watchdog_timer);
1290 adapter->watchdog_timer.function = &igb_watchdog;
1291 adapter->watchdog_timer.data = (unsigned long) adapter;
1292
1293 init_timer(&adapter->phy_info_timer);
1294 adapter->phy_info_timer.function = &igb_update_phy_info;
1295 adapter->phy_info_timer.data = (unsigned long) adapter;
1296
1297 INIT_WORK(&adapter->reset_task, igb_reset_task);
1298 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1299
450c87c8 1300 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1301 adapter->fc_autoneg = true;
1302 hw->mac.autoneg = true;
1303 hw->phy.autoneg_advertised = 0x2f;
1304
1305 hw->fc.original_type = e1000_fc_default;
1306 hw->fc.type = e1000_fc_default;
1307
1308 adapter->itr_setting = 3;
1309 adapter->itr = IGB_START_ITR;
1310
1311 igb_validate_mdi_setting(hw);
1312
1313 adapter->rx_csum = 1;
1314
1315 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1316 * enable the ACPI Magic Packet filter
1317 */
1318
1319 if (hw->bus.func == 0 ||
1320 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1321 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1322
1323 if (eeprom_data & eeprom_apme_mask)
1324 adapter->eeprom_wol |= E1000_WUFC_MAG;
1325
1326 /* now that we have the eeprom settings, apply the special cases where
1327 * the eeprom may be wrong or the board simply won't support wake on
1328 * lan on a particular port */
1329 switch (pdev->device) {
1330 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1331 adapter->eeprom_wol = 0;
1332 break;
1333 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1334 case E1000_DEV_ID_82576_FIBER:
1335 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1336 /* Wake events only supported on port A for dual fiber
1337 * regardless of eeprom setting */
1338 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1339 adapter->eeprom_wol = 0;
1340 break;
1341 }
1342
1343 /* initialize the wol settings based on the eeprom settings */
1344 adapter->wol = adapter->eeprom_wol;
e1b86d84 1345 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1346
1347 /* reset the hardware with the new settings */
1348 igb_reset(adapter);
1349
1350 /* let the f/w know that the h/w is now under the control of the
1351 * driver. */
1352 igb_get_hw_control(adapter);
1353
1354 /* tell the stack to leave us alone until igb_open() is called */
1355 netif_carrier_off(netdev);
fd2ea0a7 1356 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1357
1358 strcpy(netdev->name, "eth%d");
1359 err = register_netdev(netdev);
1360 if (err)
1361 goto err_register;
1362
421e02f0 1363#ifdef CONFIG_IGB_DCA
bbd98fe4 1364 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1365 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1366 dev_info(&pdev->dev, "DCA enabled\n");
1367 /* Always use CB2 mode, difference is masked
1368 * in the CB driver. */
1369 wr32(E1000_DCA_CTRL, 2);
1370 igb_setup_dca(adapter);
1371 }
1372#endif
1373
38c845c7
PO		 1374 /*
1375 * Initialize hardware timer: we keep it running just in case
1376 * that some program needs it later on.
1377 */
1378 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1379 adapter->cycles.read = igb_read_clock;
1380 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1381 adapter->cycles.mult = 1;
1382 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1383 wr32(E1000_TIMINCA,
1384 (1<<24) |
1385 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1386#if 0
1387 /*
1388 * Avoid rollover while we initialize by resetting the time counter.
1389 */
1390 wr32(E1000_SYSTIML, 0x00000000);
1391 wr32(E1000_SYSTIMH, 0x00000000);
1392#else
1393 /*
1394 * Set registers so that rollover occurs soon to test this.
1395 */
1396 wr32(E1000_SYSTIML, 0x00000000);
1397 wr32(E1000_SYSTIMH, 0xFF800000);
1398#endif
1399 wrfl();
1400 timecounter_init(&adapter->clock,
1401 &adapter->cycles,
1402 ktime_to_ns(ktime_get_real()));
1403
33af6bcc
PO		 1404 /*
1405 * Synchronize our NIC clock against system wall clock. NIC
1406 * time stamp reading requires ~3us per sample, each sample
1407 * was pretty stable even under load => only require 10
1408 * samples for each offset comparison.
1409 */
1410 memset(&adapter->compare, 0, sizeof(adapter->compare));
1411 adapter->compare.source = &adapter->clock;
1412 adapter->compare.target = ktime_get_real;
1413 adapter->compare.num_samples = 10;
1414 timecompare_update(&adapter->compare, 0);
1415
38c845c7
PO		 1416#ifdef DEBUG
1417 {
1418 char buffer[160];
1419 printk(KERN_DEBUG
1420 "igb: %s: hw %p initialized timer\n",
1421 igb_get_time_str(adapter, buffer),
1422 &adapter->hw);
1423 }
1424#endif
1425
9d5c8243
AK		 1426 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1427 /* print bus type/speed/width info */
7c510e4b 1428 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1429 netdev->name,
1430 ((hw->bus.speed == e1000_bus_speed_2500)
1431 ? "2.5Gb/s" : "unknown"),
1432 ((hw->bus.width == e1000_bus_width_pcie_x4)
1433 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1434 ? "Width x1" : "unknown"),
7c510e4b 1435 netdev->dev_addr);
9d5c8243
AK		 1436
1437 igb_read_part_num(hw, &part_num);
1438 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1439 (part_num >> 8), (part_num & 0xff));
1440
1441 dev_info(&pdev->dev,
1442 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1443 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1444 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1445 adapter->num_rx_queues, adapter->num_tx_queues);
1446
9d5c8243
AK		 1447 return 0;
1448
1449err_register:
1450 igb_release_hw_control(adapter);
1451err_eeprom:
1452 if (!igb_check_reset_block(hw))
f5f4cf08 1453 igb_reset_phy(hw);
9d5c8243
AK		 1454
1455 if (hw->flash_address)
1456 iounmap(hw->flash_address);
1457
a88f10ec 1458 igb_free_queues(adapter);
9d5c8243 1459err_sw_init:
9d5c8243
AK		 1460 iounmap(hw->hw_addr);
1461err_ioremap:
1462 free_netdev(netdev);
1463err_alloc_etherdev:
aed5dec3
AD		 1464 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1465 IORESOURCE_MEM));
9d5c8243
AK		 1466err_pci_reg:
1467err_dma:
1468 pci_disable_device(pdev);
1469 return err;
1470}
1471
1472/**
1473 * igb_remove - Device Removal Routine
1474 * @pdev: PCI device information struct
1475 *
1476 * igb_remove is called by the PCI subsystem to alert the driver
1477 * that it should release a PCI device. The could be caused by a
1478 * Hot-Plug event, or because the driver is going to be removed from
1479 * memory.
1480 **/
1481static void __devexit igb_remove(struct pci_dev *pdev)
1482{
1483 struct net_device *netdev = pci_get_drvdata(pdev);
1484 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1485 struct e1000_hw *hw = &adapter->hw;
ea943d41 1486 int err;
9d5c8243
AK		 1487
1488 /* flush_scheduled work may reschedule our watchdog task, so
1489 * explicitly disable watchdog tasks from being rescheduled */
1490 set_bit(__IGB_DOWN, &adapter->state);
1491 del_timer_sync(&adapter->watchdog_timer);
1492 del_timer_sync(&adapter->phy_info_timer);
1493
1494 flush_scheduled_work();
1495
421e02f0 1496#ifdef CONFIG_IGB_DCA
7dfc16fa 1497 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1498 dev_info(&pdev->dev, "DCA disabled\n");
1499 dca_remove_requester(&pdev->dev);
7dfc16fa 1500 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1501 wr32(E1000_DCA_CTRL, 1);
1502 }
1503#endif
1504
9d5c8243
AK		 1505 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1506 * would have already happened in close and is redundant. */
1507 igb_release_hw_control(adapter);
1508
1509 unregister_netdev(netdev);
1510
f5f4cf08
AD		 1511 if (!igb_check_reset_block(&adapter->hw))
1512 igb_reset_phy(&adapter->hw);
9d5c8243 1513
9d5c8243
AK		 1514 igb_reset_interrupt_capability(adapter);
1515
a88f10ec 1516 igb_free_queues(adapter);
9d5c8243 1517
28b0759c
AD		 1518 iounmap(hw->hw_addr);
1519 if (hw->flash_address)
1520 iounmap(hw->flash_address);
aed5dec3
AD		 1521 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1522 IORESOURCE_MEM));
9d5c8243
AK		 1523
1524 free_netdev(netdev);
1525
ea943d41
JK		 1526 err = pci_disable_pcie_error_reporting(pdev);
1527 if (err)
1528 dev_err(&pdev->dev,
1529 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1530
9d5c8243
AK		 1531 pci_disable_device(pdev);
1532}
1533
1534/**
1535 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1536 * @adapter: board private structure to initialize
1537 *
1538 * igb_sw_init initializes the Adapter private data structure.
1539 * Fields are initialized based on PCI device information and
1540 * OS network device settings (MTU size).
1541 **/
1542static int __devinit igb_sw_init(struct igb_adapter *adapter)
1543{
1544 struct e1000_hw *hw = &adapter->hw;
1545 struct net_device *netdev = adapter->netdev;
1546 struct pci_dev *pdev = adapter->pdev;
1547
1548 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1549
68fd9910
AD		 1550 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1551 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1552 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1553 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1554 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1555 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1556
661086df
PWJ		 1557 /* This call may decrease the number of queues depending on
1558 * interrupt mode. */
9d5c8243
AK		 1559 igb_set_interrupt_capability(adapter);
1560
1561 if (igb_alloc_queues(adapter)) {
1562 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1563 return -ENOMEM;
1564 }
1565
1566 /* Explicitly disable IRQ since the NIC can be in any state. */
1567 igb_irq_disable(adapter);
1568
1569 set_bit(__IGB_DOWN, &adapter->state);
1570 return 0;
1571}
1572
1573/**
1574 * igb_open - Called when a network interface is made active
1575 * @netdev: network interface device structure
1576 *
1577 * Returns 0 on success, negative value on failure
1578 *
1579 * The open entry point is called when a network interface is made
1580 * active by the system (IFF_UP). At this point all resources needed
1581 * for transmit and receive operations are allocated, the interrupt
1582 * handler is registered with the OS, the watchdog timer is started,
1583 * and the stack is notified that the interface is ready.
1584 **/
1585static int igb_open(struct net_device *netdev)
1586{
1587 struct igb_adapter *adapter = netdev_priv(netdev);
1588 struct e1000_hw *hw = &adapter->hw;
1589 int err;
1590 int i;
1591
1592 /* disallow open during test */
1593 if (test_bit(__IGB_TESTING, &adapter->state))
1594 return -EBUSY;
1595
1596 /* allocate transmit descriptors */
1597 err = igb_setup_all_tx_resources(adapter);
1598 if (err)
1599 goto err_setup_tx;
1600
1601 /* allocate receive descriptors */
1602 err = igb_setup_all_rx_resources(adapter);
1603 if (err)
1604 goto err_setup_rx;
1605
1606 /* e1000_power_up_phy(adapter); */
1607
1608 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1609 if ((adapter->hw.mng_cookie.status &
1610 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1611 igb_update_mng_vlan(adapter);
1612
1613 /* before we allocate an interrupt, we must be ready to handle it.
1614 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1615 * as soon as we call pci_request_irq, so we have to setup our
1616 * clean_rx handler before we do so. */
1617 igb_configure(adapter);
1618
1619 err = igb_request_irq(adapter);
1620 if (err)
1621 goto err_req_irq;
1622
1623 /* From here on the code is the same as igb_up() */
1624 clear_bit(__IGB_DOWN, &adapter->state);
1625
844290e5
PW		 1626 for (i = 0; i < adapter->num_rx_queues; i++)
1627 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1628
1629 /* Clear any pending interrupts. */
1630 rd32(E1000_ICR);
844290e5
PW		 1631
1632 igb_irq_enable(adapter);
1633
d55b53ff
JK		 1634 netif_tx_start_all_queues(netdev);
1635
9d5c8243
AK		 1636 /* Fire a link status change interrupt to start the watchdog. */
1637 wr32(E1000_ICS, E1000_ICS_LSC);
1638
1639 return 0;
1640
1641err_req_irq:
1642 igb_release_hw_control(adapter);
1643 /* e1000_power_down_phy(adapter); */
1644 igb_free_all_rx_resources(adapter);
1645err_setup_rx:
1646 igb_free_all_tx_resources(adapter);
1647err_setup_tx:
1648 igb_reset(adapter);
1649
1650 return err;
1651}
1652
1653/**
1654 * igb_close - Disables a network interface
1655 * @netdev: network interface device structure
1656 *
1657 * Returns 0, this is not allowed to fail
1658 *
1659 * The close entry point is called when an interface is de-activated
1660 * by the OS. The hardware is still under the driver's control, but
1661 * needs to be disabled. A global MAC reset is issued to stop the
1662 * hardware, and all transmit and receive resources are freed.
1663 **/
1664static int igb_close(struct net_device *netdev)
1665{
1666 struct igb_adapter *adapter = netdev_priv(netdev);
1667
1668 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1669 igb_down(adapter);
1670
1671 igb_free_irq(adapter);
1672
1673 igb_free_all_tx_resources(adapter);
1674 igb_free_all_rx_resources(adapter);
1675
1676 /* kill manageability vlan ID if supported, but not if a vlan with
1677 * the same ID is registered on the host OS (let 8021q kill it) */
1678 if ((adapter->hw.mng_cookie.status &
1679 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1680 !(adapter->vlgrp &&
1681 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1682 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1683
1684 return 0;
1685}
1686
1687/**
1688 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1689 * @adapter: board private structure
1690 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1691 *
1692 * Return 0 on success, negative on failure
1693 **/
9d5c8243
AK		 1694int igb_setup_tx_resources(struct igb_adapter *adapter,
1695 struct igb_ring *tx_ring)
1696{
1697 struct pci_dev *pdev = adapter->pdev;
1698 int size;
1699
1700 size = sizeof(struct igb_buffer) * tx_ring->count;
1701 tx_ring->buffer_info = vmalloc(size);
1702 if (!tx_ring->buffer_info)
1703 goto err;
1704 memset(tx_ring->buffer_info, 0, size);
1705
1706 /* round up to nearest 4K */
0e014cb1 1707 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1708 tx_ring->size = ALIGN(tx_ring->size, 4096);
1709
1710 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1711 &tx_ring->dma);
1712
1713 if (!tx_ring->desc)
1714 goto err;
1715
1716 tx_ring->adapter = adapter;
1717 tx_ring->next_to_use = 0;
1718 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1719 return 0;
1720
1721err:
1722 vfree(tx_ring->buffer_info);
1723 dev_err(&adapter->pdev->dev,
1724 "Unable to allocate memory for the transmit descriptor ring\n");
1725 return -ENOMEM;
1726}
1727
1728/**
1729 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1730 * (Descriptors) for all queues
1731 * @adapter: board private structure
1732 *
1733 * Return 0 on success, negative on failure
1734 **/
1735static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1736{
1737 int i, err = 0;
661086df 1738 int r_idx;
9d5c8243
AK		 1739
1740 for (i = 0; i < adapter->num_tx_queues; i++) {
1741 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1742 if (err) {
1743 dev_err(&adapter->pdev->dev,
1744 "Allocation for Tx Queue %u failed\n", i);
1745 for (i--; i >= 0; i--)
3b644cf6 1746 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1747 break;
1748 }
1749 }
1750
661086df
PWJ		 1751 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1752 r_idx = i % adapter->num_tx_queues;
1753 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1754 }
9d5c8243
AK		 1755 return err;
1756}
1757
1758/**
1759 * igb_configure_tx - Configure transmit Unit after Reset
1760 * @adapter: board private structure
1761 *
1762 * Configure the Tx unit of the MAC after a reset.
1763 **/
1764static void igb_configure_tx(struct igb_adapter *adapter)
1765{
0e014cb1 1766 u64 tdba;
9d5c8243
AK		 1767 struct e1000_hw *hw = &adapter->hw;
1768 u32 tctl;
1769 u32 txdctl, txctrl;
26bc19ec 1770 int i, j;
9d5c8243
AK		 1771
1772 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1773 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1774 j = ring->reg_idx;
1775 wr32(E1000_TDLEN(j),
73cd78f1 1776 ring->count * sizeof(struct e1000_tx_desc));
9d5c8243 1777 tdba = ring->dma;
26bc19ec 1778 wr32(E1000_TDBAL(j),
73cd78f1 1779 tdba & 0x00000000ffffffffULL);
26bc19ec 1780 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1781
26bc19ec
AD		 1782 ring->head = E1000_TDH(j);
1783 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1784 writel(0, hw->hw_addr + ring->tail);
1785 writel(0, hw->hw_addr + ring->head);
26bc19ec 1786 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1787 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1788 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1789
1790 /* Turn off Relaxed Ordering on head write-backs. The
1791 * writebacks MUST be delivered in order or it will
1792 * completely screw up our bookeeping.
1793 */
26bc19ec 1794 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1795 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1796 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1797 }
1798
9d5c8243
AK		 1799 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1800
1801 /* Program the Transmit Control Register */
1802
1803 tctl = rd32(E1000_TCTL);
1804 tctl &= ~E1000_TCTL_CT;
1805 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1806 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1807
1808 igb_config_collision_dist(hw);
1809
1810 /* Setup Transmit Descriptor Settings for eop descriptor */
1811 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1812
1813 /* Enable transmits */
1814 tctl |= E1000_TCTL_EN;
1815
1816 wr32(E1000_TCTL, tctl);
1817}
1818
1819/**
1820 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1821 * @adapter: board private structure
1822 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1823 *
1824 * Returns 0 on success, negative on failure
1825 **/
9d5c8243
AK		 1826int igb_setup_rx_resources(struct igb_adapter *adapter,
1827 struct igb_ring *rx_ring)
1828{
1829 struct pci_dev *pdev = adapter->pdev;
1830 int size, desc_len;
1831
1832 size = sizeof(struct igb_buffer) * rx_ring->count;
1833 rx_ring->buffer_info = vmalloc(size);
1834 if (!rx_ring->buffer_info)
1835 goto err;
1836 memset(rx_ring->buffer_info, 0, size);
1837
1838 desc_len = sizeof(union e1000_adv_rx_desc);
1839
1840 /* Round up to nearest 4K */
1841 rx_ring->size = rx_ring->count * desc_len;
1842 rx_ring->size = ALIGN(rx_ring->size, 4096);
1843
1844 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1845 &rx_ring->dma);
1846
1847 if (!rx_ring->desc)
1848 goto err;
1849
1850 rx_ring->next_to_clean = 0;
1851 rx_ring->next_to_use = 0;
9d5c8243
AK		 1852
1853 rx_ring->adapter = adapter;
9d5c8243
AK		 1854
1855 return 0;
1856
1857err:
1858 vfree(rx_ring->buffer_info);
1859 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1860 "the receive descriptor ring\n");
1861 return -ENOMEM;
1862}
1863
1864/**
1865 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1866 * (Descriptors) for all queues
1867 * @adapter: board private structure
1868 *
1869 * Return 0 on success, negative on failure
1870 **/
1871static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1872{
1873 int i, err = 0;
1874
1875 for (i = 0; i < adapter->num_rx_queues; i++) {
1876 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1877 if (err) {
1878 dev_err(&adapter->pdev->dev,
1879 "Allocation for Rx Queue %u failed\n", i);
1880 for (i--; i >= 0; i--)
3b644cf6 1881 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1882 break;
1883 }
1884 }
1885
1886 return err;
1887}
1888
1889/**
1890 * igb_setup_rctl - configure the receive control registers
1891 * @adapter: Board private structure
1892 **/
1893static void igb_setup_rctl(struct igb_adapter *adapter)
1894{
1895 struct e1000_hw *hw = &adapter->hw;
1896 u32 rctl;
1897 u32 srrctl = 0;
26bc19ec 1898 int i, j;
9d5c8243
AK		 1899
1900 rctl = rd32(E1000_RCTL);
1901
1902 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1903 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1904
69d728ba 1905 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1906 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1907
87cb7e8c
AK		 1908 /*
1909 * enable stripping of CRC. It's unlikely this will break BMC
1910 * redirection as it did with e1000. Newer features require
1911 * that the HW strips the CRC.
73cd78f1 1912 */
87cb7e8c 1913 rctl |= E1000_RCTL_SECRC;
9d5c8243 1914
9b07f3d3 1915 /*
ec54d7d6 1916 * disable store bad packets and clear size bits.
9b07f3d3 1917 */
ec54d7d6 1918 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1919
ec54d7d6 1920 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1921 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1922
1923 /* Setup buffer sizes */
1924 switch (adapter->rx_buffer_len) {
1925 case IGB_RXBUFFER_256:
1926 rctl |= E1000_RCTL_SZ_256;
1927 break;
1928 case IGB_RXBUFFER_512:
1929 rctl |= E1000_RCTL_SZ_512;
1930 break;
1931 default:
1932 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1933 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1934 break;
9d5c8243
AK		 1935 }
1936
1937 /* 82575 and greater support packet-split where the protocol
1938 * header is placed in skb->data and the packet data is
1939 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1940 * In the case of a non-split, skb->data is linearly filled,
1941 * followed by the page buffers. Therefore, skb->data is
1942 * sized to hold the largest protocol header.
1943 */
1944 /* allocations using alloc_page take too long for regular MTU
1945 * so only enable packet split for jumbo frames */
ec54d7d6 1946 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1947 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1948 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1949 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1950 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1951 } else {
1952 adapter->rx_ps_hdr_size = 0;
1953 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1954 }
1955
26bc19ec
AD		 1956 for (i = 0; i < adapter->num_rx_queues; i++) {
1957 j = adapter->rx_ring[i].reg_idx;
1958 wr32(E1000_SRRCTL(j), srrctl);
1959 }
9d5c8243
AK		 1960
1961 wr32(E1000_RCTL, rctl);
1962}
1963
1964/**
1965 * igb_configure_rx - Configure receive Unit after Reset
1966 * @adapter: board private structure
1967 *
1968 * Configure the Rx unit of the MAC after a reset.
1969 **/
1970static void igb_configure_rx(struct igb_adapter *adapter)
1971{
1972 u64 rdba;
1973 struct e1000_hw *hw = &adapter->hw;
1974 u32 rctl, rxcsum;
1975 u32 rxdctl;
26bc19ec 1976 int i, j;
9d5c8243
AK		 1977
1978 /* disable receives while setting up the descriptors */
1979 rctl = rd32(E1000_RCTL);
1980 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1981 wrfl();
1982 mdelay(10);
1983
1984 if (adapter->itr_setting > 3)
6eb5a7f1 1985 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1986
1987 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1988 * the Base and Length of the Rx Descriptor Ring */
1989 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 1990 struct igb_ring *ring = &adapter->rx_ring[i];
26bc19ec 1991 j = ring->reg_idx;
9d5c8243 1992 rdba = ring->dma;
26bc19ec 1993 wr32(E1000_RDBAL(j),
73cd78f1 1994 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1995 wr32(E1000_RDBAH(j), rdba >> 32);
1996 wr32(E1000_RDLEN(j),
73cd78f1 1997 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 1998
26bc19ec
AD		 1999 ring->head = E1000_RDH(j);
2000 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2001 writel(0, hw->hw_addr + ring->tail);
2002 writel(0, hw->hw_addr + ring->head);
2003
26bc19ec 2004 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2005 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2006 rxdctl &= 0xFFF00000;
2007 rxdctl |= IGB_RX_PTHRESH;
2008 rxdctl |= IGB_RX_HTHRESH << 8;
2009 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2010 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2011 }
2012
2013 if (adapter->num_rx_queues > 1) {
2014 u32 random[10];
2015 u32 mrqc;
2016 u32 j, shift;
2017 union e1000_reta {
2018 u32 dword;
2019 u8 bytes[4];
2020 } reta;
2021
2022 get_random_bytes(&random[0], 40);
2023
2d064c06
AD		 2024 if (hw->mac.type >= e1000_82576)
2025 shift = 0;
2026 else
2027 shift = 6;
9d5c8243
AK		 2028 for (j = 0; j < (32 * 4); j++) {
2029 reta.bytes[j & 3] =
26bc19ec 2030 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2031 if ((j & 3) == 3)
2032 writel(reta.dword,
2033 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2034 }
2035 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2036
2037 /* Fill out hash function seeds */
2038 for (j = 0; j < 10; j++)
2039 array_wr32(E1000_RSSRK(0), j, random[j]);
2040
2041 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2042 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2043 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2044 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2045 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2046 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2047 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2048 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2049
2050
2051 wr32(E1000_MRQC, mrqc);
2052
2053 /* Multiqueue and raw packet checksumming are mutually
2054 * exclusive. Note that this not the same as TCP/IP
2055 * checksumming, which works fine. */
2056 rxcsum = rd32(E1000_RXCSUM);
2057 rxcsum |= E1000_RXCSUM_PCSD;
2058 wr32(E1000_RXCSUM, rxcsum);
2059 } else {
2060 /* Enable Receive Checksum Offload for TCP and UDP */
2061 rxcsum = rd32(E1000_RXCSUM);
2062 if (adapter->rx_csum) {
2063 rxcsum |= E1000_RXCSUM_TUOFL;
2064
2065 /* Enable IPv4 payload checksum for UDP fragments
2066 * Must be used in conjunction with packet-split. */
2067 if (adapter->rx_ps_hdr_size)
2068 rxcsum |= E1000_RXCSUM_IPPCSE;
2069 } else {
2070 rxcsum &= ~E1000_RXCSUM_TUOFL;
2071 /* don't need to clear IPPCSE as it defaults to 0 */
2072 }
2073 wr32(E1000_RXCSUM, rxcsum);
2074 }
2075
2076 if (adapter->vlgrp)
2077 wr32(E1000_RLPML,
2078 adapter->max_frame_size + VLAN_TAG_SIZE);
2079 else
2080 wr32(E1000_RLPML, adapter->max_frame_size);
2081
2082 /* Enable Receives */
2083 wr32(E1000_RCTL, rctl);
2084}
2085
2086/**
2087 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2088 * @tx_ring: Tx descriptor ring for a specific queue
2089 *
2090 * Free all transmit software resources
2091 **/
68fd9910 2092void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2093{
3b644cf6 2094 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2095
3b644cf6 2096 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2097
2098 vfree(tx_ring->buffer_info);
2099 tx_ring->buffer_info = NULL;
2100
2101 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2102
2103 tx_ring->desc = NULL;
2104}
2105
2106/**
2107 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2108 * @adapter: board private structure
2109 *
2110 * Free all transmit software resources
2111 **/
2112static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2113{
2114 int i;
2115
2116 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2117 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2118}
2119
2120static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2121 struct igb_buffer *buffer_info)
2122{
2123 if (buffer_info->dma) {
2124 pci_unmap_page(adapter->pdev,
2125 buffer_info->dma,
2126 buffer_info->length,
2127 PCI_DMA_TODEVICE);
2128 buffer_info->dma = 0;
2129 }
2130 if (buffer_info->skb) {
2131 dev_kfree_skb_any(buffer_info->skb);
2132 buffer_info->skb = NULL;
2133 }
2134 buffer_info->time_stamp = 0;
73cd78f1 2135 buffer_info->next_to_watch = 0;
9d5c8243
AK		 2136 /* buffer_info must be completely set up in the transmit path */
2137}
2138
2139/**
2140 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2141 * @tx_ring: ring to be cleaned
2142 **/
3b644cf6 2143static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2144{
3b644cf6 2145 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2146 struct igb_buffer *buffer_info;
2147 unsigned long size;
2148 unsigned int i;
2149
2150 if (!tx_ring->buffer_info)
2151 return;
2152 /* Free all the Tx ring sk_buffs */
2153
2154 for (i = 0; i < tx_ring->count; i++) {
2155 buffer_info = &tx_ring->buffer_info[i];
2156 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2157 }
2158
2159 size = sizeof(struct igb_buffer) * tx_ring->count;
2160 memset(tx_ring->buffer_info, 0, size);
2161
2162 /* Zero out the descriptor ring */
2163
2164 memset(tx_ring->desc, 0, tx_ring->size);
2165
2166 tx_ring->next_to_use = 0;
2167 tx_ring->next_to_clean = 0;
2168
2169 writel(0, adapter->hw.hw_addr + tx_ring->head);
2170 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2171}
2172
2173/**
2174 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2175 * @adapter: board private structure
2176 **/
2177static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2178{
2179 int i;
2180
2181 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2182 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2183}
2184
2185/**
2186 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2187 * @rx_ring: ring to clean the resources from
2188 *
2189 * Free all receive software resources
2190 **/
68fd9910 2191void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2192{
3b644cf6 2193 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2194
3b644cf6 2195 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2196
2197 vfree(rx_ring->buffer_info);
2198 rx_ring->buffer_info = NULL;
2199
2200 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2201
2202 rx_ring->desc = NULL;
2203}
2204
2205/**
2206 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2207 * @adapter: board private structure
2208 *
2209 * Free all receive software resources
2210 **/
2211static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2212{
2213 int i;
2214
2215 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2216 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2217}
2218
2219/**
2220 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2221 * @rx_ring: ring to free buffers from
2222 **/
3b644cf6 2223static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2224{
3b644cf6 2225 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2226 struct igb_buffer *buffer_info;
2227 struct pci_dev *pdev = adapter->pdev;
2228 unsigned long size;
2229 unsigned int i;
2230
2231 if (!rx_ring->buffer_info)
2232 return;
2233 /* Free all the Rx ring sk_buffs */
2234 for (i = 0; i < rx_ring->count; i++) {
2235 buffer_info = &rx_ring->buffer_info[i];
2236 if (buffer_info->dma) {
2237 if (adapter->rx_ps_hdr_size)
2238 pci_unmap_single(pdev, buffer_info->dma,
2239 adapter->rx_ps_hdr_size,
2240 PCI_DMA_FROMDEVICE);
2241 else
2242 pci_unmap_single(pdev, buffer_info->dma,
2243 adapter->rx_buffer_len,
2244 PCI_DMA_FROMDEVICE);
2245 buffer_info->dma = 0;
2246 }
2247
2248 if (buffer_info->skb) {
2249 dev_kfree_skb(buffer_info->skb);
2250 buffer_info->skb = NULL;
2251 }
2252 if (buffer_info->page) {
bf36c1a0
AD		 2253 if (buffer_info->page_dma)
2254 pci_unmap_page(pdev, buffer_info->page_dma,
2255 PAGE_SIZE / 2,
2256 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2257 put_page(buffer_info->page);
2258 buffer_info->page = NULL;
2259 buffer_info->page_dma = 0;
bf36c1a0 2260 buffer_info->page_offset = 0;
9d5c8243
AK		 2261 }
2262 }
2263
9d5c8243
AK		 2264 size = sizeof(struct igb_buffer) * rx_ring->count;
2265 memset(rx_ring->buffer_info, 0, size);
2266
2267 /* Zero out the descriptor ring */
2268 memset(rx_ring->desc, 0, rx_ring->size);
2269
2270 rx_ring->next_to_clean = 0;
2271 rx_ring->next_to_use = 0;
2272
2273 writel(0, adapter->hw.hw_addr + rx_ring->head);
2274 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2275}
2276
2277/**
2278 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2279 * @adapter: board private structure
2280 **/
2281static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2282{
2283 int i;
2284
2285 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2286 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2287}
2288
2289/**
2290 * igb_set_mac - Change the Ethernet Address of the NIC
2291 * @netdev: network interface device structure
2292 * @p: pointer to an address structure
2293 *
2294 * Returns 0 on success, negative on failure
2295 **/
2296static int igb_set_mac(struct net_device *netdev, void *p)
2297{
2298 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2299 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2300 struct sockaddr *addr = p;
2301
2302 if (!is_valid_ether_addr(addr->sa_data))
2303 return -EADDRNOTAVAIL;
2304
2305 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2306 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2307
28b0759c 2308 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243
AK		 2309
2310 return 0;
2311}
2312
2313/**
2314 * igb_set_multi - Multicast and Promiscuous mode set
2315 * @netdev: network interface device structure
2316 *
2317 * The set_multi entry point is called whenever the multicast address
2318 * list or the network interface flags are updated. This routine is
2319 * responsible for configuring the hardware for proper multicast,
2320 * promiscuous mode, and all-multi behavior.
2321 **/
2322static void igb_set_multi(struct net_device *netdev)
2323{
2324 struct igb_adapter *adapter = netdev_priv(netdev);
2325 struct e1000_hw *hw = &adapter->hw;
2326 struct e1000_mac_info *mac = &hw->mac;
2327 struct dev_mc_list *mc_ptr;
2328 u8 *mta_list;
2329 u32 rctl;
2330 int i;
2331
2332 /* Check for Promiscuous and All Multicast modes */
2333
2334 rctl = rd32(E1000_RCTL);
2335
746b9f02 2336 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2337 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2338 rctl &= ~E1000_RCTL_VFE;
2339 } else {
2340 if (netdev->flags & IFF_ALLMULTI) {
2341 rctl |= E1000_RCTL_MPE;
2342 rctl &= ~E1000_RCTL_UPE;
2343 } else
2344 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2345 rctl |= E1000_RCTL_VFE;
746b9f02 2346 }
9d5c8243
AK		 2347 wr32(E1000_RCTL, rctl);
2348
2349 if (!netdev->mc_count) {
2350 /* nothing to program, so clear mc list */
8a900862
AD		 2351 igb_update_mc_addr_list(hw, NULL, 0, 1,
2352 mac->rar_entry_count);
9d5c8243
AK		 2353 return;
2354 }
2355
2356 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2357 if (!mta_list)
2358 return;
2359
2360 /* The shared function expects a packed array of only addresses. */
2361 mc_ptr = netdev->mc_list;
2362
2363 for (i = 0; i < netdev->mc_count; i++) {
2364 if (!mc_ptr)
2365 break;
2366 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2367 mc_ptr = mc_ptr->next;
2368 }
8a900862 2369 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2370 kfree(mta_list);
2371}
2372
2373/* Need to wait a few seconds after link up to get diagnostic information from
2374 * the phy */
2375static void igb_update_phy_info(unsigned long data)
2376{
2377 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2378 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2379}
2380
4d6b725e
AD		 2381/**
2382 * igb_has_link - check shared code for link and determine up/down
2383 * @adapter: pointer to driver private info
2384 **/
2385static bool igb_has_link(struct igb_adapter *adapter)
2386{
2387 struct e1000_hw *hw = &adapter->hw;
2388 bool link_active = false;
2389 s32 ret_val = 0;
2390
2391 /* get_link_status is set on LSC (link status) interrupt or
2392 * rx sequence error interrupt. get_link_status will stay
2393 * false until the e1000_check_for_link establishes link
2394 * for copper adapters ONLY
2395 */
2396 switch (hw->phy.media_type) {
2397 case e1000_media_type_copper:
2398 if (hw->mac.get_link_status) {
2399 ret_val = hw->mac.ops.check_for_link(hw);
2400 link_active = !hw->mac.get_link_status;
2401 } else {
2402 link_active = true;
2403 }
2404 break;
2405 case e1000_media_type_fiber:
2406 ret_val = hw->mac.ops.check_for_link(hw);
2407 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2408 break;
2409 case e1000_media_type_internal_serdes:
2410 ret_val = hw->mac.ops.check_for_link(hw);
2411 link_active = hw->mac.serdes_has_link;
2412 break;
2413 default:
2414 case e1000_media_type_unknown:
2415 break;
2416 }
2417
2418 return link_active;
2419}
2420
9d5c8243
AK		 2421/**
2422 * igb_watchdog - Timer Call-back
2423 * @data: pointer to adapter cast into an unsigned long
2424 **/
2425static void igb_watchdog(unsigned long data)
2426{
2427 struct igb_adapter *adapter = (struct igb_adapter *)data;
2428 /* Do the rest outside of interrupt context */
2429 schedule_work(&adapter->watchdog_task);
2430}
2431
2432static void igb_watchdog_task(struct work_struct *work)
2433{
2434 struct igb_adapter *adapter = container_of(work,
2435 struct igb_adapter, watchdog_task);
2436 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2437 struct net_device *netdev = adapter->netdev;
2438 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2439 u32 link;
7a6ea550 2440 u32 eics = 0;
7a6ea550 2441 int i;
9d5c8243 2442
4d6b725e
AD		 2443 link = igb_has_link(adapter);
2444 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2445 goto link_up;
2446
9d5c8243
AK		 2447 if (link) {
2448 if (!netif_carrier_ok(netdev)) {
2449 u32 ctrl;
2450 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2451 &adapter->link_speed,
2452 &adapter->link_duplex);
2453
2454 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2455 /* Links status message must follow this format */
2456 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2457 "Flow Control: %s\n",
527d47c1 2458 netdev->name,
9d5c8243
AK		 2459 adapter->link_speed,
2460 adapter->link_duplex == FULL_DUPLEX ?
2461 "Full Duplex" : "Half Duplex",
2462 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2463 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2464 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2465 E1000_CTRL_TFCE) ? "TX" : "None")));
2466
2467 /* tweak tx_queue_len according to speed/duplex and
2468 * adjust the timeout factor */
2469 netdev->tx_queue_len = adapter->tx_queue_len;
2470 adapter->tx_timeout_factor = 1;
2471 switch (adapter->link_speed) {
2472 case SPEED_10:
2473 netdev->tx_queue_len = 10;
2474 adapter->tx_timeout_factor = 14;
2475 break;
2476 case SPEED_100:
2477 netdev->tx_queue_len = 100;
2478 /* maybe add some timeout factor ? */
2479 break;
2480 }
2481
2482 netif_carrier_on(netdev);
fd2ea0a7 2483 netif_tx_wake_all_queues(netdev);
9d5c8243 2484
4b1a9877 2485 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2486 if (!test_bit(__IGB_DOWN, &adapter->state))
2487 mod_timer(&adapter->phy_info_timer,
2488 round_jiffies(jiffies + 2 * HZ));
2489 }
2490 } else {
2491 if (netif_carrier_ok(netdev)) {
2492 adapter->link_speed = 0;
2493 adapter->link_duplex = 0;
527d47c1
AD		 2494 /* Links status message must follow this format */
2495 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2496 netdev->name);
9d5c8243 2497 netif_carrier_off(netdev);
fd2ea0a7 2498 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2499
2500 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2501 if (!test_bit(__IGB_DOWN, &adapter->state))
2502 mod_timer(&adapter->phy_info_timer,
2503 round_jiffies(jiffies + 2 * HZ));
2504 }
2505 }
2506
2507link_up:
2508 igb_update_stats(adapter);
2509
4b1a9877 2510 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2511 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2512 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2513 adapter->colc_old = adapter->stats.colc;
2514
2515 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2516 adapter->gorc_old = adapter->stats.gorc;
2517 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2518 adapter->gotc_old = adapter->stats.gotc;
2519
2520 igb_update_adaptive(&adapter->hw);
2521
2522 if (!netif_carrier_ok(netdev)) {
2523 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2524 /* We've lost link, so the controller stops DMA,
2525 * but we've got queued Tx work that's never going
2526 * to get done, so reset controller to flush Tx.
2527 * (Do the reset outside of interrupt context). */
2528 adapter->tx_timeout_count++;
2529 schedule_work(&adapter->reset_task);
2530 }
2531 }
2532
2533 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2534 if (adapter->msix_entries) {
2535 for (i = 0; i < adapter->num_rx_queues; i++)
2536 eics |= adapter->rx_ring[i].eims_value;
2537 wr32(E1000_EICS, eics);
2538 } else {
2539 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2540 }
9d5c8243
AK		 2541
2542 /* Force detection of hung controller every watchdog period */
2543 tx_ring->detect_tx_hung = true;
2544
2545 /* Reset the timer */
2546 if (!test_bit(__IGB_DOWN, &adapter->state))
2547 mod_timer(&adapter->watchdog_timer,
2548 round_jiffies(jiffies + 2 * HZ));
2549}
2550
2551enum latency_range {
2552 lowest_latency = 0,
2553 low_latency = 1,
2554 bulk_latency = 2,
2555 latency_invalid = 255
2556};
2557
2558
6eb5a7f1
AD		 2559/**
2560 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2561 *
2562 * Stores a new ITR value based on strictly on packet size. This
2563 * algorithm is less sophisticated than that used in igb_update_itr,
2564 * due to the difficulty of synchronizing statistics across multiple
2565 * receive rings. The divisors and thresholds used by this fuction
2566 * were determined based on theoretical maximum wire speed and testing
2567 * data, in order to minimize response time while increasing bulk
2568 * throughput.
2569 * This functionality is controlled by the InterruptThrottleRate module
2570 * parameter (see igb_param.c)
2571 * NOTE: This function is called only when operating in a multiqueue
2572 * receive environment.
2573 * @rx_ring: pointer to ring
2574 **/
2575static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2576{
6eb5a7f1
AD		 2577 int new_val = rx_ring->itr_val;
2578 int avg_wire_size = 0;
2579 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2580
6eb5a7f1
AD		 2581 if (!rx_ring->total_packets)
2582 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2583
6eb5a7f1
AD		 2584 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2585 * ints/sec - ITR timer value of 120 ticks.
2586 */
2587 if (adapter->link_speed != SPEED_1000) {
2588 new_val = 120;
2589 goto set_itr_val;
9d5c8243 2590 }
6eb5a7f1 2591 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2592
6eb5a7f1
AD		 2593 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2594 avg_wire_size += 24;
2595
2596 /* Don't starve jumbo frames */
2597 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2598
6eb5a7f1
AD		 2599 /* Give a little boost to mid-size frames */
2600 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2601 new_val = avg_wire_size / 3;
2602 else
2603 new_val = avg_wire_size / 2;
9d5c8243 2604
6eb5a7f1 2605set_itr_val:
9d5c8243
AK		 2606 if (new_val != rx_ring->itr_val) {
2607 rx_ring->itr_val = new_val;
6eb5a7f1 2608 rx_ring->set_itr = 1;
9d5c8243 2609 }
6eb5a7f1
AD		 2610clear_counts:
2611 rx_ring->total_bytes = 0;
2612 rx_ring->total_packets = 0;
9d5c8243
AK		 2613}
2614
2615/**
2616 * igb_update_itr - update the dynamic ITR value based on statistics
2617 * Stores a new ITR value based on packets and byte
2618 * counts during the last interrupt. The advantage of per interrupt
2619 * computation is faster updates and more accurate ITR for the current
2620 * traffic pattern. Constants in this function were computed
2621 * based on theoretical maximum wire speed and thresholds were set based
2622 * on testing data as well as attempting to minimize response time
2623 * while increasing bulk throughput.
2624 * this functionality is controlled by the InterruptThrottleRate module
2625 * parameter (see igb_param.c)
2626 * NOTE: These calculations are only valid when operating in a single-
2627 * queue environment.
2628 * @adapter: pointer to adapter
2629 * @itr_setting: current adapter->itr
2630 * @packets: the number of packets during this measurement interval
2631 * @bytes: the number of bytes during this measurement interval
2632 **/
2633static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2634 int packets, int bytes)
2635{
2636 unsigned int retval = itr_setting;
2637
2638 if (packets == 0)
2639 goto update_itr_done;
2640
2641 switch (itr_setting) {
2642 case lowest_latency:
2643 /* handle TSO and jumbo frames */
2644 if (bytes/packets > 8000)
2645 retval = bulk_latency;
2646 else if ((packets < 5) && (bytes > 512))
2647 retval = low_latency;
2648 break;
2649 case low_latency: /* 50 usec aka 20000 ints/s */
2650 if (bytes > 10000) {
2651 /* this if handles the TSO accounting */
2652 if (bytes/packets > 8000) {
2653 retval = bulk_latency;
2654 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2655 retval = bulk_latency;
2656 } else if ((packets > 35)) {
2657 retval = lowest_latency;
2658 }
2659 } else if (bytes/packets > 2000) {
2660 retval = bulk_latency;
2661 } else if (packets <= 2 && bytes < 512) {
2662 retval = lowest_latency;
2663 }
2664 break;
2665 case bulk_latency: /* 250 usec aka 4000 ints/s */
2666 if (bytes > 25000) {
2667 if (packets > 35)
2668 retval = low_latency;
2669 } else if (bytes < 6000) {
2670 retval = low_latency;
2671 }
2672 break;
2673 }
2674
2675update_itr_done:
2676 return retval;
2677}
2678
6eb5a7f1 2679static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2680{
2681 u16 current_itr;
2682 u32 new_itr = adapter->itr;
2683
2684 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2685 if (adapter->link_speed != SPEED_1000) {
2686 current_itr = 0;
2687 new_itr = 4000;
2688 goto set_itr_now;
2689 }
2690
2691 adapter->rx_itr = igb_update_itr(adapter,
2692 adapter->rx_itr,
2693 adapter->rx_ring->total_packets,
2694 adapter->rx_ring->total_bytes);
9d5c8243 2695
6eb5a7f1 2696 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2697 adapter->tx_itr = igb_update_itr(adapter,
2698 adapter->tx_itr,
2699 adapter->tx_ring->total_packets,
2700 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2701 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2702 } else {
2703 current_itr = adapter->rx_itr;
2704 }
2705
6eb5a7f1 2706 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2707 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2708 current_itr = low_latency;
2709
9d5c8243
AK		 2710 switch (current_itr) {
2711 /* counts and packets in update_itr are dependent on these numbers */
2712 case lowest_latency:
2713 new_itr = 70000;
2714 break;
2715 case low_latency:
2716 new_itr = 20000; /* aka hwitr = ~200 */
2717 break;
2718 case bulk_latency:
2719 new_itr = 4000;
2720 break;
2721 default:
2722 break;
2723 }
2724
2725set_itr_now:
6eb5a7f1
AD		 2726 adapter->rx_ring->total_bytes = 0;
2727 adapter->rx_ring->total_packets = 0;
2728 if (adapter->rx_ring->buddy) {
2729 adapter->rx_ring->buddy->total_bytes = 0;
2730 adapter->rx_ring->buddy->total_packets = 0;
2731 }
2732
9d5c8243
AK		 2733 if (new_itr != adapter->itr) {
2734 /* this attempts to bias the interrupt rate towards Bulk
2735 * by adding intermediate steps when interrupt rate is
2736 * increasing */
2737 new_itr = new_itr > adapter->itr ?
2738 min(adapter->itr + (new_itr >> 2), new_itr) :
2739 new_itr;
2740 /* Don't write the value here; it resets the adapter's
2741 * internal timer, and causes us to delay far longer than
2742 * we should between interrupts. Instead, we write the ITR
2743 * value at the beginning of the next interrupt so the timing
2744 * ends up being correct.
2745 */
2746 adapter->itr = new_itr;
6eb5a7f1
AD		 2747 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2748 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2749 }
2750
2751 return;
2752}
2753
2754
2755#define IGB_TX_FLAGS_CSUM 0x00000001
2756#define IGB_TX_FLAGS_VLAN 0x00000002
2757#define IGB_TX_FLAGS_TSO 0x00000004
2758#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2759#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2760#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2761#define IGB_TX_FLAGS_VLAN_SHIFT 16
2762
2763static inline int igb_tso_adv(struct igb_adapter *adapter,
2764 struct igb_ring *tx_ring,
2765 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2766{
2767 struct e1000_adv_tx_context_desc *context_desc;
2768 unsigned int i;
2769 int err;
2770 struct igb_buffer *buffer_info;
2771 u32 info = 0, tu_cmd = 0;
2772 u32 mss_l4len_idx, l4len;
2773 *hdr_len = 0;
2774
2775 if (skb_header_cloned(skb)) {
2776 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2777 if (err)
2778 return err;
2779 }
2780
2781 l4len = tcp_hdrlen(skb);
2782 *hdr_len += l4len;
2783
2784 if (skb->protocol == htons(ETH_P_IP)) {
2785 struct iphdr *iph = ip_hdr(skb);
2786 iph->tot_len = 0;
2787 iph->check = 0;
2788 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2789 iph->daddr, 0,
2790 IPPROTO_TCP,
2791 0);
2792 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2793 ipv6_hdr(skb)->payload_len = 0;
2794 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2795 &ipv6_hdr(skb)->daddr,
2796 0, IPPROTO_TCP, 0);
2797 }
2798
2799 i = tx_ring->next_to_use;
2800
2801 buffer_info = &tx_ring->buffer_info[i];
2802 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2803 /* VLAN MACLEN IPLEN */
2804 if (tx_flags & IGB_TX_FLAGS_VLAN)
2805 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2806 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2807 *hdr_len += skb_network_offset(skb);
2808 info |= skb_network_header_len(skb);
2809 *hdr_len += skb_network_header_len(skb);
2810 context_desc->vlan_macip_lens = cpu_to_le32(info);
2811
2812 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2813 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2814
2815 if (skb->protocol == htons(ETH_P_IP))
2816 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2817 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2818
2819 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2820
2821 /* MSS L4LEN IDX */
2822 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2823 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2824
73cd78f1 2825 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 2826 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2827 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2828
2829 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2830 context_desc->seqnum_seed = 0;
2831
2832 buffer_info->time_stamp = jiffies;
0e014cb1 2833 buffer_info->next_to_watch = i;
9d5c8243
AK		 2834 buffer_info->dma = 0;
2835 i++;
2836 if (i == tx_ring->count)
2837 i = 0;
2838
2839 tx_ring->next_to_use = i;
2840
2841 return true;
2842}
2843
2844static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2845 struct igb_ring *tx_ring,
2846 struct sk_buff *skb, u32 tx_flags)
2847{
2848 struct e1000_adv_tx_context_desc *context_desc;
2849 unsigned int i;
2850 struct igb_buffer *buffer_info;
2851 u32 info = 0, tu_cmd = 0;
2852
2853 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2854 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2855 i = tx_ring->next_to_use;
2856 buffer_info = &tx_ring->buffer_info[i];
2857 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2858
2859 if (tx_flags & IGB_TX_FLAGS_VLAN)
2860 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2861 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2862 if (skb->ip_summed == CHECKSUM_PARTIAL)
2863 info |= skb_network_header_len(skb);
2864
2865 context_desc->vlan_macip_lens = cpu_to_le32(info);
2866
2867 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2868
2869 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2870 switch (skb->protocol) {
09640e63 2871 case cpu_to_be16(ETH_P_IP):
9d5c8243 2872 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2873 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2874 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2875 break;
09640e63 2876 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2877 /* XXX what about other V6 headers?? */
2878 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2879 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2880 break;
2881 default:
2882 if (unlikely(net_ratelimit()))
2883 dev_warn(&adapter->pdev->dev,
2884 "partial checksum but proto=%x!\n",
2885 skb->protocol);
2886 break;
2887 }
9d5c8243
AK		 2888 }
2889
2890 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2891 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2892 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2893 context_desc->mss_l4len_idx =
2894 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 2895 else
2896 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 2897
2898 buffer_info->time_stamp = jiffies;
0e014cb1 2899 buffer_info->next_to_watch = i;
9d5c8243
AK		 2900 buffer_info->dma = 0;
2901
2902 i++;
2903 if (i == tx_ring->count)
2904 i = 0;
2905 tx_ring->next_to_use = i;
2906
2907 return true;
2908 }
9d5c8243
AK		 2909 return false;
2910}
2911
2912#define IGB_MAX_TXD_PWR 16
2913#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2914
2915static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2916 struct igb_ring *tx_ring, struct sk_buff *skb,
2917 unsigned int first)
9d5c8243
AK		 2918{
2919 struct igb_buffer *buffer_info;
2920 unsigned int len = skb_headlen(skb);
2921 unsigned int count = 0, i;
2922 unsigned int f;
2923
2924 i = tx_ring->next_to_use;
2925
2926 buffer_info = &tx_ring->buffer_info[i];
2927 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2928 buffer_info->length = len;
2929 /* set time_stamp *before* dma to help avoid a possible race */
2930 buffer_info->time_stamp = jiffies;
0e014cb1 2931 buffer_info->next_to_watch = i;
9d5c8243
AK		 2932 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2933 PCI_DMA_TODEVICE);
2934 count++;
2935 i++;
2936 if (i == tx_ring->count)
2937 i = 0;
2938
2939 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2940 struct skb_frag_struct *frag;
2941
2942 frag = &skb_shinfo(skb)->frags[f];
2943 len = frag->size;
2944
2945 buffer_info = &tx_ring->buffer_info[i];
2946 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2947 buffer_info->length = len;
2948 buffer_info->time_stamp = jiffies;
0e014cb1 2949 buffer_info->next_to_watch = i;
9d5c8243
AK		 2950 buffer_info->dma = pci_map_page(adapter->pdev,
2951 frag->page,
2952 frag->page_offset,
2953 len,
2954 PCI_DMA_TODEVICE);
2955
2956 count++;
2957 i++;
2958 if (i == tx_ring->count)
2959 i = 0;
2960 }
2961
0e014cb1 2962 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2963 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2964 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2965
2966 return count;
2967}
2968
2969static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2970 struct igb_ring *tx_ring,
2971 int tx_flags, int count, u32 paylen,
2972 u8 hdr_len)
2973{
2974 union e1000_adv_tx_desc *tx_desc = NULL;
2975 struct igb_buffer *buffer_info;
2976 u32 olinfo_status = 0, cmd_type_len;
2977 unsigned int i;
2978
2979 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2980 E1000_ADVTXD_DCMD_DEXT);
2981
2982 if (tx_flags & IGB_TX_FLAGS_VLAN)
2983 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2984
33af6bcc
PO		 2985 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
2986 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
2987
9d5c8243
AK		 2988 if (tx_flags & IGB_TX_FLAGS_TSO) {
2989 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2990
2991 /* insert tcp checksum */
2992 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2993
2994 /* insert ip checksum */
2995 if (tx_flags & IGB_TX_FLAGS_IPV4)
2996 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2997
2998 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2999 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3000 }
3001
7dfc16fa
AD		 3002 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3003 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3004 IGB_TX_FLAGS_VLAN)))
661086df 3005 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3006
3007 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3008
3009 i = tx_ring->next_to_use;
3010 while (count--) {
3011 buffer_info = &tx_ring->buffer_info[i];
3012 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3013 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3014 tx_desc->read.cmd_type_len =
3015 cpu_to_le32(cmd_type_len | buffer_info->length);
3016 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3017 i++;
3018 if (i == tx_ring->count)
3019 i = 0;
3020 }
3021
3022 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3023 /* Force memory writes to complete before letting h/w
3024 * know there are new descriptors to fetch. (Only
3025 * applicable for weak-ordered memory model archs,
3026 * such as IA-64). */
3027 wmb();
3028
3029 tx_ring->next_to_use = i;
3030 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3031 /* we need this if more than one processor can write to our tail
3032 * at a time, it syncronizes IO on IA64/Altix systems */
3033 mmiowb();
3034}
3035
3036static int __igb_maybe_stop_tx(struct net_device *netdev,
3037 struct igb_ring *tx_ring, int size)
3038{
3039 struct igb_adapter *adapter = netdev_priv(netdev);
3040
661086df 3041 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3042
9d5c8243
AK		 3043 /* Herbert's original patch had:
3044 * smp_mb__after_netif_stop_queue();
3045 * but since that doesn't exist yet, just open code it. */
3046 smp_mb();
3047
3048 /* We need to check again in a case another CPU has just
3049 * made room available. */
3050 if (IGB_DESC_UNUSED(tx_ring) < size)
3051 return -EBUSY;
3052
3053 /* A reprieve! */
661086df 3054 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3055 ++adapter->restart_queue;
3056 return 0;
3057}
3058
3059static int igb_maybe_stop_tx(struct net_device *netdev,
3060 struct igb_ring *tx_ring, int size)
3061{
3062 if (IGB_DESC_UNUSED(tx_ring) >= size)
3063 return 0;
3064 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3065}
3066
3067#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
3068
3069static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3070 struct net_device *netdev,
3071 struct igb_ring *tx_ring)
3072{
3073 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3074 unsigned int first;
9d5c8243 3075 unsigned int tx_flags = 0;
9d5c8243
AK		 3076 u8 hdr_len = 0;
3077 int tso = 0;
33af6bcc 3078 union skb_shared_tx *shtx;
9d5c8243 3079
9d5c8243
AK		 3080 if (test_bit(__IGB_DOWN, &adapter->state)) {
3081 dev_kfree_skb_any(skb);
3082 return NETDEV_TX_OK;
3083 }
3084
3085 if (skb->len <= 0) {
3086 dev_kfree_skb_any(skb);
3087 return NETDEV_TX_OK;
3088 }
3089
9d5c8243
AK		 3090 /* need: 1 descriptor per page,
3091 * + 2 desc gap to keep tail from touching head,
3092 * + 1 desc for skb->data,
3093 * + 1 desc for context descriptor,
3094 * otherwise try next time */
3095 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3096 /* this is a hard error */
9d5c8243
AK		 3097 return NETDEV_TX_BUSY;
3098 }
33af6bcc
PO		 3099
3100 /*
3101 * TODO: check that there currently is no other packet with
3102 * time stamping in the queue
3103 *
3104 * When doing time stamping, keep the connection to the socket
3105 * a while longer: it is still needed by skb_hwtstamp_tx(),
3106 * called either in igb_tx_hwtstamp() or by our caller when
3107 * doing software time stamping.
3108 */
3109 shtx = skb_tx(skb);
3110 if (unlikely(shtx->hardware)) {
3111 shtx->in_progress = 1;
3112 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3113 } else if (likely(!shtx->software)) {
3114 /*
3115 * TODO: can this be solved in dev.c:dev_hard_start_xmit()?
3116 * There are probably unmodified driver which do something
3117 * like this and thus don't work in combination with
3118 * SOF_TIMESTAMPING_TX_SOFTWARE.
3119 */
3120 skb_orphan(skb);
3121 }
9d5c8243
AK		 3122
3123 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3124 tx_flags |= IGB_TX_FLAGS_VLAN;
3125 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3126 }
3127
661086df
PWJ		 3128 if (skb->protocol == htons(ETH_P_IP))
3129 tx_flags |= IGB_TX_FLAGS_IPV4;
3130
0e014cb1 3131 first = tx_ring->next_to_use;
9d5c8243
AK		 3132 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3133 &hdr_len) : 0;
3134
3135 if (tso < 0) {
3136 dev_kfree_skb_any(skb);
9d5c8243
AK		 3137 return NETDEV_TX_OK;
3138 }
3139
3140 if (tso)
3141 tx_flags |= IGB_TX_FLAGS_TSO;
3142 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3143 if (skb->ip_summed == CHECKSUM_PARTIAL)
3144 tx_flags |= IGB_TX_FLAGS_CSUM;
3145
9d5c8243 3146 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3147 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3148 skb->len, hdr_len);
3149
3150 netdev->trans_start = jiffies;
3151
3152 /* Make sure there is space in the ring for the next send. */
3153 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3154
9d5c8243
AK		 3155 return NETDEV_TX_OK;
3156}
3157
3158static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3159{
3160 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3161 struct igb_ring *tx_ring;
3162
661086df
PWJ		 3163 int r_idx = 0;
3164 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3165 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3166
3167 /* This goes back to the question of how to logically map a tx queue
3168 * to a flow. Right now, performance is impacted slightly negatively
3169 * if using multiple tx queues. If the stack breaks away from a
3170 * single qdisc implementation, we can look at this again. */
3171 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3172}
3173
3174/**
3175 * igb_tx_timeout - Respond to a Tx Hang
3176 * @netdev: network interface device structure
3177 **/
3178static void igb_tx_timeout(struct net_device *netdev)
3179{
3180 struct igb_adapter *adapter = netdev_priv(netdev);
3181 struct e1000_hw *hw = &adapter->hw;
3182
3183 /* Do the reset outside of interrupt context */
3184 adapter->tx_timeout_count++;
3185 schedule_work(&adapter->reset_task);
265de409
AD		 3186 wr32(E1000_EICS,
3187 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3188}
3189
3190static void igb_reset_task(struct work_struct *work)
3191{
3192 struct igb_adapter *adapter;
3193 adapter = container_of(work, struct igb_adapter, reset_task);
3194
3195 igb_reinit_locked(adapter);
3196}
3197
3198/**
3199 * igb_get_stats - Get System Network Statistics
3200 * @netdev: network interface device structure
3201 *
3202 * Returns the address of the device statistics structure.
3203 * The statistics are actually updated from the timer callback.
3204 **/
73cd78f1 3205static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3206{
3207 struct igb_adapter *adapter = netdev_priv(netdev);
3208
3209 /* only return the current stats */
3210 return &adapter->net_stats;
3211}
3212
3213/**
3214 * igb_change_mtu - Change the Maximum Transfer Unit
3215 * @netdev: network interface device structure
3216 * @new_mtu: new value for maximum frame size
3217 *
3218 * Returns 0 on success, negative on failure
3219 **/
3220static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3221{
3222 struct igb_adapter *adapter = netdev_priv(netdev);
3223 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3224
3225 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3226 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3227 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3228 return -EINVAL;
3229 }
3230
3231#define MAX_STD_JUMBO_FRAME_SIZE 9234
3232 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3233 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3234 return -EINVAL;
3235 }
3236
3237 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3238 msleep(1);
73cd78f1 3239
9d5c8243
AK		 3240 /* igb_down has a dependency on max_frame_size */
3241 adapter->max_frame_size = max_frame;
3242 if (netif_running(netdev))
3243 igb_down(adapter);
3244
3245 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3246 * means we reserve 2 more, this pushes us to allocate from the next
3247 * larger slab size.
3248 * i.e. RXBUFFER_2048 --> size-4096 slab
3249 */
3250
3251 if (max_frame <= IGB_RXBUFFER_256)
3252 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3253 else if (max_frame <= IGB_RXBUFFER_512)
3254 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3255 else if (max_frame <= IGB_RXBUFFER_1024)
3256 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3257 else if (max_frame <= IGB_RXBUFFER_2048)
3258 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3259 else
bf36c1a0
AD		 3260#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3261 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3262#else
3263 adapter->rx_buffer_len = PAGE_SIZE / 2;
3264#endif
9d5c8243
AK		 3265 /* adjust allocation if LPE protects us, and we aren't using SBP */
3266 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3267 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3268 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3269
3270 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3271 netdev->mtu, new_mtu);
3272 netdev->mtu = new_mtu;
3273
3274 if (netif_running(netdev))
3275 igb_up(adapter);
3276 else
3277 igb_reset(adapter);
3278
3279 clear_bit(__IGB_RESETTING, &adapter->state);
3280
3281 return 0;
3282}
3283
3284/**
3285 * igb_update_stats - Update the board statistics counters
3286 * @adapter: board private structure
3287 **/
3288
3289void igb_update_stats(struct igb_adapter *adapter)
3290{
3291 struct e1000_hw *hw = &adapter->hw;
3292 struct pci_dev *pdev = adapter->pdev;
3293 u16 phy_tmp;
3294
3295#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3296
3297 /*
3298 * Prevent stats update while adapter is being reset, or if the pci
3299 * connection is down.
3300 */
3301 if (adapter->link_speed == 0)
3302 return;
3303 if (pci_channel_offline(pdev))
3304 return;
3305
3306 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3307 adapter->stats.gprc += rd32(E1000_GPRC);
3308 adapter->stats.gorc += rd32(E1000_GORCL);
3309 rd32(E1000_GORCH); /* clear GORCL */
3310 adapter->stats.bprc += rd32(E1000_BPRC);
3311 adapter->stats.mprc += rd32(E1000_MPRC);
3312 adapter->stats.roc += rd32(E1000_ROC);
3313
3314 adapter->stats.prc64 += rd32(E1000_PRC64);
3315 adapter->stats.prc127 += rd32(E1000_PRC127);
3316 adapter->stats.prc255 += rd32(E1000_PRC255);
3317 adapter->stats.prc511 += rd32(E1000_PRC511);
3318 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3319 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3320 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3321 adapter->stats.sec += rd32(E1000_SEC);
3322
3323 adapter->stats.mpc += rd32(E1000_MPC);
3324 adapter->stats.scc += rd32(E1000_SCC);
3325 adapter->stats.ecol += rd32(E1000_ECOL);
3326 adapter->stats.mcc += rd32(E1000_MCC);
3327 adapter->stats.latecol += rd32(E1000_LATECOL);
3328 adapter->stats.dc += rd32(E1000_DC);
3329 adapter->stats.rlec += rd32(E1000_RLEC);
3330 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3331 adapter->stats.xontxc += rd32(E1000_XONTXC);
3332 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3333 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3334 adapter->stats.fcruc += rd32(E1000_FCRUC);
3335 adapter->stats.gptc += rd32(E1000_GPTC);
3336 adapter->stats.gotc += rd32(E1000_GOTCL);
3337 rd32(E1000_GOTCH); /* clear GOTCL */
3338 adapter->stats.rnbc += rd32(E1000_RNBC);
3339 adapter->stats.ruc += rd32(E1000_RUC);
3340 adapter->stats.rfc += rd32(E1000_RFC);
3341 adapter->stats.rjc += rd32(E1000_RJC);
3342 adapter->stats.tor += rd32(E1000_TORH);
3343 adapter->stats.tot += rd32(E1000_TOTH);
3344 adapter->stats.tpr += rd32(E1000_TPR);
3345
3346 adapter->stats.ptc64 += rd32(E1000_PTC64);
3347 adapter->stats.ptc127 += rd32(E1000_PTC127);
3348 adapter->stats.ptc255 += rd32(E1000_PTC255);
3349 adapter->stats.ptc511 += rd32(E1000_PTC511);
3350 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3351 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3352
3353 adapter->stats.mptc += rd32(E1000_MPTC);
3354 adapter->stats.bptc += rd32(E1000_BPTC);
3355
3356 /* used for adaptive IFS */
3357
3358 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3359 adapter->stats.tpt += hw->mac.tx_packet_delta;
3360 hw->mac.collision_delta = rd32(E1000_COLC);
3361 adapter->stats.colc += hw->mac.collision_delta;
3362
3363 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3364 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3365 adapter->stats.tncrs += rd32(E1000_TNCRS);
3366 adapter->stats.tsctc += rd32(E1000_TSCTC);
3367 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3368
3369 adapter->stats.iac += rd32(E1000_IAC);
3370 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3371 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3372 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3373 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3374 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3375 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3376 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3377 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3378
3379 /* Fill out the OS statistics structure */
3380 adapter->net_stats.multicast = adapter->stats.mprc;
3381 adapter->net_stats.collisions = adapter->stats.colc;
3382
3383 /* Rx Errors */
3384
3385 /* RLEC on some newer hardware can be incorrect so build
3386 * our own version based on RUC and ROC */
3387 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3388 adapter->stats.crcerrs + adapter->stats.algnerrc +
3389 adapter->stats.ruc + adapter->stats.roc +
3390 adapter->stats.cexterr;
3391 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3392 adapter->stats.roc;
3393 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3394 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3395 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3396
3397 /* Tx Errors */
3398 adapter->net_stats.tx_errors = adapter->stats.ecol +
3399 adapter->stats.latecol;
3400 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3401 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3402 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3403
3404 /* Tx Dropped needs to be maintained elsewhere */
3405
3406 /* Phy Stats */
3407 if (hw->phy.media_type == e1000_media_type_copper) {
3408 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3409 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3410 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3411 adapter->phy_stats.idle_errors += phy_tmp;
3412 }
3413 }
3414
3415 /* Management Stats */
3416 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3417 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3418 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3419}
3420
9d5c8243
AK		 3421static irqreturn_t igb_msix_other(int irq, void *data)
3422{
3423 struct net_device *netdev = data;
3424 struct igb_adapter *adapter = netdev_priv(netdev);
3425 struct e1000_hw *hw = &adapter->hw;
844290e5 3426 u32 icr = rd32(E1000_ICR);
9d5c8243 3427
844290e5 3428 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3429
3430 if(icr & E1000_ICR_DOUTSYNC) {
3431 /* HW is reporting DMA is out of sync */
3432 adapter->stats.doosync++;
3433 }
844290e5
PW		 3434 if (!(icr & E1000_ICR_LSC))
3435 goto no_link_interrupt;
3436 hw->mac.get_link_status = 1;
3437 /* guard against interrupt when we're going down */
3438 if (!test_bit(__IGB_DOWN, &adapter->state))
3439 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3440
9d5c8243 3441no_link_interrupt:
dda0e083 3442 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3443 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3444
3445 return IRQ_HANDLED;
3446}
3447
3448static irqreturn_t igb_msix_tx(int irq, void *data)
3449{
3450 struct igb_ring *tx_ring = data;
3451 struct igb_adapter *adapter = tx_ring->adapter;
3452 struct e1000_hw *hw = &adapter->hw;
3453
421e02f0 3454#ifdef CONFIG_IGB_DCA
7dfc16fa 3455 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3456 igb_update_tx_dca(tx_ring);
3457#endif
73cd78f1 3458
9d5c8243
AK		 3459 tx_ring->total_bytes = 0;
3460 tx_ring->total_packets = 0;
661086df
PWJ		 3461
3462 /* auto mask will automatically reenable the interrupt when we write
3463 * EICS */
3b644cf6 3464 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3465 /* Ring was not completely cleaned, so fire another interrupt */
3466 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3467 else
9d5c8243 3468 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3469
9d5c8243
AK		 3470 return IRQ_HANDLED;
3471}
3472
6eb5a7f1
AD		 3473static void igb_write_itr(struct igb_ring *ring)
3474{
3475 struct e1000_hw *hw = &ring->adapter->hw;
3476 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3477 switch (hw->mac.type) {
3478 case e1000_82576:
73cd78f1 3479 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3480 0x80000000);
3481 break;
3482 default:
73cd78f1 3483 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3484 (ring->itr_val << 16));
3485 break;
3486 }
3487 ring->set_itr = 0;
3488 }
3489}
3490
9d5c8243
AK		 3491static irqreturn_t igb_msix_rx(int irq, void *data)
3492{
3493 struct igb_ring *rx_ring = data;
9d5c8243 3494
844290e5
PW		 3495 /* Write the ITR value calculated at the end of the
3496 * previous interrupt.
3497 */
9d5c8243 3498
6eb5a7f1 3499 igb_write_itr(rx_ring);
9d5c8243 3500
288379f0
BH		 3501 if (napi_schedule_prep(&rx_ring->napi))
3502 __napi_schedule(&rx_ring->napi);
844290e5 3503
421e02f0 3504#ifdef CONFIG_IGB_DCA
8d253320 3505 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3506 igb_update_rx_dca(rx_ring);
3507#endif
3508 return IRQ_HANDLED;
3509}
3510
421e02f0 3511#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3512static void igb_update_rx_dca(struct igb_ring *rx_ring)
3513{
3514 u32 dca_rxctrl;
3515 struct igb_adapter *adapter = rx_ring->adapter;
3516 struct e1000_hw *hw = &adapter->hw;
3517 int cpu = get_cpu();
26bc19ec 3518 int q = rx_ring->reg_idx;
fe4506b6
JC		 3519
3520 if (rx_ring->cpu != cpu) {
3521 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3522 if (hw->mac.type == e1000_82576) {
3523 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3524 dca_rxctrl |= dca_get_tag(cpu) <<
3525 E1000_DCA_RXCTRL_CPUID_SHIFT;
3526 } else {
3527 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3528 dca_rxctrl |= dca_get_tag(cpu);
3529 }
fe4506b6
JC		 3530 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3531 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3532 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3533 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3534 rx_ring->cpu = cpu;
3535 }
3536 put_cpu();
3537}
3538
3539static void igb_update_tx_dca(struct igb_ring *tx_ring)
3540{
3541 u32 dca_txctrl;
3542 struct igb_adapter *adapter = tx_ring->adapter;
3543 struct e1000_hw *hw = &adapter->hw;
3544 int cpu = get_cpu();
26bc19ec 3545 int q = tx_ring->reg_idx;
fe4506b6
JC		 3546
3547 if (tx_ring->cpu != cpu) {
3548 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3549 if (hw->mac.type == e1000_82576) {
3550 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3551 dca_txctrl |= dca_get_tag(cpu) <<
3552 E1000_DCA_TXCTRL_CPUID_SHIFT;
3553 } else {
3554 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3555 dca_txctrl |= dca_get_tag(cpu);
3556 }
fe4506b6
JC		 3557 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3558 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3559 tx_ring->cpu = cpu;
3560 }
3561 put_cpu();
3562}
3563
3564static void igb_setup_dca(struct igb_adapter *adapter)
3565{
3566 int i;
3567
7dfc16fa 3568 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3569 return;
3570
3571 for (i = 0; i < adapter->num_tx_queues; i++) {
3572 adapter->tx_ring[i].cpu = -1;
3573 igb_update_tx_dca(&adapter->tx_ring[i]);
3574 }
3575 for (i = 0; i < adapter->num_rx_queues; i++) {
3576 adapter->rx_ring[i].cpu = -1;
3577 igb_update_rx_dca(&adapter->rx_ring[i]);
3578 }
3579}
3580
3581static int __igb_notify_dca(struct device *dev, void *data)
3582{
3583 struct net_device *netdev = dev_get_drvdata(dev);
3584 struct igb_adapter *adapter = netdev_priv(netdev);
3585 struct e1000_hw *hw = &adapter->hw;
3586 unsigned long event = *(unsigned long *)data;
3587
3588 switch (event) {
3589 case DCA_PROVIDER_ADD:
3590 /* if already enabled, don't do it again */
7dfc16fa 3591 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3592 break;
fe4506b6
JC		 3593 /* Always use CB2 mode, difference is masked
3594 * in the CB driver. */
3595 wr32(E1000_DCA_CTRL, 2);
3596 if (dca_add_requester(dev) == 0) {
bbd98fe4 3597 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3598 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3599 igb_setup_dca(adapter);
3600 break;
3601 }
3602 /* Fall Through since DCA is disabled. */
3603 case DCA_PROVIDER_REMOVE:
7dfc16fa 3604 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3605 /* without this a class_device is left
3606 * hanging around in the sysfs model */
3607 dca_remove_requester(dev);
3608 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3609 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3610 wr32(E1000_DCA_CTRL, 1);
3611 }
3612 break;
3613 }
bbd98fe4 3614
fe4506b6 3615 return 0;
9d5c8243
AK		 3616}
3617
fe4506b6
JC		 3618static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3619 void *p)
3620{
3621 int ret_val;
3622
3623 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3624 __igb_notify_dca);
3625
3626 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3627}
421e02f0 3628#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3629
3630/**
3631 * igb_intr_msi - Interrupt Handler
3632 * @irq: interrupt number
3633 * @data: pointer to a network interface device structure
3634 **/
3635static irqreturn_t igb_intr_msi(int irq, void *data)
3636{
3637 struct net_device *netdev = data;
3638 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3639 struct e1000_hw *hw = &adapter->hw;
3640 /* read ICR disables interrupts using IAM */
3641 u32 icr = rd32(E1000_ICR);
3642
6eb5a7f1 3643 igb_write_itr(adapter->rx_ring);
9d5c8243 3644
dda0e083
AD		 3645 if(icr & E1000_ICR_DOUTSYNC) {
3646 /* HW is reporting DMA is out of sync */
3647 adapter->stats.doosync++;
3648 }
3649
9d5c8243
AK		 3650 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3651 hw->mac.get_link_status = 1;
3652 if (!test_bit(__IGB_DOWN, &adapter->state))
3653 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3654 }
3655
288379f0 3656 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3657
3658 return IRQ_HANDLED;
3659}
3660
3661/**
4a3c6433 3662 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3663 * @irq: interrupt number
3664 * @data: pointer to a network interface device structure
3665 **/
3666static irqreturn_t igb_intr(int irq, void *data)
3667{
3668 struct net_device *netdev = data;
3669 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3670 struct e1000_hw *hw = &adapter->hw;
3671 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3672 * need for the IMC write */
3673 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3674 if (!icr)
3675 return IRQ_NONE; /* Not our interrupt */
3676
6eb5a7f1 3677 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3678
3679 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3680 * not set, then the adapter didn't send an interrupt */
3681 if (!(icr & E1000_ICR_INT_ASSERTED))
3682 return IRQ_NONE;
3683
dda0e083
AD		 3684 if(icr & E1000_ICR_DOUTSYNC) {
3685 /* HW is reporting DMA is out of sync */
3686 adapter->stats.doosync++;
3687 }
3688
9d5c8243
AK		 3689 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3690 hw->mac.get_link_status = 1;
3691 /* guard against interrupt when we're going down */
3692 if (!test_bit(__IGB_DOWN, &adapter->state))
3693 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3694 }
3695
288379f0 3696 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3697
3698 return IRQ_HANDLED;
3699}
3700
3701/**
661086df
PWJ		 3702 * igb_poll - NAPI Rx polling callback
3703 * @napi: napi polling structure
3704 * @budget: count of how many packets we should handle
9d5c8243 3705 **/
661086df 3706static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3707{
661086df
PWJ		 3708 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3709 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3710 struct net_device *netdev = adapter->netdev;
661086df 3711 int tx_clean_complete, work_done = 0;
9d5c8243 3712
661086df 3713 /* this poll routine only supports one tx and one rx queue */
421e02f0 3714#ifdef CONFIG_IGB_DCA
7dfc16fa 3715 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3716 igb_update_tx_dca(&adapter->tx_ring[0]);
3717#endif
661086df 3718 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3719
421e02f0 3720#ifdef CONFIG_IGB_DCA
7dfc16fa 3721 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3722 igb_update_rx_dca(&adapter->rx_ring[0]);
3723#endif
661086df 3724 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3725
3726 /* If no Tx and not enough Rx work done, exit the polling mode */
3727 if ((tx_clean_complete && (work_done < budget)) ||
3728 !netif_running(netdev)) {
9d5c8243 3729 if (adapter->itr_setting & 3)
6eb5a7f1 3730 igb_set_itr(adapter);
288379f0 3731 napi_complete(napi);
9d5c8243
AK		 3732 if (!test_bit(__IGB_DOWN, &adapter->state))
3733 igb_irq_enable(adapter);
3734 return 0;
3735 }
3736
3737 return 1;
3738}
3739
3740static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3741{
3742 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3743 struct igb_adapter *adapter = rx_ring->adapter;
3744 struct e1000_hw *hw = &adapter->hw;
3745 struct net_device *netdev = adapter->netdev;
3746 int work_done = 0;
3747
421e02f0 3748#ifdef CONFIG_IGB_DCA
7dfc16fa 3749 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3750 igb_update_rx_dca(rx_ring);
3751#endif
3b644cf6 3752 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 3753
9d5c8243
AK		 3754 /* If not enough Rx work done, exit the polling mode */
3755 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3756 napi_complete(napi);
9d5c8243 3757
6eb5a7f1
AD		 3758 if (adapter->itr_setting & 3) {
3759 if (adapter->num_rx_queues == 1)
3760 igb_set_itr(adapter);
3761 else
3762 igb_update_ring_itr(rx_ring);
9d5c8243 3763 }
844290e5
PW		 3764 if (!test_bit(__IGB_DOWN, &adapter->state))
3765 wr32(E1000_EIMS, rx_ring->eims_value);
3766
9d5c8243
AK		 3767 return 0;
3768 }
3769
3770 return 1;
3771}
6d8126f9 3772
33af6bcc
PO		 3773/**
3774 * igb_hwtstamp - utility function which checks for TX time stamp
3775 * @adapter: board private structure
3776 * @skb: packet that was just sent
3777 *
3778 * If we were asked to do hardware stamping and such a time stamp is
3779 * available, then it must have been for this skb here because we only
3780 * allow only one such packet into the queue.
3781 */
3782static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
3783{
3784 union skb_shared_tx *shtx = skb_tx(skb);
3785 struct e1000_hw *hw = &adapter->hw;
3786
3787 if (unlikely(shtx->hardware)) {
3788 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
3789 if (valid) {
3790 u64 regval = rd32(E1000_TXSTMPL);
3791 u64 ns;
3792 struct skb_shared_hwtstamps shhwtstamps;
3793
3794 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3795 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
3796 ns = timecounter_cyc2time(&adapter->clock,
3797 regval);
3798 timecompare_update(&adapter->compare, ns);
3799 shhwtstamps.hwtstamp = ns_to_ktime(ns);
3800 shhwtstamps.syststamp =
3801 timecompare_transform(&adapter->compare, ns);
3802 skb_tstamp_tx(skb, &shhwtstamps);
3803 }
3804
3805 /* delayed orphaning: skb_tstamp_tx() needs the socket */
3806 skb_orphan(skb);
3807 }
3808}
3809
9d5c8243
AK		 3810/**
3811 * igb_clean_tx_irq - Reclaim resources after transmit completes
3812 * @adapter: board private structure
3813 * returns true if ring is completely cleaned
3814 **/
3b644cf6 3815static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3816{
3b644cf6 3817 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3818 struct net_device *netdev = adapter->netdev;
0e014cb1 3819 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3820 struct igb_buffer *buffer_info;
3821 struct sk_buff *skb;
0e014cb1 3822 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3823 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3824 unsigned int i, eop, count = 0;
3825 bool cleaned = false;
9d5c8243 3826
9d5c8243 3827 i = tx_ring->next_to_clean;
0e014cb1
AD		 3828 eop = tx_ring->buffer_info[i].next_to_watch;
3829 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3830
3831 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3832 (count < tx_ring->count)) {
3833 for (cleaned = false; !cleaned; count++) {
3834 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3835 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3836 cleaned = (i == eop);
9d5c8243
AK		 3837 skb = buffer_info->skb;
3838
3839 if (skb) {
3840 unsigned int segs, bytecount;
3841 /* gso_segs is currently only valid for tcp */
3842 segs = skb_shinfo(skb)->gso_segs ?: 1;
3843 /* multiply data chunks by size of headers */
3844 bytecount = ((segs - 1) * skb_headlen(skb)) +
3845 skb->len;
3846 total_packets += segs;
3847 total_bytes += bytecount;
33af6bcc
PO		 3848
3849 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 3850 }
3851
3852 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3853 tx_desc->wb.status = 0;
9d5c8243
AK		 3854
3855 i++;
3856 if (i == tx_ring->count)
3857 i = 0;
9d5c8243 3858 }
0e014cb1
AD		 3859 eop = tx_ring->buffer_info[i].next_to_watch;
3860 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3861 }
3862
9d5c8243
AK		 3863 tx_ring->next_to_clean = i;
3864
fc7d345d 3865 if (unlikely(count &&
9d5c8243
AK		 3866 netif_carrier_ok(netdev) &&
3867 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3868 /* Make sure that anybody stopping the queue after this
3869 * sees the new next_to_clean.
3870 */
3871 smp_mb();
661086df
PWJ		 3872 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3873 !(test_bit(__IGB_DOWN, &adapter->state))) {
3874 netif_wake_subqueue(netdev, tx_ring->queue_index);
3875 ++adapter->restart_queue;
3876 }
9d5c8243
AK		 3877 }
3878
3879 if (tx_ring->detect_tx_hung) {
3880 /* Detect a transmit hang in hardware, this serializes the
3881 * check with the clearing of time_stamp and movement of i */
3882 tx_ring->detect_tx_hung = false;
3883 if (tx_ring->buffer_info[i].time_stamp &&
3884 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3885 (adapter->tx_timeout_factor * HZ))
3886 && !(rd32(E1000_STATUS) &
3887 E1000_STATUS_TXOFF)) {
3888
9d5c8243
AK		 3889 /* detected Tx unit hang */
3890 dev_err(&adapter->pdev->dev,
3891 "Detected Tx Unit Hang\n"
2d064c06 3892 " Tx Queue <%d>\n"
9d5c8243
AK		 3893 " TDH <%x>\n"
3894 " TDT <%x>\n"
3895 " next_to_use <%x>\n"
3896 " next_to_clean <%x>\n"
9d5c8243
AK		 3897 "buffer_info[next_to_clean]\n"
3898 " time_stamp <%lx>\n"
0e014cb1 3899 " next_to_watch <%x>\n"
9d5c8243
AK		 3900 " jiffies <%lx>\n"
3901 " desc.status <%x>\n",
2d064c06 3902 tx_ring->queue_index,
9d5c8243
AK		 3903 readl(adapter->hw.hw_addr + tx_ring->head),
3904 readl(adapter->hw.hw_addr + tx_ring->tail),
3905 tx_ring->next_to_use,
3906 tx_ring->next_to_clean,
9d5c8243 3907 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3908 eop,
9d5c8243 3909 jiffies,
0e014cb1 3910 eop_desc->wb.status);
661086df 3911 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3912 }
3913 }
3914 tx_ring->total_bytes += total_bytes;
3915 tx_ring->total_packets += total_packets;
e21ed353
AD		 3916 tx_ring->tx_stats.bytes += total_bytes;
3917 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3918 adapter->net_stats.tx_bytes += total_bytes;
3919 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3920 return (count < tx_ring->count);
9d5c8243
AK		 3921}
3922
9d5c8243
AK		 3923/**
3924 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3925 * @ring: pointer to receive ring receving this packet
9d5c8243 3926 * @status: descriptor status field as written by hardware
73cd78f1 3927 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 3928 * @skb: pointer to sk_buff to be indicated to stack
3929 **/
d3352520
AD		 3930static void igb_receive_skb(struct igb_ring *ring, u8 status,
3931 union e1000_adv_rx_desc * rx_desc,
3932 struct sk_buff *skb)
3933{
3934 struct igb_adapter * adapter = ring->adapter;
3935 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3936
0c8dfc83 3937 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3938 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3939 if (vlan_extracted)
5c0999b7
HX		 3940 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3941 le16_to_cpu(rx_desc->wb.upper.vlan),
3942 skb);
d3352520 3943 else
5c0999b7 3944 napi_gro_receive(&ring->napi, skb);
d3352520 3945 } else {
d3352520
AD		 3946 if (vlan_extracted)
3947 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3948 le16_to_cpu(rx_desc->wb.upper.vlan));
3949 else
d3352520 3950 netif_receive_skb(skb);
d3352520 3951 }
9d5c8243
AK		 3952}
3953
9d5c8243
AK		 3954static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3955 u32 status_err, struct sk_buff *skb)
3956{
3957 skb->ip_summed = CHECKSUM_NONE;
3958
3959 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3960 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3961 return;
3962 /* TCP/UDP checksum error bit is set */
3963 if (status_err &
3964 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3965 /* let the stack verify checksum errors */
3966 adapter->hw_csum_err++;
3967 return;
3968 }
3969 /* It must be a TCP or UDP packet with a valid checksum */
3970 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3971 skb->ip_summed = CHECKSUM_UNNECESSARY;
3972
3973 adapter->hw_csum_good++;
3974}
3975
3b644cf6
MW		 3976static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3977 int *work_done, int budget)
9d5c8243 3978{
3b644cf6 3979 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3980 struct net_device *netdev = adapter->netdev;
33af6bcc 3981 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3982 struct pci_dev *pdev = adapter->pdev;
3983 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3984 struct igb_buffer *buffer_info , *next_buffer;
3985 struct sk_buff *skb;
9d5c8243
AK		 3986 bool cleaned = false;
3987 int cleaned_count = 0;
3988 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 3989 unsigned int i;
3990 u32 length, hlen, staterr;
9d5c8243
AK		 3991
3992 i = rx_ring->next_to_clean;
69d3ca53 3993 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3994 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3995 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3996
3997 while (staterr & E1000_RXD_STAT_DD) {
3998 if (*work_done >= budget)
3999 break;
4000 (*work_done)++;
9d5c8243 4001
69d3ca53
AD		 4002 skb = buffer_info->skb;
4003 prefetch(skb->data - NET_IP_ALIGN);
4004 buffer_info->skb = NULL;
4005
4006 i++;
4007 if (i == rx_ring->count)
4008 i = 0;
4009 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4010 prefetch(next_rxd);
4011 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4012
4013 length = le16_to_cpu(rx_desc->wb.upper.length);
4014 cleaned = true;
4015 cleaned_count++;
4016
bf36c1a0
AD		 4017 if (!adapter->rx_ps_hdr_size) {
4018 pci_unmap_single(pdev, buffer_info->dma,
4019 adapter->rx_buffer_len +
4020 NET_IP_ALIGN,
4021 PCI_DMA_FROMDEVICE);
4022 skb_put(skb, length);
4023 goto send_up;
9d5c8243
AK		 4024 }
4025
69d3ca53
AD		 4026 /* HW will not DMA in data larger than the given buffer, even
4027 * if it parses the (NFS, of course) header to be larger. In
4028 * that case, it fills the header buffer and spills the rest
4029 * into the page.
4030 */
4031 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4032 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4033 if (hlen > adapter->rx_ps_hdr_size)
4034 hlen = adapter->rx_ps_hdr_size;
4035
bf36c1a0
AD		 4036 if (!skb_shinfo(skb)->nr_frags) {
4037 pci_unmap_single(pdev, buffer_info->dma,
73cd78f1 4038 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
bf36c1a0
AD		 4039 PCI_DMA_FROMDEVICE);
4040 skb_put(skb, hlen);
4041 }
4042
4043 if (length) {
9d5c8243 4044 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4045 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4046 buffer_info->page_dma = 0;
bf36c1a0
AD		 4047
4048 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4049 buffer_info->page,
4050 buffer_info->page_offset,
4051 length);
4052
4053 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4054 (page_count(buffer_info->page) != 1))
4055 buffer_info->page = NULL;
4056 else
4057 get_page(buffer_info->page);
9d5c8243
AK		 4058
4059 skb->len += length;
4060 skb->data_len += length;
9d5c8243 4061
bf36c1a0 4062 skb->truesize += length;
9d5c8243 4063 }
9d5c8243 4064
bf36c1a0 4065 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4066 buffer_info->skb = next_buffer->skb;
4067 buffer_info->dma = next_buffer->dma;
4068 next_buffer->skb = skb;
4069 next_buffer->dma = 0;
bf36c1a0
AD		 4070 goto next_desc;
4071 }
69d3ca53 4072send_up:
33af6bcc
PO		 4073 /*
4074 * If this bit is set, then the RX registers contain
4075 * the time stamp. No other packet will be time
4076 * stamped until we read these registers, so read the
4077 * registers to make them available again. Because
4078 * only one packet can be time stamped at a time, we
4079 * know that the register values must belong to this
4080 * one here and therefore we don't need to compare
4081 * any of the additional attributes stored for it.
4082 *
4083 * If nothing went wrong, then it should have a
4084 * skb_shared_tx that we can turn into a
4085 * skb_shared_hwtstamps.
4086 *
4087 * TODO: can time stamping be triggered (thus locking
4088 * the registers) without the packet reaching this point
4089 * here? In that case RX time stamping would get stuck.
4090 *
4091 * TODO: in "time stamp all packets" mode this bit is
4092 * not set. Need a global flag for this mode and then
4093 * always read the registers. Cannot be done without
4094 * a race condition.
4095 */
4096 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4097 u64 regval;
4098 u64 ns;
4099 struct skb_shared_hwtstamps *shhwtstamps =
4100 skb_hwtstamps(skb);
4101
4102 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4103 "igb: no RX time stamp available for time stamped packet");
4104 regval = rd32(E1000_RXSTMPL);
4105 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4106 ns = timecounter_cyc2time(&adapter->clock, regval);
4107 timecompare_update(&adapter->compare, ns);
4108 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4109 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4110 shhwtstamps->syststamp =
4111 timecompare_transform(&adapter->compare, ns);
4112 }
4113
9d5c8243
AK		 4114 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4115 dev_kfree_skb_irq(skb);
4116 goto next_desc;
4117 }
9d5c8243
AK		 4118
4119 total_bytes += skb->len;
4120 total_packets++;
4121
4122 igb_rx_checksum_adv(adapter, staterr, skb);
4123
4124 skb->protocol = eth_type_trans(skb, netdev);
4125
d3352520 4126 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4127
9d5c8243
AK		 4128next_desc:
4129 rx_desc->wb.upper.status_error = 0;
4130
4131 /* return some buffers to hardware, one at a time is too slow */
4132 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4133 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4134 cleaned_count = 0;
4135 }
4136
4137 /* use prefetched values */
4138 rx_desc = next_rxd;
4139 buffer_info = next_buffer;
9d5c8243
AK		 4140 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4141 }
bf36c1a0 4142
9d5c8243
AK		 4143 rx_ring->next_to_clean = i;
4144 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4145
4146 if (cleaned_count)
3b644cf6 4147 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4148
4149 rx_ring->total_packets += total_packets;
4150 rx_ring->total_bytes += total_bytes;
4151 rx_ring->rx_stats.packets += total_packets;
4152 rx_ring->rx_stats.bytes += total_bytes;
4153 adapter->net_stats.rx_bytes += total_bytes;
4154 adapter->net_stats.rx_packets += total_packets;
4155 return cleaned;
4156}
4157
9d5c8243
AK		 4158/**
4159 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4160 * @adapter: address of board private structure
4161 **/
3b644cf6 4162static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4163 int cleaned_count)
4164{
3b644cf6 4165 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4166 struct net_device *netdev = adapter->netdev;
4167 struct pci_dev *pdev = adapter->pdev;
4168 union e1000_adv_rx_desc *rx_desc;
4169 struct igb_buffer *buffer_info;
4170 struct sk_buff *skb;
4171 unsigned int i;
db761762 4172 int bufsz;
9d5c8243
AK		 4173
4174 i = rx_ring->next_to_use;
4175 buffer_info = &rx_ring->buffer_info[i];
4176
db761762
AD		 4177 if (adapter->rx_ps_hdr_size)
4178 bufsz = adapter->rx_ps_hdr_size;
4179 else
4180 bufsz = adapter->rx_buffer_len;
4181 bufsz += NET_IP_ALIGN;
4182
9d5c8243
AK		 4183 while (cleaned_count--) {
4184 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4185
bf36c1a0 4186 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4187 if (!buffer_info->page) {
bf36c1a0
AD		 4188 buffer_info->page = alloc_page(GFP_ATOMIC);
4189 if (!buffer_info->page) {
4190 adapter->alloc_rx_buff_failed++;
4191 goto no_buffers;
4192 }
4193 buffer_info->page_offset = 0;
4194 } else {
4195 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4196 }
4197 buffer_info->page_dma =
db761762 4198 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4199 buffer_info->page_offset,
4200 PAGE_SIZE / 2,
9d5c8243
AK		 4201 PCI_DMA_FROMDEVICE);
4202 }
4203
4204 if (!buffer_info->skb) {
9d5c8243 4205 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4206 if (!skb) {
4207 adapter->alloc_rx_buff_failed++;
4208 goto no_buffers;
4209 }
4210
4211 /* Make buffer alignment 2 beyond a 16 byte boundary
4212 * this will result in a 16 byte aligned IP header after
4213 * the 14 byte MAC header is removed
4214 */
4215 skb_reserve(skb, NET_IP_ALIGN);
4216
4217 buffer_info->skb = skb;
4218 buffer_info->dma = pci_map_single(pdev, skb->data,
4219 bufsz,
4220 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4221 }
4222 /* Refresh the desc even if buffer_addrs didn't change because
4223 * each write-back erases this info. */
4224 if (adapter->rx_ps_hdr_size) {
4225 rx_desc->read.pkt_addr =
4226 cpu_to_le64(buffer_info->page_dma);
4227 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4228 } else {
4229 rx_desc->read.pkt_addr =
4230 cpu_to_le64(buffer_info->dma);
4231 rx_desc->read.hdr_addr = 0;
4232 }
4233
4234 i++;
4235 if (i == rx_ring->count)
4236 i = 0;
4237 buffer_info = &rx_ring->buffer_info[i];
4238 }
4239
4240no_buffers:
4241 if (rx_ring->next_to_use != i) {
4242 rx_ring->next_to_use = i;
4243 if (i == 0)
4244 i = (rx_ring->count - 1);
4245 else
4246 i--;
4247
4248 /* Force memory writes to complete before letting h/w
4249 * know there are new descriptors to fetch. (Only
4250 * applicable for weak-ordered memory model archs,
4251 * such as IA-64). */
4252 wmb();
4253 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4254 }
4255}
4256
4257/**
4258 * igb_mii_ioctl -
4259 * @netdev:
4260 * @ifreq:
4261 * @cmd:
4262 **/
4263static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4264{
4265 struct igb_adapter *adapter = netdev_priv(netdev);
4266 struct mii_ioctl_data *data = if_mii(ifr);
4267
4268 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4269 return -EOPNOTSUPP;
4270
4271 switch (cmd) {
4272 case SIOCGMIIPHY:
4273 data->phy_id = adapter->hw.phy.addr;
4274 break;
4275 case SIOCGMIIREG:
4276 if (!capable(CAP_NET_ADMIN))
4277 return -EPERM;
f5f4cf08
AD		 4278 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4279 &data->val_out))
9d5c8243
AK		 4280 return -EIO;
4281 break;
4282 case SIOCSMIIREG:
4283 default:
4284 return -EOPNOTSUPP;
4285 }
4286 return 0;
4287}
4288
c6cb090b
PO		 4289/**
4290 * igb_hwtstamp_ioctl - control hardware time stamping
4291 * @netdev:
4292 * @ifreq:
4293 * @cmd:
4294 *
33af6bcc
PO		 4295 * Outgoing time stamping can be enabled and disabled. Play nice and
4296 * disable it when requested, although it shouldn't case any overhead
4297 * when no packet needs it. At most one packet in the queue may be
4298 * marked for time stamping, otherwise it would be impossible to tell
4299 * for sure to which packet the hardware time stamp belongs.
4300 *
4301 * Incoming time stamping has to be configured via the hardware
4302 * filters. Not all combinations are supported, in particular event
4303 * type has to be specified. Matching the kind of event packet is
4304 * not supported, with the exception of "all V2 events regardless of
4305 * level 2 or 4".
4306 *
c6cb090b
PO		 4307 **/
4308static int igb_hwtstamp_ioctl(struct net_device *netdev,
4309 struct ifreq *ifr, int cmd)
4310{
33af6bcc
PO		 4311 struct igb_adapter *adapter = netdev_priv(netdev);
4312 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4313 struct hwtstamp_config config;
33af6bcc
PO		 4314 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4315 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4316 u32 tsync_rx_ctl_type = 0;
4317 u32 tsync_rx_cfg = 0;
4318 int is_l4 = 0;
4319 int is_l2 = 0;
4320 short port = 319; /* PTP */
4321 u32 regval;
c6cb090b
PO		 4322
4323 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4324 return -EFAULT;
4325
4326 /* reserved for future extensions */
4327 if (config.flags)
4328 return -EINVAL;
4329
33af6bcc
PO		 4330 switch (config.tx_type) {
4331 case HWTSTAMP_TX_OFF:
4332 tsync_tx_ctl_bit = 0;
4333 break;
4334 case HWTSTAMP_TX_ON:
4335 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4336 break;
4337 default:
4338 return -ERANGE;
4339 }
4340
4341 switch (config.rx_filter) {
4342 case HWTSTAMP_FILTER_NONE:
4343 tsync_rx_ctl_bit = 0;
4344 break;
4345 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4346 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4347 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4348 case HWTSTAMP_FILTER_ALL:
4349 /*
4350 * register TSYNCRXCFG must be set, therefore it is not
4351 * possible to time stamp both Sync and Delay_Req messages
4352 * => fall back to time stamping all packets
4353 */
4354 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4355 config.rx_filter = HWTSTAMP_FILTER_ALL;
4356 break;
4357 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4358 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4359 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4360 is_l4 = 1;
4361 break;
4362 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4363 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4364 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4365 is_l4 = 1;
4366 break;
4367 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4368 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4369 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4370 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4371 is_l2 = 1;
4372 is_l4 = 1;
4373 config.rx_filter = HWTSTAMP_FILTER_SOME;
4374 break;
4375 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4376 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4377 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4378 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4379 is_l2 = 1;
4380 is_l4 = 1;
4381 config.rx_filter = HWTSTAMP_FILTER_SOME;
4382 break;
4383 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4384 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4385 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4386 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4387 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4388 is_l2 = 1;
4389 break;
4390 default:
4391 return -ERANGE;
4392 }
4393
4394 /* enable/disable TX */
4395 regval = rd32(E1000_TSYNCTXCTL);
4396 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4397 wr32(E1000_TSYNCTXCTL, regval);
4398
4399 /* enable/disable RX, define which PTP packets are time stamped */
4400 regval = rd32(E1000_TSYNCRXCTL);
4401 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4402 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4403 wr32(E1000_TSYNCRXCTL, regval);
4404 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4405
4406 /*
4407 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4408 * (Ethertype to filter on)
4409 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4410 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4411 */
4412 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4413
4414 /* L4 Queue Filter[0]: only filter by source and destination port */
4415 wr32(E1000_SPQF0, htons(port));
4416 wr32(E1000_IMIREXT(0), is_l4 ?
4417 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4418 wr32(E1000_IMIR(0), is_l4 ?
4419 (htons(port)
4420 | (0<<16) /* immediate interrupt disabled */
4421 | 0 /* (1<<17) bit cleared: do not bypass
4422 destination port check */)
4423 : 0);
4424 wr32(E1000_FTQF0, is_l4 ?
4425 (0x11 /* UDP */
4426 | (1<<15) /* VF not compared */
4427 | (1<<27) /* Enable Timestamping */
4428 | (7<<28) /* only source port filter enabled,
4429 source/target address and protocol
4430 masked */)
4431 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4432 enabled */));
4433
4434 wrfl();
4435
4436 adapter->hwtstamp_config = config;
4437
4438 /* clear TX/RX time stamp registers, just to be sure */
4439 regval = rd32(E1000_TXSTMPH);
4440 regval = rd32(E1000_RXSTMPH);
c6cb090b 4441
33af6bcc
PO		 4442 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4443 -EFAULT : 0;
c6cb090b
PO		 4444}
4445
9d5c8243
AK		 4446/**
4447 * igb_ioctl -
4448 * @netdev:
4449 * @ifreq:
4450 * @cmd:
4451 **/
4452static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4453{
4454 switch (cmd) {
4455 case SIOCGMIIPHY:
4456 case SIOCGMIIREG:
4457 case SIOCSMIIREG:
4458 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 4459 case SIOCSHWTSTAMP:
4460 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 4461 default:
4462 return -EOPNOTSUPP;
4463 }
4464}
4465
4466static void igb_vlan_rx_register(struct net_device *netdev,
4467 struct vlan_group *grp)
4468{
4469 struct igb_adapter *adapter = netdev_priv(netdev);
4470 struct e1000_hw *hw = &adapter->hw;
4471 u32 ctrl, rctl;
4472
4473 igb_irq_disable(adapter);
4474 adapter->vlgrp = grp;
4475
4476 if (grp) {
4477 /* enable VLAN tag insert/strip */
4478 ctrl = rd32(E1000_CTRL);
4479 ctrl |= E1000_CTRL_VME;
4480 wr32(E1000_CTRL, ctrl);
4481
4482 /* enable VLAN receive filtering */
4483 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4484 rctl &= ~E1000_RCTL_CFIEN;
4485 wr32(E1000_RCTL, rctl);
4486 igb_update_mng_vlan(adapter);
4487 wr32(E1000_RLPML,
4488 adapter->max_frame_size + VLAN_TAG_SIZE);
4489 } else {
4490 /* disable VLAN tag insert/strip */
4491 ctrl = rd32(E1000_CTRL);
4492 ctrl &= ~E1000_CTRL_VME;
4493 wr32(E1000_CTRL, ctrl);
4494
9d5c8243
AK		 4495 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4496 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4497 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4498 }
4499 wr32(E1000_RLPML,
4500 adapter->max_frame_size);
4501 }
4502
4503 if (!test_bit(__IGB_DOWN, &adapter->state))
4504 igb_irq_enable(adapter);
4505}
4506
4507static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4508{
4509 struct igb_adapter *adapter = netdev_priv(netdev);
4510 struct e1000_hw *hw = &adapter->hw;
4511 u32 vfta, index;
4512
28b0759c 4513 if ((hw->mng_cookie.status &
9d5c8243
AK		 4514 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4515 (vid == adapter->mng_vlan_id))
4516 return;
4517 /* add VID to filter table */
4518 index = (vid >> 5) & 0x7F;
4519 vfta = array_rd32(E1000_VFTA, index);
4520 vfta |= (1 << (vid & 0x1F));
4521 igb_write_vfta(&adapter->hw, index, vfta);
4522}
4523
4524static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4525{
4526 struct igb_adapter *adapter = netdev_priv(netdev);
4527 struct e1000_hw *hw = &adapter->hw;
4528 u32 vfta, index;
4529
4530 igb_irq_disable(adapter);
4531 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4532
4533 if (!test_bit(__IGB_DOWN, &adapter->state))
4534 igb_irq_enable(adapter);
4535
4536 if ((adapter->hw.mng_cookie.status &
4537 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4538 (vid == adapter->mng_vlan_id)) {
4539 /* release control to f/w */
4540 igb_release_hw_control(adapter);
4541 return;
4542 }
4543
4544 /* remove VID from filter table */
4545 index = (vid >> 5) & 0x7F;
4546 vfta = array_rd32(E1000_VFTA, index);
4547 vfta &= ~(1 << (vid & 0x1F));
4548 igb_write_vfta(&adapter->hw, index, vfta);
4549}
4550
4551static void igb_restore_vlan(struct igb_adapter *adapter)
4552{
4553 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4554
4555 if (adapter->vlgrp) {
4556 u16 vid;
4557 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4558 if (!vlan_group_get_device(adapter->vlgrp, vid))
4559 continue;
4560 igb_vlan_rx_add_vid(adapter->netdev, vid);
4561 }
4562 }
4563}
4564
4565int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4566{
4567 struct e1000_mac_info *mac = &adapter->hw.mac;
4568
4569 mac->autoneg = 0;
4570
4571 /* Fiber NICs only allow 1000 gbps Full duplex */
4572 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4573 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4574 dev_err(&adapter->pdev->dev,
4575 "Unsupported Speed/Duplex configuration\n");
4576 return -EINVAL;
4577 }
4578
4579 switch (spddplx) {
4580 case SPEED_10 + DUPLEX_HALF:
4581 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4582 break;
4583 case SPEED_10 + DUPLEX_FULL:
4584 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4585 break;
4586 case SPEED_100 + DUPLEX_HALF:
4587 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4588 break;
4589 case SPEED_100 + DUPLEX_FULL:
4590 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4591 break;
4592 case SPEED_1000 + DUPLEX_FULL:
4593 mac->autoneg = 1;
4594 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4595 break;
4596 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4597 default:
4598 dev_err(&adapter->pdev->dev,
4599 "Unsupported Speed/Duplex configuration\n");
4600 return -EINVAL;
4601 }
4602 return 0;
4603}
4604
9d5c8243
AK		 4605static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4606{
4607 struct net_device *netdev = pci_get_drvdata(pdev);
4608 struct igb_adapter *adapter = netdev_priv(netdev);
4609 struct e1000_hw *hw = &adapter->hw;
2d064c06 4610 u32 ctrl, rctl, status;
9d5c8243
AK		 4611 u32 wufc = adapter->wol;
4612#ifdef CONFIG_PM
4613 int retval = 0;
4614#endif
4615
4616 netif_device_detach(netdev);
4617
a88f10ec
AD		 4618 if (netif_running(netdev))
4619 igb_close(netdev);
4620
4621 igb_reset_interrupt_capability(adapter);
4622
4623 igb_free_queues(adapter);
9d5c8243
AK		 4624
4625#ifdef CONFIG_PM
4626 retval = pci_save_state(pdev);
4627 if (retval)
4628 return retval;
4629#endif
4630
4631 status = rd32(E1000_STATUS);
4632 if (status & E1000_STATUS_LU)
4633 wufc &= ~E1000_WUFC_LNKC;
4634
4635 if (wufc) {
4636 igb_setup_rctl(adapter);
4637 igb_set_multi(netdev);
4638
4639 /* turn on all-multi mode if wake on multicast is enabled */
4640 if (wufc & E1000_WUFC_MC) {
4641 rctl = rd32(E1000_RCTL);
4642 rctl |= E1000_RCTL_MPE;
4643 wr32(E1000_RCTL, rctl);
4644 }
4645
4646 ctrl = rd32(E1000_CTRL);
4647 /* advertise wake from D3Cold */
4648 #define E1000_CTRL_ADVD3WUC 0x00100000
4649 /* phy power management enable */
4650 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4651 ctrl |= E1000_CTRL_ADVD3WUC;
4652 wr32(E1000_CTRL, ctrl);
4653
9d5c8243
AK		 4654 /* Allow time for pending master requests to run */
4655 igb_disable_pcie_master(&adapter->hw);
4656
4657 wr32(E1000_WUC, E1000_WUC_PME_EN);
4658 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4659 } else {
4660 wr32(E1000_WUC, 0);
4661 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4662 }
4663
2d064c06
AD		 4664 /* make sure adapter isn't asleep if manageability/wol is enabled */
4665 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4666 pci_enable_wake(pdev, PCI_D3hot, 1);
4667 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4668 } else {
4669 igb_shutdown_fiber_serdes_link_82575(hw);
4670 pci_enable_wake(pdev, PCI_D3hot, 0);
4671 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4672 }
4673
4674 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4675 * would have already happened in close and is redundant. */
4676 igb_release_hw_control(adapter);
4677
4678 pci_disable_device(pdev);
4679
4680 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4681
4682 return 0;
4683}
4684
4685#ifdef CONFIG_PM
4686static int igb_resume(struct pci_dev *pdev)
4687{
4688 struct net_device *netdev = pci_get_drvdata(pdev);
4689 struct igb_adapter *adapter = netdev_priv(netdev);
4690 struct e1000_hw *hw = &adapter->hw;
4691 u32 err;
4692
4693 pci_set_power_state(pdev, PCI_D0);
4694 pci_restore_state(pdev);
42bfd33a 4695
aed5dec3 4696 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4697 if (err) {
4698 dev_err(&pdev->dev,
4699 "igb: Cannot enable PCI device from suspend\n");
4700 return err;
4701 }
4702 pci_set_master(pdev);
4703
4704 pci_enable_wake(pdev, PCI_D3hot, 0);
4705 pci_enable_wake(pdev, PCI_D3cold, 0);
4706
a88f10ec
AD		 4707 igb_set_interrupt_capability(adapter);
4708
4709 if (igb_alloc_queues(adapter)) {
4710 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4711 return -ENOMEM;
9d5c8243
AK		 4712 }
4713
4714 /* e1000_power_up_phy(adapter); */
4715
4716 igb_reset(adapter);
a8564f03
AD		 4717
4718 /* let the f/w know that the h/w is now under the control of the
4719 * driver. */
4720 igb_get_hw_control(adapter);
4721
9d5c8243
AK		 4722 wr32(E1000_WUS, ~0);
4723
a88f10ec
AD		 4724 if (netif_running(netdev)) {
4725 err = igb_open(netdev);
4726 if (err)
4727 return err;
4728 }
9d5c8243
AK		 4729
4730 netif_device_attach(netdev);
4731
9d5c8243
AK		 4732 return 0;
4733}
4734#endif
4735
4736static void igb_shutdown(struct pci_dev *pdev)
4737{
4738 igb_suspend(pdev, PMSG_SUSPEND);
4739}
4740
4741#ifdef CONFIG_NET_POLL_CONTROLLER
4742/*
4743 * Polling 'interrupt' - used by things like netconsole to send skbs
4744 * without having to re-enable interrupts. It's not called while
4745 * the interrupt routine is executing.
4746 */
4747static void igb_netpoll(struct net_device *netdev)
4748{
4749 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4750 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4751 int i;
9d5c8243 4752
eebbbdba
AD		 4753 if (!adapter->msix_entries) {
4754 igb_irq_disable(adapter);
4755 napi_schedule(&adapter->rx_ring[0].napi);
4756 return;
4757 }
9d5c8243 4758
eebbbdba
AD		 4759 for (i = 0; i < adapter->num_tx_queues; i++) {
4760 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4761 wr32(E1000_EIMC, tx_ring->eims_value);
4762 igb_clean_tx_irq(tx_ring);
4763 wr32(E1000_EIMS, tx_ring->eims_value);
4764 }
9d5c8243 4765
eebbbdba
AD		 4766 for (i = 0; i < adapter->num_rx_queues; i++) {
4767 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4768 wr32(E1000_EIMC, rx_ring->eims_value);
4769 napi_schedule(&rx_ring->napi);
4770 }
9d5c8243
AK		 4771}
4772#endif /* CONFIG_NET_POLL_CONTROLLER */
4773
4774/**
4775 * igb_io_error_detected - called when PCI error is detected
4776 * @pdev: Pointer to PCI device
4777 * @state: The current pci connection state
4778 *
4779 * This function is called after a PCI bus error affecting
4780 * this device has been detected.
4781 */
4782static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4783 pci_channel_state_t state)
4784{
4785 struct net_device *netdev = pci_get_drvdata(pdev);
4786 struct igb_adapter *adapter = netdev_priv(netdev);
4787
4788 netif_device_detach(netdev);
4789
4790 if (netif_running(netdev))
4791 igb_down(adapter);
4792 pci_disable_device(pdev);
4793
4794 /* Request a slot slot reset. */
4795 return PCI_ERS_RESULT_NEED_RESET;
4796}
4797
4798/**
4799 * igb_io_slot_reset - called after the pci bus has been reset.
4800 * @pdev: Pointer to PCI device
4801 *
4802 * Restart the card from scratch, as if from a cold-boot. Implementation
4803 * resembles the first-half of the igb_resume routine.
4804 */
4805static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4806{
4807 struct net_device *netdev = pci_get_drvdata(pdev);
4808 struct igb_adapter *adapter = netdev_priv(netdev);
4809 struct e1000_hw *hw = &adapter->hw;
40a914fa 4810 pci_ers_result_t result;
42bfd33a 4811 int err;
9d5c8243 4812
aed5dec3 4813 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4814 dev_err(&pdev->dev,
4815 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4816 result = PCI_ERS_RESULT_DISCONNECT;
4817 } else {
4818 pci_set_master(pdev);
4819 pci_restore_state(pdev);
9d5c8243 4820
40a914fa
AD		 4821 pci_enable_wake(pdev, PCI_D3hot, 0);
4822 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4823
40a914fa
AD		 4824 igb_reset(adapter);
4825 wr32(E1000_WUS, ~0);
4826 result = PCI_ERS_RESULT_RECOVERED;
4827 }
9d5c8243 4828
ea943d41
JK		 4829 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4830 if (err) {
4831 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4832 "failed 0x%0x\n", err);
4833 /* non-fatal, continue */
4834 }
40a914fa
AD		 4835
4836 return result;
9d5c8243
AK		 4837}
4838
4839/**
4840 * igb_io_resume - called when traffic can start flowing again.
4841 * @pdev: Pointer to PCI device
4842 *
4843 * This callback is called when the error recovery driver tells us that
4844 * its OK to resume normal operation. Implementation resembles the
4845 * second-half of the igb_resume routine.
4846 */
4847static void igb_io_resume(struct pci_dev *pdev)
4848{
4849 struct net_device *netdev = pci_get_drvdata(pdev);
4850 struct igb_adapter *adapter = netdev_priv(netdev);
4851
9d5c8243
AK		 4852 if (netif_running(netdev)) {
4853 if (igb_up(adapter)) {
4854 dev_err(&pdev->dev, "igb_up failed after reset\n");
4855 return;
4856 }
4857 }
4858
4859 netif_device_attach(netdev);
4860
4861 /* let the f/w know that the h/w is now under the control of the
4862 * driver. */
4863 igb_get_hw_control(adapter);
9d5c8243
AK		 4864}
4865
4866/* igb_main.c */
Linux kernel - Deliverables
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