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igb: increase minimum rx buffer size to 1K
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
93static void igb_setup_rctl(struct igb_adapter *);
94static void igb_clean_all_tx_rings(struct igb_adapter *);
95static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 96static void igb_clean_tx_ring(struct igb_ring *);
97static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 98static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 99static void igb_update_phy_info(unsigned long);
100static void igb_watchdog(unsigned long);
101static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 102static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
103 struct net_device *,
104 struct igb_ring *);
105static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
106 struct net_device *);
9d5c8243
AK		 107static struct net_device_stats *igb_get_stats(struct net_device *);
108static int igb_change_mtu(struct net_device *, int);
109static int igb_set_mac(struct net_device *, void *);
68d480c4 110static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 111static irqreturn_t igb_intr(int irq, void *);
112static irqreturn_t igb_intr_msi(int irq, void *);
113static irqreturn_t igb_msix_other(int irq, void *);
047e0030 114static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 115#ifdef CONFIG_IGB_DCA
047e0030 116static void igb_update_dca(struct igb_q_vector *);
fe4506b6 117static void igb_setup_dca(struct igb_adapter *);
421e02f0 118#endif /* CONFIG_IGB_DCA */
047e0030 119static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 120static int igb_poll(struct napi_struct *, int);
047e0030 121static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
3b644cf6 122static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
26ad9178 130static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 131static void igb_ping_all_vfs(struct igb_adapter *);
132static void igb_msg_task(struct igb_adapter *);
133static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 134static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 135static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 137
c8159b2d
ED		 138static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
139{
140 u32 reg_data;
141
142 reg_data = rd32(E1000_VMOLR(vfn));
143 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 144 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
145 E1000_VMOLR_AUPE | /* Accept untagged packets */
146 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
147 wr32(E1000_VMOLR(vfn), reg_data);
148}
149
150static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
151 int vfn)
152{
153 struct e1000_hw *hw = &adapter->hw;
154 u32 vmolr;
155
ae641bdc
AD		 156 /* if it isn't the PF check to see if VFs are enabled and
157 * increase the size to support vlan tags */
158 if (vfn < adapter->vfs_allocated_count &&
159 adapter->vf_data[vfn].vlans_enabled)
160 size += VLAN_TAG_SIZE;
161
c8159b2d
ED		 162 vmolr = rd32(E1000_VMOLR(vfn));
163 vmolr &= ~E1000_VMOLR_RLPML_MASK;
164 vmolr |= size | E1000_VMOLR_LPE;
165 wr32(E1000_VMOLR(vfn), vmolr);
166
167 return 0;
168}
169
9d5c8243 170#ifdef CONFIG_PM
3fe7c4c9 171static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 172static int igb_resume(struct pci_dev *);
173#endif
174static void igb_shutdown(struct pci_dev *);
421e02f0 175#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 176static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
177static struct notifier_block dca_notifier = {
178 .notifier_call = igb_notify_dca,
179 .next = NULL,
180 .priority = 0
181};
182#endif
9d5c8243
AK		 183#ifdef CONFIG_NET_POLL_CONTROLLER
184/* for netdump / net console */
185static void igb_netpoll(struct net_device *);
186#endif
37680117 187#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 188static unsigned int max_vfs = 0;
189module_param(max_vfs, uint, 0);
190MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
191 "per physical function");
192#endif /* CONFIG_PCI_IOV */
193
9d5c8243
AK		 194static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
195 pci_channel_state_t);
196static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
197static void igb_io_resume(struct pci_dev *);
198
199static struct pci_error_handlers igb_err_handler = {
200 .error_detected = igb_io_error_detected,
201 .slot_reset = igb_io_slot_reset,
202 .resume = igb_io_resume,
203};
204
205
206static struct pci_driver igb_driver = {
207 .name = igb_driver_name,
208 .id_table = igb_pci_tbl,
209 .probe = igb_probe,
210 .remove = __devexit_p(igb_remove),
211#ifdef CONFIG_PM
212 /* Power Managment Hooks */
213 .suspend = igb_suspend,
214 .resume = igb_resume,
215#endif
216 .shutdown = igb_shutdown,
217 .err_handler = &igb_err_handler
218};
219
7dfc16fa
AD		 220static int global_quad_port_a; /* global quad port a indication */
221
9d5c8243
AK		 222MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
223MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_VERSION);
226
38c845c7
PO		 227/**
228 * Scale the NIC clock cycle by a large factor so that
229 * relatively small clock corrections can be added or
230 * substracted at each clock tick. The drawbacks of a
231 * large factor are a) that the clock register overflows
232 * more quickly (not such a big deal) and b) that the
233 * increment per tick has to fit into 24 bits.
234 *
235 * Note that
236 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
237 * IGB_TSYNC_SCALE
238 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
239 *
240 * The base scale factor is intentionally a power of two
241 * so that the division in %struct timecounter can be done with
242 * a shift.
243 */
244#define IGB_TSYNC_SHIFT (19)
245#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
246
247/**
248 * The duration of one clock cycle of the NIC.
249 *
250 * @todo This hard-coded value is part of the specification and might change
251 * in future hardware revisions. Add revision check.
252 */
253#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
254
255#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
256# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
257#endif
258
259/**
260 * igb_read_clock - read raw cycle counter (to be used by time counter)
261 */
262static cycle_t igb_read_clock(const struct cyclecounter *tc)
263{
264 struct igb_adapter *adapter =
265 container_of(tc, struct igb_adapter, cycles);
266 struct e1000_hw *hw = &adapter->hw;
267 u64 stamp;
268
269 stamp = rd32(E1000_SYSTIML);
270 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
271
272 return stamp;
273}
274
9d5c8243
AK		 275#ifdef DEBUG
276/**
277 * igb_get_hw_dev_name - return device name string
278 * used by hardware layer to print debugging information
279 **/
280char *igb_get_hw_dev_name(struct e1000_hw *hw)
281{
282 struct igb_adapter *adapter = hw->back;
283 return adapter->netdev->name;
284}
38c845c7
PO		 285
286/**
287 * igb_get_time_str - format current NIC and system time as string
288 */
289static char *igb_get_time_str(struct igb_adapter *adapter,
290 char buffer[160])
291{
292 cycle_t hw = adapter->cycles.read(&adapter->cycles);
293 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
294 struct timespec sys;
295 struct timespec delta;
296 getnstimeofday(&sys);
297
298 delta = timespec_sub(nic, sys);
299
300 sprintf(buffer,
33af6bcc
PO		 301 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
302 hw,
38c845c7
PO		 303 (long)nic.tv_sec, nic.tv_nsec,
304 (long)sys.tv_sec, sys.tv_nsec,
305 (long)delta.tv_sec, delta.tv_nsec);
306
307 return buffer;
308}
9d5c8243
AK		 309#endif
310
c493ea45
AD		 311/**
312 * igb_desc_unused - calculate if we have unused descriptors
313 **/
314static int igb_desc_unused(struct igb_ring *ring)
315{
316 if (ring->next_to_clean > ring->next_to_use)
317 return ring->next_to_clean - ring->next_to_use - 1;
318
319 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
320}
321
9d5c8243
AK		 322/**
323 * igb_init_module - Driver Registration Routine
324 *
325 * igb_init_module is the first routine called when the driver is
326 * loaded. All it does is register with the PCI subsystem.
327 **/
328static int __init igb_init_module(void)
329{
330 int ret;
331 printk(KERN_INFO "%s - version %s\n",
332 igb_driver_string, igb_driver_version);
333
334 printk(KERN_INFO "%s\n", igb_copyright);
335
7dfc16fa
AD		 336 global_quad_port_a = 0;
337
421e02f0 338#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 339 dca_register_notify(&dca_notifier);
340#endif
bbd98fe4
AD		 341
342 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 343 return ret;
344}
345
346module_init(igb_init_module);
347
348/**
349 * igb_exit_module - Driver Exit Cleanup Routine
350 *
351 * igb_exit_module is called just before the driver is removed
352 * from memory.
353 **/
354static void __exit igb_exit_module(void)
355{
421e02f0 356#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 357 dca_unregister_notify(&dca_notifier);
358#endif
9d5c8243
AK		 359 pci_unregister_driver(&igb_driver);
360}
361
362module_exit(igb_exit_module);
363
26bc19ec
AD		 364#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
365/**
366 * igb_cache_ring_register - Descriptor ring to register mapping
367 * @adapter: board private structure to initialize
368 *
369 * Once we know the feature-set enabled for the device, we'll cache
370 * the register offset the descriptor ring is assigned to.
371 **/
372static void igb_cache_ring_register(struct igb_adapter *adapter)
373{
374 int i;
047e0030 375 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 376
377 switch (adapter->hw.mac.type) {
378 case e1000_82576:
379 /* The queues are allocated for virtualization such that VF 0
380 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
381 * In order to avoid collision we start at the first free queue
382 * and continue consuming queues in the same sequence
383 */
384 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 385 adapter->rx_ring[i].reg_idx = rbase_offset +
386 Q_IDX_82576(i);
26bc19ec 387 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 388 adapter->tx_ring[i].reg_idx = rbase_offset +
389 Q_IDX_82576(i);
26bc19ec
AD		 390 break;
391 case e1000_82575:
392 default:
393 for (i = 0; i < adapter->num_rx_queues; i++)
394 adapter->rx_ring[i].reg_idx = i;
395 for (i = 0; i < adapter->num_tx_queues; i++)
396 adapter->tx_ring[i].reg_idx = i;
397 break;
398 }
399}
400
047e0030
AD		 401static void igb_free_queues(struct igb_adapter *adapter)
402{
403 kfree(adapter->tx_ring);
404 kfree(adapter->rx_ring);
405
406 adapter->tx_ring = NULL;
407 adapter->rx_ring = NULL;
408
409 adapter->num_rx_queues = 0;
410 adapter->num_tx_queues = 0;
411}
412
9d5c8243
AK		 413/**
414 * igb_alloc_queues - Allocate memory for all rings
415 * @adapter: board private structure to initialize
416 *
417 * We allocate one ring per queue at run-time since we don't know the
418 * number of queues at compile-time.
419 **/
420static int igb_alloc_queues(struct igb_adapter *adapter)
421{
422 int i;
423
424 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
425 sizeof(struct igb_ring), GFP_KERNEL);
426 if (!adapter->tx_ring)
047e0030 427 goto err;
9d5c8243
AK		 428
429 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
430 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 431 if (!adapter->rx_ring)
432 goto err;
6eb5a7f1 433
661086df
PWJ		 434 for (i = 0; i < adapter->num_tx_queues; i++) {
435 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 436 ring->count = adapter->tx_ring_count;
661086df
PWJ		 437 ring->queue_index = i;
438 }
9d5c8243
AK		 439 for (i = 0; i < adapter->num_rx_queues; i++) {
440 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 441 ring->count = adapter->rx_ring_count;
844290e5 442 ring->queue_index = i;
9d5c8243 443 }
26bc19ec
AD		 444
445 igb_cache_ring_register(adapter);
9d5c8243 446
047e0030 447 return 0;
a88f10ec 448
047e0030
AD		 449err:
450 igb_free_queues(adapter);
d1a8c9e1 451
047e0030 452 return -ENOMEM;
a88f10ec
AD		 453}
454
9d5c8243 455#define IGB_N0_QUEUE -1
047e0030 456static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 457{
458 u32 msixbm = 0;
047e0030 459 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 460 struct e1000_hw *hw = &adapter->hw;
2d064c06 461 u32 ivar, index;
047e0030
AD		 462 int rx_queue = IGB_N0_QUEUE;
463 int tx_queue = IGB_N0_QUEUE;
464
465 if (q_vector->rx_ring)
466 rx_queue = q_vector->rx_ring->reg_idx;
467 if (q_vector->tx_ring)
468 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 469
470 switch (hw->mac.type) {
471 case e1000_82575:
9d5c8243
AK		 472 /* The 82575 assigns vectors using a bitmask, which matches the
473 bitmask for the EICR/EIMS/EIMC registers. To assign one
474 or more queues to a vector, we write the appropriate bits
475 into the MSIXBM register for that vector. */
047e0030 476 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 477 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 478 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 479 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 480 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 481 q_vector->eims_value = msixbm;
2d064c06
AD		 482 break;
483 case e1000_82576:
26bc19ec 484 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 485 Each queue has a single entry in the table to which we write
486 a vector number along with a "valid" bit. Sadly, the layout
487 of the table is somewhat counterintuitive. */
488 if (rx_queue > IGB_N0_QUEUE) {
047e0030 489 index = (rx_queue & 0x7);
2d064c06 490 ivar = array_rd32(E1000_IVAR0, index);
047e0030 491 if (rx_queue < 8) {
26bc19ec
AD		 492 /* vector goes into low byte of register */
493 ivar = ivar & 0xFFFFFF00;
494 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 495 } else {
496 /* vector goes into third byte of register */
497 ivar = ivar & 0xFF00FFFF;
498 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 499 }
2d064c06
AD		 500 array_wr32(E1000_IVAR0, index, ivar);
501 }
502 if (tx_queue > IGB_N0_QUEUE) {
047e0030 503 index = (tx_queue & 0x7);
2d064c06 504 ivar = array_rd32(E1000_IVAR0, index);
047e0030 505 if (tx_queue < 8) {
26bc19ec
AD		 506 /* vector goes into second byte of register */
507 ivar = ivar & 0xFFFF00FF;
508 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 509 } else {
510 /* vector goes into high byte of register */
511 ivar = ivar & 0x00FFFFFF;
512 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 513 }
2d064c06
AD		 514 array_wr32(E1000_IVAR0, index, ivar);
515 }
047e0030 516 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 517 break;
518 default:
519 BUG();
520 break;
521 }
9d5c8243
AK		 522}
523
524/**
525 * igb_configure_msix - Configure MSI-X hardware
526 *
527 * igb_configure_msix sets up the hardware to properly
528 * generate MSI-X interrupts.
529 **/
530static void igb_configure_msix(struct igb_adapter *adapter)
531{
532 u32 tmp;
533 int i, vector = 0;
534 struct e1000_hw *hw = &adapter->hw;
535
536 adapter->eims_enable_mask = 0;
9d5c8243
AK		 537
538 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 539 switch (hw->mac.type) {
540 case e1000_82575:
9d5c8243
AK		 541 tmp = rd32(E1000_CTRL_EXT);
542 /* enable MSI-X PBA support*/
543 tmp |= E1000_CTRL_EXT_PBA_CLR;
544
545 /* Auto-Mask interrupts upon ICR read. */
546 tmp |= E1000_CTRL_EXT_EIAME;
547 tmp |= E1000_CTRL_EXT_IRCA;
548
549 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 550
551 /* enable msix_other interrupt */
552 array_wr32(E1000_MSIXBM(0), vector++,
553 E1000_EIMS_OTHER);
844290e5 554 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 555
2d064c06
AD		 556 break;
557
558 case e1000_82576:
047e0030
AD		 559 /* Turn on MSI-X capability first, or our settings
560 * won't stick. And it will take days to debug. */
561 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
562 E1000_GPIE_PBA | E1000_GPIE_EIAME |
563 E1000_GPIE_NSICR);
564
565 /* enable msix_other interrupt */
566 adapter->eims_other = 1 << vector;
2d064c06 567 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 568
047e0030 569 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 570 break;
571 default:
572 /* do nothing, since nothing else supports MSI-X */
573 break;
574 } /* switch (hw->mac.type) */
047e0030
AD		 575
576 adapter->eims_enable_mask |= adapter->eims_other;
577
578 for (i = 0; i < adapter->num_q_vectors; i++) {
579 struct igb_q_vector *q_vector = adapter->q_vector[i];
580 igb_assign_vector(q_vector, vector++);
581 adapter->eims_enable_mask |= q_vector->eims_value;
582 }
583
9d5c8243
AK		 584 wrfl();
585}
586
587/**
588 * igb_request_msix - Initialize MSI-X interrupts
589 *
590 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
591 * kernel.
592 **/
593static int igb_request_msix(struct igb_adapter *adapter)
594{
595 struct net_device *netdev = adapter->netdev;
047e0030 596 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 597 int i, err = 0, vector = 0;
598
047e0030
AD		 599 err = request_irq(adapter->msix_entries[vector].vector,
600 &igb_msix_other, 0, netdev->name, adapter);
601 if (err)
602 goto out;
603 vector++;
604
605 for (i = 0; i < adapter->num_q_vectors; i++) {
606 struct igb_q_vector *q_vector = adapter->q_vector[i];
607
608 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
609
610 if (q_vector->rx_ring && q_vector->tx_ring)
611 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
612 q_vector->rx_ring->queue_index);
613 else if (q_vector->tx_ring)
614 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
615 q_vector->tx_ring->queue_index);
616 else if (q_vector->rx_ring)
617 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
618 q_vector->rx_ring->queue_index);
9d5c8243 619 else
047e0030
AD		 620 sprintf(q_vector->name, "%s-unused", netdev->name);
621
9d5c8243 622 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 623 &igb_msix_ring, 0, q_vector->name,
624 q_vector);
9d5c8243
AK		 625 if (err)
626 goto out;
9d5c8243
AK		 627 vector++;
628 }
629
9d5c8243
AK		 630 igb_configure_msix(adapter);
631 return 0;
632out:
633 return err;
634}
635
636static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
637{
638 if (adapter->msix_entries) {
639 pci_disable_msix(adapter->pdev);
640 kfree(adapter->msix_entries);
641 adapter->msix_entries = NULL;
047e0030 642 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 643 pci_disable_msi(adapter->pdev);
047e0030 644 }
9d5c8243
AK		 645}
646
047e0030
AD		 647/**
648 * igb_free_q_vectors - Free memory allocated for interrupt vectors
649 * @adapter: board private structure to initialize
650 *
651 * This function frees the memory allocated to the q_vectors. In addition if
652 * NAPI is enabled it will delete any references to the NAPI struct prior
653 * to freeing the q_vector.
654 **/
655static void igb_free_q_vectors(struct igb_adapter *adapter)
656{
657 int v_idx;
658
659 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
660 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
661 adapter->q_vector[v_idx] = NULL;
662 netif_napi_del(&q_vector->napi);
663 kfree(q_vector);
664 }
665 adapter->num_q_vectors = 0;
666}
667
668/**
669 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
670 *
671 * This function resets the device so that it has 0 rx queues, tx queues, and
672 * MSI-X interrupts allocated.
673 */
674static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
675{
676 igb_free_queues(adapter);
677 igb_free_q_vectors(adapter);
678 igb_reset_interrupt_capability(adapter);
679}
9d5c8243
AK		 680
681/**
682 * igb_set_interrupt_capability - set MSI or MSI-X if supported
683 *
684 * Attempt to configure interrupts using the best available
685 * capabilities of the hardware and kernel.
686 **/
687static void igb_set_interrupt_capability(struct igb_adapter *adapter)
688{
689 int err;
690 int numvecs, i;
691
83b7180d 692 /* Number of supported queues. */
83b7180d
AD		 693 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
694 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
695
047e0030
AD		 696 /* start with one vector for every rx queue */
697 numvecs = adapter->num_rx_queues;
698
699 /* if tx handler is seperate add 1 for every tx queue */
700 numvecs += adapter->num_tx_queues;
701
702 /* store the number of vectors reserved for queues */
703 adapter->num_q_vectors = numvecs;
704
705 /* add 1 vector for link status interrupts */
706 numvecs++;
9d5c8243
AK		 707 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
708 GFP_KERNEL);
709 if (!adapter->msix_entries)
710 goto msi_only;
711
712 for (i = 0; i < numvecs; i++)
713 adapter->msix_entries[i].entry = i;
714
715 err = pci_enable_msix(adapter->pdev,
716 adapter->msix_entries,
717 numvecs);
718 if (err == 0)
34a20e89 719 goto out;
9d5c8243
AK		 720
721 igb_reset_interrupt_capability(adapter);
722
723 /* If we can't do MSI-X, try MSI */
724msi_only:
2a3abf6d
AD		 725#ifdef CONFIG_PCI_IOV
726 /* disable SR-IOV for non MSI-X configurations */
727 if (adapter->vf_data) {
728 struct e1000_hw *hw = &adapter->hw;
729 /* disable iov and allow time for transactions to clear */
730 pci_disable_sriov(adapter->pdev);
731 msleep(500);
732
733 kfree(adapter->vf_data);
734 adapter->vf_data = NULL;
735 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
736 msleep(100);
737 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
738 }
739#endif
9d5c8243 740 adapter->num_rx_queues = 1;
661086df 741 adapter->num_tx_queues = 1;
047e0030 742 adapter->num_q_vectors = 1;
9d5c8243 743 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 744 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 745out:
661086df 746 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 747 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 748 return;
749}
750
047e0030
AD		 751/**
752 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
753 * @adapter: board private structure to initialize
754 *
755 * We allocate one q_vector per queue interrupt. If allocation fails we
756 * return -ENOMEM.
757 **/
758static int igb_alloc_q_vectors(struct igb_adapter *adapter)
759{
760 struct igb_q_vector *q_vector;
761 struct e1000_hw *hw = &adapter->hw;
762 int v_idx;
763
764 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
765 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
766 if (!q_vector)
767 goto err_out;
768 q_vector->adapter = adapter;
769 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
770 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
771 q_vector->itr_val = IGB_START_ITR;
772 q_vector->set_itr = 1;
773 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
774 adapter->q_vector[v_idx] = q_vector;
775 }
776 return 0;
777
778err_out:
779 while (v_idx) {
780 v_idx--;
781 q_vector = adapter->q_vector[v_idx];
782 netif_napi_del(&q_vector->napi);
783 kfree(q_vector);
784 adapter->q_vector[v_idx] = NULL;
785 }
786 return -ENOMEM;
787}
788
789static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
790 int ring_idx, int v_idx)
791{
792 struct igb_q_vector *q_vector;
793
794 q_vector = adapter->q_vector[v_idx];
795 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
796 q_vector->rx_ring->q_vector = q_vector;
797 q_vector->itr_val = adapter->itr;
798}
799
800static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
801 int ring_idx, int v_idx)
802{
803 struct igb_q_vector *q_vector;
804
805 q_vector = adapter->q_vector[v_idx];
806 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
807 q_vector->tx_ring->q_vector = q_vector;
808 q_vector->itr_val = adapter->itr;
809}
810
811/**
812 * igb_map_ring_to_vector - maps allocated queues to vectors
813 *
814 * This function maps the recently allocated queues to vectors.
815 **/
816static int igb_map_ring_to_vector(struct igb_adapter *adapter)
817{
818 int i;
819 int v_idx = 0;
820
821 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
822 (adapter->num_q_vectors < adapter->num_tx_queues))
823 return -ENOMEM;
824
825 if (adapter->num_q_vectors >=
826 (adapter->num_rx_queues + adapter->num_tx_queues)) {
827 for (i = 0; i < adapter->num_rx_queues; i++)
828 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
829 for (i = 0; i < adapter->num_tx_queues; i++)
830 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
831 } else {
832 for (i = 0; i < adapter->num_rx_queues; i++) {
833 if (i < adapter->num_tx_queues)
834 igb_map_tx_ring_to_vector(adapter, i, v_idx);
835 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
836 }
837 for (; i < adapter->num_tx_queues; i++)
838 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
839 }
840 return 0;
841}
842
843/**
844 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
845 *
846 * This function initializes the interrupts and allocates all of the queues.
847 **/
848static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
849{
850 struct pci_dev *pdev = adapter->pdev;
851 int err;
852
853 igb_set_interrupt_capability(adapter);
854
855 err = igb_alloc_q_vectors(adapter);
856 if (err) {
857 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
858 goto err_alloc_q_vectors;
859 }
860
861 err = igb_alloc_queues(adapter);
862 if (err) {
863 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
864 goto err_alloc_queues;
865 }
866
867 err = igb_map_ring_to_vector(adapter);
868 if (err) {
869 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
870 goto err_map_queues;
871 }
872
873
874 return 0;
875err_map_queues:
876 igb_free_queues(adapter);
877err_alloc_queues:
878 igb_free_q_vectors(adapter);
879err_alloc_q_vectors:
880 igb_reset_interrupt_capability(adapter);
881 return err;
882}
883
9d5c8243
AK		 884/**
885 * igb_request_irq - initialize interrupts
886 *
887 * Attempts to configure interrupts using the best available
888 * capabilities of the hardware and kernel.
889 **/
890static int igb_request_irq(struct igb_adapter *adapter)
891{
892 struct net_device *netdev = adapter->netdev;
047e0030 893 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 894 struct e1000_hw *hw = &adapter->hw;
895 int err = 0;
896
897 if (adapter->msix_entries) {
898 err = igb_request_msix(adapter);
844290e5 899 if (!err)
9d5c8243 900 goto request_done;
9d5c8243 901 /* fall back to MSI */
047e0030 902 igb_clear_interrupt_scheme(adapter);
9d5c8243 903 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 904 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 905 igb_free_all_tx_resources(adapter);
906 igb_free_all_rx_resources(adapter);
047e0030 907 adapter->num_tx_queues = 1;
9d5c8243 908 adapter->num_rx_queues = 1;
047e0030
AD		 909 adapter->num_q_vectors = 1;
910 err = igb_alloc_q_vectors(adapter);
911 if (err) {
912 dev_err(&pdev->dev,
913 "Unable to allocate memory for vectors\n");
914 goto request_done;
915 }
916 err = igb_alloc_queues(adapter);
917 if (err) {
918 dev_err(&pdev->dev,
919 "Unable to allocate memory for queues\n");
920 igb_free_q_vectors(adapter);
921 goto request_done;
922 }
923 igb_setup_all_tx_resources(adapter);
924 igb_setup_all_rx_resources(adapter);
844290e5 925 } else {
2d064c06
AD		 926 switch (hw->mac.type) {
927 case e1000_82575:
928 wr32(E1000_MSIXBM(0),
047e0030
AD		 929 (E1000_EICR_RX_QUEUE0 |
930 E1000_EICR_TX_QUEUE0 |
931 E1000_EIMS_OTHER));
2d064c06
AD		 932 break;
933 case e1000_82576:
934 wr32(E1000_IVAR0, E1000_IVAR_VALID);
935 break;
936 default:
937 break;
938 }
9d5c8243 939 }
844290e5 940
7dfc16fa 941 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 942 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 943 netdev->name, adapter);
9d5c8243
AK		 944 if (!err)
945 goto request_done;
047e0030 946
9d5c8243
AK		 947 /* fall back to legacy interrupts */
948 igb_reset_interrupt_capability(adapter);
7dfc16fa 949 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 950 }
951
952 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 953 netdev->name, adapter);
9d5c8243 954
6cb5e577 955 if (err)
9d5c8243
AK		 956 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
957 err);
9d5c8243
AK		 958
959request_done:
960 return err;
961}
962
963static void igb_free_irq(struct igb_adapter *adapter)
964{
9d5c8243
AK		 965 if (adapter->msix_entries) {
966 int vector = 0, i;
967
047e0030 968 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 969
047e0030
AD		 970 for (i = 0; i < adapter->num_q_vectors; i++) {
971 struct igb_q_vector *q_vector = adapter->q_vector[i];
972 free_irq(adapter->msix_entries[vector++].vector,
973 q_vector);
974 }
975 } else {
976 free_irq(adapter->pdev->irq, adapter);
9d5c8243 977 }
9d5c8243
AK		 978}
979
980/**
981 * igb_irq_disable - Mask off interrupt generation on the NIC
982 * @adapter: board private structure
983 **/
984static void igb_irq_disable(struct igb_adapter *adapter)
985{
986 struct e1000_hw *hw = &adapter->hw;
987
988 if (adapter->msix_entries) {
2dfd1212
AD		 989 u32 regval = rd32(E1000_EIAM);
990 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
991 wr32(E1000_EIMC, adapter->eims_enable_mask);
992 regval = rd32(E1000_EIAC);
993 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 994 }
844290e5
PW		 995
996 wr32(E1000_IAM, 0);
9d5c8243
AK		 997 wr32(E1000_IMC, ~0);
998 wrfl();
999 synchronize_irq(adapter->pdev->irq);
1000}
1001
1002/**
1003 * igb_irq_enable - Enable default interrupt generation settings
1004 * @adapter: board private structure
1005 **/
1006static void igb_irq_enable(struct igb_adapter *adapter)
1007{
1008 struct e1000_hw *hw = &adapter->hw;
1009
1010 if (adapter->msix_entries) {
2dfd1212
AD		 1011 u32 regval = rd32(E1000_EIAC);
1012 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1013 regval = rd32(E1000_EIAM);
1014 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1015 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 1016 if (adapter->vfs_allocated_count)
1017 wr32(E1000_MBVFIMR, 0xFF);
1018 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
1019 E1000_IMS_DOUTSYNC));
844290e5
PW		 1020 } else {
1021 wr32(E1000_IMS, IMS_ENABLE_MASK);
1022 wr32(E1000_IAM, IMS_ENABLE_MASK);
1023 }
9d5c8243
AK		 1024}
1025
1026static void igb_update_mng_vlan(struct igb_adapter *adapter)
1027{
1028 struct net_device *netdev = adapter->netdev;
1029 u16 vid = adapter->hw.mng_cookie.vlan_id;
1030 u16 old_vid = adapter->mng_vlan_id;
1031 if (adapter->vlgrp) {
1032 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
1033 if (adapter->hw.mng_cookie.status &
1034 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1035 igb_vlan_rx_add_vid(netdev, vid);
1036 adapter->mng_vlan_id = vid;
1037 } else
1038 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1039
1040 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1041 (vid != old_vid) &&
1042 !vlan_group_get_device(adapter->vlgrp, old_vid))
1043 igb_vlan_rx_kill_vid(netdev, old_vid);
1044 } else
1045 adapter->mng_vlan_id = vid;
1046 }
1047}
1048
1049/**
1050 * igb_release_hw_control - release control of the h/w to f/w
1051 * @adapter: address of board private structure
1052 *
1053 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1054 * For ASF and Pass Through versions of f/w this means that the
1055 * driver is no longer loaded.
1056 *
1057 **/
1058static void igb_release_hw_control(struct igb_adapter *adapter)
1059{
1060 struct e1000_hw *hw = &adapter->hw;
1061 u32 ctrl_ext;
1062
1063 /* Let firmware take over control of h/w */
1064 ctrl_ext = rd32(E1000_CTRL_EXT);
1065 wr32(E1000_CTRL_EXT,
1066 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1067}
1068
1069
1070/**
1071 * igb_get_hw_control - get control of the h/w from f/w
1072 * @adapter: address of board private structure
1073 *
1074 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1075 * For ASF and Pass Through versions of f/w this means that
1076 * the driver is loaded.
1077 *
1078 **/
1079static void igb_get_hw_control(struct igb_adapter *adapter)
1080{
1081 struct e1000_hw *hw = &adapter->hw;
1082 u32 ctrl_ext;
1083
1084 /* Let firmware know the driver has taken over */
1085 ctrl_ext = rd32(E1000_CTRL_EXT);
1086 wr32(E1000_CTRL_EXT,
1087 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1088}
1089
9d5c8243
AK		 1090/**
1091 * igb_configure - configure the hardware for RX and TX
1092 * @adapter: private board structure
1093 **/
1094static void igb_configure(struct igb_adapter *adapter)
1095{
1096 struct net_device *netdev = adapter->netdev;
1097 int i;
1098
1099 igb_get_hw_control(adapter);
ff41f8dc 1100 igb_set_rx_mode(netdev);
9d5c8243
AK		 1101
1102 igb_restore_vlan(adapter);
9d5c8243
AK		 1103
1104 igb_configure_tx(adapter);
1105 igb_setup_rctl(adapter);
1106 igb_configure_rx(adapter);
662d7205
AD		 1107
1108 igb_rx_fifo_flush_82575(&adapter->hw);
1109
c493ea45 1110 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1111 * at least 1 descriptor unused to make sure
1112 * next_to_use != next_to_clean */
1113 for (i = 0; i < adapter->num_rx_queues; i++) {
1114 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1115 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1116 }
1117
1118
1119 adapter->tx_queue_len = netdev->tx_queue_len;
1120}
1121
1122
1123/**
1124 * igb_up - Open the interface and prepare it to handle traffic
1125 * @adapter: board private structure
1126 **/
1127
1128int igb_up(struct igb_adapter *adapter)
1129{
1130 struct e1000_hw *hw = &adapter->hw;
1131 int i;
1132
1133 /* hardware has been reset, we need to reload some things */
1134 igb_configure(adapter);
1135
1136 clear_bit(__IGB_DOWN, &adapter->state);
1137
047e0030
AD		 1138 for (i = 0; i < adapter->num_q_vectors; i++) {
1139 struct igb_q_vector *q_vector = adapter->q_vector[i];
1140 napi_enable(&q_vector->napi);
1141 }
844290e5 1142 if (adapter->msix_entries)
9d5c8243 1143 igb_configure_msix(adapter);
9d5c8243 1144
4ae196df 1145 igb_vmm_control(adapter);
e1739522
AD		 1146 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1147
9d5c8243
AK		 1148 /* Clear any pending interrupts. */
1149 rd32(E1000_ICR);
1150 igb_irq_enable(adapter);
1151
4cb9be7a
JB		 1152 netif_tx_start_all_queues(adapter->netdev);
1153
9d5c8243
AK		 1154 /* Fire a link change interrupt to start the watchdog. */
1155 wr32(E1000_ICS, E1000_ICS_LSC);
1156 return 0;
1157}
1158
1159void igb_down(struct igb_adapter *adapter)
1160{
1161 struct e1000_hw *hw = &adapter->hw;
1162 struct net_device *netdev = adapter->netdev;
1163 u32 tctl, rctl;
1164 int i;
1165
1166 /* signal that we're down so the interrupt handler does not
1167 * reschedule our watchdog timer */
1168 set_bit(__IGB_DOWN, &adapter->state);
1169
1170 /* disable receives in the hardware */
1171 rctl = rd32(E1000_RCTL);
1172 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1173 /* flush and sleep below */
1174
fd2ea0a7 1175 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1176
1177 /* disable transmits in the hardware */
1178 tctl = rd32(E1000_TCTL);
1179 tctl &= ~E1000_TCTL_EN;
1180 wr32(E1000_TCTL, tctl);
1181 /* flush both disables and wait for them to finish */
1182 wrfl();
1183 msleep(10);
1184
047e0030
AD		 1185 for (i = 0; i < adapter->num_q_vectors; i++) {
1186 struct igb_q_vector *q_vector = adapter->q_vector[i];
1187 napi_disable(&q_vector->napi);
1188 }
9d5c8243 1189
9d5c8243
AK		 1190 igb_irq_disable(adapter);
1191
1192 del_timer_sync(&adapter->watchdog_timer);
1193 del_timer_sync(&adapter->phy_info_timer);
1194
1195 netdev->tx_queue_len = adapter->tx_queue_len;
1196 netif_carrier_off(netdev);
04fe6358
AD		 1197
1198 /* record the stats before reset*/
1199 igb_update_stats(adapter);
1200
9d5c8243
AK		 1201 adapter->link_speed = 0;
1202 adapter->link_duplex = 0;
1203
3023682e
JK		 1204 if (!pci_channel_offline(adapter->pdev))
1205 igb_reset(adapter);
9d5c8243
AK		 1206 igb_clean_all_tx_rings(adapter);
1207 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1208#ifdef CONFIG_IGB_DCA
1209
1210 /* since we reset the hardware DCA settings were cleared */
1211 igb_setup_dca(adapter);
1212#endif
9d5c8243
AK		 1213}
1214
1215void igb_reinit_locked(struct igb_adapter *adapter)
1216{
1217 WARN_ON(in_interrupt());
1218 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1219 msleep(1);
1220 igb_down(adapter);
1221 igb_up(adapter);
1222 clear_bit(__IGB_RESETTING, &adapter->state);
1223}
1224
1225void igb_reset(struct igb_adapter *adapter)
1226{
1227 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1228 struct e1000_mac_info *mac = &hw->mac;
1229 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1230 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1231 u16 hwm;
1232
1233 /* Repartition Pba for greater than 9k mtu
1234 * To take effect CTRL.RST is required.
1235 */
fa4dfae0
AD		 1236 switch (mac->type) {
1237 case e1000_82576:
2d064c06 1238 pba = E1000_PBA_64K;
fa4dfae0
AD		 1239 break;
1240 case e1000_82575:
1241 default:
1242 pba = E1000_PBA_34K;
1243 break;
2d064c06 1244 }
9d5c8243 1245
2d064c06
AD		 1246 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1247 (mac->type < e1000_82576)) {
9d5c8243
AK		 1248 /* adjust PBA for jumbo frames */
1249 wr32(E1000_PBA, pba);
1250
1251 /* To maintain wire speed transmits, the Tx FIFO should be
1252 * large enough to accommodate two full transmit packets,
1253 * rounded up to the next 1KB and expressed in KB. Likewise,
1254 * the Rx FIFO should be large enough to accommodate at least
1255 * one full receive packet and is similarly rounded up and
1256 * expressed in KB. */
1257 pba = rd32(E1000_PBA);
1258 /* upper 16 bits has Tx packet buffer allocation size in KB */
1259 tx_space = pba >> 16;
1260 /* lower 16 bits has Rx packet buffer allocation size in KB */
1261 pba &= 0xffff;
1262 /* the tx fifo also stores 16 bytes of information about the tx
1263 * but don't include ethernet FCS because hardware appends it */
1264 min_tx_space = (adapter->max_frame_size +
85e8d004 1265 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1266 ETH_FCS_LEN) * 2;
1267 min_tx_space = ALIGN(min_tx_space, 1024);
1268 min_tx_space >>= 10;
1269 /* software strips receive CRC, so leave room for it */
1270 min_rx_space = adapter->max_frame_size;
1271 min_rx_space = ALIGN(min_rx_space, 1024);
1272 min_rx_space >>= 10;
1273
1274 /* If current Tx allocation is less than the min Tx FIFO size,
1275 * and the min Tx FIFO size is less than the current Rx FIFO
1276 * allocation, take space away from current Rx allocation */
1277 if (tx_space < min_tx_space &&
1278 ((min_tx_space - tx_space) < pba)) {
1279 pba = pba - (min_tx_space - tx_space);
1280
1281 /* if short on rx space, rx wins and must trump tx
1282 * adjustment */
1283 if (pba < min_rx_space)
1284 pba = min_rx_space;
1285 }
2d064c06 1286 wr32(E1000_PBA, pba);
9d5c8243 1287 }
9d5c8243
AK		 1288
1289 /* flow control settings */
1290 /* The high water mark must be low enough to fit one full frame
1291 * (or the size used for early receive) above it in the Rx FIFO.
1292 * Set it to the lower of:
1293 * - 90% of the Rx FIFO size, or
1294 * - the full Rx FIFO size minus one full frame */
1295 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1296 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1297
2d064c06
AD		 1298 if (mac->type < e1000_82576) {
1299 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1300 fc->low_water = fc->high_water - 8;
1301 } else {
1302 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1303 fc->low_water = fc->high_water - 16;
1304 }
9d5c8243
AK		 1305 fc->pause_time = 0xFFFF;
1306 fc->send_xon = 1;
0cce119a 1307 fc->current_mode = fc->requested_mode;
9d5c8243 1308
4ae196df
AD		 1309 /* disable receive for all VFs and wait one second */
1310 if (adapter->vfs_allocated_count) {
1311 int i;
1312 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1313 adapter->vf_data[i].clear_to_send = false;
1314
1315 /* ping all the active vfs to let them know we are going down */
1316 igb_ping_all_vfs(adapter);
1317
1318 /* disable transmits and receives */
1319 wr32(E1000_VFRE, 0);
1320 wr32(E1000_VFTE, 0);
1321 }
1322
9d5c8243
AK		 1323 /* Allow time for pending master requests to run */
1324 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1325 wr32(E1000_WUC, 0);
1326
1327 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1328 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1329
1330 igb_update_mng_vlan(adapter);
1331
1332 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1333 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1334
1335 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1336 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1337}
1338
2e5c6922
SH		 1339static const struct net_device_ops igb_netdev_ops = {
1340 .ndo_open = igb_open,
1341 .ndo_stop = igb_close,
00829823 1342 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1343 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1344 .ndo_set_rx_mode = igb_set_rx_mode,
1345 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1346 .ndo_set_mac_address = igb_set_mac,
1347 .ndo_change_mtu = igb_change_mtu,
1348 .ndo_do_ioctl = igb_ioctl,
1349 .ndo_tx_timeout = igb_tx_timeout,
1350 .ndo_validate_addr = eth_validate_addr,
1351 .ndo_vlan_rx_register = igb_vlan_rx_register,
1352 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1353 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1354#ifdef CONFIG_NET_POLL_CONTROLLER
1355 .ndo_poll_controller = igb_netpoll,
1356#endif
1357};
1358
9d5c8243
AK		 1359/**
1360 * igb_probe - Device Initialization Routine
1361 * @pdev: PCI device information struct
1362 * @ent: entry in igb_pci_tbl
1363 *
1364 * Returns 0 on success, negative on failure
1365 *
1366 * igb_probe initializes an adapter identified by a pci_dev structure.
1367 * The OS initialization, configuring of the adapter private structure,
1368 * and a hardware reset occur.
1369 **/
1370static int __devinit igb_probe(struct pci_dev *pdev,
1371 const struct pci_device_id *ent)
1372{
1373 struct net_device *netdev;
1374 struct igb_adapter *adapter;
1375 struct e1000_hw *hw;
1376 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1377 unsigned long mmio_start, mmio_len;
2d6a5e95 1378 int err, pci_using_dac;
682337fe 1379 u16 eeprom_data = 0;
9d5c8243
AK		 1380 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1381 u32 part_num;
1382
aed5dec3 1383 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1384 if (err)
1385 return err;
1386
1387 pci_using_dac = 0;
6a35528a 1388 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1389 if (!err) {
6a35528a 1390 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1391 if (!err)
1392 pci_using_dac = 1;
1393 } else {
284901a9 1394 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1395 if (err) {
284901a9 1396 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1397 if (err) {
1398 dev_err(&pdev->dev, "No usable DMA "
1399 "configuration, aborting\n");
1400 goto err_dma;
1401 }
1402 }
1403 }
1404
aed5dec3
AD		 1405 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1406 IORESOURCE_MEM),
1407 igb_driver_name);
9d5c8243
AK		 1408 if (err)
1409 goto err_pci_reg;
1410
19d5afd4 1411 pci_enable_pcie_error_reporting(pdev);
40a914fa 1412
9d5c8243 1413 pci_set_master(pdev);
c682fc23 1414 pci_save_state(pdev);
9d5c8243
AK		 1415
1416 err = -ENOMEM;
1bfaf07b
AD		 1417 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1418 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1419 if (!netdev)
1420 goto err_alloc_etherdev;
1421
1422 SET_NETDEV_DEV(netdev, &pdev->dev);
1423
1424 pci_set_drvdata(pdev, netdev);
1425 adapter = netdev_priv(netdev);
1426 adapter->netdev = netdev;
1427 adapter->pdev = pdev;
1428 hw = &adapter->hw;
1429 hw->back = adapter;
1430 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1431
1432 mmio_start = pci_resource_start(pdev, 0);
1433 mmio_len = pci_resource_len(pdev, 0);
1434
1435 err = -EIO;
28b0759c
AD		 1436 hw->hw_addr = ioremap(mmio_start, mmio_len);
1437 if (!hw->hw_addr)
9d5c8243
AK		 1438 goto err_ioremap;
1439
2e5c6922 1440 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1441 igb_set_ethtool_ops(netdev);
9d5c8243 1442 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1443
1444 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1445
1446 netdev->mem_start = mmio_start;
1447 netdev->mem_end = mmio_start + mmio_len;
1448
9d5c8243
AK		 1449 /* PCI config space info */
1450 hw->vendor_id = pdev->vendor;
1451 hw->device_id = pdev->device;
1452 hw->revision_id = pdev->revision;
1453 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1454 hw->subsystem_device_id = pdev->subsystem_device;
1455
1456 /* setup the private structure */
1457 hw->back = adapter;
1458 /* Copy the default MAC, PHY and NVM function pointers */
1459 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1460 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1461 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1462 /* Initialize skew-specific constants */
1463 err = ei->get_invariants(hw);
1464 if (err)
450c87c8 1465 goto err_sw_init;
9d5c8243 1466
2a3abf6d
AD		 1467#ifdef CONFIG_PCI_IOV
1468 /* since iov functionality isn't critical to base device function we
1469 * can accept failure. If it fails we don't allow iov to be enabled */
1470 if (hw->mac.type == e1000_82576) {
1471 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1472 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1473 int i;
1474 unsigned char mac_addr[ETH_ALEN];
1475
9ca046d5 1476 if (num_vfs) {
2a3abf6d
AD		 1477 adapter->vf_data = kcalloc(num_vfs,
1478 sizeof(struct vf_data_storage),
1479 GFP_KERNEL);
9ca046d5
AD		 1480 if (!adapter->vf_data) {
1481 dev_err(&pdev->dev,
1482 "Could not allocate VF private data - "
1483 "IOV enable failed\n");
2a3abf6d 1484 } else {
9ca046d5
AD		 1485 err = pci_enable_sriov(pdev, num_vfs);
1486 if (!err) {
1487 adapter->vfs_allocated_count = num_vfs;
1488 dev_info(&pdev->dev,
1489 "%d vfs allocated\n",
1490 num_vfs);
1491 for (i = 0;
1492 i < adapter->vfs_allocated_count;
1493 i++) {
1494 random_ether_addr(mac_addr);
1495 igb_set_vf_mac(adapter, i,
1496 mac_addr);
1497 }
1498 } else {
1499 kfree(adapter->vf_data);
1500 adapter->vf_data = NULL;
1501 }
2a3abf6d
AD		 1502 }
1503 }
1504 }
1505
1506#endif
450c87c8 1507 /* setup the private structure */
9d5c8243
AK		 1508 err = igb_sw_init(adapter);
1509 if (err)
1510 goto err_sw_init;
1511
1512 igb_get_bus_info_pcie(hw);
1513
7dfc16fa
AD		 1514 /* set flags */
1515 switch (hw->mac.type) {
7dfc16fa 1516 case e1000_82575:
7dfc16fa
AD		 1517 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1518 break;
bbd98fe4 1519 case e1000_82576:
7dfc16fa
AD		 1520 default:
1521 break;
1522 }
1523
9d5c8243
AK		 1524 hw->phy.autoneg_wait_to_complete = false;
1525 hw->mac.adaptive_ifs = true;
1526
1527 /* Copper options */
1528 if (hw->phy.media_type == e1000_media_type_copper) {
1529 hw->phy.mdix = AUTO_ALL_MODES;
1530 hw->phy.disable_polarity_correction = false;
1531 hw->phy.ms_type = e1000_ms_hw_default;
1532 }
1533
1534 if (igb_check_reset_block(hw))
1535 dev_info(&pdev->dev,
1536 "PHY reset is blocked due to SOL/IDER session.\n");
1537
1538 netdev->features = NETIF_F_SG |
7d8eb29e 1539 NETIF_F_IP_CSUM |
9d5c8243
AK		 1540 NETIF_F_HW_VLAN_TX |
1541 NETIF_F_HW_VLAN_RX |
1542 NETIF_F_HW_VLAN_FILTER;
1543
7d8eb29e 1544 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1545 netdev->features |= NETIF_F_TSO;
9d5c8243 1546 netdev->features |= NETIF_F_TSO6;
48f29ffc 1547
5c0999b7 1548 netdev->features |= NETIF_F_GRO;
d3352520 1549
48f29ffc
JK		 1550 netdev->vlan_features |= NETIF_F_TSO;
1551 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1552 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1553 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1554 netdev->vlan_features |= NETIF_F_SG;
1555
9d5c8243
AK		 1556 if (pci_using_dac)
1557 netdev->features |= NETIF_F_HIGHDMA;
1558
b9473560
JB		 1559 if (adapter->hw.mac.type == e1000_82576)
1560 netdev->features |= NETIF_F_SCTP_CSUM;
1561
9d5c8243
AK		 1562 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1563
1564 /* before reading the NVM, reset the controller to put the device in a
1565 * known good starting state */
1566 hw->mac.ops.reset_hw(hw);
1567
1568 /* make sure the NVM is good */
1569 if (igb_validate_nvm_checksum(hw) < 0) {
1570 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1571 err = -EIO;
1572 goto err_eeprom;
1573 }
1574
1575 /* copy the MAC address out of the NVM */
1576 if (hw->mac.ops.read_mac_addr(hw))
1577 dev_err(&pdev->dev, "NVM Read Error\n");
1578
1579 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1580 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1581
1582 if (!is_valid_ether_addr(netdev->perm_addr)) {
1583 dev_err(&pdev->dev, "Invalid MAC Address\n");
1584 err = -EIO;
1585 goto err_eeprom;
1586 }
1587
0e340485
AD		 1588 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1589 (unsigned long) adapter);
1590 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1591 (unsigned long) adapter);
9d5c8243
AK		 1592
1593 INIT_WORK(&adapter->reset_task, igb_reset_task);
1594 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1595
450c87c8 1596 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1597 adapter->fc_autoneg = true;
1598 hw->mac.autoneg = true;
1599 hw->phy.autoneg_advertised = 0x2f;
1600
0cce119a
AD		 1601 hw->fc.requested_mode = e1000_fc_default;
1602 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1603
cbd347ad 1604 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1605 adapter->itr = IGB_START_ITR;
1606
1607 igb_validate_mdi_setting(hw);
1608
9d5c8243
AK		 1609 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1610 * enable the ACPI Magic Packet filter
1611 */
1612
a2cf8b6c 1613 if (hw->bus.func == 0)
312c75ae 1614 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1615 else if (hw->bus.func == 1)
1616 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1617
1618 if (eeprom_data & eeprom_apme_mask)
1619 adapter->eeprom_wol |= E1000_WUFC_MAG;
1620
1621 /* now that we have the eeprom settings, apply the special cases where
1622 * the eeprom may be wrong or the board simply won't support wake on
1623 * lan on a particular port */
1624 switch (pdev->device) {
1625 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1626 adapter->eeprom_wol = 0;
1627 break;
1628 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1629 case E1000_DEV_ID_82576_FIBER:
1630 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1631 /* Wake events only supported on port A for dual fiber
1632 * regardless of eeprom setting */
1633 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1634 adapter->eeprom_wol = 0;
1635 break;
c8ea5ea9
AD		 1636 case E1000_DEV_ID_82576_QUAD_COPPER:
1637 /* if quad port adapter, disable WoL on all but port A */
1638 if (global_quad_port_a != 0)
1639 adapter->eeprom_wol = 0;
1640 else
1641 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1642 /* Reset for multiple quad port adapters */
1643 if (++global_quad_port_a == 4)
1644 global_quad_port_a = 0;
1645 break;
9d5c8243
AK		 1646 }
1647
1648 /* initialize the wol settings based on the eeprom settings */
1649 adapter->wol = adapter->eeprom_wol;
e1b86d84 1650 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1651
1652 /* reset the hardware with the new settings */
1653 igb_reset(adapter);
1654
1655 /* let the f/w know that the h/w is now under the control of the
1656 * driver. */
1657 igb_get_hw_control(adapter);
1658
9d5c8243
AK		 1659 strcpy(netdev->name, "eth%d");
1660 err = register_netdev(netdev);
1661 if (err)
1662 goto err_register;
1663
b168dfc5
JB		 1664 /* carrier off reporting is important to ethtool even BEFORE open */
1665 netif_carrier_off(netdev);
1666
421e02f0 1667#ifdef CONFIG_IGB_DCA
bbd98fe4 1668 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1669 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1670 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1671 igb_setup_dca(adapter);
1672 }
1673#endif
1674
38c845c7
PO		 1675 /*
1676 * Initialize hardware timer: we keep it running just in case
1677 * that some program needs it later on.
1678 */
1679 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1680 adapter->cycles.read = igb_read_clock;
1681 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1682 adapter->cycles.mult = 1;
1683 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1684 wr32(E1000_TIMINCA,
1685 (1<<24) |
1686 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1687#if 0
1688 /*
1689 * Avoid rollover while we initialize by resetting the time counter.
1690 */
1691 wr32(E1000_SYSTIML, 0x00000000);
1692 wr32(E1000_SYSTIMH, 0x00000000);
1693#else
1694 /*
1695 * Set registers so that rollover occurs soon to test this.
1696 */
1697 wr32(E1000_SYSTIML, 0x00000000);
1698 wr32(E1000_SYSTIMH, 0xFF800000);
1699#endif
1700 wrfl();
1701 timecounter_init(&adapter->clock,
1702 &adapter->cycles,
1703 ktime_to_ns(ktime_get_real()));
1704
33af6bcc
PO		 1705 /*
1706 * Synchronize our NIC clock against system wall clock. NIC
1707 * time stamp reading requires ~3us per sample, each sample
1708 * was pretty stable even under load => only require 10
1709 * samples for each offset comparison.
1710 */
1711 memset(&adapter->compare, 0, sizeof(adapter->compare));
1712 adapter->compare.source = &adapter->clock;
1713 adapter->compare.target = ktime_get_real;
1714 adapter->compare.num_samples = 10;
1715 timecompare_update(&adapter->compare, 0);
1716
38c845c7
PO		 1717#ifdef DEBUG
1718 {
1719 char buffer[160];
1720 printk(KERN_DEBUG
1721 "igb: %s: hw %p initialized timer\n",
1722 igb_get_time_str(adapter, buffer),
1723 &adapter->hw);
1724 }
1725#endif
1726
9d5c8243
AK		 1727 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1728 /* print bus type/speed/width info */
7c510e4b 1729 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1730 netdev->name,
1731 ((hw->bus.speed == e1000_bus_speed_2500)
1732 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1733 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1734 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1735 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1736 "unknown"),
7c510e4b 1737 netdev->dev_addr);
9d5c8243
AK		 1738
1739 igb_read_part_num(hw, &part_num);
1740 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1741 (part_num >> 8), (part_num & 0xff));
1742
1743 dev_info(&pdev->dev,
1744 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1745 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1746 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1747 adapter->num_rx_queues, adapter->num_tx_queues);
1748
9d5c8243
AK		 1749 return 0;
1750
1751err_register:
1752 igb_release_hw_control(adapter);
1753err_eeprom:
1754 if (!igb_check_reset_block(hw))
f5f4cf08 1755 igb_reset_phy(hw);
9d5c8243
AK		 1756
1757 if (hw->flash_address)
1758 iounmap(hw->flash_address);
9d5c8243 1759err_sw_init:
047e0030 1760 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1761 iounmap(hw->hw_addr);
1762err_ioremap:
1763 free_netdev(netdev);
1764err_alloc_etherdev:
aed5dec3
AD		 1765 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1766 IORESOURCE_MEM));
9d5c8243
AK		 1767err_pci_reg:
1768err_dma:
1769 pci_disable_device(pdev);
1770 return err;
1771}
1772
1773/**
1774 * igb_remove - Device Removal Routine
1775 * @pdev: PCI device information struct
1776 *
1777 * igb_remove is called by the PCI subsystem to alert the driver
1778 * that it should release a PCI device. The could be caused by a
1779 * Hot-Plug event, or because the driver is going to be removed from
1780 * memory.
1781 **/
1782static void __devexit igb_remove(struct pci_dev *pdev)
1783{
1784 struct net_device *netdev = pci_get_drvdata(pdev);
1785 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1786 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1787
1788 /* flush_scheduled work may reschedule our watchdog task, so
1789 * explicitly disable watchdog tasks from being rescheduled */
1790 set_bit(__IGB_DOWN, &adapter->state);
1791 del_timer_sync(&adapter->watchdog_timer);
1792 del_timer_sync(&adapter->phy_info_timer);
1793
1794 flush_scheduled_work();
1795
421e02f0 1796#ifdef CONFIG_IGB_DCA
7dfc16fa 1797 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1798 dev_info(&pdev->dev, "DCA disabled\n");
1799 dca_remove_requester(&pdev->dev);
7dfc16fa 1800 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1801 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1802 }
1803#endif
1804
9d5c8243
AK		 1805 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1806 * would have already happened in close and is redundant. */
1807 igb_release_hw_control(adapter);
1808
1809 unregister_netdev(netdev);
1810
f5f4cf08
AD		 1811 if (!igb_check_reset_block(&adapter->hw))
1812 igb_reset_phy(&adapter->hw);
9d5c8243 1813
047e0030 1814 igb_clear_interrupt_scheme(adapter);
9d5c8243 1815
37680117
AD		 1816#ifdef CONFIG_PCI_IOV
1817 /* reclaim resources allocated to VFs */
1818 if (adapter->vf_data) {
1819 /* disable iov and allow time for transactions to clear */
1820 pci_disable_sriov(pdev);
1821 msleep(500);
1822
1823 kfree(adapter->vf_data);
1824 adapter->vf_data = NULL;
1825 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1826 msleep(100);
1827 dev_info(&pdev->dev, "IOV Disabled\n");
1828 }
1829#endif
28b0759c
AD		 1830 iounmap(hw->hw_addr);
1831 if (hw->flash_address)
1832 iounmap(hw->flash_address);
aed5dec3
AD		 1833 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1834 IORESOURCE_MEM));
9d5c8243
AK		 1835
1836 free_netdev(netdev);
1837
19d5afd4 1838 pci_disable_pcie_error_reporting(pdev);
40a914fa 1839
9d5c8243
AK		 1840 pci_disable_device(pdev);
1841}
1842
1843/**
1844 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1845 * @adapter: board private structure to initialize
1846 *
1847 * igb_sw_init initializes the Adapter private data structure.
1848 * Fields are initialized based on PCI device information and
1849 * OS network device settings (MTU size).
1850 **/
1851static int __devinit igb_sw_init(struct igb_adapter *adapter)
1852{
1853 struct e1000_hw *hw = &adapter->hw;
1854 struct net_device *netdev = adapter->netdev;
1855 struct pci_dev *pdev = adapter->pdev;
1856
1857 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1858
68fd9910
AD		 1859 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1860 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1861 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1862 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1863 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1864 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1865
661086df
PWJ		 1866 /* This call may decrease the number of queues depending on
1867 * interrupt mode. */
047e0030 1868 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1869 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1870 return -ENOMEM;
1871 }
1872
1873 /* Explicitly disable IRQ since the NIC can be in any state. */
1874 igb_irq_disable(adapter);
1875
1876 set_bit(__IGB_DOWN, &adapter->state);
1877 return 0;
1878}
1879
1880/**
1881 * igb_open - Called when a network interface is made active
1882 * @netdev: network interface device structure
1883 *
1884 * Returns 0 on success, negative value on failure
1885 *
1886 * The open entry point is called when a network interface is made
1887 * active by the system (IFF_UP). At this point all resources needed
1888 * for transmit and receive operations are allocated, the interrupt
1889 * handler is registered with the OS, the watchdog timer is started,
1890 * and the stack is notified that the interface is ready.
1891 **/
1892static int igb_open(struct net_device *netdev)
1893{
1894 struct igb_adapter *adapter = netdev_priv(netdev);
1895 struct e1000_hw *hw = &adapter->hw;
1896 int err;
1897 int i;
1898
1899 /* disallow open during test */
1900 if (test_bit(__IGB_TESTING, &adapter->state))
1901 return -EBUSY;
1902
b168dfc5
JB		 1903 netif_carrier_off(netdev);
1904
9d5c8243
AK		 1905 /* allocate transmit descriptors */
1906 err = igb_setup_all_tx_resources(adapter);
1907 if (err)
1908 goto err_setup_tx;
1909
1910 /* allocate receive descriptors */
1911 err = igb_setup_all_rx_resources(adapter);
1912 if (err)
1913 goto err_setup_rx;
1914
1915 /* e1000_power_up_phy(adapter); */
1916
1917 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1918 if ((adapter->hw.mng_cookie.status &
1919 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1920 igb_update_mng_vlan(adapter);
1921
1922 /* before we allocate an interrupt, we must be ready to handle it.
1923 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1924 * as soon as we call pci_request_irq, so we have to setup our
1925 * clean_rx handler before we do so. */
1926 igb_configure(adapter);
1927
4ae196df 1928 igb_vmm_control(adapter);
e1739522
AD		 1929 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1930
9d5c8243
AK		 1931 err = igb_request_irq(adapter);
1932 if (err)
1933 goto err_req_irq;
1934
1935 /* From here on the code is the same as igb_up() */
1936 clear_bit(__IGB_DOWN, &adapter->state);
1937
047e0030
AD		 1938 for (i = 0; i < adapter->num_q_vectors; i++) {
1939 struct igb_q_vector *q_vector = adapter->q_vector[i];
1940 napi_enable(&q_vector->napi);
1941 }
9d5c8243
AK		 1942
1943 /* Clear any pending interrupts. */
1944 rd32(E1000_ICR);
844290e5
PW		 1945
1946 igb_irq_enable(adapter);
1947
d55b53ff
JK		 1948 netif_tx_start_all_queues(netdev);
1949
9d5c8243
AK		 1950 /* Fire a link status change interrupt to start the watchdog. */
1951 wr32(E1000_ICS, E1000_ICS_LSC);
1952
1953 return 0;
1954
1955err_req_irq:
1956 igb_release_hw_control(adapter);
1957 /* e1000_power_down_phy(adapter); */
1958 igb_free_all_rx_resources(adapter);
1959err_setup_rx:
1960 igb_free_all_tx_resources(adapter);
1961err_setup_tx:
1962 igb_reset(adapter);
1963
1964 return err;
1965}
1966
1967/**
1968 * igb_close - Disables a network interface
1969 * @netdev: network interface device structure
1970 *
1971 * Returns 0, this is not allowed to fail
1972 *
1973 * The close entry point is called when an interface is de-activated
1974 * by the OS. The hardware is still under the driver's control, but
1975 * needs to be disabled. A global MAC reset is issued to stop the
1976 * hardware, and all transmit and receive resources are freed.
1977 **/
1978static int igb_close(struct net_device *netdev)
1979{
1980 struct igb_adapter *adapter = netdev_priv(netdev);
1981
1982 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1983 igb_down(adapter);
1984
1985 igb_free_irq(adapter);
1986
1987 igb_free_all_tx_resources(adapter);
1988 igb_free_all_rx_resources(adapter);
1989
1990 /* kill manageability vlan ID if supported, but not if a vlan with
1991 * the same ID is registered on the host OS (let 8021q kill it) */
1992 if ((adapter->hw.mng_cookie.status &
1993 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1994 !(adapter->vlgrp &&
1995 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1996 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1997
1998 return 0;
1999}
2000
2001/**
2002 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2003 * @adapter: board private structure
2004 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2005 *
2006 * Return 0 on success, negative on failure
2007 **/
9d5c8243
AK		 2008int igb_setup_tx_resources(struct igb_adapter *adapter,
2009 struct igb_ring *tx_ring)
2010{
2011 struct pci_dev *pdev = adapter->pdev;
2012 int size;
2013
2014 size = sizeof(struct igb_buffer) * tx_ring->count;
2015 tx_ring->buffer_info = vmalloc(size);
2016 if (!tx_ring->buffer_info)
2017 goto err;
2018 memset(tx_ring->buffer_info, 0, size);
2019
2020 /* round up to nearest 4K */
85e8d004 2021 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2022 tx_ring->size = ALIGN(tx_ring->size, 4096);
2023
2024 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2025 &tx_ring->dma);
2026
2027 if (!tx_ring->desc)
2028 goto err;
2029
9d5c8243
AK		 2030 tx_ring->next_to_use = 0;
2031 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2032 return 0;
2033
2034err:
2035 vfree(tx_ring->buffer_info);
047e0030 2036 dev_err(&pdev->dev,
9d5c8243
AK		 2037 "Unable to allocate memory for the transmit descriptor ring\n");
2038 return -ENOMEM;
2039}
2040
2041/**
2042 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2043 * (Descriptors) for all queues
2044 * @adapter: board private structure
2045 *
2046 * Return 0 on success, negative on failure
2047 **/
2048static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2049{
2050 int i, err = 0;
661086df 2051 int r_idx;
9d5c8243
AK		 2052
2053 for (i = 0; i < adapter->num_tx_queues; i++) {
2054 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2055 if (err) {
2056 dev_err(&adapter->pdev->dev,
2057 "Allocation for Tx Queue %u failed\n", i);
2058 for (i--; i >= 0; i--)
3b644cf6 2059 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2060 break;
2061 }
2062 }
2063
661086df
PWJ		 2064 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2065 r_idx = i % adapter->num_tx_queues;
2066 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2067 }
9d5c8243
AK		 2068 return err;
2069}
2070
2071/**
2072 * igb_configure_tx - Configure transmit Unit after Reset
2073 * @adapter: board private structure
2074 *
2075 * Configure the Tx unit of the MAC after a reset.
2076 **/
2077static void igb_configure_tx(struct igb_adapter *adapter)
2078{
0e014cb1 2079 u64 tdba;
9d5c8243
AK		 2080 struct e1000_hw *hw = &adapter->hw;
2081 u32 tctl;
2082 u32 txdctl, txctrl;
26bc19ec 2083 int i, j;
9d5c8243
AK		 2084
2085 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 2086 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 2087 j = ring->reg_idx;
2088 wr32(E1000_TDLEN(j),
85e8d004 2089 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 2090 tdba = ring->dma;
26bc19ec 2091 wr32(E1000_TDBAL(j),
73cd78f1 2092 tdba & 0x00000000ffffffffULL);
26bc19ec 2093 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 2094
26bc19ec
AD		 2095 ring->head = E1000_TDH(j);
2096 ring->tail = E1000_TDT(j);
9d5c8243
AK		 2097 writel(0, hw->hw_addr + ring->tail);
2098 writel(0, hw->hw_addr + ring->head);
26bc19ec 2099 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 2100 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 2101 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 2102
2103 /* Turn off Relaxed Ordering on head write-backs. The
2104 * writebacks MUST be delivered in order or it will
2105 * completely screw up our bookeeping.
2106 */
26bc19ec 2107 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 2108 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 2109 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 2110 }
2111
e1739522
AD		 2112 /* disable queue 0 to prevent tail bump w/o re-configuration */
2113 if (adapter->vfs_allocated_count)
2114 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2115
2116 /* Program the Transmit Control Register */
9d5c8243
AK		 2117 tctl = rd32(E1000_TCTL);
2118 tctl &= ~E1000_TCTL_CT;
2119 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2120 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2121
2122 igb_config_collision_dist(hw);
2123
2124 /* Setup Transmit Descriptor Settings for eop descriptor */
2125 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
2126
2127 /* Enable transmits */
2128 tctl |= E1000_TCTL_EN;
2129
2130 wr32(E1000_TCTL, tctl);
2131}
2132
2133/**
2134 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2135 * @adapter: board private structure
2136 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2137 *
2138 * Returns 0 on success, negative on failure
2139 **/
9d5c8243
AK		 2140int igb_setup_rx_resources(struct igb_adapter *adapter,
2141 struct igb_ring *rx_ring)
2142{
2143 struct pci_dev *pdev = adapter->pdev;
2144 int size, desc_len;
2145
2146 size = sizeof(struct igb_buffer) * rx_ring->count;
2147 rx_ring->buffer_info = vmalloc(size);
2148 if (!rx_ring->buffer_info)
2149 goto err;
2150 memset(rx_ring->buffer_info, 0, size);
2151
2152 desc_len = sizeof(union e1000_adv_rx_desc);
2153
2154 /* Round up to nearest 4K */
2155 rx_ring->size = rx_ring->count * desc_len;
2156 rx_ring->size = ALIGN(rx_ring->size, 4096);
2157
2158 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2159 &rx_ring->dma);
2160
2161 if (!rx_ring->desc)
2162 goto err;
2163
2164 rx_ring->next_to_clean = 0;
2165 rx_ring->next_to_use = 0;
9d5c8243 2166
9d5c8243
AK		 2167 return 0;
2168
2169err:
2170 vfree(rx_ring->buffer_info);
2171 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2172 "the receive descriptor ring\n");
2173 return -ENOMEM;
2174}
2175
2176/**
2177 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2178 * (Descriptors) for all queues
2179 * @adapter: board private structure
2180 *
2181 * Return 0 on success, negative on failure
2182 **/
2183static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2184{
2185 int i, err = 0;
2186
2187 for (i = 0; i < adapter->num_rx_queues; i++) {
2188 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2189 if (err) {
2190 dev_err(&adapter->pdev->dev,
2191 "Allocation for Rx Queue %u failed\n", i);
2192 for (i--; i >= 0; i--)
3b644cf6 2193 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2194 break;
2195 }
2196 }
2197
2198 return err;
2199}
2200
2201/**
2202 * igb_setup_rctl - configure the receive control registers
2203 * @adapter: Board private structure
2204 **/
2205static void igb_setup_rctl(struct igb_adapter *adapter)
2206{
2207 struct e1000_hw *hw = &adapter->hw;
2208 u32 rctl;
2209 u32 srrctl = 0;
77a22941 2210 int i;
9d5c8243
AK		 2211
2212 rctl = rd32(E1000_RCTL);
2213
2214 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2215 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2216
69d728ba 2217 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2218 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2219
87cb7e8c
AK		 2220 /*
2221 * enable stripping of CRC. It's unlikely this will break BMC
2222 * redirection as it did with e1000. Newer features require
2223 * that the HW strips the CRC.
73cd78f1 2224 */
87cb7e8c 2225 rctl |= E1000_RCTL_SECRC;
9d5c8243 2226
9b07f3d3 2227 /*
ec54d7d6 2228 * disable store bad packets and clear size bits.
9b07f3d3 2229 */
ec54d7d6 2230 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2231
ec54d7d6 2232 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 2233 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 2234
2235 /* Setup buffer sizes */
7d95b717
AD		 2236 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2237 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
9d5c8243
AK		 2238
2239 /* 82575 and greater support packet-split where the protocol
2240 * header is placed in skb->data and the packet data is
2241 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2242 * In the case of a non-split, skb->data is linearly filled,
2243 * followed by the page buffers. Therefore, skb->data is
2244 * sized to hold the largest protocol header.
2245 */
2246 /* allocations using alloc_page take too long for regular MTU
2247 * so only enable packet split for jumbo frames */
ec54d7d6 2248 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2249 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2250 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2251 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2252 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2253 } else {
2254 adapter->rx_ps_hdr_size = 0;
2255 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2256 }
2257
e1739522
AD		 2258 /* Attention!!! For SR-IOV PF driver operations you must enable
2259 * queue drop for all VF and PF queues to prevent head of line blocking
2260 * if an un-trusted VF does not provide descriptors to hardware.
2261 */
2262 if (adapter->vfs_allocated_count) {
2263 u32 vmolr;
2264
e1739522
AD		 2265 /* set all queue drop enable bits */
2266 wr32(E1000_QDE, ALL_QUEUES);
2267 srrctl |= E1000_SRRCTL_DROP_EN;
2268
2269 /* disable queue 0 to prevent tail write w/o re-config */
2270 wr32(E1000_RXDCTL(0), 0);
2271
77a22941 2272 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2273 if (rctl & E1000_RCTL_LPE)
2274 vmolr |= E1000_VMOLR_LPE;
77a22941 2275 if (adapter->num_rx_queues > 1)
e1739522 2276 vmolr |= E1000_VMOLR_RSSE;
77a22941 2277 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2278 }
2279
26bc19ec 2280 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2281 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2282 wr32(E1000_SRRCTL(j), srrctl);
2283 }
9d5c8243
AK		 2284
2285 wr32(E1000_RCTL, rctl);
2286}
2287
e1739522
AD		 2288/**
2289 * igb_rlpml_set - set maximum receive packet size
2290 * @adapter: board private structure
2291 *
2292 * Configure maximum receivable packet size.
2293 **/
2294static void igb_rlpml_set(struct igb_adapter *adapter)
2295{
2296 u32 max_frame_size = adapter->max_frame_size;
2297 struct e1000_hw *hw = &adapter->hw;
2298 u16 pf_id = adapter->vfs_allocated_count;
2299
2300 if (adapter->vlgrp)
2301 max_frame_size += VLAN_TAG_SIZE;
2302
2303 /* if vfs are enabled we set RLPML to the largest possible request
2304 * size and set the VMOLR RLPML to the size we need */
2305 if (pf_id) {
2306 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2307 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2308 }
2309
2310 wr32(E1000_RLPML, max_frame_size);
2311}
2312
2313/**
2314 * igb_configure_vt_default_pool - Configure VT default pool
2315 * @adapter: board private structure
2316 *
2317 * Configure the default pool
2318 **/
2319static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2320{
2321 struct e1000_hw *hw = &adapter->hw;
2322 u16 pf_id = adapter->vfs_allocated_count;
2323 u32 vtctl;
2324
2325 /* not in sr-iov mode - do nothing */
2326 if (!pf_id)
2327 return;
2328
2329 vtctl = rd32(E1000_VT_CTL);
2330 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2331 E1000_VT_CTL_DISABLE_DEF_POOL);
2332 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2333 wr32(E1000_VT_CTL, vtctl);
2334}
2335
9d5c8243
AK		 2336/**
2337 * igb_configure_rx - Configure receive Unit after Reset
2338 * @adapter: board private structure
2339 *
2340 * Configure the Rx unit of the MAC after a reset.
2341 **/
2342static void igb_configure_rx(struct igb_adapter *adapter)
2343{
2344 u64 rdba;
2345 struct e1000_hw *hw = &adapter->hw;
2346 u32 rctl, rxcsum;
2347 u32 rxdctl;
9107584e 2348 int i;
9d5c8243
AK		 2349
2350 /* disable receives while setting up the descriptors */
2351 rctl = rd32(E1000_RCTL);
2352 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2353 wrfl();
2354 mdelay(10);
2355
2356 if (adapter->itr_setting > 3)
6eb5a7f1 2357 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2358
2359 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2360 * the Base and Length of the Rx Descriptor Ring */
2361 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2362 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2363 int j = ring->reg_idx;
9d5c8243 2364 rdba = ring->dma;
26bc19ec 2365 wr32(E1000_RDBAL(j),
73cd78f1 2366 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2367 wr32(E1000_RDBAH(j), rdba >> 32);
2368 wr32(E1000_RDLEN(j),
73cd78f1 2369 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2370
26bc19ec
AD		 2371 ring->head = E1000_RDH(j);
2372 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2373 writel(0, hw->hw_addr + ring->tail);
2374 writel(0, hw->hw_addr + ring->head);
2375
26bc19ec 2376 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2377 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2378 rxdctl &= 0xFFF00000;
2379 rxdctl |= IGB_RX_PTHRESH;
2380 rxdctl |= IGB_RX_HTHRESH << 8;
2381 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2382 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2383 }
2384
2385 if (adapter->num_rx_queues > 1) {
2386 u32 random[10];
2387 u32 mrqc;
2388 u32 j, shift;
2389 union e1000_reta {
2390 u32 dword;
2391 u8 bytes[4];
2392 } reta;
2393
2394 get_random_bytes(&random[0], 40);
2395
2d064c06
AD		 2396 if (hw->mac.type >= e1000_82576)
2397 shift = 0;
2398 else
2399 shift = 6;
9d5c8243
AK		 2400 for (j = 0; j < (32 * 4); j++) {
2401 reta.bytes[j & 3] =
26bc19ec 2402 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2403 if ((j & 3) == 3)
2404 writel(reta.dword,
2405 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2406 }
e1739522
AD		 2407 if (adapter->vfs_allocated_count)
2408 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2409 else
2410 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2411
2412 /* Fill out hash function seeds */
2413 for (j = 0; j < 10; j++)
2414 array_wr32(E1000_RSSRK(0), j, random[j]);
2415
2416 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2417 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2418 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2419 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2420 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2421 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2422 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2424
9d5c8243 2425 wr32(E1000_MRQC, mrqc);
2844f797 2426 } else if (adapter->vfs_allocated_count) {
e1739522 2427 /* Enable multi-queue for sr-iov */
2844f797 2428 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2429 }
2430
2844f797
AD		 2431 /* Enable Receive Checksum Offload for TCP and UDP */
2432 rxcsum = rd32(E1000_RXCSUM);
2433 /* Disable raw packet checksumming */
2434 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2435
2436 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2437 /* Enable Receive Checksum Offload for SCTP */
2438 rxcsum |= E1000_RXCSUM_CRCOFL;
2439
7beb0146 2440 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2441 wr32(E1000_RXCSUM, rxcsum);
2442
e1739522
AD		 2443 /* Set the default pool for the PF's first queue */
2444 igb_configure_vt_default_pool(adapter);
2445
68d480c4
AD		 2446 /* set UTA to appropriate mode */
2447 igb_set_uta(adapter);
2448
26ad9178
AD		 2449 /* set the correct pool for the PF default MAC address in entry 0 */
2450 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2451 adapter->vfs_allocated_count);
2452
e1739522 2453 igb_rlpml_set(adapter);
9d5c8243
AK		 2454
2455 /* Enable Receives */
2456 wr32(E1000_RCTL, rctl);
2457}
2458
2459/**
2460 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2461 * @tx_ring: Tx descriptor ring for a specific queue
2462 *
2463 * Free all transmit software resources
2464 **/
68fd9910 2465void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2466{
047e0030 2467 struct pci_dev *pdev = tx_ring->q_vector->adapter->pdev;
9d5c8243 2468
3b644cf6 2469 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2470
2471 vfree(tx_ring->buffer_info);
2472 tx_ring->buffer_info = NULL;
2473
2474 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2475
2476 tx_ring->desc = NULL;
2477}
2478
2479/**
2480 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2481 * @adapter: board private structure
2482 *
2483 * Free all transmit software resources
2484 **/
2485static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2486{
2487 int i;
2488
2489 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2490 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2491}
2492
2493static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2494 struct igb_buffer *buffer_info)
2495{
65689fef 2496 buffer_info->dma = 0;
9d5c8243 2497 if (buffer_info->skb) {
65689fef
AD		 2498 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2499 DMA_TO_DEVICE);
9d5c8243
AK		 2500 dev_kfree_skb_any(buffer_info->skb);
2501 buffer_info->skb = NULL;
2502 }
2503 buffer_info->time_stamp = 0;
2504 /* buffer_info must be completely set up in the transmit path */
2505}
2506
2507/**
2508 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2509 * @tx_ring: ring to be cleaned
2510 **/
3b644cf6 2511static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2512{
047e0030 2513 struct igb_adapter *adapter = tx_ring->q_vector->adapter;
9d5c8243
AK		 2514 struct igb_buffer *buffer_info;
2515 unsigned long size;
2516 unsigned int i;
2517
2518 if (!tx_ring->buffer_info)
2519 return;
2520 /* Free all the Tx ring sk_buffs */
2521
2522 for (i = 0; i < tx_ring->count; i++) {
2523 buffer_info = &tx_ring->buffer_info[i];
2524 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2525 }
2526
2527 size = sizeof(struct igb_buffer) * tx_ring->count;
2528 memset(tx_ring->buffer_info, 0, size);
2529
2530 /* Zero out the descriptor ring */
2531
2532 memset(tx_ring->desc, 0, tx_ring->size);
2533
2534 tx_ring->next_to_use = 0;
2535 tx_ring->next_to_clean = 0;
2536
2537 writel(0, adapter->hw.hw_addr + tx_ring->head);
2538 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2539}
2540
2541/**
2542 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2543 * @adapter: board private structure
2544 **/
2545static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2546{
2547 int i;
2548
2549 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2550 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2551}
2552
2553/**
2554 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2555 * @rx_ring: ring to clean the resources from
2556 *
2557 * Free all receive software resources
2558 **/
68fd9910 2559void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2560{
047e0030 2561 struct pci_dev *pdev = rx_ring->q_vector->adapter->pdev;
9d5c8243 2562
3b644cf6 2563 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2564
2565 vfree(rx_ring->buffer_info);
2566 rx_ring->buffer_info = NULL;
2567
2568 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2569
2570 rx_ring->desc = NULL;
2571}
2572
2573/**
2574 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2575 * @adapter: board private structure
2576 *
2577 * Free all receive software resources
2578 **/
2579static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2580{
2581 int i;
2582
2583 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2584 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2585}
2586
2587/**
2588 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2589 * @rx_ring: ring to free buffers from
2590 **/
3b644cf6 2591static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2592{
047e0030 2593 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243
AK		 2594 struct igb_buffer *buffer_info;
2595 struct pci_dev *pdev = adapter->pdev;
2596 unsigned long size;
2597 unsigned int i;
2598
2599 if (!rx_ring->buffer_info)
2600 return;
2601 /* Free all the Rx ring sk_buffs */
2602 for (i = 0; i < rx_ring->count; i++) {
2603 buffer_info = &rx_ring->buffer_info[i];
2604 if (buffer_info->dma) {
2605 if (adapter->rx_ps_hdr_size)
2606 pci_unmap_single(pdev, buffer_info->dma,
2607 adapter->rx_ps_hdr_size,
2608 PCI_DMA_FROMDEVICE);
2609 else
2610 pci_unmap_single(pdev, buffer_info->dma,
2611 adapter->rx_buffer_len,
2612 PCI_DMA_FROMDEVICE);
2613 buffer_info->dma = 0;
2614 }
2615
2616 if (buffer_info->skb) {
2617 dev_kfree_skb(buffer_info->skb);
2618 buffer_info->skb = NULL;
2619 }
2620 if (buffer_info->page) {
bf36c1a0
AD		 2621 if (buffer_info->page_dma)
2622 pci_unmap_page(pdev, buffer_info->page_dma,
2623 PAGE_SIZE / 2,
2624 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2625 put_page(buffer_info->page);
2626 buffer_info->page = NULL;
2627 buffer_info->page_dma = 0;
bf36c1a0 2628 buffer_info->page_offset = 0;
9d5c8243
AK		 2629 }
2630 }
2631
9d5c8243
AK		 2632 size = sizeof(struct igb_buffer) * rx_ring->count;
2633 memset(rx_ring->buffer_info, 0, size);
2634
2635 /* Zero out the descriptor ring */
2636 memset(rx_ring->desc, 0, rx_ring->size);
2637
2638 rx_ring->next_to_clean = 0;
2639 rx_ring->next_to_use = 0;
2640
2641 writel(0, adapter->hw.hw_addr + rx_ring->head);
2642 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2643}
2644
2645/**
2646 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2647 * @adapter: board private structure
2648 **/
2649static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2650{
2651 int i;
2652
2653 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2654 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2655}
2656
2657/**
2658 * igb_set_mac - Change the Ethernet Address of the NIC
2659 * @netdev: network interface device structure
2660 * @p: pointer to an address structure
2661 *
2662 * Returns 0 on success, negative on failure
2663 **/
2664static int igb_set_mac(struct net_device *netdev, void *p)
2665{
2666 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2667 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2668 struct sockaddr *addr = p;
2669
2670 if (!is_valid_ether_addr(addr->sa_data))
2671 return -EADDRNOTAVAIL;
2672
2673 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2674 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2675
26ad9178
AD		 2676 /* set the correct pool for the new PF MAC address in entry 0 */
2677 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2678 adapter->vfs_allocated_count);
e1739522 2679
9d5c8243
AK		 2680 return 0;
2681}
2682
2683/**
68d480c4 2684 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2685 * @netdev: network interface device structure
2686 *
68d480c4
AD		 2687 * Writes multicast address list to the MTA hash table.
2688 * Returns: -ENOMEM on failure
2689 * 0 on no addresses written
2690 * X on writing X addresses to MTA
9d5c8243 2691 **/
68d480c4 2692static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2693{
2694 struct igb_adapter *adapter = netdev_priv(netdev);
2695 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2696 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2697 u8 *mta_list;
2698 u32 vmolr = 0;
9d5c8243
AK		 2699 int i;
2700
68d480c4
AD		 2701 if (!netdev->mc_count) {
2702 /* nothing to program, so clear mc list */
2703 igb_update_mc_addr_list(hw, NULL, 0);
2704 igb_restore_vf_multicasts(adapter);
2705 return 0;
2706 }
9d5c8243 2707
68d480c4
AD		 2708 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2709 if (!mta_list)
2710 return -ENOMEM;
ff41f8dc 2711
68d480c4
AD		 2712 /* set vmolr receive overflow multicast bit */
2713 vmolr |= E1000_VMOLR_ROMPE;
2714
2715 /* The shared function expects a packed array of only addresses. */
2716 mc_ptr = netdev->mc_list;
2717
2718 for (i = 0; i < netdev->mc_count; i++) {
2719 if (!mc_ptr)
2720 break;
2721 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2722 mc_ptr = mc_ptr->next;
746b9f02 2723 }
68d480c4
AD		 2724 igb_update_mc_addr_list(hw, mta_list, i);
2725 kfree(mta_list);
2726
2727 return netdev->mc_count;
2728}
2729
2730/**
2731 * igb_write_uc_addr_list - write unicast addresses to RAR table
2732 * @netdev: network interface device structure
2733 *
2734 * Writes unicast address list to the RAR table.
2735 * Returns: -ENOMEM on failure/insufficient address space
2736 * 0 on no addresses written
2737 * X on writing X addresses to the RAR table
2738 **/
2739static int igb_write_uc_addr_list(struct net_device *netdev)
2740{
2741 struct igb_adapter *adapter = netdev_priv(netdev);
2742 struct e1000_hw *hw = &adapter->hw;
2743 unsigned int vfn = adapter->vfs_allocated_count;
2744 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2745 int count = 0;
2746
2747 /* return ENOMEM indicating insufficient memory for addresses */
2748 if (netdev->uc.count > rar_entries)
2749 return -ENOMEM;
9d5c8243 2750
ff41f8dc
AD		 2751 if (netdev->uc.count && rar_entries) {
2752 struct netdev_hw_addr *ha;
2753 list_for_each_entry(ha, &netdev->uc.list, list) {
2754 if (!rar_entries)
2755 break;
26ad9178
AD		 2756 igb_rar_set_qsel(adapter, ha->addr,
2757 rar_entries--,
68d480c4
AD		 2758 vfn);
2759 count++;
ff41f8dc
AD		 2760 }
2761 }
2762 /* write the addresses in reverse order to avoid write combining */
2763 for (; rar_entries > 0 ; rar_entries--) {
2764 wr32(E1000_RAH(rar_entries), 0);
2765 wr32(E1000_RAL(rar_entries), 0);
2766 }
2767 wrfl();
2768
68d480c4
AD		 2769 return count;
2770}
2771
2772/**
2773 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2774 * @netdev: network interface device structure
2775 *
2776 * The set_rx_mode entry point is called whenever the unicast or multicast
2777 * address lists or the network interface flags are updated. This routine is
2778 * responsible for configuring the hardware for proper unicast, multicast,
2779 * promiscuous mode, and all-multi behavior.
2780 **/
2781static void igb_set_rx_mode(struct net_device *netdev)
2782{
2783 struct igb_adapter *adapter = netdev_priv(netdev);
2784 struct e1000_hw *hw = &adapter->hw;
2785 unsigned int vfn = adapter->vfs_allocated_count;
2786 u32 rctl, vmolr = 0;
2787 int count;
2788
2789 /* Check for Promiscuous and All Multicast modes */
2790 rctl = rd32(E1000_RCTL);
2791
2792 /* clear the effected bits */
2793 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2794
2795 if (netdev->flags & IFF_PROMISC) {
2796 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2797 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2798 } else {
2799 if (netdev->flags & IFF_ALLMULTI) {
2800 rctl |= E1000_RCTL_MPE;
2801 vmolr |= E1000_VMOLR_MPME;
2802 } else {
2803 /*
2804 * Write addresses to the MTA, if the attempt fails
2805 * then we should just turn on promiscous mode so
2806 * that we can at least receive multicast traffic
2807 */
2808 count = igb_write_mc_addr_list(netdev);
2809 if (count < 0) {
2810 rctl |= E1000_RCTL_MPE;
2811 vmolr |= E1000_VMOLR_MPME;
2812 } else if (count) {
2813 vmolr |= E1000_VMOLR_ROMPE;
2814 }
2815 }
2816 /*
2817 * Write addresses to available RAR registers, if there is not
2818 * sufficient space to store all the addresses then enable
2819 * unicast promiscous mode
2820 */
2821 count = igb_write_uc_addr_list(netdev);
2822 if (count < 0) {
2823 rctl |= E1000_RCTL_UPE;
2824 vmolr |= E1000_VMOLR_ROPE;
2825 }
2826 rctl |= E1000_RCTL_VFE;
28fc06f5 2827 }
68d480c4 2828 wr32(E1000_RCTL, rctl);
28fc06f5 2829
68d480c4
AD		 2830 /*
2831 * In order to support SR-IOV and eventually VMDq it is necessary to set
2832 * the VMOLR to enable the appropriate modes. Without this workaround
2833 * we will have issues with VLAN tag stripping not being done for frames
2834 * that are only arriving because we are the default pool
2835 */
2836 if (hw->mac.type < e1000_82576)
28fc06f5 2837 return;
9d5c8243 2838
68d480c4
AD		 2839 vmolr |= rd32(E1000_VMOLR(vfn)) &
2840 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2841 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2842 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2843}
2844
2845/* Need to wait a few seconds after link up to get diagnostic information from
2846 * the phy */
2847static void igb_update_phy_info(unsigned long data)
2848{
2849 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2850 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2851}
2852
4d6b725e
AD		 2853/**
2854 * igb_has_link - check shared code for link and determine up/down
2855 * @adapter: pointer to driver private info
2856 **/
2857static bool igb_has_link(struct igb_adapter *adapter)
2858{
2859 struct e1000_hw *hw = &adapter->hw;
2860 bool link_active = false;
2861 s32 ret_val = 0;
2862
2863 /* get_link_status is set on LSC (link status) interrupt or
2864 * rx sequence error interrupt. get_link_status will stay
2865 * false until the e1000_check_for_link establishes link
2866 * for copper adapters ONLY
2867 */
2868 switch (hw->phy.media_type) {
2869 case e1000_media_type_copper:
2870 if (hw->mac.get_link_status) {
2871 ret_val = hw->mac.ops.check_for_link(hw);
2872 link_active = !hw->mac.get_link_status;
2873 } else {
2874 link_active = true;
2875 }
2876 break;
4d6b725e
AD		 2877 case e1000_media_type_internal_serdes:
2878 ret_val = hw->mac.ops.check_for_link(hw);
2879 link_active = hw->mac.serdes_has_link;
2880 break;
2881 default:
2882 case e1000_media_type_unknown:
2883 break;
2884 }
2885
2886 return link_active;
2887}
2888
9d5c8243
AK		 2889/**
2890 * igb_watchdog - Timer Call-back
2891 * @data: pointer to adapter cast into an unsigned long
2892 **/
2893static void igb_watchdog(unsigned long data)
2894{
2895 struct igb_adapter *adapter = (struct igb_adapter *)data;
2896 /* Do the rest outside of interrupt context */
2897 schedule_work(&adapter->watchdog_task);
2898}
2899
2900static void igb_watchdog_task(struct work_struct *work)
2901{
2902 struct igb_adapter *adapter = container_of(work,
2903 struct igb_adapter, watchdog_task);
2904 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2905 struct net_device *netdev = adapter->netdev;
2906 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2907 u32 link;
7a6ea550 2908 int i;
9d5c8243 2909
4d6b725e
AD		 2910 link = igb_has_link(adapter);
2911 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2912 goto link_up;
2913
9d5c8243
AK		 2914 if (link) {
2915 if (!netif_carrier_ok(netdev)) {
2916 u32 ctrl;
2917 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2918 &adapter->link_speed,
2919 &adapter->link_duplex);
2920
2921 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2922 /* Links status message must follow this format */
2923 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2924 "Flow Control: %s\n",
527d47c1 2925 netdev->name,
9d5c8243
AK		 2926 adapter->link_speed,
2927 adapter->link_duplex == FULL_DUPLEX ?
2928 "Full Duplex" : "Half Duplex",
2929 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2930 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2931 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2932 E1000_CTRL_TFCE) ? "TX" : "None")));
2933
2934 /* tweak tx_queue_len according to speed/duplex and
2935 * adjust the timeout factor */
2936 netdev->tx_queue_len = adapter->tx_queue_len;
2937 adapter->tx_timeout_factor = 1;
2938 switch (adapter->link_speed) {
2939 case SPEED_10:
2940 netdev->tx_queue_len = 10;
2941 adapter->tx_timeout_factor = 14;
2942 break;
2943 case SPEED_100:
2944 netdev->tx_queue_len = 100;
2945 /* maybe add some timeout factor ? */
2946 break;
2947 }
2948
2949 netif_carrier_on(netdev);
9d5c8243 2950
4ae196df
AD		 2951 igb_ping_all_vfs(adapter);
2952
4b1a9877 2953 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2954 if (!test_bit(__IGB_DOWN, &adapter->state))
2955 mod_timer(&adapter->phy_info_timer,
2956 round_jiffies(jiffies + 2 * HZ));
2957 }
2958 } else {
2959 if (netif_carrier_ok(netdev)) {
2960 adapter->link_speed = 0;
2961 adapter->link_duplex = 0;
527d47c1
AD		 2962 /* Links status message must follow this format */
2963 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2964 netdev->name);
9d5c8243 2965 netif_carrier_off(netdev);
4b1a9877 2966
4ae196df
AD		 2967 igb_ping_all_vfs(adapter);
2968
4b1a9877 2969 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2970 if (!test_bit(__IGB_DOWN, &adapter->state))
2971 mod_timer(&adapter->phy_info_timer,
2972 round_jiffies(jiffies + 2 * HZ));
2973 }
2974 }
2975
2976link_up:
2977 igb_update_stats(adapter);
2978
4b1a9877 2979 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2980 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2981 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2982 adapter->colc_old = adapter->stats.colc;
2983
2984 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2985 adapter->gorc_old = adapter->stats.gorc;
2986 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2987 adapter->gotc_old = adapter->stats.gotc;
2988
2989 igb_update_adaptive(&adapter->hw);
2990
2991 if (!netif_carrier_ok(netdev)) {
c493ea45 2992 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2993 /* We've lost link, so the controller stops DMA,
2994 * but we've got queued Tx work that's never going
2995 * to get done, so reset controller to flush Tx.
2996 * (Do the reset outside of interrupt context). */
2997 adapter->tx_timeout_count++;
2998 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 2999 /* return immediately since reset is imminent */
3000 return;
9d5c8243
AK		 3001 }
3002 }
3003
3004 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3005 if (adapter->msix_entries) {
047e0030
AD		 3006 u32 eics = 0;
3007 for (i = 0; i < adapter->num_q_vectors; i++) {
3008 struct igb_q_vector *q_vector = adapter->q_vector[i];
3009 eics |= q_vector->eims_value;
3010 }
7a6ea550
AD		 3011 wr32(E1000_EICS, eics);
3012 } else {
3013 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3014 }
9d5c8243
AK		 3015
3016 /* Force detection of hung controller every watchdog period */
3017 tx_ring->detect_tx_hung = true;
3018
3019 /* Reset the timer */
3020 if (!test_bit(__IGB_DOWN, &adapter->state))
3021 mod_timer(&adapter->watchdog_timer,
3022 round_jiffies(jiffies + 2 * HZ));
3023}
3024
3025enum latency_range {
3026 lowest_latency = 0,
3027 low_latency = 1,
3028 bulk_latency = 2,
3029 latency_invalid = 255
3030};
3031
3032
6eb5a7f1
AD		 3033/**
3034 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3035 *
3036 * Stores a new ITR value based on strictly on packet size. This
3037 * algorithm is less sophisticated than that used in igb_update_itr,
3038 * due to the difficulty of synchronizing statistics across multiple
3039 * receive rings. The divisors and thresholds used by this fuction
3040 * were determined based on theoretical maximum wire speed and testing
3041 * data, in order to minimize response time while increasing bulk
3042 * throughput.
3043 * This functionality is controlled by the InterruptThrottleRate module
3044 * parameter (see igb_param.c)
3045 * NOTE: This function is called only when operating in a multiqueue
3046 * receive environment.
047e0030 3047 * @q_vector: pointer to q_vector
6eb5a7f1 3048 **/
047e0030 3049static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3050{
047e0030 3051 int new_val = q_vector->itr_val;
6eb5a7f1 3052 int avg_wire_size = 0;
047e0030 3053 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3054
6eb5a7f1
AD		 3055 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3056 * ints/sec - ITR timer value of 120 ticks.
3057 */
3058 if (adapter->link_speed != SPEED_1000) {
047e0030 3059 new_val = 976;
6eb5a7f1 3060 goto set_itr_val;
9d5c8243 3061 }
047e0030
AD		 3062
3063 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3064 struct igb_ring *ring = q_vector->rx_ring;
3065 avg_wire_size = ring->total_bytes / ring->total_packets;
3066 }
3067
3068 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3069 struct igb_ring *ring = q_vector->tx_ring;
3070 avg_wire_size = max_t(u32, avg_wire_size,
3071 (ring->total_bytes /
3072 ring->total_packets));
3073 }
3074
3075 /* if avg_wire_size isn't set no work was done */
3076 if (!avg_wire_size)
3077 goto clear_counts;
9d5c8243 3078
6eb5a7f1
AD		 3079 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3080 avg_wire_size += 24;
3081
3082 /* Don't starve jumbo frames */
3083 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3084
6eb5a7f1
AD		 3085 /* Give a little boost to mid-size frames */
3086 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3087 new_val = avg_wire_size / 3;
3088 else
3089 new_val = avg_wire_size / 2;
9d5c8243 3090
6eb5a7f1 3091set_itr_val:
047e0030
AD		 3092 if (new_val != q_vector->itr_val) {
3093 q_vector->itr_val = new_val;
3094 q_vector->set_itr = 1;
9d5c8243 3095 }
6eb5a7f1 3096clear_counts:
047e0030
AD		 3097 if (q_vector->rx_ring) {
3098 q_vector->rx_ring->total_bytes = 0;
3099 q_vector->rx_ring->total_packets = 0;
3100 }
3101 if (q_vector->tx_ring) {
3102 q_vector->tx_ring->total_bytes = 0;
3103 q_vector->tx_ring->total_packets = 0;
3104 }
9d5c8243
AK		 3105}
3106
3107/**
3108 * igb_update_itr - update the dynamic ITR value based on statistics
3109 * Stores a new ITR value based on packets and byte
3110 * counts during the last interrupt. The advantage of per interrupt
3111 * computation is faster updates and more accurate ITR for the current
3112 * traffic pattern. Constants in this function were computed
3113 * based on theoretical maximum wire speed and thresholds were set based
3114 * on testing data as well as attempting to minimize response time
3115 * while increasing bulk throughput.
3116 * this functionality is controlled by the InterruptThrottleRate module
3117 * parameter (see igb_param.c)
3118 * NOTE: These calculations are only valid when operating in a single-
3119 * queue environment.
3120 * @adapter: pointer to adapter
047e0030 3121 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3122 * @packets: the number of packets during this measurement interval
3123 * @bytes: the number of bytes during this measurement interval
3124 **/
3125static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3126 int packets, int bytes)
3127{
3128 unsigned int retval = itr_setting;
3129
3130 if (packets == 0)
3131 goto update_itr_done;
3132
3133 switch (itr_setting) {
3134 case lowest_latency:
3135 /* handle TSO and jumbo frames */
3136 if (bytes/packets > 8000)
3137 retval = bulk_latency;
3138 else if ((packets < 5) && (bytes > 512))
3139 retval = low_latency;
3140 break;
3141 case low_latency: /* 50 usec aka 20000 ints/s */
3142 if (bytes > 10000) {
3143 /* this if handles the TSO accounting */
3144 if (bytes/packets > 8000) {
3145 retval = bulk_latency;
3146 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3147 retval = bulk_latency;
3148 } else if ((packets > 35)) {
3149 retval = lowest_latency;
3150 }
3151 } else if (bytes/packets > 2000) {
3152 retval = bulk_latency;
3153 } else if (packets <= 2 && bytes < 512) {
3154 retval = lowest_latency;
3155 }
3156 break;
3157 case bulk_latency: /* 250 usec aka 4000 ints/s */
3158 if (bytes > 25000) {
3159 if (packets > 35)
3160 retval = low_latency;
1e5c3d21 3161 } else if (bytes < 1500) {
9d5c8243
AK		 3162 retval = low_latency;
3163 }
3164 break;
3165 }
3166
3167update_itr_done:
3168 return retval;
3169}
3170
6eb5a7f1 3171static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3172{
047e0030 3173 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3174 u16 current_itr;
047e0030 3175 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3176
3177 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3178 if (adapter->link_speed != SPEED_1000) {
3179 current_itr = 0;
3180 new_itr = 4000;
3181 goto set_itr_now;
3182 }
3183
3184 adapter->rx_itr = igb_update_itr(adapter,
3185 adapter->rx_itr,
3186 adapter->rx_ring->total_packets,
3187 adapter->rx_ring->total_bytes);
9d5c8243 3188
047e0030
AD		 3189 adapter->tx_itr = igb_update_itr(adapter,
3190 adapter->tx_itr,
3191 adapter->tx_ring->total_packets,
3192 adapter->tx_ring->total_bytes);
3193 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3194
6eb5a7f1 3195 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3196 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3197 current_itr = low_latency;
3198
9d5c8243
AK		 3199 switch (current_itr) {
3200 /* counts and packets in update_itr are dependent on these numbers */
3201 case lowest_latency:
78b1f607 3202 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3203 break;
3204 case low_latency:
78b1f607 3205 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3206 break;
3207 case bulk_latency:
78b1f607 3208 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3209 break;
3210 default:
3211 break;
3212 }
3213
3214set_itr_now:
6eb5a7f1
AD		 3215 adapter->rx_ring->total_bytes = 0;
3216 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3217 adapter->tx_ring->total_bytes = 0;
3218 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3219
047e0030 3220 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3221 /* this attempts to bias the interrupt rate towards Bulk
3222 * by adding intermediate steps when interrupt rate is
3223 * increasing */
047e0030
AD		 3224 new_itr = new_itr > q_vector->itr_val ?
3225 max((new_itr * q_vector->itr_val) /
3226 (new_itr + (q_vector->itr_val >> 2)),
3227 new_itr) :
9d5c8243
AK		 3228 new_itr;
3229 /* Don't write the value here; it resets the adapter's
3230 * internal timer, and causes us to delay far longer than
3231 * we should between interrupts. Instead, we write the ITR
3232 * value at the beginning of the next interrupt so the timing
3233 * ends up being correct.
3234 */
047e0030
AD		 3235 q_vector->itr_val = new_itr;
3236 q_vector->set_itr = 1;
9d5c8243
AK		 3237 }
3238
3239 return;
3240}
3241
9d5c8243
AK		 3242#define IGB_TX_FLAGS_CSUM 0x00000001
3243#define IGB_TX_FLAGS_VLAN 0x00000002
3244#define IGB_TX_FLAGS_TSO 0x00000004
3245#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3246#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3247#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3248#define IGB_TX_FLAGS_VLAN_SHIFT 16
3249
3250static inline int igb_tso_adv(struct igb_adapter *adapter,
3251 struct igb_ring *tx_ring,
3252 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3253{
3254 struct e1000_adv_tx_context_desc *context_desc;
3255 unsigned int i;
3256 int err;
3257 struct igb_buffer *buffer_info;
3258 u32 info = 0, tu_cmd = 0;
3259 u32 mss_l4len_idx, l4len;
3260 *hdr_len = 0;
3261
3262 if (skb_header_cloned(skb)) {
3263 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3264 if (err)
3265 return err;
3266 }
3267
3268 l4len = tcp_hdrlen(skb);
3269 *hdr_len += l4len;
3270
3271 if (skb->protocol == htons(ETH_P_IP)) {
3272 struct iphdr *iph = ip_hdr(skb);
3273 iph->tot_len = 0;
3274 iph->check = 0;
3275 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3276 iph->daddr, 0,
3277 IPPROTO_TCP,
3278 0);
3279 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3280 ipv6_hdr(skb)->payload_len = 0;
3281 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3282 &ipv6_hdr(skb)->daddr,
3283 0, IPPROTO_TCP, 0);
3284 }
3285
3286 i = tx_ring->next_to_use;
3287
3288 buffer_info = &tx_ring->buffer_info[i];
3289 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3290 /* VLAN MACLEN IPLEN */
3291 if (tx_flags & IGB_TX_FLAGS_VLAN)
3292 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3293 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3294 *hdr_len += skb_network_offset(skb);
3295 info |= skb_network_header_len(skb);
3296 *hdr_len += skb_network_header_len(skb);
3297 context_desc->vlan_macip_lens = cpu_to_le32(info);
3298
3299 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3300 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3301
3302 if (skb->protocol == htons(ETH_P_IP))
3303 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3304 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3305
3306 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3307
3308 /* MSS L4LEN IDX */
3309 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3310 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3311
73cd78f1 3312 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3313 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3314 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3315
3316 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3317 context_desc->seqnum_seed = 0;
3318
3319 buffer_info->time_stamp = jiffies;
0e014cb1 3320 buffer_info->next_to_watch = i;
9d5c8243
AK		 3321 buffer_info->dma = 0;
3322 i++;
3323 if (i == tx_ring->count)
3324 i = 0;
3325
3326 tx_ring->next_to_use = i;
3327
3328 return true;
3329}
3330
3331static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3332 struct igb_ring *tx_ring,
3333 struct sk_buff *skb, u32 tx_flags)
3334{
3335 struct e1000_adv_tx_context_desc *context_desc;
3336 unsigned int i;
3337 struct igb_buffer *buffer_info;
3338 u32 info = 0, tu_cmd = 0;
3339
3340 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3341 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3342 i = tx_ring->next_to_use;
3343 buffer_info = &tx_ring->buffer_info[i];
3344 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3345
3346 if (tx_flags & IGB_TX_FLAGS_VLAN)
3347 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3348 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3349 if (skb->ip_summed == CHECKSUM_PARTIAL)
3350 info |= skb_network_header_len(skb);
3351
3352 context_desc->vlan_macip_lens = cpu_to_le32(info);
3353
3354 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3355
3356 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3357 __be16 protocol;
3358
3359 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3360 const struct vlan_ethhdr *vhdr =
3361 (const struct vlan_ethhdr*)skb->data;
3362
3363 protocol = vhdr->h_vlan_encapsulated_proto;
3364 } else {
3365 protocol = skb->protocol;
3366 }
3367
3368 switch (protocol) {
09640e63 3369 case cpu_to_be16(ETH_P_IP):
9d5c8243 3370 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3371 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3372 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3373 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3374 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3375 break;
09640e63 3376 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3377 /* XXX what about other V6 headers?? */
3378 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3379 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3380 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3381 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3382 break;
3383 default:
3384 if (unlikely(net_ratelimit()))
3385 dev_warn(&adapter->pdev->dev,
3386 "partial checksum but proto=%x!\n",
3387 skb->protocol);
3388 break;
3389 }
9d5c8243
AK		 3390 }
3391
3392 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3393 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3394 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3395 context_desc->mss_l4len_idx =
3396 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3397 else
3398 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3399
3400 buffer_info->time_stamp = jiffies;
0e014cb1 3401 buffer_info->next_to_watch = i;
9d5c8243
AK		 3402 buffer_info->dma = 0;
3403
3404 i++;
3405 if (i == tx_ring->count)
3406 i = 0;
3407 tx_ring->next_to_use = i;
3408
3409 return true;
3410 }
9d5c8243
AK		 3411 return false;
3412}
3413
3414#define IGB_MAX_TXD_PWR 16
3415#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3416
3417static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3418 struct igb_ring *tx_ring, struct sk_buff *skb,
3419 unsigned int first)
9d5c8243
AK		 3420{
3421 struct igb_buffer *buffer_info;
3422 unsigned int len = skb_headlen(skb);
3423 unsigned int count = 0, i;
3424 unsigned int f;
65689fef 3425 dma_addr_t *map;
9d5c8243
AK		 3426
3427 i = tx_ring->next_to_use;
3428
65689fef
AD		 3429 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3430 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3431 return 0;
3432 }
3433
3434 map = skb_shinfo(skb)->dma_maps;
3435
9d5c8243
AK		 3436 buffer_info = &tx_ring->buffer_info[i];
3437 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3438 buffer_info->length = len;
3439 /* set time_stamp *before* dma to help avoid a possible race */
3440 buffer_info->time_stamp = jiffies;
0e014cb1 3441 buffer_info->next_to_watch = i;
042a53a9 3442 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3443
3444 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3445 struct skb_frag_struct *frag;
3446
65689fef
AD		 3447 i++;
3448 if (i == tx_ring->count)
3449 i = 0;
3450
9d5c8243
AK		 3451 frag = &skb_shinfo(skb)->frags[f];
3452 len = frag->size;
3453
3454 buffer_info = &tx_ring->buffer_info[i];
3455 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3456 buffer_info->length = len;
3457 buffer_info->time_stamp = jiffies;
0e014cb1 3458 buffer_info->next_to_watch = i;
65689fef 3459 buffer_info->dma = map[count];
9d5c8243 3460 count++;
9d5c8243
AK		 3461 }
3462
9d5c8243 3463 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3464 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3465
042a53a9 3466 return count + 1;
9d5c8243
AK		 3467}
3468
3469static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3470 struct igb_ring *tx_ring,
3471 int tx_flags, int count, u32 paylen,
3472 u8 hdr_len)
3473{
3474 union e1000_adv_tx_desc *tx_desc = NULL;
3475 struct igb_buffer *buffer_info;
3476 u32 olinfo_status = 0, cmd_type_len;
3477 unsigned int i;
3478
3479 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3480 E1000_ADVTXD_DCMD_DEXT);
3481
3482 if (tx_flags & IGB_TX_FLAGS_VLAN)
3483 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3484
33af6bcc
PO		 3485 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3486 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3487
9d5c8243
AK		 3488 if (tx_flags & IGB_TX_FLAGS_TSO) {
3489 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3490
3491 /* insert tcp checksum */
3492 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3493
3494 /* insert ip checksum */
3495 if (tx_flags & IGB_TX_FLAGS_IPV4)
3496 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3497
3498 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3499 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3500 }
3501
7dfc16fa
AD		 3502 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3503 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3504 IGB_TX_FLAGS_VLAN)))
661086df 3505 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3506
3507 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3508
3509 i = tx_ring->next_to_use;
3510 while (count--) {
3511 buffer_info = &tx_ring->buffer_info[i];
3512 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3513 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3514 tx_desc->read.cmd_type_len =
3515 cpu_to_le32(cmd_type_len | buffer_info->length);
3516 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3517 i++;
3518 if (i == tx_ring->count)
3519 i = 0;
3520 }
3521
3522 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3523 /* Force memory writes to complete before letting h/w
3524 * know there are new descriptors to fetch. (Only
3525 * applicable for weak-ordered memory model archs,
3526 * such as IA-64). */
3527 wmb();
3528
3529 tx_ring->next_to_use = i;
3530 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3531 /* we need this if more than one processor can write to our tail
3532 * at a time, it syncronizes IO on IA64/Altix systems */
3533 mmiowb();
3534}
3535
3536static int __igb_maybe_stop_tx(struct net_device *netdev,
3537 struct igb_ring *tx_ring, int size)
3538{
3539 struct igb_adapter *adapter = netdev_priv(netdev);
3540
661086df 3541 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3542
9d5c8243
AK		 3543 /* Herbert's original patch had:
3544 * smp_mb__after_netif_stop_queue();
3545 * but since that doesn't exist yet, just open code it. */
3546 smp_mb();
3547
3548 /* We need to check again in a case another CPU has just
3549 * made room available. */
c493ea45 3550 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3551 return -EBUSY;
3552
3553 /* A reprieve! */
661086df 3554 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3555 ++adapter->restart_queue;
3556 return 0;
3557}
3558
3559static int igb_maybe_stop_tx(struct net_device *netdev,
3560 struct igb_ring *tx_ring, int size)
3561{
c493ea45 3562 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3563 return 0;
3564 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3565}
3566
3b29a56d
SH		 3567static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3568 struct net_device *netdev,
3569 struct igb_ring *tx_ring)
9d5c8243
AK		 3570{
3571 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3572 unsigned int first;
9d5c8243 3573 unsigned int tx_flags = 0;
9d5c8243 3574 u8 hdr_len = 0;
65689fef 3575 int count = 0;
9d5c8243 3576 int tso = 0;
33af6bcc 3577 union skb_shared_tx *shtx;
9d5c8243 3578
9d5c8243
AK		 3579 if (test_bit(__IGB_DOWN, &adapter->state)) {
3580 dev_kfree_skb_any(skb);
3581 return NETDEV_TX_OK;
3582 }
3583
3584 if (skb->len <= 0) {
3585 dev_kfree_skb_any(skb);
3586 return NETDEV_TX_OK;
3587 }
3588
9d5c8243
AK		 3589 /* need: 1 descriptor per page,
3590 * + 2 desc gap to keep tail from touching head,
3591 * + 1 desc for skb->data,
3592 * + 1 desc for context descriptor,
3593 * otherwise try next time */
3594 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3595 /* this is a hard error */
9d5c8243
AK		 3596 return NETDEV_TX_BUSY;
3597 }
33af6bcc
PO		 3598
3599 /*
3600 * TODO: check that there currently is no other packet with
3601 * time stamping in the queue
3602 *
3603 * When doing time stamping, keep the connection to the socket
3604 * a while longer: it is still needed by skb_hwtstamp_tx(),
3605 * called either in igb_tx_hwtstamp() or by our caller when
3606 * doing software time stamping.
3607 */
3608 shtx = skb_tx(skb);
3609 if (unlikely(shtx->hardware)) {
3610 shtx->in_progress = 1;
3611 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3612 }
9d5c8243
AK		 3613
3614 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3615 tx_flags |= IGB_TX_FLAGS_VLAN;
3616 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3617 }
3618
661086df
PWJ		 3619 if (skb->protocol == htons(ETH_P_IP))
3620 tx_flags |= IGB_TX_FLAGS_IPV4;
3621
0e014cb1 3622 first = tx_ring->next_to_use;
9d5c8243
AK		 3623 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3624 &hdr_len) : 0;
3625
3626 if (tso < 0) {
3627 dev_kfree_skb_any(skb);
9d5c8243
AK		 3628 return NETDEV_TX_OK;
3629 }
3630
3631 if (tso)
3632 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3633 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3634 (skb->ip_summed == CHECKSUM_PARTIAL))
3635 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3636
65689fef
AD		 3637 /*
3638 * count reflects descriptors mapped, if 0 then mapping error
3639 * has occured and we need to rewind the descriptor queue
3640 */
3641 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3642
3643 if (count) {
3644 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3645 skb->len, hdr_len);
65689fef
AD		 3646 /* Make sure there is space in the ring for the next send. */
3647 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3648 } else {
3649 dev_kfree_skb_any(skb);
3650 tx_ring->buffer_info[first].time_stamp = 0;
3651 tx_ring->next_to_use = first;
3652 }
9d5c8243 3653
9d5c8243
AK		 3654 return NETDEV_TX_OK;
3655}
3656
3b29a56d
SH		 3657static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3658 struct net_device *netdev)
9d5c8243
AK		 3659{
3660 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3661 struct igb_ring *tx_ring;
3662
661086df 3663 int r_idx = 0;
1bfaf07b 3664 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3665 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3666
3667 /* This goes back to the question of how to logically map a tx queue
3668 * to a flow. Right now, performance is impacted slightly negatively
3669 * if using multiple tx queues. If the stack breaks away from a
3670 * single qdisc implementation, we can look at this again. */
3b29a56d 3671 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3672}
3673
3674/**
3675 * igb_tx_timeout - Respond to a Tx Hang
3676 * @netdev: network interface device structure
3677 **/
3678static void igb_tx_timeout(struct net_device *netdev)
3679{
3680 struct igb_adapter *adapter = netdev_priv(netdev);
3681 struct e1000_hw *hw = &adapter->hw;
3682
3683 /* Do the reset outside of interrupt context */
3684 adapter->tx_timeout_count++;
3685 schedule_work(&adapter->reset_task);
265de409
AD		 3686 wr32(E1000_EICS,
3687 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3688}
3689
3690static void igb_reset_task(struct work_struct *work)
3691{
3692 struct igb_adapter *adapter;
3693 adapter = container_of(work, struct igb_adapter, reset_task);
3694
3695 igb_reinit_locked(adapter);
3696}
3697
3698/**
3699 * igb_get_stats - Get System Network Statistics
3700 * @netdev: network interface device structure
3701 *
3702 * Returns the address of the device statistics structure.
3703 * The statistics are actually updated from the timer callback.
3704 **/
73cd78f1 3705static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3706{
9d5c8243 3707 /* only return the current stats */
8d24e933 3708 return &netdev->stats;
9d5c8243
AK		 3709}
3710
3711/**
3712 * igb_change_mtu - Change the Maximum Transfer Unit
3713 * @netdev: network interface device structure
3714 * @new_mtu: new value for maximum frame size
3715 *
3716 * Returns 0 on success, negative on failure
3717 **/
3718static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3719{
3720 struct igb_adapter *adapter = netdev_priv(netdev);
3721 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3722
3723 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3724 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3725 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3726 return -EINVAL;
3727 }
3728
9d5c8243
AK		 3729 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3730 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3731 return -EINVAL;
3732 }
3733
3734 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3735 msleep(1);
73cd78f1 3736
9d5c8243
AK		 3737 /* igb_down has a dependency on max_frame_size */
3738 adapter->max_frame_size = max_frame;
3739 if (netif_running(netdev))
3740 igb_down(adapter);
3741
3742 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3743 * means we reserve 2 more, this pushes us to allocate from the next
3744 * larger slab size.
3745 * i.e. RXBUFFER_2048 --> size-4096 slab
3746 */
3747
7d95b717 3748 if (max_frame <= IGB_RXBUFFER_1024)
9d5c8243
AK		 3749 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3750 else if (max_frame <= IGB_RXBUFFER_2048)
3751 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3752 else
bf36c1a0
AD		 3753#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3754 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3755#else
3756 adapter->rx_buffer_len = PAGE_SIZE / 2;
3757#endif
e1739522 3758
9d5c8243
AK		 3759 /* adjust allocation if LPE protects us, and we aren't using SBP */
3760 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3761 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3762 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3763
3764 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3765 netdev->mtu, new_mtu);
3766 netdev->mtu = new_mtu;
3767
3768 if (netif_running(netdev))
3769 igb_up(adapter);
3770 else
3771 igb_reset(adapter);
3772
3773 clear_bit(__IGB_RESETTING, &adapter->state);
3774
3775 return 0;
3776}
3777
3778/**
3779 * igb_update_stats - Update the board statistics counters
3780 * @adapter: board private structure
3781 **/
3782
3783void igb_update_stats(struct igb_adapter *adapter)
3784{
8d24e933 3785 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3786 struct e1000_hw *hw = &adapter->hw;
3787 struct pci_dev *pdev = adapter->pdev;
3788 u16 phy_tmp;
3789
3790#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3791
3792 /*
3793 * Prevent stats update while adapter is being reset, or if the pci
3794 * connection is down.
3795 */
3796 if (adapter->link_speed == 0)
3797 return;
3798 if (pci_channel_offline(pdev))
3799 return;
3800
3801 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3802 adapter->stats.gprc += rd32(E1000_GPRC);
3803 adapter->stats.gorc += rd32(E1000_GORCL);
3804 rd32(E1000_GORCH); /* clear GORCL */
3805 adapter->stats.bprc += rd32(E1000_BPRC);
3806 adapter->stats.mprc += rd32(E1000_MPRC);
3807 adapter->stats.roc += rd32(E1000_ROC);
3808
3809 adapter->stats.prc64 += rd32(E1000_PRC64);
3810 adapter->stats.prc127 += rd32(E1000_PRC127);
3811 adapter->stats.prc255 += rd32(E1000_PRC255);
3812 adapter->stats.prc511 += rd32(E1000_PRC511);
3813 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3814 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3815 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3816 adapter->stats.sec += rd32(E1000_SEC);
3817
3818 adapter->stats.mpc += rd32(E1000_MPC);
3819 adapter->stats.scc += rd32(E1000_SCC);
3820 adapter->stats.ecol += rd32(E1000_ECOL);
3821 adapter->stats.mcc += rd32(E1000_MCC);
3822 adapter->stats.latecol += rd32(E1000_LATECOL);
3823 adapter->stats.dc += rd32(E1000_DC);
3824 adapter->stats.rlec += rd32(E1000_RLEC);
3825 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3826 adapter->stats.xontxc += rd32(E1000_XONTXC);
3827 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3828 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3829 adapter->stats.fcruc += rd32(E1000_FCRUC);
3830 adapter->stats.gptc += rd32(E1000_GPTC);
3831 adapter->stats.gotc += rd32(E1000_GOTCL);
3832 rd32(E1000_GOTCH); /* clear GOTCL */
3833 adapter->stats.rnbc += rd32(E1000_RNBC);
3834 adapter->stats.ruc += rd32(E1000_RUC);
3835 adapter->stats.rfc += rd32(E1000_RFC);
3836 adapter->stats.rjc += rd32(E1000_RJC);
3837 adapter->stats.tor += rd32(E1000_TORH);
3838 adapter->stats.tot += rd32(E1000_TOTH);
3839 adapter->stats.tpr += rd32(E1000_TPR);
3840
3841 adapter->stats.ptc64 += rd32(E1000_PTC64);
3842 adapter->stats.ptc127 += rd32(E1000_PTC127);
3843 adapter->stats.ptc255 += rd32(E1000_PTC255);
3844 adapter->stats.ptc511 += rd32(E1000_PTC511);
3845 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3846 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3847
3848 adapter->stats.mptc += rd32(E1000_MPTC);
3849 adapter->stats.bptc += rd32(E1000_BPTC);
3850
3851 /* used for adaptive IFS */
3852
3853 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3854 adapter->stats.tpt += hw->mac.tx_packet_delta;
3855 hw->mac.collision_delta = rd32(E1000_COLC);
3856 adapter->stats.colc += hw->mac.collision_delta;
3857
3858 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3859 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3860 adapter->stats.tncrs += rd32(E1000_TNCRS);
3861 adapter->stats.tsctc += rd32(E1000_TSCTC);
3862 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3863
3864 adapter->stats.iac += rd32(E1000_IAC);
3865 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3866 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3867 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3868 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3869 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3870 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3871 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3872 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3873
3874 /* Fill out the OS statistics structure */
8d24e933
AK		 3875 netdev->stats.multicast = adapter->stats.mprc;
3876 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3877
3878 /* Rx Errors */
3879
8c0ab70a
JDB		 3880 if (hw->mac.type != e1000_82575) {
3881 u32 rqdpc_tmp;
3ea73afa 3882 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3883 int i;
3884 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3885 * Queue Drop Packet Count) stats only gets incremented, if
3886 * the DROP_EN but it set (in the SRRCTL register for that
3887 * queue). If DROP_EN bit is NOT set, then the some what
3888 * equivalent count is stored in RNBC (not per queue basis).
3889 * Also note the drop count is due to lack of available
3890 * descriptors.
3891 */
3892 for (i = 0; i < adapter->num_rx_queues; i++) {
3893 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3894 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3895 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3896 }
8d24e933 3897 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3898 }
3899
3ea73afa
JDB		 3900 /* Note RNBC (Receive No Buffers Count) is an not an exact
3901 * drop count as the hardware FIFO might save the day. Thats
3902 * one of the reason for saving it in rx_fifo_errors, as its
3903 * potentially not a true drop.
3904 */
8d24e933 3905 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3906
9d5c8243 3907 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3908 * our own version based on RUC and ROC */
8d24e933 3909 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3910 adapter->stats.crcerrs + adapter->stats.algnerrc +
3911 adapter->stats.ruc + adapter->stats.roc +
3912 adapter->stats.cexterr;
8d24e933 3913 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3914 adapter->stats.roc;
8d24e933
AK		 3915 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3916 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3917 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3918
3919 /* Tx Errors */
8d24e933 3920 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3921 adapter->stats.latecol;
8d24e933
AK		 3922 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3923 netdev->stats.tx_window_errors = adapter->stats.latecol;
3924 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3925
3926 /* Tx Dropped needs to be maintained elsewhere */
3927
3928 /* Phy Stats */
3929 if (hw->phy.media_type == e1000_media_type_copper) {
3930 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3931 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3932 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3933 adapter->phy_stats.idle_errors += phy_tmp;
3934 }
3935 }
3936
3937 /* Management Stats */
3938 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3939 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3940 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3941}
3942
9d5c8243
AK		 3943static irqreturn_t igb_msix_other(int irq, void *data)
3944{
047e0030 3945 struct igb_adapter *adapter = data;
9d5c8243 3946 struct e1000_hw *hw = &adapter->hw;
844290e5 3947 u32 icr = rd32(E1000_ICR);
844290e5 3948 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3949
047e0030 3950 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3951 /* HW is reporting DMA is out of sync */
3952 adapter->stats.doosync++;
3953 }
eebbbdba 3954
4ae196df
AD		 3955 /* Check for a mailbox event */
3956 if (icr & E1000_ICR_VMMB)
3957 igb_msg_task(adapter);
3958
3959 if (icr & E1000_ICR_LSC) {
3960 hw->mac.get_link_status = 1;
3961 /* guard against interrupt when we're going down */
3962 if (!test_bit(__IGB_DOWN, &adapter->state))
3963 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3964 }
3965
3966 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3967 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3968
3969 return IRQ_HANDLED;
3970}
3971
047e0030 3972static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 3973{
047e0030 3974 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 3975
047e0030
AD		 3976 if (!q_vector->set_itr)
3977 return;
73cd78f1 3978
047e0030
AD		 3979 if (!itr_val)
3980 itr_val = 0x4;
661086df 3981
047e0030
AD		 3982 if (q_vector->itr_shift)
3983 itr_val |= itr_val << q_vector->itr_shift;
661086df 3984 else
047e0030 3985 itr_val |= 0x8000000;
661086df 3986
047e0030
AD		 3987 writel(itr_val, q_vector->itr_register);
3988 q_vector->set_itr = 0;
6eb5a7f1
AD		 3989}
3990
047e0030 3991static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 3992{
047e0030 3993 struct igb_q_vector *q_vector = data;
9d5c8243 3994
047e0030
AD		 3995 /* Write the ITR value calculated from the previous interrupt. */
3996 igb_write_itr(q_vector);
9d5c8243 3997
047e0030 3998 napi_schedule(&q_vector->napi);
844290e5 3999
047e0030 4000 return IRQ_HANDLED;
fe4506b6
JC		 4001}
4002
421e02f0 4003#ifdef CONFIG_IGB_DCA
047e0030 4004static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4005{
047e0030 4006 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4007 struct e1000_hw *hw = &adapter->hw;
4008 int cpu = get_cpu();
fe4506b6 4009
047e0030
AD		 4010 if (q_vector->cpu == cpu)
4011 goto out_no_update;
4012
4013 if (q_vector->tx_ring) {
4014 int q = q_vector->tx_ring->reg_idx;
4015 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4016 if (hw->mac.type == e1000_82575) {
4017 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4018 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4019 } else {
047e0030
AD		 4020 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4021 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4022 E1000_DCA_TXCTRL_CPUID_SHIFT;
4023 }
4024 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4025 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4026 }
4027 if (q_vector->rx_ring) {
4028 int q = q_vector->rx_ring->reg_idx;
4029 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4030 if (hw->mac.type == e1000_82575) {
2d064c06 4031 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4032 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4033 } else {
4034 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4035 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4036 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4037 }
fe4506b6
JC		 4038 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4039 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4040 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4041 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4042 }
047e0030
AD		 4043 q_vector->cpu = cpu;
4044out_no_update:
fe4506b6
JC		 4045 put_cpu();
4046}
4047
4048static void igb_setup_dca(struct igb_adapter *adapter)
4049{
7e0e99ef 4050 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4051 int i;
4052
7dfc16fa 4053 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4054 return;
4055
7e0e99ef
AD		 4056 /* Always use CB2 mode, difference is masked in the CB driver. */
4057 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4058
047e0030
AD		 4059 for (i = 0; i < adapter->num_q_vectors; i++) {
4060 struct igb_q_vector *q_vector = adapter->q_vector[i];
4061 q_vector->cpu = -1;
4062 igb_update_dca(q_vector);
fe4506b6
JC		 4063 }
4064}
4065
4066static int __igb_notify_dca(struct device *dev, void *data)
4067{
4068 struct net_device *netdev = dev_get_drvdata(dev);
4069 struct igb_adapter *adapter = netdev_priv(netdev);
4070 struct e1000_hw *hw = &adapter->hw;
4071 unsigned long event = *(unsigned long *)data;
4072
4073 switch (event) {
4074 case DCA_PROVIDER_ADD:
4075 /* if already enabled, don't do it again */
7dfc16fa 4076 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4077 break;
fe4506b6
JC		 4078 /* Always use CB2 mode, difference is masked
4079 * in the CB driver. */
cbd347ad 4080 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4081 if (dca_add_requester(dev) == 0) {
bbd98fe4 4082 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4083 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4084 igb_setup_dca(adapter);
4085 break;
4086 }
4087 /* Fall Through since DCA is disabled. */
4088 case DCA_PROVIDER_REMOVE:
7dfc16fa 4089 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4090 /* without this a class_device is left
047e0030 4091 * hanging around in the sysfs model */
fe4506b6
JC		 4092 dca_remove_requester(dev);
4093 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4094 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4095 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4096 }
4097 break;
4098 }
bbd98fe4 4099
fe4506b6 4100 return 0;
9d5c8243
AK		 4101}
4102
fe4506b6
JC		 4103static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4104 void *p)
4105{
4106 int ret_val;
4107
4108 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4109 __igb_notify_dca);
4110
4111 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4112}
421e02f0 4113#endif /* CONFIG_IGB_DCA */
9d5c8243 4114
4ae196df
AD		 4115static void igb_ping_all_vfs(struct igb_adapter *adapter)
4116{
4117 struct e1000_hw *hw = &adapter->hw;
4118 u32 ping;
4119 int i;
4120
4121 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4122 ping = E1000_PF_CONTROL_MSG;
4123 if (adapter->vf_data[i].clear_to_send)
4124 ping |= E1000_VT_MSGTYPE_CTS;
4125 igb_write_mbx(hw, &ping, 1, i);
4126 }
4127}
4128
4129static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4130 u32 *msgbuf, u32 vf)
4131{
4132 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4133 u16 *hash_list = (u16 *)&msgbuf[1];
4134 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4135 int i;
4136
4137 /* only up to 30 hash values supported */
4138 if (n > 30)
4139 n = 30;
4140
4141 /* salt away the number of multi cast addresses assigned
4142 * to this VF for later use to restore when the PF multi cast
4143 * list changes
4144 */
4145 vf_data->num_vf_mc_hashes = n;
4146
4147 /* VFs are limited to using the MTA hash table for their multicast
4148 * addresses */
4149 for (i = 0; i < n; i++)
a419aef8 4150 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4151
4152 /* Flush and reset the mta with the new values */
ff41f8dc 4153 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4154
4155 return 0;
4156}
4157
4158static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4159{
4160 struct e1000_hw *hw = &adapter->hw;
4161 struct vf_data_storage *vf_data;
4162 int i, j;
4163
4164 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4165 vf_data = &adapter->vf_data[i];
75f4f382 4166 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4167 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4168 }
4169}
4170
4171static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4172{
4173 struct e1000_hw *hw = &adapter->hw;
4174 u32 pool_mask, reg, vid;
4175 int i;
4176
4177 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4178
4179 /* Find the vlan filter for this id */
4180 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4181 reg = rd32(E1000_VLVF(i));
4182
4183 /* remove the vf from the pool */
4184 reg &= ~pool_mask;
4185
4186 /* if pool is empty then remove entry from vfta */
4187 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4188 (reg & E1000_VLVF_VLANID_ENABLE)) {
4189 reg = 0;
4190 vid = reg & E1000_VLVF_VLANID_MASK;
4191 igb_vfta_set(hw, vid, false);
4192 }
4193
4194 wr32(E1000_VLVF(i), reg);
4195 }
ae641bdc
AD		 4196
4197 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4198}
4199
4200static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4201{
4202 struct e1000_hw *hw = &adapter->hw;
4203 u32 reg, i;
4204
4205 /* It is an error to call this function when VFs are not enabled */
4206 if (!adapter->vfs_allocated_count)
4207 return -1;
4208
4209 /* Find the vlan filter for this id */
4210 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4211 reg = rd32(E1000_VLVF(i));
4212 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4213 vid == (reg & E1000_VLVF_VLANID_MASK))
4214 break;
4215 }
4216
4217 if (add) {
4218 if (i == E1000_VLVF_ARRAY_SIZE) {
4219 /* Did not find a matching VLAN ID entry that was
4220 * enabled. Search for a free filter entry, i.e.
4221 * one without the enable bit set
4222 */
4223 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4224 reg = rd32(E1000_VLVF(i));
4225 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4226 break;
4227 }
4228 }
4229 if (i < E1000_VLVF_ARRAY_SIZE) {
4230 /* Found an enabled/available entry */
4231 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4232
4233 /* if !enabled we need to set this up in vfta */
4234 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4235 /* add VID to filter table, if bit already set
4236 * PF must have added it outside of table */
4237 if (igb_vfta_set(hw, vid, true))
4238 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4239 adapter->vfs_allocated_count);
4ae196df
AD		 4240 reg |= E1000_VLVF_VLANID_ENABLE;
4241 }
cad6d05f
AD		 4242 reg &= ~E1000_VLVF_VLANID_MASK;
4243 reg |= vid;
4ae196df
AD		 4244
4245 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4246
4247 /* do not modify RLPML for PF devices */
4248 if (vf >= adapter->vfs_allocated_count)
4249 return 0;
4250
4251 if (!adapter->vf_data[vf].vlans_enabled) {
4252 u32 size;
4253 reg = rd32(E1000_VMOLR(vf));
4254 size = reg & E1000_VMOLR_RLPML_MASK;
4255 size += 4;
4256 reg &= ~E1000_VMOLR_RLPML_MASK;
4257 reg |= size;
4258 wr32(E1000_VMOLR(vf), reg);
4259 }
4260 adapter->vf_data[vf].vlans_enabled++;
4261
4ae196df
AD		 4262 return 0;
4263 }
4264 } else {
4265 if (i < E1000_VLVF_ARRAY_SIZE) {
4266 /* remove vf from the pool */
4267 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4268 /* if pool is empty then remove entry from vfta */
4269 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4270 reg = 0;
4271 igb_vfta_set(hw, vid, false);
4272 }
4273 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4274
4275 /* do not modify RLPML for PF devices */
4276 if (vf >= adapter->vfs_allocated_count)
4277 return 0;
4278
4279 adapter->vf_data[vf].vlans_enabled--;
4280 if (!adapter->vf_data[vf].vlans_enabled) {
4281 u32 size;
4282 reg = rd32(E1000_VMOLR(vf));
4283 size = reg & E1000_VMOLR_RLPML_MASK;
4284 size -= 4;
4285 reg &= ~E1000_VMOLR_RLPML_MASK;
4286 reg |= size;
4287 wr32(E1000_VMOLR(vf), reg);
4288 }
4ae196df
AD		 4289 return 0;
4290 }
4291 }
4292 return -1;
4293}
4294
4295static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4296{
4297 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4298 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4299
4300 return igb_vlvf_set(adapter, vid, add, vf);
4301}
4302
4303static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4304{
4305 struct e1000_hw *hw = &adapter->hw;
4306
4307 /* disable mailbox functionality for vf */
4308 adapter->vf_data[vf].clear_to_send = false;
4309
4310 /* reset offloads to defaults */
4311 igb_set_vmolr(hw, vf);
4312
4313 /* reset vlans for device */
4314 igb_clear_vf_vfta(adapter, vf);
4315
4316 /* reset multicast table array for vf */
4317 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4318
4319 /* Flush and reset the mta with the new values */
ff41f8dc 4320 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4321}
4322
4323static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4324{
4325 struct e1000_hw *hw = &adapter->hw;
4326 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4327 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4328 u32 reg, msgbuf[3];
4329 u8 *addr = (u8 *)(&msgbuf[1]);
4330
4331 /* process all the same items cleared in a function level reset */
4332 igb_vf_reset_event(adapter, vf);
4333
4334 /* set vf mac address */
26ad9178 4335 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4336
4337 /* enable transmit and receive for vf */
4338 reg = rd32(E1000_VFTE);
4339 wr32(E1000_VFTE, reg | (1 << vf));
4340 reg = rd32(E1000_VFRE);
4341 wr32(E1000_VFRE, reg | (1 << vf));
4342
4343 /* enable mailbox functionality for vf */
4344 adapter->vf_data[vf].clear_to_send = true;
4345
4346 /* reply to reset with ack and vf mac address */
4347 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4348 memcpy(addr, vf_mac, 6);
4349 igb_write_mbx(hw, msgbuf, 3, vf);
4350}
4351
4352static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4353{
4354 unsigned char *addr = (char *)&msg[1];
4355 int err = -1;
4356
4357 if (is_valid_ether_addr(addr))
4358 err = igb_set_vf_mac(adapter, vf, addr);
4359
4360 return err;
4361
4362}
4363
4364static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4365{
4366 struct e1000_hw *hw = &adapter->hw;
4367 u32 msg = E1000_VT_MSGTYPE_NACK;
4368
4369 /* if device isn't clear to send it shouldn't be reading either */
4370 if (!adapter->vf_data[vf].clear_to_send)
4371 igb_write_mbx(hw, &msg, 1, vf);
4372}
4373
4374
4375static void igb_msg_task(struct igb_adapter *adapter)
4376{
4377 struct e1000_hw *hw = &adapter->hw;
4378 u32 vf;
4379
4380 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4381 /* process any reset requests */
4382 if (!igb_check_for_rst(hw, vf)) {
4383 adapter->vf_data[vf].clear_to_send = false;
4384 igb_vf_reset_event(adapter, vf);
4385 }
4386
4387 /* process any messages pending */
4388 if (!igb_check_for_msg(hw, vf))
4389 igb_rcv_msg_from_vf(adapter, vf);
4390
4391 /* process any acks */
4392 if (!igb_check_for_ack(hw, vf))
4393 igb_rcv_ack_from_vf(adapter, vf);
4394
4395 }
4396}
4397
4398static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4399{
4400 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4401 u32 msgbuf[mbx_size];
4402 struct e1000_hw *hw = &adapter->hw;
4403 s32 retval;
4404
4405 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4406
4407 if (retval)
4408 dev_err(&adapter->pdev->dev,
4409 "Error receiving message from VF\n");
4410
4411 /* this is a message we already processed, do nothing */
4412 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4413 return retval;
4414
4415 /*
4416 * until the vf completes a reset it should not be
4417 * allowed to start any configuration.
4418 */
4419
4420 if (msgbuf[0] == E1000_VF_RESET) {
4421 igb_vf_reset_msg(adapter, vf);
4422
4423 return retval;
4424 }
4425
4426 if (!adapter->vf_data[vf].clear_to_send) {
4427 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4428 igb_write_mbx(hw, msgbuf, 1, vf);
4429 return retval;
4430 }
4431
4432 switch ((msgbuf[0] & 0xFFFF)) {
4433 case E1000_VF_SET_MAC_ADDR:
4434 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4435 break;
4436 case E1000_VF_SET_MULTICAST:
4437 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4438 break;
4439 case E1000_VF_SET_LPE:
4440 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4441 break;
4442 case E1000_VF_SET_VLAN:
4443 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4444 break;
4445 default:
4446 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4447 retval = -1;
4448 break;
4449 }
4450
4451 /* notify the VF of the results of what it sent us */
4452 if (retval)
4453 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4454 else
4455 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4456
4457 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4458
4459 igb_write_mbx(hw, msgbuf, 1, vf);
4460
4461 return retval;
4462}
4463
68d480c4
AD		 4464/**
4465 * igb_set_uta - Set unicast filter table address
4466 * @adapter: board private structure
4467 *
4468 * The unicast table address is a register array of 32-bit registers.
4469 * The table is meant to be used in a way similar to how the MTA is used
4470 * however due to certain limitations in the hardware it is necessary to
4471 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4472 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4473 **/
4474static void igb_set_uta(struct igb_adapter *adapter)
4475{
4476 struct e1000_hw *hw = &adapter->hw;
4477 int i;
4478
4479 /* The UTA table only exists on 82576 hardware and newer */
4480 if (hw->mac.type < e1000_82576)
4481 return;
4482
4483 /* we only need to do this if VMDq is enabled */
4484 if (!adapter->vfs_allocated_count)
4485 return;
4486
4487 for (i = 0; i < hw->mac.uta_reg_count; i++)
4488 array_wr32(E1000_UTA, i, ~0);
4489}
4490
9d5c8243
AK		 4491/**
4492 * igb_intr_msi - Interrupt Handler
4493 * @irq: interrupt number
4494 * @data: pointer to a network interface device structure
4495 **/
4496static irqreturn_t igb_intr_msi(int irq, void *data)
4497{
047e0030
AD		 4498 struct igb_adapter *adapter = data;
4499 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4500 struct e1000_hw *hw = &adapter->hw;
4501 /* read ICR disables interrupts using IAM */
4502 u32 icr = rd32(E1000_ICR);
4503
047e0030 4504 igb_write_itr(q_vector);
9d5c8243 4505
047e0030 4506 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4507 /* HW is reporting DMA is out of sync */
4508 adapter->stats.doosync++;
4509 }
4510
9d5c8243
AK		 4511 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4512 hw->mac.get_link_status = 1;
4513 if (!test_bit(__IGB_DOWN, &adapter->state))
4514 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4515 }
4516
047e0030 4517 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4518
4519 return IRQ_HANDLED;
4520}
4521
4522/**
4a3c6433 4523 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4524 * @irq: interrupt number
4525 * @data: pointer to a network interface device structure
4526 **/
4527static irqreturn_t igb_intr(int irq, void *data)
4528{
047e0030
AD		 4529 struct igb_adapter *adapter = data;
4530 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4531 struct e1000_hw *hw = &adapter->hw;
4532 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4533 * need for the IMC write */
4534 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4535 if (!icr)
4536 return IRQ_NONE; /* Not our interrupt */
4537
047e0030 4538 igb_write_itr(q_vector);
9d5c8243
AK		 4539
4540 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4541 * not set, then the adapter didn't send an interrupt */
4542 if (!(icr & E1000_ICR_INT_ASSERTED))
4543 return IRQ_NONE;
4544
047e0030 4545 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4546 /* HW is reporting DMA is out of sync */
4547 adapter->stats.doosync++;
4548 }
4549
9d5c8243
AK		 4550 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4551 hw->mac.get_link_status = 1;
4552 /* guard against interrupt when we're going down */
4553 if (!test_bit(__IGB_DOWN, &adapter->state))
4554 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4555 }
4556
047e0030 4557 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4558
4559 return IRQ_HANDLED;
4560}
4561
047e0030 4562static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4563{
047e0030 4564 struct igb_adapter *adapter = q_vector->adapter;
46544258 4565 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4566
46544258 4567 if (adapter->itr_setting & 3) {
047e0030 4568 if (!adapter->msix_entries)
6eb5a7f1 4569 igb_set_itr(adapter);
46544258 4570 else
047e0030 4571 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4572 }
4573
46544258
AD		 4574 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4575 if (adapter->msix_entries)
047e0030 4576 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4577 else
4578 igb_irq_enable(adapter);
4579 }
9d5c8243
AK		 4580}
4581
46544258
AD		 4582/**
4583 * igb_poll - NAPI Rx polling callback
4584 * @napi: napi polling structure
4585 * @budget: count of how many packets we should handle
4586 **/
4587static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4588{
047e0030
AD		 4589 struct igb_q_vector *q_vector = container_of(napi,
4590 struct igb_q_vector,
4591 napi);
4592 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4593
421e02f0 4594#ifdef CONFIG_IGB_DCA
047e0030
AD		 4595 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4596 igb_update_dca(q_vector);
fe4506b6 4597#endif
047e0030
AD		 4598 if (q_vector->tx_ring)
4599 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4600
047e0030
AD		 4601 if (q_vector->rx_ring)
4602 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4603
4604 if (!tx_clean_complete)
4605 work_done = budget;
46544258 4606
9d5c8243 4607 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4608 if (work_done < budget) {
288379f0 4609 napi_complete(napi);
047e0030 4610 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4611 }
4612
46544258 4613 return work_done;
9d5c8243 4614}
6d8126f9 4615
33af6bcc
PO		 4616/**
4617 * igb_hwtstamp - utility function which checks for TX time stamp
4618 * @adapter: board private structure
4619 * @skb: packet that was just sent
4620 *
4621 * If we were asked to do hardware stamping and such a time stamp is
4622 * available, then it must have been for this skb here because we only
4623 * allow only one such packet into the queue.
4624 */
4625static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4626{
4627 union skb_shared_tx *shtx = skb_tx(skb);
4628 struct e1000_hw *hw = &adapter->hw;
4629
4630 if (unlikely(shtx->hardware)) {
4631 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4632 if (valid) {
4633 u64 regval = rd32(E1000_TXSTMPL);
4634 u64 ns;
4635 struct skb_shared_hwtstamps shhwtstamps;
4636
4637 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4638 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4639 ns = timecounter_cyc2time(&adapter->clock,
4640 regval);
4641 timecompare_update(&adapter->compare, ns);
4642 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4643 shhwtstamps.syststamp =
4644 timecompare_transform(&adapter->compare, ns);
4645 skb_tstamp_tx(skb, &shhwtstamps);
4646 }
33af6bcc
PO		 4647 }
4648}
4649
9d5c8243
AK		 4650/**
4651 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4652 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4653 * returns true if ring is completely cleaned
4654 **/
047e0030 4655static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4656{
047e0030
AD		 4657 struct igb_adapter *adapter = q_vector->adapter;
4658 struct igb_ring *tx_ring = q_vector->tx_ring;
3b644cf6 4659 struct net_device *netdev = adapter->netdev;
0e014cb1 4660 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4661 struct igb_buffer *buffer_info;
4662 struct sk_buff *skb;
0e014cb1 4663 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4664 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4665 unsigned int i, eop, count = 0;
4666 bool cleaned = false;
9d5c8243 4667
9d5c8243 4668 i = tx_ring->next_to_clean;
0e014cb1
AD		 4669 eop = tx_ring->buffer_info[i].next_to_watch;
4670 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4671
4672 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4673 (count < tx_ring->count)) {
4674 for (cleaned = false; !cleaned; count++) {
4675 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4676 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4677 cleaned = (i == eop);
9d5c8243
AK		 4678 skb = buffer_info->skb;
4679
4680 if (skb) {
4681 unsigned int segs, bytecount;
4682 /* gso_segs is currently only valid for tcp */
4683 segs = skb_shinfo(skb)->gso_segs ?: 1;
4684 /* multiply data chunks by size of headers */
4685 bytecount = ((segs - 1) * skb_headlen(skb)) +
4686 skb->len;
4687 total_packets += segs;
4688 total_bytes += bytecount;
33af6bcc
PO		 4689
4690 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4691 }
4692
4693 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4694 tx_desc->wb.status = 0;
9d5c8243
AK		 4695
4696 i++;
4697 if (i == tx_ring->count)
4698 i = 0;
9d5c8243 4699 }
0e014cb1
AD		 4700 eop = tx_ring->buffer_info[i].next_to_watch;
4701 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4702 }
4703
9d5c8243
AK		 4704 tx_ring->next_to_clean = i;
4705
fc7d345d 4706 if (unlikely(count &&
9d5c8243 4707 netif_carrier_ok(netdev) &&
c493ea45 4708 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4709 /* Make sure that anybody stopping the queue after this
4710 * sees the new next_to_clean.
4711 */
4712 smp_mb();
661086df
PWJ		 4713 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4714 !(test_bit(__IGB_DOWN, &adapter->state))) {
4715 netif_wake_subqueue(netdev, tx_ring->queue_index);
4716 ++adapter->restart_queue;
4717 }
9d5c8243
AK		 4718 }
4719
4720 if (tx_ring->detect_tx_hung) {
4721 /* Detect a transmit hang in hardware, this serializes the
4722 * check with the clearing of time_stamp and movement of i */
4723 tx_ring->detect_tx_hung = false;
4724 if (tx_ring->buffer_info[i].time_stamp &&
4725 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4726 (adapter->tx_timeout_factor * HZ))
4727 && !(rd32(E1000_STATUS) &
4728 E1000_STATUS_TXOFF)) {
4729
9d5c8243
AK		 4730 /* detected Tx unit hang */
4731 dev_err(&adapter->pdev->dev,
4732 "Detected Tx Unit Hang\n"
2d064c06 4733 " Tx Queue <%d>\n"
9d5c8243
AK		 4734 " TDH <%x>\n"
4735 " TDT <%x>\n"
4736 " next_to_use <%x>\n"
4737 " next_to_clean <%x>\n"
9d5c8243
AK		 4738 "buffer_info[next_to_clean]\n"
4739 " time_stamp <%lx>\n"
0e014cb1 4740 " next_to_watch <%x>\n"
9d5c8243
AK		 4741 " jiffies <%lx>\n"
4742 " desc.status <%x>\n",
2d064c06 4743 tx_ring->queue_index,
9d5c8243
AK		 4744 readl(adapter->hw.hw_addr + tx_ring->head),
4745 readl(adapter->hw.hw_addr + tx_ring->tail),
4746 tx_ring->next_to_use,
4747 tx_ring->next_to_clean,
9d5c8243 4748 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4749 eop,
9d5c8243 4750 jiffies,
0e014cb1 4751 eop_desc->wb.status);
661086df 4752 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4753 }
4754 }
4755 tx_ring->total_bytes += total_bytes;
4756 tx_ring->total_packets += total_packets;
e21ed353
AD		 4757 tx_ring->tx_stats.bytes += total_bytes;
4758 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4759 netdev->stats.tx_bytes += total_bytes;
4760 netdev->stats.tx_packets += total_packets;
0e014cb1 4761 return (count < tx_ring->count);
9d5c8243
AK		 4762}
4763
9d5c8243
AK		 4764/**
4765 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4766 * @q_vector: structure containing interrupt and ring information
4767 * @skb: packet to send up
4768 * @vlan_tag: vlan tag for packet
9d5c8243 4769 **/
047e0030
AD		 4770static void igb_receive_skb(struct igb_q_vector *q_vector,
4771 struct sk_buff *skb,
4772 u16 vlan_tag)
4773{
4774 struct igb_adapter *adapter = q_vector->adapter;
4775
4776 if (vlan_tag)
4777 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4778 vlan_tag, skb);
182ff8df 4779 else
047e0030 4780 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4781}
4782
9d5c8243
AK		 4783static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4784 u32 status_err, struct sk_buff *skb)
4785{
4786 skb->ip_summed = CHECKSUM_NONE;
4787
4788 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4789 if ((status_err & E1000_RXD_STAT_IXSM) ||
4790 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4791 return;
4792 /* TCP/UDP checksum error bit is set */
4793 if (status_err &
4794 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4795 /*
4796 * work around errata with sctp packets where the TCPE aka
4797 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4798 * packets, (aka let the stack check the crc32c)
4799 */
4800 if (!((adapter->hw.mac.type == e1000_82576) &&
4801 (skb->len == 60)))
4802 adapter->hw_csum_err++;
9d5c8243 4803 /* let the stack verify checksum errors */
9d5c8243
AK		 4804 return;
4805 }
4806 /* It must be a TCP or UDP packet with a valid checksum */
4807 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4808 skb->ip_summed = CHECKSUM_UNNECESSARY;
4809
b9473560 4810 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4811}
4812
2d94d8ab
AD		 4813static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4814 union e1000_adv_rx_desc *rx_desc)
4815{
4816 /* HW will not DMA in data larger than the given buffer, even if it
4817 * parses the (NFS, of course) header to be larger. In that case, it
4818 * fills the header buffer and spills the rest into the page.
4819 */
4820 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4821 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4822 if (hlen > adapter->rx_ps_hdr_size)
4823 hlen = adapter->rx_ps_hdr_size;
4824 return hlen;
4825}
4826
047e0030
AD		 4827static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4828 int *work_done, int budget)
9d5c8243 4829{
047e0030 4830 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 4831 struct net_device *netdev = adapter->netdev;
047e0030 4832 struct igb_ring *rx_ring = q_vector->rx_ring;
33af6bcc 4833 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4834 struct pci_dev *pdev = adapter->pdev;
4835 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4836 struct igb_buffer *buffer_info , *next_buffer;
4837 struct sk_buff *skb;
9d5c8243
AK		 4838 bool cleaned = false;
4839 int cleaned_count = 0;
4840 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4841 unsigned int i;
2d94d8ab
AD		 4842 u32 staterr;
4843 u16 length;
047e0030 4844 u16 vlan_tag;
9d5c8243
AK		 4845
4846 i = rx_ring->next_to_clean;
69d3ca53 4847 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4848 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4850
4851 while (staterr & E1000_RXD_STAT_DD) {
4852 if (*work_done >= budget)
4853 break;
4854 (*work_done)++;
9d5c8243 4855
69d3ca53
AD		 4856 skb = buffer_info->skb;
4857 prefetch(skb->data - NET_IP_ALIGN);
4858 buffer_info->skb = NULL;
4859
4860 i++;
4861 if (i == rx_ring->count)
4862 i = 0;
4863 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4864 prefetch(next_rxd);
4865 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4866
4867 length = le16_to_cpu(rx_desc->wb.upper.length);
4868 cleaned = true;
4869 cleaned_count++;
4870
91615f76 4871 /* this is the fast path for the non-packet split case */
bf36c1a0
AD		 4872 if (!adapter->rx_ps_hdr_size) {
4873 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4874 adapter->rx_buffer_len,
bf36c1a0 4875 PCI_DMA_FROMDEVICE);
91615f76 4876 buffer_info->dma = 0;
bf36c1a0
AD		 4877 skb_put(skb, length);
4878 goto send_up;
9d5c8243
AK		 4879 }
4880
2d94d8ab
AD		 4881 if (buffer_info->dma) {
4882 u16 hlen = igb_get_hlen(adapter, rx_desc);
bf36c1a0 4883 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4884 adapter->rx_ps_hdr_size,
bf36c1a0 4885 PCI_DMA_FROMDEVICE);
91615f76 4886 buffer_info->dma = 0;
bf36c1a0
AD		 4887 skb_put(skb, hlen);
4888 }
4889
4890 if (length) {
9d5c8243 4891 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4892 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4893 buffer_info->page_dma = 0;
bf36c1a0
AD		 4894
4895 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4896 buffer_info->page,
4897 buffer_info->page_offset,
4898 length);
4899
4900 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4901 (page_count(buffer_info->page) != 1))
4902 buffer_info->page = NULL;
4903 else
4904 get_page(buffer_info->page);
9d5c8243
AK		 4905
4906 skb->len += length;
4907 skb->data_len += length;
9d5c8243 4908
bf36c1a0 4909 skb->truesize += length;
9d5c8243 4910 }
9d5c8243 4911
bf36c1a0 4912 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4913 buffer_info->skb = next_buffer->skb;
4914 buffer_info->dma = next_buffer->dma;
4915 next_buffer->skb = skb;
4916 next_buffer->dma = 0;
bf36c1a0
AD		 4917 goto next_desc;
4918 }
69d3ca53 4919send_up:
33af6bcc
PO		 4920 /*
4921 * If this bit is set, then the RX registers contain
4922 * the time stamp. No other packet will be time
4923 * stamped until we read these registers, so read the
4924 * registers to make them available again. Because
4925 * only one packet can be time stamped at a time, we
4926 * know that the register values must belong to this
4927 * one here and therefore we don't need to compare
4928 * any of the additional attributes stored for it.
4929 *
4930 * If nothing went wrong, then it should have a
4931 * skb_shared_tx that we can turn into a
4932 * skb_shared_hwtstamps.
4933 *
4934 * TODO: can time stamping be triggered (thus locking
4935 * the registers) without the packet reaching this point
4936 * here? In that case RX time stamping would get stuck.
4937 *
4938 * TODO: in "time stamp all packets" mode this bit is
4939 * not set. Need a global flag for this mode and then
4940 * always read the registers. Cannot be done without
4941 * a race condition.
4942 */
4943 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4944 u64 regval;
4945 u64 ns;
4946 struct skb_shared_hwtstamps *shhwtstamps =
4947 skb_hwtstamps(skb);
4948
4949 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4950 "igb: no RX time stamp available for time stamped packet");
4951 regval = rd32(E1000_RXSTMPL);
4952 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4953 ns = timecounter_cyc2time(&adapter->clock, regval);
4954 timecompare_update(&adapter->compare, ns);
4955 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4956 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4957 shhwtstamps->syststamp =
4958 timecompare_transform(&adapter->compare, ns);
4959 }
4960
9d5c8243
AK		 4961 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4962 dev_kfree_skb_irq(skb);
4963 goto next_desc;
4964 }
9d5c8243
AK		 4965
4966 total_bytes += skb->len;
4967 total_packets++;
4968
4969 igb_rx_checksum_adv(adapter, staterr, skb);
4970
4971 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 4972 skb_record_rx_queue(skb, rx_ring->queue_index);
4973
4974 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
4975 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 4976
047e0030 4977 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 4978
9d5c8243
AK		 4979next_desc:
4980 rx_desc->wb.upper.status_error = 0;
4981
4982 /* return some buffers to hardware, one at a time is too slow */
4983 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4984 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4985 cleaned_count = 0;
4986 }
4987
4988 /* use prefetched values */
4989 rx_desc = next_rxd;
4990 buffer_info = next_buffer;
9d5c8243
AK		 4991 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4992 }
bf36c1a0 4993
9d5c8243 4994 rx_ring->next_to_clean = i;
c493ea45 4995 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 4996
4997 if (cleaned_count)
3b644cf6 4998 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4999
5000 rx_ring->total_packets += total_packets;
5001 rx_ring->total_bytes += total_bytes;
5002 rx_ring->rx_stats.packets += total_packets;
5003 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5004 netdev->stats.rx_bytes += total_bytes;
5005 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5006 return cleaned;
5007}
5008
9d5c8243
AK		 5009/**
5010 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5011 * @adapter: address of board private structure
5012 **/
3b644cf6 5013static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 5014 int cleaned_count)
5015{
047e0030 5016 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243
AK		 5017 struct net_device *netdev = adapter->netdev;
5018 struct pci_dev *pdev = adapter->pdev;
5019 union e1000_adv_rx_desc *rx_desc;
5020 struct igb_buffer *buffer_info;
5021 struct sk_buff *skb;
5022 unsigned int i;
db761762 5023 int bufsz;
9d5c8243
AK		 5024
5025 i = rx_ring->next_to_use;
5026 buffer_info = &rx_ring->buffer_info[i];
5027
db761762
AD		 5028 if (adapter->rx_ps_hdr_size)
5029 bufsz = adapter->rx_ps_hdr_size;
5030 else
5031 bufsz = adapter->rx_buffer_len;
db761762 5032
9d5c8243
AK		 5033 while (cleaned_count--) {
5034 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5035
bf36c1a0 5036 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 5037 if (!buffer_info->page) {
bf36c1a0
AD		 5038 buffer_info->page = alloc_page(GFP_ATOMIC);
5039 if (!buffer_info->page) {
5040 adapter->alloc_rx_buff_failed++;
5041 goto no_buffers;
5042 }
5043 buffer_info->page_offset = 0;
5044 } else {
5045 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5046 }
5047 buffer_info->page_dma =
db761762 5048 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 5049 buffer_info->page_offset,
5050 PAGE_SIZE / 2,
9d5c8243
AK		 5051 PCI_DMA_FROMDEVICE);
5052 }
5053
5054 if (!buffer_info->skb) {
89d71a66 5055 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243
AK		 5056 if (!skb) {
5057 adapter->alloc_rx_buff_failed++;
5058 goto no_buffers;
5059 }
5060
9d5c8243
AK		 5061 buffer_info->skb = skb;
5062 buffer_info->dma = pci_map_single(pdev, skb->data,
5063 bufsz,
5064 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5065 }
5066 /* Refresh the desc even if buffer_addrs didn't change because
5067 * each write-back erases this info. */
5068 if (adapter->rx_ps_hdr_size) {
5069 rx_desc->read.pkt_addr =
5070 cpu_to_le64(buffer_info->page_dma);
5071 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5072 } else {
5073 rx_desc->read.pkt_addr =
5074 cpu_to_le64(buffer_info->dma);
5075 rx_desc->read.hdr_addr = 0;
5076 }
5077
5078 i++;
5079 if (i == rx_ring->count)
5080 i = 0;
5081 buffer_info = &rx_ring->buffer_info[i];
5082 }
5083
5084no_buffers:
5085 if (rx_ring->next_to_use != i) {
5086 rx_ring->next_to_use = i;
5087 if (i == 0)
5088 i = (rx_ring->count - 1);
5089 else
5090 i--;
5091
5092 /* Force memory writes to complete before letting h/w
5093 * know there are new descriptors to fetch. (Only
5094 * applicable for weak-ordered memory model archs,
5095 * such as IA-64). */
5096 wmb();
5097 writel(i, adapter->hw.hw_addr + rx_ring->tail);
5098 }
5099}
5100
5101/**
5102 * igb_mii_ioctl -
5103 * @netdev:
5104 * @ifreq:
5105 * @cmd:
5106 **/
5107static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5108{
5109 struct igb_adapter *adapter = netdev_priv(netdev);
5110 struct mii_ioctl_data *data = if_mii(ifr);
5111
5112 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5113 return -EOPNOTSUPP;
5114
5115 switch (cmd) {
5116 case SIOCGMIIPHY:
5117 data->phy_id = adapter->hw.phy.addr;
5118 break;
5119 case SIOCGMIIREG:
f5f4cf08
AD		 5120 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5121 &data->val_out))
9d5c8243
AK		 5122 return -EIO;
5123 break;
5124 case SIOCSMIIREG:
5125 default:
5126 return -EOPNOTSUPP;
5127 }
5128 return 0;
5129}
5130
c6cb090b
PO		 5131/**
5132 * igb_hwtstamp_ioctl - control hardware time stamping
5133 * @netdev:
5134 * @ifreq:
5135 * @cmd:
5136 *
33af6bcc
PO		 5137 * Outgoing time stamping can be enabled and disabled. Play nice and
5138 * disable it when requested, although it shouldn't case any overhead
5139 * when no packet needs it. At most one packet in the queue may be
5140 * marked for time stamping, otherwise it would be impossible to tell
5141 * for sure to which packet the hardware time stamp belongs.
5142 *
5143 * Incoming time stamping has to be configured via the hardware
5144 * filters. Not all combinations are supported, in particular event
5145 * type has to be specified. Matching the kind of event packet is
5146 * not supported, with the exception of "all V2 events regardless of
5147 * level 2 or 4".
5148 *
c6cb090b
PO		 5149 **/
5150static int igb_hwtstamp_ioctl(struct net_device *netdev,
5151 struct ifreq *ifr, int cmd)
5152{
33af6bcc
PO		 5153 struct igb_adapter *adapter = netdev_priv(netdev);
5154 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5155 struct hwtstamp_config config;
33af6bcc
PO		 5156 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5157 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5158 u32 tsync_rx_ctl_type = 0;
5159 u32 tsync_rx_cfg = 0;
5160 int is_l4 = 0;
5161 int is_l2 = 0;
5162 short port = 319; /* PTP */
5163 u32 regval;
c6cb090b
PO		 5164
5165 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5166 return -EFAULT;
5167
5168 /* reserved for future extensions */
5169 if (config.flags)
5170 return -EINVAL;
5171
33af6bcc
PO		 5172 switch (config.tx_type) {
5173 case HWTSTAMP_TX_OFF:
5174 tsync_tx_ctl_bit = 0;
5175 break;
5176 case HWTSTAMP_TX_ON:
5177 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5178 break;
5179 default:
5180 return -ERANGE;
5181 }
5182
5183 switch (config.rx_filter) {
5184 case HWTSTAMP_FILTER_NONE:
5185 tsync_rx_ctl_bit = 0;
5186 break;
5187 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5188 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5189 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5190 case HWTSTAMP_FILTER_ALL:
5191 /*
5192 * register TSYNCRXCFG must be set, therefore it is not
5193 * possible to time stamp both Sync and Delay_Req messages
5194 * => fall back to time stamping all packets
5195 */
5196 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5197 config.rx_filter = HWTSTAMP_FILTER_ALL;
5198 break;
5199 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5200 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5201 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5202 is_l4 = 1;
5203 break;
5204 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5205 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5206 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5207 is_l4 = 1;
5208 break;
5209 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5210 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5211 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5212 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5213 is_l2 = 1;
5214 is_l4 = 1;
5215 config.rx_filter = HWTSTAMP_FILTER_SOME;
5216 break;
5217 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5218 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5219 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5220 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5221 is_l2 = 1;
5222 is_l4 = 1;
5223 config.rx_filter = HWTSTAMP_FILTER_SOME;
5224 break;
5225 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5226 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5227 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5228 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5229 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5230 is_l2 = 1;
5231 break;
5232 default:
5233 return -ERANGE;
5234 }
5235
5236 /* enable/disable TX */
5237 regval = rd32(E1000_TSYNCTXCTL);
5238 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5239 wr32(E1000_TSYNCTXCTL, regval);
5240
5241 /* enable/disable RX, define which PTP packets are time stamped */
5242 regval = rd32(E1000_TSYNCRXCTL);
5243 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5244 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5245 wr32(E1000_TSYNCRXCTL, regval);
5246 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5247
5248 /*
5249 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5250 * (Ethertype to filter on)
5251 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5252 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5253 */
5254 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5255
5256 /* L4 Queue Filter[0]: only filter by source and destination port */
5257 wr32(E1000_SPQF0, htons(port));
5258 wr32(E1000_IMIREXT(0), is_l4 ?
5259 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5260 wr32(E1000_IMIR(0), is_l4 ?
5261 (htons(port)
5262 | (0<<16) /* immediate interrupt disabled */
5263 | 0 /* (1<<17) bit cleared: do not bypass
5264 destination port check */)
5265 : 0);
5266 wr32(E1000_FTQF0, is_l4 ?
5267 (0x11 /* UDP */
5268 | (1<<15) /* VF not compared */
5269 | (1<<27) /* Enable Timestamping */
5270 | (7<<28) /* only source port filter enabled,
5271 source/target address and protocol
5272 masked */)
5273 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5274 enabled */));
5275
5276 wrfl();
5277
5278 adapter->hwtstamp_config = config;
5279
5280 /* clear TX/RX time stamp registers, just to be sure */
5281 regval = rd32(E1000_TXSTMPH);
5282 regval = rd32(E1000_RXSTMPH);
c6cb090b 5283
33af6bcc
PO		 5284 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5285 -EFAULT : 0;
c6cb090b
PO		 5286}
5287
9d5c8243
AK		 5288/**
5289 * igb_ioctl -
5290 * @netdev:
5291 * @ifreq:
5292 * @cmd:
5293 **/
5294static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5295{
5296 switch (cmd) {
5297 case SIOCGMIIPHY:
5298 case SIOCGMIIREG:
5299 case SIOCSMIIREG:
5300 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5301 case SIOCSHWTSTAMP:
5302 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5303 default:
5304 return -EOPNOTSUPP;
5305 }
5306}
5307
009bc06e
AD		 5308s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5309{
5310 struct igb_adapter *adapter = hw->back;
5311 u16 cap_offset;
5312
5313 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5314 if (!cap_offset)
5315 return -E1000_ERR_CONFIG;
5316
5317 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5318
5319 return 0;
5320}
5321
5322s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5323{
5324 struct igb_adapter *adapter = hw->back;
5325 u16 cap_offset;
5326
5327 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5328 if (!cap_offset)
5329 return -E1000_ERR_CONFIG;
5330
5331 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5332
5333 return 0;
5334}
5335
9d5c8243
AK		 5336static void igb_vlan_rx_register(struct net_device *netdev,
5337 struct vlan_group *grp)
5338{
5339 struct igb_adapter *adapter = netdev_priv(netdev);
5340 struct e1000_hw *hw = &adapter->hw;
5341 u32 ctrl, rctl;
5342
5343 igb_irq_disable(adapter);
5344 adapter->vlgrp = grp;
5345
5346 if (grp) {
5347 /* enable VLAN tag insert/strip */
5348 ctrl = rd32(E1000_CTRL);
5349 ctrl |= E1000_CTRL_VME;
5350 wr32(E1000_CTRL, ctrl);
5351
5352 /* enable VLAN receive filtering */
5353 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5354 rctl &= ~E1000_RCTL_CFIEN;
5355 wr32(E1000_RCTL, rctl);
5356 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5357 } else {
5358 /* disable VLAN tag insert/strip */
5359 ctrl = rd32(E1000_CTRL);
5360 ctrl &= ~E1000_CTRL_VME;
5361 wr32(E1000_CTRL, ctrl);
5362
9d5c8243
AK		 5363 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5364 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5365 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5366 }
9d5c8243
AK		 5367 }
5368
e1739522
AD		 5369 igb_rlpml_set(adapter);
5370
9d5c8243
AK		 5371 if (!test_bit(__IGB_DOWN, &adapter->state))
5372 igb_irq_enable(adapter);
5373}
5374
5375static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5376{
5377 struct igb_adapter *adapter = netdev_priv(netdev);
5378 struct e1000_hw *hw = &adapter->hw;
4ae196df 5379 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5380
28b0759c 5381 if ((hw->mng_cookie.status &
9d5c8243
AK		 5382 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5383 (vid == adapter->mng_vlan_id))
5384 return;
4ae196df
AD		 5385
5386 /* add vid to vlvf if sr-iov is enabled,
5387 * if that fails add directly to filter table */
5388 if (igb_vlvf_set(adapter, vid, true, pf_id))
5389 igb_vfta_set(hw, vid, true);
5390
9d5c8243
AK		 5391}
5392
5393static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5394{
5395 struct igb_adapter *adapter = netdev_priv(netdev);
5396 struct e1000_hw *hw = &adapter->hw;
4ae196df 5397 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5398
5399 igb_irq_disable(adapter);
5400 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5401
5402 if (!test_bit(__IGB_DOWN, &adapter->state))
5403 igb_irq_enable(adapter);
5404
5405 if ((adapter->hw.mng_cookie.status &
5406 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5407 (vid == adapter->mng_vlan_id)) {
5408 /* release control to f/w */
5409 igb_release_hw_control(adapter);
5410 return;
5411 }
5412
4ae196df
AD		 5413 /* remove vid from vlvf if sr-iov is enabled,
5414 * if not in vlvf remove from vfta */
5415 if (igb_vlvf_set(adapter, vid, false, pf_id))
5416 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5417}
5418
5419static void igb_restore_vlan(struct igb_adapter *adapter)
5420{
5421 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5422
5423 if (adapter->vlgrp) {
5424 u16 vid;
5425 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5426 if (!vlan_group_get_device(adapter->vlgrp, vid))
5427 continue;
5428 igb_vlan_rx_add_vid(adapter->netdev, vid);
5429 }
5430 }
5431}
5432
5433int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5434{
5435 struct e1000_mac_info *mac = &adapter->hw.mac;
5436
5437 mac->autoneg = 0;
5438
9d5c8243
AK		 5439 switch (spddplx) {
5440 case SPEED_10 + DUPLEX_HALF:
5441 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5442 break;
5443 case SPEED_10 + DUPLEX_FULL:
5444 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5445 break;
5446 case SPEED_100 + DUPLEX_HALF:
5447 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5448 break;
5449 case SPEED_100 + DUPLEX_FULL:
5450 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5451 break;
5452 case SPEED_1000 + DUPLEX_FULL:
5453 mac->autoneg = 1;
5454 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5455 break;
5456 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5457 default:
5458 dev_err(&adapter->pdev->dev,
5459 "Unsupported Speed/Duplex configuration\n");
5460 return -EINVAL;
5461 }
5462 return 0;
5463}
5464
3fe7c4c9 5465static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5466{
5467 struct net_device *netdev = pci_get_drvdata(pdev);
5468 struct igb_adapter *adapter = netdev_priv(netdev);
5469 struct e1000_hw *hw = &adapter->hw;
2d064c06 5470 u32 ctrl, rctl, status;
9d5c8243
AK		 5471 u32 wufc = adapter->wol;
5472#ifdef CONFIG_PM
5473 int retval = 0;
5474#endif
5475
5476 netif_device_detach(netdev);
5477
a88f10ec
AD		 5478 if (netif_running(netdev))
5479 igb_close(netdev);
5480
047e0030 5481 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5482
5483#ifdef CONFIG_PM
5484 retval = pci_save_state(pdev);
5485 if (retval)
5486 return retval;
5487#endif
5488
5489 status = rd32(E1000_STATUS);
5490 if (status & E1000_STATUS_LU)
5491 wufc &= ~E1000_WUFC_LNKC;
5492
5493 if (wufc) {
5494 igb_setup_rctl(adapter);
ff41f8dc 5495 igb_set_rx_mode(netdev);
9d5c8243
AK		 5496
5497 /* turn on all-multi mode if wake on multicast is enabled */
5498 if (wufc & E1000_WUFC_MC) {
5499 rctl = rd32(E1000_RCTL);
5500 rctl |= E1000_RCTL_MPE;
5501 wr32(E1000_RCTL, rctl);
5502 }
5503
5504 ctrl = rd32(E1000_CTRL);
5505 /* advertise wake from D3Cold */
5506 #define E1000_CTRL_ADVD3WUC 0x00100000
5507 /* phy power management enable */
5508 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5509 ctrl |= E1000_CTRL_ADVD3WUC;
5510 wr32(E1000_CTRL, ctrl);
5511
9d5c8243
AK		 5512 /* Allow time for pending master requests to run */
5513 igb_disable_pcie_master(&adapter->hw);
5514
5515 wr32(E1000_WUC, E1000_WUC_PME_EN);
5516 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5517 } else {
5518 wr32(E1000_WUC, 0);
5519 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5520 }
5521
3fe7c4c9
RW		 5522 *enable_wake = wufc || adapter->en_mng_pt;
5523 if (!*enable_wake)
2fb02a26 5524 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5525
5526 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5527 * would have already happened in close and is redundant. */
5528 igb_release_hw_control(adapter);
5529
5530 pci_disable_device(pdev);
5531
9d5c8243
AK		 5532 return 0;
5533}
5534
5535#ifdef CONFIG_PM
3fe7c4c9
RW		 5536static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5537{
5538 int retval;
5539 bool wake;
5540
5541 retval = __igb_shutdown(pdev, &wake);
5542 if (retval)
5543 return retval;
5544
5545 if (wake) {
5546 pci_prepare_to_sleep(pdev);
5547 } else {
5548 pci_wake_from_d3(pdev, false);
5549 pci_set_power_state(pdev, PCI_D3hot);
5550 }
5551
5552 return 0;
5553}
5554
9d5c8243
AK		 5555static int igb_resume(struct pci_dev *pdev)
5556{
5557 struct net_device *netdev = pci_get_drvdata(pdev);
5558 struct igb_adapter *adapter = netdev_priv(netdev);
5559 struct e1000_hw *hw = &adapter->hw;
5560 u32 err;
5561
5562 pci_set_power_state(pdev, PCI_D0);
5563 pci_restore_state(pdev);
42bfd33a 5564
aed5dec3 5565 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5566 if (err) {
5567 dev_err(&pdev->dev,
5568 "igb: Cannot enable PCI device from suspend\n");
5569 return err;
5570 }
5571 pci_set_master(pdev);
5572
5573 pci_enable_wake(pdev, PCI_D3hot, 0);
5574 pci_enable_wake(pdev, PCI_D3cold, 0);
5575
047e0030 5576 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5577 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5578 return -ENOMEM;
9d5c8243
AK		 5579 }
5580
5581 /* e1000_power_up_phy(adapter); */
5582
5583 igb_reset(adapter);
a8564f03
AD		 5584
5585 /* let the f/w know that the h/w is now under the control of the
5586 * driver. */
5587 igb_get_hw_control(adapter);
5588
9d5c8243
AK		 5589 wr32(E1000_WUS, ~0);
5590
a88f10ec
AD		 5591 if (netif_running(netdev)) {
5592 err = igb_open(netdev);
5593 if (err)
5594 return err;
5595 }
9d5c8243
AK		 5596
5597 netif_device_attach(netdev);
5598
9d5c8243
AK		 5599 return 0;
5600}
5601#endif
5602
5603static void igb_shutdown(struct pci_dev *pdev)
5604{
3fe7c4c9
RW		 5605 bool wake;
5606
5607 __igb_shutdown(pdev, &wake);
5608
5609 if (system_state == SYSTEM_POWER_OFF) {
5610 pci_wake_from_d3(pdev, wake);
5611 pci_set_power_state(pdev, PCI_D3hot);
5612 }
9d5c8243
AK		 5613}
5614
5615#ifdef CONFIG_NET_POLL_CONTROLLER
5616/*
5617 * Polling 'interrupt' - used by things like netconsole to send skbs
5618 * without having to re-enable interrupts. It's not called while
5619 * the interrupt routine is executing.
5620 */
5621static void igb_netpoll(struct net_device *netdev)
5622{
5623 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5624 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5625 int i;
9d5c8243 5626
eebbbdba 5627 if (!adapter->msix_entries) {
047e0030 5628 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5629 igb_irq_disable(adapter);
047e0030 5630 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5631 return;
5632 }
9d5c8243 5633
047e0030
AD		 5634 for (i = 0; i < adapter->num_q_vectors; i++) {
5635 struct igb_q_vector *q_vector = adapter->q_vector[i];
5636 wr32(E1000_EIMC, q_vector->eims_value);
5637 napi_schedule(&q_vector->napi);
eebbbdba 5638 }
9d5c8243
AK		 5639}
5640#endif /* CONFIG_NET_POLL_CONTROLLER */
5641
5642/**
5643 * igb_io_error_detected - called when PCI error is detected
5644 * @pdev: Pointer to PCI device
5645 * @state: The current pci connection state
5646 *
5647 * This function is called after a PCI bus error affecting
5648 * this device has been detected.
5649 */
5650static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5651 pci_channel_state_t state)
5652{
5653 struct net_device *netdev = pci_get_drvdata(pdev);
5654 struct igb_adapter *adapter = netdev_priv(netdev);
5655
5656 netif_device_detach(netdev);
5657
59ed6eec
AD		 5658 if (state == pci_channel_io_perm_failure)
5659 return PCI_ERS_RESULT_DISCONNECT;
5660
9d5c8243
AK		 5661 if (netif_running(netdev))
5662 igb_down(adapter);
5663 pci_disable_device(pdev);
5664
5665 /* Request a slot slot reset. */
5666 return PCI_ERS_RESULT_NEED_RESET;
5667}
5668
5669/**
5670 * igb_io_slot_reset - called after the pci bus has been reset.
5671 * @pdev: Pointer to PCI device
5672 *
5673 * Restart the card from scratch, as if from a cold-boot. Implementation
5674 * resembles the first-half of the igb_resume routine.
5675 */
5676static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5677{
5678 struct net_device *netdev = pci_get_drvdata(pdev);
5679 struct igb_adapter *adapter = netdev_priv(netdev);
5680 struct e1000_hw *hw = &adapter->hw;
40a914fa 5681 pci_ers_result_t result;
42bfd33a 5682 int err;
9d5c8243 5683
aed5dec3 5684 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5685 dev_err(&pdev->dev,
5686 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5687 result = PCI_ERS_RESULT_DISCONNECT;
5688 } else {
5689 pci_set_master(pdev);
5690 pci_restore_state(pdev);
9d5c8243 5691
40a914fa
AD		 5692 pci_enable_wake(pdev, PCI_D3hot, 0);
5693 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5694
40a914fa
AD		 5695 igb_reset(adapter);
5696 wr32(E1000_WUS, ~0);
5697 result = PCI_ERS_RESULT_RECOVERED;
5698 }
9d5c8243 5699
ea943d41
JK		 5700 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5701 if (err) {
5702 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5703 "failed 0x%0x\n", err);
5704 /* non-fatal, continue */
5705 }
40a914fa
AD		 5706
5707 return result;
9d5c8243
AK		 5708}
5709
5710/**
5711 * igb_io_resume - called when traffic can start flowing again.
5712 * @pdev: Pointer to PCI device
5713 *
5714 * This callback is called when the error recovery driver tells us that
5715 * its OK to resume normal operation. Implementation resembles the
5716 * second-half of the igb_resume routine.
5717 */
5718static void igb_io_resume(struct pci_dev *pdev)
5719{
5720 struct net_device *netdev = pci_get_drvdata(pdev);
5721 struct igb_adapter *adapter = netdev_priv(netdev);
5722
9d5c8243
AK		 5723 if (netif_running(netdev)) {
5724 if (igb_up(adapter)) {
5725 dev_err(&pdev->dev, "igb_up failed after reset\n");
5726 return;
5727 }
5728 }
5729
5730 netif_device_attach(netdev);
5731
5732 /* let the f/w know that the h/w is now under the control of the
5733 * driver. */
5734 igb_get_hw_control(adapter);
9d5c8243
AK		 5735}
5736
26ad9178
AD		 5737static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5738 u8 qsel)
5739{
5740 u32 rar_low, rar_high;
5741 struct e1000_hw *hw = &adapter->hw;
5742
5743 /* HW expects these in little endian so we reverse the byte order
5744 * from network order (big endian) to little endian
5745 */
5746 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5747 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5748 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5749
5750 /* Indicate to hardware the Address is Valid. */
5751 rar_high |= E1000_RAH_AV;
5752
5753 if (hw->mac.type == e1000_82575)
5754 rar_high |= E1000_RAH_POOL_1 * qsel;
5755 else
5756 rar_high |= E1000_RAH_POOL_1 << qsel;
5757
5758 wr32(E1000_RAL(index), rar_low);
5759 wrfl();
5760 wr32(E1000_RAH(index), rar_high);
5761 wrfl();
5762}
5763
4ae196df
AD		 5764static int igb_set_vf_mac(struct igb_adapter *adapter,
5765 int vf, unsigned char *mac_addr)
5766{
5767 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5768 /* VF MAC addresses start at end of receive addresses and moves
5769 * torwards the first, as a result a collision should not be possible */
5770 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5771
37680117 5772 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5773
26ad9178 5774 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5775
5776 return 0;
5777}
5778
5779static void igb_vmm_control(struct igb_adapter *adapter)
5780{
5781 struct e1000_hw *hw = &adapter->hw;
5782 u32 reg_data;
5783
5784 if (!adapter->vfs_allocated_count)
5785 return;
5786
5787 /* VF's need PF reset indication before they
5788 * can send/receive mail */
5789 reg_data = rd32(E1000_CTRL_EXT);
5790 reg_data |= E1000_CTRL_EXT_PFRSTD;
5791 wr32(E1000_CTRL_EXT, reg_data);
5792
5793 igb_vmdq_set_loopback_pf(hw, true);
5794 igb_vmdq_set_replication_pf(hw, true);
5795}
5796
9d5c8243 5797/* igb_main.c */
Linux kernel - Deliverables
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