Commit | Line | Data |
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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/pagemap.h> | |
33 | #include <linux/netdevice.h> | |
9d5c8243 | 34 | #include <linux/ipv6.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
9d5c8243 AK |
36 | #include <net/checksum.h> |
37 | #include <net/ip6_checksum.h> | |
c6cb090b | 38 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
39 | #include <linux/mii.h> |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/pci.h> | |
c54106bb | 43 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
44 | #include <linux/delay.h> |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/if_ether.h> | |
40a914fa | 47 | #include <linux/aer.h> |
421e02f0 | 48 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
49 | #include <linux/dca.h> |
50 | #endif | |
9d5c8243 AK |
51 | #include "igb.h" |
52 | ||
55cac248 | 53 | #define DRV_VERSION "2.1.0-k2" |
9d5c8243 AK |
54 | char igb_driver_name[] = "igb"; |
55 | char igb_driver_version[] = DRV_VERSION; | |
56 | static const char igb_driver_string[] = | |
57 | "Intel(R) Gigabit Ethernet Network Driver"; | |
86d5d38f | 58 | static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation."; |
9d5c8243 | 59 | |
9d5c8243 AK |
60 | static const struct e1000_info *igb_info_tbl[] = { |
61 | [board_82575] = &e1000_82575_info, | |
62 | }; | |
63 | ||
a3aa1884 | 64 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
d2ba2ed8 AD |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, | |
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, | |
68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, | |
55cac248 AD |
69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
70 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
71 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, | |
72 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
73 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
2d064c06 | 74 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 75 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 76 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
77 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
78 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 79 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
b894fa26 | 80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
c8ea5ea9 | 81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
83 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
85 | /* required last entry */ | |
86 | {0, } | |
87 | }; | |
88 | ||
89 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
90 | ||
91 | void igb_reset(struct igb_adapter *); | |
92 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
93 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
94 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
95 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 96 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 AK |
97 | void igb_update_stats(struct igb_adapter *); |
98 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | |
99 | static void __devexit igb_remove(struct pci_dev *pdev); | |
100 | static int igb_sw_init(struct igb_adapter *); | |
101 | static int igb_open(struct net_device *); | |
102 | static int igb_close(struct net_device *); | |
103 | static void igb_configure_tx(struct igb_adapter *); | |
104 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
105 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
106 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
107 | static void igb_clean_tx_ring(struct igb_ring *); |
108 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 109 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
110 | static void igb_update_phy_info(unsigned long); |
111 | static void igb_watchdog(unsigned long); | |
112 | static void igb_watchdog_task(struct work_struct *); | |
b1a436c3 | 113 | static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); |
9d5c8243 AK |
114 | static struct net_device_stats *igb_get_stats(struct net_device *); |
115 | static int igb_change_mtu(struct net_device *, int); | |
116 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 117 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
118 | static irqreturn_t igb_intr(int irq, void *); |
119 | static irqreturn_t igb_intr_msi(int irq, void *); | |
120 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 121 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 122 | #ifdef CONFIG_IGB_DCA |
047e0030 | 123 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 124 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 125 | #endif /* CONFIG_IGB_DCA */ |
047e0030 | 126 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
661086df | 127 | static int igb_poll(struct napi_struct *, int); |
047e0030 | 128 | static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int); |
9d5c8243 AK |
129 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
130 | static void igb_tx_timeout(struct net_device *); | |
131 | static void igb_reset_task(struct work_struct *); | |
132 | static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |
133 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | |
134 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
135 | static void igb_restore_vlan(struct igb_adapter *); | |
26ad9178 | 136 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
137 | static void igb_ping_all_vfs(struct igb_adapter *); |
138 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 139 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 140 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 141 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
8151d294 WM |
142 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
143 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
144 | int vf, u16 vlan, u8 qos); | |
145 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); | |
146 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, | |
147 | struct ifla_vf_info *ivi); | |
9d5c8243 | 148 | |
9d5c8243 | 149 | #ifdef CONFIG_PM |
3fe7c4c9 | 150 | static int igb_suspend(struct pci_dev *, pm_message_t); |
9d5c8243 AK |
151 | static int igb_resume(struct pci_dev *); |
152 | #endif | |
153 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 154 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
155 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
156 | static struct notifier_block dca_notifier = { | |
157 | .notifier_call = igb_notify_dca, | |
158 | .next = NULL, | |
159 | .priority = 0 | |
160 | }; | |
161 | #endif | |
9d5c8243 AK |
162 | #ifdef CONFIG_NET_POLL_CONTROLLER |
163 | /* for netdump / net console */ | |
164 | static void igb_netpoll(struct net_device *); | |
165 | #endif | |
37680117 | 166 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
167 | static unsigned int max_vfs = 0; |
168 | module_param(max_vfs, uint, 0); | |
169 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
170 | "per physical function"); | |
171 | #endif /* CONFIG_PCI_IOV */ | |
172 | ||
9d5c8243 AK |
173 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
174 | pci_channel_state_t); | |
175 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
176 | static void igb_io_resume(struct pci_dev *); | |
177 | ||
178 | static struct pci_error_handlers igb_err_handler = { | |
179 | .error_detected = igb_io_error_detected, | |
180 | .slot_reset = igb_io_slot_reset, | |
181 | .resume = igb_io_resume, | |
182 | }; | |
183 | ||
184 | ||
185 | static struct pci_driver igb_driver = { | |
186 | .name = igb_driver_name, | |
187 | .id_table = igb_pci_tbl, | |
188 | .probe = igb_probe, | |
189 | .remove = __devexit_p(igb_remove), | |
190 | #ifdef CONFIG_PM | |
191 | /* Power Managment Hooks */ | |
192 | .suspend = igb_suspend, | |
193 | .resume = igb_resume, | |
194 | #endif | |
195 | .shutdown = igb_shutdown, | |
196 | .err_handler = &igb_err_handler | |
197 | }; | |
198 | ||
199 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
200 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
201 | MODULE_LICENSE("GPL"); | |
202 | MODULE_VERSION(DRV_VERSION); | |
203 | ||
c97ec42a TI |
204 | struct igb_reg_info { |
205 | u32 ofs; | |
206 | char *name; | |
207 | }; | |
208 | ||
209 | static const struct igb_reg_info igb_reg_info_tbl[] = { | |
210 | ||
211 | /* General Registers */ | |
212 | {E1000_CTRL, "CTRL"}, | |
213 | {E1000_STATUS, "STATUS"}, | |
214 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
215 | ||
216 | /* Interrupt Registers */ | |
217 | {E1000_ICR, "ICR"}, | |
218 | ||
219 | /* RX Registers */ | |
220 | {E1000_RCTL, "RCTL"}, | |
221 | {E1000_RDLEN(0), "RDLEN"}, | |
222 | {E1000_RDH(0), "RDH"}, | |
223 | {E1000_RDT(0), "RDT"}, | |
224 | {E1000_RXDCTL(0), "RXDCTL"}, | |
225 | {E1000_RDBAL(0), "RDBAL"}, | |
226 | {E1000_RDBAH(0), "RDBAH"}, | |
227 | ||
228 | /* TX Registers */ | |
229 | {E1000_TCTL, "TCTL"}, | |
230 | {E1000_TDBAL(0), "TDBAL"}, | |
231 | {E1000_TDBAH(0), "TDBAH"}, | |
232 | {E1000_TDLEN(0), "TDLEN"}, | |
233 | {E1000_TDH(0), "TDH"}, | |
234 | {E1000_TDT(0), "TDT"}, | |
235 | {E1000_TXDCTL(0), "TXDCTL"}, | |
236 | {E1000_TDFH, "TDFH"}, | |
237 | {E1000_TDFT, "TDFT"}, | |
238 | {E1000_TDFHS, "TDFHS"}, | |
239 | {E1000_TDFPC, "TDFPC"}, | |
240 | ||
241 | /* List Terminator */ | |
242 | {} | |
243 | }; | |
244 | ||
245 | /* | |
246 | * igb_regdump - register printout routine | |
247 | */ | |
248 | static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) | |
249 | { | |
250 | int n = 0; | |
251 | char rname[16]; | |
252 | u32 regs[8]; | |
253 | ||
254 | switch (reginfo->ofs) { | |
255 | case E1000_RDLEN(0): | |
256 | for (n = 0; n < 4; n++) | |
257 | regs[n] = rd32(E1000_RDLEN(n)); | |
258 | break; | |
259 | case E1000_RDH(0): | |
260 | for (n = 0; n < 4; n++) | |
261 | regs[n] = rd32(E1000_RDH(n)); | |
262 | break; | |
263 | case E1000_RDT(0): | |
264 | for (n = 0; n < 4; n++) | |
265 | regs[n] = rd32(E1000_RDT(n)); | |
266 | break; | |
267 | case E1000_RXDCTL(0): | |
268 | for (n = 0; n < 4; n++) | |
269 | regs[n] = rd32(E1000_RXDCTL(n)); | |
270 | break; | |
271 | case E1000_RDBAL(0): | |
272 | for (n = 0; n < 4; n++) | |
273 | regs[n] = rd32(E1000_RDBAL(n)); | |
274 | break; | |
275 | case E1000_RDBAH(0): | |
276 | for (n = 0; n < 4; n++) | |
277 | regs[n] = rd32(E1000_RDBAH(n)); | |
278 | break; | |
279 | case E1000_TDBAL(0): | |
280 | for (n = 0; n < 4; n++) | |
281 | regs[n] = rd32(E1000_RDBAL(n)); | |
282 | break; | |
283 | case E1000_TDBAH(0): | |
284 | for (n = 0; n < 4; n++) | |
285 | regs[n] = rd32(E1000_TDBAH(n)); | |
286 | break; | |
287 | case E1000_TDLEN(0): | |
288 | for (n = 0; n < 4; n++) | |
289 | regs[n] = rd32(E1000_TDLEN(n)); | |
290 | break; | |
291 | case E1000_TDH(0): | |
292 | for (n = 0; n < 4; n++) | |
293 | regs[n] = rd32(E1000_TDH(n)); | |
294 | break; | |
295 | case E1000_TDT(0): | |
296 | for (n = 0; n < 4; n++) | |
297 | regs[n] = rd32(E1000_TDT(n)); | |
298 | break; | |
299 | case E1000_TXDCTL(0): | |
300 | for (n = 0; n < 4; n++) | |
301 | regs[n] = rd32(E1000_TXDCTL(n)); | |
302 | break; | |
303 | default: | |
304 | printk(KERN_INFO "%-15s %08x\n", | |
305 | reginfo->name, rd32(reginfo->ofs)); | |
306 | return; | |
307 | } | |
308 | ||
309 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); | |
310 | printk(KERN_INFO "%-15s ", rname); | |
311 | for (n = 0; n < 4; n++) | |
312 | printk(KERN_CONT "%08x ", regs[n]); | |
313 | printk(KERN_CONT "\n"); | |
314 | } | |
315 | ||
316 | /* | |
317 | * igb_dump - Print registers, tx-rings and rx-rings | |
318 | */ | |
319 | static void igb_dump(struct igb_adapter *adapter) | |
320 | { | |
321 | struct net_device *netdev = adapter->netdev; | |
322 | struct e1000_hw *hw = &adapter->hw; | |
323 | struct igb_reg_info *reginfo; | |
324 | int n = 0; | |
325 | struct igb_ring *tx_ring; | |
326 | union e1000_adv_tx_desc *tx_desc; | |
327 | struct my_u0 { u64 a; u64 b; } *u0; | |
328 | struct igb_buffer *buffer_info; | |
329 | struct igb_ring *rx_ring; | |
330 | union e1000_adv_rx_desc *rx_desc; | |
331 | u32 staterr; | |
332 | int i = 0; | |
333 | ||
334 | if (!netif_msg_hw(adapter)) | |
335 | return; | |
336 | ||
337 | /* Print netdevice Info */ | |
338 | if (netdev) { | |
339 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
340 | printk(KERN_INFO "Device Name state " | |
341 | "trans_start last_rx\n"); | |
342 | printk(KERN_INFO "%-15s %016lX %016lX %016lX\n", | |
343 | netdev->name, | |
344 | netdev->state, | |
345 | netdev->trans_start, | |
346 | netdev->last_rx); | |
347 | } | |
348 | ||
349 | /* Print Registers */ | |
350 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
351 | printk(KERN_INFO " Register Name Value\n"); | |
352 | for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; | |
353 | reginfo->name; reginfo++) { | |
354 | igb_regdump(hw, reginfo); | |
355 | } | |
356 | ||
357 | /* Print TX Ring Summary */ | |
358 | if (!netdev || !netif_running(netdev)) | |
359 | goto exit; | |
360 | ||
361 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
362 | printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]" | |
363 | " leng ntw timestamp\n"); | |
364 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
365 | tx_ring = adapter->tx_ring[n]; | |
366 | buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; | |
367 | printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n", | |
368 | n, tx_ring->next_to_use, tx_ring->next_to_clean, | |
369 | (u64)buffer_info->dma, | |
370 | buffer_info->length, | |
371 | buffer_info->next_to_watch, | |
372 | (u64)buffer_info->time_stamp); | |
373 | } | |
374 | ||
375 | /* Print TX Rings */ | |
376 | if (!netif_msg_tx_done(adapter)) | |
377 | goto rx_ring_summary; | |
378 | ||
379 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
380 | ||
381 | /* Transmit Descriptor Formats | |
382 | * | |
383 | * Advanced Transmit Descriptor | |
384 | * +--------------------------------------------------------------+ | |
385 | * 0 | Buffer Address [63:0] | | |
386 | * +--------------------------------------------------------------+ | |
387 | * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | | |
388 | * +--------------------------------------------------------------+ | |
389 | * 63 46 45 40 39 38 36 35 32 31 24 15 0 | |
390 | */ | |
391 | ||
392 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
393 | tx_ring = adapter->tx_ring[n]; | |
394 | printk(KERN_INFO "------------------------------------\n"); | |
395 | printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
396 | printk(KERN_INFO "------------------------------------\n"); | |
397 | printk(KERN_INFO "T [desc] [address 63:0 ] " | |
398 | "[PlPOCIStDDM Ln] [bi->dma ] " | |
399 | "leng ntw timestamp bi->skb\n"); | |
400 | ||
401 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
402 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
403 | buffer_info = &tx_ring->buffer_info[i]; | |
404 | u0 = (struct my_u0 *)tx_desc; | |
405 | printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX" | |
406 | " %04X %3X %016llX %p", i, | |
407 | le64_to_cpu(u0->a), | |
408 | le64_to_cpu(u0->b), | |
409 | (u64)buffer_info->dma, | |
410 | buffer_info->length, | |
411 | buffer_info->next_to_watch, | |
412 | (u64)buffer_info->time_stamp, | |
413 | buffer_info->skb); | |
414 | if (i == tx_ring->next_to_use && | |
415 | i == tx_ring->next_to_clean) | |
416 | printk(KERN_CONT " NTC/U\n"); | |
417 | else if (i == tx_ring->next_to_use) | |
418 | printk(KERN_CONT " NTU\n"); | |
419 | else if (i == tx_ring->next_to_clean) | |
420 | printk(KERN_CONT " NTC\n"); | |
421 | else | |
422 | printk(KERN_CONT "\n"); | |
423 | ||
424 | if (netif_msg_pktdata(adapter) && buffer_info->dma != 0) | |
425 | print_hex_dump(KERN_INFO, "", | |
426 | DUMP_PREFIX_ADDRESS, | |
427 | 16, 1, phys_to_virt(buffer_info->dma), | |
428 | buffer_info->length, true); | |
429 | } | |
430 | } | |
431 | ||
432 | /* Print RX Rings Summary */ | |
433 | rx_ring_summary: | |
434 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
435 | printk(KERN_INFO "Queue [NTU] [NTC]\n"); | |
436 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
437 | rx_ring = adapter->rx_ring[n]; | |
438 | printk(KERN_INFO " %5d %5X %5X\n", n, | |
439 | rx_ring->next_to_use, rx_ring->next_to_clean); | |
440 | } | |
441 | ||
442 | /* Print RX Rings */ | |
443 | if (!netif_msg_rx_status(adapter)) | |
444 | goto exit; | |
445 | ||
446 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
447 | ||
448 | /* Advanced Receive Descriptor (Read) Format | |
449 | * 63 1 0 | |
450 | * +-----------------------------------------------------+ | |
451 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
452 | * +----------------------------------------------+------+ | |
453 | * 8 | Header Buffer Address [63:1] | DD | | |
454 | * +-----------------------------------------------------+ | |
455 | * | |
456 | * | |
457 | * Advanced Receive Descriptor (Write-Back) Format | |
458 | * | |
459 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
460 | * +------------------------------------------------------+ | |
461 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
462 | * | Checksum Ident | | | | Type | Type | | |
463 | * +------------------------------------------------------+ | |
464 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
465 | * +------------------------------------------------------+ | |
466 | * 63 48 47 32 31 20 19 0 | |
467 | */ | |
468 | ||
469 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
470 | rx_ring = adapter->rx_ring[n]; | |
471 | printk(KERN_INFO "------------------------------------\n"); | |
472 | printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
473 | printk(KERN_INFO "------------------------------------\n"); | |
474 | printk(KERN_INFO "R [desc] [ PktBuf A0] " | |
475 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " | |
476 | "<-- Adv Rx Read format\n"); | |
477 | printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] " | |
478 | "[vl er S cks ln] ---------------- [bi->skb] " | |
479 | "<-- Adv Rx Write-Back format\n"); | |
480 | ||
481 | for (i = 0; i < rx_ring->count; i++) { | |
482 | buffer_info = &rx_ring->buffer_info[i]; | |
483 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
484 | u0 = (struct my_u0 *)rx_desc; | |
485 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
486 | if (staterr & E1000_RXD_STAT_DD) { | |
487 | /* Descriptor Done */ | |
488 | printk(KERN_INFO "RWB[0x%03X] %016llX " | |
489 | "%016llX ---------------- %p", i, | |
490 | le64_to_cpu(u0->a), | |
491 | le64_to_cpu(u0->b), | |
492 | buffer_info->skb); | |
493 | } else { | |
494 | printk(KERN_INFO "R [0x%03X] %016llX " | |
495 | "%016llX %016llX %p", i, | |
496 | le64_to_cpu(u0->a), | |
497 | le64_to_cpu(u0->b), | |
498 | (u64)buffer_info->dma, | |
499 | buffer_info->skb); | |
500 | ||
501 | if (netif_msg_pktdata(adapter)) { | |
502 | print_hex_dump(KERN_INFO, "", | |
503 | DUMP_PREFIX_ADDRESS, | |
504 | 16, 1, | |
505 | phys_to_virt(buffer_info->dma), | |
506 | rx_ring->rx_buffer_len, true); | |
507 | if (rx_ring->rx_buffer_len | |
508 | < IGB_RXBUFFER_1024) | |
509 | print_hex_dump(KERN_INFO, "", | |
510 | DUMP_PREFIX_ADDRESS, | |
511 | 16, 1, | |
512 | phys_to_virt( | |
513 | buffer_info->page_dma + | |
514 | buffer_info->page_offset), | |
515 | PAGE_SIZE/2, true); | |
516 | } | |
517 | } | |
518 | ||
519 | if (i == rx_ring->next_to_use) | |
520 | printk(KERN_CONT " NTU\n"); | |
521 | else if (i == rx_ring->next_to_clean) | |
522 | printk(KERN_CONT " NTC\n"); | |
523 | else | |
524 | printk(KERN_CONT "\n"); | |
525 | ||
526 | } | |
527 | } | |
528 | ||
529 | exit: | |
530 | return; | |
531 | } | |
532 | ||
533 | ||
38c845c7 PO |
534 | /** |
535 | * igb_read_clock - read raw cycle counter (to be used by time counter) | |
536 | */ | |
537 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | |
538 | { | |
539 | struct igb_adapter *adapter = | |
540 | container_of(tc, struct igb_adapter, cycles); | |
541 | struct e1000_hw *hw = &adapter->hw; | |
c5b9bd5e AD |
542 | u64 stamp = 0; |
543 | int shift = 0; | |
38c845c7 | 544 | |
55cac248 AD |
545 | /* |
546 | * The timestamp latches on lowest register read. For the 82580 | |
547 | * the lowest register is SYSTIMR instead of SYSTIML. However we never | |
548 | * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it. | |
549 | */ | |
550 | if (hw->mac.type == e1000_82580) { | |
551 | stamp = rd32(E1000_SYSTIMR) >> 8; | |
552 | shift = IGB_82580_TSYNC_SHIFT; | |
553 | } | |
554 | ||
c5b9bd5e AD |
555 | stamp |= (u64)rd32(E1000_SYSTIML) << shift; |
556 | stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32); | |
38c845c7 PO |
557 | return stamp; |
558 | } | |
559 | ||
9d5c8243 | 560 | /** |
c041076a | 561 | * igb_get_hw_dev - return device |
9d5c8243 AK |
562 | * used by hardware layer to print debugging information |
563 | **/ | |
c041076a | 564 | struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
9d5c8243 AK |
565 | { |
566 | struct igb_adapter *adapter = hw->back; | |
c041076a | 567 | return adapter->netdev; |
9d5c8243 | 568 | } |
38c845c7 | 569 | |
9d5c8243 AK |
570 | /** |
571 | * igb_init_module - Driver Registration Routine | |
572 | * | |
573 | * igb_init_module is the first routine called when the driver is | |
574 | * loaded. All it does is register with the PCI subsystem. | |
575 | **/ | |
576 | static int __init igb_init_module(void) | |
577 | { | |
578 | int ret; | |
579 | printk(KERN_INFO "%s - version %s\n", | |
580 | igb_driver_string, igb_driver_version); | |
581 | ||
582 | printk(KERN_INFO "%s\n", igb_copyright); | |
583 | ||
421e02f0 | 584 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
585 | dca_register_notify(&dca_notifier); |
586 | #endif | |
bbd98fe4 | 587 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
588 | return ret; |
589 | } | |
590 | ||
591 | module_init(igb_init_module); | |
592 | ||
593 | /** | |
594 | * igb_exit_module - Driver Exit Cleanup Routine | |
595 | * | |
596 | * igb_exit_module is called just before the driver is removed | |
597 | * from memory. | |
598 | **/ | |
599 | static void __exit igb_exit_module(void) | |
600 | { | |
421e02f0 | 601 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
602 | dca_unregister_notify(&dca_notifier); |
603 | #endif | |
9d5c8243 AK |
604 | pci_unregister_driver(&igb_driver); |
605 | } | |
606 | ||
607 | module_exit(igb_exit_module); | |
608 | ||
26bc19ec AD |
609 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
610 | /** | |
611 | * igb_cache_ring_register - Descriptor ring to register mapping | |
612 | * @adapter: board private structure to initialize | |
613 | * | |
614 | * Once we know the feature-set enabled for the device, we'll cache | |
615 | * the register offset the descriptor ring is assigned to. | |
616 | **/ | |
617 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
618 | { | |
ee1b9f06 | 619 | int i = 0, j = 0; |
047e0030 | 620 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
621 | |
622 | switch (adapter->hw.mac.type) { | |
623 | case e1000_82576: | |
624 | /* The queues are allocated for virtualization such that VF 0 | |
625 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
626 | * In order to avoid collision we start at the first free queue | |
627 | * and continue consuming queues in the same sequence | |
628 | */ | |
ee1b9f06 | 629 | if (adapter->vfs_allocated_count) { |
a99955fc | 630 | for (; i < adapter->rss_queues; i++) |
3025a446 AD |
631 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
632 | Q_IDX_82576(i); | |
ee1b9f06 | 633 | } |
26bc19ec | 634 | case e1000_82575: |
55cac248 | 635 | case e1000_82580: |
d2ba2ed8 | 636 | case e1000_i350: |
26bc19ec | 637 | default: |
ee1b9f06 | 638 | for (; i < adapter->num_rx_queues; i++) |
3025a446 | 639 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
ee1b9f06 | 640 | for (; j < adapter->num_tx_queues; j++) |
3025a446 | 641 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
26bc19ec AD |
642 | break; |
643 | } | |
644 | } | |
645 | ||
047e0030 AD |
646 | static void igb_free_queues(struct igb_adapter *adapter) |
647 | { | |
3025a446 | 648 | int i; |
047e0030 | 649 | |
3025a446 AD |
650 | for (i = 0; i < adapter->num_tx_queues; i++) { |
651 | kfree(adapter->tx_ring[i]); | |
652 | adapter->tx_ring[i] = NULL; | |
653 | } | |
654 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
655 | kfree(adapter->rx_ring[i]); | |
656 | adapter->rx_ring[i] = NULL; | |
657 | } | |
047e0030 AD |
658 | adapter->num_rx_queues = 0; |
659 | adapter->num_tx_queues = 0; | |
660 | } | |
661 | ||
9d5c8243 AK |
662 | /** |
663 | * igb_alloc_queues - Allocate memory for all rings | |
664 | * @adapter: board private structure to initialize | |
665 | * | |
666 | * We allocate one ring per queue at run-time since we don't know the | |
667 | * number of queues at compile-time. | |
668 | **/ | |
669 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
670 | { | |
3025a446 | 671 | struct igb_ring *ring; |
9d5c8243 AK |
672 | int i; |
673 | ||
661086df | 674 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 AD |
675 | ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); |
676 | if (!ring) | |
677 | goto err; | |
68fd9910 | 678 | ring->count = adapter->tx_ring_count; |
661086df | 679 | ring->queue_index = i; |
59d71989 | 680 | ring->dev = &adapter->pdev->dev; |
e694e964 | 681 | ring->netdev = adapter->netdev; |
85ad76b2 AD |
682 | /* For 82575, context index must be unique per ring. */ |
683 | if (adapter->hw.mac.type == e1000_82575) | |
684 | ring->flags = IGB_RING_FLAG_TX_CTX_IDX; | |
3025a446 | 685 | adapter->tx_ring[i] = ring; |
661086df | 686 | } |
85ad76b2 | 687 | |
9d5c8243 | 688 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3025a446 AD |
689 | ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); |
690 | if (!ring) | |
691 | goto err; | |
68fd9910 | 692 | ring->count = adapter->rx_ring_count; |
844290e5 | 693 | ring->queue_index = i; |
59d71989 | 694 | ring->dev = &adapter->pdev->dev; |
e694e964 | 695 | ring->netdev = adapter->netdev; |
4c844851 | 696 | ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
85ad76b2 AD |
697 | ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */ |
698 | /* set flag indicating ring supports SCTP checksum offload */ | |
699 | if (adapter->hw.mac.type >= e1000_82576) | |
700 | ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM; | |
3025a446 | 701 | adapter->rx_ring[i] = ring; |
9d5c8243 | 702 | } |
26bc19ec AD |
703 | |
704 | igb_cache_ring_register(adapter); | |
9d5c8243 | 705 | |
047e0030 | 706 | return 0; |
a88f10ec | 707 | |
047e0030 AD |
708 | err: |
709 | igb_free_queues(adapter); | |
d1a8c9e1 | 710 | |
047e0030 | 711 | return -ENOMEM; |
a88f10ec AD |
712 | } |
713 | ||
9d5c8243 | 714 | #define IGB_N0_QUEUE -1 |
047e0030 | 715 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 AK |
716 | { |
717 | u32 msixbm = 0; | |
047e0030 | 718 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 719 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 | 720 | u32 ivar, index; |
047e0030 AD |
721 | int rx_queue = IGB_N0_QUEUE; |
722 | int tx_queue = IGB_N0_QUEUE; | |
723 | ||
724 | if (q_vector->rx_ring) | |
725 | rx_queue = q_vector->rx_ring->reg_idx; | |
726 | if (q_vector->tx_ring) | |
727 | tx_queue = q_vector->tx_ring->reg_idx; | |
2d064c06 AD |
728 | |
729 | switch (hw->mac.type) { | |
730 | case e1000_82575: | |
9d5c8243 AK |
731 | /* The 82575 assigns vectors using a bitmask, which matches the |
732 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
733 | or more queues to a vector, we write the appropriate bits | |
734 | into the MSIXBM register for that vector. */ | |
047e0030 | 735 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 736 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 737 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 738 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
feeb2721 AD |
739 | if (!adapter->msix_entries && msix_vector == 0) |
740 | msixbm |= E1000_EIMS_OTHER; | |
9d5c8243 | 741 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 742 | q_vector->eims_value = msixbm; |
2d064c06 AD |
743 | break; |
744 | case e1000_82576: | |
26bc19ec | 745 | /* 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
746 | Each queue has a single entry in the table to which we write |
747 | a vector number along with a "valid" bit. Sadly, the layout | |
748 | of the table is somewhat counterintuitive. */ | |
749 | if (rx_queue > IGB_N0_QUEUE) { | |
047e0030 | 750 | index = (rx_queue & 0x7); |
2d064c06 | 751 | ivar = array_rd32(E1000_IVAR0, index); |
047e0030 | 752 | if (rx_queue < 8) { |
26bc19ec AD |
753 | /* vector goes into low byte of register */ |
754 | ivar = ivar & 0xFFFFFF00; | |
755 | ivar |= msix_vector | E1000_IVAR_VALID; | |
047e0030 AD |
756 | } else { |
757 | /* vector goes into third byte of register */ | |
758 | ivar = ivar & 0xFF00FFFF; | |
759 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
2d064c06 | 760 | } |
2d064c06 AD |
761 | array_wr32(E1000_IVAR0, index, ivar); |
762 | } | |
763 | if (tx_queue > IGB_N0_QUEUE) { | |
047e0030 | 764 | index = (tx_queue & 0x7); |
2d064c06 | 765 | ivar = array_rd32(E1000_IVAR0, index); |
047e0030 | 766 | if (tx_queue < 8) { |
26bc19ec AD |
767 | /* vector goes into second byte of register */ |
768 | ivar = ivar & 0xFFFF00FF; | |
769 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
047e0030 AD |
770 | } else { |
771 | /* vector goes into high byte of register */ | |
772 | ivar = ivar & 0x00FFFFFF; | |
773 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
2d064c06 | 774 | } |
2d064c06 AD |
775 | array_wr32(E1000_IVAR0, index, ivar); |
776 | } | |
047e0030 | 777 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 778 | break; |
55cac248 | 779 | case e1000_82580: |
d2ba2ed8 | 780 | case e1000_i350: |
55cac248 AD |
781 | /* 82580 uses the same table-based approach as 82576 but has fewer |
782 | entries as a result we carry over for queues greater than 4. */ | |
783 | if (rx_queue > IGB_N0_QUEUE) { | |
784 | index = (rx_queue >> 1); | |
785 | ivar = array_rd32(E1000_IVAR0, index); | |
786 | if (rx_queue & 0x1) { | |
787 | /* vector goes into third byte of register */ | |
788 | ivar = ivar & 0xFF00FFFF; | |
789 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
790 | } else { | |
791 | /* vector goes into low byte of register */ | |
792 | ivar = ivar & 0xFFFFFF00; | |
793 | ivar |= msix_vector | E1000_IVAR_VALID; | |
794 | } | |
795 | array_wr32(E1000_IVAR0, index, ivar); | |
796 | } | |
797 | if (tx_queue > IGB_N0_QUEUE) { | |
798 | index = (tx_queue >> 1); | |
799 | ivar = array_rd32(E1000_IVAR0, index); | |
800 | if (tx_queue & 0x1) { | |
801 | /* vector goes into high byte of register */ | |
802 | ivar = ivar & 0x00FFFFFF; | |
803 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
804 | } else { | |
805 | /* vector goes into second byte of register */ | |
806 | ivar = ivar & 0xFFFF00FF; | |
807 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
808 | } | |
809 | array_wr32(E1000_IVAR0, index, ivar); | |
810 | } | |
811 | q_vector->eims_value = 1 << msix_vector; | |
812 | break; | |
2d064c06 AD |
813 | default: |
814 | BUG(); | |
815 | break; | |
816 | } | |
26b39276 AD |
817 | |
818 | /* add q_vector eims value to global eims_enable_mask */ | |
819 | adapter->eims_enable_mask |= q_vector->eims_value; | |
820 | ||
821 | /* configure q_vector to set itr on first interrupt */ | |
822 | q_vector->set_itr = 1; | |
9d5c8243 AK |
823 | } |
824 | ||
825 | /** | |
826 | * igb_configure_msix - Configure MSI-X hardware | |
827 | * | |
828 | * igb_configure_msix sets up the hardware to properly | |
829 | * generate MSI-X interrupts. | |
830 | **/ | |
831 | static void igb_configure_msix(struct igb_adapter *adapter) | |
832 | { | |
833 | u32 tmp; | |
834 | int i, vector = 0; | |
835 | struct e1000_hw *hw = &adapter->hw; | |
836 | ||
837 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
838 | |
839 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
840 | switch (hw->mac.type) { |
841 | case e1000_82575: | |
9d5c8243 AK |
842 | tmp = rd32(E1000_CTRL_EXT); |
843 | /* enable MSI-X PBA support*/ | |
844 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
845 | ||
846 | /* Auto-Mask interrupts upon ICR read. */ | |
847 | tmp |= E1000_CTRL_EXT_EIAME; | |
848 | tmp |= E1000_CTRL_EXT_IRCA; | |
849 | ||
850 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
851 | |
852 | /* enable msix_other interrupt */ | |
853 | array_wr32(E1000_MSIXBM(0), vector++, | |
854 | E1000_EIMS_OTHER); | |
844290e5 | 855 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 856 | |
2d064c06 AD |
857 | break; |
858 | ||
859 | case e1000_82576: | |
55cac248 | 860 | case e1000_82580: |
d2ba2ed8 | 861 | case e1000_i350: |
047e0030 AD |
862 | /* Turn on MSI-X capability first, or our settings |
863 | * won't stick. And it will take days to debug. */ | |
864 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
865 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | |
866 | E1000_GPIE_NSICR); | |
867 | ||
868 | /* enable msix_other interrupt */ | |
869 | adapter->eims_other = 1 << vector; | |
2d064c06 | 870 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 871 | |
047e0030 | 872 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
873 | break; |
874 | default: | |
875 | /* do nothing, since nothing else supports MSI-X */ | |
876 | break; | |
877 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
878 | |
879 | adapter->eims_enable_mask |= adapter->eims_other; | |
880 | ||
26b39276 AD |
881 | for (i = 0; i < adapter->num_q_vectors; i++) |
882 | igb_assign_vector(adapter->q_vector[i], vector++); | |
047e0030 | 883 | |
9d5c8243 AK |
884 | wrfl(); |
885 | } | |
886 | ||
887 | /** | |
888 | * igb_request_msix - Initialize MSI-X interrupts | |
889 | * | |
890 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
891 | * kernel. | |
892 | **/ | |
893 | static int igb_request_msix(struct igb_adapter *adapter) | |
894 | { | |
895 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 896 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
897 | int i, err = 0, vector = 0; |
898 | ||
047e0030 | 899 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 900 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 AD |
901 | if (err) |
902 | goto out; | |
903 | vector++; | |
904 | ||
905 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
906 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
907 | ||
908 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); | |
909 | ||
910 | if (q_vector->rx_ring && q_vector->tx_ring) | |
911 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, | |
912 | q_vector->rx_ring->queue_index); | |
913 | else if (q_vector->tx_ring) | |
914 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, | |
915 | q_vector->tx_ring->queue_index); | |
916 | else if (q_vector->rx_ring) | |
917 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, | |
918 | q_vector->rx_ring->queue_index); | |
9d5c8243 | 919 | else |
047e0030 AD |
920 | sprintf(q_vector->name, "%s-unused", netdev->name); |
921 | ||
9d5c8243 | 922 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 923 | igb_msix_ring, 0, q_vector->name, |
047e0030 | 924 | q_vector); |
9d5c8243 AK |
925 | if (err) |
926 | goto out; | |
9d5c8243 AK |
927 | vector++; |
928 | } | |
929 | ||
9d5c8243 AK |
930 | igb_configure_msix(adapter); |
931 | return 0; | |
932 | out: | |
933 | return err; | |
934 | } | |
935 | ||
936 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
937 | { | |
938 | if (adapter->msix_entries) { | |
939 | pci_disable_msix(adapter->pdev); | |
940 | kfree(adapter->msix_entries); | |
941 | adapter->msix_entries = NULL; | |
047e0030 | 942 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 943 | pci_disable_msi(adapter->pdev); |
047e0030 | 944 | } |
9d5c8243 AK |
945 | } |
946 | ||
047e0030 AD |
947 | /** |
948 | * igb_free_q_vectors - Free memory allocated for interrupt vectors | |
949 | * @adapter: board private structure to initialize | |
950 | * | |
951 | * This function frees the memory allocated to the q_vectors. In addition if | |
952 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
953 | * to freeing the q_vector. | |
954 | **/ | |
955 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
956 | { | |
957 | int v_idx; | |
958 | ||
959 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | |
960 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
961 | adapter->q_vector[v_idx] = NULL; | |
fe0592b4 NN |
962 | if (!q_vector) |
963 | continue; | |
047e0030 AD |
964 | netif_napi_del(&q_vector->napi); |
965 | kfree(q_vector); | |
966 | } | |
967 | adapter->num_q_vectors = 0; | |
968 | } | |
969 | ||
970 | /** | |
971 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts | |
972 | * | |
973 | * This function resets the device so that it has 0 rx queues, tx queues, and | |
974 | * MSI-X interrupts allocated. | |
975 | */ | |
976 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
977 | { | |
978 | igb_free_queues(adapter); | |
979 | igb_free_q_vectors(adapter); | |
980 | igb_reset_interrupt_capability(adapter); | |
981 | } | |
9d5c8243 AK |
982 | |
983 | /** | |
984 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
985 | * | |
986 | * Attempt to configure interrupts using the best available | |
987 | * capabilities of the hardware and kernel. | |
988 | **/ | |
989 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |
990 | { | |
991 | int err; | |
992 | int numvecs, i; | |
993 | ||
83b7180d | 994 | /* Number of supported queues. */ |
a99955fc | 995 | adapter->num_rx_queues = adapter->rss_queues; |
5fa8517f GR |
996 | if (adapter->vfs_allocated_count) |
997 | adapter->num_tx_queues = 1; | |
998 | else | |
999 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 1000 | |
047e0030 AD |
1001 | /* start with one vector for every rx queue */ |
1002 | numvecs = adapter->num_rx_queues; | |
1003 | ||
3ad2f3fb | 1004 | /* if tx handler is separate add 1 for every tx queue */ |
a99955fc AD |
1005 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
1006 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
1007 | |
1008 | /* store the number of vectors reserved for queues */ | |
1009 | adapter->num_q_vectors = numvecs; | |
1010 | ||
1011 | /* add 1 vector for link status interrupts */ | |
1012 | numvecs++; | |
9d5c8243 AK |
1013 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
1014 | GFP_KERNEL); | |
1015 | if (!adapter->msix_entries) | |
1016 | goto msi_only; | |
1017 | ||
1018 | for (i = 0; i < numvecs; i++) | |
1019 | adapter->msix_entries[i].entry = i; | |
1020 | ||
1021 | err = pci_enable_msix(adapter->pdev, | |
1022 | adapter->msix_entries, | |
1023 | numvecs); | |
1024 | if (err == 0) | |
34a20e89 | 1025 | goto out; |
9d5c8243 AK |
1026 | |
1027 | igb_reset_interrupt_capability(adapter); | |
1028 | ||
1029 | /* If we can't do MSI-X, try MSI */ | |
1030 | msi_only: | |
2a3abf6d AD |
1031 | #ifdef CONFIG_PCI_IOV |
1032 | /* disable SR-IOV for non MSI-X configurations */ | |
1033 | if (adapter->vf_data) { | |
1034 | struct e1000_hw *hw = &adapter->hw; | |
1035 | /* disable iov and allow time for transactions to clear */ | |
1036 | pci_disable_sriov(adapter->pdev); | |
1037 | msleep(500); | |
1038 | ||
1039 | kfree(adapter->vf_data); | |
1040 | adapter->vf_data = NULL; | |
1041 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
1042 | msleep(100); | |
1043 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
1044 | } | |
1045 | #endif | |
4fc82adf | 1046 | adapter->vfs_allocated_count = 0; |
a99955fc | 1047 | adapter->rss_queues = 1; |
4fc82adf | 1048 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 1049 | adapter->num_rx_queues = 1; |
661086df | 1050 | adapter->num_tx_queues = 1; |
047e0030 | 1051 | adapter->num_q_vectors = 1; |
9d5c8243 | 1052 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1053 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 1054 | out: |
661086df | 1055 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 1056 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
9d5c8243 AK |
1057 | } |
1058 | ||
047e0030 AD |
1059 | /** |
1060 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors | |
1061 | * @adapter: board private structure to initialize | |
1062 | * | |
1063 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
1064 | * return -ENOMEM. | |
1065 | **/ | |
1066 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) | |
1067 | { | |
1068 | struct igb_q_vector *q_vector; | |
1069 | struct e1000_hw *hw = &adapter->hw; | |
1070 | int v_idx; | |
1071 | ||
1072 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | |
1073 | q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL); | |
1074 | if (!q_vector) | |
1075 | goto err_out; | |
1076 | q_vector->adapter = adapter; | |
047e0030 AD |
1077 | q_vector->itr_register = hw->hw_addr + E1000_EITR(0); |
1078 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
1079 | netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64); |
1080 | adapter->q_vector[v_idx] = q_vector; | |
1081 | } | |
1082 | return 0; | |
1083 | ||
1084 | err_out: | |
fe0592b4 | 1085 | igb_free_q_vectors(adapter); |
047e0030 AD |
1086 | return -ENOMEM; |
1087 | } | |
1088 | ||
1089 | static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter, | |
1090 | int ring_idx, int v_idx) | |
1091 | { | |
3025a446 | 1092 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; |
047e0030 | 1093 | |
3025a446 | 1094 | q_vector->rx_ring = adapter->rx_ring[ring_idx]; |
047e0030 | 1095 | q_vector->rx_ring->q_vector = q_vector; |
4fc82adf AD |
1096 | q_vector->itr_val = adapter->rx_itr_setting; |
1097 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
1098 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
1099 | } |
1100 | ||
1101 | static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter, | |
1102 | int ring_idx, int v_idx) | |
1103 | { | |
3025a446 | 1104 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; |
047e0030 | 1105 | |
3025a446 | 1106 | q_vector->tx_ring = adapter->tx_ring[ring_idx]; |
047e0030 | 1107 | q_vector->tx_ring->q_vector = q_vector; |
4fc82adf AD |
1108 | q_vector->itr_val = adapter->tx_itr_setting; |
1109 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
1110 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
1111 | } |
1112 | ||
1113 | /** | |
1114 | * igb_map_ring_to_vector - maps allocated queues to vectors | |
1115 | * | |
1116 | * This function maps the recently allocated queues to vectors. | |
1117 | **/ | |
1118 | static int igb_map_ring_to_vector(struct igb_adapter *adapter) | |
1119 | { | |
1120 | int i; | |
1121 | int v_idx = 0; | |
1122 | ||
1123 | if ((adapter->num_q_vectors < adapter->num_rx_queues) || | |
1124 | (adapter->num_q_vectors < adapter->num_tx_queues)) | |
1125 | return -ENOMEM; | |
1126 | ||
1127 | if (adapter->num_q_vectors >= | |
1128 | (adapter->num_rx_queues + adapter->num_tx_queues)) { | |
1129 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1130 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | |
1131 | for (i = 0; i < adapter->num_tx_queues; i++) | |
1132 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | |
1133 | } else { | |
1134 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1135 | if (i < adapter->num_tx_queues) | |
1136 | igb_map_tx_ring_to_vector(adapter, i, v_idx); | |
1137 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | |
1138 | } | |
1139 | for (; i < adapter->num_tx_queues; i++) | |
1140 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | |
1141 | } | |
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | /** | |
1146 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors | |
1147 | * | |
1148 | * This function initializes the interrupts and allocates all of the queues. | |
1149 | **/ | |
1150 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter) | |
1151 | { | |
1152 | struct pci_dev *pdev = adapter->pdev; | |
1153 | int err; | |
1154 | ||
1155 | igb_set_interrupt_capability(adapter); | |
1156 | ||
1157 | err = igb_alloc_q_vectors(adapter); | |
1158 | if (err) { | |
1159 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
1160 | goto err_alloc_q_vectors; | |
1161 | } | |
1162 | ||
1163 | err = igb_alloc_queues(adapter); | |
1164 | if (err) { | |
1165 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
1166 | goto err_alloc_queues; | |
1167 | } | |
1168 | ||
1169 | err = igb_map_ring_to_vector(adapter); | |
1170 | if (err) { | |
1171 | dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n"); | |
1172 | goto err_map_queues; | |
1173 | } | |
1174 | ||
1175 | ||
1176 | return 0; | |
1177 | err_map_queues: | |
1178 | igb_free_queues(adapter); | |
1179 | err_alloc_queues: | |
1180 | igb_free_q_vectors(adapter); | |
1181 | err_alloc_q_vectors: | |
1182 | igb_reset_interrupt_capability(adapter); | |
1183 | return err; | |
1184 | } | |
1185 | ||
9d5c8243 AK |
1186 | /** |
1187 | * igb_request_irq - initialize interrupts | |
1188 | * | |
1189 | * Attempts to configure interrupts using the best available | |
1190 | * capabilities of the hardware and kernel. | |
1191 | **/ | |
1192 | static int igb_request_irq(struct igb_adapter *adapter) | |
1193 | { | |
1194 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 1195 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
1196 | int err = 0; |
1197 | ||
1198 | if (adapter->msix_entries) { | |
1199 | err = igb_request_msix(adapter); | |
844290e5 | 1200 | if (!err) |
9d5c8243 | 1201 | goto request_done; |
9d5c8243 | 1202 | /* fall back to MSI */ |
047e0030 | 1203 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 1204 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1205 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1206 | igb_free_all_tx_resources(adapter); |
1207 | igb_free_all_rx_resources(adapter); | |
047e0030 | 1208 | adapter->num_tx_queues = 1; |
9d5c8243 | 1209 | adapter->num_rx_queues = 1; |
047e0030 AD |
1210 | adapter->num_q_vectors = 1; |
1211 | err = igb_alloc_q_vectors(adapter); | |
1212 | if (err) { | |
1213 | dev_err(&pdev->dev, | |
1214 | "Unable to allocate memory for vectors\n"); | |
1215 | goto request_done; | |
1216 | } | |
1217 | err = igb_alloc_queues(adapter); | |
1218 | if (err) { | |
1219 | dev_err(&pdev->dev, | |
1220 | "Unable to allocate memory for queues\n"); | |
1221 | igb_free_q_vectors(adapter); | |
1222 | goto request_done; | |
1223 | } | |
1224 | igb_setup_all_tx_resources(adapter); | |
1225 | igb_setup_all_rx_resources(adapter); | |
844290e5 | 1226 | } else { |
feeb2721 | 1227 | igb_assign_vector(adapter->q_vector[0], 0); |
9d5c8243 | 1228 | } |
844290e5 | 1229 | |
7dfc16fa | 1230 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
a0607fd3 | 1231 | err = request_irq(adapter->pdev->irq, igb_intr_msi, 0, |
047e0030 | 1232 | netdev->name, adapter); |
9d5c8243 AK |
1233 | if (!err) |
1234 | goto request_done; | |
047e0030 | 1235 | |
9d5c8243 AK |
1236 | /* fall back to legacy interrupts */ |
1237 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 1238 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1239 | } |
1240 | ||
a0607fd3 | 1241 | err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 1242 | netdev->name, adapter); |
9d5c8243 | 1243 | |
6cb5e577 | 1244 | if (err) |
9d5c8243 AK |
1245 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
1246 | err); | |
9d5c8243 AK |
1247 | |
1248 | request_done: | |
1249 | return err; | |
1250 | } | |
1251 | ||
1252 | static void igb_free_irq(struct igb_adapter *adapter) | |
1253 | { | |
9d5c8243 AK |
1254 | if (adapter->msix_entries) { |
1255 | int vector = 0, i; | |
1256 | ||
047e0030 | 1257 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 1258 | |
047e0030 AD |
1259 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1260 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1261 | free_irq(adapter->msix_entries[vector++].vector, | |
1262 | q_vector); | |
1263 | } | |
1264 | } else { | |
1265 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 1266 | } |
9d5c8243 AK |
1267 | } |
1268 | ||
1269 | /** | |
1270 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
1271 | * @adapter: board private structure | |
1272 | **/ | |
1273 | static void igb_irq_disable(struct igb_adapter *adapter) | |
1274 | { | |
1275 | struct e1000_hw *hw = &adapter->hw; | |
1276 | ||
25568a53 AD |
1277 | /* |
1278 | * we need to be careful when disabling interrupts. The VFs are also | |
1279 | * mapped into these registers and so clearing the bits can cause | |
1280 | * issues on the VF drivers so we only need to clear what we set | |
1281 | */ | |
9d5c8243 | 1282 | if (adapter->msix_entries) { |
2dfd1212 AD |
1283 | u32 regval = rd32(E1000_EIAM); |
1284 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
1285 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
1286 | regval = rd32(E1000_EIAC); | |
1287 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 1288 | } |
844290e5 PW |
1289 | |
1290 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
1291 | wr32(E1000_IMC, ~0); |
1292 | wrfl(); | |
1293 | synchronize_irq(adapter->pdev->irq); | |
1294 | } | |
1295 | ||
1296 | /** | |
1297 | * igb_irq_enable - Enable default interrupt generation settings | |
1298 | * @adapter: board private structure | |
1299 | **/ | |
1300 | static void igb_irq_enable(struct igb_adapter *adapter) | |
1301 | { | |
1302 | struct e1000_hw *hw = &adapter->hw; | |
1303 | ||
1304 | if (adapter->msix_entries) { | |
25568a53 | 1305 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC; |
2dfd1212 AD |
1306 | u32 regval = rd32(E1000_EIAC); |
1307 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1308 | regval = rd32(E1000_EIAM); | |
1309 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1310 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1311 | if (adapter->vfs_allocated_count) { |
4ae196df | 1312 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1313 | ims |= E1000_IMS_VMMB; |
1314 | } | |
55cac248 AD |
1315 | if (adapter->hw.mac.type == e1000_82580) |
1316 | ims |= E1000_IMS_DRSTA; | |
1317 | ||
25568a53 | 1318 | wr32(E1000_IMS, ims); |
844290e5 | 1319 | } else { |
55cac248 AD |
1320 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1321 | E1000_IMS_DRSTA); | |
1322 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1323 | E1000_IMS_DRSTA); | |
844290e5 | 1324 | } |
9d5c8243 AK |
1325 | } |
1326 | ||
1327 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1328 | { | |
51466239 | 1329 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1330 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1331 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1332 | |
1333 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1334 | /* add VID to filter table */ | |
1335 | igb_vfta_set(hw, vid, true); | |
1336 | adapter->mng_vlan_id = vid; | |
1337 | } else { | |
1338 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1339 | } | |
1340 | ||
1341 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1342 | (vid != old_vid) && | |
1343 | !vlan_group_get_device(adapter->vlgrp, old_vid)) { | |
1344 | /* remove VID from filter table */ | |
1345 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1346 | } |
1347 | } | |
1348 | ||
1349 | /** | |
1350 | * igb_release_hw_control - release control of the h/w to f/w | |
1351 | * @adapter: address of board private structure | |
1352 | * | |
1353 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
1354 | * For ASF and Pass Through versions of f/w this means that the | |
1355 | * driver is no longer loaded. | |
1356 | * | |
1357 | **/ | |
1358 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1359 | { | |
1360 | struct e1000_hw *hw = &adapter->hw; | |
1361 | u32 ctrl_ext; | |
1362 | ||
1363 | /* Let firmware take over control of h/w */ | |
1364 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1365 | wr32(E1000_CTRL_EXT, | |
1366 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1367 | } | |
1368 | ||
9d5c8243 AK |
1369 | /** |
1370 | * igb_get_hw_control - get control of the h/w from f/w | |
1371 | * @adapter: address of board private structure | |
1372 | * | |
1373 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
1374 | * For ASF and Pass Through versions of f/w this means that | |
1375 | * the driver is loaded. | |
1376 | * | |
1377 | **/ | |
1378 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1379 | { | |
1380 | struct e1000_hw *hw = &adapter->hw; | |
1381 | u32 ctrl_ext; | |
1382 | ||
1383 | /* Let firmware know the driver has taken over */ | |
1384 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1385 | wr32(E1000_CTRL_EXT, | |
1386 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1387 | } | |
1388 | ||
9d5c8243 AK |
1389 | /** |
1390 | * igb_configure - configure the hardware for RX and TX | |
1391 | * @adapter: private board structure | |
1392 | **/ | |
1393 | static void igb_configure(struct igb_adapter *adapter) | |
1394 | { | |
1395 | struct net_device *netdev = adapter->netdev; | |
1396 | int i; | |
1397 | ||
1398 | igb_get_hw_control(adapter); | |
ff41f8dc | 1399 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1400 | |
1401 | igb_restore_vlan(adapter); | |
9d5c8243 | 1402 | |
85b430b4 | 1403 | igb_setup_tctl(adapter); |
06cf2666 | 1404 | igb_setup_mrqc(adapter); |
9d5c8243 | 1405 | igb_setup_rctl(adapter); |
85b430b4 AD |
1406 | |
1407 | igb_configure_tx(adapter); | |
9d5c8243 | 1408 | igb_configure_rx(adapter); |
662d7205 AD |
1409 | |
1410 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1411 | ||
c493ea45 | 1412 | /* call igb_desc_unused which always leaves |
9d5c8243 AK |
1413 | * at least 1 descriptor unused to make sure |
1414 | * next_to_use != next_to_clean */ | |
1415 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 1416 | struct igb_ring *ring = adapter->rx_ring[i]; |
c493ea45 | 1417 | igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring)); |
9d5c8243 | 1418 | } |
9d5c8243 AK |
1419 | } |
1420 | ||
88a268c1 NN |
1421 | /** |
1422 | * igb_power_up_link - Power up the phy/serdes link | |
1423 | * @adapter: address of board private structure | |
1424 | **/ | |
1425 | void igb_power_up_link(struct igb_adapter *adapter) | |
1426 | { | |
1427 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1428 | igb_power_up_phy_copper(&adapter->hw); | |
1429 | else | |
1430 | igb_power_up_serdes_link_82575(&adapter->hw); | |
1431 | } | |
1432 | ||
1433 | /** | |
1434 | * igb_power_down_link - Power down the phy/serdes link | |
1435 | * @adapter: address of board private structure | |
1436 | */ | |
1437 | static void igb_power_down_link(struct igb_adapter *adapter) | |
1438 | { | |
1439 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1440 | igb_power_down_phy_copper_82575(&adapter->hw); | |
1441 | else | |
1442 | igb_shutdown_serdes_link_82575(&adapter->hw); | |
1443 | } | |
9d5c8243 AK |
1444 | |
1445 | /** | |
1446 | * igb_up - Open the interface and prepare it to handle traffic | |
1447 | * @adapter: board private structure | |
1448 | **/ | |
9d5c8243 AK |
1449 | int igb_up(struct igb_adapter *adapter) |
1450 | { | |
1451 | struct e1000_hw *hw = &adapter->hw; | |
1452 | int i; | |
1453 | ||
1454 | /* hardware has been reset, we need to reload some things */ | |
1455 | igb_configure(adapter); | |
1456 | ||
1457 | clear_bit(__IGB_DOWN, &adapter->state); | |
1458 | ||
047e0030 AD |
1459 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1460 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1461 | napi_enable(&q_vector->napi); | |
1462 | } | |
844290e5 | 1463 | if (adapter->msix_entries) |
9d5c8243 | 1464 | igb_configure_msix(adapter); |
feeb2721 AD |
1465 | else |
1466 | igb_assign_vector(adapter->q_vector[0], 0); | |
9d5c8243 AK |
1467 | |
1468 | /* Clear any pending interrupts. */ | |
1469 | rd32(E1000_ICR); | |
1470 | igb_irq_enable(adapter); | |
1471 | ||
d4960307 AD |
1472 | /* notify VFs that reset has been completed */ |
1473 | if (adapter->vfs_allocated_count) { | |
1474 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1475 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1476 | wr32(E1000_CTRL_EXT, reg_data); | |
1477 | } | |
1478 | ||
4cb9be7a JB |
1479 | netif_tx_start_all_queues(adapter->netdev); |
1480 | ||
25568a53 AD |
1481 | /* start the watchdog. */ |
1482 | hw->mac.get_link_status = 1; | |
1483 | schedule_work(&adapter->watchdog_task); | |
1484 | ||
9d5c8243 AK |
1485 | return 0; |
1486 | } | |
1487 | ||
1488 | void igb_down(struct igb_adapter *adapter) | |
1489 | { | |
9d5c8243 | 1490 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1491 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1492 | u32 tctl, rctl; |
1493 | int i; | |
1494 | ||
1495 | /* signal that we're down so the interrupt handler does not | |
1496 | * reschedule our watchdog timer */ | |
1497 | set_bit(__IGB_DOWN, &adapter->state); | |
1498 | ||
1499 | /* disable receives in the hardware */ | |
1500 | rctl = rd32(E1000_RCTL); | |
1501 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1502 | /* flush and sleep below */ | |
1503 | ||
fd2ea0a7 | 1504 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1505 | |
1506 | /* disable transmits in the hardware */ | |
1507 | tctl = rd32(E1000_TCTL); | |
1508 | tctl &= ~E1000_TCTL_EN; | |
1509 | wr32(E1000_TCTL, tctl); | |
1510 | /* flush both disables and wait for them to finish */ | |
1511 | wrfl(); | |
1512 | msleep(10); | |
1513 | ||
047e0030 AD |
1514 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1515 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1516 | napi_disable(&q_vector->napi); | |
1517 | } | |
9d5c8243 | 1518 | |
9d5c8243 AK |
1519 | igb_irq_disable(adapter); |
1520 | ||
1521 | del_timer_sync(&adapter->watchdog_timer); | |
1522 | del_timer_sync(&adapter->phy_info_timer); | |
1523 | ||
9d5c8243 | 1524 | netif_carrier_off(netdev); |
04fe6358 AD |
1525 | |
1526 | /* record the stats before reset*/ | |
1527 | igb_update_stats(adapter); | |
1528 | ||
9d5c8243 AK |
1529 | adapter->link_speed = 0; |
1530 | adapter->link_duplex = 0; | |
1531 | ||
3023682e JK |
1532 | if (!pci_channel_offline(adapter->pdev)) |
1533 | igb_reset(adapter); | |
9d5c8243 AK |
1534 | igb_clean_all_tx_rings(adapter); |
1535 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1536 | #ifdef CONFIG_IGB_DCA |
1537 | ||
1538 | /* since we reset the hardware DCA settings were cleared */ | |
1539 | igb_setup_dca(adapter); | |
1540 | #endif | |
9d5c8243 AK |
1541 | } |
1542 | ||
1543 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1544 | { | |
1545 | WARN_ON(in_interrupt()); | |
1546 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1547 | msleep(1); | |
1548 | igb_down(adapter); | |
1549 | igb_up(adapter); | |
1550 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1551 | } | |
1552 | ||
1553 | void igb_reset(struct igb_adapter *adapter) | |
1554 | { | |
090b1795 | 1555 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1556 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1557 | struct e1000_mac_info *mac = &hw->mac; |
1558 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
1559 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
1560 | u16 hwm; | |
1561 | ||
1562 | /* Repartition Pba for greater than 9k mtu | |
1563 | * To take effect CTRL.RST is required. | |
1564 | */ | |
fa4dfae0 | 1565 | switch (mac->type) { |
d2ba2ed8 | 1566 | case e1000_i350: |
55cac248 AD |
1567 | case e1000_82580: |
1568 | pba = rd32(E1000_RXPBS); | |
1569 | pba = igb_rxpbs_adjust_82580(pba); | |
1570 | break; | |
fa4dfae0 | 1571 | case e1000_82576: |
d249be54 AD |
1572 | pba = rd32(E1000_RXPBS); |
1573 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1574 | break; |
1575 | case e1000_82575: | |
1576 | default: | |
1577 | pba = E1000_PBA_34K; | |
1578 | break; | |
2d064c06 | 1579 | } |
9d5c8243 | 1580 | |
2d064c06 AD |
1581 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1582 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1583 | /* adjust PBA for jumbo frames */ |
1584 | wr32(E1000_PBA, pba); | |
1585 | ||
1586 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1587 | * large enough to accommodate two full transmit packets, | |
1588 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1589 | * the Rx FIFO should be large enough to accommodate at least | |
1590 | * one full receive packet and is similarly rounded up and | |
1591 | * expressed in KB. */ | |
1592 | pba = rd32(E1000_PBA); | |
1593 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1594 | tx_space = pba >> 16; | |
1595 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1596 | pba &= 0xffff; | |
1597 | /* the tx fifo also stores 16 bytes of information about the tx | |
1598 | * but don't include ethernet FCS because hardware appends it */ | |
1599 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 1600 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1601 | ETH_FCS_LEN) * 2; |
1602 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1603 | min_tx_space >>= 10; | |
1604 | /* software strips receive CRC, so leave room for it */ | |
1605 | min_rx_space = adapter->max_frame_size; | |
1606 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1607 | min_rx_space >>= 10; | |
1608 | ||
1609 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1610 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1611 | * allocation, take space away from current Rx allocation */ | |
1612 | if (tx_space < min_tx_space && | |
1613 | ((min_tx_space - tx_space) < pba)) { | |
1614 | pba = pba - (min_tx_space - tx_space); | |
1615 | ||
1616 | /* if short on rx space, rx wins and must trump tx | |
1617 | * adjustment */ | |
1618 | if (pba < min_rx_space) | |
1619 | pba = min_rx_space; | |
1620 | } | |
2d064c06 | 1621 | wr32(E1000_PBA, pba); |
9d5c8243 | 1622 | } |
9d5c8243 AK |
1623 | |
1624 | /* flow control settings */ | |
1625 | /* The high water mark must be low enough to fit one full frame | |
1626 | * (or the size used for early receive) above it in the Rx FIFO. | |
1627 | * Set it to the lower of: | |
1628 | * - 90% of the Rx FIFO size, or | |
1629 | * - the full Rx FIFO size minus one full frame */ | |
1630 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1631 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1632 | |
d405ea3e AD |
1633 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ |
1634 | fc->low_water = fc->high_water - 16; | |
9d5c8243 AK |
1635 | fc->pause_time = 0xFFFF; |
1636 | fc->send_xon = 1; | |
0cce119a | 1637 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1638 | |
4ae196df AD |
1639 | /* disable receive for all VFs and wait one second */ |
1640 | if (adapter->vfs_allocated_count) { | |
1641 | int i; | |
1642 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
f2ca0dbe | 1643 | adapter->vf_data[i].flags = 0; |
4ae196df AD |
1644 | |
1645 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1646 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1647 | |
1648 | /* disable transmits and receives */ | |
1649 | wr32(E1000_VFRE, 0); | |
1650 | wr32(E1000_VFTE, 0); | |
1651 | } | |
1652 | ||
9d5c8243 | 1653 | /* Allow time for pending master requests to run */ |
330a6d6a | 1654 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1655 | wr32(E1000_WUC, 0); |
1656 | ||
330a6d6a | 1657 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1658 | dev_err(&pdev->dev, "Hardware Error\n"); |
9d5c8243 | 1659 | |
55cac248 AD |
1660 | if (hw->mac.type == e1000_82580) { |
1661 | u32 reg = rd32(E1000_PCIEMISC); | |
1662 | wr32(E1000_PCIEMISC, | |
1663 | reg & ~E1000_PCIEMISC_LX_DECISION); | |
1664 | } | |
88a268c1 NN |
1665 | if (!netif_running(adapter->netdev)) |
1666 | igb_power_down_link(adapter); | |
1667 | ||
9d5c8243 AK |
1668 | igb_update_mng_vlan(adapter); |
1669 | ||
1670 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1671 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1672 | ||
330a6d6a | 1673 | igb_get_phy_info(hw); |
9d5c8243 AK |
1674 | } |
1675 | ||
2e5c6922 | 1676 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1677 | .ndo_open = igb_open, |
2e5c6922 | 1678 | .ndo_stop = igb_close, |
00829823 | 1679 | .ndo_start_xmit = igb_xmit_frame_adv, |
2e5c6922 | 1680 | .ndo_get_stats = igb_get_stats, |
ff41f8dc AD |
1681 | .ndo_set_rx_mode = igb_set_rx_mode, |
1682 | .ndo_set_multicast_list = igb_set_rx_mode, | |
2e5c6922 SH |
1683 | .ndo_set_mac_address = igb_set_mac, |
1684 | .ndo_change_mtu = igb_change_mtu, | |
1685 | .ndo_do_ioctl = igb_ioctl, | |
1686 | .ndo_tx_timeout = igb_tx_timeout, | |
1687 | .ndo_validate_addr = eth_validate_addr, | |
1688 | .ndo_vlan_rx_register = igb_vlan_rx_register, | |
1689 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, | |
1690 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
8151d294 WM |
1691 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
1692 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | |
1693 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | |
1694 | .ndo_get_vf_config = igb_ndo_get_vf_config, | |
2e5c6922 SH |
1695 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1696 | .ndo_poll_controller = igb_netpoll, | |
1697 | #endif | |
1698 | }; | |
1699 | ||
9d5c8243 AK |
1700 | /** |
1701 | * igb_probe - Device Initialization Routine | |
1702 | * @pdev: PCI device information struct | |
1703 | * @ent: entry in igb_pci_tbl | |
1704 | * | |
1705 | * Returns 0 on success, negative on failure | |
1706 | * | |
1707 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1708 | * The OS initialization, configuring of the adapter private structure, | |
1709 | * and a hardware reset occur. | |
1710 | **/ | |
1711 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1712 | const struct pci_device_id *ent) | |
1713 | { | |
1714 | struct net_device *netdev; | |
1715 | struct igb_adapter *adapter; | |
1716 | struct e1000_hw *hw; | |
4337e993 AD |
1717 | u16 eeprom_data = 0; |
1718 | static int global_quad_port_a; /* global quad port a indication */ | |
9d5c8243 AK |
1719 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1720 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 1721 | int err, pci_using_dac; |
9d5c8243 AK |
1722 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
1723 | u32 part_num; | |
1724 | ||
aed5dec3 | 1725 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1726 | if (err) |
1727 | return err; | |
1728 | ||
1729 | pci_using_dac = 0; | |
59d71989 | 1730 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 | 1731 | if (!err) { |
59d71989 | 1732 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
1733 | if (!err) |
1734 | pci_using_dac = 1; | |
1735 | } else { | |
59d71989 | 1736 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 | 1737 | if (err) { |
59d71989 | 1738 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 AK |
1739 | if (err) { |
1740 | dev_err(&pdev->dev, "No usable DMA " | |
1741 | "configuration, aborting\n"); | |
1742 | goto err_dma; | |
1743 | } | |
1744 | } | |
1745 | } | |
1746 | ||
aed5dec3 AD |
1747 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1748 | IORESOURCE_MEM), | |
1749 | igb_driver_name); | |
9d5c8243 AK |
1750 | if (err) |
1751 | goto err_pci_reg; | |
1752 | ||
19d5afd4 | 1753 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 1754 | |
9d5c8243 | 1755 | pci_set_master(pdev); |
c682fc23 | 1756 | pci_save_state(pdev); |
9d5c8243 AK |
1757 | |
1758 | err = -ENOMEM; | |
1bfaf07b AD |
1759 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1760 | IGB_ABS_MAX_TX_QUEUES); | |
9d5c8243 AK |
1761 | if (!netdev) |
1762 | goto err_alloc_etherdev; | |
1763 | ||
1764 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1765 | ||
1766 | pci_set_drvdata(pdev, netdev); | |
1767 | adapter = netdev_priv(netdev); | |
1768 | adapter->netdev = netdev; | |
1769 | adapter->pdev = pdev; | |
1770 | hw = &adapter->hw; | |
1771 | hw->back = adapter; | |
1772 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
1773 | ||
1774 | mmio_start = pci_resource_start(pdev, 0); | |
1775 | mmio_len = pci_resource_len(pdev, 0); | |
1776 | ||
1777 | err = -EIO; | |
28b0759c AD |
1778 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1779 | if (!hw->hw_addr) | |
9d5c8243 AK |
1780 | goto err_ioremap; |
1781 | ||
2e5c6922 | 1782 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1783 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1784 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1785 | |
1786 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1787 | ||
1788 | netdev->mem_start = mmio_start; | |
1789 | netdev->mem_end = mmio_start + mmio_len; | |
1790 | ||
9d5c8243 AK |
1791 | /* PCI config space info */ |
1792 | hw->vendor_id = pdev->vendor; | |
1793 | hw->device_id = pdev->device; | |
1794 | hw->revision_id = pdev->revision; | |
1795 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1796 | hw->subsystem_device_id = pdev->subsystem_device; | |
1797 | ||
9d5c8243 AK |
1798 | /* Copy the default MAC, PHY and NVM function pointers */ |
1799 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1800 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1801 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1802 | /* Initialize skew-specific constants */ | |
1803 | err = ei->get_invariants(hw); | |
1804 | if (err) | |
450c87c8 | 1805 | goto err_sw_init; |
9d5c8243 | 1806 | |
450c87c8 | 1807 | /* setup the private structure */ |
9d5c8243 AK |
1808 | err = igb_sw_init(adapter); |
1809 | if (err) | |
1810 | goto err_sw_init; | |
1811 | ||
1812 | igb_get_bus_info_pcie(hw); | |
1813 | ||
1814 | hw->phy.autoneg_wait_to_complete = false; | |
9d5c8243 AK |
1815 | |
1816 | /* Copper options */ | |
1817 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1818 | hw->phy.mdix = AUTO_ALL_MODES; | |
1819 | hw->phy.disable_polarity_correction = false; | |
1820 | hw->phy.ms_type = e1000_ms_hw_default; | |
1821 | } | |
1822 | ||
1823 | if (igb_check_reset_block(hw)) | |
1824 | dev_info(&pdev->dev, | |
1825 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1826 | ||
1827 | netdev->features = NETIF_F_SG | | |
7d8eb29e | 1828 | NETIF_F_IP_CSUM | |
9d5c8243 AK |
1829 | NETIF_F_HW_VLAN_TX | |
1830 | NETIF_F_HW_VLAN_RX | | |
1831 | NETIF_F_HW_VLAN_FILTER; | |
1832 | ||
7d8eb29e | 1833 | netdev->features |= NETIF_F_IPV6_CSUM; |
9d5c8243 | 1834 | netdev->features |= NETIF_F_TSO; |
9d5c8243 | 1835 | netdev->features |= NETIF_F_TSO6; |
5c0999b7 | 1836 | netdev->features |= NETIF_F_GRO; |
d3352520 | 1837 | |
48f29ffc JK |
1838 | netdev->vlan_features |= NETIF_F_TSO; |
1839 | netdev->vlan_features |= NETIF_F_TSO6; | |
7d8eb29e | 1840 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 1841 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
48f29ffc JK |
1842 | netdev->vlan_features |= NETIF_F_SG; |
1843 | ||
9d5c8243 AK |
1844 | if (pci_using_dac) |
1845 | netdev->features |= NETIF_F_HIGHDMA; | |
1846 | ||
5b043fb0 | 1847 | if (hw->mac.type >= e1000_82576) |
b9473560 JB |
1848 | netdev->features |= NETIF_F_SCTP_CSUM; |
1849 | ||
330a6d6a | 1850 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
1851 | |
1852 | /* before reading the NVM, reset the controller to put the device in a | |
1853 | * known good starting state */ | |
1854 | hw->mac.ops.reset_hw(hw); | |
1855 | ||
1856 | /* make sure the NVM is good */ | |
1857 | if (igb_validate_nvm_checksum(hw) < 0) { | |
1858 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
1859 | err = -EIO; | |
1860 | goto err_eeprom; | |
1861 | } | |
1862 | ||
1863 | /* copy the MAC address out of the NVM */ | |
1864 | if (hw->mac.ops.read_mac_addr(hw)) | |
1865 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1866 | ||
1867 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1868 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1869 | ||
1870 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1871 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1872 | err = -EIO; | |
1873 | goto err_eeprom; | |
1874 | } | |
1875 | ||
0e340485 AD |
1876 | setup_timer(&adapter->watchdog_timer, &igb_watchdog, |
1877 | (unsigned long) adapter); | |
1878 | setup_timer(&adapter->phy_info_timer, &igb_update_phy_info, | |
1879 | (unsigned long) adapter); | |
9d5c8243 AK |
1880 | |
1881 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
1882 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
1883 | ||
450c87c8 | 1884 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
1885 | adapter->fc_autoneg = true; |
1886 | hw->mac.autoneg = true; | |
1887 | hw->phy.autoneg_advertised = 0x2f; | |
1888 | ||
0cce119a AD |
1889 | hw->fc.requested_mode = e1000_fc_default; |
1890 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 1891 | |
9d5c8243 AK |
1892 | igb_validate_mdi_setting(hw); |
1893 | ||
9d5c8243 AK |
1894 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, |
1895 | * enable the ACPI Magic Packet filter | |
1896 | */ | |
1897 | ||
a2cf8b6c | 1898 | if (hw->bus.func == 0) |
312c75ae | 1899 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
55cac248 AD |
1900 | else if (hw->mac.type == e1000_82580) |
1901 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | |
1902 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
1903 | &eeprom_data); | |
a2cf8b6c AD |
1904 | else if (hw->bus.func == 1) |
1905 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 AK |
1906 | |
1907 | if (eeprom_data & eeprom_apme_mask) | |
1908 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
1909 | ||
1910 | /* now that we have the eeprom settings, apply the special cases where | |
1911 | * the eeprom may be wrong or the board simply won't support wake on | |
1912 | * lan on a particular port */ | |
1913 | switch (pdev->device) { | |
1914 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1915 | adapter->eeprom_wol = 0; | |
1916 | break; | |
1917 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1918 | case E1000_DEV_ID_82576_FIBER: |
1919 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1920 | /* Wake events only supported on port A for dual fiber |
1921 | * regardless of eeprom setting */ | |
1922 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
1923 | adapter->eeprom_wol = 0; | |
1924 | break; | |
c8ea5ea9 | 1925 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 1926 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
1927 | /* if quad port adapter, disable WoL on all but port A */ |
1928 | if (global_quad_port_a != 0) | |
1929 | adapter->eeprom_wol = 0; | |
1930 | else | |
1931 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
1932 | /* Reset for multiple quad port adapters */ | |
1933 | if (++global_quad_port_a == 4) | |
1934 | global_quad_port_a = 0; | |
1935 | break; | |
9d5c8243 AK |
1936 | } |
1937 | ||
1938 | /* initialize the wol settings based on the eeprom settings */ | |
1939 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 1940 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
1941 | |
1942 | /* reset the hardware with the new settings */ | |
1943 | igb_reset(adapter); | |
1944 | ||
1945 | /* let the f/w know that the h/w is now under the control of the | |
1946 | * driver. */ | |
1947 | igb_get_hw_control(adapter); | |
1948 | ||
9d5c8243 AK |
1949 | strcpy(netdev->name, "eth%d"); |
1950 | err = register_netdev(netdev); | |
1951 | if (err) | |
1952 | goto err_register; | |
1953 | ||
b168dfc5 JB |
1954 | /* carrier off reporting is important to ethtool even BEFORE open */ |
1955 | netif_carrier_off(netdev); | |
1956 | ||
421e02f0 | 1957 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 1958 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 1959 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 1960 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
1961 | igb_setup_dca(adapter); |
1962 | } | |
fe4506b6 | 1963 | |
38c845c7 | 1964 | #endif |
9d5c8243 AK |
1965 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1966 | /* print bus type/speed/width info */ | |
7c510e4b | 1967 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 | 1968 | netdev->name, |
559e9c49 | 1969 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
ff846f52 | 1970 | (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : |
559e9c49 | 1971 | "unknown"), |
59c3de89 AD |
1972 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
1973 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : | |
1974 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : | |
1975 | "unknown"), | |
7c510e4b | 1976 | netdev->dev_addr); |
9d5c8243 AK |
1977 | |
1978 | igb_read_part_num(hw, &part_num); | |
1979 | dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, | |
1980 | (part_num >> 8), (part_num & 0xff)); | |
1981 | ||
1982 | dev_info(&pdev->dev, | |
1983 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
1984 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 1985 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 AK |
1986 | adapter->num_rx_queues, adapter->num_tx_queues); |
1987 | ||
9d5c8243 AK |
1988 | return 0; |
1989 | ||
1990 | err_register: | |
1991 | igb_release_hw_control(adapter); | |
1992 | err_eeprom: | |
1993 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 1994 | igb_reset_phy(hw); |
9d5c8243 AK |
1995 | |
1996 | if (hw->flash_address) | |
1997 | iounmap(hw->flash_address); | |
9d5c8243 | 1998 | err_sw_init: |
047e0030 | 1999 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
2000 | iounmap(hw->hw_addr); |
2001 | err_ioremap: | |
2002 | free_netdev(netdev); | |
2003 | err_alloc_etherdev: | |
559e9c49 AD |
2004 | pci_release_selected_regions(pdev, |
2005 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
2006 | err_pci_reg: |
2007 | err_dma: | |
2008 | pci_disable_device(pdev); | |
2009 | return err; | |
2010 | } | |
2011 | ||
2012 | /** | |
2013 | * igb_remove - Device Removal Routine | |
2014 | * @pdev: PCI device information struct | |
2015 | * | |
2016 | * igb_remove is called by the PCI subsystem to alert the driver | |
2017 | * that it should release a PCI device. The could be caused by a | |
2018 | * Hot-Plug event, or because the driver is going to be removed from | |
2019 | * memory. | |
2020 | **/ | |
2021 | static void __devexit igb_remove(struct pci_dev *pdev) | |
2022 | { | |
2023 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2024 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 2025 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
2026 | |
2027 | /* flush_scheduled work may reschedule our watchdog task, so | |
2028 | * explicitly disable watchdog tasks from being rescheduled */ | |
2029 | set_bit(__IGB_DOWN, &adapter->state); | |
2030 | del_timer_sync(&adapter->watchdog_timer); | |
2031 | del_timer_sync(&adapter->phy_info_timer); | |
2032 | ||
2033 | flush_scheduled_work(); | |
2034 | ||
421e02f0 | 2035 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 2036 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
2037 | dev_info(&pdev->dev, "DCA disabled\n"); |
2038 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 2039 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 2040 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
2041 | } |
2042 | #endif | |
2043 | ||
9d5c8243 AK |
2044 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
2045 | * would have already happened in close and is redundant. */ | |
2046 | igb_release_hw_control(adapter); | |
2047 | ||
2048 | unregister_netdev(netdev); | |
2049 | ||
047e0030 | 2050 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 2051 | |
37680117 AD |
2052 | #ifdef CONFIG_PCI_IOV |
2053 | /* reclaim resources allocated to VFs */ | |
2054 | if (adapter->vf_data) { | |
2055 | /* disable iov and allow time for transactions to clear */ | |
2056 | pci_disable_sriov(pdev); | |
2057 | msleep(500); | |
2058 | ||
2059 | kfree(adapter->vf_data); | |
2060 | adapter->vf_data = NULL; | |
2061 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
2062 | msleep(100); | |
2063 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
2064 | } | |
2065 | #endif | |
559e9c49 | 2066 | |
28b0759c AD |
2067 | iounmap(hw->hw_addr); |
2068 | if (hw->flash_address) | |
2069 | iounmap(hw->flash_address); | |
559e9c49 AD |
2070 | pci_release_selected_regions(pdev, |
2071 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
2072 | |
2073 | free_netdev(netdev); | |
2074 | ||
19d5afd4 | 2075 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 2076 | |
9d5c8243 AK |
2077 | pci_disable_device(pdev); |
2078 | } | |
2079 | ||
a6b623e0 AD |
2080 | /** |
2081 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space | |
2082 | * @adapter: board private structure to initialize | |
2083 | * | |
2084 | * This function initializes the vf specific data storage and then attempts to | |
2085 | * allocate the VFs. The reason for ordering it this way is because it is much | |
2086 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
2087 | * the memory for the VFs. | |
2088 | **/ | |
2089 | static void __devinit igb_probe_vfs(struct igb_adapter * adapter) | |
2090 | { | |
2091 | #ifdef CONFIG_PCI_IOV | |
2092 | struct pci_dev *pdev = adapter->pdev; | |
2093 | ||
a6b623e0 AD |
2094 | if (adapter->vfs_allocated_count) { |
2095 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
2096 | sizeof(struct vf_data_storage), | |
2097 | GFP_KERNEL); | |
2098 | /* if allocation failed then we do not support SR-IOV */ | |
2099 | if (!adapter->vf_data) { | |
2100 | adapter->vfs_allocated_count = 0; | |
2101 | dev_err(&pdev->dev, "Unable to allocate memory for VF " | |
2102 | "Data Storage\n"); | |
2103 | } | |
2104 | } | |
2105 | ||
2106 | if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) { | |
2107 | kfree(adapter->vf_data); | |
2108 | adapter->vf_data = NULL; | |
2109 | #endif /* CONFIG_PCI_IOV */ | |
2110 | adapter->vfs_allocated_count = 0; | |
2111 | #ifdef CONFIG_PCI_IOV | |
2112 | } else { | |
2113 | unsigned char mac_addr[ETH_ALEN]; | |
2114 | int i; | |
2115 | dev_info(&pdev->dev, "%d vfs allocated\n", | |
2116 | adapter->vfs_allocated_count); | |
2117 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
2118 | random_ether_addr(mac_addr); | |
2119 | igb_set_vf_mac(adapter, i, mac_addr); | |
2120 | } | |
2121 | } | |
2122 | #endif /* CONFIG_PCI_IOV */ | |
2123 | } | |
2124 | ||
115f459a AD |
2125 | |
2126 | /** | |
2127 | * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp | |
2128 | * @adapter: board private structure to initialize | |
2129 | * | |
2130 | * igb_init_hw_timer initializes the function pointer and values for the hw | |
2131 | * timer found in hardware. | |
2132 | **/ | |
2133 | static void igb_init_hw_timer(struct igb_adapter *adapter) | |
2134 | { | |
2135 | struct e1000_hw *hw = &adapter->hw; | |
2136 | ||
2137 | switch (hw->mac.type) { | |
d2ba2ed8 | 2138 | case e1000_i350: |
55cac248 AD |
2139 | case e1000_82580: |
2140 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
2141 | adapter->cycles.read = igb_read_clock; | |
2142 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
2143 | adapter->cycles.mult = 1; | |
2144 | /* | |
2145 | * The 82580 timesync updates the system timer every 8ns by 8ns | |
2146 | * and the value cannot be shifted. Instead we need to shift | |
2147 | * the registers to generate a 64bit timer value. As a result | |
2148 | * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by | |
2149 | * 24 in order to generate a larger value for synchronization. | |
2150 | */ | |
2151 | adapter->cycles.shift = IGB_82580_TSYNC_SHIFT; | |
2152 | /* disable system timer temporarily by setting bit 31 */ | |
2153 | wr32(E1000_TSAUXC, 0x80000000); | |
2154 | wrfl(); | |
2155 | ||
2156 | /* Set registers so that rollover occurs soon to test this. */ | |
2157 | wr32(E1000_SYSTIMR, 0x00000000); | |
2158 | wr32(E1000_SYSTIML, 0x80000000); | |
2159 | wr32(E1000_SYSTIMH, 0x000000FF); | |
2160 | wrfl(); | |
2161 | ||
2162 | /* enable system timer by clearing bit 31 */ | |
2163 | wr32(E1000_TSAUXC, 0x0); | |
2164 | wrfl(); | |
2165 | ||
2166 | timecounter_init(&adapter->clock, | |
2167 | &adapter->cycles, | |
2168 | ktime_to_ns(ktime_get_real())); | |
2169 | /* | |
2170 | * Synchronize our NIC clock against system wall clock. NIC | |
2171 | * time stamp reading requires ~3us per sample, each sample | |
2172 | * was pretty stable even under load => only require 10 | |
2173 | * samples for each offset comparison. | |
2174 | */ | |
2175 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
2176 | adapter->compare.source = &adapter->clock; | |
2177 | adapter->compare.target = ktime_get_real; | |
2178 | adapter->compare.num_samples = 10; | |
2179 | timecompare_update(&adapter->compare, 0); | |
2180 | break; | |
115f459a AD |
2181 | case e1000_82576: |
2182 | /* | |
2183 | * Initialize hardware timer: we keep it running just in case | |
2184 | * that some program needs it later on. | |
2185 | */ | |
2186 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
2187 | adapter->cycles.read = igb_read_clock; | |
2188 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
2189 | adapter->cycles.mult = 1; | |
2190 | /** | |
2191 | * Scale the NIC clock cycle by a large factor so that | |
2192 | * relatively small clock corrections can be added or | |
2193 | * substracted at each clock tick. The drawbacks of a large | |
2194 | * factor are a) that the clock register overflows more quickly | |
2195 | * (not such a big deal) and b) that the increment per tick has | |
2196 | * to fit into 24 bits. As a result we need to use a shift of | |
2197 | * 19 so we can fit a value of 16 into the TIMINCA register. | |
2198 | */ | |
2199 | adapter->cycles.shift = IGB_82576_TSYNC_SHIFT; | |
2200 | wr32(E1000_TIMINCA, | |
2201 | (1 << E1000_TIMINCA_16NS_SHIFT) | | |
2202 | (16 << IGB_82576_TSYNC_SHIFT)); | |
2203 | ||
2204 | /* Set registers so that rollover occurs soon to test this. */ | |
2205 | wr32(E1000_SYSTIML, 0x00000000); | |
2206 | wr32(E1000_SYSTIMH, 0xFF800000); | |
2207 | wrfl(); | |
2208 | ||
2209 | timecounter_init(&adapter->clock, | |
2210 | &adapter->cycles, | |
2211 | ktime_to_ns(ktime_get_real())); | |
2212 | /* | |
2213 | * Synchronize our NIC clock against system wall clock. NIC | |
2214 | * time stamp reading requires ~3us per sample, each sample | |
2215 | * was pretty stable even under load => only require 10 | |
2216 | * samples for each offset comparison. | |
2217 | */ | |
2218 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
2219 | adapter->compare.source = &adapter->clock; | |
2220 | adapter->compare.target = ktime_get_real; | |
2221 | adapter->compare.num_samples = 10; | |
2222 | timecompare_update(&adapter->compare, 0); | |
2223 | break; | |
2224 | case e1000_82575: | |
2225 | /* 82575 does not support timesync */ | |
2226 | default: | |
2227 | break; | |
2228 | } | |
2229 | ||
2230 | } | |
2231 | ||
9d5c8243 AK |
2232 | /** |
2233 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
2234 | * @adapter: board private structure to initialize | |
2235 | * | |
2236 | * igb_sw_init initializes the Adapter private data structure. | |
2237 | * Fields are initialized based on PCI device information and | |
2238 | * OS network device settings (MTU size). | |
2239 | **/ | |
2240 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
2241 | { | |
2242 | struct e1000_hw *hw = &adapter->hw; | |
2243 | struct net_device *netdev = adapter->netdev; | |
2244 | struct pci_dev *pdev = adapter->pdev; | |
2245 | ||
2246 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
2247 | ||
68fd9910 AD |
2248 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
2249 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
4fc82adf AD |
2250 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; |
2251 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
2252 | ||
9d5c8243 AK |
2253 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2254 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
2255 | ||
a6b623e0 AD |
2256 | #ifdef CONFIG_PCI_IOV |
2257 | if (hw->mac.type == e1000_82576) | |
c0f2276f | 2258 | adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs; |
a6b623e0 AD |
2259 | |
2260 | #endif /* CONFIG_PCI_IOV */ | |
a99955fc AD |
2261 | adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); |
2262 | ||
2263 | /* | |
2264 | * if rss_queues > 4 or vfs are going to be allocated with rss_queues | |
2265 | * then we should combine the queues into a queue pair in order to | |
2266 | * conserve interrupts due to limited supply | |
2267 | */ | |
2268 | if ((adapter->rss_queues > 4) || | |
2269 | ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6))) | |
2270 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
2271 | ||
a6b623e0 | 2272 | /* This call may decrease the number of queues */ |
047e0030 | 2273 | if (igb_init_interrupt_scheme(adapter)) { |
9d5c8243 AK |
2274 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
2275 | return -ENOMEM; | |
2276 | } | |
2277 | ||
115f459a | 2278 | igb_init_hw_timer(adapter); |
a6b623e0 AD |
2279 | igb_probe_vfs(adapter); |
2280 | ||
9d5c8243 AK |
2281 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
2282 | igb_irq_disable(adapter); | |
2283 | ||
2284 | set_bit(__IGB_DOWN, &adapter->state); | |
2285 | return 0; | |
2286 | } | |
2287 | ||
2288 | /** | |
2289 | * igb_open - Called when a network interface is made active | |
2290 | * @netdev: network interface device structure | |
2291 | * | |
2292 | * Returns 0 on success, negative value on failure | |
2293 | * | |
2294 | * The open entry point is called when a network interface is made | |
2295 | * active by the system (IFF_UP). At this point all resources needed | |
2296 | * for transmit and receive operations are allocated, the interrupt | |
2297 | * handler is registered with the OS, the watchdog timer is started, | |
2298 | * and the stack is notified that the interface is ready. | |
2299 | **/ | |
2300 | static int igb_open(struct net_device *netdev) | |
2301 | { | |
2302 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2303 | struct e1000_hw *hw = &adapter->hw; | |
2304 | int err; | |
2305 | int i; | |
2306 | ||
2307 | /* disallow open during test */ | |
2308 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
2309 | return -EBUSY; | |
2310 | ||
b168dfc5 JB |
2311 | netif_carrier_off(netdev); |
2312 | ||
9d5c8243 AK |
2313 | /* allocate transmit descriptors */ |
2314 | err = igb_setup_all_tx_resources(adapter); | |
2315 | if (err) | |
2316 | goto err_setup_tx; | |
2317 | ||
2318 | /* allocate receive descriptors */ | |
2319 | err = igb_setup_all_rx_resources(adapter); | |
2320 | if (err) | |
2321 | goto err_setup_rx; | |
2322 | ||
88a268c1 | 2323 | igb_power_up_link(adapter); |
9d5c8243 | 2324 | |
9d5c8243 AK |
2325 | /* before we allocate an interrupt, we must be ready to handle it. |
2326 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2327 | * as soon as we call pci_request_irq, so we have to setup our | |
2328 | * clean_rx handler before we do so. */ | |
2329 | igb_configure(adapter); | |
2330 | ||
2331 | err = igb_request_irq(adapter); | |
2332 | if (err) | |
2333 | goto err_req_irq; | |
2334 | ||
2335 | /* From here on the code is the same as igb_up() */ | |
2336 | clear_bit(__IGB_DOWN, &adapter->state); | |
2337 | ||
047e0030 AD |
2338 | for (i = 0; i < adapter->num_q_vectors; i++) { |
2339 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
2340 | napi_enable(&q_vector->napi); | |
2341 | } | |
9d5c8243 AK |
2342 | |
2343 | /* Clear any pending interrupts. */ | |
2344 | rd32(E1000_ICR); | |
844290e5 PW |
2345 | |
2346 | igb_irq_enable(adapter); | |
2347 | ||
d4960307 AD |
2348 | /* notify VFs that reset has been completed */ |
2349 | if (adapter->vfs_allocated_count) { | |
2350 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2351 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2352 | wr32(E1000_CTRL_EXT, reg_data); | |
2353 | } | |
2354 | ||
d55b53ff JK |
2355 | netif_tx_start_all_queues(netdev); |
2356 | ||
25568a53 AD |
2357 | /* start the watchdog. */ |
2358 | hw->mac.get_link_status = 1; | |
2359 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2360 | |
2361 | return 0; | |
2362 | ||
2363 | err_req_irq: | |
2364 | igb_release_hw_control(adapter); | |
88a268c1 | 2365 | igb_power_down_link(adapter); |
9d5c8243 AK |
2366 | igb_free_all_rx_resources(adapter); |
2367 | err_setup_rx: | |
2368 | igb_free_all_tx_resources(adapter); | |
2369 | err_setup_tx: | |
2370 | igb_reset(adapter); | |
2371 | ||
2372 | return err; | |
2373 | } | |
2374 | ||
2375 | /** | |
2376 | * igb_close - Disables a network interface | |
2377 | * @netdev: network interface device structure | |
2378 | * | |
2379 | * Returns 0, this is not allowed to fail | |
2380 | * | |
2381 | * The close entry point is called when an interface is de-activated | |
2382 | * by the OS. The hardware is still under the driver's control, but | |
2383 | * needs to be disabled. A global MAC reset is issued to stop the | |
2384 | * hardware, and all transmit and receive resources are freed. | |
2385 | **/ | |
2386 | static int igb_close(struct net_device *netdev) | |
2387 | { | |
2388 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2389 | ||
2390 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
2391 | igb_down(adapter); | |
2392 | ||
2393 | igb_free_irq(adapter); | |
2394 | ||
2395 | igb_free_all_tx_resources(adapter); | |
2396 | igb_free_all_rx_resources(adapter); | |
2397 | ||
9d5c8243 AK |
2398 | return 0; |
2399 | } | |
2400 | ||
2401 | /** | |
2402 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
9d5c8243 AK |
2403 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
2404 | * | |
2405 | * Return 0 on success, negative on failure | |
2406 | **/ | |
80785298 | 2407 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2408 | { |
59d71989 | 2409 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
2410 | int size; |
2411 | ||
2412 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2413 | tx_ring->buffer_info = vmalloc(size); | |
2414 | if (!tx_ring->buffer_info) | |
2415 | goto err; | |
2416 | memset(tx_ring->buffer_info, 0, size); | |
2417 | ||
2418 | /* round up to nearest 4K */ | |
85e8d004 | 2419 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2420 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2421 | ||
59d71989 AD |
2422 | tx_ring->desc = dma_alloc_coherent(dev, |
2423 | tx_ring->size, | |
2424 | &tx_ring->dma, | |
2425 | GFP_KERNEL); | |
9d5c8243 AK |
2426 | |
2427 | if (!tx_ring->desc) | |
2428 | goto err; | |
2429 | ||
9d5c8243 AK |
2430 | tx_ring->next_to_use = 0; |
2431 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
2432 | return 0; |
2433 | ||
2434 | err: | |
2435 | vfree(tx_ring->buffer_info); | |
59d71989 | 2436 | dev_err(dev, |
9d5c8243 AK |
2437 | "Unable to allocate memory for the transmit descriptor ring\n"); |
2438 | return -ENOMEM; | |
2439 | } | |
2440 | ||
2441 | /** | |
2442 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
2443 | * (Descriptors) for all queues | |
2444 | * @adapter: board private structure | |
2445 | * | |
2446 | * Return 0 on success, negative on failure | |
2447 | **/ | |
2448 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2449 | { | |
439705e1 | 2450 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2451 | int i, err = 0; |
2452 | ||
2453 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 2454 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
9d5c8243 | 2455 | if (err) { |
439705e1 | 2456 | dev_err(&pdev->dev, |
9d5c8243 AK |
2457 | "Allocation for Tx Queue %u failed\n", i); |
2458 | for (i--; i >= 0; i--) | |
3025a446 | 2459 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2460 | break; |
2461 | } | |
2462 | } | |
2463 | ||
a99955fc | 2464 | for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) { |
439705e1 | 2465 | int r_idx = i % adapter->num_tx_queues; |
3025a446 | 2466 | adapter->multi_tx_table[i] = adapter->tx_ring[r_idx]; |
eebbbdba | 2467 | } |
9d5c8243 AK |
2468 | return err; |
2469 | } | |
2470 | ||
2471 | /** | |
85b430b4 AD |
2472 | * igb_setup_tctl - configure the transmit control registers |
2473 | * @adapter: Board private structure | |
9d5c8243 | 2474 | **/ |
d7ee5b3a | 2475 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2476 | { |
9d5c8243 AK |
2477 | struct e1000_hw *hw = &adapter->hw; |
2478 | u32 tctl; | |
9d5c8243 | 2479 | |
85b430b4 AD |
2480 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2481 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2482 | |
2483 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2484 | tctl = rd32(E1000_TCTL); |
2485 | tctl &= ~E1000_TCTL_CT; | |
2486 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2487 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2488 | ||
2489 | igb_config_collision_dist(hw); | |
2490 | ||
9d5c8243 AK |
2491 | /* Enable transmits */ |
2492 | tctl |= E1000_TCTL_EN; | |
2493 | ||
2494 | wr32(E1000_TCTL, tctl); | |
2495 | } | |
2496 | ||
85b430b4 AD |
2497 | /** |
2498 | * igb_configure_tx_ring - Configure transmit ring after Reset | |
2499 | * @adapter: board private structure | |
2500 | * @ring: tx ring to configure | |
2501 | * | |
2502 | * Configure a transmit ring after a reset. | |
2503 | **/ | |
d7ee5b3a AD |
2504 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
2505 | struct igb_ring *ring) | |
85b430b4 AD |
2506 | { |
2507 | struct e1000_hw *hw = &adapter->hw; | |
2508 | u32 txdctl; | |
2509 | u64 tdba = ring->dma; | |
2510 | int reg_idx = ring->reg_idx; | |
2511 | ||
2512 | /* disable the queue */ | |
2513 | txdctl = rd32(E1000_TXDCTL(reg_idx)); | |
2514 | wr32(E1000_TXDCTL(reg_idx), | |
2515 | txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); | |
2516 | wrfl(); | |
2517 | mdelay(10); | |
2518 | ||
2519 | wr32(E1000_TDLEN(reg_idx), | |
2520 | ring->count * sizeof(union e1000_adv_tx_desc)); | |
2521 | wr32(E1000_TDBAL(reg_idx), | |
2522 | tdba & 0x00000000ffffffffULL); | |
2523 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); | |
2524 | ||
fce99e34 AD |
2525 | ring->head = hw->hw_addr + E1000_TDH(reg_idx); |
2526 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); | |
2527 | writel(0, ring->head); | |
2528 | writel(0, ring->tail); | |
85b430b4 AD |
2529 | |
2530 | txdctl |= IGB_TX_PTHRESH; | |
2531 | txdctl |= IGB_TX_HTHRESH << 8; | |
2532 | txdctl |= IGB_TX_WTHRESH << 16; | |
2533 | ||
2534 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
2535 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
2536 | } | |
2537 | ||
2538 | /** | |
2539 | * igb_configure_tx - Configure transmit Unit after Reset | |
2540 | * @adapter: board private structure | |
2541 | * | |
2542 | * Configure the Tx unit of the MAC after a reset. | |
2543 | **/ | |
2544 | static void igb_configure_tx(struct igb_adapter *adapter) | |
2545 | { | |
2546 | int i; | |
2547 | ||
2548 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 2549 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
85b430b4 AD |
2550 | } |
2551 | ||
9d5c8243 AK |
2552 | /** |
2553 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
9d5c8243 AK |
2554 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
2555 | * | |
2556 | * Returns 0 on success, negative on failure | |
2557 | **/ | |
80785298 | 2558 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2559 | { |
59d71989 | 2560 | struct device *dev = rx_ring->dev; |
9d5c8243 AK |
2561 | int size, desc_len; |
2562 | ||
2563 | size = sizeof(struct igb_buffer) * rx_ring->count; | |
2564 | rx_ring->buffer_info = vmalloc(size); | |
2565 | if (!rx_ring->buffer_info) | |
2566 | goto err; | |
2567 | memset(rx_ring->buffer_info, 0, size); | |
2568 | ||
2569 | desc_len = sizeof(union e1000_adv_rx_desc); | |
2570 | ||
2571 | /* Round up to nearest 4K */ | |
2572 | rx_ring->size = rx_ring->count * desc_len; | |
2573 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
2574 | ||
59d71989 AD |
2575 | rx_ring->desc = dma_alloc_coherent(dev, |
2576 | rx_ring->size, | |
2577 | &rx_ring->dma, | |
2578 | GFP_KERNEL); | |
9d5c8243 AK |
2579 | |
2580 | if (!rx_ring->desc) | |
2581 | goto err; | |
2582 | ||
2583 | rx_ring->next_to_clean = 0; | |
2584 | rx_ring->next_to_use = 0; | |
9d5c8243 | 2585 | |
9d5c8243 AK |
2586 | return 0; |
2587 | ||
2588 | err: | |
2589 | vfree(rx_ring->buffer_info); | |
439705e1 | 2590 | rx_ring->buffer_info = NULL; |
59d71989 AD |
2591 | dev_err(dev, "Unable to allocate memory for the receive descriptor" |
2592 | " ring\n"); | |
9d5c8243 AK |
2593 | return -ENOMEM; |
2594 | } | |
2595 | ||
2596 | /** | |
2597 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
2598 | * (Descriptors) for all queues | |
2599 | * @adapter: board private structure | |
2600 | * | |
2601 | * Return 0 on success, negative on failure | |
2602 | **/ | |
2603 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
2604 | { | |
439705e1 | 2605 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2606 | int i, err = 0; |
2607 | ||
2608 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 2609 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
9d5c8243 | 2610 | if (err) { |
439705e1 | 2611 | dev_err(&pdev->dev, |
9d5c8243 AK |
2612 | "Allocation for Rx Queue %u failed\n", i); |
2613 | for (i--; i >= 0; i--) | |
3025a446 | 2614 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
2615 | break; |
2616 | } | |
2617 | } | |
2618 | ||
2619 | return err; | |
2620 | } | |
2621 | ||
06cf2666 AD |
2622 | /** |
2623 | * igb_setup_mrqc - configure the multiple receive queue control registers | |
2624 | * @adapter: Board private structure | |
2625 | **/ | |
2626 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
2627 | { | |
2628 | struct e1000_hw *hw = &adapter->hw; | |
2629 | u32 mrqc, rxcsum; | |
2630 | u32 j, num_rx_queues, shift = 0, shift2 = 0; | |
2631 | union e1000_reta { | |
2632 | u32 dword; | |
2633 | u8 bytes[4]; | |
2634 | } reta; | |
2635 | static const u8 rsshash[40] = { | |
2636 | 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, | |
2637 | 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, | |
2638 | 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, | |
2639 | 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa }; | |
2640 | ||
2641 | /* Fill out hash function seeds */ | |
2642 | for (j = 0; j < 10; j++) { | |
2643 | u32 rsskey = rsshash[(j * 4)]; | |
2644 | rsskey |= rsshash[(j * 4) + 1] << 8; | |
2645 | rsskey |= rsshash[(j * 4) + 2] << 16; | |
2646 | rsskey |= rsshash[(j * 4) + 3] << 24; | |
2647 | array_wr32(E1000_RSSRK(0), j, rsskey); | |
2648 | } | |
2649 | ||
a99955fc | 2650 | num_rx_queues = adapter->rss_queues; |
06cf2666 AD |
2651 | |
2652 | if (adapter->vfs_allocated_count) { | |
2653 | /* 82575 and 82576 supports 2 RSS queues for VMDq */ | |
2654 | switch (hw->mac.type) { | |
d2ba2ed8 | 2655 | case e1000_i350: |
55cac248 AD |
2656 | case e1000_82580: |
2657 | num_rx_queues = 1; | |
2658 | shift = 0; | |
2659 | break; | |
06cf2666 AD |
2660 | case e1000_82576: |
2661 | shift = 3; | |
2662 | num_rx_queues = 2; | |
2663 | break; | |
2664 | case e1000_82575: | |
2665 | shift = 2; | |
2666 | shift2 = 6; | |
2667 | default: | |
2668 | break; | |
2669 | } | |
2670 | } else { | |
2671 | if (hw->mac.type == e1000_82575) | |
2672 | shift = 6; | |
2673 | } | |
2674 | ||
2675 | for (j = 0; j < (32 * 4); j++) { | |
2676 | reta.bytes[j & 3] = (j % num_rx_queues) << shift; | |
2677 | if (shift2) | |
2678 | reta.bytes[j & 3] |= num_rx_queues << shift2; | |
2679 | if ((j & 3) == 3) | |
2680 | wr32(E1000_RETA(j >> 2), reta.dword); | |
2681 | } | |
2682 | ||
2683 | /* | |
2684 | * Disable raw packet checksumming so that RSS hash is placed in | |
2685 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum | |
2686 | * offloads as they are enabled by default | |
2687 | */ | |
2688 | rxcsum = rd32(E1000_RXCSUM); | |
2689 | rxcsum |= E1000_RXCSUM_PCSD; | |
2690 | ||
2691 | if (adapter->hw.mac.type >= e1000_82576) | |
2692 | /* Enable Receive Checksum Offload for SCTP */ | |
2693 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
2694 | ||
2695 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
2696 | wr32(E1000_RXCSUM, rxcsum); | |
2697 | ||
2698 | /* If VMDq is enabled then we set the appropriate mode for that, else | |
2699 | * we default to RSS so that an RSS hash is calculated per packet even | |
2700 | * if we are only using one queue */ | |
2701 | if (adapter->vfs_allocated_count) { | |
2702 | if (hw->mac.type > e1000_82575) { | |
2703 | /* Set the default pool for the PF's first queue */ | |
2704 | u32 vtctl = rd32(E1000_VT_CTL); | |
2705 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
2706 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
2707 | vtctl |= adapter->vfs_allocated_count << | |
2708 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
2709 | wr32(E1000_VT_CTL, vtctl); | |
2710 | } | |
a99955fc | 2711 | if (adapter->rss_queues > 1) |
06cf2666 AD |
2712 | mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
2713 | else | |
2714 | mrqc = E1000_MRQC_ENABLE_VMDQ; | |
2715 | } else { | |
2716 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | |
2717 | } | |
2718 | igb_vmm_control(adapter); | |
2719 | ||
2720 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | |
2721 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | |
2722 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | |
2723 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | |
2724 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | |
2725 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | |
2726 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | |
2727 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
2728 | ||
2729 | wr32(E1000_MRQC, mrqc); | |
2730 | } | |
2731 | ||
9d5c8243 AK |
2732 | /** |
2733 | * igb_setup_rctl - configure the receive control registers | |
2734 | * @adapter: Board private structure | |
2735 | **/ | |
d7ee5b3a | 2736 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
2737 | { |
2738 | struct e1000_hw *hw = &adapter->hw; | |
2739 | u32 rctl; | |
9d5c8243 AK |
2740 | |
2741 | rctl = rd32(E1000_RCTL); | |
2742 | ||
2743 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 2744 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 2745 | |
69d728ba | 2746 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 2747 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 2748 | |
87cb7e8c AK |
2749 | /* |
2750 | * enable stripping of CRC. It's unlikely this will break BMC | |
2751 | * redirection as it did with e1000. Newer features require | |
2752 | * that the HW strips the CRC. | |
73cd78f1 | 2753 | */ |
87cb7e8c | 2754 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 2755 | |
559e9c49 | 2756 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 2757 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 2758 | |
6ec43fe6 AD |
2759 | /* enable LPE to prevent packets larger than max_frame_size */ |
2760 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 2761 | |
952f72a8 AD |
2762 | /* disable queue 0 to prevent tail write w/o re-config */ |
2763 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 2764 | |
e1739522 AD |
2765 | /* Attention!!! For SR-IOV PF driver operations you must enable |
2766 | * queue drop for all VF and PF queues to prevent head of line blocking | |
2767 | * if an un-trusted VF does not provide descriptors to hardware. | |
2768 | */ | |
2769 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
2770 | /* set all queue drop enable bits */ |
2771 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
2772 | } |
2773 | ||
9d5c8243 AK |
2774 | wr32(E1000_RCTL, rctl); |
2775 | } | |
2776 | ||
7d5753f0 AD |
2777 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
2778 | int vfn) | |
2779 | { | |
2780 | struct e1000_hw *hw = &adapter->hw; | |
2781 | u32 vmolr; | |
2782 | ||
2783 | /* if it isn't the PF check to see if VFs are enabled and | |
2784 | * increase the size to support vlan tags */ | |
2785 | if (vfn < adapter->vfs_allocated_count && | |
2786 | adapter->vf_data[vfn].vlans_enabled) | |
2787 | size += VLAN_TAG_SIZE; | |
2788 | ||
2789 | vmolr = rd32(E1000_VMOLR(vfn)); | |
2790 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
2791 | vmolr |= size | E1000_VMOLR_LPE; | |
2792 | wr32(E1000_VMOLR(vfn), vmolr); | |
2793 | ||
2794 | return 0; | |
2795 | } | |
2796 | ||
e1739522 AD |
2797 | /** |
2798 | * igb_rlpml_set - set maximum receive packet size | |
2799 | * @adapter: board private structure | |
2800 | * | |
2801 | * Configure maximum receivable packet size. | |
2802 | **/ | |
2803 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
2804 | { | |
2805 | u32 max_frame_size = adapter->max_frame_size; | |
2806 | struct e1000_hw *hw = &adapter->hw; | |
2807 | u16 pf_id = adapter->vfs_allocated_count; | |
2808 | ||
2809 | if (adapter->vlgrp) | |
2810 | max_frame_size += VLAN_TAG_SIZE; | |
2811 | ||
2812 | /* if vfs are enabled we set RLPML to the largest possible request | |
2813 | * size and set the VMOLR RLPML to the size we need */ | |
2814 | if (pf_id) { | |
2815 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
7d5753f0 | 2816 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
2817 | } |
2818 | ||
2819 | wr32(E1000_RLPML, max_frame_size); | |
2820 | } | |
2821 | ||
8151d294 WM |
2822 | static inline void igb_set_vmolr(struct igb_adapter *adapter, |
2823 | int vfn, bool aupe) | |
7d5753f0 AD |
2824 | { |
2825 | struct e1000_hw *hw = &adapter->hw; | |
2826 | u32 vmolr; | |
2827 | ||
2828 | /* | |
2829 | * This register exists only on 82576 and newer so if we are older then | |
2830 | * we should exit and do nothing | |
2831 | */ | |
2832 | if (hw->mac.type < e1000_82576) | |
2833 | return; | |
2834 | ||
2835 | vmolr = rd32(E1000_VMOLR(vfn)); | |
8151d294 WM |
2836 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
2837 | if (aupe) | |
2838 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ | |
2839 | else | |
2840 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | |
7d5753f0 AD |
2841 | |
2842 | /* clear all bits that might not be set */ | |
2843 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
2844 | ||
a99955fc | 2845 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 AD |
2846 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
2847 | /* | |
2848 | * for VMDq only allow the VFs and pool 0 to accept broadcast and | |
2849 | * multicast packets | |
2850 | */ | |
2851 | if (vfn <= adapter->vfs_allocated_count) | |
2852 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ | |
2853 | ||
2854 | wr32(E1000_VMOLR(vfn), vmolr); | |
2855 | } | |
2856 | ||
85b430b4 AD |
2857 | /** |
2858 | * igb_configure_rx_ring - Configure a receive ring after Reset | |
2859 | * @adapter: board private structure | |
2860 | * @ring: receive ring to be configured | |
2861 | * | |
2862 | * Configure the Rx unit of the MAC after a reset. | |
2863 | **/ | |
d7ee5b3a AD |
2864 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
2865 | struct igb_ring *ring) | |
85b430b4 AD |
2866 | { |
2867 | struct e1000_hw *hw = &adapter->hw; | |
2868 | u64 rdba = ring->dma; | |
2869 | int reg_idx = ring->reg_idx; | |
952f72a8 | 2870 | u32 srrctl, rxdctl; |
85b430b4 AD |
2871 | |
2872 | /* disable the queue */ | |
2873 | rxdctl = rd32(E1000_RXDCTL(reg_idx)); | |
2874 | wr32(E1000_RXDCTL(reg_idx), | |
2875 | rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE); | |
2876 | ||
2877 | /* Set DMA base address registers */ | |
2878 | wr32(E1000_RDBAL(reg_idx), | |
2879 | rdba & 0x00000000ffffffffULL); | |
2880 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
2881 | wr32(E1000_RDLEN(reg_idx), | |
2882 | ring->count * sizeof(union e1000_adv_rx_desc)); | |
2883 | ||
2884 | /* initialize head and tail */ | |
fce99e34 AD |
2885 | ring->head = hw->hw_addr + E1000_RDH(reg_idx); |
2886 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); | |
2887 | writel(0, ring->head); | |
2888 | writel(0, ring->tail); | |
85b430b4 | 2889 | |
952f72a8 | 2890 | /* set descriptor configuration */ |
4c844851 AD |
2891 | if (ring->rx_buffer_len < IGB_RXBUFFER_1024) { |
2892 | srrctl = ALIGN(ring->rx_buffer_len, 64) << | |
952f72a8 AD |
2893 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
2894 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 | |
2895 | srrctl |= IGB_RXBUFFER_16384 >> | |
2896 | E1000_SRRCTL_BSIZEPKT_SHIFT; | |
2897 | #else | |
2898 | srrctl |= (PAGE_SIZE / 2) >> | |
2899 | E1000_SRRCTL_BSIZEPKT_SHIFT; | |
2900 | #endif | |
2901 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | |
2902 | } else { | |
4c844851 | 2903 | srrctl = ALIGN(ring->rx_buffer_len, 1024) >> |
952f72a8 AD |
2904 | E1000_SRRCTL_BSIZEPKT_SHIFT; |
2905 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
2906 | } | |
757b77e2 NN |
2907 | if (hw->mac.type == e1000_82580) |
2908 | srrctl |= E1000_SRRCTL_TIMESTAMP; | |
e6bdb6fe NN |
2909 | /* Only set Drop Enable if we are supporting multiple queues */ |
2910 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | |
2911 | srrctl |= E1000_SRRCTL_DROP_EN; | |
952f72a8 AD |
2912 | |
2913 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
2914 | ||
7d5753f0 | 2915 | /* set filtering for VMDQ pools */ |
8151d294 | 2916 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
7d5753f0 | 2917 | |
85b430b4 AD |
2918 | /* enable receive descriptor fetching */ |
2919 | rxdctl = rd32(E1000_RXDCTL(reg_idx)); | |
2920 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
2921 | rxdctl &= 0xFFF00000; | |
2922 | rxdctl |= IGB_RX_PTHRESH; | |
2923 | rxdctl |= IGB_RX_HTHRESH << 8; | |
2924 | rxdctl |= IGB_RX_WTHRESH << 16; | |
2925 | wr32(E1000_RXDCTL(reg_idx), rxdctl); | |
2926 | } | |
2927 | ||
9d5c8243 AK |
2928 | /** |
2929 | * igb_configure_rx - Configure receive Unit after Reset | |
2930 | * @adapter: board private structure | |
2931 | * | |
2932 | * Configure the Rx unit of the MAC after a reset. | |
2933 | **/ | |
2934 | static void igb_configure_rx(struct igb_adapter *adapter) | |
2935 | { | |
9107584e | 2936 | int i; |
9d5c8243 | 2937 | |
68d480c4 AD |
2938 | /* set UTA to appropriate mode */ |
2939 | igb_set_uta(adapter); | |
2940 | ||
26ad9178 AD |
2941 | /* set the correct pool for the PF default MAC address in entry 0 */ |
2942 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
2943 | adapter->vfs_allocated_count); | |
2944 | ||
06cf2666 AD |
2945 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
2946 | * the Base and Length of the Rx Descriptor Ring */ | |
2947 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 2948 | igb_configure_rx_ring(adapter, adapter->rx_ring[i]); |
9d5c8243 AK |
2949 | } |
2950 | ||
2951 | /** | |
2952 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
2953 | * @tx_ring: Tx descriptor ring for a specific queue |
2954 | * | |
2955 | * Free all transmit software resources | |
2956 | **/ | |
68fd9910 | 2957 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2958 | { |
3b644cf6 | 2959 | igb_clean_tx_ring(tx_ring); |
9d5c8243 AK |
2960 | |
2961 | vfree(tx_ring->buffer_info); | |
2962 | tx_ring->buffer_info = NULL; | |
2963 | ||
439705e1 AD |
2964 | /* if not set, then don't free */ |
2965 | if (!tx_ring->desc) | |
2966 | return; | |
2967 | ||
59d71989 AD |
2968 | dma_free_coherent(tx_ring->dev, tx_ring->size, |
2969 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
2970 | |
2971 | tx_ring->desc = NULL; | |
2972 | } | |
2973 | ||
2974 | /** | |
2975 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
2976 | * @adapter: board private structure | |
2977 | * | |
2978 | * Free all transmit software resources | |
2979 | **/ | |
2980 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
2981 | { | |
2982 | int i; | |
2983 | ||
2984 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 2985 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2986 | } |
2987 | ||
b1a436c3 AD |
2988 | void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring, |
2989 | struct igb_buffer *buffer_info) | |
9d5c8243 | 2990 | { |
6366ad33 AD |
2991 | if (buffer_info->dma) { |
2992 | if (buffer_info->mapped_as_page) | |
59d71989 | 2993 | dma_unmap_page(tx_ring->dev, |
6366ad33 AD |
2994 | buffer_info->dma, |
2995 | buffer_info->length, | |
59d71989 | 2996 | DMA_TO_DEVICE); |
6366ad33 | 2997 | else |
59d71989 | 2998 | dma_unmap_single(tx_ring->dev, |
6366ad33 AD |
2999 | buffer_info->dma, |
3000 | buffer_info->length, | |
59d71989 | 3001 | DMA_TO_DEVICE); |
6366ad33 AD |
3002 | buffer_info->dma = 0; |
3003 | } | |
9d5c8243 AK |
3004 | if (buffer_info->skb) { |
3005 | dev_kfree_skb_any(buffer_info->skb); | |
3006 | buffer_info->skb = NULL; | |
3007 | } | |
3008 | buffer_info->time_stamp = 0; | |
6366ad33 AD |
3009 | buffer_info->length = 0; |
3010 | buffer_info->next_to_watch = 0; | |
3011 | buffer_info->mapped_as_page = false; | |
9d5c8243 AK |
3012 | } |
3013 | ||
3014 | /** | |
3015 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
3016 | * @tx_ring: ring to be cleaned |
3017 | **/ | |
3b644cf6 | 3018 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 AK |
3019 | { |
3020 | struct igb_buffer *buffer_info; | |
3021 | unsigned long size; | |
3022 | unsigned int i; | |
3023 | ||
3024 | if (!tx_ring->buffer_info) | |
3025 | return; | |
3026 | /* Free all the Tx ring sk_buffs */ | |
3027 | ||
3028 | for (i = 0; i < tx_ring->count; i++) { | |
3029 | buffer_info = &tx_ring->buffer_info[i]; | |
80785298 | 3030 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
3031 | } |
3032 | ||
3033 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
3034 | memset(tx_ring->buffer_info, 0, size); | |
3035 | ||
3036 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
3037 | memset(tx_ring->desc, 0, tx_ring->size); |
3038 | ||
3039 | tx_ring->next_to_use = 0; | |
3040 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
3041 | } |
3042 | ||
3043 | /** | |
3044 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
3045 | * @adapter: board private structure | |
3046 | **/ | |
3047 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
3048 | { | |
3049 | int i; | |
3050 | ||
3051 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3052 | igb_clean_tx_ring(adapter->tx_ring[i]); |
9d5c8243 AK |
3053 | } |
3054 | ||
3055 | /** | |
3056 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
3057 | * @rx_ring: ring to clean the resources from |
3058 | * | |
3059 | * Free all receive software resources | |
3060 | **/ | |
68fd9910 | 3061 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3062 | { |
3b644cf6 | 3063 | igb_clean_rx_ring(rx_ring); |
9d5c8243 AK |
3064 | |
3065 | vfree(rx_ring->buffer_info); | |
3066 | rx_ring->buffer_info = NULL; | |
3067 | ||
439705e1 AD |
3068 | /* if not set, then don't free */ |
3069 | if (!rx_ring->desc) | |
3070 | return; | |
3071 | ||
59d71989 AD |
3072 | dma_free_coherent(rx_ring->dev, rx_ring->size, |
3073 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
3074 | |
3075 | rx_ring->desc = NULL; | |
3076 | } | |
3077 | ||
3078 | /** | |
3079 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
3080 | * @adapter: board private structure | |
3081 | * | |
3082 | * Free all receive software resources | |
3083 | **/ | |
3084 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
3085 | { | |
3086 | int i; | |
3087 | ||
3088 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3089 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3090 | } |
3091 | ||
3092 | /** | |
3093 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
3094 | * @rx_ring: ring to free buffers from |
3095 | **/ | |
3b644cf6 | 3096 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 AK |
3097 | { |
3098 | struct igb_buffer *buffer_info; | |
9d5c8243 AK |
3099 | unsigned long size; |
3100 | unsigned int i; | |
3101 | ||
3102 | if (!rx_ring->buffer_info) | |
3103 | return; | |
439705e1 | 3104 | |
9d5c8243 AK |
3105 | /* Free all the Rx ring sk_buffs */ |
3106 | for (i = 0; i < rx_ring->count; i++) { | |
3107 | buffer_info = &rx_ring->buffer_info[i]; | |
3108 | if (buffer_info->dma) { | |
59d71989 | 3109 | dma_unmap_single(rx_ring->dev, |
80785298 | 3110 | buffer_info->dma, |
4c844851 | 3111 | rx_ring->rx_buffer_len, |
59d71989 | 3112 | DMA_FROM_DEVICE); |
9d5c8243 AK |
3113 | buffer_info->dma = 0; |
3114 | } | |
3115 | ||
3116 | if (buffer_info->skb) { | |
3117 | dev_kfree_skb(buffer_info->skb); | |
3118 | buffer_info->skb = NULL; | |
3119 | } | |
6ec43fe6 | 3120 | if (buffer_info->page_dma) { |
59d71989 | 3121 | dma_unmap_page(rx_ring->dev, |
80785298 | 3122 | buffer_info->page_dma, |
6ec43fe6 | 3123 | PAGE_SIZE / 2, |
59d71989 | 3124 | DMA_FROM_DEVICE); |
6ec43fe6 AD |
3125 | buffer_info->page_dma = 0; |
3126 | } | |
9d5c8243 | 3127 | if (buffer_info->page) { |
9d5c8243 AK |
3128 | put_page(buffer_info->page); |
3129 | buffer_info->page = NULL; | |
bf36c1a0 | 3130 | buffer_info->page_offset = 0; |
9d5c8243 AK |
3131 | } |
3132 | } | |
3133 | ||
9d5c8243 AK |
3134 | size = sizeof(struct igb_buffer) * rx_ring->count; |
3135 | memset(rx_ring->buffer_info, 0, size); | |
3136 | ||
3137 | /* Zero out the descriptor ring */ | |
3138 | memset(rx_ring->desc, 0, rx_ring->size); | |
3139 | ||
3140 | rx_ring->next_to_clean = 0; | |
3141 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
3142 | } |
3143 | ||
3144 | /** | |
3145 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
3146 | * @adapter: board private structure | |
3147 | **/ | |
3148 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
3149 | { | |
3150 | int i; | |
3151 | ||
3152 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3153 | igb_clean_rx_ring(adapter->rx_ring[i]); |
9d5c8243 AK |
3154 | } |
3155 | ||
3156 | /** | |
3157 | * igb_set_mac - Change the Ethernet Address of the NIC | |
3158 | * @netdev: network interface device structure | |
3159 | * @p: pointer to an address structure | |
3160 | * | |
3161 | * Returns 0 on success, negative on failure | |
3162 | **/ | |
3163 | static int igb_set_mac(struct net_device *netdev, void *p) | |
3164 | { | |
3165 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 3166 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3167 | struct sockaddr *addr = p; |
3168 | ||
3169 | if (!is_valid_ether_addr(addr->sa_data)) | |
3170 | return -EADDRNOTAVAIL; | |
3171 | ||
3172 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 3173 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 3174 | |
26ad9178 AD |
3175 | /* set the correct pool for the new PF MAC address in entry 0 */ |
3176 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
3177 | adapter->vfs_allocated_count); | |
e1739522 | 3178 | |
9d5c8243 AK |
3179 | return 0; |
3180 | } | |
3181 | ||
3182 | /** | |
68d480c4 | 3183 | * igb_write_mc_addr_list - write multicast addresses to MTA |
9d5c8243 AK |
3184 | * @netdev: network interface device structure |
3185 | * | |
68d480c4 AD |
3186 | * Writes multicast address list to the MTA hash table. |
3187 | * Returns: -ENOMEM on failure | |
3188 | * 0 on no addresses written | |
3189 | * X on writing X addresses to MTA | |
9d5c8243 | 3190 | **/ |
68d480c4 | 3191 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
3192 | { |
3193 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3194 | struct e1000_hw *hw = &adapter->hw; | |
22bedad3 | 3195 | struct netdev_hw_addr *ha; |
68d480c4 | 3196 | u8 *mta_list; |
9d5c8243 AK |
3197 | int i; |
3198 | ||
4cd24eaf | 3199 | if (netdev_mc_empty(netdev)) { |
68d480c4 AD |
3200 | /* nothing to program, so clear mc list */ |
3201 | igb_update_mc_addr_list(hw, NULL, 0); | |
3202 | igb_restore_vf_multicasts(adapter); | |
3203 | return 0; | |
3204 | } | |
9d5c8243 | 3205 | |
4cd24eaf | 3206 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
68d480c4 AD |
3207 | if (!mta_list) |
3208 | return -ENOMEM; | |
ff41f8dc | 3209 | |
68d480c4 | 3210 | /* The shared function expects a packed array of only addresses. */ |
48e2f183 | 3211 | i = 0; |
22bedad3 JP |
3212 | netdev_for_each_mc_addr(ha, netdev) |
3213 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); | |
68d480c4 | 3214 | |
68d480c4 AD |
3215 | igb_update_mc_addr_list(hw, mta_list, i); |
3216 | kfree(mta_list); | |
3217 | ||
4cd24eaf | 3218 | return netdev_mc_count(netdev); |
68d480c4 AD |
3219 | } |
3220 | ||
3221 | /** | |
3222 | * igb_write_uc_addr_list - write unicast addresses to RAR table | |
3223 | * @netdev: network interface device structure | |
3224 | * | |
3225 | * Writes unicast address list to the RAR table. | |
3226 | * Returns: -ENOMEM on failure/insufficient address space | |
3227 | * 0 on no addresses written | |
3228 | * X on writing X addresses to the RAR table | |
3229 | **/ | |
3230 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
3231 | { | |
3232 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3233 | struct e1000_hw *hw = &adapter->hw; | |
3234 | unsigned int vfn = adapter->vfs_allocated_count; | |
3235 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
3236 | int count = 0; | |
3237 | ||
3238 | /* return ENOMEM indicating insufficient memory for addresses */ | |
32e7bfc4 | 3239 | if (netdev_uc_count(netdev) > rar_entries) |
68d480c4 | 3240 | return -ENOMEM; |
9d5c8243 | 3241 | |
32e7bfc4 | 3242 | if (!netdev_uc_empty(netdev) && rar_entries) { |
ff41f8dc | 3243 | struct netdev_hw_addr *ha; |
32e7bfc4 JP |
3244 | |
3245 | netdev_for_each_uc_addr(ha, netdev) { | |
ff41f8dc AD |
3246 | if (!rar_entries) |
3247 | break; | |
26ad9178 AD |
3248 | igb_rar_set_qsel(adapter, ha->addr, |
3249 | rar_entries--, | |
68d480c4 AD |
3250 | vfn); |
3251 | count++; | |
ff41f8dc AD |
3252 | } |
3253 | } | |
3254 | /* write the addresses in reverse order to avoid write combining */ | |
3255 | for (; rar_entries > 0 ; rar_entries--) { | |
3256 | wr32(E1000_RAH(rar_entries), 0); | |
3257 | wr32(E1000_RAL(rar_entries), 0); | |
3258 | } | |
3259 | wrfl(); | |
3260 | ||
68d480c4 AD |
3261 | return count; |
3262 | } | |
3263 | ||
3264 | /** | |
3265 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set | |
3266 | * @netdev: network interface device structure | |
3267 | * | |
3268 | * The set_rx_mode entry point is called whenever the unicast or multicast | |
3269 | * address lists or the network interface flags are updated. This routine is | |
3270 | * responsible for configuring the hardware for proper unicast, multicast, | |
3271 | * promiscuous mode, and all-multi behavior. | |
3272 | **/ | |
3273 | static void igb_set_rx_mode(struct net_device *netdev) | |
3274 | { | |
3275 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3276 | struct e1000_hw *hw = &adapter->hw; | |
3277 | unsigned int vfn = adapter->vfs_allocated_count; | |
3278 | u32 rctl, vmolr = 0; | |
3279 | int count; | |
3280 | ||
3281 | /* Check for Promiscuous and All Multicast modes */ | |
3282 | rctl = rd32(E1000_RCTL); | |
3283 | ||
3284 | /* clear the effected bits */ | |
3285 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
3286 | ||
3287 | if (netdev->flags & IFF_PROMISC) { | |
3288 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3289 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
3290 | } else { | |
3291 | if (netdev->flags & IFF_ALLMULTI) { | |
3292 | rctl |= E1000_RCTL_MPE; | |
3293 | vmolr |= E1000_VMOLR_MPME; | |
3294 | } else { | |
3295 | /* | |
3296 | * Write addresses to the MTA, if the attempt fails | |
3297 | * then we should just turn on promiscous mode so | |
3298 | * that we can at least receive multicast traffic | |
3299 | */ | |
3300 | count = igb_write_mc_addr_list(netdev); | |
3301 | if (count < 0) { | |
3302 | rctl |= E1000_RCTL_MPE; | |
3303 | vmolr |= E1000_VMOLR_MPME; | |
3304 | } else if (count) { | |
3305 | vmolr |= E1000_VMOLR_ROMPE; | |
3306 | } | |
3307 | } | |
3308 | /* | |
3309 | * Write addresses to available RAR registers, if there is not | |
3310 | * sufficient space to store all the addresses then enable | |
3311 | * unicast promiscous mode | |
3312 | */ | |
3313 | count = igb_write_uc_addr_list(netdev); | |
3314 | if (count < 0) { | |
3315 | rctl |= E1000_RCTL_UPE; | |
3316 | vmolr |= E1000_VMOLR_ROPE; | |
3317 | } | |
3318 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 3319 | } |
68d480c4 | 3320 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 3321 | |
68d480c4 AD |
3322 | /* |
3323 | * In order to support SR-IOV and eventually VMDq it is necessary to set | |
3324 | * the VMOLR to enable the appropriate modes. Without this workaround | |
3325 | * we will have issues with VLAN tag stripping not being done for frames | |
3326 | * that are only arriving because we are the default pool | |
3327 | */ | |
3328 | if (hw->mac.type < e1000_82576) | |
28fc06f5 | 3329 | return; |
9d5c8243 | 3330 | |
68d480c4 AD |
3331 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
3332 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); | |
3333 | wr32(E1000_VMOLR(vfn), vmolr); | |
28fc06f5 | 3334 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
3335 | } |
3336 | ||
3337 | /* Need to wait a few seconds after link up to get diagnostic information from | |
3338 | * the phy */ | |
3339 | static void igb_update_phy_info(unsigned long data) | |
3340 | { | |
3341 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3342 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3343 | } |
3344 | ||
4d6b725e AD |
3345 | /** |
3346 | * igb_has_link - check shared code for link and determine up/down | |
3347 | * @adapter: pointer to driver private info | |
3348 | **/ | |
3145535a | 3349 | bool igb_has_link(struct igb_adapter *adapter) |
4d6b725e AD |
3350 | { |
3351 | struct e1000_hw *hw = &adapter->hw; | |
3352 | bool link_active = false; | |
3353 | s32 ret_val = 0; | |
3354 | ||
3355 | /* get_link_status is set on LSC (link status) interrupt or | |
3356 | * rx sequence error interrupt. get_link_status will stay | |
3357 | * false until the e1000_check_for_link establishes link | |
3358 | * for copper adapters ONLY | |
3359 | */ | |
3360 | switch (hw->phy.media_type) { | |
3361 | case e1000_media_type_copper: | |
3362 | if (hw->mac.get_link_status) { | |
3363 | ret_val = hw->mac.ops.check_for_link(hw); | |
3364 | link_active = !hw->mac.get_link_status; | |
3365 | } else { | |
3366 | link_active = true; | |
3367 | } | |
3368 | break; | |
4d6b725e AD |
3369 | case e1000_media_type_internal_serdes: |
3370 | ret_val = hw->mac.ops.check_for_link(hw); | |
3371 | link_active = hw->mac.serdes_has_link; | |
3372 | break; | |
3373 | default: | |
3374 | case e1000_media_type_unknown: | |
3375 | break; | |
3376 | } | |
3377 | ||
3378 | return link_active; | |
3379 | } | |
3380 | ||
9d5c8243 AK |
3381 | /** |
3382 | * igb_watchdog - Timer Call-back | |
3383 | * @data: pointer to adapter cast into an unsigned long | |
3384 | **/ | |
3385 | static void igb_watchdog(unsigned long data) | |
3386 | { | |
3387 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3388 | /* Do the rest outside of interrupt context */ | |
3389 | schedule_work(&adapter->watchdog_task); | |
3390 | } | |
3391 | ||
3392 | static void igb_watchdog_task(struct work_struct *work) | |
3393 | { | |
3394 | struct igb_adapter *adapter = container_of(work, | |
559e9c49 AD |
3395 | struct igb_adapter, |
3396 | watchdog_task); | |
9d5c8243 | 3397 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3398 | struct net_device *netdev = adapter->netdev; |
9d5c8243 | 3399 | u32 link; |
7a6ea550 | 3400 | int i; |
9d5c8243 | 3401 | |
4d6b725e | 3402 | link = igb_has_link(adapter); |
9d5c8243 AK |
3403 | if (link) { |
3404 | if (!netif_carrier_ok(netdev)) { | |
3405 | u32 ctrl; | |
330a6d6a AD |
3406 | hw->mac.ops.get_speed_and_duplex(hw, |
3407 | &adapter->link_speed, | |
3408 | &adapter->link_duplex); | |
9d5c8243 AK |
3409 | |
3410 | ctrl = rd32(E1000_CTRL); | |
527d47c1 AD |
3411 | /* Links status message must follow this format */ |
3412 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | |
9d5c8243 | 3413 | "Flow Control: %s\n", |
559e9c49 AD |
3414 | netdev->name, |
3415 | adapter->link_speed, | |
3416 | adapter->link_duplex == FULL_DUPLEX ? | |
9d5c8243 | 3417 | "Full Duplex" : "Half Duplex", |
559e9c49 AD |
3418 | ((ctrl & E1000_CTRL_TFCE) && |
3419 | (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" : | |
3420 | ((ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3421 | ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None"))); | |
9d5c8243 | 3422 | |
d07f3e37 | 3423 | /* adjust timeout factor according to speed/duplex */ |
9d5c8243 AK |
3424 | adapter->tx_timeout_factor = 1; |
3425 | switch (adapter->link_speed) { | |
3426 | case SPEED_10: | |
9d5c8243 AK |
3427 | adapter->tx_timeout_factor = 14; |
3428 | break; | |
3429 | case SPEED_100: | |
9d5c8243 AK |
3430 | /* maybe add some timeout factor ? */ |
3431 | break; | |
3432 | } | |
3433 | ||
3434 | netif_carrier_on(netdev); | |
9d5c8243 | 3435 | |
4ae196df AD |
3436 | igb_ping_all_vfs(adapter); |
3437 | ||
4b1a9877 | 3438 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3439 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3440 | mod_timer(&adapter->phy_info_timer, | |
3441 | round_jiffies(jiffies + 2 * HZ)); | |
3442 | } | |
3443 | } else { | |
3444 | if (netif_carrier_ok(netdev)) { | |
3445 | adapter->link_speed = 0; | |
3446 | adapter->link_duplex = 0; | |
527d47c1 AD |
3447 | /* Links status message must follow this format */ |
3448 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
3449 | netdev->name); | |
9d5c8243 | 3450 | netif_carrier_off(netdev); |
4b1a9877 | 3451 | |
4ae196df AD |
3452 | igb_ping_all_vfs(adapter); |
3453 | ||
4b1a9877 | 3454 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3455 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3456 | mod_timer(&adapter->phy_info_timer, | |
3457 | round_jiffies(jiffies + 2 * HZ)); | |
3458 | } | |
3459 | } | |
3460 | ||
9d5c8243 | 3461 | igb_update_stats(adapter); |
9d5c8243 | 3462 | |
dbabb065 | 3463 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 | 3464 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
dbabb065 | 3465 | if (!netif_carrier_ok(netdev)) { |
9d5c8243 AK |
3466 | /* We've lost link, so the controller stops DMA, |
3467 | * but we've got queued Tx work that's never going | |
3468 | * to get done, so reset controller to flush Tx. | |
3469 | * (Do the reset outside of interrupt context). */ | |
dbabb065 AD |
3470 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
3471 | adapter->tx_timeout_count++; | |
3472 | schedule_work(&adapter->reset_task); | |
3473 | /* return immediately since reset is imminent */ | |
3474 | return; | |
3475 | } | |
9d5c8243 | 3476 | } |
9d5c8243 | 3477 | |
dbabb065 AD |
3478 | /* Force detection of hung controller every watchdog period */ |
3479 | tx_ring->detect_tx_hung = true; | |
3480 | } | |
f7ba205e | 3481 | |
9d5c8243 | 3482 | /* Cause software interrupt to ensure rx ring is cleaned */ |
7a6ea550 | 3483 | if (adapter->msix_entries) { |
047e0030 AD |
3484 | u32 eics = 0; |
3485 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
3486 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
3487 | eics |= q_vector->eims_value; | |
3488 | } | |
7a6ea550 AD |
3489 | wr32(E1000_EICS, eics); |
3490 | } else { | |
3491 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
3492 | } | |
9d5c8243 | 3493 | |
9d5c8243 AK |
3494 | /* Reset the timer */ |
3495 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3496 | mod_timer(&adapter->watchdog_timer, | |
3497 | round_jiffies(jiffies + 2 * HZ)); | |
3498 | } | |
3499 | ||
3500 | enum latency_range { | |
3501 | lowest_latency = 0, | |
3502 | low_latency = 1, | |
3503 | bulk_latency = 2, | |
3504 | latency_invalid = 255 | |
3505 | }; | |
3506 | ||
6eb5a7f1 AD |
3507 | /** |
3508 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
3509 | * | |
3510 | * Stores a new ITR value based on strictly on packet size. This | |
3511 | * algorithm is less sophisticated than that used in igb_update_itr, | |
3512 | * due to the difficulty of synchronizing statistics across multiple | |
3513 | * receive rings. The divisors and thresholds used by this fuction | |
3514 | * were determined based on theoretical maximum wire speed and testing | |
3515 | * data, in order to minimize response time while increasing bulk | |
3516 | * throughput. | |
3517 | * This functionality is controlled by the InterruptThrottleRate module | |
3518 | * parameter (see igb_param.c) | |
3519 | * NOTE: This function is called only when operating in a multiqueue | |
3520 | * receive environment. | |
047e0030 | 3521 | * @q_vector: pointer to q_vector |
6eb5a7f1 | 3522 | **/ |
047e0030 | 3523 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 3524 | { |
047e0030 | 3525 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 3526 | int avg_wire_size = 0; |
047e0030 | 3527 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 3528 | |
6eb5a7f1 AD |
3529 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
3530 | * ints/sec - ITR timer value of 120 ticks. | |
3531 | */ | |
3532 | if (adapter->link_speed != SPEED_1000) { | |
047e0030 | 3533 | new_val = 976; |
6eb5a7f1 | 3534 | goto set_itr_val; |
9d5c8243 | 3535 | } |
047e0030 AD |
3536 | |
3537 | if (q_vector->rx_ring && q_vector->rx_ring->total_packets) { | |
3538 | struct igb_ring *ring = q_vector->rx_ring; | |
3539 | avg_wire_size = ring->total_bytes / ring->total_packets; | |
3540 | } | |
3541 | ||
3542 | if (q_vector->tx_ring && q_vector->tx_ring->total_packets) { | |
3543 | struct igb_ring *ring = q_vector->tx_ring; | |
3544 | avg_wire_size = max_t(u32, avg_wire_size, | |
3545 | (ring->total_bytes / | |
3546 | ring->total_packets)); | |
3547 | } | |
3548 | ||
3549 | /* if avg_wire_size isn't set no work was done */ | |
3550 | if (!avg_wire_size) | |
3551 | goto clear_counts; | |
9d5c8243 | 3552 | |
6eb5a7f1 AD |
3553 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
3554 | avg_wire_size += 24; | |
3555 | ||
3556 | /* Don't starve jumbo frames */ | |
3557 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 3558 | |
6eb5a7f1 AD |
3559 | /* Give a little boost to mid-size frames */ |
3560 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
3561 | new_val = avg_wire_size / 3; | |
3562 | else | |
3563 | new_val = avg_wire_size / 2; | |
9d5c8243 | 3564 | |
abe1c363 NN |
3565 | /* when in itr mode 3 do not exceed 20K ints/sec */ |
3566 | if (adapter->rx_itr_setting == 3 && new_val < 196) | |
3567 | new_val = 196; | |
3568 | ||
6eb5a7f1 | 3569 | set_itr_val: |
047e0030 AD |
3570 | if (new_val != q_vector->itr_val) { |
3571 | q_vector->itr_val = new_val; | |
3572 | q_vector->set_itr = 1; | |
9d5c8243 | 3573 | } |
6eb5a7f1 | 3574 | clear_counts: |
047e0030 AD |
3575 | if (q_vector->rx_ring) { |
3576 | q_vector->rx_ring->total_bytes = 0; | |
3577 | q_vector->rx_ring->total_packets = 0; | |
3578 | } | |
3579 | if (q_vector->tx_ring) { | |
3580 | q_vector->tx_ring->total_bytes = 0; | |
3581 | q_vector->tx_ring->total_packets = 0; | |
3582 | } | |
9d5c8243 AK |
3583 | } |
3584 | ||
3585 | /** | |
3586 | * igb_update_itr - update the dynamic ITR value based on statistics | |
3587 | * Stores a new ITR value based on packets and byte | |
3588 | * counts during the last interrupt. The advantage of per interrupt | |
3589 | * computation is faster updates and more accurate ITR for the current | |
3590 | * traffic pattern. Constants in this function were computed | |
3591 | * based on theoretical maximum wire speed and thresholds were set based | |
3592 | * on testing data as well as attempting to minimize response time | |
3593 | * while increasing bulk throughput. | |
3594 | * this functionality is controlled by the InterruptThrottleRate module | |
3595 | * parameter (see igb_param.c) | |
3596 | * NOTE: These calculations are only valid when operating in a single- | |
3597 | * queue environment. | |
3598 | * @adapter: pointer to adapter | |
047e0030 | 3599 | * @itr_setting: current q_vector->itr_val |
9d5c8243 AK |
3600 | * @packets: the number of packets during this measurement interval |
3601 | * @bytes: the number of bytes during this measurement interval | |
3602 | **/ | |
3603 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
3604 | int packets, int bytes) | |
3605 | { | |
3606 | unsigned int retval = itr_setting; | |
3607 | ||
3608 | if (packets == 0) | |
3609 | goto update_itr_done; | |
3610 | ||
3611 | switch (itr_setting) { | |
3612 | case lowest_latency: | |
3613 | /* handle TSO and jumbo frames */ | |
3614 | if (bytes/packets > 8000) | |
3615 | retval = bulk_latency; | |
3616 | else if ((packets < 5) && (bytes > 512)) | |
3617 | retval = low_latency; | |
3618 | break; | |
3619 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
3620 | if (bytes > 10000) { | |
3621 | /* this if handles the TSO accounting */ | |
3622 | if (bytes/packets > 8000) { | |
3623 | retval = bulk_latency; | |
3624 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
3625 | retval = bulk_latency; | |
3626 | } else if ((packets > 35)) { | |
3627 | retval = lowest_latency; | |
3628 | } | |
3629 | } else if (bytes/packets > 2000) { | |
3630 | retval = bulk_latency; | |
3631 | } else if (packets <= 2 && bytes < 512) { | |
3632 | retval = lowest_latency; | |
3633 | } | |
3634 | break; | |
3635 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
3636 | if (bytes > 25000) { | |
3637 | if (packets > 35) | |
3638 | retval = low_latency; | |
1e5c3d21 | 3639 | } else if (bytes < 1500) { |
9d5c8243 AK |
3640 | retval = low_latency; |
3641 | } | |
3642 | break; | |
3643 | } | |
3644 | ||
3645 | update_itr_done: | |
3646 | return retval; | |
3647 | } | |
3648 | ||
6eb5a7f1 | 3649 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 | 3650 | { |
047e0030 | 3651 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
9d5c8243 | 3652 | u16 current_itr; |
047e0030 | 3653 | u32 new_itr = q_vector->itr_val; |
9d5c8243 AK |
3654 | |
3655 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
3656 | if (adapter->link_speed != SPEED_1000) { | |
3657 | current_itr = 0; | |
3658 | new_itr = 4000; | |
3659 | goto set_itr_now; | |
3660 | } | |
3661 | ||
3662 | adapter->rx_itr = igb_update_itr(adapter, | |
3663 | adapter->rx_itr, | |
3025a446 AD |
3664 | q_vector->rx_ring->total_packets, |
3665 | q_vector->rx_ring->total_bytes); | |
9d5c8243 | 3666 | |
047e0030 AD |
3667 | adapter->tx_itr = igb_update_itr(adapter, |
3668 | adapter->tx_itr, | |
3025a446 AD |
3669 | q_vector->tx_ring->total_packets, |
3670 | q_vector->tx_ring->total_bytes); | |
047e0030 | 3671 | current_itr = max(adapter->rx_itr, adapter->tx_itr); |
9d5c8243 | 3672 | |
6eb5a7f1 | 3673 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
4fc82adf | 3674 | if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency) |
6eb5a7f1 AD |
3675 | current_itr = low_latency; |
3676 | ||
9d5c8243 AK |
3677 | switch (current_itr) { |
3678 | /* counts and packets in update_itr are dependent on these numbers */ | |
3679 | case lowest_latency: | |
78b1f607 | 3680 | new_itr = 56; /* aka 70,000 ints/sec */ |
9d5c8243 AK |
3681 | break; |
3682 | case low_latency: | |
78b1f607 | 3683 | new_itr = 196; /* aka 20,000 ints/sec */ |
9d5c8243 AK |
3684 | break; |
3685 | case bulk_latency: | |
78b1f607 | 3686 | new_itr = 980; /* aka 4,000 ints/sec */ |
9d5c8243 AK |
3687 | break; |
3688 | default: | |
3689 | break; | |
3690 | } | |
3691 | ||
3692 | set_itr_now: | |
3025a446 AD |
3693 | q_vector->rx_ring->total_bytes = 0; |
3694 | q_vector->rx_ring->total_packets = 0; | |
3695 | q_vector->tx_ring->total_bytes = 0; | |
3696 | q_vector->tx_ring->total_packets = 0; | |
6eb5a7f1 | 3697 | |
047e0030 | 3698 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
3699 | /* this attempts to bias the interrupt rate towards Bulk |
3700 | * by adding intermediate steps when interrupt rate is | |
3701 | * increasing */ | |
047e0030 AD |
3702 | new_itr = new_itr > q_vector->itr_val ? |
3703 | max((new_itr * q_vector->itr_val) / | |
3704 | (new_itr + (q_vector->itr_val >> 2)), | |
3705 | new_itr) : | |
9d5c8243 AK |
3706 | new_itr; |
3707 | /* Don't write the value here; it resets the adapter's | |
3708 | * internal timer, and causes us to delay far longer than | |
3709 | * we should between interrupts. Instead, we write the ITR | |
3710 | * value at the beginning of the next interrupt so the timing | |
3711 | * ends up being correct. | |
3712 | */ | |
047e0030 AD |
3713 | q_vector->itr_val = new_itr; |
3714 | q_vector->set_itr = 1; | |
9d5c8243 | 3715 | } |
9d5c8243 AK |
3716 | } |
3717 | ||
9d5c8243 AK |
3718 | #define IGB_TX_FLAGS_CSUM 0x00000001 |
3719 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
3720 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
3721 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
cdfd01fc AD |
3722 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 |
3723 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 | |
3724 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
9d5c8243 | 3725 | |
85ad76b2 | 3726 | static inline int igb_tso_adv(struct igb_ring *tx_ring, |
9d5c8243 AK |
3727 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) |
3728 | { | |
3729 | struct e1000_adv_tx_context_desc *context_desc; | |
3730 | unsigned int i; | |
3731 | int err; | |
3732 | struct igb_buffer *buffer_info; | |
3733 | u32 info = 0, tu_cmd = 0; | |
91d4ee33 NN |
3734 | u32 mss_l4len_idx; |
3735 | u8 l4len; | |
9d5c8243 AK |
3736 | |
3737 | if (skb_header_cloned(skb)) { | |
3738 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
3739 | if (err) | |
3740 | return err; | |
3741 | } | |
3742 | ||
3743 | l4len = tcp_hdrlen(skb); | |
3744 | *hdr_len += l4len; | |
3745 | ||
3746 | if (skb->protocol == htons(ETH_P_IP)) { | |
3747 | struct iphdr *iph = ip_hdr(skb); | |
3748 | iph->tot_len = 0; | |
3749 | iph->check = 0; | |
3750 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
3751 | iph->daddr, 0, | |
3752 | IPPROTO_TCP, | |
3753 | 0); | |
8e1e8a47 | 3754 | } else if (skb_is_gso_v6(skb)) { |
9d5c8243 AK |
3755 | ipv6_hdr(skb)->payload_len = 0; |
3756 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
3757 | &ipv6_hdr(skb)->daddr, | |
3758 | 0, IPPROTO_TCP, 0); | |
3759 | } | |
3760 | ||
3761 | i = tx_ring->next_to_use; | |
3762 | ||
3763 | buffer_info = &tx_ring->buffer_info[i]; | |
3764 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
3765 | /* VLAN MACLEN IPLEN */ | |
3766 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3767 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
3768 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
3769 | *hdr_len += skb_network_offset(skb); | |
3770 | info |= skb_network_header_len(skb); | |
3771 | *hdr_len += skb_network_header_len(skb); | |
3772 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
3773 | ||
3774 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
3775 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
3776 | ||
3777 | if (skb->protocol == htons(ETH_P_IP)) | |
3778 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; | |
3779 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
3780 | ||
3781 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
3782 | ||
3783 | /* MSS L4LEN IDX */ | |
3784 | mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); | |
3785 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | |
3786 | ||
73cd78f1 | 3787 | /* For 82575, context index must be unique per ring. */ |
85ad76b2 AD |
3788 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) |
3789 | mss_l4len_idx |= tx_ring->reg_idx << 4; | |
9d5c8243 AK |
3790 | |
3791 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
3792 | context_desc->seqnum_seed = 0; | |
3793 | ||
3794 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3795 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3796 | buffer_info->dma = 0; |
3797 | i++; | |
3798 | if (i == tx_ring->count) | |
3799 | i = 0; | |
3800 | ||
3801 | tx_ring->next_to_use = i; | |
3802 | ||
3803 | return true; | |
3804 | } | |
3805 | ||
85ad76b2 AD |
3806 | static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring, |
3807 | struct sk_buff *skb, u32 tx_flags) | |
9d5c8243 AK |
3808 | { |
3809 | struct e1000_adv_tx_context_desc *context_desc; | |
59d71989 | 3810 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
3811 | struct igb_buffer *buffer_info; |
3812 | u32 info = 0, tu_cmd = 0; | |
80785298 | 3813 | unsigned int i; |
9d5c8243 AK |
3814 | |
3815 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | |
3816 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | |
3817 | i = tx_ring->next_to_use; | |
3818 | buffer_info = &tx_ring->buffer_info[i]; | |
3819 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
3820 | ||
3821 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3822 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
cdfd01fc | 3823 | |
9d5c8243 AK |
3824 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); |
3825 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
3826 | info |= skb_network_header_len(skb); | |
3827 | ||
3828 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
3829 | ||
3830 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
3831 | ||
3832 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
fa4a7ef3 AJ |
3833 | __be16 protocol; |
3834 | ||
3835 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { | |
3836 | const struct vlan_ethhdr *vhdr = | |
3837 | (const struct vlan_ethhdr*)skb->data; | |
3838 | ||
3839 | protocol = vhdr->h_vlan_encapsulated_proto; | |
3840 | } else { | |
3841 | protocol = skb->protocol; | |
3842 | } | |
3843 | ||
3844 | switch (protocol) { | |
09640e63 | 3845 | case cpu_to_be16(ETH_P_IP): |
9d5c8243 | 3846 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; |
44b0cda3 MW |
3847 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
3848 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
b9473560 JB |
3849 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
3850 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
44b0cda3 | 3851 | break; |
09640e63 | 3852 | case cpu_to_be16(ETH_P_IPV6): |
44b0cda3 MW |
3853 | /* XXX what about other V6 headers?? */ |
3854 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3855 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
b9473560 JB |
3856 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
3857 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
44b0cda3 MW |
3858 | break; |
3859 | default: | |
3860 | if (unlikely(net_ratelimit())) | |
59d71989 | 3861 | dev_warn(dev, |
44b0cda3 MW |
3862 | "partial checksum but proto=%x!\n", |
3863 | skb->protocol); | |
3864 | break; | |
3865 | } | |
9d5c8243 AK |
3866 | } |
3867 | ||
3868 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
3869 | context_desc->seqnum_seed = 0; | |
85ad76b2 | 3870 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) |
7dfc16fa | 3871 | context_desc->mss_l4len_idx = |
85ad76b2 | 3872 | cpu_to_le32(tx_ring->reg_idx << 4); |
9d5c8243 AK |
3873 | |
3874 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3875 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3876 | buffer_info->dma = 0; |
3877 | ||
3878 | i++; | |
3879 | if (i == tx_ring->count) | |
3880 | i = 0; | |
3881 | tx_ring->next_to_use = i; | |
3882 | ||
3883 | return true; | |
3884 | } | |
9d5c8243 AK |
3885 | return false; |
3886 | } | |
3887 | ||
3888 | #define IGB_MAX_TXD_PWR 16 | |
3889 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | |
3890 | ||
80785298 | 3891 | static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb, |
0e014cb1 | 3892 | unsigned int first) |
9d5c8243 AK |
3893 | { |
3894 | struct igb_buffer *buffer_info; | |
59d71989 | 3895 | struct device *dev = tx_ring->dev; |
2873957d | 3896 | unsigned int hlen = skb_headlen(skb); |
9d5c8243 AK |
3897 | unsigned int count = 0, i; |
3898 | unsigned int f; | |
2873957d | 3899 | u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1; |
9d5c8243 AK |
3900 | |
3901 | i = tx_ring->next_to_use; | |
3902 | ||
3903 | buffer_info = &tx_ring->buffer_info[i]; | |
2873957d NN |
3904 | BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD); |
3905 | buffer_info->length = hlen; | |
9d5c8243 AK |
3906 | /* set time_stamp *before* dma to help avoid a possible race */ |
3907 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3908 | buffer_info->next_to_watch = i; |
2873957d | 3909 | buffer_info->dma = dma_map_single(dev, skb->data, hlen, |
59d71989 AD |
3910 | DMA_TO_DEVICE); |
3911 | if (dma_mapping_error(dev, buffer_info->dma)) | |
6366ad33 | 3912 | goto dma_error; |
9d5c8243 AK |
3913 | |
3914 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
2873957d NN |
3915 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f]; |
3916 | unsigned int len = frag->size; | |
9d5c8243 | 3917 | |
8581145f | 3918 | count++; |
65689fef AD |
3919 | i++; |
3920 | if (i == tx_ring->count) | |
3921 | i = 0; | |
3922 | ||
9d5c8243 AK |
3923 | buffer_info = &tx_ring->buffer_info[i]; |
3924 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
3925 | buffer_info->length = len; | |
3926 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3927 | buffer_info->next_to_watch = i; |
6366ad33 | 3928 | buffer_info->mapped_as_page = true; |
59d71989 | 3929 | buffer_info->dma = dma_map_page(dev, |
6366ad33 AD |
3930 | frag->page, |
3931 | frag->page_offset, | |
3932 | len, | |
59d71989 AD |
3933 | DMA_TO_DEVICE); |
3934 | if (dma_mapping_error(dev, buffer_info->dma)) | |
6366ad33 AD |
3935 | goto dma_error; |
3936 | ||
9d5c8243 AK |
3937 | } |
3938 | ||
9d5c8243 | 3939 | tx_ring->buffer_info[i].skb = skb; |
2873957d NN |
3940 | tx_ring->buffer_info[i].shtx = skb_shinfo(skb)->tx_flags; |
3941 | /* multiply data chunks by size of headers */ | |
3942 | tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len; | |
3943 | tx_ring->buffer_info[i].gso_segs = gso_segs; | |
0e014cb1 | 3944 | tx_ring->buffer_info[first].next_to_watch = i; |
9d5c8243 | 3945 | |
cdfd01fc | 3946 | return ++count; |
6366ad33 AD |
3947 | |
3948 | dma_error: | |
59d71989 | 3949 | dev_err(dev, "TX DMA map failed\n"); |
6366ad33 AD |
3950 | |
3951 | /* clear timestamp and dma mappings for failed buffer_info mapping */ | |
3952 | buffer_info->dma = 0; | |
3953 | buffer_info->time_stamp = 0; | |
3954 | buffer_info->length = 0; | |
3955 | buffer_info->next_to_watch = 0; | |
3956 | buffer_info->mapped_as_page = false; | |
6366ad33 AD |
3957 | |
3958 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
a77ff709 NN |
3959 | while (count--) { |
3960 | if (i == 0) | |
3961 | i = tx_ring->count; | |
6366ad33 | 3962 | i--; |
6366ad33 AD |
3963 | buffer_info = &tx_ring->buffer_info[i]; |
3964 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); | |
3965 | } | |
3966 | ||
3967 | return 0; | |
9d5c8243 AK |
3968 | } |
3969 | ||
85ad76b2 | 3970 | static inline void igb_tx_queue_adv(struct igb_ring *tx_ring, |
91d4ee33 | 3971 | u32 tx_flags, int count, u32 paylen, |
9d5c8243 AK |
3972 | u8 hdr_len) |
3973 | { | |
cdfd01fc | 3974 | union e1000_adv_tx_desc *tx_desc; |
9d5c8243 AK |
3975 | struct igb_buffer *buffer_info; |
3976 | u32 olinfo_status = 0, cmd_type_len; | |
cdfd01fc | 3977 | unsigned int i = tx_ring->next_to_use; |
9d5c8243 AK |
3978 | |
3979 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | |
3980 | E1000_ADVTXD_DCMD_DEXT); | |
3981 | ||
3982 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3983 | cmd_type_len |= E1000_ADVTXD_DCMD_VLE; | |
3984 | ||
33af6bcc PO |
3985 | if (tx_flags & IGB_TX_FLAGS_TSTAMP) |
3986 | cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP; | |
3987 | ||
9d5c8243 AK |
3988 | if (tx_flags & IGB_TX_FLAGS_TSO) { |
3989 | cmd_type_len |= E1000_ADVTXD_DCMD_TSE; | |
3990 | ||
3991 | /* insert tcp checksum */ | |
3992 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
3993 | ||
3994 | /* insert ip checksum */ | |
3995 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
3996 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
3997 | ||
3998 | } else if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
3999 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
4000 | } | |
4001 | ||
85ad76b2 AD |
4002 | if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) && |
4003 | (tx_flags & (IGB_TX_FLAGS_CSUM | | |
4004 | IGB_TX_FLAGS_TSO | | |
7dfc16fa | 4005 | IGB_TX_FLAGS_VLAN))) |
85ad76b2 | 4006 | olinfo_status |= tx_ring->reg_idx << 4; |
9d5c8243 AK |
4007 | |
4008 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | |
4009 | ||
cdfd01fc | 4010 | do { |
9d5c8243 AK |
4011 | buffer_info = &tx_ring->buffer_info[i]; |
4012 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
4013 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
4014 | tx_desc->read.cmd_type_len = | |
4015 | cpu_to_le32(cmd_type_len | buffer_info->length); | |
4016 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
cdfd01fc | 4017 | count--; |
9d5c8243 AK |
4018 | i++; |
4019 | if (i == tx_ring->count) | |
4020 | i = 0; | |
cdfd01fc | 4021 | } while (count > 0); |
9d5c8243 | 4022 | |
85ad76b2 | 4023 | tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD); |
9d5c8243 AK |
4024 | /* Force memory writes to complete before letting h/w |
4025 | * know there are new descriptors to fetch. (Only | |
4026 | * applicable for weak-ordered memory model archs, | |
4027 | * such as IA-64). */ | |
4028 | wmb(); | |
4029 | ||
4030 | tx_ring->next_to_use = i; | |
fce99e34 | 4031 | writel(i, tx_ring->tail); |
9d5c8243 AK |
4032 | /* we need this if more than one processor can write to our tail |
4033 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
4034 | mmiowb(); | |
4035 | } | |
4036 | ||
e694e964 | 4037 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
9d5c8243 | 4038 | { |
e694e964 AD |
4039 | struct net_device *netdev = tx_ring->netdev; |
4040 | ||
661086df | 4041 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 4042 | |
9d5c8243 AK |
4043 | /* Herbert's original patch had: |
4044 | * smp_mb__after_netif_stop_queue(); | |
4045 | * but since that doesn't exist yet, just open code it. */ | |
4046 | smp_mb(); | |
4047 | ||
4048 | /* We need to check again in a case another CPU has just | |
4049 | * made room available. */ | |
c493ea45 | 4050 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
4051 | return -EBUSY; |
4052 | ||
4053 | /* A reprieve! */ | |
661086df | 4054 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
04a5fcaa | 4055 | tx_ring->tx_stats.restart_queue++; |
9d5c8243 AK |
4056 | return 0; |
4057 | } | |
4058 | ||
717ba089 | 4059 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
9d5c8243 | 4060 | { |
c493ea45 | 4061 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 4062 | return 0; |
e694e964 | 4063 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
4064 | } |
4065 | ||
b1a436c3 AD |
4066 | netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb, |
4067 | struct igb_ring *tx_ring) | |
9d5c8243 | 4068 | { |
e694e964 | 4069 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); |
cdfd01fc | 4070 | int tso = 0, count; |
91d4ee33 NN |
4071 | u32 tx_flags = 0; |
4072 | u16 first; | |
4073 | u8 hdr_len = 0; | |
c5b9bd5e | 4074 | union skb_shared_tx *shtx = skb_tx(skb); |
9d5c8243 | 4075 | |
9d5c8243 AK |
4076 | /* need: 1 descriptor per page, |
4077 | * + 2 desc gap to keep tail from touching head, | |
4078 | * + 1 desc for skb->data, | |
4079 | * + 1 desc for context descriptor, | |
4080 | * otherwise try next time */ | |
e694e964 | 4081 | if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { |
9d5c8243 | 4082 | /* this is a hard error */ |
9d5c8243 AK |
4083 | return NETDEV_TX_BUSY; |
4084 | } | |
33af6bcc | 4085 | |
33af6bcc PO |
4086 | if (unlikely(shtx->hardware)) { |
4087 | shtx->in_progress = 1; | |
4088 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
33af6bcc | 4089 | } |
9d5c8243 | 4090 | |
cdfd01fc | 4091 | if (vlan_tx_tag_present(skb) && adapter->vlgrp) { |
9d5c8243 AK |
4092 | tx_flags |= IGB_TX_FLAGS_VLAN; |
4093 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
4094 | } | |
4095 | ||
661086df PWJ |
4096 | if (skb->protocol == htons(ETH_P_IP)) |
4097 | tx_flags |= IGB_TX_FLAGS_IPV4; | |
4098 | ||
0e014cb1 | 4099 | first = tx_ring->next_to_use; |
85ad76b2 AD |
4100 | if (skb_is_gso(skb)) { |
4101 | tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len); | |
cdfd01fc | 4102 | |
85ad76b2 AD |
4103 | if (tso < 0) { |
4104 | dev_kfree_skb_any(skb); | |
4105 | return NETDEV_TX_OK; | |
4106 | } | |
9d5c8243 AK |
4107 | } |
4108 | ||
4109 | if (tso) | |
4110 | tx_flags |= IGB_TX_FLAGS_TSO; | |
85ad76b2 | 4111 | else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) && |
bc1cbd34 AD |
4112 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
4113 | tx_flags |= IGB_TX_FLAGS_CSUM; | |
9d5c8243 | 4114 | |
65689fef | 4115 | /* |
cdfd01fc | 4116 | * count reflects descriptors mapped, if 0 or less then mapping error |
65689fef AD |
4117 | * has occured and we need to rewind the descriptor queue |
4118 | */ | |
80785298 | 4119 | count = igb_tx_map_adv(tx_ring, skb, first); |
6366ad33 | 4120 | if (!count) { |
65689fef AD |
4121 | dev_kfree_skb_any(skb); |
4122 | tx_ring->buffer_info[first].time_stamp = 0; | |
4123 | tx_ring->next_to_use = first; | |
85ad76b2 | 4124 | return NETDEV_TX_OK; |
65689fef | 4125 | } |
9d5c8243 | 4126 | |
85ad76b2 AD |
4127 | igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len); |
4128 | ||
4129 | /* Make sure there is space in the ring for the next send. */ | |
e694e964 | 4130 | igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); |
85ad76b2 | 4131 | |
9d5c8243 AK |
4132 | return NETDEV_TX_OK; |
4133 | } | |
4134 | ||
3b29a56d SH |
4135 | static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, |
4136 | struct net_device *netdev) | |
9d5c8243 AK |
4137 | { |
4138 | struct igb_adapter *adapter = netdev_priv(netdev); | |
661086df | 4139 | struct igb_ring *tx_ring; |
661086df | 4140 | int r_idx = 0; |
b1a436c3 AD |
4141 | |
4142 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4143 | dev_kfree_skb_any(skb); | |
4144 | return NETDEV_TX_OK; | |
4145 | } | |
4146 | ||
4147 | if (skb->len <= 0) { | |
4148 | dev_kfree_skb_any(skb); | |
4149 | return NETDEV_TX_OK; | |
4150 | } | |
4151 | ||
1bfaf07b | 4152 | r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); |
661086df | 4153 | tx_ring = adapter->multi_tx_table[r_idx]; |
9d5c8243 AK |
4154 | |
4155 | /* This goes back to the question of how to logically map a tx queue | |
4156 | * to a flow. Right now, performance is impacted slightly negatively | |
4157 | * if using multiple tx queues. If the stack breaks away from a | |
4158 | * single qdisc implementation, we can look at this again. */ | |
e694e964 | 4159 | return igb_xmit_frame_ring_adv(skb, tx_ring); |
9d5c8243 AK |
4160 | } |
4161 | ||
4162 | /** | |
4163 | * igb_tx_timeout - Respond to a Tx Hang | |
4164 | * @netdev: network interface device structure | |
4165 | **/ | |
4166 | static void igb_tx_timeout(struct net_device *netdev) | |
4167 | { | |
4168 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4169 | struct e1000_hw *hw = &adapter->hw; | |
4170 | ||
4171 | /* Do the reset outside of interrupt context */ | |
4172 | adapter->tx_timeout_count++; | |
f7ba205e | 4173 | |
55cac248 AD |
4174 | if (hw->mac.type == e1000_82580) |
4175 | hw->dev_spec._82575.global_device_reset = true; | |
4176 | ||
9d5c8243 | 4177 | schedule_work(&adapter->reset_task); |
265de409 AD |
4178 | wr32(E1000_EICS, |
4179 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
4180 | } |
4181 | ||
4182 | static void igb_reset_task(struct work_struct *work) | |
4183 | { | |
4184 | struct igb_adapter *adapter; | |
4185 | adapter = container_of(work, struct igb_adapter, reset_task); | |
4186 | ||
c97ec42a TI |
4187 | igb_dump(adapter); |
4188 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
9d5c8243 AK |
4189 | igb_reinit_locked(adapter); |
4190 | } | |
4191 | ||
4192 | /** | |
4193 | * igb_get_stats - Get System Network Statistics | |
4194 | * @netdev: network interface device structure | |
4195 | * | |
4196 | * Returns the address of the device statistics structure. | |
4197 | * The statistics are actually updated from the timer callback. | |
4198 | **/ | |
73cd78f1 | 4199 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) |
9d5c8243 | 4200 | { |
9d5c8243 | 4201 | /* only return the current stats */ |
8d24e933 | 4202 | return &netdev->stats; |
9d5c8243 AK |
4203 | } |
4204 | ||
4205 | /** | |
4206 | * igb_change_mtu - Change the Maximum Transfer Unit | |
4207 | * @netdev: network interface device structure | |
4208 | * @new_mtu: new value for maximum frame size | |
4209 | * | |
4210 | * Returns 0 on success, negative on failure | |
4211 | **/ | |
4212 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
4213 | { | |
4214 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4215 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 4216 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
4c844851 | 4217 | u32 rx_buffer_len, i; |
9d5c8243 | 4218 | |
c809d227 | 4219 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 4220 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
4221 | return -EINVAL; |
4222 | } | |
4223 | ||
9d5c8243 | 4224 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 4225 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
4226 | return -EINVAL; |
4227 | } | |
4228 | ||
4229 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
4230 | msleep(1); | |
73cd78f1 | 4231 | |
9d5c8243 AK |
4232 | /* igb_down has a dependency on max_frame_size */ |
4233 | adapter->max_frame_size = max_frame; | |
559e9c49 | 4234 | |
9d5c8243 AK |
4235 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN |
4236 | * means we reserve 2 more, this pushes us to allocate from the next | |
4237 | * larger slab size. | |
4238 | * i.e. RXBUFFER_2048 --> size-4096 slab | |
4239 | */ | |
4240 | ||
757b77e2 NN |
4241 | if (adapter->hw.mac.type == e1000_82580) |
4242 | max_frame += IGB_TS_HDR_LEN; | |
4243 | ||
7d95b717 | 4244 | if (max_frame <= IGB_RXBUFFER_1024) |
4c844851 | 4245 | rx_buffer_len = IGB_RXBUFFER_1024; |
6ec43fe6 | 4246 | else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE) |
4c844851 | 4247 | rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
6ec43fe6 | 4248 | else |
4c844851 AD |
4249 | rx_buffer_len = IGB_RXBUFFER_128; |
4250 | ||
757b77e2 NN |
4251 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN + IGB_TS_HDR_LEN) || |
4252 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN)) | |
4253 | rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN; | |
4254 | ||
4255 | if ((adapter->hw.mac.type == e1000_82580) && | |
4256 | (rx_buffer_len == IGB_RXBUFFER_128)) | |
4257 | rx_buffer_len += IGB_RXBUFFER_64; | |
4258 | ||
4c844851 AD |
4259 | if (netif_running(netdev)) |
4260 | igb_down(adapter); | |
9d5c8243 | 4261 | |
090b1795 | 4262 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
4263 | netdev->mtu, new_mtu); |
4264 | netdev->mtu = new_mtu; | |
4265 | ||
4c844851 | 4266 | for (i = 0; i < adapter->num_rx_queues; i++) |
3025a446 | 4267 | adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len; |
4c844851 | 4268 | |
9d5c8243 AK |
4269 | if (netif_running(netdev)) |
4270 | igb_up(adapter); | |
4271 | else | |
4272 | igb_reset(adapter); | |
4273 | ||
4274 | clear_bit(__IGB_RESETTING, &adapter->state); | |
4275 | ||
4276 | return 0; | |
4277 | } | |
4278 | ||
4279 | /** | |
4280 | * igb_update_stats - Update the board statistics counters | |
4281 | * @adapter: board private structure | |
4282 | **/ | |
4283 | ||
4284 | void igb_update_stats(struct igb_adapter *adapter) | |
4285 | { | |
128e45eb | 4286 | struct net_device_stats *net_stats = igb_get_stats(adapter->netdev); |
9d5c8243 AK |
4287 | struct e1000_hw *hw = &adapter->hw; |
4288 | struct pci_dev *pdev = adapter->pdev; | |
fa3d9a6d | 4289 | u32 reg, mpc; |
9d5c8243 | 4290 | u16 phy_tmp; |
3f9c0164 AD |
4291 | int i; |
4292 | u64 bytes, packets; | |
9d5c8243 AK |
4293 | |
4294 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
4295 | ||
4296 | /* | |
4297 | * Prevent stats update while adapter is being reset, or if the pci | |
4298 | * connection is down. | |
4299 | */ | |
4300 | if (adapter->link_speed == 0) | |
4301 | return; | |
4302 | if (pci_channel_offline(pdev)) | |
4303 | return; | |
4304 | ||
3f9c0164 AD |
4305 | bytes = 0; |
4306 | packets = 0; | |
4307 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4308 | u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF; | |
3025a446 AD |
4309 | struct igb_ring *ring = adapter->rx_ring[i]; |
4310 | ring->rx_stats.drops += rqdpc_tmp; | |
128e45eb | 4311 | net_stats->rx_fifo_errors += rqdpc_tmp; |
3025a446 AD |
4312 | bytes += ring->rx_stats.bytes; |
4313 | packets += ring->rx_stats.packets; | |
3f9c0164 AD |
4314 | } |
4315 | ||
128e45eb AD |
4316 | net_stats->rx_bytes = bytes; |
4317 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
4318 | |
4319 | bytes = 0; | |
4320 | packets = 0; | |
4321 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 AD |
4322 | struct igb_ring *ring = adapter->tx_ring[i]; |
4323 | bytes += ring->tx_stats.bytes; | |
4324 | packets += ring->tx_stats.packets; | |
3f9c0164 | 4325 | } |
128e45eb AD |
4326 | net_stats->tx_bytes = bytes; |
4327 | net_stats->tx_packets = packets; | |
3f9c0164 AD |
4328 | |
4329 | /* read stats registers */ | |
9d5c8243 AK |
4330 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
4331 | adapter->stats.gprc += rd32(E1000_GPRC); | |
4332 | adapter->stats.gorc += rd32(E1000_GORCL); | |
4333 | rd32(E1000_GORCH); /* clear GORCL */ | |
4334 | adapter->stats.bprc += rd32(E1000_BPRC); | |
4335 | adapter->stats.mprc += rd32(E1000_MPRC); | |
4336 | adapter->stats.roc += rd32(E1000_ROC); | |
4337 | ||
4338 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
4339 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
4340 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
4341 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
4342 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
4343 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
4344 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
4345 | adapter->stats.sec += rd32(E1000_SEC); | |
4346 | ||
fa3d9a6d MW |
4347 | mpc = rd32(E1000_MPC); |
4348 | adapter->stats.mpc += mpc; | |
4349 | net_stats->rx_fifo_errors += mpc; | |
9d5c8243 AK |
4350 | adapter->stats.scc += rd32(E1000_SCC); |
4351 | adapter->stats.ecol += rd32(E1000_ECOL); | |
4352 | adapter->stats.mcc += rd32(E1000_MCC); | |
4353 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
4354 | adapter->stats.dc += rd32(E1000_DC); | |
4355 | adapter->stats.rlec += rd32(E1000_RLEC); | |
4356 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
4357 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
4358 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
4359 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
4360 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
4361 | adapter->stats.gptc += rd32(E1000_GPTC); | |
4362 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
4363 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
fa3d9a6d | 4364 | adapter->stats.rnbc += rd32(E1000_RNBC); |
9d5c8243 AK |
4365 | adapter->stats.ruc += rd32(E1000_RUC); |
4366 | adapter->stats.rfc += rd32(E1000_RFC); | |
4367 | adapter->stats.rjc += rd32(E1000_RJC); | |
4368 | adapter->stats.tor += rd32(E1000_TORH); | |
4369 | adapter->stats.tot += rd32(E1000_TOTH); | |
4370 | adapter->stats.tpr += rd32(E1000_TPR); | |
4371 | ||
4372 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
4373 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
4374 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
4375 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
4376 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4377 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4378 | ||
4379 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4380 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4381 | ||
2d0b0f69 NN |
4382 | adapter->stats.tpt += rd32(E1000_TPT); |
4383 | adapter->stats.colc += rd32(E1000_COLC); | |
9d5c8243 AK |
4384 | |
4385 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
43915c7c NN |
4386 | /* read internal phy specific stats */ |
4387 | reg = rd32(E1000_CTRL_EXT); | |
4388 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | |
4389 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
4390 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
4391 | } | |
4392 | ||
9d5c8243 AK |
4393 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
4394 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
4395 | ||
4396 | adapter->stats.iac += rd32(E1000_IAC); | |
4397 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
4398 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
4399 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
4400 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
4401 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
4402 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
4403 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
4404 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
4405 | ||
4406 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
4407 | net_stats->multicast = adapter->stats.mprc; |
4408 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
4409 | |
4410 | /* Rx Errors */ | |
4411 | ||
4412 | /* RLEC on some newer hardware can be incorrect so build | |
8c0ab70a | 4413 | * our own version based on RUC and ROC */ |
128e45eb | 4414 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
4415 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4416 | adapter->stats.ruc + adapter->stats.roc + | |
4417 | adapter->stats.cexterr; | |
128e45eb AD |
4418 | net_stats->rx_length_errors = adapter->stats.ruc + |
4419 | adapter->stats.roc; | |
4420 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
4421 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
4422 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
4423 | |
4424 | /* Tx Errors */ | |
128e45eb AD |
4425 | net_stats->tx_errors = adapter->stats.ecol + |
4426 | adapter->stats.latecol; | |
4427 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
4428 | net_stats->tx_window_errors = adapter->stats.latecol; | |
4429 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
4430 | |
4431 | /* Tx Dropped needs to be maintained elsewhere */ | |
4432 | ||
4433 | /* Phy Stats */ | |
4434 | if (hw->phy.media_type == e1000_media_type_copper) { | |
4435 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 4436 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
4437 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
4438 | adapter->phy_stats.idle_errors += phy_tmp; | |
4439 | } | |
4440 | } | |
4441 | ||
4442 | /* Management Stats */ | |
4443 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
4444 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
4445 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
4446 | } | |
4447 | ||
9d5c8243 AK |
4448 | static irqreturn_t igb_msix_other(int irq, void *data) |
4449 | { | |
047e0030 | 4450 | struct igb_adapter *adapter = data; |
9d5c8243 | 4451 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 4452 | u32 icr = rd32(E1000_ICR); |
844290e5 | 4453 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 4454 | |
7f081d40 AD |
4455 | if (icr & E1000_ICR_DRSTA) |
4456 | schedule_work(&adapter->reset_task); | |
4457 | ||
047e0030 | 4458 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4459 | /* HW is reporting DMA is out of sync */ |
4460 | adapter->stats.doosync++; | |
4461 | } | |
eebbbdba | 4462 | |
4ae196df AD |
4463 | /* Check for a mailbox event */ |
4464 | if (icr & E1000_ICR_VMMB) | |
4465 | igb_msg_task(adapter); | |
4466 | ||
4467 | if (icr & E1000_ICR_LSC) { | |
4468 | hw->mac.get_link_status = 1; | |
4469 | /* guard against interrupt when we're going down */ | |
4470 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4471 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4472 | } | |
4473 | ||
25568a53 AD |
4474 | if (adapter->vfs_allocated_count) |
4475 | wr32(E1000_IMS, E1000_IMS_LSC | | |
4476 | E1000_IMS_VMMB | | |
4477 | E1000_IMS_DOUTSYNC); | |
4478 | else | |
4479 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); | |
844290e5 | 4480 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
4481 | |
4482 | return IRQ_HANDLED; | |
4483 | } | |
4484 | ||
047e0030 | 4485 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4486 | { |
26b39276 | 4487 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 4488 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 4489 | |
047e0030 AD |
4490 | if (!q_vector->set_itr) |
4491 | return; | |
73cd78f1 | 4492 | |
047e0030 AD |
4493 | if (!itr_val) |
4494 | itr_val = 0x4; | |
661086df | 4495 | |
26b39276 AD |
4496 | if (adapter->hw.mac.type == e1000_82575) |
4497 | itr_val |= itr_val << 16; | |
661086df | 4498 | else |
047e0030 | 4499 | itr_val |= 0x8000000; |
661086df | 4500 | |
047e0030 AD |
4501 | writel(itr_val, q_vector->itr_register); |
4502 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
4503 | } |
4504 | ||
047e0030 | 4505 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 4506 | { |
047e0030 | 4507 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 4508 | |
047e0030 AD |
4509 | /* Write the ITR value calculated from the previous interrupt. */ |
4510 | igb_write_itr(q_vector); | |
9d5c8243 | 4511 | |
047e0030 | 4512 | napi_schedule(&q_vector->napi); |
844290e5 | 4513 | |
047e0030 | 4514 | return IRQ_HANDLED; |
fe4506b6 JC |
4515 | } |
4516 | ||
421e02f0 | 4517 | #ifdef CONFIG_IGB_DCA |
047e0030 | 4518 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 4519 | { |
047e0030 | 4520 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 JC |
4521 | struct e1000_hw *hw = &adapter->hw; |
4522 | int cpu = get_cpu(); | |
fe4506b6 | 4523 | |
047e0030 AD |
4524 | if (q_vector->cpu == cpu) |
4525 | goto out_no_update; | |
4526 | ||
4527 | if (q_vector->tx_ring) { | |
4528 | int q = q_vector->tx_ring->reg_idx; | |
4529 | u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
4530 | if (hw->mac.type == e1000_82575) { | |
4531 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
4532 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
2d064c06 | 4533 | } else { |
047e0030 AD |
4534 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; |
4535 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | |
4536 | E1000_DCA_TXCTRL_CPUID_SHIFT; | |
4537 | } | |
4538 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; | |
4539 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
4540 | } | |
4541 | if (q_vector->rx_ring) { | |
4542 | int q = q_vector->rx_ring->reg_idx; | |
4543 | u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
4544 | if (hw->mac.type == e1000_82575) { | |
2d064c06 | 4545 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; |
92be7917 | 4546 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
047e0030 AD |
4547 | } else { |
4548 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
4549 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | |
4550 | E1000_DCA_RXCTRL_CPUID_SHIFT; | |
2d064c06 | 4551 | } |
fe4506b6 JC |
4552 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
4553 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
4554 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
4555 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
fe4506b6 | 4556 | } |
047e0030 AD |
4557 | q_vector->cpu = cpu; |
4558 | out_no_update: | |
fe4506b6 JC |
4559 | put_cpu(); |
4560 | } | |
4561 | ||
4562 | static void igb_setup_dca(struct igb_adapter *adapter) | |
4563 | { | |
7e0e99ef | 4564 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
4565 | int i; |
4566 | ||
7dfc16fa | 4567 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
4568 | return; |
4569 | ||
7e0e99ef AD |
4570 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
4571 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
4572 | ||
047e0030 | 4573 | for (i = 0; i < adapter->num_q_vectors; i++) { |
26b39276 AD |
4574 | adapter->q_vector[i]->cpu = -1; |
4575 | igb_update_dca(adapter->q_vector[i]); | |
fe4506b6 JC |
4576 | } |
4577 | } | |
4578 | ||
4579 | static int __igb_notify_dca(struct device *dev, void *data) | |
4580 | { | |
4581 | struct net_device *netdev = dev_get_drvdata(dev); | |
4582 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4583 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
4584 | struct e1000_hw *hw = &adapter->hw; |
4585 | unsigned long event = *(unsigned long *)data; | |
4586 | ||
4587 | switch (event) { | |
4588 | case DCA_PROVIDER_ADD: | |
4589 | /* if already enabled, don't do it again */ | |
7dfc16fa | 4590 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 4591 | break; |
fe4506b6 | 4592 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 4593 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 4594 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
4595 | igb_setup_dca(adapter); |
4596 | break; | |
4597 | } | |
4598 | /* Fall Through since DCA is disabled. */ | |
4599 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 4600 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 4601 | /* without this a class_device is left |
047e0030 | 4602 | * hanging around in the sysfs model */ |
fe4506b6 | 4603 | dca_remove_requester(dev); |
090b1795 | 4604 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 4605 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 4606 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
4607 | } |
4608 | break; | |
4609 | } | |
bbd98fe4 | 4610 | |
fe4506b6 | 4611 | return 0; |
9d5c8243 AK |
4612 | } |
4613 | ||
fe4506b6 JC |
4614 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
4615 | void *p) | |
4616 | { | |
4617 | int ret_val; | |
4618 | ||
4619 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
4620 | __igb_notify_dca); | |
4621 | ||
4622 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4623 | } | |
421e02f0 | 4624 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 4625 | |
4ae196df AD |
4626 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
4627 | { | |
4628 | struct e1000_hw *hw = &adapter->hw; | |
4629 | u32 ping; | |
4630 | int i; | |
4631 | ||
4632 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
4633 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 4634 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
4635 | ping |= E1000_VT_MSGTYPE_CTS; |
4636 | igb_write_mbx(hw, &ping, 1, i); | |
4637 | } | |
4638 | } | |
4639 | ||
7d5753f0 AD |
4640 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
4641 | { | |
4642 | struct e1000_hw *hw = &adapter->hw; | |
4643 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
4644 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
4645 | ||
4646 | vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC | | |
4647 | IGB_VF_FLAG_MULTI_PROMISC); | |
4648 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
4649 | ||
4650 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
4651 | vmolr |= E1000_VMOLR_MPME; | |
4652 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; | |
4653 | } else { | |
4654 | /* | |
4655 | * if we have hashes and we are clearing a multicast promisc | |
4656 | * flag we need to write the hashes to the MTA as this step | |
4657 | * was previously skipped | |
4658 | */ | |
4659 | if (vf_data->num_vf_mc_hashes > 30) { | |
4660 | vmolr |= E1000_VMOLR_MPME; | |
4661 | } else if (vf_data->num_vf_mc_hashes) { | |
4662 | int j; | |
4663 | vmolr |= E1000_VMOLR_ROMPE; | |
4664 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
4665 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
4666 | } | |
4667 | } | |
4668 | ||
4669 | wr32(E1000_VMOLR(vf), vmolr); | |
4670 | ||
4671 | /* there are flags left unprocessed, likely not supported */ | |
4672 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
4673 | return -EINVAL; | |
4674 | ||
4675 | return 0; | |
4676 | ||
4677 | } | |
4678 | ||
4ae196df AD |
4679 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
4680 | u32 *msgbuf, u32 vf) | |
4681 | { | |
4682 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
4683 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
4684 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
4685 | int i; | |
4686 | ||
7d5753f0 | 4687 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
4688 | * to this VF for later use to restore when the PF multi cast |
4689 | * list changes | |
4690 | */ | |
4691 | vf_data->num_vf_mc_hashes = n; | |
4692 | ||
7d5753f0 AD |
4693 | /* only up to 30 hash values supported */ |
4694 | if (n > 30) | |
4695 | n = 30; | |
4696 | ||
4697 | /* store the hashes for later use */ | |
4ae196df | 4698 | for (i = 0; i < n; i++) |
a419aef8 | 4699 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
4700 | |
4701 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 4702 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
4703 | |
4704 | return 0; | |
4705 | } | |
4706 | ||
4707 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
4708 | { | |
4709 | struct e1000_hw *hw = &adapter->hw; | |
4710 | struct vf_data_storage *vf_data; | |
4711 | int i, j; | |
4712 | ||
4713 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
4714 | u32 vmolr = rd32(E1000_VMOLR(i)); |
4715 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
4716 | ||
4ae196df | 4717 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
4718 | |
4719 | if ((vf_data->num_vf_mc_hashes > 30) || | |
4720 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
4721 | vmolr |= E1000_VMOLR_MPME; | |
4722 | } else if (vf_data->num_vf_mc_hashes) { | |
4723 | vmolr |= E1000_VMOLR_ROMPE; | |
4724 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
4725 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
4726 | } | |
4727 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
4728 | } |
4729 | } | |
4730 | ||
4731 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
4732 | { | |
4733 | struct e1000_hw *hw = &adapter->hw; | |
4734 | u32 pool_mask, reg, vid; | |
4735 | int i; | |
4736 | ||
4737 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
4738 | ||
4739 | /* Find the vlan filter for this id */ | |
4740 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
4741 | reg = rd32(E1000_VLVF(i)); | |
4742 | ||
4743 | /* remove the vf from the pool */ | |
4744 | reg &= ~pool_mask; | |
4745 | ||
4746 | /* if pool is empty then remove entry from vfta */ | |
4747 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
4748 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
4749 | reg = 0; | |
4750 | vid = reg & E1000_VLVF_VLANID_MASK; | |
4751 | igb_vfta_set(hw, vid, false); | |
4752 | } | |
4753 | ||
4754 | wr32(E1000_VLVF(i), reg); | |
4755 | } | |
ae641bdc AD |
4756 | |
4757 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
4758 | } |
4759 | ||
4760 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
4761 | { | |
4762 | struct e1000_hw *hw = &adapter->hw; | |
4763 | u32 reg, i; | |
4764 | ||
51466239 AD |
4765 | /* The vlvf table only exists on 82576 hardware and newer */ |
4766 | if (hw->mac.type < e1000_82576) | |
4767 | return -1; | |
4768 | ||
4769 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
4770 | if (!adapter->vfs_allocated_count) |
4771 | return -1; | |
4772 | ||
4773 | /* Find the vlan filter for this id */ | |
4774 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
4775 | reg = rd32(E1000_VLVF(i)); | |
4776 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
4777 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
4778 | break; | |
4779 | } | |
4780 | ||
4781 | if (add) { | |
4782 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
4783 | /* Did not find a matching VLAN ID entry that was | |
4784 | * enabled. Search for a free filter entry, i.e. | |
4785 | * one without the enable bit set | |
4786 | */ | |
4787 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
4788 | reg = rd32(E1000_VLVF(i)); | |
4789 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
4790 | break; | |
4791 | } | |
4792 | } | |
4793 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
4794 | /* Found an enabled/available entry */ | |
4795 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
4796 | ||
4797 | /* if !enabled we need to set this up in vfta */ | |
4798 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
4799 | /* add VID to filter table */ |
4800 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
4801 | reg |= E1000_VLVF_VLANID_ENABLE; |
4802 | } | |
cad6d05f AD |
4803 | reg &= ~E1000_VLVF_VLANID_MASK; |
4804 | reg |= vid; | |
4ae196df | 4805 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
4806 | |
4807 | /* do not modify RLPML for PF devices */ | |
4808 | if (vf >= adapter->vfs_allocated_count) | |
4809 | return 0; | |
4810 | ||
4811 | if (!adapter->vf_data[vf].vlans_enabled) { | |
4812 | u32 size; | |
4813 | reg = rd32(E1000_VMOLR(vf)); | |
4814 | size = reg & E1000_VMOLR_RLPML_MASK; | |
4815 | size += 4; | |
4816 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
4817 | reg |= size; | |
4818 | wr32(E1000_VMOLR(vf), reg); | |
4819 | } | |
ae641bdc | 4820 | |
51466239 | 4821 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
4822 | return 0; |
4823 | } | |
4824 | } else { | |
4825 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
4826 | /* remove vf from the pool */ | |
4827 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
4828 | /* if pool is empty then remove entry from vfta */ | |
4829 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
4830 | reg = 0; | |
4831 | igb_vfta_set(hw, vid, false); | |
4832 | } | |
4833 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
4834 | |
4835 | /* do not modify RLPML for PF devices */ | |
4836 | if (vf >= adapter->vfs_allocated_count) | |
4837 | return 0; | |
4838 | ||
4839 | adapter->vf_data[vf].vlans_enabled--; | |
4840 | if (!adapter->vf_data[vf].vlans_enabled) { | |
4841 | u32 size; | |
4842 | reg = rd32(E1000_VMOLR(vf)); | |
4843 | size = reg & E1000_VMOLR_RLPML_MASK; | |
4844 | size -= 4; | |
4845 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
4846 | reg |= size; | |
4847 | wr32(E1000_VMOLR(vf), reg); | |
4848 | } | |
4ae196df AD |
4849 | } |
4850 | } | |
8151d294 WM |
4851 | return 0; |
4852 | } | |
4853 | ||
4854 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | |
4855 | { | |
4856 | struct e1000_hw *hw = &adapter->hw; | |
4857 | ||
4858 | if (vid) | |
4859 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | |
4860 | else | |
4861 | wr32(E1000_VMVIR(vf), 0); | |
4862 | } | |
4863 | ||
4864 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
4865 | int vf, u16 vlan, u8 qos) | |
4866 | { | |
4867 | int err = 0; | |
4868 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4869 | ||
4870 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | |
4871 | return -EINVAL; | |
4872 | if (vlan || qos) { | |
4873 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | |
4874 | if (err) | |
4875 | goto out; | |
4876 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | |
4877 | igb_set_vmolr(adapter, vf, !vlan); | |
4878 | adapter->vf_data[vf].pf_vlan = vlan; | |
4879 | adapter->vf_data[vf].pf_qos = qos; | |
4880 | dev_info(&adapter->pdev->dev, | |
4881 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | |
4882 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4883 | dev_warn(&adapter->pdev->dev, | |
4884 | "The VF VLAN has been set," | |
4885 | " but the PF device is not up.\n"); | |
4886 | dev_warn(&adapter->pdev->dev, | |
4887 | "Bring the PF device up before" | |
4888 | " attempting to use the VF device.\n"); | |
4889 | } | |
4890 | } else { | |
4891 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | |
4892 | false, vf); | |
4893 | igb_set_vmvir(adapter, vlan, vf); | |
4894 | igb_set_vmolr(adapter, vf, true); | |
4895 | adapter->vf_data[vf].pf_vlan = 0; | |
4896 | adapter->vf_data[vf].pf_qos = 0; | |
4897 | } | |
4898 | out: | |
4899 | return err; | |
4ae196df AD |
4900 | } |
4901 | ||
4902 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
4903 | { | |
4904 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
4905 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
4906 | ||
4907 | return igb_vlvf_set(adapter, vid, add, vf); | |
4908 | } | |
4909 | ||
f2ca0dbe | 4910 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 4911 | { |
8151d294 WM |
4912 | /* clear flags */ |
4913 | adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC); | |
f2ca0dbe | 4914 | adapter->vf_data[vf].last_nack = jiffies; |
4ae196df AD |
4915 | |
4916 | /* reset offloads to defaults */ | |
8151d294 | 4917 | igb_set_vmolr(adapter, vf, true); |
4ae196df AD |
4918 | |
4919 | /* reset vlans for device */ | |
4920 | igb_clear_vf_vfta(adapter, vf); | |
8151d294 WM |
4921 | if (adapter->vf_data[vf].pf_vlan) |
4922 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | |
4923 | adapter->vf_data[vf].pf_vlan, | |
4924 | adapter->vf_data[vf].pf_qos); | |
4925 | else | |
4926 | igb_clear_vf_vfta(adapter, vf); | |
4ae196df AD |
4927 | |
4928 | /* reset multicast table array for vf */ | |
4929 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
4930 | ||
4931 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 4932 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
4933 | } |
4934 | ||
f2ca0dbe AD |
4935 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
4936 | { | |
4937 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
4938 | ||
4939 | /* generate a new mac address as we were hotplug removed/added */ | |
8151d294 WM |
4940 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
4941 | random_ether_addr(vf_mac); | |
f2ca0dbe AD |
4942 | |
4943 | /* process remaining reset events */ | |
4944 | igb_vf_reset(adapter, vf); | |
4945 | } | |
4946 | ||
4947 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
4948 | { |
4949 | struct e1000_hw *hw = &adapter->hw; | |
4950 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 4951 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
4952 | u32 reg, msgbuf[3]; |
4953 | u8 *addr = (u8 *)(&msgbuf[1]); | |
4954 | ||
4955 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 4956 | igb_vf_reset(adapter, vf); |
4ae196df AD |
4957 | |
4958 | /* set vf mac address */ | |
26ad9178 | 4959 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
4960 | |
4961 | /* enable transmit and receive for vf */ | |
4962 | reg = rd32(E1000_VFTE); | |
4963 | wr32(E1000_VFTE, reg | (1 << vf)); | |
4964 | reg = rd32(E1000_VFRE); | |
4965 | wr32(E1000_VFRE, reg | (1 << vf)); | |
4966 | ||
f2ca0dbe | 4967 | adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS; |
4ae196df AD |
4968 | |
4969 | /* reply to reset with ack and vf mac address */ | |
4970 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
4971 | memcpy(addr, vf_mac, 6); | |
4972 | igb_write_mbx(hw, msgbuf, 3, vf); | |
4973 | } | |
4974 | ||
4975 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
4976 | { | |
f2ca0dbe AD |
4977 | unsigned char *addr = (char *)&msg[1]; |
4978 | int err = -1; | |
4ae196df | 4979 | |
f2ca0dbe AD |
4980 | if (is_valid_ether_addr(addr)) |
4981 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 4982 | |
f2ca0dbe | 4983 | return err; |
4ae196df AD |
4984 | } |
4985 | ||
4986 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
4987 | { | |
4988 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 4989 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
4990 | u32 msg = E1000_VT_MSGTYPE_NACK; |
4991 | ||
4992 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
4993 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
4994 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 4995 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 4996 | vf_data->last_nack = jiffies; |
4ae196df AD |
4997 | } |
4998 | } | |
4999 | ||
f2ca0dbe | 5000 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5001 | { |
f2ca0dbe AD |
5002 | struct pci_dev *pdev = adapter->pdev; |
5003 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 5004 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 5005 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5006 | s32 retval; |
5007 | ||
f2ca0dbe | 5008 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df | 5009 | |
fef45f4c AD |
5010 | if (retval) { |
5011 | /* if receive failed revoke VF CTS stats and restart init */ | |
f2ca0dbe | 5012 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
fef45f4c AD |
5013 | vf_data->flags &= ~IGB_VF_FLAG_CTS; |
5014 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | |
5015 | return; | |
5016 | goto out; | |
5017 | } | |
4ae196df AD |
5018 | |
5019 | /* this is a message we already processed, do nothing */ | |
5020 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 5021 | return; |
4ae196df AD |
5022 | |
5023 | /* | |
5024 | * until the vf completes a reset it should not be | |
5025 | * allowed to start any configuration. | |
5026 | */ | |
5027 | ||
5028 | if (msgbuf[0] == E1000_VF_RESET) { | |
5029 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 5030 | return; |
4ae196df AD |
5031 | } |
5032 | ||
f2ca0dbe | 5033 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
fef45f4c AD |
5034 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
5035 | return; | |
5036 | retval = -1; | |
5037 | goto out; | |
4ae196df AD |
5038 | } |
5039 | ||
5040 | switch ((msgbuf[0] & 0xFFFF)) { | |
5041 | case E1000_VF_SET_MAC_ADDR: | |
5042 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
5043 | break; | |
7d5753f0 AD |
5044 | case E1000_VF_SET_PROMISC: |
5045 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
5046 | break; | |
4ae196df AD |
5047 | case E1000_VF_SET_MULTICAST: |
5048 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
5049 | break; | |
5050 | case E1000_VF_SET_LPE: | |
5051 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
5052 | break; | |
5053 | case E1000_VF_SET_VLAN: | |
8151d294 WM |
5054 | if (adapter->vf_data[vf].pf_vlan) |
5055 | retval = -1; | |
5056 | else | |
5057 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4ae196df AD |
5058 | break; |
5059 | default: | |
090b1795 | 5060 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
5061 | retval = -1; |
5062 | break; | |
5063 | } | |
5064 | ||
fef45f4c AD |
5065 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
5066 | out: | |
4ae196df AD |
5067 | /* notify the VF of the results of what it sent us */ |
5068 | if (retval) | |
5069 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
5070 | else | |
5071 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
5072 | ||
4ae196df | 5073 | igb_write_mbx(hw, msgbuf, 1, vf); |
f2ca0dbe | 5074 | } |
4ae196df | 5075 | |
f2ca0dbe AD |
5076 | static void igb_msg_task(struct igb_adapter *adapter) |
5077 | { | |
5078 | struct e1000_hw *hw = &adapter->hw; | |
5079 | u32 vf; | |
5080 | ||
5081 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
5082 | /* process any reset requests */ | |
5083 | if (!igb_check_for_rst(hw, vf)) | |
5084 | igb_vf_reset_event(adapter, vf); | |
5085 | ||
5086 | /* process any messages pending */ | |
5087 | if (!igb_check_for_msg(hw, vf)) | |
5088 | igb_rcv_msg_from_vf(adapter, vf); | |
5089 | ||
5090 | /* process any acks */ | |
5091 | if (!igb_check_for_ack(hw, vf)) | |
5092 | igb_rcv_ack_from_vf(adapter, vf); | |
5093 | } | |
4ae196df AD |
5094 | } |
5095 | ||
68d480c4 AD |
5096 | /** |
5097 | * igb_set_uta - Set unicast filter table address | |
5098 | * @adapter: board private structure | |
5099 | * | |
5100 | * The unicast table address is a register array of 32-bit registers. | |
5101 | * The table is meant to be used in a way similar to how the MTA is used | |
5102 | * however due to certain limitations in the hardware it is necessary to | |
5103 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous | |
5104 | * enable bit to allow vlan tag stripping when promiscous mode is enabled | |
5105 | **/ | |
5106 | static void igb_set_uta(struct igb_adapter *adapter) | |
5107 | { | |
5108 | struct e1000_hw *hw = &adapter->hw; | |
5109 | int i; | |
5110 | ||
5111 | /* The UTA table only exists on 82576 hardware and newer */ | |
5112 | if (hw->mac.type < e1000_82576) | |
5113 | return; | |
5114 | ||
5115 | /* we only need to do this if VMDq is enabled */ | |
5116 | if (!adapter->vfs_allocated_count) | |
5117 | return; | |
5118 | ||
5119 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
5120 | array_wr32(E1000_UTA, i, ~0); | |
5121 | } | |
5122 | ||
9d5c8243 AK |
5123 | /** |
5124 | * igb_intr_msi - Interrupt Handler | |
5125 | * @irq: interrupt number | |
5126 | * @data: pointer to a network interface device structure | |
5127 | **/ | |
5128 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
5129 | { | |
047e0030 AD |
5130 | struct igb_adapter *adapter = data; |
5131 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5132 | struct e1000_hw *hw = &adapter->hw; |
5133 | /* read ICR disables interrupts using IAM */ | |
5134 | u32 icr = rd32(E1000_ICR); | |
5135 | ||
047e0030 | 5136 | igb_write_itr(q_vector); |
9d5c8243 | 5137 | |
7f081d40 AD |
5138 | if (icr & E1000_ICR_DRSTA) |
5139 | schedule_work(&adapter->reset_task); | |
5140 | ||
047e0030 | 5141 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5142 | /* HW is reporting DMA is out of sync */ |
5143 | adapter->stats.doosync++; | |
5144 | } | |
5145 | ||
9d5c8243 AK |
5146 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5147 | hw->mac.get_link_status = 1; | |
5148 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5149 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5150 | } | |
5151 | ||
047e0030 | 5152 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5153 | |
5154 | return IRQ_HANDLED; | |
5155 | } | |
5156 | ||
5157 | /** | |
4a3c6433 | 5158 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
5159 | * @irq: interrupt number |
5160 | * @data: pointer to a network interface device structure | |
5161 | **/ | |
5162 | static irqreturn_t igb_intr(int irq, void *data) | |
5163 | { | |
047e0030 AD |
5164 | struct igb_adapter *adapter = data; |
5165 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5166 | struct e1000_hw *hw = &adapter->hw; |
5167 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
5168 | * need for the IMC write */ | |
5169 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
5170 | if (!icr) |
5171 | return IRQ_NONE; /* Not our interrupt */ | |
5172 | ||
047e0030 | 5173 | igb_write_itr(q_vector); |
9d5c8243 AK |
5174 | |
5175 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
5176 | * not set, then the adapter didn't send an interrupt */ | |
5177 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
5178 | return IRQ_NONE; | |
5179 | ||
7f081d40 AD |
5180 | if (icr & E1000_ICR_DRSTA) |
5181 | schedule_work(&adapter->reset_task); | |
5182 | ||
047e0030 | 5183 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5184 | /* HW is reporting DMA is out of sync */ |
5185 | adapter->stats.doosync++; | |
5186 | } | |
5187 | ||
9d5c8243 AK |
5188 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5189 | hw->mac.get_link_status = 1; | |
5190 | /* guard against interrupt when we're going down */ | |
5191 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5192 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5193 | } | |
5194 | ||
047e0030 | 5195 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5196 | |
5197 | return IRQ_HANDLED; | |
5198 | } | |
5199 | ||
047e0030 | 5200 | static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 5201 | { |
047e0030 | 5202 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 5203 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5204 | |
4fc82adf AD |
5205 | if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) || |
5206 | (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) { | |
047e0030 | 5207 | if (!adapter->msix_entries) |
6eb5a7f1 | 5208 | igb_set_itr(adapter); |
46544258 | 5209 | else |
047e0030 | 5210 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
5211 | } |
5212 | ||
46544258 AD |
5213 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
5214 | if (adapter->msix_entries) | |
047e0030 | 5215 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
5216 | else |
5217 | igb_irq_enable(adapter); | |
5218 | } | |
9d5c8243 AK |
5219 | } |
5220 | ||
46544258 AD |
5221 | /** |
5222 | * igb_poll - NAPI Rx polling callback | |
5223 | * @napi: napi polling structure | |
5224 | * @budget: count of how many packets we should handle | |
5225 | **/ | |
5226 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 5227 | { |
047e0030 AD |
5228 | struct igb_q_vector *q_vector = container_of(napi, |
5229 | struct igb_q_vector, | |
5230 | napi); | |
5231 | int tx_clean_complete = 1, work_done = 0; | |
9d5c8243 | 5232 | |
421e02f0 | 5233 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
5234 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
5235 | igb_update_dca(q_vector); | |
fe4506b6 | 5236 | #endif |
047e0030 AD |
5237 | if (q_vector->tx_ring) |
5238 | tx_clean_complete = igb_clean_tx_irq(q_vector); | |
9d5c8243 | 5239 | |
047e0030 AD |
5240 | if (q_vector->rx_ring) |
5241 | igb_clean_rx_irq_adv(q_vector, &work_done, budget); | |
5242 | ||
5243 | if (!tx_clean_complete) | |
5244 | work_done = budget; | |
46544258 | 5245 | |
9d5c8243 | 5246 | /* If not enough Rx work done, exit the polling mode */ |
5e6d5b17 | 5247 | if (work_done < budget) { |
288379f0 | 5248 | napi_complete(napi); |
047e0030 | 5249 | igb_ring_irq_enable(q_vector); |
9d5c8243 AK |
5250 | } |
5251 | ||
46544258 | 5252 | return work_done; |
9d5c8243 | 5253 | } |
6d8126f9 | 5254 | |
33af6bcc | 5255 | /** |
c5b9bd5e | 5256 | * igb_systim_to_hwtstamp - convert system time value to hw timestamp |
33af6bcc | 5257 | * @adapter: board private structure |
c5b9bd5e AD |
5258 | * @shhwtstamps: timestamp structure to update |
5259 | * @regval: unsigned 64bit system time value. | |
5260 | * | |
5261 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
5262 | * into a hwtstamp which can be used by the upper level timestamping functions | |
5263 | */ | |
5264 | static void igb_systim_to_hwtstamp(struct igb_adapter *adapter, | |
5265 | struct skb_shared_hwtstamps *shhwtstamps, | |
5266 | u64 regval) | |
5267 | { | |
5268 | u64 ns; | |
5269 | ||
55cac248 AD |
5270 | /* |
5271 | * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to | |
5272 | * 24 to match clock shift we setup earlier. | |
5273 | */ | |
5274 | if (adapter->hw.mac.type == e1000_82580) | |
5275 | regval <<= IGB_82580_TSYNC_SHIFT; | |
5276 | ||
c5b9bd5e AD |
5277 | ns = timecounter_cyc2time(&adapter->clock, regval); |
5278 | timecompare_update(&adapter->compare, ns); | |
5279 | memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); | |
5280 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
5281 | shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns); | |
5282 | } | |
5283 | ||
5284 | /** | |
5285 | * igb_tx_hwtstamp - utility function which checks for TX time stamp | |
5286 | * @q_vector: pointer to q_vector containing needed info | |
2873957d | 5287 | * @buffer: pointer to igb_buffer structure |
33af6bcc PO |
5288 | * |
5289 | * If we were asked to do hardware stamping and such a time stamp is | |
5290 | * available, then it must have been for this skb here because we only | |
5291 | * allow only one such packet into the queue. | |
5292 | */ | |
2873957d | 5293 | static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info) |
33af6bcc | 5294 | { |
c5b9bd5e | 5295 | struct igb_adapter *adapter = q_vector->adapter; |
33af6bcc | 5296 | struct e1000_hw *hw = &adapter->hw; |
c5b9bd5e AD |
5297 | struct skb_shared_hwtstamps shhwtstamps; |
5298 | u64 regval; | |
33af6bcc | 5299 | |
c5b9bd5e | 5300 | /* if skb does not support hw timestamp or TX stamp not valid exit */ |
2873957d | 5301 | if (likely(!buffer_info->shtx.hardware) || |
c5b9bd5e AD |
5302 | !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID)) |
5303 | return; | |
5304 | ||
5305 | regval = rd32(E1000_TXSTMPL); | |
5306 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
5307 | ||
5308 | igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval); | |
2873957d | 5309 | skb_tstamp_tx(buffer_info->skb, &shhwtstamps); |
33af6bcc PO |
5310 | } |
5311 | ||
9d5c8243 AK |
5312 | /** |
5313 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
047e0030 | 5314 | * @q_vector: pointer to q_vector containing needed info |
9d5c8243 AK |
5315 | * returns true if ring is completely cleaned |
5316 | **/ | |
047e0030 | 5317 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 5318 | { |
047e0030 AD |
5319 | struct igb_adapter *adapter = q_vector->adapter; |
5320 | struct igb_ring *tx_ring = q_vector->tx_ring; | |
e694e964 | 5321 | struct net_device *netdev = tx_ring->netdev; |
0e014cb1 | 5322 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5323 | struct igb_buffer *buffer_info; |
0e014cb1 | 5324 | union e1000_adv_tx_desc *tx_desc, *eop_desc; |
9d5c8243 | 5325 | unsigned int total_bytes = 0, total_packets = 0; |
0e014cb1 AD |
5326 | unsigned int i, eop, count = 0; |
5327 | bool cleaned = false; | |
9d5c8243 | 5328 | |
9d5c8243 | 5329 | i = tx_ring->next_to_clean; |
0e014cb1 AD |
5330 | eop = tx_ring->buffer_info[i].next_to_watch; |
5331 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
5332 | ||
5333 | while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) && | |
5334 | (count < tx_ring->count)) { | |
5335 | for (cleaned = false; !cleaned; count++) { | |
5336 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
9d5c8243 | 5337 | buffer_info = &tx_ring->buffer_info[i]; |
0e014cb1 | 5338 | cleaned = (i == eop); |
9d5c8243 | 5339 | |
2873957d NN |
5340 | if (buffer_info->skb) { |
5341 | total_bytes += buffer_info->bytecount; | |
9d5c8243 | 5342 | /* gso_segs is currently only valid for tcp */ |
2873957d NN |
5343 | total_packets += buffer_info->gso_segs; |
5344 | igb_tx_hwtstamp(q_vector, buffer_info); | |
9d5c8243 AK |
5345 | } |
5346 | ||
80785298 | 5347 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
0e014cb1 | 5348 | tx_desc->wb.status = 0; |
9d5c8243 AK |
5349 | |
5350 | i++; | |
5351 | if (i == tx_ring->count) | |
5352 | i = 0; | |
9d5c8243 | 5353 | } |
0e014cb1 AD |
5354 | eop = tx_ring->buffer_info[i].next_to_watch; |
5355 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
5356 | } | |
5357 | ||
9d5c8243 AK |
5358 | tx_ring->next_to_clean = i; |
5359 | ||
fc7d345d | 5360 | if (unlikely(count && |
9d5c8243 | 5361 | netif_carrier_ok(netdev) && |
c493ea45 | 5362 | igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { |
9d5c8243 AK |
5363 | /* Make sure that anybody stopping the queue after this |
5364 | * sees the new next_to_clean. | |
5365 | */ | |
5366 | smp_mb(); | |
661086df PWJ |
5367 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
5368 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
5369 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
04a5fcaa | 5370 | tx_ring->tx_stats.restart_queue++; |
661086df | 5371 | } |
9d5c8243 AK |
5372 | } |
5373 | ||
5374 | if (tx_ring->detect_tx_hung) { | |
5375 | /* Detect a transmit hang in hardware, this serializes the | |
5376 | * check with the clearing of time_stamp and movement of i */ | |
5377 | tx_ring->detect_tx_hung = false; | |
5378 | if (tx_ring->buffer_info[i].time_stamp && | |
5379 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | |
8e95a202 JP |
5380 | (adapter->tx_timeout_factor * HZ)) && |
5381 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { | |
9d5c8243 | 5382 | |
9d5c8243 | 5383 | /* detected Tx unit hang */ |
59d71989 | 5384 | dev_err(tx_ring->dev, |
9d5c8243 | 5385 | "Detected Tx Unit Hang\n" |
2d064c06 | 5386 | " Tx Queue <%d>\n" |
9d5c8243 AK |
5387 | " TDH <%x>\n" |
5388 | " TDT <%x>\n" | |
5389 | " next_to_use <%x>\n" | |
5390 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
5391 | "buffer_info[next_to_clean]\n" |
5392 | " time_stamp <%lx>\n" | |
0e014cb1 | 5393 | " next_to_watch <%x>\n" |
9d5c8243 AK |
5394 | " jiffies <%lx>\n" |
5395 | " desc.status <%x>\n", | |
2d064c06 | 5396 | tx_ring->queue_index, |
fce99e34 AD |
5397 | readl(tx_ring->head), |
5398 | readl(tx_ring->tail), | |
9d5c8243 AK |
5399 | tx_ring->next_to_use, |
5400 | tx_ring->next_to_clean, | |
f7ba205e | 5401 | tx_ring->buffer_info[eop].time_stamp, |
0e014cb1 | 5402 | eop, |
9d5c8243 | 5403 | jiffies, |
0e014cb1 | 5404 | eop_desc->wb.status); |
661086df | 5405 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
5406 | } |
5407 | } | |
5408 | tx_ring->total_bytes += total_bytes; | |
5409 | tx_ring->total_packets += total_packets; | |
e21ed353 AD |
5410 | tx_ring->tx_stats.bytes += total_bytes; |
5411 | tx_ring->tx_stats.packets += total_packets; | |
0e014cb1 | 5412 | return (count < tx_ring->count); |
9d5c8243 AK |
5413 | } |
5414 | ||
9d5c8243 AK |
5415 | /** |
5416 | * igb_receive_skb - helper function to handle rx indications | |
047e0030 AD |
5417 | * @q_vector: structure containing interrupt and ring information |
5418 | * @skb: packet to send up | |
5419 | * @vlan_tag: vlan tag for packet | |
9d5c8243 | 5420 | **/ |
047e0030 AD |
5421 | static void igb_receive_skb(struct igb_q_vector *q_vector, |
5422 | struct sk_buff *skb, | |
5423 | u16 vlan_tag) | |
5424 | { | |
5425 | struct igb_adapter *adapter = q_vector->adapter; | |
5426 | ||
31b24b95 | 5427 | if (vlan_tag && adapter->vlgrp) |
047e0030 AD |
5428 | vlan_gro_receive(&q_vector->napi, adapter->vlgrp, |
5429 | vlan_tag, skb); | |
182ff8df | 5430 | else |
047e0030 | 5431 | napi_gro_receive(&q_vector->napi, skb); |
9d5c8243 AK |
5432 | } |
5433 | ||
04a5fcaa | 5434 | static inline void igb_rx_checksum_adv(struct igb_ring *ring, |
9d5c8243 AK |
5435 | u32 status_err, struct sk_buff *skb) |
5436 | { | |
5437 | skb->ip_summed = CHECKSUM_NONE; | |
5438 | ||
5439 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
85ad76b2 AD |
5440 | if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) || |
5441 | (status_err & E1000_RXD_STAT_IXSM)) | |
9d5c8243 | 5442 | return; |
85ad76b2 | 5443 | |
9d5c8243 AK |
5444 | /* TCP/UDP checksum error bit is set */ |
5445 | if (status_err & | |
5446 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
b9473560 JB |
5447 | /* |
5448 | * work around errata with sctp packets where the TCPE aka | |
5449 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) | |
5450 | * packets, (aka let the stack check the crc32c) | |
5451 | */ | |
85ad76b2 AD |
5452 | if ((skb->len == 60) && |
5453 | (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) | |
04a5fcaa | 5454 | ring->rx_stats.csum_err++; |
85ad76b2 | 5455 | |
9d5c8243 | 5456 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
5457 | return; |
5458 | } | |
5459 | /* It must be a TCP or UDP packet with a valid checksum */ | |
5460 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
5461 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5462 | ||
59d71989 | 5463 | dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err); |
9d5c8243 AK |
5464 | } |
5465 | ||
757b77e2 | 5466 | static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr, |
c5b9bd5e AD |
5467 | struct sk_buff *skb) |
5468 | { | |
5469 | struct igb_adapter *adapter = q_vector->adapter; | |
5470 | struct e1000_hw *hw = &adapter->hw; | |
5471 | u64 regval; | |
5472 | ||
5473 | /* | |
5474 | * If this bit is set, then the RX registers contain the time stamp. No | |
5475 | * other packet will be time stamped until we read these registers, so | |
5476 | * read the registers to make them available again. Because only one | |
5477 | * packet can be time stamped at a time, we know that the register | |
5478 | * values must belong to this one here and therefore we don't need to | |
5479 | * compare any of the additional attributes stored for it. | |
5480 | * | |
5481 | * If nothing went wrong, then it should have a skb_shared_tx that we | |
5482 | * can turn into a skb_shared_hwtstamps. | |
5483 | */ | |
757b77e2 NN |
5484 | if (staterr & E1000_RXDADV_STAT_TSIP) { |
5485 | u32 *stamp = (u32 *)skb->data; | |
5486 | regval = le32_to_cpu(*(stamp + 2)); | |
5487 | regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32; | |
5488 | skb_pull(skb, IGB_TS_HDR_LEN); | |
5489 | } else { | |
5490 | if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) | |
5491 | return; | |
c5b9bd5e | 5492 | |
757b77e2 NN |
5493 | regval = rd32(E1000_RXSTMPL); |
5494 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
5495 | } | |
c5b9bd5e AD |
5496 | |
5497 | igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
5498 | } | |
4c844851 | 5499 | static inline u16 igb_get_hlen(struct igb_ring *rx_ring, |
2d94d8ab AD |
5500 | union e1000_adv_rx_desc *rx_desc) |
5501 | { | |
5502 | /* HW will not DMA in data larger than the given buffer, even if it | |
5503 | * parses the (NFS, of course) header to be larger. In that case, it | |
5504 | * fills the header buffer and spills the rest into the page. | |
5505 | */ | |
5506 | u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | |
5507 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
4c844851 AD |
5508 | if (hlen > rx_ring->rx_buffer_len) |
5509 | hlen = rx_ring->rx_buffer_len; | |
2d94d8ab AD |
5510 | return hlen; |
5511 | } | |
5512 | ||
047e0030 AD |
5513 | static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector, |
5514 | int *work_done, int budget) | |
9d5c8243 | 5515 | { |
047e0030 | 5516 | struct igb_ring *rx_ring = q_vector->rx_ring; |
e694e964 | 5517 | struct net_device *netdev = rx_ring->netdev; |
59d71989 | 5518 | struct device *dev = rx_ring->dev; |
9d5c8243 AK |
5519 | union e1000_adv_rx_desc *rx_desc , *next_rxd; |
5520 | struct igb_buffer *buffer_info , *next_buffer; | |
5521 | struct sk_buff *skb; | |
9d5c8243 AK |
5522 | bool cleaned = false; |
5523 | int cleaned_count = 0; | |
d1eff350 | 5524 | int current_node = numa_node_id(); |
9d5c8243 | 5525 | unsigned int total_bytes = 0, total_packets = 0; |
73cd78f1 | 5526 | unsigned int i; |
2d94d8ab AD |
5527 | u32 staterr; |
5528 | u16 length; | |
047e0030 | 5529 | u16 vlan_tag; |
9d5c8243 AK |
5530 | |
5531 | i = rx_ring->next_to_clean; | |
69d3ca53 | 5532 | buffer_info = &rx_ring->buffer_info[i]; |
9d5c8243 AK |
5533 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); |
5534 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
5535 | ||
5536 | while (staterr & E1000_RXD_STAT_DD) { | |
5537 | if (*work_done >= budget) | |
5538 | break; | |
5539 | (*work_done)++; | |
9d5c8243 | 5540 | |
69d3ca53 AD |
5541 | skb = buffer_info->skb; |
5542 | prefetch(skb->data - NET_IP_ALIGN); | |
5543 | buffer_info->skb = NULL; | |
5544 | ||
5545 | i++; | |
5546 | if (i == rx_ring->count) | |
5547 | i = 0; | |
42d0781a | 5548 | |
69d3ca53 AD |
5549 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); |
5550 | prefetch(next_rxd); | |
5551 | next_buffer = &rx_ring->buffer_info[i]; | |
9d5c8243 AK |
5552 | |
5553 | length = le16_to_cpu(rx_desc->wb.upper.length); | |
5554 | cleaned = true; | |
5555 | cleaned_count++; | |
5556 | ||
2d94d8ab | 5557 | if (buffer_info->dma) { |
59d71989 | 5558 | dma_unmap_single(dev, buffer_info->dma, |
4c844851 | 5559 | rx_ring->rx_buffer_len, |
59d71989 | 5560 | DMA_FROM_DEVICE); |
91615f76 | 5561 | buffer_info->dma = 0; |
4c844851 | 5562 | if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) { |
6ec43fe6 AD |
5563 | skb_put(skb, length); |
5564 | goto send_up; | |
5565 | } | |
4c844851 | 5566 | skb_put(skb, igb_get_hlen(rx_ring, rx_desc)); |
bf36c1a0 AD |
5567 | } |
5568 | ||
5569 | if (length) { | |
59d71989 AD |
5570 | dma_unmap_page(dev, buffer_info->page_dma, |
5571 | PAGE_SIZE / 2, DMA_FROM_DEVICE); | |
9d5c8243 | 5572 | buffer_info->page_dma = 0; |
bf36c1a0 | 5573 | |
aa913403 | 5574 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, |
bf36c1a0 AD |
5575 | buffer_info->page, |
5576 | buffer_info->page_offset, | |
5577 | length); | |
5578 | ||
d1eff350 AD |
5579 | if ((page_count(buffer_info->page) != 1) || |
5580 | (page_to_nid(buffer_info->page) != current_node)) | |
bf36c1a0 AD |
5581 | buffer_info->page = NULL; |
5582 | else | |
5583 | get_page(buffer_info->page); | |
9d5c8243 AK |
5584 | |
5585 | skb->len += length; | |
5586 | skb->data_len += length; | |
bf36c1a0 | 5587 | skb->truesize += length; |
9d5c8243 | 5588 | } |
9d5c8243 | 5589 | |
bf36c1a0 | 5590 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
b2d56536 AD |
5591 | buffer_info->skb = next_buffer->skb; |
5592 | buffer_info->dma = next_buffer->dma; | |
5593 | next_buffer->skb = skb; | |
5594 | next_buffer->dma = 0; | |
bf36c1a0 AD |
5595 | goto next_desc; |
5596 | } | |
69d3ca53 | 5597 | send_up: |
9d5c8243 AK |
5598 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
5599 | dev_kfree_skb_irq(skb); | |
5600 | goto next_desc; | |
5601 | } | |
9d5c8243 | 5602 | |
757b77e2 NN |
5603 | if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS)) |
5604 | igb_rx_hwtstamp(q_vector, staterr, skb); | |
9d5c8243 AK |
5605 | total_bytes += skb->len; |
5606 | total_packets++; | |
5607 | ||
85ad76b2 | 5608 | igb_rx_checksum_adv(rx_ring, staterr, skb); |
9d5c8243 AK |
5609 | |
5610 | skb->protocol = eth_type_trans(skb, netdev); | |
047e0030 AD |
5611 | skb_record_rx_queue(skb, rx_ring->queue_index); |
5612 | ||
5613 | vlan_tag = ((staterr & E1000_RXD_STAT_VP) ? | |
5614 | le16_to_cpu(rx_desc->wb.upper.vlan) : 0); | |
9d5c8243 | 5615 | |
047e0030 | 5616 | igb_receive_skb(q_vector, skb, vlan_tag); |
9d5c8243 | 5617 | |
9d5c8243 AK |
5618 | next_desc: |
5619 | rx_desc->wb.upper.status_error = 0; | |
5620 | ||
5621 | /* return some buffers to hardware, one at a time is too slow */ | |
5622 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
3b644cf6 | 5623 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
5624 | cleaned_count = 0; |
5625 | } | |
5626 | ||
5627 | /* use prefetched values */ | |
5628 | rx_desc = next_rxd; | |
5629 | buffer_info = next_buffer; | |
9d5c8243 AK |
5630 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
5631 | } | |
bf36c1a0 | 5632 | |
9d5c8243 | 5633 | rx_ring->next_to_clean = i; |
c493ea45 | 5634 | cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 AK |
5635 | |
5636 | if (cleaned_count) | |
3b644cf6 | 5637 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
5638 | |
5639 | rx_ring->total_packets += total_packets; | |
5640 | rx_ring->total_bytes += total_bytes; | |
5641 | rx_ring->rx_stats.packets += total_packets; | |
5642 | rx_ring->rx_stats.bytes += total_bytes; | |
9d5c8243 AK |
5643 | return cleaned; |
5644 | } | |
5645 | ||
9d5c8243 AK |
5646 | /** |
5647 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | |
5648 | * @adapter: address of board private structure | |
5649 | **/ | |
d7ee5b3a | 5650 | void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count) |
9d5c8243 | 5651 | { |
e694e964 | 5652 | struct net_device *netdev = rx_ring->netdev; |
9d5c8243 AK |
5653 | union e1000_adv_rx_desc *rx_desc; |
5654 | struct igb_buffer *buffer_info; | |
5655 | struct sk_buff *skb; | |
5656 | unsigned int i; | |
db761762 | 5657 | int bufsz; |
9d5c8243 AK |
5658 | |
5659 | i = rx_ring->next_to_use; | |
5660 | buffer_info = &rx_ring->buffer_info[i]; | |
5661 | ||
4c844851 | 5662 | bufsz = rx_ring->rx_buffer_len; |
db761762 | 5663 | |
9d5c8243 AK |
5664 | while (cleaned_count--) { |
5665 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
5666 | ||
6ec43fe6 | 5667 | if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) { |
9d5c8243 | 5668 | if (!buffer_info->page) { |
42d0781a | 5669 | buffer_info->page = netdev_alloc_page(netdev); |
bf36c1a0 | 5670 | if (!buffer_info->page) { |
04a5fcaa | 5671 | rx_ring->rx_stats.alloc_failed++; |
bf36c1a0 AD |
5672 | goto no_buffers; |
5673 | } | |
5674 | buffer_info->page_offset = 0; | |
5675 | } else { | |
5676 | buffer_info->page_offset ^= PAGE_SIZE / 2; | |
9d5c8243 AK |
5677 | } |
5678 | buffer_info->page_dma = | |
59d71989 | 5679 | dma_map_page(rx_ring->dev, buffer_info->page, |
bf36c1a0 AD |
5680 | buffer_info->page_offset, |
5681 | PAGE_SIZE / 2, | |
59d71989 AD |
5682 | DMA_FROM_DEVICE); |
5683 | if (dma_mapping_error(rx_ring->dev, | |
5684 | buffer_info->page_dma)) { | |
42d0781a AD |
5685 | buffer_info->page_dma = 0; |
5686 | rx_ring->rx_stats.alloc_failed++; | |
5687 | goto no_buffers; | |
5688 | } | |
9d5c8243 AK |
5689 | } |
5690 | ||
42d0781a AD |
5691 | skb = buffer_info->skb; |
5692 | if (!skb) { | |
89d71a66 | 5693 | skb = netdev_alloc_skb_ip_align(netdev, bufsz); |
9d5c8243 | 5694 | if (!skb) { |
04a5fcaa | 5695 | rx_ring->rx_stats.alloc_failed++; |
9d5c8243 AK |
5696 | goto no_buffers; |
5697 | } | |
5698 | ||
9d5c8243 | 5699 | buffer_info->skb = skb; |
42d0781a AD |
5700 | } |
5701 | if (!buffer_info->dma) { | |
59d71989 | 5702 | buffer_info->dma = dma_map_single(rx_ring->dev, |
80785298 | 5703 | skb->data, |
9d5c8243 | 5704 | bufsz, |
59d71989 AD |
5705 | DMA_FROM_DEVICE); |
5706 | if (dma_mapping_error(rx_ring->dev, | |
5707 | buffer_info->dma)) { | |
42d0781a AD |
5708 | buffer_info->dma = 0; |
5709 | rx_ring->rx_stats.alloc_failed++; | |
5710 | goto no_buffers; | |
5711 | } | |
9d5c8243 AK |
5712 | } |
5713 | /* Refresh the desc even if buffer_addrs didn't change because | |
5714 | * each write-back erases this info. */ | |
6ec43fe6 | 5715 | if (bufsz < IGB_RXBUFFER_1024) { |
9d5c8243 AK |
5716 | rx_desc->read.pkt_addr = |
5717 | cpu_to_le64(buffer_info->page_dma); | |
5718 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | |
5719 | } else { | |
42d0781a | 5720 | rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma); |
9d5c8243 AK |
5721 | rx_desc->read.hdr_addr = 0; |
5722 | } | |
5723 | ||
5724 | i++; | |
5725 | if (i == rx_ring->count) | |
5726 | i = 0; | |
5727 | buffer_info = &rx_ring->buffer_info[i]; | |
5728 | } | |
5729 | ||
5730 | no_buffers: | |
5731 | if (rx_ring->next_to_use != i) { | |
5732 | rx_ring->next_to_use = i; | |
5733 | if (i == 0) | |
5734 | i = (rx_ring->count - 1); | |
5735 | else | |
5736 | i--; | |
5737 | ||
5738 | /* Force memory writes to complete before letting h/w | |
5739 | * know there are new descriptors to fetch. (Only | |
5740 | * applicable for weak-ordered memory model archs, | |
5741 | * such as IA-64). */ | |
5742 | wmb(); | |
fce99e34 | 5743 | writel(i, rx_ring->tail); |
9d5c8243 AK |
5744 | } |
5745 | } | |
5746 | ||
5747 | /** | |
5748 | * igb_mii_ioctl - | |
5749 | * @netdev: | |
5750 | * @ifreq: | |
5751 | * @cmd: | |
5752 | **/ | |
5753 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
5754 | { | |
5755 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5756 | struct mii_ioctl_data *data = if_mii(ifr); | |
5757 | ||
5758 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
5759 | return -EOPNOTSUPP; | |
5760 | ||
5761 | switch (cmd) { | |
5762 | case SIOCGMIIPHY: | |
5763 | data->phy_id = adapter->hw.phy.addr; | |
5764 | break; | |
5765 | case SIOCGMIIREG: | |
f5f4cf08 AD |
5766 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
5767 | &data->val_out)) | |
9d5c8243 AK |
5768 | return -EIO; |
5769 | break; | |
5770 | case SIOCSMIIREG: | |
5771 | default: | |
5772 | return -EOPNOTSUPP; | |
5773 | } | |
5774 | return 0; | |
5775 | } | |
5776 | ||
c6cb090b PO |
5777 | /** |
5778 | * igb_hwtstamp_ioctl - control hardware time stamping | |
5779 | * @netdev: | |
5780 | * @ifreq: | |
5781 | * @cmd: | |
5782 | * | |
33af6bcc PO |
5783 | * Outgoing time stamping can be enabled and disabled. Play nice and |
5784 | * disable it when requested, although it shouldn't case any overhead | |
5785 | * when no packet needs it. At most one packet in the queue may be | |
5786 | * marked for time stamping, otherwise it would be impossible to tell | |
5787 | * for sure to which packet the hardware time stamp belongs. | |
5788 | * | |
5789 | * Incoming time stamping has to be configured via the hardware | |
5790 | * filters. Not all combinations are supported, in particular event | |
5791 | * type has to be specified. Matching the kind of event packet is | |
5792 | * not supported, with the exception of "all V2 events regardless of | |
5793 | * level 2 or 4". | |
5794 | * | |
c6cb090b PO |
5795 | **/ |
5796 | static int igb_hwtstamp_ioctl(struct net_device *netdev, | |
5797 | struct ifreq *ifr, int cmd) | |
5798 | { | |
33af6bcc PO |
5799 | struct igb_adapter *adapter = netdev_priv(netdev); |
5800 | struct e1000_hw *hw = &adapter->hw; | |
c6cb090b | 5801 | struct hwtstamp_config config; |
c5b9bd5e AD |
5802 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
5803 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
33af6bcc | 5804 | u32 tsync_rx_cfg = 0; |
c5b9bd5e AD |
5805 | bool is_l4 = false; |
5806 | bool is_l2 = false; | |
33af6bcc | 5807 | u32 regval; |
c6cb090b PO |
5808 | |
5809 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
5810 | return -EFAULT; | |
5811 | ||
5812 | /* reserved for future extensions */ | |
5813 | if (config.flags) | |
5814 | return -EINVAL; | |
5815 | ||
33af6bcc PO |
5816 | switch (config.tx_type) { |
5817 | case HWTSTAMP_TX_OFF: | |
c5b9bd5e | 5818 | tsync_tx_ctl = 0; |
33af6bcc | 5819 | case HWTSTAMP_TX_ON: |
33af6bcc PO |
5820 | break; |
5821 | default: | |
5822 | return -ERANGE; | |
5823 | } | |
5824 | ||
5825 | switch (config.rx_filter) { | |
5826 | case HWTSTAMP_FILTER_NONE: | |
c5b9bd5e | 5827 | tsync_rx_ctl = 0; |
33af6bcc PO |
5828 | break; |
5829 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
5830 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
5831 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
5832 | case HWTSTAMP_FILTER_ALL: | |
5833 | /* | |
5834 | * register TSYNCRXCFG must be set, therefore it is not | |
5835 | * possible to time stamp both Sync and Delay_Req messages | |
5836 | * => fall back to time stamping all packets | |
5837 | */ | |
c5b9bd5e | 5838 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
33af6bcc PO |
5839 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
5840 | break; | |
5841 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
c5b9bd5e | 5842 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
33af6bcc | 5843 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; |
c5b9bd5e | 5844 | is_l4 = true; |
33af6bcc PO |
5845 | break; |
5846 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
c5b9bd5e | 5847 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
33af6bcc | 5848 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; |
c5b9bd5e | 5849 | is_l4 = true; |
33af6bcc PO |
5850 | break; |
5851 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
5852 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
c5b9bd5e | 5853 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
33af6bcc | 5854 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; |
c5b9bd5e AD |
5855 | is_l2 = true; |
5856 | is_l4 = true; | |
33af6bcc PO |
5857 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
5858 | break; | |
5859 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
5860 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
c5b9bd5e | 5861 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
33af6bcc | 5862 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; |
c5b9bd5e AD |
5863 | is_l2 = true; |
5864 | is_l4 = true; | |
33af6bcc PO |
5865 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
5866 | break; | |
5867 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
5868 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
5869 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
c5b9bd5e | 5870 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
33af6bcc | 5871 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
c5b9bd5e | 5872 | is_l2 = true; |
33af6bcc PO |
5873 | break; |
5874 | default: | |
5875 | return -ERANGE; | |
5876 | } | |
5877 | ||
c5b9bd5e AD |
5878 | if (hw->mac.type == e1000_82575) { |
5879 | if (tsync_rx_ctl | tsync_tx_ctl) | |
5880 | return -EINVAL; | |
5881 | return 0; | |
5882 | } | |
5883 | ||
757b77e2 NN |
5884 | /* |
5885 | * Per-packet timestamping only works if all packets are | |
5886 | * timestamped, so enable timestamping in all packets as | |
5887 | * long as one rx filter was configured. | |
5888 | */ | |
5889 | if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) { | |
5890 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
5891 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
5892 | } | |
5893 | ||
33af6bcc PO |
5894 | /* enable/disable TX */ |
5895 | regval = rd32(E1000_TSYNCTXCTL); | |
c5b9bd5e AD |
5896 | regval &= ~E1000_TSYNCTXCTL_ENABLED; |
5897 | regval |= tsync_tx_ctl; | |
33af6bcc PO |
5898 | wr32(E1000_TSYNCTXCTL, regval); |
5899 | ||
c5b9bd5e | 5900 | /* enable/disable RX */ |
33af6bcc | 5901 | regval = rd32(E1000_TSYNCRXCTL); |
c5b9bd5e AD |
5902 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); |
5903 | regval |= tsync_rx_ctl; | |
33af6bcc | 5904 | wr32(E1000_TSYNCRXCTL, regval); |
33af6bcc | 5905 | |
c5b9bd5e AD |
5906 | /* define which PTP packets are time stamped */ |
5907 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
33af6bcc | 5908 | |
c5b9bd5e AD |
5909 | /* define ethertype filter for timestamped packets */ |
5910 | if (is_l2) | |
5911 | wr32(E1000_ETQF(3), | |
5912 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
5913 | E1000_ETQF_1588 | /* enable timestamping */ | |
5914 | ETH_P_1588)); /* 1588 eth protocol type */ | |
5915 | else | |
5916 | wr32(E1000_ETQF(3), 0); | |
5917 | ||
5918 | #define PTP_PORT 319 | |
5919 | /* L4 Queue Filter[3]: filter by destination port and protocol */ | |
5920 | if (is_l4) { | |
5921 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
5922 | | E1000_FTQF_VF_BP /* VF not compared */ | |
5923 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
5924 | | E1000_FTQF_MASK); /* mask all inputs */ | |
5925 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
5926 | ||
5927 | wr32(E1000_IMIR(3), htons(PTP_PORT)); | |
5928 | wr32(E1000_IMIREXT(3), | |
5929 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
5930 | if (hw->mac.type == e1000_82576) { | |
5931 | /* enable source port check */ | |
5932 | wr32(E1000_SPQF(3), htons(PTP_PORT)); | |
5933 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; | |
5934 | } | |
5935 | wr32(E1000_FTQF(3), ftqf); | |
5936 | } else { | |
5937 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
5938 | } | |
33af6bcc PO |
5939 | wrfl(); |
5940 | ||
5941 | adapter->hwtstamp_config = config; | |
5942 | ||
5943 | /* clear TX/RX time stamp registers, just to be sure */ | |
5944 | regval = rd32(E1000_TXSTMPH); | |
5945 | regval = rd32(E1000_RXSTMPH); | |
c6cb090b | 5946 | |
33af6bcc PO |
5947 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
5948 | -EFAULT : 0; | |
c6cb090b PO |
5949 | } |
5950 | ||
9d5c8243 AK |
5951 | /** |
5952 | * igb_ioctl - | |
5953 | * @netdev: | |
5954 | * @ifreq: | |
5955 | * @cmd: | |
5956 | **/ | |
5957 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
5958 | { | |
5959 | switch (cmd) { | |
5960 | case SIOCGMIIPHY: | |
5961 | case SIOCGMIIREG: | |
5962 | case SIOCSMIIREG: | |
5963 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b PO |
5964 | case SIOCSHWTSTAMP: |
5965 | return igb_hwtstamp_ioctl(netdev, ifr, cmd); | |
9d5c8243 AK |
5966 | default: |
5967 | return -EOPNOTSUPP; | |
5968 | } | |
5969 | } | |
5970 | ||
009bc06e AD |
5971 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
5972 | { | |
5973 | struct igb_adapter *adapter = hw->back; | |
5974 | u16 cap_offset; | |
5975 | ||
5976 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | |
5977 | if (!cap_offset) | |
5978 | return -E1000_ERR_CONFIG; | |
5979 | ||
5980 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); | |
5981 | ||
5982 | return 0; | |
5983 | } | |
5984 | ||
5985 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
5986 | { | |
5987 | struct igb_adapter *adapter = hw->back; | |
5988 | u16 cap_offset; | |
5989 | ||
5990 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | |
5991 | if (!cap_offset) | |
5992 | return -E1000_ERR_CONFIG; | |
5993 | ||
5994 | pci_write_config_word(adapter->pdev, cap_offset + reg, *value); | |
5995 | ||
5996 | return 0; | |
5997 | } | |
5998 | ||
9d5c8243 AK |
5999 | static void igb_vlan_rx_register(struct net_device *netdev, |
6000 | struct vlan_group *grp) | |
6001 | { | |
6002 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6003 | struct e1000_hw *hw = &adapter->hw; | |
6004 | u32 ctrl, rctl; | |
6005 | ||
6006 | igb_irq_disable(adapter); | |
6007 | adapter->vlgrp = grp; | |
6008 | ||
6009 | if (grp) { | |
6010 | /* enable VLAN tag insert/strip */ | |
6011 | ctrl = rd32(E1000_CTRL); | |
6012 | ctrl |= E1000_CTRL_VME; | |
6013 | wr32(E1000_CTRL, ctrl); | |
6014 | ||
51466239 | 6015 | /* Disable CFI check */ |
9d5c8243 | 6016 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
6017 | rctl &= ~E1000_RCTL_CFIEN; |
6018 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
6019 | } else { |
6020 | /* disable VLAN tag insert/strip */ | |
6021 | ctrl = rd32(E1000_CTRL); | |
6022 | ctrl &= ~E1000_CTRL_VME; | |
6023 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
6024 | } |
6025 | ||
e1739522 AD |
6026 | igb_rlpml_set(adapter); |
6027 | ||
9d5c8243 AK |
6028 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
6029 | igb_irq_enable(adapter); | |
6030 | } | |
6031 | ||
6032 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
6033 | { | |
6034 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6035 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6036 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 6037 | |
51466239 AD |
6038 | /* attempt to add filter to vlvf array */ |
6039 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 6040 | |
51466239 AD |
6041 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
6042 | igb_vfta_set(hw, vid, true); | |
9d5c8243 AK |
6043 | } |
6044 | ||
6045 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
6046 | { | |
6047 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6048 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6049 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 6050 | s32 err; |
9d5c8243 AK |
6051 | |
6052 | igb_irq_disable(adapter); | |
6053 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
6054 | ||
6055 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
6056 | igb_irq_enable(adapter); | |
6057 | ||
51466239 AD |
6058 | /* remove vlan from VLVF table array */ |
6059 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 6060 | |
51466239 AD |
6061 | /* if vid was not present in VLVF just remove it from table */ |
6062 | if (err) | |
4ae196df | 6063 | igb_vfta_set(hw, vid, false); |
9d5c8243 AK |
6064 | } |
6065 | ||
6066 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
6067 | { | |
6068 | igb_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
6069 | ||
6070 | if (adapter->vlgrp) { | |
6071 | u16 vid; | |
6072 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
6073 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
6074 | continue; | |
6075 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
6076 | } | |
6077 | } | |
6078 | } | |
6079 | ||
6080 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |
6081 | { | |
090b1795 | 6082 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
6083 | struct e1000_mac_info *mac = &adapter->hw.mac; |
6084 | ||
6085 | mac->autoneg = 0; | |
6086 | ||
9d5c8243 AK |
6087 | switch (spddplx) { |
6088 | case SPEED_10 + DUPLEX_HALF: | |
6089 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
6090 | break; | |
6091 | case SPEED_10 + DUPLEX_FULL: | |
6092 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
6093 | break; | |
6094 | case SPEED_100 + DUPLEX_HALF: | |
6095 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
6096 | break; | |
6097 | case SPEED_100 + DUPLEX_FULL: | |
6098 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
6099 | break; | |
6100 | case SPEED_1000 + DUPLEX_FULL: | |
6101 | mac->autoneg = 1; | |
6102 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
6103 | break; | |
6104 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
6105 | default: | |
090b1795 | 6106 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); |
9d5c8243 AK |
6107 | return -EINVAL; |
6108 | } | |
6109 | return 0; | |
6110 | } | |
6111 | ||
3fe7c4c9 | 6112 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake) |
9d5c8243 AK |
6113 | { |
6114 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6115 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6116 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 6117 | u32 ctrl, rctl, status; |
9d5c8243 AK |
6118 | u32 wufc = adapter->wol; |
6119 | #ifdef CONFIG_PM | |
6120 | int retval = 0; | |
6121 | #endif | |
6122 | ||
6123 | netif_device_detach(netdev); | |
6124 | ||
a88f10ec AD |
6125 | if (netif_running(netdev)) |
6126 | igb_close(netdev); | |
6127 | ||
047e0030 | 6128 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
6129 | |
6130 | #ifdef CONFIG_PM | |
6131 | retval = pci_save_state(pdev); | |
6132 | if (retval) | |
6133 | return retval; | |
6134 | #endif | |
6135 | ||
6136 | status = rd32(E1000_STATUS); | |
6137 | if (status & E1000_STATUS_LU) | |
6138 | wufc &= ~E1000_WUFC_LNKC; | |
6139 | ||
6140 | if (wufc) { | |
6141 | igb_setup_rctl(adapter); | |
ff41f8dc | 6142 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
6143 | |
6144 | /* turn on all-multi mode if wake on multicast is enabled */ | |
6145 | if (wufc & E1000_WUFC_MC) { | |
6146 | rctl = rd32(E1000_RCTL); | |
6147 | rctl |= E1000_RCTL_MPE; | |
6148 | wr32(E1000_RCTL, rctl); | |
6149 | } | |
6150 | ||
6151 | ctrl = rd32(E1000_CTRL); | |
6152 | /* advertise wake from D3Cold */ | |
6153 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
6154 | /* phy power management enable */ | |
6155 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
6156 | ctrl |= E1000_CTRL_ADVD3WUC; | |
6157 | wr32(E1000_CTRL, ctrl); | |
6158 | ||
9d5c8243 | 6159 | /* Allow time for pending master requests to run */ |
330a6d6a | 6160 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
6161 | |
6162 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
6163 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
6164 | } else { |
6165 | wr32(E1000_WUC, 0); | |
6166 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
6167 | } |
6168 | ||
3fe7c4c9 RW |
6169 | *enable_wake = wufc || adapter->en_mng_pt; |
6170 | if (!*enable_wake) | |
88a268c1 NN |
6171 | igb_power_down_link(adapter); |
6172 | else | |
6173 | igb_power_up_link(adapter); | |
9d5c8243 AK |
6174 | |
6175 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
6176 | * would have already happened in close and is redundant. */ | |
6177 | igb_release_hw_control(adapter); | |
6178 | ||
6179 | pci_disable_device(pdev); | |
6180 | ||
9d5c8243 AK |
6181 | return 0; |
6182 | } | |
6183 | ||
6184 | #ifdef CONFIG_PM | |
3fe7c4c9 RW |
6185 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) |
6186 | { | |
6187 | int retval; | |
6188 | bool wake; | |
6189 | ||
6190 | retval = __igb_shutdown(pdev, &wake); | |
6191 | if (retval) | |
6192 | return retval; | |
6193 | ||
6194 | if (wake) { | |
6195 | pci_prepare_to_sleep(pdev); | |
6196 | } else { | |
6197 | pci_wake_from_d3(pdev, false); | |
6198 | pci_set_power_state(pdev, PCI_D3hot); | |
6199 | } | |
6200 | ||
6201 | return 0; | |
6202 | } | |
6203 | ||
9d5c8243 AK |
6204 | static int igb_resume(struct pci_dev *pdev) |
6205 | { | |
6206 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6207 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6208 | struct e1000_hw *hw = &adapter->hw; | |
6209 | u32 err; | |
6210 | ||
6211 | pci_set_power_state(pdev, PCI_D0); | |
6212 | pci_restore_state(pdev); | |
b94f2d77 | 6213 | pci_save_state(pdev); |
42bfd33a | 6214 | |
aed5dec3 | 6215 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
6216 | if (err) { |
6217 | dev_err(&pdev->dev, | |
6218 | "igb: Cannot enable PCI device from suspend\n"); | |
6219 | return err; | |
6220 | } | |
6221 | pci_set_master(pdev); | |
6222 | ||
6223 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
6224 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
6225 | ||
047e0030 | 6226 | if (igb_init_interrupt_scheme(adapter)) { |
a88f10ec AD |
6227 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
6228 | return -ENOMEM; | |
9d5c8243 AK |
6229 | } |
6230 | ||
9d5c8243 | 6231 | igb_reset(adapter); |
a8564f03 AD |
6232 | |
6233 | /* let the f/w know that the h/w is now under the control of the | |
6234 | * driver. */ | |
6235 | igb_get_hw_control(adapter); | |
6236 | ||
9d5c8243 AK |
6237 | wr32(E1000_WUS, ~0); |
6238 | ||
a88f10ec AD |
6239 | if (netif_running(netdev)) { |
6240 | err = igb_open(netdev); | |
6241 | if (err) | |
6242 | return err; | |
6243 | } | |
9d5c8243 AK |
6244 | |
6245 | netif_device_attach(netdev); | |
6246 | ||
9d5c8243 AK |
6247 | return 0; |
6248 | } | |
6249 | #endif | |
6250 | ||
6251 | static void igb_shutdown(struct pci_dev *pdev) | |
6252 | { | |
3fe7c4c9 RW |
6253 | bool wake; |
6254 | ||
6255 | __igb_shutdown(pdev, &wake); | |
6256 | ||
6257 | if (system_state == SYSTEM_POWER_OFF) { | |
6258 | pci_wake_from_d3(pdev, wake); | |
6259 | pci_set_power_state(pdev, PCI_D3hot); | |
6260 | } | |
9d5c8243 AK |
6261 | } |
6262 | ||
6263 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
6264 | /* | |
6265 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6266 | * without having to re-enable interrupts. It's not called while | |
6267 | * the interrupt routine is executing. | |
6268 | */ | |
6269 | static void igb_netpoll(struct net_device *netdev) | |
6270 | { | |
6271 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 6272 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 6273 | int i; |
9d5c8243 | 6274 | |
eebbbdba | 6275 | if (!adapter->msix_entries) { |
047e0030 | 6276 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
eebbbdba | 6277 | igb_irq_disable(adapter); |
047e0030 | 6278 | napi_schedule(&q_vector->napi); |
eebbbdba AD |
6279 | return; |
6280 | } | |
9d5c8243 | 6281 | |
047e0030 AD |
6282 | for (i = 0; i < adapter->num_q_vectors; i++) { |
6283 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
6284 | wr32(E1000_EIMC, q_vector->eims_value); | |
6285 | napi_schedule(&q_vector->napi); | |
eebbbdba | 6286 | } |
9d5c8243 AK |
6287 | } |
6288 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
6289 | ||
6290 | /** | |
6291 | * igb_io_error_detected - called when PCI error is detected | |
6292 | * @pdev: Pointer to PCI device | |
6293 | * @state: The current pci connection state | |
6294 | * | |
6295 | * This function is called after a PCI bus error affecting | |
6296 | * this device has been detected. | |
6297 | */ | |
6298 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
6299 | pci_channel_state_t state) | |
6300 | { | |
6301 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6302 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6303 | ||
6304 | netif_device_detach(netdev); | |
6305 | ||
59ed6eec AD |
6306 | if (state == pci_channel_io_perm_failure) |
6307 | return PCI_ERS_RESULT_DISCONNECT; | |
6308 | ||
9d5c8243 AK |
6309 | if (netif_running(netdev)) |
6310 | igb_down(adapter); | |
6311 | pci_disable_device(pdev); | |
6312 | ||
6313 | /* Request a slot slot reset. */ | |
6314 | return PCI_ERS_RESULT_NEED_RESET; | |
6315 | } | |
6316 | ||
6317 | /** | |
6318 | * igb_io_slot_reset - called after the pci bus has been reset. | |
6319 | * @pdev: Pointer to PCI device | |
6320 | * | |
6321 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
6322 | * resembles the first-half of the igb_resume routine. | |
6323 | */ | |
6324 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
6325 | { | |
6326 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6327 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6328 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 6329 | pci_ers_result_t result; |
42bfd33a | 6330 | int err; |
9d5c8243 | 6331 | |
aed5dec3 | 6332 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
6333 | dev_err(&pdev->dev, |
6334 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
6335 | result = PCI_ERS_RESULT_DISCONNECT; |
6336 | } else { | |
6337 | pci_set_master(pdev); | |
6338 | pci_restore_state(pdev); | |
b94f2d77 | 6339 | pci_save_state(pdev); |
9d5c8243 | 6340 | |
40a914fa AD |
6341 | pci_enable_wake(pdev, PCI_D3hot, 0); |
6342 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 6343 | |
40a914fa AD |
6344 | igb_reset(adapter); |
6345 | wr32(E1000_WUS, ~0); | |
6346 | result = PCI_ERS_RESULT_RECOVERED; | |
6347 | } | |
9d5c8243 | 6348 | |
ea943d41 JK |
6349 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
6350 | if (err) { | |
6351 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
6352 | "failed 0x%0x\n", err); | |
6353 | /* non-fatal, continue */ | |
6354 | } | |
40a914fa AD |
6355 | |
6356 | return result; | |
9d5c8243 AK |
6357 | } |
6358 | ||
6359 | /** | |
6360 | * igb_io_resume - called when traffic can start flowing again. | |
6361 | * @pdev: Pointer to PCI device | |
6362 | * | |
6363 | * This callback is called when the error recovery driver tells us that | |
6364 | * its OK to resume normal operation. Implementation resembles the | |
6365 | * second-half of the igb_resume routine. | |
6366 | */ | |
6367 | static void igb_io_resume(struct pci_dev *pdev) | |
6368 | { | |
6369 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6370 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6371 | ||
9d5c8243 AK |
6372 | if (netif_running(netdev)) { |
6373 | if (igb_up(adapter)) { | |
6374 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
6375 | return; | |
6376 | } | |
6377 | } | |
6378 | ||
6379 | netif_device_attach(netdev); | |
6380 | ||
6381 | /* let the f/w know that the h/w is now under the control of the | |
6382 | * driver. */ | |
6383 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
6384 | } |
6385 | ||
26ad9178 AD |
6386 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
6387 | u8 qsel) | |
6388 | { | |
6389 | u32 rar_low, rar_high; | |
6390 | struct e1000_hw *hw = &adapter->hw; | |
6391 | ||
6392 | /* HW expects these in little endian so we reverse the byte order | |
6393 | * from network order (big endian) to little endian | |
6394 | */ | |
6395 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
6396 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
6397 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
6398 | ||
6399 | /* Indicate to hardware the Address is Valid. */ | |
6400 | rar_high |= E1000_RAH_AV; | |
6401 | ||
6402 | if (hw->mac.type == e1000_82575) | |
6403 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
6404 | else | |
6405 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
6406 | ||
6407 | wr32(E1000_RAL(index), rar_low); | |
6408 | wrfl(); | |
6409 | wr32(E1000_RAH(index), rar_high); | |
6410 | wrfl(); | |
6411 | } | |
6412 | ||
4ae196df AD |
6413 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
6414 | int vf, unsigned char *mac_addr) | |
6415 | { | |
6416 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc AD |
6417 | /* VF MAC addresses start at end of receive addresses and moves |
6418 | * torwards the first, as a result a collision should not be possible */ | |
6419 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); | |
4ae196df | 6420 | |
37680117 | 6421 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 6422 | |
26ad9178 | 6423 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
6424 | |
6425 | return 0; | |
6426 | } | |
6427 | ||
8151d294 WM |
6428 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
6429 | { | |
6430 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6431 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | |
6432 | return -EINVAL; | |
6433 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | |
6434 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | |
6435 | dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" | |
6436 | " change effective."); | |
6437 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
6438 | dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," | |
6439 | " but the PF device is not up.\n"); | |
6440 | dev_warn(&adapter->pdev->dev, "Bring the PF device up before" | |
6441 | " attempting to use the VF device.\n"); | |
6442 | } | |
6443 | return igb_set_vf_mac(adapter, vf, mac); | |
6444 | } | |
6445 | ||
6446 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) | |
6447 | { | |
6448 | return -EOPNOTSUPP; | |
6449 | } | |
6450 | ||
6451 | static int igb_ndo_get_vf_config(struct net_device *netdev, | |
6452 | int vf, struct ifla_vf_info *ivi) | |
6453 | { | |
6454 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6455 | if (vf >= adapter->vfs_allocated_count) | |
6456 | return -EINVAL; | |
6457 | ivi->vf = vf; | |
6458 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | |
6459 | ivi->tx_rate = 0; | |
6460 | ivi->vlan = adapter->vf_data[vf].pf_vlan; | |
6461 | ivi->qos = adapter->vf_data[vf].pf_qos; | |
6462 | return 0; | |
6463 | } | |
6464 | ||
4ae196df AD |
6465 | static void igb_vmm_control(struct igb_adapter *adapter) |
6466 | { | |
6467 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 6468 | u32 reg; |
4ae196df | 6469 | |
52a1dd4d AD |
6470 | switch (hw->mac.type) { |
6471 | case e1000_82575: | |
6472 | default: | |
6473 | /* replication is not supported for 82575 */ | |
4ae196df | 6474 | return; |
52a1dd4d AD |
6475 | case e1000_82576: |
6476 | /* notify HW that the MAC is adding vlan tags */ | |
6477 | reg = rd32(E1000_DTXCTL); | |
6478 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
6479 | wr32(E1000_DTXCTL, reg); | |
6480 | case e1000_82580: | |
6481 | /* enable replication vlan tag stripping */ | |
6482 | reg = rd32(E1000_RPLOLR); | |
6483 | reg |= E1000_RPLOLR_STRVLAN; | |
6484 | wr32(E1000_RPLOLR, reg); | |
d2ba2ed8 AD |
6485 | case e1000_i350: |
6486 | /* none of the above registers are supported by i350 */ | |
52a1dd4d AD |
6487 | break; |
6488 | } | |
10d8e907 | 6489 | |
d4960307 AD |
6490 | if (adapter->vfs_allocated_count) { |
6491 | igb_vmdq_set_loopback_pf(hw, true); | |
6492 | igb_vmdq_set_replication_pf(hw, true); | |
6493 | } else { | |
6494 | igb_vmdq_set_loopback_pf(hw, false); | |
6495 | igb_vmdq_set_replication_pf(hw, false); | |
6496 | } | |
4ae196df AD |
6497 | } |
6498 | ||
9d5c8243 | 6499 | /* igb_main.c */ |