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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/pagemap.h> | |
33 | #include <linux/netdevice.h> | |
9d5c8243 AK |
34 | #include <linux/ipv6.h> |
35 | #include <net/checksum.h> | |
36 | #include <net/ip6_checksum.h> | |
c6cb090b | 37 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
38 | #include <linux/mii.h> |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/if_vlan.h> | |
41 | #include <linux/pci.h> | |
c54106bb | 42 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
43 | #include <linux/delay.h> |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/if_ether.h> | |
40a914fa | 46 | #include <linux/aer.h> |
421e02f0 | 47 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
48 | #include <linux/dca.h> |
49 | #endif | |
9d5c8243 AK |
50 | #include "igb.h" |
51 | ||
86d5d38f | 52 | #define DRV_VERSION "1.3.16-k2" |
9d5c8243 AK |
53 | char igb_driver_name[] = "igb"; |
54 | char igb_driver_version[] = DRV_VERSION; | |
55 | static const char igb_driver_string[] = | |
56 | "Intel(R) Gigabit Ethernet Network Driver"; | |
86d5d38f | 57 | static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation."; |
9d5c8243 | 58 | |
9d5c8243 AK |
59 | static const struct e1000_info *igb_info_tbl[] = { |
60 | [board_82575] = &e1000_82575_info, | |
61 | }; | |
62 | ||
63 | static struct pci_device_id igb_pci_tbl[] = { | |
2d064c06 AD |
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, | |
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
9d5c8243 AK |
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
70 | /* required last entry */ | |
71 | {0, } | |
72 | }; | |
73 | ||
74 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
75 | ||
76 | void igb_reset(struct igb_adapter *); | |
77 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
78 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
79 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
80 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
9d5c8243 AK |
81 | void igb_update_stats(struct igb_adapter *); |
82 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | |
83 | static void __devexit igb_remove(struct pci_dev *pdev); | |
84 | static int igb_sw_init(struct igb_adapter *); | |
85 | static int igb_open(struct net_device *); | |
86 | static int igb_close(struct net_device *); | |
87 | static void igb_configure_tx(struct igb_adapter *); | |
88 | static void igb_configure_rx(struct igb_adapter *); | |
89 | static void igb_setup_rctl(struct igb_adapter *); | |
90 | static void igb_clean_all_tx_rings(struct igb_adapter *); | |
91 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
92 | static void igb_clean_tx_ring(struct igb_ring *); |
93 | static void igb_clean_rx_ring(struct igb_ring *); | |
9d5c8243 AK |
94 | static void igb_set_multi(struct net_device *); |
95 | static void igb_update_phy_info(unsigned long); | |
96 | static void igb_watchdog(unsigned long); | |
97 | static void igb_watchdog_task(struct work_struct *); | |
98 | static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *, | |
99 | struct igb_ring *); | |
100 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); | |
101 | static struct net_device_stats *igb_get_stats(struct net_device *); | |
102 | static int igb_change_mtu(struct net_device *, int); | |
103 | static int igb_set_mac(struct net_device *, void *); | |
104 | static irqreturn_t igb_intr(int irq, void *); | |
105 | static irqreturn_t igb_intr_msi(int irq, void *); | |
106 | static irqreturn_t igb_msix_other(int irq, void *); | |
107 | static irqreturn_t igb_msix_rx(int irq, void *); | |
108 | static irqreturn_t igb_msix_tx(int irq, void *); | |
109 | static int igb_clean_rx_ring_msix(struct napi_struct *, int); | |
421e02f0 | 110 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
111 | static void igb_update_rx_dca(struct igb_ring *); |
112 | static void igb_update_tx_dca(struct igb_ring *); | |
113 | static void igb_setup_dca(struct igb_adapter *); | |
421e02f0 | 114 | #endif /* CONFIG_IGB_DCA */ |
3b644cf6 | 115 | static bool igb_clean_tx_irq(struct igb_ring *); |
661086df | 116 | static int igb_poll(struct napi_struct *, int); |
3b644cf6 MW |
117 | static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int); |
118 | static void igb_alloc_rx_buffers_adv(struct igb_ring *, int); | |
9d5c8243 AK |
119 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
120 | static void igb_tx_timeout(struct net_device *); | |
121 | static void igb_reset_task(struct work_struct *); | |
122 | static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |
123 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | |
124 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
125 | static void igb_restore_vlan(struct igb_adapter *); | |
126 | ||
127 | static int igb_suspend(struct pci_dev *, pm_message_t); | |
128 | #ifdef CONFIG_PM | |
129 | static int igb_resume(struct pci_dev *); | |
130 | #endif | |
131 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 132 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
133 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
134 | static struct notifier_block dca_notifier = { | |
135 | .notifier_call = igb_notify_dca, | |
136 | .next = NULL, | |
137 | .priority = 0 | |
138 | }; | |
139 | #endif | |
9d5c8243 AK |
140 | |
141 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
142 | /* for netdump / net console */ | |
143 | static void igb_netpoll(struct net_device *); | |
144 | #endif | |
145 | ||
146 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, | |
147 | pci_channel_state_t); | |
148 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
149 | static void igb_io_resume(struct pci_dev *); | |
150 | ||
151 | static struct pci_error_handlers igb_err_handler = { | |
152 | .error_detected = igb_io_error_detected, | |
153 | .slot_reset = igb_io_slot_reset, | |
154 | .resume = igb_io_resume, | |
155 | }; | |
156 | ||
157 | ||
158 | static struct pci_driver igb_driver = { | |
159 | .name = igb_driver_name, | |
160 | .id_table = igb_pci_tbl, | |
161 | .probe = igb_probe, | |
162 | .remove = __devexit_p(igb_remove), | |
163 | #ifdef CONFIG_PM | |
164 | /* Power Managment Hooks */ | |
165 | .suspend = igb_suspend, | |
166 | .resume = igb_resume, | |
167 | #endif | |
168 | .shutdown = igb_shutdown, | |
169 | .err_handler = &igb_err_handler | |
170 | }; | |
171 | ||
7dfc16fa AD |
172 | static int global_quad_port_a; /* global quad port a indication */ |
173 | ||
9d5c8243 AK |
174 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); |
175 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
176 | MODULE_LICENSE("GPL"); | |
177 | MODULE_VERSION(DRV_VERSION); | |
178 | ||
38c845c7 PO |
179 | /** |
180 | * Scale the NIC clock cycle by a large factor so that | |
181 | * relatively small clock corrections can be added or | |
182 | * substracted at each clock tick. The drawbacks of a | |
183 | * large factor are a) that the clock register overflows | |
184 | * more quickly (not such a big deal) and b) that the | |
185 | * increment per tick has to fit into 24 bits. | |
186 | * | |
187 | * Note that | |
188 | * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * | |
189 | * IGB_TSYNC_SCALE | |
190 | * TIMINCA += TIMINCA * adjustment [ppm] / 1e9 | |
191 | * | |
192 | * The base scale factor is intentionally a power of two | |
193 | * so that the division in %struct timecounter can be done with | |
194 | * a shift. | |
195 | */ | |
196 | #define IGB_TSYNC_SHIFT (19) | |
197 | #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT) | |
198 | ||
199 | /** | |
200 | * The duration of one clock cycle of the NIC. | |
201 | * | |
202 | * @todo This hard-coded value is part of the specification and might change | |
203 | * in future hardware revisions. Add revision check. | |
204 | */ | |
205 | #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16 | |
206 | ||
207 | #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24) | |
208 | # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA | |
209 | #endif | |
210 | ||
211 | /** | |
212 | * igb_read_clock - read raw cycle counter (to be used by time counter) | |
213 | */ | |
214 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | |
215 | { | |
216 | struct igb_adapter *adapter = | |
217 | container_of(tc, struct igb_adapter, cycles); | |
218 | struct e1000_hw *hw = &adapter->hw; | |
219 | u64 stamp; | |
220 | ||
221 | stamp = rd32(E1000_SYSTIML); | |
222 | stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL; | |
223 | ||
224 | return stamp; | |
225 | } | |
226 | ||
9d5c8243 AK |
227 | #ifdef DEBUG |
228 | /** | |
229 | * igb_get_hw_dev_name - return device name string | |
230 | * used by hardware layer to print debugging information | |
231 | **/ | |
232 | char *igb_get_hw_dev_name(struct e1000_hw *hw) | |
233 | { | |
234 | struct igb_adapter *adapter = hw->back; | |
235 | return adapter->netdev->name; | |
236 | } | |
38c845c7 PO |
237 | |
238 | /** | |
239 | * igb_get_time_str - format current NIC and system time as string | |
240 | */ | |
241 | static char *igb_get_time_str(struct igb_adapter *adapter, | |
242 | char buffer[160]) | |
243 | { | |
244 | cycle_t hw = adapter->cycles.read(&adapter->cycles); | |
245 | struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock)); | |
246 | struct timespec sys; | |
247 | struct timespec delta; | |
248 | getnstimeofday(&sys); | |
249 | ||
250 | delta = timespec_sub(nic, sys); | |
251 | ||
252 | sprintf(buffer, | |
33af6bcc PO |
253 | "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns", |
254 | hw, | |
38c845c7 PO |
255 | (long)nic.tv_sec, nic.tv_nsec, |
256 | (long)sys.tv_sec, sys.tv_nsec, | |
257 | (long)delta.tv_sec, delta.tv_nsec); | |
258 | ||
259 | return buffer; | |
260 | } | |
9d5c8243 AK |
261 | #endif |
262 | ||
263 | /** | |
264 | * igb_init_module - Driver Registration Routine | |
265 | * | |
266 | * igb_init_module is the first routine called when the driver is | |
267 | * loaded. All it does is register with the PCI subsystem. | |
268 | **/ | |
269 | static int __init igb_init_module(void) | |
270 | { | |
271 | int ret; | |
272 | printk(KERN_INFO "%s - version %s\n", | |
273 | igb_driver_string, igb_driver_version); | |
274 | ||
275 | printk(KERN_INFO "%s\n", igb_copyright); | |
276 | ||
7dfc16fa AD |
277 | global_quad_port_a = 0; |
278 | ||
421e02f0 | 279 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
280 | dca_register_notify(&dca_notifier); |
281 | #endif | |
bbd98fe4 AD |
282 | |
283 | ret = pci_register_driver(&igb_driver); | |
9d5c8243 AK |
284 | return ret; |
285 | } | |
286 | ||
287 | module_init(igb_init_module); | |
288 | ||
289 | /** | |
290 | * igb_exit_module - Driver Exit Cleanup Routine | |
291 | * | |
292 | * igb_exit_module is called just before the driver is removed | |
293 | * from memory. | |
294 | **/ | |
295 | static void __exit igb_exit_module(void) | |
296 | { | |
421e02f0 | 297 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
298 | dca_unregister_notify(&dca_notifier); |
299 | #endif | |
9d5c8243 AK |
300 | pci_unregister_driver(&igb_driver); |
301 | } | |
302 | ||
303 | module_exit(igb_exit_module); | |
304 | ||
26bc19ec AD |
305 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
306 | /** | |
307 | * igb_cache_ring_register - Descriptor ring to register mapping | |
308 | * @adapter: board private structure to initialize | |
309 | * | |
310 | * Once we know the feature-set enabled for the device, we'll cache | |
311 | * the register offset the descriptor ring is assigned to. | |
312 | **/ | |
313 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
314 | { | |
315 | int i; | |
316 | ||
317 | switch (adapter->hw.mac.type) { | |
318 | case e1000_82576: | |
319 | /* The queues are allocated for virtualization such that VF 0 | |
320 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
321 | * In order to avoid collision we start at the first free queue | |
322 | * and continue consuming queues in the same sequence | |
323 | */ | |
324 | for (i = 0; i < adapter->num_rx_queues; i++) | |
325 | adapter->rx_ring[i].reg_idx = Q_IDX_82576(i); | |
326 | for (i = 0; i < adapter->num_tx_queues; i++) | |
327 | adapter->tx_ring[i].reg_idx = Q_IDX_82576(i); | |
328 | break; | |
329 | case e1000_82575: | |
330 | default: | |
331 | for (i = 0; i < adapter->num_rx_queues; i++) | |
332 | adapter->rx_ring[i].reg_idx = i; | |
333 | for (i = 0; i < adapter->num_tx_queues; i++) | |
334 | adapter->tx_ring[i].reg_idx = i; | |
335 | break; | |
336 | } | |
337 | } | |
338 | ||
9d5c8243 AK |
339 | /** |
340 | * igb_alloc_queues - Allocate memory for all rings | |
341 | * @adapter: board private structure to initialize | |
342 | * | |
343 | * We allocate one ring per queue at run-time since we don't know the | |
344 | * number of queues at compile-time. | |
345 | **/ | |
346 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
347 | { | |
348 | int i; | |
349 | ||
350 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
351 | sizeof(struct igb_ring), GFP_KERNEL); | |
352 | if (!adapter->tx_ring) | |
353 | return -ENOMEM; | |
354 | ||
355 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
356 | sizeof(struct igb_ring), GFP_KERNEL); | |
357 | if (!adapter->rx_ring) { | |
358 | kfree(adapter->tx_ring); | |
359 | return -ENOMEM; | |
360 | } | |
361 | ||
6eb5a7f1 AD |
362 | adapter->rx_ring->buddy = adapter->tx_ring; |
363 | ||
661086df PWJ |
364 | for (i = 0; i < adapter->num_tx_queues; i++) { |
365 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
68fd9910 | 366 | ring->count = adapter->tx_ring_count; |
661086df PWJ |
367 | ring->adapter = adapter; |
368 | ring->queue_index = i; | |
369 | } | |
9d5c8243 AK |
370 | for (i = 0; i < adapter->num_rx_queues; i++) { |
371 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
68fd9910 | 372 | ring->count = adapter->rx_ring_count; |
9d5c8243 | 373 | ring->adapter = adapter; |
844290e5 | 374 | ring->queue_index = i; |
9d5c8243 AK |
375 | ring->itr_register = E1000_ITR; |
376 | ||
844290e5 | 377 | /* set a default napi handler for each rx_ring */ |
661086df | 378 | netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64); |
9d5c8243 | 379 | } |
26bc19ec AD |
380 | |
381 | igb_cache_ring_register(adapter); | |
9d5c8243 AK |
382 | return 0; |
383 | } | |
384 | ||
a88f10ec AD |
385 | static void igb_free_queues(struct igb_adapter *adapter) |
386 | { | |
387 | int i; | |
388 | ||
389 | for (i = 0; i < adapter->num_rx_queues; i++) | |
390 | netif_napi_del(&adapter->rx_ring[i].napi); | |
391 | ||
392 | kfree(adapter->tx_ring); | |
393 | kfree(adapter->rx_ring); | |
394 | } | |
395 | ||
9d5c8243 AK |
396 | #define IGB_N0_QUEUE -1 |
397 | static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |
398 | int tx_queue, int msix_vector) | |
399 | { | |
400 | u32 msixbm = 0; | |
401 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
402 | u32 ivar, index; |
403 | ||
404 | switch (hw->mac.type) { | |
405 | case e1000_82575: | |
9d5c8243 AK |
406 | /* The 82575 assigns vectors using a bitmask, which matches the |
407 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
408 | or more queues to a vector, we write the appropriate bits | |
409 | into the MSIXBM register for that vector. */ | |
410 | if (rx_queue > IGB_N0_QUEUE) { | |
411 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; | |
412 | adapter->rx_ring[rx_queue].eims_value = msixbm; | |
413 | } | |
414 | if (tx_queue > IGB_N0_QUEUE) { | |
415 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; | |
416 | adapter->tx_ring[tx_queue].eims_value = | |
417 | E1000_EICR_TX_QUEUE0 << tx_queue; | |
418 | } | |
419 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | |
2d064c06 AD |
420 | break; |
421 | case e1000_82576: | |
26bc19ec | 422 | /* 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
423 | Each queue has a single entry in the table to which we write |
424 | a vector number along with a "valid" bit. Sadly, the layout | |
425 | of the table is somewhat counterintuitive. */ | |
426 | if (rx_queue > IGB_N0_QUEUE) { | |
26bc19ec | 427 | index = (rx_queue >> 1); |
2d064c06 | 428 | ivar = array_rd32(E1000_IVAR0, index); |
26bc19ec | 429 | if (rx_queue & 0x1) { |
2d064c06 AD |
430 | /* vector goes into third byte of register */ |
431 | ivar = ivar & 0xFF00FFFF; | |
432 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
26bc19ec AD |
433 | } else { |
434 | /* vector goes into low byte of register */ | |
435 | ivar = ivar & 0xFFFFFF00; | |
436 | ivar |= msix_vector | E1000_IVAR_VALID; | |
2d064c06 AD |
437 | } |
438 | adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; | |
439 | array_wr32(E1000_IVAR0, index, ivar); | |
440 | } | |
441 | if (tx_queue > IGB_N0_QUEUE) { | |
26bc19ec | 442 | index = (tx_queue >> 1); |
2d064c06 | 443 | ivar = array_rd32(E1000_IVAR0, index); |
26bc19ec | 444 | if (tx_queue & 0x1) { |
2d064c06 AD |
445 | /* vector goes into high byte of register */ |
446 | ivar = ivar & 0x00FFFFFF; | |
447 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
26bc19ec AD |
448 | } else { |
449 | /* vector goes into second byte of register */ | |
450 | ivar = ivar & 0xFFFF00FF; | |
451 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
2d064c06 AD |
452 | } |
453 | adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; | |
454 | array_wr32(E1000_IVAR0, index, ivar); | |
455 | } | |
456 | break; | |
457 | default: | |
458 | BUG(); | |
459 | break; | |
460 | } | |
9d5c8243 AK |
461 | } |
462 | ||
463 | /** | |
464 | * igb_configure_msix - Configure MSI-X hardware | |
465 | * | |
466 | * igb_configure_msix sets up the hardware to properly | |
467 | * generate MSI-X interrupts. | |
468 | **/ | |
469 | static void igb_configure_msix(struct igb_adapter *adapter) | |
470 | { | |
471 | u32 tmp; | |
472 | int i, vector = 0; | |
473 | struct e1000_hw *hw = &adapter->hw; | |
474 | ||
475 | adapter->eims_enable_mask = 0; | |
2d064c06 AD |
476 | if (hw->mac.type == e1000_82576) |
477 | /* Turn on MSI-X capability first, or our settings | |
478 | * won't stick. And it will take days to debug. */ | |
479 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
eebbbdba | 480 | E1000_GPIE_PBA | E1000_GPIE_EIAME | |
2d064c06 | 481 | E1000_GPIE_NSICR); |
9d5c8243 AK |
482 | |
483 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
484 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
485 | igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); | |
486 | adapter->eims_enable_mask |= tx_ring->eims_value; | |
487 | if (tx_ring->itr_val) | |
6eb5a7f1 | 488 | writel(tx_ring->itr_val, |
9d5c8243 AK |
489 | hw->hw_addr + tx_ring->itr_register); |
490 | else | |
491 | writel(1, hw->hw_addr + tx_ring->itr_register); | |
492 | } | |
493 | ||
494 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
495 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
25ac3c24 | 496 | rx_ring->buddy = NULL; |
9d5c8243 AK |
497 | igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); |
498 | adapter->eims_enable_mask |= rx_ring->eims_value; | |
499 | if (rx_ring->itr_val) | |
6eb5a7f1 | 500 | writel(rx_ring->itr_val, |
9d5c8243 AK |
501 | hw->hw_addr + rx_ring->itr_register); |
502 | else | |
503 | writel(1, hw->hw_addr + rx_ring->itr_register); | |
504 | } | |
505 | ||
506 | ||
507 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
508 | switch (hw->mac.type) { |
509 | case e1000_82575: | |
9d5c8243 AK |
510 | array_wr32(E1000_MSIXBM(0), vector++, |
511 | E1000_EIMS_OTHER); | |
512 | ||
9d5c8243 AK |
513 | tmp = rd32(E1000_CTRL_EXT); |
514 | /* enable MSI-X PBA support*/ | |
515 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
516 | ||
517 | /* Auto-Mask interrupts upon ICR read. */ | |
518 | tmp |= E1000_CTRL_EXT_EIAME; | |
519 | tmp |= E1000_CTRL_EXT_IRCA; | |
520 | ||
521 | wr32(E1000_CTRL_EXT, tmp); | |
522 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; | |
844290e5 | 523 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 524 | |
2d064c06 AD |
525 | break; |
526 | ||
527 | case e1000_82576: | |
528 | tmp = (vector++ | E1000_IVAR_VALID) << 8; | |
529 | wr32(E1000_IVAR_MISC, tmp); | |
530 | ||
531 | adapter->eims_enable_mask = (1 << (vector)) - 1; | |
532 | adapter->eims_other = 1 << (vector - 1); | |
533 | break; | |
534 | default: | |
535 | /* do nothing, since nothing else supports MSI-X */ | |
536 | break; | |
537 | } /* switch (hw->mac.type) */ | |
9d5c8243 AK |
538 | wrfl(); |
539 | } | |
540 | ||
541 | /** | |
542 | * igb_request_msix - Initialize MSI-X interrupts | |
543 | * | |
544 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
545 | * kernel. | |
546 | **/ | |
547 | static int igb_request_msix(struct igb_adapter *adapter) | |
548 | { | |
549 | struct net_device *netdev = adapter->netdev; | |
550 | int i, err = 0, vector = 0; | |
551 | ||
552 | vector = 0; | |
553 | ||
554 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
555 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
cb7b48f6 | 556 | sprintf(ring->name, "%s-tx-%d", netdev->name, i); |
9d5c8243 AK |
557 | err = request_irq(adapter->msix_entries[vector].vector, |
558 | &igb_msix_tx, 0, ring->name, | |
559 | &(adapter->tx_ring[i])); | |
560 | if (err) | |
561 | goto out; | |
562 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
6eb5a7f1 | 563 | ring->itr_val = 976; /* ~4000 ints/sec */ |
9d5c8243 AK |
564 | vector++; |
565 | } | |
566 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
567 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
568 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
cb7b48f6 | 569 | sprintf(ring->name, "%s-rx-%d", netdev->name, i); |
9d5c8243 AK |
570 | else |
571 | memcpy(ring->name, netdev->name, IFNAMSIZ); | |
572 | err = request_irq(adapter->msix_entries[vector].vector, | |
573 | &igb_msix_rx, 0, ring->name, | |
574 | &(adapter->rx_ring[i])); | |
575 | if (err) | |
576 | goto out; | |
577 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
578 | ring->itr_val = adapter->itr; | |
844290e5 PW |
579 | /* overwrite the poll routine for MSIX, we've already done |
580 | * netif_napi_add */ | |
581 | ring->napi.poll = &igb_clean_rx_ring_msix; | |
9d5c8243 AK |
582 | vector++; |
583 | } | |
584 | ||
585 | err = request_irq(adapter->msix_entries[vector].vector, | |
586 | &igb_msix_other, 0, netdev->name, netdev); | |
587 | if (err) | |
588 | goto out; | |
589 | ||
9d5c8243 AK |
590 | igb_configure_msix(adapter); |
591 | return 0; | |
592 | out: | |
593 | return err; | |
594 | } | |
595 | ||
596 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
597 | { | |
598 | if (adapter->msix_entries) { | |
599 | pci_disable_msix(adapter->pdev); | |
600 | kfree(adapter->msix_entries); | |
601 | adapter->msix_entries = NULL; | |
7dfc16fa | 602 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) |
9d5c8243 AK |
603 | pci_disable_msi(adapter->pdev); |
604 | return; | |
605 | } | |
606 | ||
607 | ||
608 | /** | |
609 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
610 | * | |
611 | * Attempt to configure interrupts using the best available | |
612 | * capabilities of the hardware and kernel. | |
613 | **/ | |
614 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |
615 | { | |
616 | int err; | |
617 | int numvecs, i; | |
618 | ||
83b7180d AD |
619 | /* Number of supported queues. */ |
620 | /* Having more queues than CPUs doesn't make sense. */ | |
621 | adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); | |
622 | adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus()); | |
623 | ||
9d5c8243 AK |
624 | numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; |
625 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), | |
626 | GFP_KERNEL); | |
627 | if (!adapter->msix_entries) | |
628 | goto msi_only; | |
629 | ||
630 | for (i = 0; i < numvecs; i++) | |
631 | adapter->msix_entries[i].entry = i; | |
632 | ||
633 | err = pci_enable_msix(adapter->pdev, | |
634 | adapter->msix_entries, | |
635 | numvecs); | |
636 | if (err == 0) | |
34a20e89 | 637 | goto out; |
9d5c8243 AK |
638 | |
639 | igb_reset_interrupt_capability(adapter); | |
640 | ||
641 | /* If we can't do MSI-X, try MSI */ | |
642 | msi_only: | |
643 | adapter->num_rx_queues = 1; | |
661086df | 644 | adapter->num_tx_queues = 1; |
9d5c8243 | 645 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 646 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 647 | out: |
661086df | 648 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 649 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
9d5c8243 AK |
650 | return; |
651 | } | |
652 | ||
653 | /** | |
654 | * igb_request_irq - initialize interrupts | |
655 | * | |
656 | * Attempts to configure interrupts using the best available | |
657 | * capabilities of the hardware and kernel. | |
658 | **/ | |
659 | static int igb_request_irq(struct igb_adapter *adapter) | |
660 | { | |
661 | struct net_device *netdev = adapter->netdev; | |
662 | struct e1000_hw *hw = &adapter->hw; | |
663 | int err = 0; | |
664 | ||
665 | if (adapter->msix_entries) { | |
666 | err = igb_request_msix(adapter); | |
844290e5 | 667 | if (!err) |
9d5c8243 | 668 | goto request_done; |
9d5c8243 AK |
669 | /* fall back to MSI */ |
670 | igb_reset_interrupt_capability(adapter); | |
671 | if (!pci_enable_msi(adapter->pdev)) | |
7dfc16fa | 672 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
673 | igb_free_all_tx_resources(adapter); |
674 | igb_free_all_rx_resources(adapter); | |
675 | adapter->num_rx_queues = 1; | |
676 | igb_alloc_queues(adapter); | |
844290e5 | 677 | } else { |
2d064c06 AD |
678 | switch (hw->mac.type) { |
679 | case e1000_82575: | |
680 | wr32(E1000_MSIXBM(0), | |
681 | (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); | |
682 | break; | |
683 | case e1000_82576: | |
684 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | |
685 | break; | |
686 | default: | |
687 | break; | |
688 | } | |
9d5c8243 | 689 | } |
844290e5 | 690 | |
7dfc16fa | 691 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 AK |
692 | err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, |
693 | netdev->name, netdev); | |
694 | if (!err) | |
695 | goto request_done; | |
696 | /* fall back to legacy interrupts */ | |
697 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 698 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
699 | } |
700 | ||
701 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, | |
702 | netdev->name, netdev); | |
703 | ||
6cb5e577 | 704 | if (err) |
9d5c8243 AK |
705 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
706 | err); | |
9d5c8243 AK |
707 | |
708 | request_done: | |
709 | return err; | |
710 | } | |
711 | ||
712 | static void igb_free_irq(struct igb_adapter *adapter) | |
713 | { | |
714 | struct net_device *netdev = adapter->netdev; | |
715 | ||
716 | if (adapter->msix_entries) { | |
717 | int vector = 0, i; | |
718 | ||
719 | for (i = 0; i < adapter->num_tx_queues; i++) | |
720 | free_irq(adapter->msix_entries[vector++].vector, | |
721 | &(adapter->tx_ring[i])); | |
722 | for (i = 0; i < adapter->num_rx_queues; i++) | |
723 | free_irq(adapter->msix_entries[vector++].vector, | |
724 | &(adapter->rx_ring[i])); | |
725 | ||
726 | free_irq(adapter->msix_entries[vector++].vector, netdev); | |
727 | return; | |
728 | } | |
729 | ||
730 | free_irq(adapter->pdev->irq, netdev); | |
731 | } | |
732 | ||
733 | /** | |
734 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
735 | * @adapter: board private structure | |
736 | **/ | |
737 | static void igb_irq_disable(struct igb_adapter *adapter) | |
738 | { | |
739 | struct e1000_hw *hw = &adapter->hw; | |
740 | ||
741 | if (adapter->msix_entries) { | |
844290e5 | 742 | wr32(E1000_EIAM, 0); |
9d5c8243 AK |
743 | wr32(E1000_EIMC, ~0); |
744 | wr32(E1000_EIAC, 0); | |
745 | } | |
844290e5 PW |
746 | |
747 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
748 | wr32(E1000_IMC, ~0); |
749 | wrfl(); | |
750 | synchronize_irq(adapter->pdev->irq); | |
751 | } | |
752 | ||
753 | /** | |
754 | * igb_irq_enable - Enable default interrupt generation settings | |
755 | * @adapter: board private structure | |
756 | **/ | |
757 | static void igb_irq_enable(struct igb_adapter *adapter) | |
758 | { | |
759 | struct e1000_hw *hw = &adapter->hw; | |
760 | ||
761 | if (adapter->msix_entries) { | |
844290e5 PW |
762 | wr32(E1000_EIAC, adapter->eims_enable_mask); |
763 | wr32(E1000_EIAM, adapter->eims_enable_mask); | |
764 | wr32(E1000_EIMS, adapter->eims_enable_mask); | |
dda0e083 | 765 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); |
844290e5 PW |
766 | } else { |
767 | wr32(E1000_IMS, IMS_ENABLE_MASK); | |
768 | wr32(E1000_IAM, IMS_ENABLE_MASK); | |
769 | } | |
9d5c8243 AK |
770 | } |
771 | ||
772 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
773 | { | |
774 | struct net_device *netdev = adapter->netdev; | |
775 | u16 vid = adapter->hw.mng_cookie.vlan_id; | |
776 | u16 old_vid = adapter->mng_vlan_id; | |
777 | if (adapter->vlgrp) { | |
778 | if (!vlan_group_get_device(adapter->vlgrp, vid)) { | |
779 | if (adapter->hw.mng_cookie.status & | |
780 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
781 | igb_vlan_rx_add_vid(netdev, vid); | |
782 | adapter->mng_vlan_id = vid; | |
783 | } else | |
784 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
785 | ||
786 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
787 | (vid != old_vid) && | |
788 | !vlan_group_get_device(adapter->vlgrp, old_vid)) | |
789 | igb_vlan_rx_kill_vid(netdev, old_vid); | |
790 | } else | |
791 | adapter->mng_vlan_id = vid; | |
792 | } | |
793 | } | |
794 | ||
795 | /** | |
796 | * igb_release_hw_control - release control of the h/w to f/w | |
797 | * @adapter: address of board private structure | |
798 | * | |
799 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
800 | * For ASF and Pass Through versions of f/w this means that the | |
801 | * driver is no longer loaded. | |
802 | * | |
803 | **/ | |
804 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
805 | { | |
806 | struct e1000_hw *hw = &adapter->hw; | |
807 | u32 ctrl_ext; | |
808 | ||
809 | /* Let firmware take over control of h/w */ | |
810 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
811 | wr32(E1000_CTRL_EXT, | |
812 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
813 | } | |
814 | ||
815 | ||
816 | /** | |
817 | * igb_get_hw_control - get control of the h/w from f/w | |
818 | * @adapter: address of board private structure | |
819 | * | |
820 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
821 | * For ASF and Pass Through versions of f/w this means that | |
822 | * the driver is loaded. | |
823 | * | |
824 | **/ | |
825 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
826 | { | |
827 | struct e1000_hw *hw = &adapter->hw; | |
828 | u32 ctrl_ext; | |
829 | ||
830 | /* Let firmware know the driver has taken over */ | |
831 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
832 | wr32(E1000_CTRL_EXT, | |
833 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
834 | } | |
835 | ||
9d5c8243 AK |
836 | /** |
837 | * igb_configure - configure the hardware for RX and TX | |
838 | * @adapter: private board structure | |
839 | **/ | |
840 | static void igb_configure(struct igb_adapter *adapter) | |
841 | { | |
842 | struct net_device *netdev = adapter->netdev; | |
843 | int i; | |
844 | ||
845 | igb_get_hw_control(adapter); | |
846 | igb_set_multi(netdev); | |
847 | ||
848 | igb_restore_vlan(adapter); | |
9d5c8243 AK |
849 | |
850 | igb_configure_tx(adapter); | |
851 | igb_setup_rctl(adapter); | |
852 | igb_configure_rx(adapter); | |
662d7205 AD |
853 | |
854 | igb_rx_fifo_flush_82575(&adapter->hw); | |
855 | ||
9d5c8243 AK |
856 | /* call IGB_DESC_UNUSED which always leaves |
857 | * at least 1 descriptor unused to make sure | |
858 | * next_to_use != next_to_clean */ | |
859 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
860 | struct igb_ring *ring = &adapter->rx_ring[i]; | |
3b644cf6 | 861 | igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring)); |
9d5c8243 AK |
862 | } |
863 | ||
864 | ||
865 | adapter->tx_queue_len = netdev->tx_queue_len; | |
866 | } | |
867 | ||
868 | ||
869 | /** | |
870 | * igb_up - Open the interface and prepare it to handle traffic | |
871 | * @adapter: board private structure | |
872 | **/ | |
873 | ||
874 | int igb_up(struct igb_adapter *adapter) | |
875 | { | |
876 | struct e1000_hw *hw = &adapter->hw; | |
877 | int i; | |
878 | ||
879 | /* hardware has been reset, we need to reload some things */ | |
880 | igb_configure(adapter); | |
881 | ||
882 | clear_bit(__IGB_DOWN, &adapter->state); | |
883 | ||
844290e5 PW |
884 | for (i = 0; i < adapter->num_rx_queues; i++) |
885 | napi_enable(&adapter->rx_ring[i].napi); | |
886 | if (adapter->msix_entries) | |
9d5c8243 | 887 | igb_configure_msix(adapter); |
9d5c8243 AK |
888 | |
889 | /* Clear any pending interrupts. */ | |
890 | rd32(E1000_ICR); | |
891 | igb_irq_enable(adapter); | |
892 | ||
893 | /* Fire a link change interrupt to start the watchdog. */ | |
894 | wr32(E1000_ICS, E1000_ICS_LSC); | |
895 | return 0; | |
896 | } | |
897 | ||
898 | void igb_down(struct igb_adapter *adapter) | |
899 | { | |
900 | struct e1000_hw *hw = &adapter->hw; | |
901 | struct net_device *netdev = adapter->netdev; | |
902 | u32 tctl, rctl; | |
903 | int i; | |
904 | ||
905 | /* signal that we're down so the interrupt handler does not | |
906 | * reschedule our watchdog timer */ | |
907 | set_bit(__IGB_DOWN, &adapter->state); | |
908 | ||
909 | /* disable receives in the hardware */ | |
910 | rctl = rd32(E1000_RCTL); | |
911 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
912 | /* flush and sleep below */ | |
913 | ||
fd2ea0a7 | 914 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
915 | |
916 | /* disable transmits in the hardware */ | |
917 | tctl = rd32(E1000_TCTL); | |
918 | tctl &= ~E1000_TCTL_EN; | |
919 | wr32(E1000_TCTL, tctl); | |
920 | /* flush both disables and wait for them to finish */ | |
921 | wrfl(); | |
922 | msleep(10); | |
923 | ||
844290e5 PW |
924 | for (i = 0; i < adapter->num_rx_queues; i++) |
925 | napi_disable(&adapter->rx_ring[i].napi); | |
9d5c8243 | 926 | |
9d5c8243 AK |
927 | igb_irq_disable(adapter); |
928 | ||
929 | del_timer_sync(&adapter->watchdog_timer); | |
930 | del_timer_sync(&adapter->phy_info_timer); | |
931 | ||
932 | netdev->tx_queue_len = adapter->tx_queue_len; | |
933 | netif_carrier_off(netdev); | |
04fe6358 AD |
934 | |
935 | /* record the stats before reset*/ | |
936 | igb_update_stats(adapter); | |
937 | ||
9d5c8243 AK |
938 | adapter->link_speed = 0; |
939 | adapter->link_duplex = 0; | |
940 | ||
3023682e JK |
941 | if (!pci_channel_offline(adapter->pdev)) |
942 | igb_reset(adapter); | |
9d5c8243 AK |
943 | igb_clean_all_tx_rings(adapter); |
944 | igb_clean_all_rx_rings(adapter); | |
945 | } | |
946 | ||
947 | void igb_reinit_locked(struct igb_adapter *adapter) | |
948 | { | |
949 | WARN_ON(in_interrupt()); | |
950 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
951 | msleep(1); | |
952 | igb_down(adapter); | |
953 | igb_up(adapter); | |
954 | clear_bit(__IGB_RESETTING, &adapter->state); | |
955 | } | |
956 | ||
957 | void igb_reset(struct igb_adapter *adapter) | |
958 | { | |
959 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
960 | struct e1000_mac_info *mac = &hw->mac; |
961 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
962 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
963 | u16 hwm; | |
964 | ||
965 | /* Repartition Pba for greater than 9k mtu | |
966 | * To take effect CTRL.RST is required. | |
967 | */ | |
fa4dfae0 AD |
968 | switch (mac->type) { |
969 | case e1000_82576: | |
2d064c06 | 970 | pba = E1000_PBA_64K; |
fa4dfae0 AD |
971 | break; |
972 | case e1000_82575: | |
973 | default: | |
974 | pba = E1000_PBA_34K; | |
975 | break; | |
2d064c06 | 976 | } |
9d5c8243 | 977 | |
2d064c06 AD |
978 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
979 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
980 | /* adjust PBA for jumbo frames */ |
981 | wr32(E1000_PBA, pba); | |
982 | ||
983 | /* To maintain wire speed transmits, the Tx FIFO should be | |
984 | * large enough to accommodate two full transmit packets, | |
985 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
986 | * the Rx FIFO should be large enough to accommodate at least | |
987 | * one full receive packet and is similarly rounded up and | |
988 | * expressed in KB. */ | |
989 | pba = rd32(E1000_PBA); | |
990 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
991 | tx_space = pba >> 16; | |
992 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
993 | pba &= 0xffff; | |
994 | /* the tx fifo also stores 16 bytes of information about the tx | |
995 | * but don't include ethernet FCS because hardware appends it */ | |
996 | min_tx_space = (adapter->max_frame_size + | |
997 | sizeof(struct e1000_tx_desc) - | |
998 | ETH_FCS_LEN) * 2; | |
999 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1000 | min_tx_space >>= 10; | |
1001 | /* software strips receive CRC, so leave room for it */ | |
1002 | min_rx_space = adapter->max_frame_size; | |
1003 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1004 | min_rx_space >>= 10; | |
1005 | ||
1006 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1007 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1008 | * allocation, take space away from current Rx allocation */ | |
1009 | if (tx_space < min_tx_space && | |
1010 | ((min_tx_space - tx_space) < pba)) { | |
1011 | pba = pba - (min_tx_space - tx_space); | |
1012 | ||
1013 | /* if short on rx space, rx wins and must trump tx | |
1014 | * adjustment */ | |
1015 | if (pba < min_rx_space) | |
1016 | pba = min_rx_space; | |
1017 | } | |
2d064c06 | 1018 | wr32(E1000_PBA, pba); |
9d5c8243 | 1019 | } |
9d5c8243 AK |
1020 | |
1021 | /* flow control settings */ | |
1022 | /* The high water mark must be low enough to fit one full frame | |
1023 | * (or the size used for early receive) above it in the Rx FIFO. | |
1024 | * Set it to the lower of: | |
1025 | * - 90% of the Rx FIFO size, or | |
1026 | * - the full Rx FIFO size minus one full frame */ | |
1027 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1028 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1029 | |
2d064c06 AD |
1030 | if (mac->type < e1000_82576) { |
1031 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | |
1032 | fc->low_water = fc->high_water - 8; | |
1033 | } else { | |
1034 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | |
1035 | fc->low_water = fc->high_water - 16; | |
1036 | } | |
9d5c8243 AK |
1037 | fc->pause_time = 0xFFFF; |
1038 | fc->send_xon = 1; | |
1039 | fc->type = fc->original_type; | |
1040 | ||
1041 | /* Allow time for pending master requests to run */ | |
1042 | adapter->hw.mac.ops.reset_hw(&adapter->hw); | |
1043 | wr32(E1000_WUC, 0); | |
1044 | ||
1045 | if (adapter->hw.mac.ops.init_hw(&adapter->hw)) | |
1046 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
1047 | ||
1048 | igb_update_mng_vlan(adapter); | |
1049 | ||
1050 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1051 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1052 | ||
1053 | igb_reset_adaptive(&adapter->hw); | |
f5f4cf08 | 1054 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
1055 | } |
1056 | ||
2e5c6922 SH |
1057 | static const struct net_device_ops igb_netdev_ops = { |
1058 | .ndo_open = igb_open, | |
1059 | .ndo_stop = igb_close, | |
00829823 | 1060 | .ndo_start_xmit = igb_xmit_frame_adv, |
2e5c6922 SH |
1061 | .ndo_get_stats = igb_get_stats, |
1062 | .ndo_set_multicast_list = igb_set_multi, | |
1063 | .ndo_set_mac_address = igb_set_mac, | |
1064 | .ndo_change_mtu = igb_change_mtu, | |
1065 | .ndo_do_ioctl = igb_ioctl, | |
1066 | .ndo_tx_timeout = igb_tx_timeout, | |
1067 | .ndo_validate_addr = eth_validate_addr, | |
1068 | .ndo_vlan_rx_register = igb_vlan_rx_register, | |
1069 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, | |
1070 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
1071 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1072 | .ndo_poll_controller = igb_netpoll, | |
1073 | #endif | |
1074 | }; | |
1075 | ||
9d5c8243 AK |
1076 | /** |
1077 | * igb_probe - Device Initialization Routine | |
1078 | * @pdev: PCI device information struct | |
1079 | * @ent: entry in igb_pci_tbl | |
1080 | * | |
1081 | * Returns 0 on success, negative on failure | |
1082 | * | |
1083 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1084 | * The OS initialization, configuring of the adapter private structure, | |
1085 | * and a hardware reset occur. | |
1086 | **/ | |
1087 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1088 | const struct pci_device_id *ent) | |
1089 | { | |
1090 | struct net_device *netdev; | |
1091 | struct igb_adapter *adapter; | |
1092 | struct e1000_hw *hw; | |
c54106bb | 1093 | struct pci_dev *us_dev; |
9d5c8243 AK |
1094 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1095 | unsigned long mmio_start, mmio_len; | |
450c87c8 | 1096 | int err, pci_using_dac, pos; |
c54106bb | 1097 | u16 eeprom_data = 0, state = 0; |
9d5c8243 AK |
1098 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
1099 | u32 part_num; | |
1100 | ||
aed5dec3 | 1101 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1102 | if (err) |
1103 | return err; | |
1104 | ||
1105 | pci_using_dac = 0; | |
1106 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
1107 | if (!err) { | |
1108 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1109 | if (!err) | |
1110 | pci_using_dac = 1; | |
1111 | } else { | |
1112 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1113 | if (err) { | |
1114 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1115 | if (err) { | |
1116 | dev_err(&pdev->dev, "No usable DMA " | |
1117 | "configuration, aborting\n"); | |
1118 | goto err_dma; | |
1119 | } | |
1120 | } | |
1121 | } | |
1122 | ||
c54106bb AD |
1123 | /* 82575 requires that the pci-e link partner disable the L0s state */ |
1124 | switch (pdev->device) { | |
1125 | case E1000_DEV_ID_82575EB_COPPER: | |
1126 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
1127 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1128 | us_dev = pdev->bus->self; | |
1129 | pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP); | |
1130 | if (pos) { | |
1131 | pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL, | |
1132 | &state); | |
1133 | state &= ~PCIE_LINK_STATE_L0S; | |
1134 | pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL, | |
1135 | state); | |
ac450208 BH |
1136 | dev_info(&pdev->dev, |
1137 | "Disabling ASPM L0s upstream switch port %s\n", | |
1138 | pci_name(us_dev)); | |
c54106bb AD |
1139 | } |
1140 | default: | |
1141 | break; | |
1142 | } | |
1143 | ||
aed5dec3 AD |
1144 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1145 | IORESOURCE_MEM), | |
1146 | igb_driver_name); | |
9d5c8243 AK |
1147 | if (err) |
1148 | goto err_pci_reg; | |
1149 | ||
ea943d41 JK |
1150 | err = pci_enable_pcie_error_reporting(pdev); |
1151 | if (err) { | |
1152 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
1153 | "0x%x\n", err); | |
1154 | /* non-fatal, continue */ | |
1155 | } | |
40a914fa | 1156 | |
9d5c8243 | 1157 | pci_set_master(pdev); |
c682fc23 | 1158 | pci_save_state(pdev); |
9d5c8243 AK |
1159 | |
1160 | err = -ENOMEM; | |
661086df | 1161 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
1162 | if (!netdev) |
1163 | goto err_alloc_etherdev; | |
1164 | ||
1165 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1166 | ||
1167 | pci_set_drvdata(pdev, netdev); | |
1168 | adapter = netdev_priv(netdev); | |
1169 | adapter->netdev = netdev; | |
1170 | adapter->pdev = pdev; | |
1171 | hw = &adapter->hw; | |
1172 | hw->back = adapter; | |
1173 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
1174 | ||
1175 | mmio_start = pci_resource_start(pdev, 0); | |
1176 | mmio_len = pci_resource_len(pdev, 0); | |
1177 | ||
1178 | err = -EIO; | |
28b0759c AD |
1179 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1180 | if (!hw->hw_addr) | |
9d5c8243 AK |
1181 | goto err_ioremap; |
1182 | ||
2e5c6922 | 1183 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1184 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1185 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1186 | |
1187 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1188 | ||
1189 | netdev->mem_start = mmio_start; | |
1190 | netdev->mem_end = mmio_start + mmio_len; | |
1191 | ||
9d5c8243 AK |
1192 | /* PCI config space info */ |
1193 | hw->vendor_id = pdev->vendor; | |
1194 | hw->device_id = pdev->device; | |
1195 | hw->revision_id = pdev->revision; | |
1196 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1197 | hw->subsystem_device_id = pdev->subsystem_device; | |
1198 | ||
1199 | /* setup the private structure */ | |
1200 | hw->back = adapter; | |
1201 | /* Copy the default MAC, PHY and NVM function pointers */ | |
1202 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1203 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1204 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1205 | /* Initialize skew-specific constants */ | |
1206 | err = ei->get_invariants(hw); | |
1207 | if (err) | |
450c87c8 | 1208 | goto err_sw_init; |
9d5c8243 | 1209 | |
450c87c8 | 1210 | /* setup the private structure */ |
9d5c8243 AK |
1211 | err = igb_sw_init(adapter); |
1212 | if (err) | |
1213 | goto err_sw_init; | |
1214 | ||
1215 | igb_get_bus_info_pcie(hw); | |
1216 | ||
7dfc16fa AD |
1217 | /* set flags */ |
1218 | switch (hw->mac.type) { | |
7dfc16fa | 1219 | case e1000_82575: |
7dfc16fa AD |
1220 | adapter->flags |= IGB_FLAG_NEED_CTX_IDX; |
1221 | break; | |
bbd98fe4 | 1222 | case e1000_82576: |
7dfc16fa AD |
1223 | default: |
1224 | break; | |
1225 | } | |
1226 | ||
9d5c8243 AK |
1227 | hw->phy.autoneg_wait_to_complete = false; |
1228 | hw->mac.adaptive_ifs = true; | |
1229 | ||
1230 | /* Copper options */ | |
1231 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1232 | hw->phy.mdix = AUTO_ALL_MODES; | |
1233 | hw->phy.disable_polarity_correction = false; | |
1234 | hw->phy.ms_type = e1000_ms_hw_default; | |
1235 | } | |
1236 | ||
1237 | if (igb_check_reset_block(hw)) | |
1238 | dev_info(&pdev->dev, | |
1239 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1240 | ||
1241 | netdev->features = NETIF_F_SG | | |
7d8eb29e | 1242 | NETIF_F_IP_CSUM | |
9d5c8243 AK |
1243 | NETIF_F_HW_VLAN_TX | |
1244 | NETIF_F_HW_VLAN_RX | | |
1245 | NETIF_F_HW_VLAN_FILTER; | |
1246 | ||
7d8eb29e | 1247 | netdev->features |= NETIF_F_IPV6_CSUM; |
9d5c8243 | 1248 | netdev->features |= NETIF_F_TSO; |
9d5c8243 | 1249 | netdev->features |= NETIF_F_TSO6; |
48f29ffc | 1250 | |
d3352520 | 1251 | #ifdef CONFIG_IGB_LRO |
5c0999b7 | 1252 | netdev->features |= NETIF_F_GRO; |
d3352520 AD |
1253 | #endif |
1254 | ||
48f29ffc JK |
1255 | netdev->vlan_features |= NETIF_F_TSO; |
1256 | netdev->vlan_features |= NETIF_F_TSO6; | |
7d8eb29e | 1257 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
48f29ffc JK |
1258 | netdev->vlan_features |= NETIF_F_SG; |
1259 | ||
9d5c8243 AK |
1260 | if (pci_using_dac) |
1261 | netdev->features |= NETIF_F_HIGHDMA; | |
1262 | ||
9d5c8243 AK |
1263 | adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw); |
1264 | ||
1265 | /* before reading the NVM, reset the controller to put the device in a | |
1266 | * known good starting state */ | |
1267 | hw->mac.ops.reset_hw(hw); | |
1268 | ||
1269 | /* make sure the NVM is good */ | |
1270 | if (igb_validate_nvm_checksum(hw) < 0) { | |
1271 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
1272 | err = -EIO; | |
1273 | goto err_eeprom; | |
1274 | } | |
1275 | ||
1276 | /* copy the MAC address out of the NVM */ | |
1277 | if (hw->mac.ops.read_mac_addr(hw)) | |
1278 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1279 | ||
1280 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1281 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1282 | ||
1283 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1284 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1285 | err = -EIO; | |
1286 | goto err_eeprom; | |
1287 | } | |
1288 | ||
1289 | init_timer(&adapter->watchdog_timer); | |
1290 | adapter->watchdog_timer.function = &igb_watchdog; | |
1291 | adapter->watchdog_timer.data = (unsigned long) adapter; | |
1292 | ||
1293 | init_timer(&adapter->phy_info_timer); | |
1294 | adapter->phy_info_timer.function = &igb_update_phy_info; | |
1295 | adapter->phy_info_timer.data = (unsigned long) adapter; | |
1296 | ||
1297 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
1298 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
1299 | ||
450c87c8 | 1300 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
1301 | adapter->fc_autoneg = true; |
1302 | hw->mac.autoneg = true; | |
1303 | hw->phy.autoneg_advertised = 0x2f; | |
1304 | ||
1305 | hw->fc.original_type = e1000_fc_default; | |
1306 | hw->fc.type = e1000_fc_default; | |
1307 | ||
cbd347ad | 1308 | adapter->itr_setting = IGB_DEFAULT_ITR; |
9d5c8243 AK |
1309 | adapter->itr = IGB_START_ITR; |
1310 | ||
1311 | igb_validate_mdi_setting(hw); | |
1312 | ||
1313 | adapter->rx_csum = 1; | |
1314 | ||
1315 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, | |
1316 | * enable the ACPI Magic Packet filter | |
1317 | */ | |
1318 | ||
1319 | if (hw->bus.func == 0 || | |
1320 | hw->device_id == E1000_DEV_ID_82575EB_COPPER) | |
312c75ae | 1321 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
9d5c8243 AK |
1322 | |
1323 | if (eeprom_data & eeprom_apme_mask) | |
1324 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
1325 | ||
1326 | /* now that we have the eeprom settings, apply the special cases where | |
1327 | * the eeprom may be wrong or the board simply won't support wake on | |
1328 | * lan on a particular port */ | |
1329 | switch (pdev->device) { | |
1330 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1331 | adapter->eeprom_wol = 0; | |
1332 | break; | |
1333 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1334 | case E1000_DEV_ID_82576_FIBER: |
1335 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1336 | /* Wake events only supported on port A for dual fiber |
1337 | * regardless of eeprom setting */ | |
1338 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
1339 | adapter->eeprom_wol = 0; | |
1340 | break; | |
1341 | } | |
1342 | ||
1343 | /* initialize the wol settings based on the eeprom settings */ | |
1344 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 1345 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
1346 | |
1347 | /* reset the hardware with the new settings */ | |
1348 | igb_reset(adapter); | |
1349 | ||
1350 | /* let the f/w know that the h/w is now under the control of the | |
1351 | * driver. */ | |
1352 | igb_get_hw_control(adapter); | |
1353 | ||
1354 | /* tell the stack to leave us alone until igb_open() is called */ | |
1355 | netif_carrier_off(netdev); | |
fd2ea0a7 | 1356 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1357 | |
1358 | strcpy(netdev->name, "eth%d"); | |
1359 | err = register_netdev(netdev); | |
1360 | if (err) | |
1361 | goto err_register; | |
1362 | ||
421e02f0 | 1363 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 1364 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 1365 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
1366 | dev_info(&pdev->dev, "DCA enabled\n"); |
1367 | /* Always use CB2 mode, difference is masked | |
1368 | * in the CB driver. */ | |
cbd347ad | 1369 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
fe4506b6 JC |
1370 | igb_setup_dca(adapter); |
1371 | } | |
1372 | #endif | |
1373 | ||
38c845c7 PO |
1374 | /* |
1375 | * Initialize hardware timer: we keep it running just in case | |
1376 | * that some program needs it later on. | |
1377 | */ | |
1378 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
1379 | adapter->cycles.read = igb_read_clock; | |
1380 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
1381 | adapter->cycles.mult = 1; | |
1382 | adapter->cycles.shift = IGB_TSYNC_SHIFT; | |
1383 | wr32(E1000_TIMINCA, | |
1384 | (1<<24) | | |
1385 | IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE); | |
1386 | #if 0 | |
1387 | /* | |
1388 | * Avoid rollover while we initialize by resetting the time counter. | |
1389 | */ | |
1390 | wr32(E1000_SYSTIML, 0x00000000); | |
1391 | wr32(E1000_SYSTIMH, 0x00000000); | |
1392 | #else | |
1393 | /* | |
1394 | * Set registers so that rollover occurs soon to test this. | |
1395 | */ | |
1396 | wr32(E1000_SYSTIML, 0x00000000); | |
1397 | wr32(E1000_SYSTIMH, 0xFF800000); | |
1398 | #endif | |
1399 | wrfl(); | |
1400 | timecounter_init(&adapter->clock, | |
1401 | &adapter->cycles, | |
1402 | ktime_to_ns(ktime_get_real())); | |
1403 | ||
33af6bcc PO |
1404 | /* |
1405 | * Synchronize our NIC clock against system wall clock. NIC | |
1406 | * time stamp reading requires ~3us per sample, each sample | |
1407 | * was pretty stable even under load => only require 10 | |
1408 | * samples for each offset comparison. | |
1409 | */ | |
1410 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
1411 | adapter->compare.source = &adapter->clock; | |
1412 | adapter->compare.target = ktime_get_real; | |
1413 | adapter->compare.num_samples = 10; | |
1414 | timecompare_update(&adapter->compare, 0); | |
1415 | ||
38c845c7 PO |
1416 | #ifdef DEBUG |
1417 | { | |
1418 | char buffer[160]; | |
1419 | printk(KERN_DEBUG | |
1420 | "igb: %s: hw %p initialized timer\n", | |
1421 | igb_get_time_str(adapter, buffer), | |
1422 | &adapter->hw); | |
1423 | } | |
1424 | #endif | |
1425 | ||
9d5c8243 AK |
1426 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1427 | /* print bus type/speed/width info */ | |
7c510e4b | 1428 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 AK |
1429 | netdev->name, |
1430 | ((hw->bus.speed == e1000_bus_speed_2500) | |
1431 | ? "2.5Gb/s" : "unknown"), | |
1432 | ((hw->bus.width == e1000_bus_width_pcie_x4) | |
1433 | ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1) | |
1434 | ? "Width x1" : "unknown"), | |
7c510e4b | 1435 | netdev->dev_addr); |
9d5c8243 AK |
1436 | |
1437 | igb_read_part_num(hw, &part_num); | |
1438 | dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, | |
1439 | (part_num >> 8), (part_num & 0xff)); | |
1440 | ||
1441 | dev_info(&pdev->dev, | |
1442 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
1443 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 1444 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 AK |
1445 | adapter->num_rx_queues, adapter->num_tx_queues); |
1446 | ||
9d5c8243 AK |
1447 | return 0; |
1448 | ||
1449 | err_register: | |
1450 | igb_release_hw_control(adapter); | |
1451 | err_eeprom: | |
1452 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 1453 | igb_reset_phy(hw); |
9d5c8243 AK |
1454 | |
1455 | if (hw->flash_address) | |
1456 | iounmap(hw->flash_address); | |
1457 | ||
a88f10ec | 1458 | igb_free_queues(adapter); |
9d5c8243 | 1459 | err_sw_init: |
9d5c8243 AK |
1460 | iounmap(hw->hw_addr); |
1461 | err_ioremap: | |
1462 | free_netdev(netdev); | |
1463 | err_alloc_etherdev: | |
aed5dec3 AD |
1464 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
1465 | IORESOURCE_MEM)); | |
9d5c8243 AK |
1466 | err_pci_reg: |
1467 | err_dma: | |
1468 | pci_disable_device(pdev); | |
1469 | return err; | |
1470 | } | |
1471 | ||
1472 | /** | |
1473 | * igb_remove - Device Removal Routine | |
1474 | * @pdev: PCI device information struct | |
1475 | * | |
1476 | * igb_remove is called by the PCI subsystem to alert the driver | |
1477 | * that it should release a PCI device. The could be caused by a | |
1478 | * Hot-Plug event, or because the driver is going to be removed from | |
1479 | * memory. | |
1480 | **/ | |
1481 | static void __devexit igb_remove(struct pci_dev *pdev) | |
1482 | { | |
1483 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1484 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 1485 | struct e1000_hw *hw = &adapter->hw; |
ea943d41 | 1486 | int err; |
9d5c8243 AK |
1487 | |
1488 | /* flush_scheduled work may reschedule our watchdog task, so | |
1489 | * explicitly disable watchdog tasks from being rescheduled */ | |
1490 | set_bit(__IGB_DOWN, &adapter->state); | |
1491 | del_timer_sync(&adapter->watchdog_timer); | |
1492 | del_timer_sync(&adapter->phy_info_timer); | |
1493 | ||
1494 | flush_scheduled_work(); | |
1495 | ||
421e02f0 | 1496 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 1497 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
1498 | dev_info(&pdev->dev, "DCA disabled\n"); |
1499 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 1500 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 1501 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
1502 | } |
1503 | #endif | |
1504 | ||
9d5c8243 AK |
1505 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
1506 | * would have already happened in close and is redundant. */ | |
1507 | igb_release_hw_control(adapter); | |
1508 | ||
1509 | unregister_netdev(netdev); | |
1510 | ||
f5f4cf08 AD |
1511 | if (!igb_check_reset_block(&adapter->hw)) |
1512 | igb_reset_phy(&adapter->hw); | |
9d5c8243 | 1513 | |
9d5c8243 AK |
1514 | igb_reset_interrupt_capability(adapter); |
1515 | ||
a88f10ec | 1516 | igb_free_queues(adapter); |
9d5c8243 | 1517 | |
28b0759c AD |
1518 | iounmap(hw->hw_addr); |
1519 | if (hw->flash_address) | |
1520 | iounmap(hw->flash_address); | |
aed5dec3 AD |
1521 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
1522 | IORESOURCE_MEM)); | |
9d5c8243 AK |
1523 | |
1524 | free_netdev(netdev); | |
1525 | ||
ea943d41 JK |
1526 | err = pci_disable_pcie_error_reporting(pdev); |
1527 | if (err) | |
1528 | dev_err(&pdev->dev, | |
1529 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
40a914fa | 1530 | |
9d5c8243 AK |
1531 | pci_disable_device(pdev); |
1532 | } | |
1533 | ||
1534 | /** | |
1535 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
1536 | * @adapter: board private structure to initialize | |
1537 | * | |
1538 | * igb_sw_init initializes the Adapter private data structure. | |
1539 | * Fields are initialized based on PCI device information and | |
1540 | * OS network device settings (MTU size). | |
1541 | **/ | |
1542 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
1543 | { | |
1544 | struct e1000_hw *hw = &adapter->hw; | |
1545 | struct net_device *netdev = adapter->netdev; | |
1546 | struct pci_dev *pdev = adapter->pdev; | |
1547 | ||
1548 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
1549 | ||
68fd9910 AD |
1550 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
1551 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
9d5c8243 AK |
1552 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
1553 | adapter->rx_ps_hdr_size = 0; /* disable packet split */ | |
1554 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
1555 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
1556 | ||
661086df PWJ |
1557 | /* This call may decrease the number of queues depending on |
1558 | * interrupt mode. */ | |
9d5c8243 AK |
1559 | igb_set_interrupt_capability(adapter); |
1560 | ||
1561 | if (igb_alloc_queues(adapter)) { | |
1562 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
1563 | return -ENOMEM; | |
1564 | } | |
1565 | ||
1566 | /* Explicitly disable IRQ since the NIC can be in any state. */ | |
1567 | igb_irq_disable(adapter); | |
1568 | ||
1569 | set_bit(__IGB_DOWN, &adapter->state); | |
1570 | return 0; | |
1571 | } | |
1572 | ||
1573 | /** | |
1574 | * igb_open - Called when a network interface is made active | |
1575 | * @netdev: network interface device structure | |
1576 | * | |
1577 | * Returns 0 on success, negative value on failure | |
1578 | * | |
1579 | * The open entry point is called when a network interface is made | |
1580 | * active by the system (IFF_UP). At this point all resources needed | |
1581 | * for transmit and receive operations are allocated, the interrupt | |
1582 | * handler is registered with the OS, the watchdog timer is started, | |
1583 | * and the stack is notified that the interface is ready. | |
1584 | **/ | |
1585 | static int igb_open(struct net_device *netdev) | |
1586 | { | |
1587 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1588 | struct e1000_hw *hw = &adapter->hw; | |
1589 | int err; | |
1590 | int i; | |
1591 | ||
1592 | /* disallow open during test */ | |
1593 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
1594 | return -EBUSY; | |
1595 | ||
1596 | /* allocate transmit descriptors */ | |
1597 | err = igb_setup_all_tx_resources(adapter); | |
1598 | if (err) | |
1599 | goto err_setup_tx; | |
1600 | ||
1601 | /* allocate receive descriptors */ | |
1602 | err = igb_setup_all_rx_resources(adapter); | |
1603 | if (err) | |
1604 | goto err_setup_rx; | |
1605 | ||
1606 | /* e1000_power_up_phy(adapter); */ | |
1607 | ||
1608 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1609 | if ((adapter->hw.mng_cookie.status & | |
1610 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) | |
1611 | igb_update_mng_vlan(adapter); | |
1612 | ||
1613 | /* before we allocate an interrupt, we must be ready to handle it. | |
1614 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
1615 | * as soon as we call pci_request_irq, so we have to setup our | |
1616 | * clean_rx handler before we do so. */ | |
1617 | igb_configure(adapter); | |
1618 | ||
1619 | err = igb_request_irq(adapter); | |
1620 | if (err) | |
1621 | goto err_req_irq; | |
1622 | ||
1623 | /* From here on the code is the same as igb_up() */ | |
1624 | clear_bit(__IGB_DOWN, &adapter->state); | |
1625 | ||
844290e5 PW |
1626 | for (i = 0; i < adapter->num_rx_queues; i++) |
1627 | napi_enable(&adapter->rx_ring[i].napi); | |
9d5c8243 AK |
1628 | |
1629 | /* Clear any pending interrupts. */ | |
1630 | rd32(E1000_ICR); | |
844290e5 PW |
1631 | |
1632 | igb_irq_enable(adapter); | |
1633 | ||
d55b53ff JK |
1634 | netif_tx_start_all_queues(netdev); |
1635 | ||
9d5c8243 AK |
1636 | /* Fire a link status change interrupt to start the watchdog. */ |
1637 | wr32(E1000_ICS, E1000_ICS_LSC); | |
1638 | ||
1639 | return 0; | |
1640 | ||
1641 | err_req_irq: | |
1642 | igb_release_hw_control(adapter); | |
1643 | /* e1000_power_down_phy(adapter); */ | |
1644 | igb_free_all_rx_resources(adapter); | |
1645 | err_setup_rx: | |
1646 | igb_free_all_tx_resources(adapter); | |
1647 | err_setup_tx: | |
1648 | igb_reset(adapter); | |
1649 | ||
1650 | return err; | |
1651 | } | |
1652 | ||
1653 | /** | |
1654 | * igb_close - Disables a network interface | |
1655 | * @netdev: network interface device structure | |
1656 | * | |
1657 | * Returns 0, this is not allowed to fail | |
1658 | * | |
1659 | * The close entry point is called when an interface is de-activated | |
1660 | * by the OS. The hardware is still under the driver's control, but | |
1661 | * needs to be disabled. A global MAC reset is issued to stop the | |
1662 | * hardware, and all transmit and receive resources are freed. | |
1663 | **/ | |
1664 | static int igb_close(struct net_device *netdev) | |
1665 | { | |
1666 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1667 | ||
1668 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
1669 | igb_down(adapter); | |
1670 | ||
1671 | igb_free_irq(adapter); | |
1672 | ||
1673 | igb_free_all_tx_resources(adapter); | |
1674 | igb_free_all_rx_resources(adapter); | |
1675 | ||
1676 | /* kill manageability vlan ID if supported, but not if a vlan with | |
1677 | * the same ID is registered on the host OS (let 8021q kill it) */ | |
1678 | if ((adapter->hw.mng_cookie.status & | |
1679 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
1680 | !(adapter->vlgrp && | |
1681 | vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) | |
1682 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | /** | |
1688 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
1689 | * @adapter: board private structure | |
1690 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
1691 | * | |
1692 | * Return 0 on success, negative on failure | |
1693 | **/ | |
9d5c8243 AK |
1694 | int igb_setup_tx_resources(struct igb_adapter *adapter, |
1695 | struct igb_ring *tx_ring) | |
1696 | { | |
1697 | struct pci_dev *pdev = adapter->pdev; | |
1698 | int size; | |
1699 | ||
1700 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
1701 | tx_ring->buffer_info = vmalloc(size); | |
1702 | if (!tx_ring->buffer_info) | |
1703 | goto err; | |
1704 | memset(tx_ring->buffer_info, 0, size); | |
1705 | ||
1706 | /* round up to nearest 4K */ | |
0e014cb1 | 1707 | tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); |
9d5c8243 AK |
1708 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1709 | ||
1710 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, | |
1711 | &tx_ring->dma); | |
1712 | ||
1713 | if (!tx_ring->desc) | |
1714 | goto err; | |
1715 | ||
1716 | tx_ring->adapter = adapter; | |
1717 | tx_ring->next_to_use = 0; | |
1718 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
1719 | return 0; |
1720 | ||
1721 | err: | |
1722 | vfree(tx_ring->buffer_info); | |
1723 | dev_err(&adapter->pdev->dev, | |
1724 | "Unable to allocate memory for the transmit descriptor ring\n"); | |
1725 | return -ENOMEM; | |
1726 | } | |
1727 | ||
1728 | /** | |
1729 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
1730 | * (Descriptors) for all queues | |
1731 | * @adapter: board private structure | |
1732 | * | |
1733 | * Return 0 on success, negative on failure | |
1734 | **/ | |
1735 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
1736 | { | |
1737 | int i, err = 0; | |
661086df | 1738 | int r_idx; |
9d5c8243 AK |
1739 | |
1740 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1741 | err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
1742 | if (err) { | |
1743 | dev_err(&adapter->pdev->dev, | |
1744 | "Allocation for Tx Queue %u failed\n", i); | |
1745 | for (i--; i >= 0; i--) | |
3b644cf6 | 1746 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
1747 | break; |
1748 | } | |
1749 | } | |
1750 | ||
661086df PWJ |
1751 | for (i = 0; i < IGB_MAX_TX_QUEUES; i++) { |
1752 | r_idx = i % adapter->num_tx_queues; | |
1753 | adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; | |
eebbbdba | 1754 | } |
9d5c8243 AK |
1755 | return err; |
1756 | } | |
1757 | ||
1758 | /** | |
1759 | * igb_configure_tx - Configure transmit Unit after Reset | |
1760 | * @adapter: board private structure | |
1761 | * | |
1762 | * Configure the Tx unit of the MAC after a reset. | |
1763 | **/ | |
1764 | static void igb_configure_tx(struct igb_adapter *adapter) | |
1765 | { | |
0e014cb1 | 1766 | u64 tdba; |
9d5c8243 AK |
1767 | struct e1000_hw *hw = &adapter->hw; |
1768 | u32 tctl; | |
1769 | u32 txdctl, txctrl; | |
26bc19ec | 1770 | int i, j; |
9d5c8243 AK |
1771 | |
1772 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
73cd78f1 | 1773 | struct igb_ring *ring = &adapter->tx_ring[i]; |
26bc19ec AD |
1774 | j = ring->reg_idx; |
1775 | wr32(E1000_TDLEN(j), | |
73cd78f1 | 1776 | ring->count * sizeof(struct e1000_tx_desc)); |
9d5c8243 | 1777 | tdba = ring->dma; |
26bc19ec | 1778 | wr32(E1000_TDBAL(j), |
73cd78f1 | 1779 | tdba & 0x00000000ffffffffULL); |
26bc19ec | 1780 | wr32(E1000_TDBAH(j), tdba >> 32); |
9d5c8243 | 1781 | |
26bc19ec AD |
1782 | ring->head = E1000_TDH(j); |
1783 | ring->tail = E1000_TDT(j); | |
9d5c8243 AK |
1784 | writel(0, hw->hw_addr + ring->tail); |
1785 | writel(0, hw->hw_addr + ring->head); | |
26bc19ec | 1786 | txdctl = rd32(E1000_TXDCTL(j)); |
9d5c8243 | 1787 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; |
26bc19ec | 1788 | wr32(E1000_TXDCTL(j), txdctl); |
9d5c8243 AK |
1789 | |
1790 | /* Turn off Relaxed Ordering on head write-backs. The | |
1791 | * writebacks MUST be delivered in order or it will | |
1792 | * completely screw up our bookeeping. | |
1793 | */ | |
26bc19ec | 1794 | txctrl = rd32(E1000_DCA_TXCTRL(j)); |
9d5c8243 | 1795 | txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; |
26bc19ec | 1796 | wr32(E1000_DCA_TXCTRL(j), txctrl); |
9d5c8243 AK |
1797 | } |
1798 | ||
9d5c8243 AK |
1799 | /* Use the default values for the Tx Inter Packet Gap (IPG) timer */ |
1800 | ||
1801 | /* Program the Transmit Control Register */ | |
1802 | ||
1803 | tctl = rd32(E1000_TCTL); | |
1804 | tctl &= ~E1000_TCTL_CT; | |
1805 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
1806 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
1807 | ||
1808 | igb_config_collision_dist(hw); | |
1809 | ||
1810 | /* Setup Transmit Descriptor Settings for eop descriptor */ | |
1811 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS; | |
1812 | ||
1813 | /* Enable transmits */ | |
1814 | tctl |= E1000_TCTL_EN; | |
1815 | ||
1816 | wr32(E1000_TCTL, tctl); | |
1817 | } | |
1818 | ||
1819 | /** | |
1820 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
1821 | * @adapter: board private structure | |
1822 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1823 | * | |
1824 | * Returns 0 on success, negative on failure | |
1825 | **/ | |
9d5c8243 AK |
1826 | int igb_setup_rx_resources(struct igb_adapter *adapter, |
1827 | struct igb_ring *rx_ring) | |
1828 | { | |
1829 | struct pci_dev *pdev = adapter->pdev; | |
1830 | int size, desc_len; | |
1831 | ||
1832 | size = sizeof(struct igb_buffer) * rx_ring->count; | |
1833 | rx_ring->buffer_info = vmalloc(size); | |
1834 | if (!rx_ring->buffer_info) | |
1835 | goto err; | |
1836 | memset(rx_ring->buffer_info, 0, size); | |
1837 | ||
1838 | desc_len = sizeof(union e1000_adv_rx_desc); | |
1839 | ||
1840 | /* Round up to nearest 4K */ | |
1841 | rx_ring->size = rx_ring->count * desc_len; | |
1842 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
1843 | ||
1844 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, | |
1845 | &rx_ring->dma); | |
1846 | ||
1847 | if (!rx_ring->desc) | |
1848 | goto err; | |
1849 | ||
1850 | rx_ring->next_to_clean = 0; | |
1851 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
1852 | |
1853 | rx_ring->adapter = adapter; | |
9d5c8243 AK |
1854 | |
1855 | return 0; | |
1856 | ||
1857 | err: | |
1858 | vfree(rx_ring->buffer_info); | |
1859 | dev_err(&adapter->pdev->dev, "Unable to allocate memory for " | |
1860 | "the receive descriptor ring\n"); | |
1861 | return -ENOMEM; | |
1862 | } | |
1863 | ||
1864 | /** | |
1865 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
1866 | * (Descriptors) for all queues | |
1867 | * @adapter: board private structure | |
1868 | * | |
1869 | * Return 0 on success, negative on failure | |
1870 | **/ | |
1871 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
1872 | { | |
1873 | int i, err = 0; | |
1874 | ||
1875 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1876 | err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
1877 | if (err) { | |
1878 | dev_err(&adapter->pdev->dev, | |
1879 | "Allocation for Rx Queue %u failed\n", i); | |
1880 | for (i--; i >= 0; i--) | |
3b644cf6 | 1881 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
1882 | break; |
1883 | } | |
1884 | } | |
1885 | ||
1886 | return err; | |
1887 | } | |
1888 | ||
1889 | /** | |
1890 | * igb_setup_rctl - configure the receive control registers | |
1891 | * @adapter: Board private structure | |
1892 | **/ | |
1893 | static void igb_setup_rctl(struct igb_adapter *adapter) | |
1894 | { | |
1895 | struct e1000_hw *hw = &adapter->hw; | |
1896 | u32 rctl; | |
1897 | u32 srrctl = 0; | |
26bc19ec | 1898 | int i, j; |
9d5c8243 AK |
1899 | |
1900 | rctl = rd32(E1000_RCTL); | |
1901 | ||
1902 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 1903 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 1904 | |
69d728ba | 1905 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 1906 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 1907 | |
87cb7e8c AK |
1908 | /* |
1909 | * enable stripping of CRC. It's unlikely this will break BMC | |
1910 | * redirection as it did with e1000. Newer features require | |
1911 | * that the HW strips the CRC. | |
73cd78f1 | 1912 | */ |
87cb7e8c | 1913 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 1914 | |
9b07f3d3 | 1915 | /* |
ec54d7d6 | 1916 | * disable store bad packets and clear size bits. |
9b07f3d3 | 1917 | */ |
ec54d7d6 | 1918 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 1919 | |
ec54d7d6 | 1920 | /* enable LPE when to prevent packets larger than max_frame_size */ |
9b07f3d3 | 1921 | rctl |= E1000_RCTL_LPE; |
b4557be2 AD |
1922 | |
1923 | /* Setup buffer sizes */ | |
1924 | switch (adapter->rx_buffer_len) { | |
1925 | case IGB_RXBUFFER_256: | |
1926 | rctl |= E1000_RCTL_SZ_256; | |
1927 | break; | |
1928 | case IGB_RXBUFFER_512: | |
1929 | rctl |= E1000_RCTL_SZ_512; | |
1930 | break; | |
1931 | default: | |
1932 | srrctl = ALIGN(adapter->rx_buffer_len, 1024) | |
1933 | >> E1000_SRRCTL_BSIZEPKT_SHIFT; | |
1934 | break; | |
9d5c8243 AK |
1935 | } |
1936 | ||
1937 | /* 82575 and greater support packet-split where the protocol | |
1938 | * header is placed in skb->data and the packet data is | |
1939 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | |
1940 | * In the case of a non-split, skb->data is linearly filled, | |
1941 | * followed by the page buffers. Therefore, skb->data is | |
1942 | * sized to hold the largest protocol header. | |
1943 | */ | |
1944 | /* allocations using alloc_page take too long for regular MTU | |
1945 | * so only enable packet split for jumbo frames */ | |
ec54d7d6 | 1946 | if (adapter->netdev->mtu > ETH_DATA_LEN) { |
9d5c8243 | 1947 | adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; |
bf36c1a0 | 1948 | srrctl |= adapter->rx_ps_hdr_size << |
9d5c8243 | 1949 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
9d5c8243 AK |
1950 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
1951 | } else { | |
1952 | adapter->rx_ps_hdr_size = 0; | |
1953 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1954 | } | |
1955 | ||
26bc19ec AD |
1956 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1957 | j = adapter->rx_ring[i].reg_idx; | |
1958 | wr32(E1000_SRRCTL(j), srrctl); | |
1959 | } | |
9d5c8243 AK |
1960 | |
1961 | wr32(E1000_RCTL, rctl); | |
1962 | } | |
1963 | ||
1964 | /** | |
1965 | * igb_configure_rx - Configure receive Unit after Reset | |
1966 | * @adapter: board private structure | |
1967 | * | |
1968 | * Configure the Rx unit of the MAC after a reset. | |
1969 | **/ | |
1970 | static void igb_configure_rx(struct igb_adapter *adapter) | |
1971 | { | |
1972 | u64 rdba; | |
1973 | struct e1000_hw *hw = &adapter->hw; | |
1974 | u32 rctl, rxcsum; | |
1975 | u32 rxdctl; | |
26bc19ec | 1976 | int i, j; |
9d5c8243 AK |
1977 | |
1978 | /* disable receives while setting up the descriptors */ | |
1979 | rctl = rd32(E1000_RCTL); | |
1980 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1981 | wrfl(); | |
1982 | mdelay(10); | |
1983 | ||
1984 | if (adapter->itr_setting > 3) | |
6eb5a7f1 | 1985 | wr32(E1000_ITR, adapter->itr); |
9d5c8243 AK |
1986 | |
1987 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1988 | * the Base and Length of the Rx Descriptor Ring */ | |
1989 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
73cd78f1 | 1990 | struct igb_ring *ring = &adapter->rx_ring[i]; |
26bc19ec | 1991 | j = ring->reg_idx; |
9d5c8243 | 1992 | rdba = ring->dma; |
26bc19ec | 1993 | wr32(E1000_RDBAL(j), |
73cd78f1 | 1994 | rdba & 0x00000000ffffffffULL); |
26bc19ec AD |
1995 | wr32(E1000_RDBAH(j), rdba >> 32); |
1996 | wr32(E1000_RDLEN(j), | |
73cd78f1 | 1997 | ring->count * sizeof(union e1000_adv_rx_desc)); |
9d5c8243 | 1998 | |
26bc19ec AD |
1999 | ring->head = E1000_RDH(j); |
2000 | ring->tail = E1000_RDT(j); | |
9d5c8243 AK |
2001 | writel(0, hw->hw_addr + ring->tail); |
2002 | writel(0, hw->hw_addr + ring->head); | |
2003 | ||
26bc19ec | 2004 | rxdctl = rd32(E1000_RXDCTL(j)); |
9d5c8243 AK |
2005 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; |
2006 | rxdctl &= 0xFFF00000; | |
2007 | rxdctl |= IGB_RX_PTHRESH; | |
2008 | rxdctl |= IGB_RX_HTHRESH << 8; | |
2009 | rxdctl |= IGB_RX_WTHRESH << 16; | |
26bc19ec | 2010 | wr32(E1000_RXDCTL(j), rxdctl); |
9d5c8243 AK |
2011 | } |
2012 | ||
2013 | if (adapter->num_rx_queues > 1) { | |
2014 | u32 random[10]; | |
2015 | u32 mrqc; | |
2016 | u32 j, shift; | |
2017 | union e1000_reta { | |
2018 | u32 dword; | |
2019 | u8 bytes[4]; | |
2020 | } reta; | |
2021 | ||
2022 | get_random_bytes(&random[0], 40); | |
2023 | ||
2d064c06 AD |
2024 | if (hw->mac.type >= e1000_82576) |
2025 | shift = 0; | |
2026 | else | |
2027 | shift = 6; | |
9d5c8243 AK |
2028 | for (j = 0; j < (32 * 4); j++) { |
2029 | reta.bytes[j & 3] = | |
26bc19ec | 2030 | adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift; |
9d5c8243 AK |
2031 | if ((j & 3) == 3) |
2032 | writel(reta.dword, | |
2033 | hw->hw_addr + E1000_RETA(0) + (j & ~3)); | |
2034 | } | |
2035 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | |
2036 | ||
2037 | /* Fill out hash function seeds */ | |
2038 | for (j = 0; j < 10; j++) | |
2039 | array_wr32(E1000_RSSRK(0), j, random[j]); | |
2040 | ||
2041 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | |
2042 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | |
2043 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | |
2044 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | |
2045 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | |
2046 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | |
2047 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | |
2048 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
2049 | ||
2050 | ||
2051 | wr32(E1000_MRQC, mrqc); | |
2052 | ||
2053 | /* Multiqueue and raw packet checksumming are mutually | |
2054 | * exclusive. Note that this not the same as TCP/IP | |
2055 | * checksumming, which works fine. */ | |
2056 | rxcsum = rd32(E1000_RXCSUM); | |
2057 | rxcsum |= E1000_RXCSUM_PCSD; | |
2058 | wr32(E1000_RXCSUM, rxcsum); | |
2059 | } else { | |
2060 | /* Enable Receive Checksum Offload for TCP and UDP */ | |
2061 | rxcsum = rd32(E1000_RXCSUM); | |
56fbbb4e AD |
2062 | if (adapter->rx_csum) |
2063 | rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE; | |
2064 | else | |
2065 | rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE); | |
2066 | ||
9d5c8243 AK |
2067 | wr32(E1000_RXCSUM, rxcsum); |
2068 | } | |
2069 | ||
2070 | if (adapter->vlgrp) | |
2071 | wr32(E1000_RLPML, | |
2072 | adapter->max_frame_size + VLAN_TAG_SIZE); | |
2073 | else | |
2074 | wr32(E1000_RLPML, adapter->max_frame_size); | |
2075 | ||
2076 | /* Enable Receives */ | |
2077 | wr32(E1000_RCTL, rctl); | |
2078 | } | |
2079 | ||
2080 | /** | |
2081 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
2082 | * @tx_ring: Tx descriptor ring for a specific queue |
2083 | * | |
2084 | * Free all transmit software resources | |
2085 | **/ | |
68fd9910 | 2086 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2087 | { |
3b644cf6 | 2088 | struct pci_dev *pdev = tx_ring->adapter->pdev; |
9d5c8243 | 2089 | |
3b644cf6 | 2090 | igb_clean_tx_ring(tx_ring); |
9d5c8243 AK |
2091 | |
2092 | vfree(tx_ring->buffer_info); | |
2093 | tx_ring->buffer_info = NULL; | |
2094 | ||
2095 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
2096 | ||
2097 | tx_ring->desc = NULL; | |
2098 | } | |
2099 | ||
2100 | /** | |
2101 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
2102 | * @adapter: board private structure | |
2103 | * | |
2104 | * Free all transmit software resources | |
2105 | **/ | |
2106 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
2107 | { | |
2108 | int i; | |
2109 | ||
2110 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2111 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
2112 | } |
2113 | ||
2114 | static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, | |
2115 | struct igb_buffer *buffer_info) | |
2116 | { | |
2117 | if (buffer_info->dma) { | |
2118 | pci_unmap_page(adapter->pdev, | |
2119 | buffer_info->dma, | |
2120 | buffer_info->length, | |
2121 | PCI_DMA_TODEVICE); | |
2122 | buffer_info->dma = 0; | |
2123 | } | |
2124 | if (buffer_info->skb) { | |
2125 | dev_kfree_skb_any(buffer_info->skb); | |
2126 | buffer_info->skb = NULL; | |
2127 | } | |
2128 | buffer_info->time_stamp = 0; | |
73cd78f1 | 2129 | buffer_info->next_to_watch = 0; |
9d5c8243 AK |
2130 | /* buffer_info must be completely set up in the transmit path */ |
2131 | } | |
2132 | ||
2133 | /** | |
2134 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
2135 | * @tx_ring: ring to be cleaned |
2136 | **/ | |
3b644cf6 | 2137 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 2138 | { |
3b644cf6 | 2139 | struct igb_adapter *adapter = tx_ring->adapter; |
9d5c8243 AK |
2140 | struct igb_buffer *buffer_info; |
2141 | unsigned long size; | |
2142 | unsigned int i; | |
2143 | ||
2144 | if (!tx_ring->buffer_info) | |
2145 | return; | |
2146 | /* Free all the Tx ring sk_buffs */ | |
2147 | ||
2148 | for (i = 0; i < tx_ring->count; i++) { | |
2149 | buffer_info = &tx_ring->buffer_info[i]; | |
2150 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
2151 | } | |
2152 | ||
2153 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2154 | memset(tx_ring->buffer_info, 0, size); | |
2155 | ||
2156 | /* Zero out the descriptor ring */ | |
2157 | ||
2158 | memset(tx_ring->desc, 0, tx_ring->size); | |
2159 | ||
2160 | tx_ring->next_to_use = 0; | |
2161 | tx_ring->next_to_clean = 0; | |
2162 | ||
2163 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2164 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2165 | } | |
2166 | ||
2167 | /** | |
2168 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
2169 | * @adapter: board private structure | |
2170 | **/ | |
2171 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
2172 | { | |
2173 | int i; | |
2174 | ||
2175 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2176 | igb_clean_tx_ring(&adapter->tx_ring[i]); |
9d5c8243 AK |
2177 | } |
2178 | ||
2179 | /** | |
2180 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
2181 | * @rx_ring: ring to clean the resources from |
2182 | * | |
2183 | * Free all receive software resources | |
2184 | **/ | |
68fd9910 | 2185 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2186 | { |
3b644cf6 | 2187 | struct pci_dev *pdev = rx_ring->adapter->pdev; |
9d5c8243 | 2188 | |
3b644cf6 | 2189 | igb_clean_rx_ring(rx_ring); |
9d5c8243 AK |
2190 | |
2191 | vfree(rx_ring->buffer_info); | |
2192 | rx_ring->buffer_info = NULL; | |
2193 | ||
2194 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
2195 | ||
2196 | rx_ring->desc = NULL; | |
2197 | } | |
2198 | ||
2199 | /** | |
2200 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
2201 | * @adapter: board private structure | |
2202 | * | |
2203 | * Free all receive software resources | |
2204 | **/ | |
2205 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
2206 | { | |
2207 | int i; | |
2208 | ||
2209 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2210 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
2211 | } |
2212 | ||
2213 | /** | |
2214 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
2215 | * @rx_ring: ring to free buffers from |
2216 | **/ | |
3b644cf6 | 2217 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 2218 | { |
3b644cf6 | 2219 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
2220 | struct igb_buffer *buffer_info; |
2221 | struct pci_dev *pdev = adapter->pdev; | |
2222 | unsigned long size; | |
2223 | unsigned int i; | |
2224 | ||
2225 | if (!rx_ring->buffer_info) | |
2226 | return; | |
2227 | /* Free all the Rx ring sk_buffs */ | |
2228 | for (i = 0; i < rx_ring->count; i++) { | |
2229 | buffer_info = &rx_ring->buffer_info[i]; | |
2230 | if (buffer_info->dma) { | |
2231 | if (adapter->rx_ps_hdr_size) | |
2232 | pci_unmap_single(pdev, buffer_info->dma, | |
2233 | adapter->rx_ps_hdr_size, | |
2234 | PCI_DMA_FROMDEVICE); | |
2235 | else | |
2236 | pci_unmap_single(pdev, buffer_info->dma, | |
2237 | adapter->rx_buffer_len, | |
2238 | PCI_DMA_FROMDEVICE); | |
2239 | buffer_info->dma = 0; | |
2240 | } | |
2241 | ||
2242 | if (buffer_info->skb) { | |
2243 | dev_kfree_skb(buffer_info->skb); | |
2244 | buffer_info->skb = NULL; | |
2245 | } | |
2246 | if (buffer_info->page) { | |
bf36c1a0 AD |
2247 | if (buffer_info->page_dma) |
2248 | pci_unmap_page(pdev, buffer_info->page_dma, | |
2249 | PAGE_SIZE / 2, | |
2250 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
2251 | put_page(buffer_info->page); |
2252 | buffer_info->page = NULL; | |
2253 | buffer_info->page_dma = 0; | |
bf36c1a0 | 2254 | buffer_info->page_offset = 0; |
9d5c8243 AK |
2255 | } |
2256 | } | |
2257 | ||
9d5c8243 AK |
2258 | size = sizeof(struct igb_buffer) * rx_ring->count; |
2259 | memset(rx_ring->buffer_info, 0, size); | |
2260 | ||
2261 | /* Zero out the descriptor ring */ | |
2262 | memset(rx_ring->desc, 0, rx_ring->size); | |
2263 | ||
2264 | rx_ring->next_to_clean = 0; | |
2265 | rx_ring->next_to_use = 0; | |
2266 | ||
2267 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2268 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2269 | } | |
2270 | ||
2271 | /** | |
2272 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
2273 | * @adapter: board private structure | |
2274 | **/ | |
2275 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
2276 | { | |
2277 | int i; | |
2278 | ||
2279 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2280 | igb_clean_rx_ring(&adapter->rx_ring[i]); |
9d5c8243 AK |
2281 | } |
2282 | ||
2283 | /** | |
2284 | * igb_set_mac - Change the Ethernet Address of the NIC | |
2285 | * @netdev: network interface device structure | |
2286 | * @p: pointer to an address structure | |
2287 | * | |
2288 | * Returns 0 on success, negative on failure | |
2289 | **/ | |
2290 | static int igb_set_mac(struct net_device *netdev, void *p) | |
2291 | { | |
2292 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 2293 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
2294 | struct sockaddr *addr = p; |
2295 | ||
2296 | if (!is_valid_ether_addr(addr->sa_data)) | |
2297 | return -EADDRNOTAVAIL; | |
2298 | ||
2299 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 2300 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 2301 | |
28b0759c | 2302 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
9d5c8243 AK |
2303 | |
2304 | return 0; | |
2305 | } | |
2306 | ||
2307 | /** | |
2308 | * igb_set_multi - Multicast and Promiscuous mode set | |
2309 | * @netdev: network interface device structure | |
2310 | * | |
2311 | * The set_multi entry point is called whenever the multicast address | |
2312 | * list or the network interface flags are updated. This routine is | |
2313 | * responsible for configuring the hardware for proper multicast, | |
2314 | * promiscuous mode, and all-multi behavior. | |
2315 | **/ | |
2316 | static void igb_set_multi(struct net_device *netdev) | |
2317 | { | |
2318 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2319 | struct e1000_hw *hw = &adapter->hw; | |
2320 | struct e1000_mac_info *mac = &hw->mac; | |
2321 | struct dev_mc_list *mc_ptr; | |
2322 | u8 *mta_list; | |
2323 | u32 rctl; | |
2324 | int i; | |
2325 | ||
2326 | /* Check for Promiscuous and All Multicast modes */ | |
2327 | ||
2328 | rctl = rd32(E1000_RCTL); | |
2329 | ||
746b9f02 | 2330 | if (netdev->flags & IFF_PROMISC) { |
9d5c8243 | 2331 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
746b9f02 PM |
2332 | rctl &= ~E1000_RCTL_VFE; |
2333 | } else { | |
2334 | if (netdev->flags & IFF_ALLMULTI) { | |
2335 | rctl |= E1000_RCTL_MPE; | |
2336 | rctl &= ~E1000_RCTL_UPE; | |
2337 | } else | |
2338 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | |
78ed11a5 | 2339 | rctl |= E1000_RCTL_VFE; |
746b9f02 | 2340 | } |
9d5c8243 AK |
2341 | wr32(E1000_RCTL, rctl); |
2342 | ||
2343 | if (!netdev->mc_count) { | |
2344 | /* nothing to program, so clear mc list */ | |
8a900862 AD |
2345 | igb_update_mc_addr_list(hw, NULL, 0, 1, |
2346 | mac->rar_entry_count); | |
9d5c8243 AK |
2347 | return; |
2348 | } | |
2349 | ||
2350 | mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); | |
2351 | if (!mta_list) | |
2352 | return; | |
2353 | ||
2354 | /* The shared function expects a packed array of only addresses. */ | |
2355 | mc_ptr = netdev->mc_list; | |
2356 | ||
2357 | for (i = 0; i < netdev->mc_count; i++) { | |
2358 | if (!mc_ptr) | |
2359 | break; | |
2360 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | |
2361 | mc_ptr = mc_ptr->next; | |
2362 | } | |
8a900862 | 2363 | igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count); |
9d5c8243 AK |
2364 | kfree(mta_list); |
2365 | } | |
2366 | ||
2367 | /* Need to wait a few seconds after link up to get diagnostic information from | |
2368 | * the phy */ | |
2369 | static void igb_update_phy_info(unsigned long data) | |
2370 | { | |
2371 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 2372 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
2373 | } |
2374 | ||
4d6b725e AD |
2375 | /** |
2376 | * igb_has_link - check shared code for link and determine up/down | |
2377 | * @adapter: pointer to driver private info | |
2378 | **/ | |
2379 | static bool igb_has_link(struct igb_adapter *adapter) | |
2380 | { | |
2381 | struct e1000_hw *hw = &adapter->hw; | |
2382 | bool link_active = false; | |
2383 | s32 ret_val = 0; | |
2384 | ||
2385 | /* get_link_status is set on LSC (link status) interrupt or | |
2386 | * rx sequence error interrupt. get_link_status will stay | |
2387 | * false until the e1000_check_for_link establishes link | |
2388 | * for copper adapters ONLY | |
2389 | */ | |
2390 | switch (hw->phy.media_type) { | |
2391 | case e1000_media_type_copper: | |
2392 | if (hw->mac.get_link_status) { | |
2393 | ret_val = hw->mac.ops.check_for_link(hw); | |
2394 | link_active = !hw->mac.get_link_status; | |
2395 | } else { | |
2396 | link_active = true; | |
2397 | } | |
2398 | break; | |
2399 | case e1000_media_type_fiber: | |
2400 | ret_val = hw->mac.ops.check_for_link(hw); | |
2401 | link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU); | |
2402 | break; | |
2403 | case e1000_media_type_internal_serdes: | |
2404 | ret_val = hw->mac.ops.check_for_link(hw); | |
2405 | link_active = hw->mac.serdes_has_link; | |
2406 | break; | |
2407 | default: | |
2408 | case e1000_media_type_unknown: | |
2409 | break; | |
2410 | } | |
2411 | ||
2412 | return link_active; | |
2413 | } | |
2414 | ||
9d5c8243 AK |
2415 | /** |
2416 | * igb_watchdog - Timer Call-back | |
2417 | * @data: pointer to adapter cast into an unsigned long | |
2418 | **/ | |
2419 | static void igb_watchdog(unsigned long data) | |
2420 | { | |
2421 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
2422 | /* Do the rest outside of interrupt context */ | |
2423 | schedule_work(&adapter->watchdog_task); | |
2424 | } | |
2425 | ||
2426 | static void igb_watchdog_task(struct work_struct *work) | |
2427 | { | |
2428 | struct igb_adapter *adapter = container_of(work, | |
2429 | struct igb_adapter, watchdog_task); | |
2430 | struct e1000_hw *hw = &adapter->hw; | |
9d5c8243 AK |
2431 | struct net_device *netdev = adapter->netdev; |
2432 | struct igb_ring *tx_ring = adapter->tx_ring; | |
9d5c8243 | 2433 | u32 link; |
7a6ea550 | 2434 | u32 eics = 0; |
7a6ea550 | 2435 | int i; |
9d5c8243 | 2436 | |
4d6b725e AD |
2437 | link = igb_has_link(adapter); |
2438 | if ((netif_carrier_ok(netdev)) && link) | |
9d5c8243 AK |
2439 | goto link_up; |
2440 | ||
9d5c8243 AK |
2441 | if (link) { |
2442 | if (!netif_carrier_ok(netdev)) { | |
2443 | u32 ctrl; | |
2444 | hw->mac.ops.get_speed_and_duplex(&adapter->hw, | |
2445 | &adapter->link_speed, | |
2446 | &adapter->link_duplex); | |
2447 | ||
2448 | ctrl = rd32(E1000_CTRL); | |
527d47c1 AD |
2449 | /* Links status message must follow this format */ |
2450 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | |
9d5c8243 | 2451 | "Flow Control: %s\n", |
527d47c1 | 2452 | netdev->name, |
9d5c8243 AK |
2453 | adapter->link_speed, |
2454 | adapter->link_duplex == FULL_DUPLEX ? | |
2455 | "Full Duplex" : "Half Duplex", | |
2456 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & | |
2457 | E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & | |
2458 | E1000_CTRL_RFCE) ? "RX" : ((ctrl & | |
2459 | E1000_CTRL_TFCE) ? "TX" : "None"))); | |
2460 | ||
2461 | /* tweak tx_queue_len according to speed/duplex and | |
2462 | * adjust the timeout factor */ | |
2463 | netdev->tx_queue_len = adapter->tx_queue_len; | |
2464 | adapter->tx_timeout_factor = 1; | |
2465 | switch (adapter->link_speed) { | |
2466 | case SPEED_10: | |
2467 | netdev->tx_queue_len = 10; | |
2468 | adapter->tx_timeout_factor = 14; | |
2469 | break; | |
2470 | case SPEED_100: | |
2471 | netdev->tx_queue_len = 100; | |
2472 | /* maybe add some timeout factor ? */ | |
2473 | break; | |
2474 | } | |
2475 | ||
2476 | netif_carrier_on(netdev); | |
fd2ea0a7 | 2477 | netif_tx_wake_all_queues(netdev); |
9d5c8243 | 2478 | |
4b1a9877 | 2479 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
2480 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2481 | mod_timer(&adapter->phy_info_timer, | |
2482 | round_jiffies(jiffies + 2 * HZ)); | |
2483 | } | |
2484 | } else { | |
2485 | if (netif_carrier_ok(netdev)) { | |
2486 | adapter->link_speed = 0; | |
2487 | adapter->link_duplex = 0; | |
527d47c1 AD |
2488 | /* Links status message must follow this format */ |
2489 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
2490 | netdev->name); | |
9d5c8243 | 2491 | netif_carrier_off(netdev); |
fd2ea0a7 | 2492 | netif_tx_stop_all_queues(netdev); |
4b1a9877 AD |
2493 | |
2494 | /* link state has changed, schedule phy info update */ | |
9d5c8243 AK |
2495 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2496 | mod_timer(&adapter->phy_info_timer, | |
2497 | round_jiffies(jiffies + 2 * HZ)); | |
2498 | } | |
2499 | } | |
2500 | ||
2501 | link_up: | |
2502 | igb_update_stats(adapter); | |
2503 | ||
4b1a9877 | 2504 | hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; |
9d5c8243 | 2505 | adapter->tpt_old = adapter->stats.tpt; |
4b1a9877 | 2506 | hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old; |
9d5c8243 AK |
2507 | adapter->colc_old = adapter->stats.colc; |
2508 | ||
2509 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; | |
2510 | adapter->gorc_old = adapter->stats.gorc; | |
2511 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | |
2512 | adapter->gotc_old = adapter->stats.gotc; | |
2513 | ||
2514 | igb_update_adaptive(&adapter->hw); | |
2515 | ||
2516 | if (!netif_carrier_ok(netdev)) { | |
2517 | if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) { | |
2518 | /* We've lost link, so the controller stops DMA, | |
2519 | * but we've got queued Tx work that's never going | |
2520 | * to get done, so reset controller to flush Tx. | |
2521 | * (Do the reset outside of interrupt context). */ | |
2522 | adapter->tx_timeout_count++; | |
2523 | schedule_work(&adapter->reset_task); | |
2524 | } | |
2525 | } | |
2526 | ||
2527 | /* Cause software interrupt to ensure rx ring is cleaned */ | |
7a6ea550 AD |
2528 | if (adapter->msix_entries) { |
2529 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2530 | eics |= adapter->rx_ring[i].eims_value; | |
2531 | wr32(E1000_EICS, eics); | |
2532 | } else { | |
2533 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
2534 | } | |
9d5c8243 AK |
2535 | |
2536 | /* Force detection of hung controller every watchdog period */ | |
2537 | tx_ring->detect_tx_hung = true; | |
2538 | ||
2539 | /* Reset the timer */ | |
2540 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
2541 | mod_timer(&adapter->watchdog_timer, | |
2542 | round_jiffies(jiffies + 2 * HZ)); | |
2543 | } | |
2544 | ||
2545 | enum latency_range { | |
2546 | lowest_latency = 0, | |
2547 | low_latency = 1, | |
2548 | bulk_latency = 2, | |
2549 | latency_invalid = 255 | |
2550 | }; | |
2551 | ||
2552 | ||
6eb5a7f1 AD |
2553 | /** |
2554 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
2555 | * | |
2556 | * Stores a new ITR value based on strictly on packet size. This | |
2557 | * algorithm is less sophisticated than that used in igb_update_itr, | |
2558 | * due to the difficulty of synchronizing statistics across multiple | |
2559 | * receive rings. The divisors and thresholds used by this fuction | |
2560 | * were determined based on theoretical maximum wire speed and testing | |
2561 | * data, in order to minimize response time while increasing bulk | |
2562 | * throughput. | |
2563 | * This functionality is controlled by the InterruptThrottleRate module | |
2564 | * parameter (see igb_param.c) | |
2565 | * NOTE: This function is called only when operating in a multiqueue | |
2566 | * receive environment. | |
2567 | * @rx_ring: pointer to ring | |
2568 | **/ | |
2569 | static void igb_update_ring_itr(struct igb_ring *rx_ring) | |
9d5c8243 | 2570 | { |
6eb5a7f1 AD |
2571 | int new_val = rx_ring->itr_val; |
2572 | int avg_wire_size = 0; | |
2573 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 2574 | |
6eb5a7f1 AD |
2575 | if (!rx_ring->total_packets) |
2576 | goto clear_counts; /* no packets, so don't do anything */ | |
9d5c8243 | 2577 | |
6eb5a7f1 AD |
2578 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
2579 | * ints/sec - ITR timer value of 120 ticks. | |
2580 | */ | |
2581 | if (adapter->link_speed != SPEED_1000) { | |
2582 | new_val = 120; | |
2583 | goto set_itr_val; | |
9d5c8243 | 2584 | } |
6eb5a7f1 | 2585 | avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets; |
9d5c8243 | 2586 | |
6eb5a7f1 AD |
2587 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
2588 | avg_wire_size += 24; | |
2589 | ||
2590 | /* Don't starve jumbo frames */ | |
2591 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 2592 | |
6eb5a7f1 AD |
2593 | /* Give a little boost to mid-size frames */ |
2594 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
2595 | new_val = avg_wire_size / 3; | |
2596 | else | |
2597 | new_val = avg_wire_size / 2; | |
9d5c8243 | 2598 | |
6eb5a7f1 | 2599 | set_itr_val: |
9d5c8243 AK |
2600 | if (new_val != rx_ring->itr_val) { |
2601 | rx_ring->itr_val = new_val; | |
6eb5a7f1 | 2602 | rx_ring->set_itr = 1; |
9d5c8243 | 2603 | } |
6eb5a7f1 AD |
2604 | clear_counts: |
2605 | rx_ring->total_bytes = 0; | |
2606 | rx_ring->total_packets = 0; | |
9d5c8243 AK |
2607 | } |
2608 | ||
2609 | /** | |
2610 | * igb_update_itr - update the dynamic ITR value based on statistics | |
2611 | * Stores a new ITR value based on packets and byte | |
2612 | * counts during the last interrupt. The advantage of per interrupt | |
2613 | * computation is faster updates and more accurate ITR for the current | |
2614 | * traffic pattern. Constants in this function were computed | |
2615 | * based on theoretical maximum wire speed and thresholds were set based | |
2616 | * on testing data as well as attempting to minimize response time | |
2617 | * while increasing bulk throughput. | |
2618 | * this functionality is controlled by the InterruptThrottleRate module | |
2619 | * parameter (see igb_param.c) | |
2620 | * NOTE: These calculations are only valid when operating in a single- | |
2621 | * queue environment. | |
2622 | * @adapter: pointer to adapter | |
2623 | * @itr_setting: current adapter->itr | |
2624 | * @packets: the number of packets during this measurement interval | |
2625 | * @bytes: the number of bytes during this measurement interval | |
2626 | **/ | |
2627 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
2628 | int packets, int bytes) | |
2629 | { | |
2630 | unsigned int retval = itr_setting; | |
2631 | ||
2632 | if (packets == 0) | |
2633 | goto update_itr_done; | |
2634 | ||
2635 | switch (itr_setting) { | |
2636 | case lowest_latency: | |
2637 | /* handle TSO and jumbo frames */ | |
2638 | if (bytes/packets > 8000) | |
2639 | retval = bulk_latency; | |
2640 | else if ((packets < 5) && (bytes > 512)) | |
2641 | retval = low_latency; | |
2642 | break; | |
2643 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
2644 | if (bytes > 10000) { | |
2645 | /* this if handles the TSO accounting */ | |
2646 | if (bytes/packets > 8000) { | |
2647 | retval = bulk_latency; | |
2648 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
2649 | retval = bulk_latency; | |
2650 | } else if ((packets > 35)) { | |
2651 | retval = lowest_latency; | |
2652 | } | |
2653 | } else if (bytes/packets > 2000) { | |
2654 | retval = bulk_latency; | |
2655 | } else if (packets <= 2 && bytes < 512) { | |
2656 | retval = lowest_latency; | |
2657 | } | |
2658 | break; | |
2659 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
2660 | if (bytes > 25000) { | |
2661 | if (packets > 35) | |
2662 | retval = low_latency; | |
1e5c3d21 | 2663 | } else if (bytes < 1500) { |
9d5c8243 AK |
2664 | retval = low_latency; |
2665 | } | |
2666 | break; | |
2667 | } | |
2668 | ||
2669 | update_itr_done: | |
2670 | return retval; | |
2671 | } | |
2672 | ||
6eb5a7f1 | 2673 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 AK |
2674 | { |
2675 | u16 current_itr; | |
2676 | u32 new_itr = adapter->itr; | |
2677 | ||
2678 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
2679 | if (adapter->link_speed != SPEED_1000) { | |
2680 | current_itr = 0; | |
2681 | new_itr = 4000; | |
2682 | goto set_itr_now; | |
2683 | } | |
2684 | ||
2685 | adapter->rx_itr = igb_update_itr(adapter, | |
2686 | adapter->rx_itr, | |
2687 | adapter->rx_ring->total_packets, | |
2688 | adapter->rx_ring->total_bytes); | |
9d5c8243 | 2689 | |
6eb5a7f1 | 2690 | if (adapter->rx_ring->buddy) { |
9d5c8243 AK |
2691 | adapter->tx_itr = igb_update_itr(adapter, |
2692 | adapter->tx_itr, | |
2693 | adapter->tx_ring->total_packets, | |
2694 | adapter->tx_ring->total_bytes); | |
9d5c8243 AK |
2695 | current_itr = max(adapter->rx_itr, adapter->tx_itr); |
2696 | } else { | |
2697 | current_itr = adapter->rx_itr; | |
2698 | } | |
2699 | ||
6eb5a7f1 | 2700 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
73cd78f1 | 2701 | if (adapter->itr_setting == 3 && current_itr == lowest_latency) |
6eb5a7f1 AD |
2702 | current_itr = low_latency; |
2703 | ||
9d5c8243 AK |
2704 | switch (current_itr) { |
2705 | /* counts and packets in update_itr are dependent on these numbers */ | |
2706 | case lowest_latency: | |
2707 | new_itr = 70000; | |
2708 | break; | |
2709 | case low_latency: | |
2710 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2711 | break; | |
2712 | case bulk_latency: | |
2713 | new_itr = 4000; | |
2714 | break; | |
2715 | default: | |
2716 | break; | |
2717 | } | |
2718 | ||
2719 | set_itr_now: | |
6eb5a7f1 AD |
2720 | adapter->rx_ring->total_bytes = 0; |
2721 | adapter->rx_ring->total_packets = 0; | |
2722 | if (adapter->rx_ring->buddy) { | |
2723 | adapter->rx_ring->buddy->total_bytes = 0; | |
2724 | adapter->rx_ring->buddy->total_packets = 0; | |
2725 | } | |
2726 | ||
9d5c8243 AK |
2727 | if (new_itr != adapter->itr) { |
2728 | /* this attempts to bias the interrupt rate towards Bulk | |
2729 | * by adding intermediate steps when interrupt rate is | |
2730 | * increasing */ | |
2731 | new_itr = new_itr > adapter->itr ? | |
2732 | min(adapter->itr + (new_itr >> 2), new_itr) : | |
2733 | new_itr; | |
2734 | /* Don't write the value here; it resets the adapter's | |
2735 | * internal timer, and causes us to delay far longer than | |
2736 | * we should between interrupts. Instead, we write the ITR | |
2737 | * value at the beginning of the next interrupt so the timing | |
2738 | * ends up being correct. | |
2739 | */ | |
2740 | adapter->itr = new_itr; | |
6eb5a7f1 AD |
2741 | adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256); |
2742 | adapter->rx_ring->set_itr = 1; | |
9d5c8243 AK |
2743 | } |
2744 | ||
2745 | return; | |
2746 | } | |
2747 | ||
2748 | ||
2749 | #define IGB_TX_FLAGS_CSUM 0x00000001 | |
2750 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
2751 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
2752 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
33af6bcc | 2753 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 |
9d5c8243 AK |
2754 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
2755 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
2756 | ||
2757 | static inline int igb_tso_adv(struct igb_adapter *adapter, | |
2758 | struct igb_ring *tx_ring, | |
2759 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) | |
2760 | { | |
2761 | struct e1000_adv_tx_context_desc *context_desc; | |
2762 | unsigned int i; | |
2763 | int err; | |
2764 | struct igb_buffer *buffer_info; | |
2765 | u32 info = 0, tu_cmd = 0; | |
2766 | u32 mss_l4len_idx, l4len; | |
2767 | *hdr_len = 0; | |
2768 | ||
2769 | if (skb_header_cloned(skb)) { | |
2770 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2771 | if (err) | |
2772 | return err; | |
2773 | } | |
2774 | ||
2775 | l4len = tcp_hdrlen(skb); | |
2776 | *hdr_len += l4len; | |
2777 | ||
2778 | if (skb->protocol == htons(ETH_P_IP)) { | |
2779 | struct iphdr *iph = ip_hdr(skb); | |
2780 | iph->tot_len = 0; | |
2781 | iph->check = 0; | |
2782 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
2783 | iph->daddr, 0, | |
2784 | IPPROTO_TCP, | |
2785 | 0); | |
2786 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
2787 | ipv6_hdr(skb)->payload_len = 0; | |
2788 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
2789 | &ipv6_hdr(skb)->daddr, | |
2790 | 0, IPPROTO_TCP, 0); | |
2791 | } | |
2792 | ||
2793 | i = tx_ring->next_to_use; | |
2794 | ||
2795 | buffer_info = &tx_ring->buffer_info[i]; | |
2796 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2797 | /* VLAN MACLEN IPLEN */ | |
2798 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2799 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2800 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2801 | *hdr_len += skb_network_offset(skb); | |
2802 | info |= skb_network_header_len(skb); | |
2803 | *hdr_len += skb_network_header_len(skb); | |
2804 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2805 | ||
2806 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
2807 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2808 | ||
2809 | if (skb->protocol == htons(ETH_P_IP)) | |
2810 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; | |
2811 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2812 | ||
2813 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2814 | ||
2815 | /* MSS L4LEN IDX */ | |
2816 | mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); | |
2817 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | |
2818 | ||
73cd78f1 | 2819 | /* For 82575, context index must be unique per ring. */ |
7dfc16fa AD |
2820 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
2821 | mss_l4len_idx |= tx_ring->queue_index << 4; | |
9d5c8243 AK |
2822 | |
2823 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
2824 | context_desc->seqnum_seed = 0; | |
2825 | ||
2826 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2827 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2828 | buffer_info->dma = 0; |
2829 | i++; | |
2830 | if (i == tx_ring->count) | |
2831 | i = 0; | |
2832 | ||
2833 | tx_ring->next_to_use = i; | |
2834 | ||
2835 | return true; | |
2836 | } | |
2837 | ||
2838 | static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |
2839 | struct igb_ring *tx_ring, | |
2840 | struct sk_buff *skb, u32 tx_flags) | |
2841 | { | |
2842 | struct e1000_adv_tx_context_desc *context_desc; | |
2843 | unsigned int i; | |
2844 | struct igb_buffer *buffer_info; | |
2845 | u32 info = 0, tu_cmd = 0; | |
2846 | ||
2847 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | |
2848 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | |
2849 | i = tx_ring->next_to_use; | |
2850 | buffer_info = &tx_ring->buffer_info[i]; | |
2851 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2852 | ||
2853 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2854 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2855 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2856 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
2857 | info |= skb_network_header_len(skb); | |
2858 | ||
2859 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2860 | ||
2861 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2862 | ||
2863 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
44b0cda3 | 2864 | switch (skb->protocol) { |
09640e63 | 2865 | case cpu_to_be16(ETH_P_IP): |
9d5c8243 | 2866 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; |
44b0cda3 MW |
2867 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
2868 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2869 | break; | |
09640e63 | 2870 | case cpu_to_be16(ETH_P_IPV6): |
44b0cda3 MW |
2871 | /* XXX what about other V6 headers?? */ |
2872 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
2873 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2874 | break; | |
2875 | default: | |
2876 | if (unlikely(net_ratelimit())) | |
2877 | dev_warn(&adapter->pdev->dev, | |
2878 | "partial checksum but proto=%x!\n", | |
2879 | skb->protocol); | |
2880 | break; | |
2881 | } | |
9d5c8243 AK |
2882 | } |
2883 | ||
2884 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2885 | context_desc->seqnum_seed = 0; | |
7dfc16fa AD |
2886 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
2887 | context_desc->mss_l4len_idx = | |
2888 | cpu_to_le32(tx_ring->queue_index << 4); | |
265de409 AD |
2889 | else |
2890 | context_desc->mss_l4len_idx = 0; | |
9d5c8243 AK |
2891 | |
2892 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2893 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2894 | buffer_info->dma = 0; |
2895 | ||
2896 | i++; | |
2897 | if (i == tx_ring->count) | |
2898 | i = 0; | |
2899 | tx_ring->next_to_use = i; | |
2900 | ||
2901 | return true; | |
2902 | } | |
9d5c8243 AK |
2903 | return false; |
2904 | } | |
2905 | ||
2906 | #define IGB_MAX_TXD_PWR 16 | |
2907 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | |
2908 | ||
2909 | static inline int igb_tx_map_adv(struct igb_adapter *adapter, | |
0e014cb1 AD |
2910 | struct igb_ring *tx_ring, struct sk_buff *skb, |
2911 | unsigned int first) | |
9d5c8243 AK |
2912 | { |
2913 | struct igb_buffer *buffer_info; | |
2914 | unsigned int len = skb_headlen(skb); | |
2915 | unsigned int count = 0, i; | |
2916 | unsigned int f; | |
2917 | ||
2918 | i = tx_ring->next_to_use; | |
2919 | ||
2920 | buffer_info = &tx_ring->buffer_info[i]; | |
2921 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
2922 | buffer_info->length = len; | |
2923 | /* set time_stamp *before* dma to help avoid a possible race */ | |
2924 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2925 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2926 | buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len, |
2927 | PCI_DMA_TODEVICE); | |
2928 | count++; | |
2929 | i++; | |
2930 | if (i == tx_ring->count) | |
2931 | i = 0; | |
2932 | ||
2933 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
2934 | struct skb_frag_struct *frag; | |
2935 | ||
2936 | frag = &skb_shinfo(skb)->frags[f]; | |
2937 | len = frag->size; | |
2938 | ||
2939 | buffer_info = &tx_ring->buffer_info[i]; | |
2940 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
2941 | buffer_info->length = len; | |
2942 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2943 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2944 | buffer_info->dma = pci_map_page(adapter->pdev, |
2945 | frag->page, | |
2946 | frag->page_offset, | |
2947 | len, | |
2948 | PCI_DMA_TODEVICE); | |
2949 | ||
2950 | count++; | |
2951 | i++; | |
2952 | if (i == tx_ring->count) | |
2953 | i = 0; | |
2954 | } | |
2955 | ||
0e014cb1 | 2956 | i = ((i == 0) ? tx_ring->count - 1 : i - 1); |
9d5c8243 | 2957 | tx_ring->buffer_info[i].skb = skb; |
0e014cb1 | 2958 | tx_ring->buffer_info[first].next_to_watch = i; |
9d5c8243 AK |
2959 | |
2960 | return count; | |
2961 | } | |
2962 | ||
2963 | static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | |
2964 | struct igb_ring *tx_ring, | |
2965 | int tx_flags, int count, u32 paylen, | |
2966 | u8 hdr_len) | |
2967 | { | |
2968 | union e1000_adv_tx_desc *tx_desc = NULL; | |
2969 | struct igb_buffer *buffer_info; | |
2970 | u32 olinfo_status = 0, cmd_type_len; | |
2971 | unsigned int i; | |
2972 | ||
2973 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | |
2974 | E1000_ADVTXD_DCMD_DEXT); | |
2975 | ||
2976 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2977 | cmd_type_len |= E1000_ADVTXD_DCMD_VLE; | |
2978 | ||
33af6bcc PO |
2979 | if (tx_flags & IGB_TX_FLAGS_TSTAMP) |
2980 | cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP; | |
2981 | ||
9d5c8243 AK |
2982 | if (tx_flags & IGB_TX_FLAGS_TSO) { |
2983 | cmd_type_len |= E1000_ADVTXD_DCMD_TSE; | |
2984 | ||
2985 | /* insert tcp checksum */ | |
2986 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
2987 | ||
2988 | /* insert ip checksum */ | |
2989 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
2990 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
2991 | ||
2992 | } else if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
2993 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
2994 | } | |
2995 | ||
7dfc16fa AD |
2996 | if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) && |
2997 | (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | | |
2998 | IGB_TX_FLAGS_VLAN))) | |
661086df | 2999 | olinfo_status |= tx_ring->queue_index << 4; |
9d5c8243 AK |
3000 | |
3001 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | |
3002 | ||
3003 | i = tx_ring->next_to_use; | |
3004 | while (count--) { | |
3005 | buffer_info = &tx_ring->buffer_info[i]; | |
3006 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
3007 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
3008 | tx_desc->read.cmd_type_len = | |
3009 | cpu_to_le32(cmd_type_len | buffer_info->length); | |
3010 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
3011 | i++; | |
3012 | if (i == tx_ring->count) | |
3013 | i = 0; | |
3014 | } | |
3015 | ||
3016 | tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd); | |
3017 | /* Force memory writes to complete before letting h/w | |
3018 | * know there are new descriptors to fetch. (Only | |
3019 | * applicable for weak-ordered memory model archs, | |
3020 | * such as IA-64). */ | |
3021 | wmb(); | |
3022 | ||
3023 | tx_ring->next_to_use = i; | |
3024 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
3025 | /* we need this if more than one processor can write to our tail | |
3026 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
3027 | mmiowb(); | |
3028 | } | |
3029 | ||
3030 | static int __igb_maybe_stop_tx(struct net_device *netdev, | |
3031 | struct igb_ring *tx_ring, int size) | |
3032 | { | |
3033 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3034 | ||
661086df | 3035 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 3036 | |
9d5c8243 AK |
3037 | /* Herbert's original patch had: |
3038 | * smp_mb__after_netif_stop_queue(); | |
3039 | * but since that doesn't exist yet, just open code it. */ | |
3040 | smp_mb(); | |
3041 | ||
3042 | /* We need to check again in a case another CPU has just | |
3043 | * made room available. */ | |
3044 | if (IGB_DESC_UNUSED(tx_ring) < size) | |
3045 | return -EBUSY; | |
3046 | ||
3047 | /* A reprieve! */ | |
661086df | 3048 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
3049 | ++adapter->restart_queue; |
3050 | return 0; | |
3051 | } | |
3052 | ||
3053 | static int igb_maybe_stop_tx(struct net_device *netdev, | |
3054 | struct igb_ring *tx_ring, int size) | |
3055 | { | |
3056 | if (IGB_DESC_UNUSED(tx_ring) >= size) | |
3057 | return 0; | |
3058 | return __igb_maybe_stop_tx(netdev, tx_ring, size); | |
3059 | } | |
3060 | ||
9d5c8243 AK |
3061 | static int igb_xmit_frame_ring_adv(struct sk_buff *skb, |
3062 | struct net_device *netdev, | |
3063 | struct igb_ring *tx_ring) | |
3064 | { | |
3065 | struct igb_adapter *adapter = netdev_priv(netdev); | |
0e014cb1 | 3066 | unsigned int first; |
9d5c8243 | 3067 | unsigned int tx_flags = 0; |
9d5c8243 AK |
3068 | u8 hdr_len = 0; |
3069 | int tso = 0; | |
33af6bcc | 3070 | union skb_shared_tx *shtx; |
9d5c8243 | 3071 | |
9d5c8243 AK |
3072 | if (test_bit(__IGB_DOWN, &adapter->state)) { |
3073 | dev_kfree_skb_any(skb); | |
3074 | return NETDEV_TX_OK; | |
3075 | } | |
3076 | ||
3077 | if (skb->len <= 0) { | |
3078 | dev_kfree_skb_any(skb); | |
3079 | return NETDEV_TX_OK; | |
3080 | } | |
3081 | ||
9d5c8243 AK |
3082 | /* need: 1 descriptor per page, |
3083 | * + 2 desc gap to keep tail from touching head, | |
3084 | * + 1 desc for skb->data, | |
3085 | * + 1 desc for context descriptor, | |
3086 | * otherwise try next time */ | |
3087 | if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { | |
3088 | /* this is a hard error */ | |
9d5c8243 AK |
3089 | return NETDEV_TX_BUSY; |
3090 | } | |
33af6bcc PO |
3091 | |
3092 | /* | |
3093 | * TODO: check that there currently is no other packet with | |
3094 | * time stamping in the queue | |
3095 | * | |
3096 | * When doing time stamping, keep the connection to the socket | |
3097 | * a while longer: it is still needed by skb_hwtstamp_tx(), | |
3098 | * called either in igb_tx_hwtstamp() or by our caller when | |
3099 | * doing software time stamping. | |
3100 | */ | |
3101 | shtx = skb_tx(skb); | |
3102 | if (unlikely(shtx->hardware)) { | |
3103 | shtx->in_progress = 1; | |
3104 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
3105 | } else if (likely(!shtx->software)) { | |
3106 | /* | |
3107 | * TODO: can this be solved in dev.c:dev_hard_start_xmit()? | |
3108 | * There are probably unmodified driver which do something | |
3109 | * like this and thus don't work in combination with | |
3110 | * SOF_TIMESTAMPING_TX_SOFTWARE. | |
3111 | */ | |
3112 | skb_orphan(skb); | |
3113 | } | |
9d5c8243 AK |
3114 | |
3115 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | |
3116 | tx_flags |= IGB_TX_FLAGS_VLAN; | |
3117 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
3118 | } | |
3119 | ||
661086df PWJ |
3120 | if (skb->protocol == htons(ETH_P_IP)) |
3121 | tx_flags |= IGB_TX_FLAGS_IPV4; | |
3122 | ||
0e014cb1 | 3123 | first = tx_ring->next_to_use; |
9d5c8243 AK |
3124 | tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, |
3125 | &hdr_len) : 0; | |
3126 | ||
3127 | if (tso < 0) { | |
3128 | dev_kfree_skb_any(skb); | |
9d5c8243 AK |
3129 | return NETDEV_TX_OK; |
3130 | } | |
3131 | ||
3132 | if (tso) | |
3133 | tx_flags |= IGB_TX_FLAGS_TSO; | |
bc1cbd34 AD |
3134 | else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) && |
3135 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
3136 | tx_flags |= IGB_TX_FLAGS_CSUM; | |
9d5c8243 | 3137 | |
9d5c8243 | 3138 | igb_tx_queue_adv(adapter, tx_ring, tx_flags, |
0e014cb1 | 3139 | igb_tx_map_adv(adapter, tx_ring, skb, first), |
9d5c8243 AK |
3140 | skb->len, hdr_len); |
3141 | ||
3142 | netdev->trans_start = jiffies; | |
3143 | ||
3144 | /* Make sure there is space in the ring for the next send. */ | |
3145 | igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); | |
3146 | ||
9d5c8243 AK |
3147 | return NETDEV_TX_OK; |
3148 | } | |
3149 | ||
3150 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev) | |
3151 | { | |
3152 | struct igb_adapter *adapter = netdev_priv(netdev); | |
661086df PWJ |
3153 | struct igb_ring *tx_ring; |
3154 | ||
661086df PWJ |
3155 | int r_idx = 0; |
3156 | r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1); | |
3157 | tx_ring = adapter->multi_tx_table[r_idx]; | |
9d5c8243 AK |
3158 | |
3159 | /* This goes back to the question of how to logically map a tx queue | |
3160 | * to a flow. Right now, performance is impacted slightly negatively | |
3161 | * if using multiple tx queues. If the stack breaks away from a | |
3162 | * single qdisc implementation, we can look at this again. */ | |
3163 | return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring)); | |
3164 | } | |
3165 | ||
3166 | /** | |
3167 | * igb_tx_timeout - Respond to a Tx Hang | |
3168 | * @netdev: network interface device structure | |
3169 | **/ | |
3170 | static void igb_tx_timeout(struct net_device *netdev) | |
3171 | { | |
3172 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3173 | struct e1000_hw *hw = &adapter->hw; | |
3174 | ||
3175 | /* Do the reset outside of interrupt context */ | |
3176 | adapter->tx_timeout_count++; | |
3177 | schedule_work(&adapter->reset_task); | |
265de409 AD |
3178 | wr32(E1000_EICS, |
3179 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
3180 | } |
3181 | ||
3182 | static void igb_reset_task(struct work_struct *work) | |
3183 | { | |
3184 | struct igb_adapter *adapter; | |
3185 | adapter = container_of(work, struct igb_adapter, reset_task); | |
3186 | ||
3187 | igb_reinit_locked(adapter); | |
3188 | } | |
3189 | ||
3190 | /** | |
3191 | * igb_get_stats - Get System Network Statistics | |
3192 | * @netdev: network interface device structure | |
3193 | * | |
3194 | * Returns the address of the device statistics structure. | |
3195 | * The statistics are actually updated from the timer callback. | |
3196 | **/ | |
73cd78f1 | 3197 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) |
9d5c8243 AK |
3198 | { |
3199 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3200 | ||
3201 | /* only return the current stats */ | |
3202 | return &adapter->net_stats; | |
3203 | } | |
3204 | ||
3205 | /** | |
3206 | * igb_change_mtu - Change the Maximum Transfer Unit | |
3207 | * @netdev: network interface device structure | |
3208 | * @new_mtu: new value for maximum frame size | |
3209 | * | |
3210 | * Returns 0 on success, negative on failure | |
3211 | **/ | |
3212 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
3213 | { | |
3214 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3215 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3216 | ||
3217 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | |
3218 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | |
3219 | dev_err(&adapter->pdev->dev, "Invalid MTU setting\n"); | |
3220 | return -EINVAL; | |
3221 | } | |
3222 | ||
3223 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 | |
3224 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { | |
3225 | dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n"); | |
3226 | return -EINVAL; | |
3227 | } | |
3228 | ||
3229 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
3230 | msleep(1); | |
73cd78f1 | 3231 | |
9d5c8243 AK |
3232 | /* igb_down has a dependency on max_frame_size */ |
3233 | adapter->max_frame_size = max_frame; | |
3234 | if (netif_running(netdev)) | |
3235 | igb_down(adapter); | |
3236 | ||
3237 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN | |
3238 | * means we reserve 2 more, this pushes us to allocate from the next | |
3239 | * larger slab size. | |
3240 | * i.e. RXBUFFER_2048 --> size-4096 slab | |
3241 | */ | |
3242 | ||
3243 | if (max_frame <= IGB_RXBUFFER_256) | |
3244 | adapter->rx_buffer_len = IGB_RXBUFFER_256; | |
3245 | else if (max_frame <= IGB_RXBUFFER_512) | |
3246 | adapter->rx_buffer_len = IGB_RXBUFFER_512; | |
3247 | else if (max_frame <= IGB_RXBUFFER_1024) | |
3248 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | |
3249 | else if (max_frame <= IGB_RXBUFFER_2048) | |
3250 | adapter->rx_buffer_len = IGB_RXBUFFER_2048; | |
3251 | else | |
bf36c1a0 AD |
3252 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 |
3253 | adapter->rx_buffer_len = IGB_RXBUFFER_16384; | |
3254 | #else | |
3255 | adapter->rx_buffer_len = PAGE_SIZE / 2; | |
3256 | #endif | |
9d5c8243 AK |
3257 | /* adjust allocation if LPE protects us, and we aren't using SBP */ |
3258 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || | |
3259 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) | |
3260 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
3261 | ||
3262 | dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n", | |
3263 | netdev->mtu, new_mtu); | |
3264 | netdev->mtu = new_mtu; | |
3265 | ||
3266 | if (netif_running(netdev)) | |
3267 | igb_up(adapter); | |
3268 | else | |
3269 | igb_reset(adapter); | |
3270 | ||
3271 | clear_bit(__IGB_RESETTING, &adapter->state); | |
3272 | ||
3273 | return 0; | |
3274 | } | |
3275 | ||
3276 | /** | |
3277 | * igb_update_stats - Update the board statistics counters | |
3278 | * @adapter: board private structure | |
3279 | **/ | |
3280 | ||
3281 | void igb_update_stats(struct igb_adapter *adapter) | |
3282 | { | |
3283 | struct e1000_hw *hw = &adapter->hw; | |
3284 | struct pci_dev *pdev = adapter->pdev; | |
3285 | u16 phy_tmp; | |
3286 | ||
3287 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
3288 | ||
3289 | /* | |
3290 | * Prevent stats update while adapter is being reset, or if the pci | |
3291 | * connection is down. | |
3292 | */ | |
3293 | if (adapter->link_speed == 0) | |
3294 | return; | |
3295 | if (pci_channel_offline(pdev)) | |
3296 | return; | |
3297 | ||
3298 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); | |
3299 | adapter->stats.gprc += rd32(E1000_GPRC); | |
3300 | adapter->stats.gorc += rd32(E1000_GORCL); | |
3301 | rd32(E1000_GORCH); /* clear GORCL */ | |
3302 | adapter->stats.bprc += rd32(E1000_BPRC); | |
3303 | adapter->stats.mprc += rd32(E1000_MPRC); | |
3304 | adapter->stats.roc += rd32(E1000_ROC); | |
3305 | ||
3306 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
3307 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
3308 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
3309 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
3310 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
3311 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
3312 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
3313 | adapter->stats.sec += rd32(E1000_SEC); | |
3314 | ||
3315 | adapter->stats.mpc += rd32(E1000_MPC); | |
3316 | adapter->stats.scc += rd32(E1000_SCC); | |
3317 | adapter->stats.ecol += rd32(E1000_ECOL); | |
3318 | adapter->stats.mcc += rd32(E1000_MCC); | |
3319 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
3320 | adapter->stats.dc += rd32(E1000_DC); | |
3321 | adapter->stats.rlec += rd32(E1000_RLEC); | |
3322 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
3323 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
3324 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
3325 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
3326 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
3327 | adapter->stats.gptc += rd32(E1000_GPTC); | |
3328 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
3329 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
3330 | adapter->stats.rnbc += rd32(E1000_RNBC); | |
3331 | adapter->stats.ruc += rd32(E1000_RUC); | |
3332 | adapter->stats.rfc += rd32(E1000_RFC); | |
3333 | adapter->stats.rjc += rd32(E1000_RJC); | |
3334 | adapter->stats.tor += rd32(E1000_TORH); | |
3335 | adapter->stats.tot += rd32(E1000_TOTH); | |
3336 | adapter->stats.tpr += rd32(E1000_TPR); | |
3337 | ||
3338 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
3339 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
3340 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
3341 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
3342 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
3343 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
3344 | ||
3345 | adapter->stats.mptc += rd32(E1000_MPTC); | |
3346 | adapter->stats.bptc += rd32(E1000_BPTC); | |
3347 | ||
3348 | /* used for adaptive IFS */ | |
3349 | ||
3350 | hw->mac.tx_packet_delta = rd32(E1000_TPT); | |
3351 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
3352 | hw->mac.collision_delta = rd32(E1000_COLC); | |
3353 | adapter->stats.colc += hw->mac.collision_delta; | |
3354 | ||
3355 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
3356 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3357 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
3358 | adapter->stats.tsctc += rd32(E1000_TSCTC); | |
3359 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
3360 | ||
3361 | adapter->stats.iac += rd32(E1000_IAC); | |
3362 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
3363 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
3364 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
3365 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
3366 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
3367 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
3368 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
3369 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
3370 | ||
3371 | /* Fill out the OS statistics structure */ | |
3372 | adapter->net_stats.multicast = adapter->stats.mprc; | |
3373 | adapter->net_stats.collisions = adapter->stats.colc; | |
3374 | ||
3375 | /* Rx Errors */ | |
3376 | ||
3377 | /* RLEC on some newer hardware can be incorrect so build | |
3378 | * our own version based on RUC and ROC */ | |
3379 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + | |
3380 | adapter->stats.crcerrs + adapter->stats.algnerrc + | |
3381 | adapter->stats.ruc + adapter->stats.roc + | |
3382 | adapter->stats.cexterr; | |
3383 | adapter->net_stats.rx_length_errors = adapter->stats.ruc + | |
3384 | adapter->stats.roc; | |
3385 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
3386 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; | |
3387 | adapter->net_stats.rx_missed_errors = adapter->stats.mpc; | |
3388 | ||
3389 | /* Tx Errors */ | |
3390 | adapter->net_stats.tx_errors = adapter->stats.ecol + | |
3391 | adapter->stats.latecol; | |
3392 | adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; | |
3393 | adapter->net_stats.tx_window_errors = adapter->stats.latecol; | |
3394 | adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; | |
3395 | ||
3396 | /* Tx Dropped needs to be maintained elsewhere */ | |
3397 | ||
3398 | /* Phy Stats */ | |
3399 | if (hw->phy.media_type == e1000_media_type_copper) { | |
3400 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 3401 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
3402 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
3403 | adapter->phy_stats.idle_errors += phy_tmp; | |
3404 | } | |
3405 | } | |
3406 | ||
3407 | /* Management Stats */ | |
3408 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
3409 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
3410 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
3411 | } | |
3412 | ||
9d5c8243 AK |
3413 | static irqreturn_t igb_msix_other(int irq, void *data) |
3414 | { | |
3415 | struct net_device *netdev = data; | |
3416 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3417 | struct e1000_hw *hw = &adapter->hw; | |
844290e5 | 3418 | u32 icr = rd32(E1000_ICR); |
9d5c8243 | 3419 | |
844290e5 | 3420 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 AD |
3421 | |
3422 | if(icr & E1000_ICR_DOUTSYNC) { | |
3423 | /* HW is reporting DMA is out of sync */ | |
3424 | adapter->stats.doosync++; | |
3425 | } | |
844290e5 PW |
3426 | if (!(icr & E1000_ICR_LSC)) |
3427 | goto no_link_interrupt; | |
3428 | hw->mac.get_link_status = 1; | |
3429 | /* guard against interrupt when we're going down */ | |
3430 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3431 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
eebbbdba | 3432 | |
9d5c8243 | 3433 | no_link_interrupt: |
dda0e083 | 3434 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); |
844290e5 | 3435 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
3436 | |
3437 | return IRQ_HANDLED; | |
3438 | } | |
3439 | ||
3440 | static irqreturn_t igb_msix_tx(int irq, void *data) | |
3441 | { | |
3442 | struct igb_ring *tx_ring = data; | |
3443 | struct igb_adapter *adapter = tx_ring->adapter; | |
3444 | struct e1000_hw *hw = &adapter->hw; | |
3445 | ||
421e02f0 | 3446 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3447 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3448 | igb_update_tx_dca(tx_ring); |
3449 | #endif | |
73cd78f1 | 3450 | |
9d5c8243 AK |
3451 | tx_ring->total_bytes = 0; |
3452 | tx_ring->total_packets = 0; | |
661086df PWJ |
3453 | |
3454 | /* auto mask will automatically reenable the interrupt when we write | |
3455 | * EICS */ | |
3b644cf6 | 3456 | if (!igb_clean_tx_irq(tx_ring)) |
9d5c8243 AK |
3457 | /* Ring was not completely cleaned, so fire another interrupt */ |
3458 | wr32(E1000_EICS, tx_ring->eims_value); | |
661086df | 3459 | else |
9d5c8243 | 3460 | wr32(E1000_EIMS, tx_ring->eims_value); |
661086df | 3461 | |
9d5c8243 AK |
3462 | return IRQ_HANDLED; |
3463 | } | |
3464 | ||
6eb5a7f1 AD |
3465 | static void igb_write_itr(struct igb_ring *ring) |
3466 | { | |
3467 | struct e1000_hw *hw = &ring->adapter->hw; | |
3468 | if ((ring->adapter->itr_setting & 3) && ring->set_itr) { | |
3469 | switch (hw->mac.type) { | |
3470 | case e1000_82576: | |
73cd78f1 | 3471 | wr32(ring->itr_register, ring->itr_val | |
6eb5a7f1 AD |
3472 | 0x80000000); |
3473 | break; | |
3474 | default: | |
73cd78f1 | 3475 | wr32(ring->itr_register, ring->itr_val | |
6eb5a7f1 AD |
3476 | (ring->itr_val << 16)); |
3477 | break; | |
3478 | } | |
3479 | ring->set_itr = 0; | |
3480 | } | |
3481 | } | |
3482 | ||
9d5c8243 AK |
3483 | static irqreturn_t igb_msix_rx(int irq, void *data) |
3484 | { | |
3485 | struct igb_ring *rx_ring = data; | |
9d5c8243 | 3486 | |
844290e5 PW |
3487 | /* Write the ITR value calculated at the end of the |
3488 | * previous interrupt. | |
3489 | */ | |
9d5c8243 | 3490 | |
6eb5a7f1 | 3491 | igb_write_itr(rx_ring); |
9d5c8243 | 3492 | |
288379f0 BH |
3493 | if (napi_schedule_prep(&rx_ring->napi)) |
3494 | __napi_schedule(&rx_ring->napi); | |
844290e5 | 3495 | |
421e02f0 | 3496 | #ifdef CONFIG_IGB_DCA |
8d253320 | 3497 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3498 | igb_update_rx_dca(rx_ring); |
3499 | #endif | |
3500 | return IRQ_HANDLED; | |
3501 | } | |
3502 | ||
421e02f0 | 3503 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
3504 | static void igb_update_rx_dca(struct igb_ring *rx_ring) |
3505 | { | |
3506 | u32 dca_rxctrl; | |
3507 | struct igb_adapter *adapter = rx_ring->adapter; | |
3508 | struct e1000_hw *hw = &adapter->hw; | |
3509 | int cpu = get_cpu(); | |
26bc19ec | 3510 | int q = rx_ring->reg_idx; |
fe4506b6 JC |
3511 | |
3512 | if (rx_ring->cpu != cpu) { | |
3513 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
2d064c06 AD |
3514 | if (hw->mac.type == e1000_82576) { |
3515 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
3516 | dca_rxctrl |= dca_get_tag(cpu) << | |
3517 | E1000_DCA_RXCTRL_CPUID_SHIFT; | |
3518 | } else { | |
3519 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | |
3520 | dca_rxctrl |= dca_get_tag(cpu); | |
3521 | } | |
fe4506b6 JC |
3522 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
3523 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
3524 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
3525 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
3526 | rx_ring->cpu = cpu; | |
3527 | } | |
3528 | put_cpu(); | |
3529 | } | |
3530 | ||
3531 | static void igb_update_tx_dca(struct igb_ring *tx_ring) | |
3532 | { | |
3533 | u32 dca_txctrl; | |
3534 | struct igb_adapter *adapter = tx_ring->adapter; | |
3535 | struct e1000_hw *hw = &adapter->hw; | |
3536 | int cpu = get_cpu(); | |
26bc19ec | 3537 | int q = tx_ring->reg_idx; |
fe4506b6 JC |
3538 | |
3539 | if (tx_ring->cpu != cpu) { | |
3540 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
2d064c06 AD |
3541 | if (hw->mac.type == e1000_82576) { |
3542 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; | |
3543 | dca_txctrl |= dca_get_tag(cpu) << | |
3544 | E1000_DCA_TXCTRL_CPUID_SHIFT; | |
3545 | } else { | |
3546 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
3547 | dca_txctrl |= dca_get_tag(cpu); | |
3548 | } | |
fe4506b6 JC |
3549 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; |
3550 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
3551 | tx_ring->cpu = cpu; | |
3552 | } | |
3553 | put_cpu(); | |
3554 | } | |
3555 | ||
3556 | static void igb_setup_dca(struct igb_adapter *adapter) | |
3557 | { | |
3558 | int i; | |
3559 | ||
7dfc16fa | 3560 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
3561 | return; |
3562 | ||
3563 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3564 | adapter->tx_ring[i].cpu = -1; | |
3565 | igb_update_tx_dca(&adapter->tx_ring[i]); | |
3566 | } | |
3567 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3568 | adapter->rx_ring[i].cpu = -1; | |
3569 | igb_update_rx_dca(&adapter->rx_ring[i]); | |
3570 | } | |
3571 | } | |
3572 | ||
3573 | static int __igb_notify_dca(struct device *dev, void *data) | |
3574 | { | |
3575 | struct net_device *netdev = dev_get_drvdata(dev); | |
3576 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3577 | struct e1000_hw *hw = &adapter->hw; | |
3578 | unsigned long event = *(unsigned long *)data; | |
3579 | ||
3580 | switch (event) { | |
3581 | case DCA_PROVIDER_ADD: | |
3582 | /* if already enabled, don't do it again */ | |
7dfc16fa | 3583 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 3584 | break; |
fe4506b6 JC |
3585 | /* Always use CB2 mode, difference is masked |
3586 | * in the CB driver. */ | |
cbd347ad | 3587 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
fe4506b6 | 3588 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 3589 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
3590 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); |
3591 | igb_setup_dca(adapter); | |
3592 | break; | |
3593 | } | |
3594 | /* Fall Through since DCA is disabled. */ | |
3595 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 3596 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
3597 | /* without this a class_device is left |
3598 | * hanging around in the sysfs model */ | |
3599 | dca_remove_requester(dev); | |
3600 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); | |
7dfc16fa | 3601 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 3602 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
3603 | } |
3604 | break; | |
3605 | } | |
bbd98fe4 | 3606 | |
fe4506b6 | 3607 | return 0; |
9d5c8243 AK |
3608 | } |
3609 | ||
fe4506b6 JC |
3610 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
3611 | void *p) | |
3612 | { | |
3613 | int ret_val; | |
3614 | ||
3615 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
3616 | __igb_notify_dca); | |
3617 | ||
3618 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
3619 | } | |
421e02f0 | 3620 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 AK |
3621 | |
3622 | /** | |
3623 | * igb_intr_msi - Interrupt Handler | |
3624 | * @irq: interrupt number | |
3625 | * @data: pointer to a network interface device structure | |
3626 | **/ | |
3627 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
3628 | { | |
3629 | struct net_device *netdev = data; | |
3630 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
3631 | struct e1000_hw *hw = &adapter->hw; |
3632 | /* read ICR disables interrupts using IAM */ | |
3633 | u32 icr = rd32(E1000_ICR); | |
3634 | ||
6eb5a7f1 | 3635 | igb_write_itr(adapter->rx_ring); |
9d5c8243 | 3636 | |
dda0e083 AD |
3637 | if(icr & E1000_ICR_DOUTSYNC) { |
3638 | /* HW is reporting DMA is out of sync */ | |
3639 | adapter->stats.doosync++; | |
3640 | } | |
3641 | ||
9d5c8243 AK |
3642 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
3643 | hw->mac.get_link_status = 1; | |
3644 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3645 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3646 | } | |
3647 | ||
288379f0 | 3648 | napi_schedule(&adapter->rx_ring[0].napi); |
9d5c8243 AK |
3649 | |
3650 | return IRQ_HANDLED; | |
3651 | } | |
3652 | ||
3653 | /** | |
4a3c6433 | 3654 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
3655 | * @irq: interrupt number |
3656 | * @data: pointer to a network interface device structure | |
3657 | **/ | |
3658 | static irqreturn_t igb_intr(int irq, void *data) | |
3659 | { | |
3660 | struct net_device *netdev = data; | |
3661 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
3662 | struct e1000_hw *hw = &adapter->hw; |
3663 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
3664 | * need for the IMC write */ | |
3665 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
3666 | if (!icr) |
3667 | return IRQ_NONE; /* Not our interrupt */ | |
3668 | ||
6eb5a7f1 | 3669 | igb_write_itr(adapter->rx_ring); |
9d5c8243 AK |
3670 | |
3671 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
3672 | * not set, then the adapter didn't send an interrupt */ | |
3673 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
3674 | return IRQ_NONE; | |
3675 | ||
dda0e083 AD |
3676 | if(icr & E1000_ICR_DOUTSYNC) { |
3677 | /* HW is reporting DMA is out of sync */ | |
3678 | adapter->stats.doosync++; | |
3679 | } | |
3680 | ||
9d5c8243 AK |
3681 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
3682 | hw->mac.get_link_status = 1; | |
3683 | /* guard against interrupt when we're going down */ | |
3684 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3685 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3686 | } | |
3687 | ||
288379f0 | 3688 | napi_schedule(&adapter->rx_ring[0].napi); |
9d5c8243 AK |
3689 | |
3690 | return IRQ_HANDLED; | |
3691 | } | |
3692 | ||
3693 | /** | |
661086df PWJ |
3694 | * igb_poll - NAPI Rx polling callback |
3695 | * @napi: napi polling structure | |
3696 | * @budget: count of how many packets we should handle | |
9d5c8243 | 3697 | **/ |
661086df | 3698 | static int igb_poll(struct napi_struct *napi, int budget) |
9d5c8243 | 3699 | { |
661086df PWJ |
3700 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); |
3701 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 3702 | struct net_device *netdev = adapter->netdev; |
661086df | 3703 | int tx_clean_complete, work_done = 0; |
9d5c8243 | 3704 | |
661086df | 3705 | /* this poll routine only supports one tx and one rx queue */ |
421e02f0 | 3706 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3707 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3708 | igb_update_tx_dca(&adapter->tx_ring[0]); |
3709 | #endif | |
661086df | 3710 | tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]); |
fe4506b6 | 3711 | |
421e02f0 | 3712 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3713 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3714 | igb_update_rx_dca(&adapter->rx_ring[0]); |
3715 | #endif | |
661086df | 3716 | igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget); |
9d5c8243 AK |
3717 | |
3718 | /* If no Tx and not enough Rx work done, exit the polling mode */ | |
3719 | if ((tx_clean_complete && (work_done < budget)) || | |
3720 | !netif_running(netdev)) { | |
9d5c8243 | 3721 | if (adapter->itr_setting & 3) |
6eb5a7f1 | 3722 | igb_set_itr(adapter); |
288379f0 | 3723 | napi_complete(napi); |
9d5c8243 AK |
3724 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3725 | igb_irq_enable(adapter); | |
3726 | return 0; | |
3727 | } | |
3728 | ||
3729 | return 1; | |
3730 | } | |
3731 | ||
3732 | static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget) | |
3733 | { | |
3734 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); | |
3735 | struct igb_adapter *adapter = rx_ring->adapter; | |
3736 | struct e1000_hw *hw = &adapter->hw; | |
3737 | struct net_device *netdev = adapter->netdev; | |
3738 | int work_done = 0; | |
3739 | ||
421e02f0 | 3740 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3741 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3742 | igb_update_rx_dca(rx_ring); |
3743 | #endif | |
3b644cf6 | 3744 | igb_clean_rx_irq_adv(rx_ring, &work_done, budget); |
9d5c8243 | 3745 | |
9d5c8243 AK |
3746 | /* If not enough Rx work done, exit the polling mode */ |
3747 | if ((work_done == 0) || !netif_running(netdev)) { | |
288379f0 | 3748 | napi_complete(napi); |
9d5c8243 | 3749 | |
6eb5a7f1 AD |
3750 | if (adapter->itr_setting & 3) { |
3751 | if (adapter->num_rx_queues == 1) | |
3752 | igb_set_itr(adapter); | |
3753 | else | |
3754 | igb_update_ring_itr(rx_ring); | |
9d5c8243 | 3755 | } |
844290e5 PW |
3756 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3757 | wr32(E1000_EIMS, rx_ring->eims_value); | |
3758 | ||
9d5c8243 AK |
3759 | return 0; |
3760 | } | |
3761 | ||
3762 | return 1; | |
3763 | } | |
6d8126f9 | 3764 | |
33af6bcc PO |
3765 | /** |
3766 | * igb_hwtstamp - utility function which checks for TX time stamp | |
3767 | * @adapter: board private structure | |
3768 | * @skb: packet that was just sent | |
3769 | * | |
3770 | * If we were asked to do hardware stamping and such a time stamp is | |
3771 | * available, then it must have been for this skb here because we only | |
3772 | * allow only one such packet into the queue. | |
3773 | */ | |
3774 | static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb) | |
3775 | { | |
3776 | union skb_shared_tx *shtx = skb_tx(skb); | |
3777 | struct e1000_hw *hw = &adapter->hw; | |
3778 | ||
3779 | if (unlikely(shtx->hardware)) { | |
3780 | u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID; | |
3781 | if (valid) { | |
3782 | u64 regval = rd32(E1000_TXSTMPL); | |
3783 | u64 ns; | |
3784 | struct skb_shared_hwtstamps shhwtstamps; | |
3785 | ||
3786 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
3787 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
3788 | ns = timecounter_cyc2time(&adapter->clock, | |
3789 | regval); | |
3790 | timecompare_update(&adapter->compare, ns); | |
3791 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
3792 | shhwtstamps.syststamp = | |
3793 | timecompare_transform(&adapter->compare, ns); | |
3794 | skb_tstamp_tx(skb, &shhwtstamps); | |
3795 | } | |
3796 | ||
3797 | /* delayed orphaning: skb_tstamp_tx() needs the socket */ | |
3798 | skb_orphan(skb); | |
3799 | } | |
3800 | } | |
3801 | ||
9d5c8243 AK |
3802 | /** |
3803 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
3804 | * @adapter: board private structure | |
3805 | * returns true if ring is completely cleaned | |
3806 | **/ | |
3b644cf6 | 3807 | static bool igb_clean_tx_irq(struct igb_ring *tx_ring) |
9d5c8243 | 3808 | { |
3b644cf6 | 3809 | struct igb_adapter *adapter = tx_ring->adapter; |
3b644cf6 | 3810 | struct net_device *netdev = adapter->netdev; |
0e014cb1 | 3811 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3812 | struct igb_buffer *buffer_info; |
3813 | struct sk_buff *skb; | |
0e014cb1 | 3814 | union e1000_adv_tx_desc *tx_desc, *eop_desc; |
9d5c8243 | 3815 | unsigned int total_bytes = 0, total_packets = 0; |
0e014cb1 AD |
3816 | unsigned int i, eop, count = 0; |
3817 | bool cleaned = false; | |
9d5c8243 | 3818 | |
9d5c8243 | 3819 | i = tx_ring->next_to_clean; |
0e014cb1 AD |
3820 | eop = tx_ring->buffer_info[i].next_to_watch; |
3821 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
3822 | ||
3823 | while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) && | |
3824 | (count < tx_ring->count)) { | |
3825 | for (cleaned = false; !cleaned; count++) { | |
3826 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
9d5c8243 | 3827 | buffer_info = &tx_ring->buffer_info[i]; |
0e014cb1 | 3828 | cleaned = (i == eop); |
9d5c8243 AK |
3829 | skb = buffer_info->skb; |
3830 | ||
3831 | if (skb) { | |
3832 | unsigned int segs, bytecount; | |
3833 | /* gso_segs is currently only valid for tcp */ | |
3834 | segs = skb_shinfo(skb)->gso_segs ?: 1; | |
3835 | /* multiply data chunks by size of headers */ | |
3836 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
3837 | skb->len; | |
3838 | total_packets += segs; | |
3839 | total_bytes += bytecount; | |
33af6bcc PO |
3840 | |
3841 | igb_tx_hwtstamp(adapter, skb); | |
9d5c8243 AK |
3842 | } |
3843 | ||
3844 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
0e014cb1 | 3845 | tx_desc->wb.status = 0; |
9d5c8243 AK |
3846 | |
3847 | i++; | |
3848 | if (i == tx_ring->count) | |
3849 | i = 0; | |
9d5c8243 | 3850 | } |
0e014cb1 AD |
3851 | eop = tx_ring->buffer_info[i].next_to_watch; |
3852 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
3853 | } | |
3854 | ||
9d5c8243 AK |
3855 | tx_ring->next_to_clean = i; |
3856 | ||
fc7d345d | 3857 | if (unlikely(count && |
9d5c8243 AK |
3858 | netif_carrier_ok(netdev) && |
3859 | IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) { | |
3860 | /* Make sure that anybody stopping the queue after this | |
3861 | * sees the new next_to_clean. | |
3862 | */ | |
3863 | smp_mb(); | |
661086df PWJ |
3864 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
3865 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
3866 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
3867 | ++adapter->restart_queue; | |
3868 | } | |
9d5c8243 AK |
3869 | } |
3870 | ||
3871 | if (tx_ring->detect_tx_hung) { | |
3872 | /* Detect a transmit hang in hardware, this serializes the | |
3873 | * check with the clearing of time_stamp and movement of i */ | |
3874 | tx_ring->detect_tx_hung = false; | |
3875 | if (tx_ring->buffer_info[i].time_stamp && | |
3876 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | |
3877 | (adapter->tx_timeout_factor * HZ)) | |
3878 | && !(rd32(E1000_STATUS) & | |
3879 | E1000_STATUS_TXOFF)) { | |
3880 | ||
9d5c8243 AK |
3881 | /* detected Tx unit hang */ |
3882 | dev_err(&adapter->pdev->dev, | |
3883 | "Detected Tx Unit Hang\n" | |
2d064c06 | 3884 | " Tx Queue <%d>\n" |
9d5c8243 AK |
3885 | " TDH <%x>\n" |
3886 | " TDT <%x>\n" | |
3887 | " next_to_use <%x>\n" | |
3888 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
3889 | "buffer_info[next_to_clean]\n" |
3890 | " time_stamp <%lx>\n" | |
0e014cb1 | 3891 | " next_to_watch <%x>\n" |
9d5c8243 AK |
3892 | " jiffies <%lx>\n" |
3893 | " desc.status <%x>\n", | |
2d064c06 | 3894 | tx_ring->queue_index, |
9d5c8243 AK |
3895 | readl(adapter->hw.hw_addr + tx_ring->head), |
3896 | readl(adapter->hw.hw_addr + tx_ring->tail), | |
3897 | tx_ring->next_to_use, | |
3898 | tx_ring->next_to_clean, | |
9d5c8243 | 3899 | tx_ring->buffer_info[i].time_stamp, |
0e014cb1 | 3900 | eop, |
9d5c8243 | 3901 | jiffies, |
0e014cb1 | 3902 | eop_desc->wb.status); |
661086df | 3903 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
3904 | } |
3905 | } | |
3906 | tx_ring->total_bytes += total_bytes; | |
3907 | tx_ring->total_packets += total_packets; | |
e21ed353 AD |
3908 | tx_ring->tx_stats.bytes += total_bytes; |
3909 | tx_ring->tx_stats.packets += total_packets; | |
9d5c8243 AK |
3910 | adapter->net_stats.tx_bytes += total_bytes; |
3911 | adapter->net_stats.tx_packets += total_packets; | |
0e014cb1 | 3912 | return (count < tx_ring->count); |
9d5c8243 AK |
3913 | } |
3914 | ||
9d5c8243 AK |
3915 | /** |
3916 | * igb_receive_skb - helper function to handle rx indications | |
eebbbdba | 3917 | * @ring: pointer to receive ring receving this packet |
9d5c8243 | 3918 | * @status: descriptor status field as written by hardware |
73cd78f1 | 3919 | * @rx_desc: receive descriptor containing vlan and type information. |
9d5c8243 AK |
3920 | * @skb: pointer to sk_buff to be indicated to stack |
3921 | **/ | |
d3352520 AD |
3922 | static void igb_receive_skb(struct igb_ring *ring, u8 status, |
3923 | union e1000_adv_rx_desc * rx_desc, | |
3924 | struct sk_buff *skb) | |
3925 | { | |
3926 | struct igb_adapter * adapter = ring->adapter; | |
3927 | bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP)); | |
3928 | ||
0c8dfc83 | 3929 | skb_record_rx_queue(skb, ring->queue_index); |
5c0999b7 | 3930 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) { |
d3352520 | 3931 | if (vlan_extracted) |
5c0999b7 HX |
3932 | vlan_gro_receive(&ring->napi, adapter->vlgrp, |
3933 | le16_to_cpu(rx_desc->wb.upper.vlan), | |
3934 | skb); | |
d3352520 | 3935 | else |
5c0999b7 | 3936 | napi_gro_receive(&ring->napi, skb); |
d3352520 | 3937 | } else { |
d3352520 AD |
3938 | if (vlan_extracted) |
3939 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | |
3940 | le16_to_cpu(rx_desc->wb.upper.vlan)); | |
3941 | else | |
d3352520 | 3942 | netif_receive_skb(skb); |
d3352520 | 3943 | } |
9d5c8243 AK |
3944 | } |
3945 | ||
9d5c8243 AK |
3946 | static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, |
3947 | u32 status_err, struct sk_buff *skb) | |
3948 | { | |
3949 | skb->ip_summed = CHECKSUM_NONE; | |
3950 | ||
3951 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
3952 | if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum) | |
3953 | return; | |
3954 | /* TCP/UDP checksum error bit is set */ | |
3955 | if (status_err & | |
3956 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
3957 | /* let the stack verify checksum errors */ | |
3958 | adapter->hw_csum_err++; | |
3959 | return; | |
3960 | } | |
3961 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3962 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
3963 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3964 | ||
3965 | adapter->hw_csum_good++; | |
3966 | } | |
3967 | ||
3b644cf6 MW |
3968 | static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, |
3969 | int *work_done, int budget) | |
9d5c8243 | 3970 | { |
3b644cf6 | 3971 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 | 3972 | struct net_device *netdev = adapter->netdev; |
33af6bcc | 3973 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3974 | struct pci_dev *pdev = adapter->pdev; |
3975 | union e1000_adv_rx_desc *rx_desc , *next_rxd; | |
3976 | struct igb_buffer *buffer_info , *next_buffer; | |
3977 | struct sk_buff *skb; | |
9d5c8243 AK |
3978 | bool cleaned = false; |
3979 | int cleaned_count = 0; | |
3980 | unsigned int total_bytes = 0, total_packets = 0; | |
73cd78f1 AD |
3981 | unsigned int i; |
3982 | u32 length, hlen, staterr; | |
9d5c8243 AK |
3983 | |
3984 | i = rx_ring->next_to_clean; | |
69d3ca53 | 3985 | buffer_info = &rx_ring->buffer_info[i]; |
9d5c8243 AK |
3986 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); |
3987 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
3988 | ||
3989 | while (staterr & E1000_RXD_STAT_DD) { | |
3990 | if (*work_done >= budget) | |
3991 | break; | |
3992 | (*work_done)++; | |
9d5c8243 | 3993 | |
69d3ca53 AD |
3994 | skb = buffer_info->skb; |
3995 | prefetch(skb->data - NET_IP_ALIGN); | |
3996 | buffer_info->skb = NULL; | |
3997 | ||
3998 | i++; | |
3999 | if (i == rx_ring->count) | |
4000 | i = 0; | |
4001 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); | |
4002 | prefetch(next_rxd); | |
4003 | next_buffer = &rx_ring->buffer_info[i]; | |
9d5c8243 AK |
4004 | |
4005 | length = le16_to_cpu(rx_desc->wb.upper.length); | |
4006 | cleaned = true; | |
4007 | cleaned_count++; | |
4008 | ||
bf36c1a0 AD |
4009 | if (!adapter->rx_ps_hdr_size) { |
4010 | pci_unmap_single(pdev, buffer_info->dma, | |
4011 | adapter->rx_buffer_len + | |
4012 | NET_IP_ALIGN, | |
4013 | PCI_DMA_FROMDEVICE); | |
4014 | skb_put(skb, length); | |
4015 | goto send_up; | |
9d5c8243 AK |
4016 | } |
4017 | ||
69d3ca53 AD |
4018 | /* HW will not DMA in data larger than the given buffer, even |
4019 | * if it parses the (NFS, of course) header to be larger. In | |
4020 | * that case, it fills the header buffer and spills the rest | |
4021 | * into the page. | |
4022 | */ | |
4023 | hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | |
4024 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
4025 | if (hlen > adapter->rx_ps_hdr_size) | |
4026 | hlen = adapter->rx_ps_hdr_size; | |
4027 | ||
bf36c1a0 AD |
4028 | if (!skb_shinfo(skb)->nr_frags) { |
4029 | pci_unmap_single(pdev, buffer_info->dma, | |
73cd78f1 | 4030 | adapter->rx_ps_hdr_size + NET_IP_ALIGN, |
bf36c1a0 AD |
4031 | PCI_DMA_FROMDEVICE); |
4032 | skb_put(skb, hlen); | |
4033 | } | |
4034 | ||
4035 | if (length) { | |
9d5c8243 | 4036 | pci_unmap_page(pdev, buffer_info->page_dma, |
bf36c1a0 | 4037 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9d5c8243 | 4038 | buffer_info->page_dma = 0; |
bf36c1a0 AD |
4039 | |
4040 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++, | |
4041 | buffer_info->page, | |
4042 | buffer_info->page_offset, | |
4043 | length); | |
4044 | ||
4045 | if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) || | |
4046 | (page_count(buffer_info->page) != 1)) | |
4047 | buffer_info->page = NULL; | |
4048 | else | |
4049 | get_page(buffer_info->page); | |
9d5c8243 AK |
4050 | |
4051 | skb->len += length; | |
4052 | skb->data_len += length; | |
9d5c8243 | 4053 | |
bf36c1a0 | 4054 | skb->truesize += length; |
9d5c8243 | 4055 | } |
9d5c8243 | 4056 | |
bf36c1a0 | 4057 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
b2d56536 AD |
4058 | buffer_info->skb = next_buffer->skb; |
4059 | buffer_info->dma = next_buffer->dma; | |
4060 | next_buffer->skb = skb; | |
4061 | next_buffer->dma = 0; | |
bf36c1a0 AD |
4062 | goto next_desc; |
4063 | } | |
69d3ca53 | 4064 | send_up: |
33af6bcc PO |
4065 | /* |
4066 | * If this bit is set, then the RX registers contain | |
4067 | * the time stamp. No other packet will be time | |
4068 | * stamped until we read these registers, so read the | |
4069 | * registers to make them available again. Because | |
4070 | * only one packet can be time stamped at a time, we | |
4071 | * know that the register values must belong to this | |
4072 | * one here and therefore we don't need to compare | |
4073 | * any of the additional attributes stored for it. | |
4074 | * | |
4075 | * If nothing went wrong, then it should have a | |
4076 | * skb_shared_tx that we can turn into a | |
4077 | * skb_shared_hwtstamps. | |
4078 | * | |
4079 | * TODO: can time stamping be triggered (thus locking | |
4080 | * the registers) without the packet reaching this point | |
4081 | * here? In that case RX time stamping would get stuck. | |
4082 | * | |
4083 | * TODO: in "time stamp all packets" mode this bit is | |
4084 | * not set. Need a global flag for this mode and then | |
4085 | * always read the registers. Cannot be done without | |
4086 | * a race condition. | |
4087 | */ | |
4088 | if (unlikely(staterr & E1000_RXD_STAT_TS)) { | |
4089 | u64 regval; | |
4090 | u64 ns; | |
4091 | struct skb_shared_hwtstamps *shhwtstamps = | |
4092 | skb_hwtstamps(skb); | |
4093 | ||
4094 | WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID), | |
4095 | "igb: no RX time stamp available for time stamped packet"); | |
4096 | regval = rd32(E1000_RXSTMPL); | |
4097 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
4098 | ns = timecounter_cyc2time(&adapter->clock, regval); | |
4099 | timecompare_update(&adapter->compare, ns); | |
4100 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
4101 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
4102 | shhwtstamps->syststamp = | |
4103 | timecompare_transform(&adapter->compare, ns); | |
4104 | } | |
4105 | ||
9d5c8243 AK |
4106 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
4107 | dev_kfree_skb_irq(skb); | |
4108 | goto next_desc; | |
4109 | } | |
9d5c8243 AK |
4110 | |
4111 | total_bytes += skb->len; | |
4112 | total_packets++; | |
4113 | ||
4114 | igb_rx_checksum_adv(adapter, staterr, skb); | |
4115 | ||
4116 | skb->protocol = eth_type_trans(skb, netdev); | |
4117 | ||
d3352520 | 4118 | igb_receive_skb(rx_ring, staterr, rx_desc, skb); |
9d5c8243 | 4119 | |
9d5c8243 AK |
4120 | next_desc: |
4121 | rx_desc->wb.upper.status_error = 0; | |
4122 | ||
4123 | /* return some buffers to hardware, one at a time is too slow */ | |
4124 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
3b644cf6 | 4125 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
4126 | cleaned_count = 0; |
4127 | } | |
4128 | ||
4129 | /* use prefetched values */ | |
4130 | rx_desc = next_rxd; | |
4131 | buffer_info = next_buffer; | |
9d5c8243 AK |
4132 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
4133 | } | |
bf36c1a0 | 4134 | |
9d5c8243 AK |
4135 | rx_ring->next_to_clean = i; |
4136 | cleaned_count = IGB_DESC_UNUSED(rx_ring); | |
4137 | ||
4138 | if (cleaned_count) | |
3b644cf6 | 4139 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
4140 | |
4141 | rx_ring->total_packets += total_packets; | |
4142 | rx_ring->total_bytes += total_bytes; | |
4143 | rx_ring->rx_stats.packets += total_packets; | |
4144 | rx_ring->rx_stats.bytes += total_bytes; | |
4145 | adapter->net_stats.rx_bytes += total_bytes; | |
4146 | adapter->net_stats.rx_packets += total_packets; | |
4147 | return cleaned; | |
4148 | } | |
4149 | ||
9d5c8243 AK |
4150 | /** |
4151 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | |
4152 | * @adapter: address of board private structure | |
4153 | **/ | |
3b644cf6 | 4154 | static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, |
9d5c8243 AK |
4155 | int cleaned_count) |
4156 | { | |
3b644cf6 | 4157 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
4158 | struct net_device *netdev = adapter->netdev; |
4159 | struct pci_dev *pdev = adapter->pdev; | |
4160 | union e1000_adv_rx_desc *rx_desc; | |
4161 | struct igb_buffer *buffer_info; | |
4162 | struct sk_buff *skb; | |
4163 | unsigned int i; | |
db761762 | 4164 | int bufsz; |
9d5c8243 AK |
4165 | |
4166 | i = rx_ring->next_to_use; | |
4167 | buffer_info = &rx_ring->buffer_info[i]; | |
4168 | ||
db761762 AD |
4169 | if (adapter->rx_ps_hdr_size) |
4170 | bufsz = adapter->rx_ps_hdr_size; | |
4171 | else | |
4172 | bufsz = adapter->rx_buffer_len; | |
4173 | bufsz += NET_IP_ALIGN; | |
4174 | ||
9d5c8243 AK |
4175 | while (cleaned_count--) { |
4176 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
4177 | ||
bf36c1a0 | 4178 | if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) { |
9d5c8243 | 4179 | if (!buffer_info->page) { |
bf36c1a0 AD |
4180 | buffer_info->page = alloc_page(GFP_ATOMIC); |
4181 | if (!buffer_info->page) { | |
4182 | adapter->alloc_rx_buff_failed++; | |
4183 | goto no_buffers; | |
4184 | } | |
4185 | buffer_info->page_offset = 0; | |
4186 | } else { | |
4187 | buffer_info->page_offset ^= PAGE_SIZE / 2; | |
9d5c8243 AK |
4188 | } |
4189 | buffer_info->page_dma = | |
db761762 | 4190 | pci_map_page(pdev, buffer_info->page, |
bf36c1a0 AD |
4191 | buffer_info->page_offset, |
4192 | PAGE_SIZE / 2, | |
9d5c8243 AK |
4193 | PCI_DMA_FROMDEVICE); |
4194 | } | |
4195 | ||
4196 | if (!buffer_info->skb) { | |
9d5c8243 | 4197 | skb = netdev_alloc_skb(netdev, bufsz); |
9d5c8243 AK |
4198 | if (!skb) { |
4199 | adapter->alloc_rx_buff_failed++; | |
4200 | goto no_buffers; | |
4201 | } | |
4202 | ||
4203 | /* Make buffer alignment 2 beyond a 16 byte boundary | |
4204 | * this will result in a 16 byte aligned IP header after | |
4205 | * the 14 byte MAC header is removed | |
4206 | */ | |
4207 | skb_reserve(skb, NET_IP_ALIGN); | |
4208 | ||
4209 | buffer_info->skb = skb; | |
4210 | buffer_info->dma = pci_map_single(pdev, skb->data, | |
4211 | bufsz, | |
4212 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
4213 | } |
4214 | /* Refresh the desc even if buffer_addrs didn't change because | |
4215 | * each write-back erases this info. */ | |
4216 | if (adapter->rx_ps_hdr_size) { | |
4217 | rx_desc->read.pkt_addr = | |
4218 | cpu_to_le64(buffer_info->page_dma); | |
4219 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | |
4220 | } else { | |
4221 | rx_desc->read.pkt_addr = | |
4222 | cpu_to_le64(buffer_info->dma); | |
4223 | rx_desc->read.hdr_addr = 0; | |
4224 | } | |
4225 | ||
4226 | i++; | |
4227 | if (i == rx_ring->count) | |
4228 | i = 0; | |
4229 | buffer_info = &rx_ring->buffer_info[i]; | |
4230 | } | |
4231 | ||
4232 | no_buffers: | |
4233 | if (rx_ring->next_to_use != i) { | |
4234 | rx_ring->next_to_use = i; | |
4235 | if (i == 0) | |
4236 | i = (rx_ring->count - 1); | |
4237 | else | |
4238 | i--; | |
4239 | ||
4240 | /* Force memory writes to complete before letting h/w | |
4241 | * know there are new descriptors to fetch. (Only | |
4242 | * applicable for weak-ordered memory model archs, | |
4243 | * such as IA-64). */ | |
4244 | wmb(); | |
4245 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
4246 | } | |
4247 | } | |
4248 | ||
4249 | /** | |
4250 | * igb_mii_ioctl - | |
4251 | * @netdev: | |
4252 | * @ifreq: | |
4253 | * @cmd: | |
4254 | **/ | |
4255 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4256 | { | |
4257 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4258 | struct mii_ioctl_data *data = if_mii(ifr); | |
4259 | ||
4260 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
4261 | return -EOPNOTSUPP; | |
4262 | ||
4263 | switch (cmd) { | |
4264 | case SIOCGMIIPHY: | |
4265 | data->phy_id = adapter->hw.phy.addr; | |
4266 | break; | |
4267 | case SIOCGMIIREG: | |
4268 | if (!capable(CAP_NET_ADMIN)) | |
4269 | return -EPERM; | |
f5f4cf08 AD |
4270 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
4271 | &data->val_out)) | |
9d5c8243 AK |
4272 | return -EIO; |
4273 | break; | |
4274 | case SIOCSMIIREG: | |
4275 | default: | |
4276 | return -EOPNOTSUPP; | |
4277 | } | |
4278 | return 0; | |
4279 | } | |
4280 | ||
c6cb090b PO |
4281 | /** |
4282 | * igb_hwtstamp_ioctl - control hardware time stamping | |
4283 | * @netdev: | |
4284 | * @ifreq: | |
4285 | * @cmd: | |
4286 | * | |
33af6bcc PO |
4287 | * Outgoing time stamping can be enabled and disabled. Play nice and |
4288 | * disable it when requested, although it shouldn't case any overhead | |
4289 | * when no packet needs it. At most one packet in the queue may be | |
4290 | * marked for time stamping, otherwise it would be impossible to tell | |
4291 | * for sure to which packet the hardware time stamp belongs. | |
4292 | * | |
4293 | * Incoming time stamping has to be configured via the hardware | |
4294 | * filters. Not all combinations are supported, in particular event | |
4295 | * type has to be specified. Matching the kind of event packet is | |
4296 | * not supported, with the exception of "all V2 events regardless of | |
4297 | * level 2 or 4". | |
4298 | * | |
c6cb090b PO |
4299 | **/ |
4300 | static int igb_hwtstamp_ioctl(struct net_device *netdev, | |
4301 | struct ifreq *ifr, int cmd) | |
4302 | { | |
33af6bcc PO |
4303 | struct igb_adapter *adapter = netdev_priv(netdev); |
4304 | struct e1000_hw *hw = &adapter->hw; | |
c6cb090b | 4305 | struct hwtstamp_config config; |
33af6bcc PO |
4306 | u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; |
4307 | u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED; | |
4308 | u32 tsync_rx_ctl_type = 0; | |
4309 | u32 tsync_rx_cfg = 0; | |
4310 | int is_l4 = 0; | |
4311 | int is_l2 = 0; | |
4312 | short port = 319; /* PTP */ | |
4313 | u32 regval; | |
c6cb090b PO |
4314 | |
4315 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
4316 | return -EFAULT; | |
4317 | ||
4318 | /* reserved for future extensions */ | |
4319 | if (config.flags) | |
4320 | return -EINVAL; | |
4321 | ||
33af6bcc PO |
4322 | switch (config.tx_type) { |
4323 | case HWTSTAMP_TX_OFF: | |
4324 | tsync_tx_ctl_bit = 0; | |
4325 | break; | |
4326 | case HWTSTAMP_TX_ON: | |
4327 | tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; | |
4328 | break; | |
4329 | default: | |
4330 | return -ERANGE; | |
4331 | } | |
4332 | ||
4333 | switch (config.rx_filter) { | |
4334 | case HWTSTAMP_FILTER_NONE: | |
4335 | tsync_rx_ctl_bit = 0; | |
4336 | break; | |
4337 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
4338 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
4339 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
4340 | case HWTSTAMP_FILTER_ALL: | |
4341 | /* | |
4342 | * register TSYNCRXCFG must be set, therefore it is not | |
4343 | * possible to time stamp both Sync and Delay_Req messages | |
4344 | * => fall back to time stamping all packets | |
4345 | */ | |
4346 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL; | |
4347 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
4348 | break; | |
4349 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
4350 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | |
4351 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
4352 | is_l4 = 1; | |
4353 | break; | |
4354 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
4355 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | |
4356 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
4357 | is_l4 = 1; | |
4358 | break; | |
4359 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
4360 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
4361 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
4362 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; | |
4363 | is_l2 = 1; | |
4364 | is_l4 = 1; | |
4365 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
4366 | break; | |
4367 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
4368 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
4369 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
4370 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; | |
4371 | is_l2 = 1; | |
4372 | is_l4 = 1; | |
4373 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
4374 | break; | |
4375 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
4376 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
4377 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
4378 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2; | |
4379 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
4380 | is_l2 = 1; | |
4381 | break; | |
4382 | default: | |
4383 | return -ERANGE; | |
4384 | } | |
4385 | ||
4386 | /* enable/disable TX */ | |
4387 | regval = rd32(E1000_TSYNCTXCTL); | |
4388 | regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit; | |
4389 | wr32(E1000_TSYNCTXCTL, regval); | |
4390 | ||
4391 | /* enable/disable RX, define which PTP packets are time stamped */ | |
4392 | regval = rd32(E1000_TSYNCRXCTL); | |
4393 | regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit; | |
4394 | regval = (regval & ~0xE) | tsync_rx_ctl_type; | |
4395 | wr32(E1000_TSYNCRXCTL, regval); | |
4396 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
4397 | ||
4398 | /* | |
4399 | * Ethertype Filter Queue Filter[0][15:0] = 0x88F7 | |
4400 | * (Ethertype to filter on) | |
4401 | * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter) | |
4402 | * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping) | |
4403 | */ | |
4404 | wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0); | |
4405 | ||
4406 | /* L4 Queue Filter[0]: only filter by source and destination port */ | |
4407 | wr32(E1000_SPQF0, htons(port)); | |
4408 | wr32(E1000_IMIREXT(0), is_l4 ? | |
4409 | ((1<<12) | (1<<19) /* bypass size and control flags */) : 0); | |
4410 | wr32(E1000_IMIR(0), is_l4 ? | |
4411 | (htons(port) | |
4412 | | (0<<16) /* immediate interrupt disabled */ | |
4413 | | 0 /* (1<<17) bit cleared: do not bypass | |
4414 | destination port check */) | |
4415 | : 0); | |
4416 | wr32(E1000_FTQF0, is_l4 ? | |
4417 | (0x11 /* UDP */ | |
4418 | | (1<<15) /* VF not compared */ | |
4419 | | (1<<27) /* Enable Timestamping */ | |
4420 | | (7<<28) /* only source port filter enabled, | |
4421 | source/target address and protocol | |
4422 | masked */) | |
4423 | : ((1<<15) | (15<<28) /* all mask bits set = filter not | |
4424 | enabled */)); | |
4425 | ||
4426 | wrfl(); | |
4427 | ||
4428 | adapter->hwtstamp_config = config; | |
4429 | ||
4430 | /* clear TX/RX time stamp registers, just to be sure */ | |
4431 | regval = rd32(E1000_TXSTMPH); | |
4432 | regval = rd32(E1000_RXSTMPH); | |
c6cb090b | 4433 | |
33af6bcc PO |
4434 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
4435 | -EFAULT : 0; | |
c6cb090b PO |
4436 | } |
4437 | ||
9d5c8243 AK |
4438 | /** |
4439 | * igb_ioctl - | |
4440 | * @netdev: | |
4441 | * @ifreq: | |
4442 | * @cmd: | |
4443 | **/ | |
4444 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4445 | { | |
4446 | switch (cmd) { | |
4447 | case SIOCGMIIPHY: | |
4448 | case SIOCGMIIREG: | |
4449 | case SIOCSMIIREG: | |
4450 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b PO |
4451 | case SIOCSHWTSTAMP: |
4452 | return igb_hwtstamp_ioctl(netdev, ifr, cmd); | |
9d5c8243 AK |
4453 | default: |
4454 | return -EOPNOTSUPP; | |
4455 | } | |
4456 | } | |
4457 | ||
4458 | static void igb_vlan_rx_register(struct net_device *netdev, | |
4459 | struct vlan_group *grp) | |
4460 | { | |
4461 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4462 | struct e1000_hw *hw = &adapter->hw; | |
4463 | u32 ctrl, rctl; | |
4464 | ||
4465 | igb_irq_disable(adapter); | |
4466 | adapter->vlgrp = grp; | |
4467 | ||
4468 | if (grp) { | |
4469 | /* enable VLAN tag insert/strip */ | |
4470 | ctrl = rd32(E1000_CTRL); | |
4471 | ctrl |= E1000_CTRL_VME; | |
4472 | wr32(E1000_CTRL, ctrl); | |
4473 | ||
4474 | /* enable VLAN receive filtering */ | |
4475 | rctl = rd32(E1000_RCTL); | |
9d5c8243 AK |
4476 | rctl &= ~E1000_RCTL_CFIEN; |
4477 | wr32(E1000_RCTL, rctl); | |
4478 | igb_update_mng_vlan(adapter); | |
4479 | wr32(E1000_RLPML, | |
4480 | adapter->max_frame_size + VLAN_TAG_SIZE); | |
4481 | } else { | |
4482 | /* disable VLAN tag insert/strip */ | |
4483 | ctrl = rd32(E1000_CTRL); | |
4484 | ctrl &= ~E1000_CTRL_VME; | |
4485 | wr32(E1000_CTRL, ctrl); | |
4486 | ||
9d5c8243 AK |
4487 | if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { |
4488 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
4489 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
4490 | } | |
4491 | wr32(E1000_RLPML, | |
4492 | adapter->max_frame_size); | |
4493 | } | |
4494 | ||
4495 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4496 | igb_irq_enable(adapter); | |
4497 | } | |
4498 | ||
4499 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
4500 | { | |
4501 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4502 | struct e1000_hw *hw = &adapter->hw; | |
4503 | u32 vfta, index; | |
4504 | ||
28b0759c | 4505 | if ((hw->mng_cookie.status & |
9d5c8243 AK |
4506 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && |
4507 | (vid == adapter->mng_vlan_id)) | |
4508 | return; | |
4509 | /* add VID to filter table */ | |
4510 | index = (vid >> 5) & 0x7F; | |
4511 | vfta = array_rd32(E1000_VFTA, index); | |
4512 | vfta |= (1 << (vid & 0x1F)); | |
4513 | igb_write_vfta(&adapter->hw, index, vfta); | |
4514 | } | |
4515 | ||
4516 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
4517 | { | |
4518 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4519 | struct e1000_hw *hw = &adapter->hw; | |
4520 | u32 vfta, index; | |
4521 | ||
4522 | igb_irq_disable(adapter); | |
4523 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
4524 | ||
4525 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4526 | igb_irq_enable(adapter); | |
4527 | ||
4528 | if ((adapter->hw.mng_cookie.status & | |
4529 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
4530 | (vid == adapter->mng_vlan_id)) { | |
4531 | /* release control to f/w */ | |
4532 | igb_release_hw_control(adapter); | |
4533 | return; | |
4534 | } | |
4535 | ||
4536 | /* remove VID from filter table */ | |
4537 | index = (vid >> 5) & 0x7F; | |
4538 | vfta = array_rd32(E1000_VFTA, index); | |
4539 | vfta &= ~(1 << (vid & 0x1F)); | |
4540 | igb_write_vfta(&adapter->hw, index, vfta); | |
4541 | } | |
4542 | ||
4543 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
4544 | { | |
4545 | igb_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
4546 | ||
4547 | if (adapter->vlgrp) { | |
4548 | u16 vid; | |
4549 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
4550 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
4551 | continue; | |
4552 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
4553 | } | |
4554 | } | |
4555 | } | |
4556 | ||
4557 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |
4558 | { | |
4559 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
4560 | ||
4561 | mac->autoneg = 0; | |
4562 | ||
4563 | /* Fiber NICs only allow 1000 gbps Full duplex */ | |
4564 | if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && | |
4565 | spddplx != (SPEED_1000 + DUPLEX_FULL)) { | |
4566 | dev_err(&adapter->pdev->dev, | |
4567 | "Unsupported Speed/Duplex configuration\n"); | |
4568 | return -EINVAL; | |
4569 | } | |
4570 | ||
4571 | switch (spddplx) { | |
4572 | case SPEED_10 + DUPLEX_HALF: | |
4573 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
4574 | break; | |
4575 | case SPEED_10 + DUPLEX_FULL: | |
4576 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
4577 | break; | |
4578 | case SPEED_100 + DUPLEX_HALF: | |
4579 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
4580 | break; | |
4581 | case SPEED_100 + DUPLEX_FULL: | |
4582 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
4583 | break; | |
4584 | case SPEED_1000 + DUPLEX_FULL: | |
4585 | mac->autoneg = 1; | |
4586 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
4587 | break; | |
4588 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
4589 | default: | |
4590 | dev_err(&adapter->pdev->dev, | |
4591 | "Unsupported Speed/Duplex configuration\n"); | |
4592 | return -EINVAL; | |
4593 | } | |
4594 | return 0; | |
4595 | } | |
4596 | ||
9d5c8243 AK |
4597 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) |
4598 | { | |
4599 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4600 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4601 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 4602 | u32 ctrl, rctl, status; |
9d5c8243 AK |
4603 | u32 wufc = adapter->wol; |
4604 | #ifdef CONFIG_PM | |
4605 | int retval = 0; | |
4606 | #endif | |
4607 | ||
4608 | netif_device_detach(netdev); | |
4609 | ||
a88f10ec AD |
4610 | if (netif_running(netdev)) |
4611 | igb_close(netdev); | |
4612 | ||
4613 | igb_reset_interrupt_capability(adapter); | |
4614 | ||
4615 | igb_free_queues(adapter); | |
9d5c8243 AK |
4616 | |
4617 | #ifdef CONFIG_PM | |
4618 | retval = pci_save_state(pdev); | |
4619 | if (retval) | |
4620 | return retval; | |
4621 | #endif | |
4622 | ||
4623 | status = rd32(E1000_STATUS); | |
4624 | if (status & E1000_STATUS_LU) | |
4625 | wufc &= ~E1000_WUFC_LNKC; | |
4626 | ||
4627 | if (wufc) { | |
4628 | igb_setup_rctl(adapter); | |
4629 | igb_set_multi(netdev); | |
4630 | ||
4631 | /* turn on all-multi mode if wake on multicast is enabled */ | |
4632 | if (wufc & E1000_WUFC_MC) { | |
4633 | rctl = rd32(E1000_RCTL); | |
4634 | rctl |= E1000_RCTL_MPE; | |
4635 | wr32(E1000_RCTL, rctl); | |
4636 | } | |
4637 | ||
4638 | ctrl = rd32(E1000_CTRL); | |
4639 | /* advertise wake from D3Cold */ | |
4640 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
4641 | /* phy power management enable */ | |
4642 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
4643 | ctrl |= E1000_CTRL_ADVD3WUC; | |
4644 | wr32(E1000_CTRL, ctrl); | |
4645 | ||
9d5c8243 AK |
4646 | /* Allow time for pending master requests to run */ |
4647 | igb_disable_pcie_master(&adapter->hw); | |
4648 | ||
4649 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
4650 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
4651 | } else { |
4652 | wr32(E1000_WUC, 0); | |
4653 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
4654 | } |
4655 | ||
2d064c06 AD |
4656 | /* make sure adapter isn't asleep if manageability/wol is enabled */ |
4657 | if (wufc || adapter->en_mng_pt) { | |
9d5c8243 AK |
4658 | pci_enable_wake(pdev, PCI_D3hot, 1); |
4659 | pci_enable_wake(pdev, PCI_D3cold, 1); | |
2d064c06 AD |
4660 | } else { |
4661 | igb_shutdown_fiber_serdes_link_82575(hw); | |
4662 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4663 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 AK |
4664 | } |
4665 | ||
4666 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
4667 | * would have already happened in close and is redundant. */ | |
4668 | igb_release_hw_control(adapter); | |
4669 | ||
4670 | pci_disable_device(pdev); | |
4671 | ||
4672 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
4673 | ||
4674 | return 0; | |
4675 | } | |
4676 | ||
4677 | #ifdef CONFIG_PM | |
4678 | static int igb_resume(struct pci_dev *pdev) | |
4679 | { | |
4680 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4681 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4682 | struct e1000_hw *hw = &adapter->hw; | |
4683 | u32 err; | |
4684 | ||
4685 | pci_set_power_state(pdev, PCI_D0); | |
4686 | pci_restore_state(pdev); | |
42bfd33a | 4687 | |
aed5dec3 | 4688 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
4689 | if (err) { |
4690 | dev_err(&pdev->dev, | |
4691 | "igb: Cannot enable PCI device from suspend\n"); | |
4692 | return err; | |
4693 | } | |
4694 | pci_set_master(pdev); | |
4695 | ||
4696 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4697 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4698 | ||
a88f10ec AD |
4699 | igb_set_interrupt_capability(adapter); |
4700 | ||
4701 | if (igb_alloc_queues(adapter)) { | |
4702 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
4703 | return -ENOMEM; | |
9d5c8243 AK |
4704 | } |
4705 | ||
4706 | /* e1000_power_up_phy(adapter); */ | |
4707 | ||
4708 | igb_reset(adapter); | |
a8564f03 AD |
4709 | |
4710 | /* let the f/w know that the h/w is now under the control of the | |
4711 | * driver. */ | |
4712 | igb_get_hw_control(adapter); | |
4713 | ||
9d5c8243 AK |
4714 | wr32(E1000_WUS, ~0); |
4715 | ||
a88f10ec AD |
4716 | if (netif_running(netdev)) { |
4717 | err = igb_open(netdev); | |
4718 | if (err) | |
4719 | return err; | |
4720 | } | |
9d5c8243 AK |
4721 | |
4722 | netif_device_attach(netdev); | |
4723 | ||
9d5c8243 AK |
4724 | return 0; |
4725 | } | |
4726 | #endif | |
4727 | ||
4728 | static void igb_shutdown(struct pci_dev *pdev) | |
4729 | { | |
4730 | igb_suspend(pdev, PMSG_SUSPEND); | |
4731 | } | |
4732 | ||
4733 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4734 | /* | |
4735 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4736 | * without having to re-enable interrupts. It's not called while | |
4737 | * the interrupt routine is executing. | |
4738 | */ | |
4739 | static void igb_netpoll(struct net_device *netdev) | |
4740 | { | |
4741 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 4742 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 4743 | int i; |
9d5c8243 | 4744 | |
eebbbdba AD |
4745 | if (!adapter->msix_entries) { |
4746 | igb_irq_disable(adapter); | |
4747 | napi_schedule(&adapter->rx_ring[0].napi); | |
4748 | return; | |
4749 | } | |
9d5c8243 | 4750 | |
eebbbdba AD |
4751 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4752 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
4753 | wr32(E1000_EIMC, tx_ring->eims_value); | |
4754 | igb_clean_tx_irq(tx_ring); | |
4755 | wr32(E1000_EIMS, tx_ring->eims_value); | |
4756 | } | |
9d5c8243 | 4757 | |
eebbbdba AD |
4758 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4759 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
4760 | wr32(E1000_EIMC, rx_ring->eims_value); | |
4761 | napi_schedule(&rx_ring->napi); | |
4762 | } | |
9d5c8243 AK |
4763 | } |
4764 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
4765 | ||
4766 | /** | |
4767 | * igb_io_error_detected - called when PCI error is detected | |
4768 | * @pdev: Pointer to PCI device | |
4769 | * @state: The current pci connection state | |
4770 | * | |
4771 | * This function is called after a PCI bus error affecting | |
4772 | * this device has been detected. | |
4773 | */ | |
4774 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
4775 | pci_channel_state_t state) | |
4776 | { | |
4777 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4778 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4779 | ||
4780 | netif_device_detach(netdev); | |
4781 | ||
4782 | if (netif_running(netdev)) | |
4783 | igb_down(adapter); | |
4784 | pci_disable_device(pdev); | |
4785 | ||
4786 | /* Request a slot slot reset. */ | |
4787 | return PCI_ERS_RESULT_NEED_RESET; | |
4788 | } | |
4789 | ||
4790 | /** | |
4791 | * igb_io_slot_reset - called after the pci bus has been reset. | |
4792 | * @pdev: Pointer to PCI device | |
4793 | * | |
4794 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
4795 | * resembles the first-half of the igb_resume routine. | |
4796 | */ | |
4797 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
4798 | { | |
4799 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4800 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4801 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 4802 | pci_ers_result_t result; |
42bfd33a | 4803 | int err; |
9d5c8243 | 4804 | |
aed5dec3 | 4805 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
4806 | dev_err(&pdev->dev, |
4807 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
4808 | result = PCI_ERS_RESULT_DISCONNECT; |
4809 | } else { | |
4810 | pci_set_master(pdev); | |
4811 | pci_restore_state(pdev); | |
9d5c8243 | 4812 | |
40a914fa AD |
4813 | pci_enable_wake(pdev, PCI_D3hot, 0); |
4814 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 4815 | |
40a914fa AD |
4816 | igb_reset(adapter); |
4817 | wr32(E1000_WUS, ~0); | |
4818 | result = PCI_ERS_RESULT_RECOVERED; | |
4819 | } | |
9d5c8243 | 4820 | |
ea943d41 JK |
4821 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
4822 | if (err) { | |
4823 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
4824 | "failed 0x%0x\n", err); | |
4825 | /* non-fatal, continue */ | |
4826 | } | |
40a914fa AD |
4827 | |
4828 | return result; | |
9d5c8243 AK |
4829 | } |
4830 | ||
4831 | /** | |
4832 | * igb_io_resume - called when traffic can start flowing again. | |
4833 | * @pdev: Pointer to PCI device | |
4834 | * | |
4835 | * This callback is called when the error recovery driver tells us that | |
4836 | * its OK to resume normal operation. Implementation resembles the | |
4837 | * second-half of the igb_resume routine. | |
4838 | */ | |
4839 | static void igb_io_resume(struct pci_dev *pdev) | |
4840 | { | |
4841 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4842 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4843 | ||
9d5c8243 AK |
4844 | if (netif_running(netdev)) { |
4845 | if (igb_up(adapter)) { | |
4846 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
4847 | return; | |
4848 | } | |
4849 | } | |
4850 | ||
4851 | netif_device_attach(netdev); | |
4852 | ||
4853 | /* let the f/w know that the h/w is now under the control of the | |
4854 | * driver. */ | |
4855 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
4856 | } |
4857 | ||
4858 | /* igb_main.c */ |