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igb: update ethtool stats to support multiqueue
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
44
45#include "igb.h"
46
47#define DRV_VERSION "1.0.8-k2"
48char igb_driver_name[] = "igb";
49char igb_driver_version[] = DRV_VERSION;
50static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver";
52static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
53
54
55static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info,
57};
58
59static struct pci_device_id igb_pci_tbl[] = {
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
63 /* required last entry */
64 {0, }
65};
66
67MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
68
69void igb_reset(struct igb_adapter *);
70static int igb_setup_all_tx_resources(struct igb_adapter *);
71static int igb_setup_all_rx_resources(struct igb_adapter *);
72static void igb_free_all_tx_resources(struct igb_adapter *);
73static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 74static void igb_free_tx_resources(struct igb_ring *);
75static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 76void igb_update_stats(struct igb_adapter *);
77static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78static void __devexit igb_remove(struct pci_dev *pdev);
79static int igb_sw_init(struct igb_adapter *);
80static int igb_open(struct net_device *);
81static int igb_close(struct net_device *);
82static void igb_configure_tx(struct igb_adapter *);
83static void igb_configure_rx(struct igb_adapter *);
84static void igb_setup_rctl(struct igb_adapter *);
85static void igb_clean_all_tx_rings(struct igb_adapter *);
86static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 87static void igb_clean_tx_ring(struct igb_ring *);
88static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 89static void igb_set_multi(struct net_device *);
90static void igb_update_phy_info(unsigned long);
91static void igb_watchdog(unsigned long);
92static void igb_watchdog_task(struct work_struct *);
93static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
94 struct igb_ring *);
95static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
96static struct net_device_stats *igb_get_stats(struct net_device *);
97static int igb_change_mtu(struct net_device *, int);
98static int igb_set_mac(struct net_device *, void *);
99static irqreturn_t igb_intr(int irq, void *);
100static irqreturn_t igb_intr_msi(int irq, void *);
101static irqreturn_t igb_msix_other(int irq, void *);
102static irqreturn_t igb_msix_rx(int irq, void *);
103static irqreturn_t igb_msix_tx(int irq, void *);
104static int igb_clean_rx_ring_msix(struct napi_struct *, int);
3b644cf6 105static bool igb_clean_tx_irq(struct igb_ring *);
661086df 106static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 107static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
108static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 109static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
110static void igb_tx_timeout(struct net_device *);
111static void igb_reset_task(struct work_struct *);
112static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
113static void igb_vlan_rx_add_vid(struct net_device *, u16);
114static void igb_vlan_rx_kill_vid(struct net_device *, u16);
115static void igb_restore_vlan(struct igb_adapter *);
116
117static int igb_suspend(struct pci_dev *, pm_message_t);
118#ifdef CONFIG_PM
119static int igb_resume(struct pci_dev *);
120#endif
121static void igb_shutdown(struct pci_dev *);
122
123#ifdef CONFIG_NET_POLL_CONTROLLER
124/* for netdump / net console */
125static void igb_netpoll(struct net_device *);
126#endif
127
128static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
129 pci_channel_state_t);
130static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
131static void igb_io_resume(struct pci_dev *);
132
133static struct pci_error_handlers igb_err_handler = {
134 .error_detected = igb_io_error_detected,
135 .slot_reset = igb_io_slot_reset,
136 .resume = igb_io_resume,
137};
138
139
140static struct pci_driver igb_driver = {
141 .name = igb_driver_name,
142 .id_table = igb_pci_tbl,
143 .probe = igb_probe,
144 .remove = __devexit_p(igb_remove),
145#ifdef CONFIG_PM
146 /* Power Managment Hooks */
147 .suspend = igb_suspend,
148 .resume = igb_resume,
149#endif
150 .shutdown = igb_shutdown,
151 .err_handler = &igb_err_handler
152};
153
154MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
155MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
156MODULE_LICENSE("GPL");
157MODULE_VERSION(DRV_VERSION);
158
159#ifdef DEBUG
160/**
161 * igb_get_hw_dev_name - return device name string
162 * used by hardware layer to print debugging information
163 **/
164char *igb_get_hw_dev_name(struct e1000_hw *hw)
165{
166 struct igb_adapter *adapter = hw->back;
167 return adapter->netdev->name;
168}
169#endif
170
171/**
172 * igb_init_module - Driver Registration Routine
173 *
174 * igb_init_module is the first routine called when the driver is
175 * loaded. All it does is register with the PCI subsystem.
176 **/
177static int __init igb_init_module(void)
178{
179 int ret;
180 printk(KERN_INFO "%s - version %s\n",
181 igb_driver_string, igb_driver_version);
182
183 printk(KERN_INFO "%s\n", igb_copyright);
184
185 ret = pci_register_driver(&igb_driver);
186 return ret;
187}
188
189module_init(igb_init_module);
190
191/**
192 * igb_exit_module - Driver Exit Cleanup Routine
193 *
194 * igb_exit_module is called just before the driver is removed
195 * from memory.
196 **/
197static void __exit igb_exit_module(void)
198{
199 pci_unregister_driver(&igb_driver);
200}
201
202module_exit(igb_exit_module);
203
204/**
205 * igb_alloc_queues - Allocate memory for all rings
206 * @adapter: board private structure to initialize
207 *
208 * We allocate one ring per queue at run-time since we don't know the
209 * number of queues at compile-time.
210 **/
211static int igb_alloc_queues(struct igb_adapter *adapter)
212{
213 int i;
214
215 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
216 sizeof(struct igb_ring), GFP_KERNEL);
217 if (!adapter->tx_ring)
218 return -ENOMEM;
219
220 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
221 sizeof(struct igb_ring), GFP_KERNEL);
222 if (!adapter->rx_ring) {
223 kfree(adapter->tx_ring);
224 return -ENOMEM;
225 }
226
661086df
PWJ		 227 for (i = 0; i < adapter->num_tx_queues; i++) {
228 struct igb_ring *ring = &(adapter->tx_ring[i]);
229 ring->adapter = adapter;
230 ring->queue_index = i;
231 }
9d5c8243
AK		 232 for (i = 0; i < adapter->num_rx_queues; i++) {
233 struct igb_ring *ring = &(adapter->rx_ring[i]);
234 ring->adapter = adapter;
844290e5 235 ring->queue_index = i;
9d5c8243
AK		 236 ring->itr_register = E1000_ITR;
237
844290e5 238 /* set a default napi handler for each rx_ring */
661086df 239 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 240 }
241 return 0;
242}
243
244#define IGB_N0_QUEUE -1
245static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
246 int tx_queue, int msix_vector)
247{
248 u32 msixbm = 0;
249 struct e1000_hw *hw = &adapter->hw;
250 /* The 82575 assigns vectors using a bitmask, which matches the
251 bitmask for the EICR/EIMS/EIMC registers. To assign one
252 or more queues to a vector, we write the appropriate bits
253 into the MSIXBM register for that vector. */
254 if (rx_queue > IGB_N0_QUEUE) {
255 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
256 adapter->rx_ring[rx_queue].eims_value = msixbm;
257 }
258 if (tx_queue > IGB_N0_QUEUE) {
259 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
260 adapter->tx_ring[tx_queue].eims_value =
261 E1000_EICR_TX_QUEUE0 << tx_queue;
262 }
263 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
264}
265
266/**
267 * igb_configure_msix - Configure MSI-X hardware
268 *
269 * igb_configure_msix sets up the hardware to properly
270 * generate MSI-X interrupts.
271 **/
272static void igb_configure_msix(struct igb_adapter *adapter)
273{
274 u32 tmp;
275 int i, vector = 0;
276 struct e1000_hw *hw = &adapter->hw;
277
278 adapter->eims_enable_mask = 0;
279
280 for (i = 0; i < adapter->num_tx_queues; i++) {
281 struct igb_ring *tx_ring = &adapter->tx_ring[i];
282 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
283 adapter->eims_enable_mask |= tx_ring->eims_value;
284 if (tx_ring->itr_val)
285 writel(1000000000 / (tx_ring->itr_val * 256),
286 hw->hw_addr + tx_ring->itr_register);
287 else
288 writel(1, hw->hw_addr + tx_ring->itr_register);
289 }
290
291 for (i = 0; i < adapter->num_rx_queues; i++) {
292 struct igb_ring *rx_ring = &adapter->rx_ring[i];
293 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
294 adapter->eims_enable_mask |= rx_ring->eims_value;
295 if (rx_ring->itr_val)
296 writel(1000000000 / (rx_ring->itr_val * 256),
297 hw->hw_addr + rx_ring->itr_register);
298 else
299 writel(1, hw->hw_addr + rx_ring->itr_register);
300 }
301
302
303 /* set vector for other causes, i.e. link changes */
304 array_wr32(E1000_MSIXBM(0), vector++,
305 E1000_EIMS_OTHER);
306
9d5c8243
AK		 307 tmp = rd32(E1000_CTRL_EXT);
308 /* enable MSI-X PBA support*/
309 tmp |= E1000_CTRL_EXT_PBA_CLR;
310
311 /* Auto-Mask interrupts upon ICR read. */
312 tmp |= E1000_CTRL_EXT_EIAME;
313 tmp |= E1000_CTRL_EXT_IRCA;
314
315 wr32(E1000_CTRL_EXT, tmp);
316 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 317 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243
AK		 318
319 wrfl();
320}
321
322/**
323 * igb_request_msix - Initialize MSI-X interrupts
324 *
325 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
326 * kernel.
327 **/
328static int igb_request_msix(struct igb_adapter *adapter)
329{
330 struct net_device *netdev = adapter->netdev;
331 int i, err = 0, vector = 0;
332
333 vector = 0;
334
335 for (i = 0; i < adapter->num_tx_queues; i++) {
336 struct igb_ring *ring = &(adapter->tx_ring[i]);
337 sprintf(ring->name, "%s-tx%d", netdev->name, i);
338 err = request_irq(adapter->msix_entries[vector].vector,
339 &igb_msix_tx, 0, ring->name,
340 &(adapter->tx_ring[i]));
341 if (err)
342 goto out;
343 ring->itr_register = E1000_EITR(0) + (vector << 2);
344 ring->itr_val = adapter->itr;
345 vector++;
346 }
347 for (i = 0; i < adapter->num_rx_queues; i++) {
348 struct igb_ring *ring = &(adapter->rx_ring[i]);
349 if (strlen(netdev->name) < (IFNAMSIZ - 5))
350 sprintf(ring->name, "%s-rx%d", netdev->name, i);
351 else
352 memcpy(ring->name, netdev->name, IFNAMSIZ);
353 err = request_irq(adapter->msix_entries[vector].vector,
354 &igb_msix_rx, 0, ring->name,
355 &(adapter->rx_ring[i]));
356 if (err)
357 goto out;
358 ring->itr_register = E1000_EITR(0) + (vector << 2);
359 ring->itr_val = adapter->itr;
844290e5
PW		 360 /* overwrite the poll routine for MSIX, we've already done
361 * netif_napi_add */
362 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 363 vector++;
364 }
365
366 err = request_irq(adapter->msix_entries[vector].vector,
367 &igb_msix_other, 0, netdev->name, netdev);
368 if (err)
369 goto out;
370
9d5c8243
AK		 371 igb_configure_msix(adapter);
372 return 0;
373out:
374 return err;
375}
376
377static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
378{
379 if (adapter->msix_entries) {
380 pci_disable_msix(adapter->pdev);
381 kfree(adapter->msix_entries);
382 adapter->msix_entries = NULL;
383 } else if (adapter->msi_enabled)
384 pci_disable_msi(adapter->pdev);
385 return;
386}
387
388
389/**
390 * igb_set_interrupt_capability - set MSI or MSI-X if supported
391 *
392 * Attempt to configure interrupts using the best available
393 * capabilities of the hardware and kernel.
394 **/
395static void igb_set_interrupt_capability(struct igb_adapter *adapter)
396{
397 int err;
398 int numvecs, i;
399
400 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
401 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
402 GFP_KERNEL);
403 if (!adapter->msix_entries)
404 goto msi_only;
405
406 for (i = 0; i < numvecs; i++)
407 adapter->msix_entries[i].entry = i;
408
409 err = pci_enable_msix(adapter->pdev,
410 adapter->msix_entries,
411 numvecs);
412 if (err == 0)
413 return;
414
415 igb_reset_interrupt_capability(adapter);
416
417 /* If we can't do MSI-X, try MSI */
418msi_only:
419 adapter->num_rx_queues = 1;
661086df 420 adapter->num_tx_queues = 1;
9d5c8243
AK		 421 if (!pci_enable_msi(adapter->pdev))
422 adapter->msi_enabled = 1;
661086df
PWJ		 423
424#ifdef CONFIG_NETDEVICES_MULTIQUEUE
425 /* Notify the stack of the (possibly) reduced Tx Queue count. */
426 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
427#endif
9d5c8243
AK		 428 return;
429}
430
431/**
432 * igb_request_irq - initialize interrupts
433 *
434 * Attempts to configure interrupts using the best available
435 * capabilities of the hardware and kernel.
436 **/
437static int igb_request_irq(struct igb_adapter *adapter)
438{
439 struct net_device *netdev = adapter->netdev;
440 struct e1000_hw *hw = &adapter->hw;
441 int err = 0;
442
443 if (adapter->msix_entries) {
444 err = igb_request_msix(adapter);
844290e5 445 if (!err)
9d5c8243 446 goto request_done;
9d5c8243
AK		 447 /* fall back to MSI */
448 igb_reset_interrupt_capability(adapter);
449 if (!pci_enable_msi(adapter->pdev))
450 adapter->msi_enabled = 1;
451 igb_free_all_tx_resources(adapter);
452 igb_free_all_rx_resources(adapter);
453 adapter->num_rx_queues = 1;
454 igb_alloc_queues(adapter);
844290e5
PW		 455 } else {
456 wr32(E1000_MSIXBM(0), (E1000_EICR_RX_QUEUE0 |
457 E1000_EIMS_OTHER));
9d5c8243 458 }
844290e5 459
9d5c8243
AK		 460 if (adapter->msi_enabled) {
461 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
462 netdev->name, netdev);
463 if (!err)
464 goto request_done;
465 /* fall back to legacy interrupts */
466 igb_reset_interrupt_capability(adapter);
467 adapter->msi_enabled = 0;
468 }
469
470 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
471 netdev->name, netdev);
472
6cb5e577 473 if (err)
9d5c8243
AK		 474 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
475 err);
9d5c8243
AK		 476
477request_done:
478 return err;
479}
480
481static void igb_free_irq(struct igb_adapter *adapter)
482{
483 struct net_device *netdev = adapter->netdev;
484
485 if (adapter->msix_entries) {
486 int vector = 0, i;
487
488 for (i = 0; i < adapter->num_tx_queues; i++)
489 free_irq(adapter->msix_entries[vector++].vector,
490 &(adapter->tx_ring[i]));
491 for (i = 0; i < adapter->num_rx_queues; i++)
492 free_irq(adapter->msix_entries[vector++].vector,
493 &(adapter->rx_ring[i]));
494
495 free_irq(adapter->msix_entries[vector++].vector, netdev);
496 return;
497 }
498
499 free_irq(adapter->pdev->irq, netdev);
500}
501
502/**
503 * igb_irq_disable - Mask off interrupt generation on the NIC
504 * @adapter: board private structure
505 **/
506static void igb_irq_disable(struct igb_adapter *adapter)
507{
508 struct e1000_hw *hw = &adapter->hw;
509
510 if (adapter->msix_entries) {
844290e5 511 wr32(E1000_EIAM, 0);
9d5c8243
AK		 512 wr32(E1000_EIMC, ~0);
513 wr32(E1000_EIAC, 0);
514 }
844290e5
PW		 515
516 wr32(E1000_IAM, 0);
9d5c8243
AK		 517 wr32(E1000_IMC, ~0);
518 wrfl();
519 synchronize_irq(adapter->pdev->irq);
520}
521
522/**
523 * igb_irq_enable - Enable default interrupt generation settings
524 * @adapter: board private structure
525 **/
526static void igb_irq_enable(struct igb_adapter *adapter)
527{
528 struct e1000_hw *hw = &adapter->hw;
529
530 if (adapter->msix_entries) {
844290e5
PW		 531 wr32(E1000_EIAC, adapter->eims_enable_mask);
532 wr32(E1000_EIAM, adapter->eims_enable_mask);
533 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 534 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 535 } else {
536 wr32(E1000_IMS, IMS_ENABLE_MASK);
537 wr32(E1000_IAM, IMS_ENABLE_MASK);
538 }
9d5c8243
AK		 539}
540
541static void igb_update_mng_vlan(struct igb_adapter *adapter)
542{
543 struct net_device *netdev = adapter->netdev;
544 u16 vid = adapter->hw.mng_cookie.vlan_id;
545 u16 old_vid = adapter->mng_vlan_id;
546 if (adapter->vlgrp) {
547 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
548 if (adapter->hw.mng_cookie.status &
549 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
550 igb_vlan_rx_add_vid(netdev, vid);
551 adapter->mng_vlan_id = vid;
552 } else
553 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
554
555 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
556 (vid != old_vid) &&
557 !vlan_group_get_device(adapter->vlgrp, old_vid))
558 igb_vlan_rx_kill_vid(netdev, old_vid);
559 } else
560 adapter->mng_vlan_id = vid;
561 }
562}
563
564/**
565 * igb_release_hw_control - release control of the h/w to f/w
566 * @adapter: address of board private structure
567 *
568 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
569 * For ASF and Pass Through versions of f/w this means that the
570 * driver is no longer loaded.
571 *
572 **/
573static void igb_release_hw_control(struct igb_adapter *adapter)
574{
575 struct e1000_hw *hw = &adapter->hw;
576 u32 ctrl_ext;
577
578 /* Let firmware take over control of h/w */
579 ctrl_ext = rd32(E1000_CTRL_EXT);
580 wr32(E1000_CTRL_EXT,
581 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
582}
583
584
585/**
586 * igb_get_hw_control - get control of the h/w from f/w
587 * @adapter: address of board private structure
588 *
589 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
590 * For ASF and Pass Through versions of f/w this means that
591 * the driver is loaded.
592 *
593 **/
594static void igb_get_hw_control(struct igb_adapter *adapter)
595{
596 struct e1000_hw *hw = &adapter->hw;
597 u32 ctrl_ext;
598
599 /* Let firmware know the driver has taken over */
600 ctrl_ext = rd32(E1000_CTRL_EXT);
601 wr32(E1000_CTRL_EXT,
602 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
603}
604
605static void igb_init_manageability(struct igb_adapter *adapter)
606{
607 struct e1000_hw *hw = &adapter->hw;
608
609 if (adapter->en_mng_pt) {
610 u32 manc2h = rd32(E1000_MANC2H);
611 u32 manc = rd32(E1000_MANC);
612
9d5c8243
AK		 613 /* enable receiving management packets to the host */
614 /* this will probably generate destination unreachable messages
615 * from the host OS, but the packets will be handled on SMBUS */
616 manc |= E1000_MANC_EN_MNG2HOST;
617#define E1000_MNG2HOST_PORT_623 (1 << 5)
618#define E1000_MNG2HOST_PORT_664 (1 << 6)
619 manc2h |= E1000_MNG2HOST_PORT_623;
620 manc2h |= E1000_MNG2HOST_PORT_664;
621 wr32(E1000_MANC2H, manc2h);
622
623 wr32(E1000_MANC, manc);
624 }
625}
626
9d5c8243
AK		 627/**
628 * igb_configure - configure the hardware for RX and TX
629 * @adapter: private board structure
630 **/
631static void igb_configure(struct igb_adapter *adapter)
632{
633 struct net_device *netdev = adapter->netdev;
634 int i;
635
636 igb_get_hw_control(adapter);
637 igb_set_multi(netdev);
638
639 igb_restore_vlan(adapter);
640 igb_init_manageability(adapter);
641
642 igb_configure_tx(adapter);
643 igb_setup_rctl(adapter);
644 igb_configure_rx(adapter);
662d7205
AD		 645
646 igb_rx_fifo_flush_82575(&adapter->hw);
647
9d5c8243
AK		 648 /* call IGB_DESC_UNUSED which always leaves
649 * at least 1 descriptor unused to make sure
650 * next_to_use != next_to_clean */
651 for (i = 0; i < adapter->num_rx_queues; i++) {
652 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 653 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 654 }
655
656
657 adapter->tx_queue_len = netdev->tx_queue_len;
658}
659
660
661/**
662 * igb_up - Open the interface and prepare it to handle traffic
663 * @adapter: board private structure
664 **/
665
666int igb_up(struct igb_adapter *adapter)
667{
668 struct e1000_hw *hw = &adapter->hw;
669 int i;
670
671 /* hardware has been reset, we need to reload some things */
672 igb_configure(adapter);
673
674 clear_bit(__IGB_DOWN, &adapter->state);
675
844290e5
PW		 676 for (i = 0; i < adapter->num_rx_queues; i++)
677 napi_enable(&adapter->rx_ring[i].napi);
678 if (adapter->msix_entries)
9d5c8243 679 igb_configure_msix(adapter);
9d5c8243
AK		 680
681 /* Clear any pending interrupts. */
682 rd32(E1000_ICR);
683 igb_irq_enable(adapter);
684
685 /* Fire a link change interrupt to start the watchdog. */
686 wr32(E1000_ICS, E1000_ICS_LSC);
687 return 0;
688}
689
690void igb_down(struct igb_adapter *adapter)
691{
692 struct e1000_hw *hw = &adapter->hw;
693 struct net_device *netdev = adapter->netdev;
694 u32 tctl, rctl;
695 int i;
696
697 /* signal that we're down so the interrupt handler does not
698 * reschedule our watchdog timer */
699 set_bit(__IGB_DOWN, &adapter->state);
700
701 /* disable receives in the hardware */
702 rctl = rd32(E1000_RCTL);
703 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
704 /* flush and sleep below */
705
706 netif_stop_queue(netdev);
661086df
PWJ		 707#ifdef CONFIG_NETDEVICES_MULTIQUEUE
708 for (i = 0; i < adapter->num_tx_queues; i++)
709 netif_stop_subqueue(netdev, i);
710#endif
9d5c8243
AK		 711
712 /* disable transmits in the hardware */
713 tctl = rd32(E1000_TCTL);
714 tctl &= ~E1000_TCTL_EN;
715 wr32(E1000_TCTL, tctl);
716 /* flush both disables and wait for them to finish */
717 wrfl();
718 msleep(10);
719
844290e5
PW		 720 for (i = 0; i < adapter->num_rx_queues; i++)
721 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 722
9d5c8243
AK		 723 igb_irq_disable(adapter);
724
725 del_timer_sync(&adapter->watchdog_timer);
726 del_timer_sync(&adapter->phy_info_timer);
727
728 netdev->tx_queue_len = adapter->tx_queue_len;
729 netif_carrier_off(netdev);
730 adapter->link_speed = 0;
731 adapter->link_duplex = 0;
732
3023682e
JK		 733 if (!pci_channel_offline(adapter->pdev))
734 igb_reset(adapter);
9d5c8243
AK		 735 igb_clean_all_tx_rings(adapter);
736 igb_clean_all_rx_rings(adapter);
737}
738
739void igb_reinit_locked(struct igb_adapter *adapter)
740{
741 WARN_ON(in_interrupt());
742 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
743 msleep(1);
744 igb_down(adapter);
745 igb_up(adapter);
746 clear_bit(__IGB_RESETTING, &adapter->state);
747}
748
749void igb_reset(struct igb_adapter *adapter)
750{
751 struct e1000_hw *hw = &adapter->hw;
752 struct e1000_fc_info *fc = &adapter->hw.fc;
753 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
754 u16 hwm;
755
756 /* Repartition Pba for greater than 9k mtu
757 * To take effect CTRL.RST is required.
758 */
759 pba = E1000_PBA_34K;
760
761 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
762 /* adjust PBA for jumbo frames */
763 wr32(E1000_PBA, pba);
764
765 /* To maintain wire speed transmits, the Tx FIFO should be
766 * large enough to accommodate two full transmit packets,
767 * rounded up to the next 1KB and expressed in KB. Likewise,
768 * the Rx FIFO should be large enough to accommodate at least
769 * one full receive packet and is similarly rounded up and
770 * expressed in KB. */
771 pba = rd32(E1000_PBA);
772 /* upper 16 bits has Tx packet buffer allocation size in KB */
773 tx_space = pba >> 16;
774 /* lower 16 bits has Rx packet buffer allocation size in KB */
775 pba &= 0xffff;
776 /* the tx fifo also stores 16 bytes of information about the tx
777 * but don't include ethernet FCS because hardware appends it */
778 min_tx_space = (adapter->max_frame_size +
779 sizeof(struct e1000_tx_desc) -
780 ETH_FCS_LEN) * 2;
781 min_tx_space = ALIGN(min_tx_space, 1024);
782 min_tx_space >>= 10;
783 /* software strips receive CRC, so leave room for it */
784 min_rx_space = adapter->max_frame_size;
785 min_rx_space = ALIGN(min_rx_space, 1024);
786 min_rx_space >>= 10;
787
788 /* If current Tx allocation is less than the min Tx FIFO size,
789 * and the min Tx FIFO size is less than the current Rx FIFO
790 * allocation, take space away from current Rx allocation */
791 if (tx_space < min_tx_space &&
792 ((min_tx_space - tx_space) < pba)) {
793 pba = pba - (min_tx_space - tx_space);
794
795 /* if short on rx space, rx wins and must trump tx
796 * adjustment */
797 if (pba < min_rx_space)
798 pba = min_rx_space;
799 }
800 }
801 wr32(E1000_PBA, pba);
802
803 /* flow control settings */
804 /* The high water mark must be low enough to fit one full frame
805 * (or the size used for early receive) above it in the Rx FIFO.
806 * Set it to the lower of:
807 * - 90% of the Rx FIFO size, or
808 * - the full Rx FIFO size minus one full frame */
809 hwm = min(((pba << 10) * 9 / 10),
810 ((pba << 10) - adapter->max_frame_size));
811
812 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
813 fc->low_water = fc->high_water - 8;
814 fc->pause_time = 0xFFFF;
815 fc->send_xon = 1;
816 fc->type = fc->original_type;
817
818 /* Allow time for pending master requests to run */
819 adapter->hw.mac.ops.reset_hw(&adapter->hw);
820 wr32(E1000_WUC, 0);
821
822 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
823 dev_err(&adapter->pdev->dev, "Hardware Error\n");
824
825 igb_update_mng_vlan(adapter);
826
827 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
828 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
829
830 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 831 if (adapter->hw.phy.ops.get_phy_info)
832 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 833}
834
42bfd33a
TI		 835/**
836 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
837 * @pdev: PCI device information struct
838 *
839 * Returns true if an adapter needs ioport resources
840 **/
841static int igb_is_need_ioport(struct pci_dev *pdev)
842{
843 switch (pdev->device) {
844 /* Currently there are no adapters that need ioport resources */
845 default:
846 return false;
847 }
848}
849
9d5c8243
AK		 850/**
851 * igb_probe - Device Initialization Routine
852 * @pdev: PCI device information struct
853 * @ent: entry in igb_pci_tbl
854 *
855 * Returns 0 on success, negative on failure
856 *
857 * igb_probe initializes an adapter identified by a pci_dev structure.
858 * The OS initialization, configuring of the adapter private structure,
859 * and a hardware reset occur.
860 **/
861static int __devinit igb_probe(struct pci_dev *pdev,
862 const struct pci_device_id *ent)
863{
864 struct net_device *netdev;
865 struct igb_adapter *adapter;
866 struct e1000_hw *hw;
867 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
868 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 869 int i, err, pci_using_dac;
870 u16 eeprom_data = 0;
871 u16 eeprom_apme_mask = IGB_EEPROM_APME;
872 u32 part_num;
42bfd33a 873 int bars, need_ioport;
9d5c8243 874
42bfd33a
TI		 875 /* do not allocate ioport bars when not needed */
876 need_ioport = igb_is_need_ioport(pdev);
877 if (need_ioport) {
878 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
879 err = pci_enable_device(pdev);
880 } else {
881 bars = pci_select_bars(pdev, IORESOURCE_MEM);
882 err = pci_enable_device_mem(pdev);
883 }
9d5c8243
AK		 884 if (err)
885 return err;
886
887 pci_using_dac = 0;
888 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
889 if (!err) {
890 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
891 if (!err)
892 pci_using_dac = 1;
893 } else {
894 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
895 if (err) {
896 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
897 if (err) {
898 dev_err(&pdev->dev, "No usable DMA "
899 "configuration, aborting\n");
900 goto err_dma;
901 }
902 }
903 }
904
42bfd33a 905 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 906 if (err)
907 goto err_pci_reg;
908
909 pci_set_master(pdev);
c682fc23 910 pci_save_state(pdev);
9d5c8243
AK		 911
912 err = -ENOMEM;
661086df
PWJ		 913#ifdef CONFIG_NETDEVICES_MULTIQUEUE
914 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
915#else
9d5c8243 916 netdev = alloc_etherdev(sizeof(struct igb_adapter));
661086df 917#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
9d5c8243
AK		 918 if (!netdev)
919 goto err_alloc_etherdev;
920
921 SET_NETDEV_DEV(netdev, &pdev->dev);
922
923 pci_set_drvdata(pdev, netdev);
924 adapter = netdev_priv(netdev);
925 adapter->netdev = netdev;
926 adapter->pdev = pdev;
927 hw = &adapter->hw;
928 hw->back = adapter;
929 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 930 adapter->bars = bars;
931 adapter->need_ioport = need_ioport;
9d5c8243
AK		 932
933 mmio_start = pci_resource_start(pdev, 0);
934 mmio_len = pci_resource_len(pdev, 0);
935
936 err = -EIO;
937 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
938 if (!adapter->hw.hw_addr)
939 goto err_ioremap;
940
941 netdev->open = &igb_open;
942 netdev->stop = &igb_close;
943 netdev->get_stats = &igb_get_stats;
944 netdev->set_multicast_list = &igb_set_multi;
945 netdev->set_mac_address = &igb_set_mac;
946 netdev->change_mtu = &igb_change_mtu;
947 netdev->do_ioctl = &igb_ioctl;
948 igb_set_ethtool_ops(netdev);
949 netdev->tx_timeout = &igb_tx_timeout;
950 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 951 netdev->vlan_rx_register = igb_vlan_rx_register;
952 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
953 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
954#ifdef CONFIG_NET_POLL_CONTROLLER
955 netdev->poll_controller = igb_netpoll;
956#endif
957 netdev->hard_start_xmit = &igb_xmit_frame_adv;
958
959 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
960
961 netdev->mem_start = mmio_start;
962 netdev->mem_end = mmio_start + mmio_len;
963
9d5c8243
AK		 964 /* PCI config space info */
965 hw->vendor_id = pdev->vendor;
966 hw->device_id = pdev->device;
967 hw->revision_id = pdev->revision;
968 hw->subsystem_vendor_id = pdev->subsystem_vendor;
969 hw->subsystem_device_id = pdev->subsystem_device;
970
971 /* setup the private structure */
972 hw->back = adapter;
973 /* Copy the default MAC, PHY and NVM function pointers */
974 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
975 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
976 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
977 /* Initialize skew-specific constants */
978 err = ei->get_invariants(hw);
979 if (err)
980 goto err_hw_init;
981
982 err = igb_sw_init(adapter);
983 if (err)
984 goto err_sw_init;
985
986 igb_get_bus_info_pcie(hw);
987
988 hw->phy.autoneg_wait_to_complete = false;
989 hw->mac.adaptive_ifs = true;
990
991 /* Copper options */
992 if (hw->phy.media_type == e1000_media_type_copper) {
993 hw->phy.mdix = AUTO_ALL_MODES;
994 hw->phy.disable_polarity_correction = false;
995 hw->phy.ms_type = e1000_ms_hw_default;
996 }
997
998 if (igb_check_reset_block(hw))
999 dev_info(&pdev->dev,
1000 "PHY reset is blocked due to SOL/IDER session.\n");
1001
1002 netdev->features = NETIF_F_SG |
1003 NETIF_F_HW_CSUM |
1004 NETIF_F_HW_VLAN_TX |
1005 NETIF_F_HW_VLAN_RX |
1006 NETIF_F_HW_VLAN_FILTER;
1007
1008 netdev->features |= NETIF_F_TSO;
9d5c8243 1009 netdev->features |= NETIF_F_TSO6;
48f29ffc
JK		 1010
1011 netdev->vlan_features |= NETIF_F_TSO;
1012 netdev->vlan_features |= NETIF_F_TSO6;
1013 netdev->vlan_features |= NETIF_F_HW_CSUM;
1014 netdev->vlan_features |= NETIF_F_SG;
1015
9d5c8243
AK		 1016 if (pci_using_dac)
1017 netdev->features |= NETIF_F_HIGHDMA;
1018
661086df
PWJ		 1019#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1020 netdev->features |= NETIF_F_MULTI_QUEUE;
1021#endif
1022
9d5c8243
AK		 1023 netdev->features |= NETIF_F_LLTX;
1024 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1025
1026 /* before reading the NVM, reset the controller to put the device in a
1027 * known good starting state */
1028 hw->mac.ops.reset_hw(hw);
1029
1030 /* make sure the NVM is good */
1031 if (igb_validate_nvm_checksum(hw) < 0) {
1032 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1033 err = -EIO;
1034 goto err_eeprom;
1035 }
1036
1037 /* copy the MAC address out of the NVM */
1038 if (hw->mac.ops.read_mac_addr(hw))
1039 dev_err(&pdev->dev, "NVM Read Error\n");
1040
1041 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1042 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1043
1044 if (!is_valid_ether_addr(netdev->perm_addr)) {
1045 dev_err(&pdev->dev, "Invalid MAC Address\n");
1046 err = -EIO;
1047 goto err_eeprom;
1048 }
1049
1050 init_timer(&adapter->watchdog_timer);
1051 adapter->watchdog_timer.function = &igb_watchdog;
1052 adapter->watchdog_timer.data = (unsigned long) adapter;
1053
1054 init_timer(&adapter->phy_info_timer);
1055 adapter->phy_info_timer.function = &igb_update_phy_info;
1056 adapter->phy_info_timer.data = (unsigned long) adapter;
1057
1058 INIT_WORK(&adapter->reset_task, igb_reset_task);
1059 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1060
1061 /* Initialize link & ring properties that are user-changeable */
1062 adapter->tx_ring->count = 256;
1063 for (i = 0; i < adapter->num_tx_queues; i++)
1064 adapter->tx_ring[i].count = adapter->tx_ring->count;
1065 adapter->rx_ring->count = 256;
1066 for (i = 0; i < adapter->num_rx_queues; i++)
1067 adapter->rx_ring[i].count = adapter->rx_ring->count;
1068
1069 adapter->fc_autoneg = true;
1070 hw->mac.autoneg = true;
1071 hw->phy.autoneg_advertised = 0x2f;
1072
1073 hw->fc.original_type = e1000_fc_default;
1074 hw->fc.type = e1000_fc_default;
1075
1076 adapter->itr_setting = 3;
1077 adapter->itr = IGB_START_ITR;
1078
1079 igb_validate_mdi_setting(hw);
1080
1081 adapter->rx_csum = 1;
1082
1083 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1084 * enable the ACPI Magic Packet filter
1085 */
1086
1087 if (hw->bus.func == 0 ||
1088 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1089 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1090 &eeprom_data);
1091
1092 if (eeprom_data & eeprom_apme_mask)
1093 adapter->eeprom_wol |= E1000_WUFC_MAG;
1094
1095 /* now that we have the eeprom settings, apply the special cases where
1096 * the eeprom may be wrong or the board simply won't support wake on
1097 * lan on a particular port */
1098 switch (pdev->device) {
1099 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1100 adapter->eeprom_wol = 0;
1101 break;
1102 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1103 /* Wake events only supported on port A for dual fiber
1104 * regardless of eeprom setting */
1105 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1106 adapter->eeprom_wol = 0;
1107 break;
1108 }
1109
1110 /* initialize the wol settings based on the eeprom settings */
1111 adapter->wol = adapter->eeprom_wol;
1112
1113 /* reset the hardware with the new settings */
1114 igb_reset(adapter);
1115
1116 /* let the f/w know that the h/w is now under the control of the
1117 * driver. */
1118 igb_get_hw_control(adapter);
1119
1120 /* tell the stack to leave us alone until igb_open() is called */
1121 netif_carrier_off(netdev);
1122 netif_stop_queue(netdev);
661086df
PWJ		 1123#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1124 for (i = 0; i < adapter->num_tx_queues; i++)
1125 netif_stop_subqueue(netdev, i);
1126#endif
9d5c8243
AK		 1127
1128 strcpy(netdev->name, "eth%d");
1129 err = register_netdev(netdev);
1130 if (err)
1131 goto err_register;
1132
1133 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1134 /* print bus type/speed/width info */
1135 dev_info(&pdev->dev,
1136 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1137 netdev->name,
1138 ((hw->bus.speed == e1000_bus_speed_2500)
1139 ? "2.5Gb/s" : "unknown"),
1140 ((hw->bus.width == e1000_bus_width_pcie_x4)
1141 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1142 ? "Width x1" : "unknown"),
1143 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1144 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1145
1146 igb_read_part_num(hw, &part_num);
1147 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1148 (part_num >> 8), (part_num & 0xff));
1149
1150 dev_info(&pdev->dev,
1151 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1152 adapter->msix_entries ? "MSI-X" :
1153 adapter->msi_enabled ? "MSI" : "legacy",
1154 adapter->num_rx_queues, adapter->num_tx_queues);
1155
9d5c8243
AK		 1156 return 0;
1157
1158err_register:
1159 igb_release_hw_control(adapter);
1160err_eeprom:
1161 if (!igb_check_reset_block(hw))
1162 hw->phy.ops.reset_phy(hw);
1163
1164 if (hw->flash_address)
1165 iounmap(hw->flash_address);
1166
1167 igb_remove_device(hw);
1168 kfree(adapter->tx_ring);
1169 kfree(adapter->rx_ring);
1170err_sw_init:
1171err_hw_init:
1172 iounmap(hw->hw_addr);
1173err_ioremap:
1174 free_netdev(netdev);
1175err_alloc_etherdev:
42bfd33a 1176 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1177err_pci_reg:
1178err_dma:
1179 pci_disable_device(pdev);
1180 return err;
1181}
1182
1183/**
1184 * igb_remove - Device Removal Routine
1185 * @pdev: PCI device information struct
1186 *
1187 * igb_remove is called by the PCI subsystem to alert the driver
1188 * that it should release a PCI device. The could be caused by a
1189 * Hot-Plug event, or because the driver is going to be removed from
1190 * memory.
1191 **/
1192static void __devexit igb_remove(struct pci_dev *pdev)
1193{
1194 struct net_device *netdev = pci_get_drvdata(pdev);
1195 struct igb_adapter *adapter = netdev_priv(netdev);
1196
1197 /* flush_scheduled work may reschedule our watchdog task, so
1198 * explicitly disable watchdog tasks from being rescheduled */
1199 set_bit(__IGB_DOWN, &adapter->state);
1200 del_timer_sync(&adapter->watchdog_timer);
1201 del_timer_sync(&adapter->phy_info_timer);
1202
1203 flush_scheduled_work();
1204
9d5c8243
AK		 1205 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1206 * would have already happened in close and is redundant. */
1207 igb_release_hw_control(adapter);
1208
1209 unregister_netdev(netdev);
1210
1211 if (!igb_check_reset_block(&adapter->hw))
1212 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1213
1214 igb_remove_device(&adapter->hw);
1215 igb_reset_interrupt_capability(adapter);
1216
1217 kfree(adapter->tx_ring);
1218 kfree(adapter->rx_ring);
1219
1220 iounmap(adapter->hw.hw_addr);
1221 if (adapter->hw.flash_address)
1222 iounmap(adapter->hw.flash_address);
42bfd33a 1223 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1224
1225 free_netdev(netdev);
1226
1227 pci_disable_device(pdev);
1228}
1229
1230/**
1231 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1232 * @adapter: board private structure to initialize
1233 *
1234 * igb_sw_init initializes the Adapter private data structure.
1235 * Fields are initialized based on PCI device information and
1236 * OS network device settings (MTU size).
1237 **/
1238static int __devinit igb_sw_init(struct igb_adapter *adapter)
1239{
1240 struct e1000_hw *hw = &adapter->hw;
1241 struct net_device *netdev = adapter->netdev;
1242 struct pci_dev *pdev = adapter->pdev;
1243
1244 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1245
1246 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1247 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1248 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1249 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1250
1251 /* Number of supported queues. */
1252 /* Having more queues than CPUs doesn't make sense. */
661086df
PWJ		 1253 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1254#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1255 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1256#else
9d5c8243 1257 adapter->num_tx_queues = 1;
661086df 1258#endif /* CONFIG_NET_MULTI_QUEUE_DEVICE */
9d5c8243 1259
661086df
PWJ		 1260 /* This call may decrease the number of queues depending on
1261 * interrupt mode. */
9d5c8243
AK		 1262 igb_set_interrupt_capability(adapter);
1263
1264 if (igb_alloc_queues(adapter)) {
1265 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1266 return -ENOMEM;
1267 }
1268
1269 /* Explicitly disable IRQ since the NIC can be in any state. */
1270 igb_irq_disable(adapter);
1271
1272 set_bit(__IGB_DOWN, &adapter->state);
1273 return 0;
1274}
1275
1276/**
1277 * igb_open - Called when a network interface is made active
1278 * @netdev: network interface device structure
1279 *
1280 * Returns 0 on success, negative value on failure
1281 *
1282 * The open entry point is called when a network interface is made
1283 * active by the system (IFF_UP). At this point all resources needed
1284 * for transmit and receive operations are allocated, the interrupt
1285 * handler is registered with the OS, the watchdog timer is started,
1286 * and the stack is notified that the interface is ready.
1287 **/
1288static int igb_open(struct net_device *netdev)
1289{
1290 struct igb_adapter *adapter = netdev_priv(netdev);
1291 struct e1000_hw *hw = &adapter->hw;
1292 int err;
1293 int i;
1294
1295 /* disallow open during test */
1296 if (test_bit(__IGB_TESTING, &adapter->state))
1297 return -EBUSY;
1298
1299 /* allocate transmit descriptors */
1300 err = igb_setup_all_tx_resources(adapter);
1301 if (err)
1302 goto err_setup_tx;
1303
1304 /* allocate receive descriptors */
1305 err = igb_setup_all_rx_resources(adapter);
1306 if (err)
1307 goto err_setup_rx;
1308
1309 /* e1000_power_up_phy(adapter); */
1310
1311 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1312 if ((adapter->hw.mng_cookie.status &
1313 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1314 igb_update_mng_vlan(adapter);
1315
1316 /* before we allocate an interrupt, we must be ready to handle it.
1317 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1318 * as soon as we call pci_request_irq, so we have to setup our
1319 * clean_rx handler before we do so. */
1320 igb_configure(adapter);
1321
1322 err = igb_request_irq(adapter);
1323 if (err)
1324 goto err_req_irq;
1325
1326 /* From here on the code is the same as igb_up() */
1327 clear_bit(__IGB_DOWN, &adapter->state);
1328
844290e5
PW		 1329 for (i = 0; i < adapter->num_rx_queues; i++)
1330 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1331
1332 /* Clear any pending interrupts. */
1333 rd32(E1000_ICR);
844290e5
PW		 1334
1335 igb_irq_enable(adapter);
1336
9d5c8243
AK		 1337 /* Fire a link status change interrupt to start the watchdog. */
1338 wr32(E1000_ICS, E1000_ICS_LSC);
1339
1340 return 0;
1341
1342err_req_irq:
1343 igb_release_hw_control(adapter);
1344 /* e1000_power_down_phy(adapter); */
1345 igb_free_all_rx_resources(adapter);
1346err_setup_rx:
1347 igb_free_all_tx_resources(adapter);
1348err_setup_tx:
1349 igb_reset(adapter);
1350
1351 return err;
1352}
1353
1354/**
1355 * igb_close - Disables a network interface
1356 * @netdev: network interface device structure
1357 *
1358 * Returns 0, this is not allowed to fail
1359 *
1360 * The close entry point is called when an interface is de-activated
1361 * by the OS. The hardware is still under the driver's control, but
1362 * needs to be disabled. A global MAC reset is issued to stop the
1363 * hardware, and all transmit and receive resources are freed.
1364 **/
1365static int igb_close(struct net_device *netdev)
1366{
1367 struct igb_adapter *adapter = netdev_priv(netdev);
1368
1369 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1370 igb_down(adapter);
1371
1372 igb_free_irq(adapter);
1373
1374 igb_free_all_tx_resources(adapter);
1375 igb_free_all_rx_resources(adapter);
1376
1377 /* kill manageability vlan ID if supported, but not if a vlan with
1378 * the same ID is registered on the host OS (let 8021q kill it) */
1379 if ((adapter->hw.mng_cookie.status &
1380 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1381 !(adapter->vlgrp &&
1382 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1383 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1384
1385 return 0;
1386}
1387
1388/**
1389 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1390 * @adapter: board private structure
1391 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1392 *
1393 * Return 0 on success, negative on failure
1394 **/
1395
1396int igb_setup_tx_resources(struct igb_adapter *adapter,
1397 struct igb_ring *tx_ring)
1398{
1399 struct pci_dev *pdev = adapter->pdev;
1400 int size;
1401
1402 size = sizeof(struct igb_buffer) * tx_ring->count;
1403 tx_ring->buffer_info = vmalloc(size);
1404 if (!tx_ring->buffer_info)
1405 goto err;
1406 memset(tx_ring->buffer_info, 0, size);
1407
1408 /* round up to nearest 4K */
1409 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1410 + sizeof(u32);
1411 tx_ring->size = ALIGN(tx_ring->size, 4096);
1412
1413 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1414 &tx_ring->dma);
1415
1416 if (!tx_ring->desc)
1417 goto err;
1418
1419 tx_ring->adapter = adapter;
1420 tx_ring->next_to_use = 0;
1421 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1422 return 0;
1423
1424err:
1425 vfree(tx_ring->buffer_info);
1426 dev_err(&adapter->pdev->dev,
1427 "Unable to allocate memory for the transmit descriptor ring\n");
1428 return -ENOMEM;
1429}
1430
1431/**
1432 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1433 * (Descriptors) for all queues
1434 * @adapter: board private structure
1435 *
1436 * Return 0 on success, negative on failure
1437 **/
1438static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1439{
1440 int i, err = 0;
661086df
PWJ		 1441#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1442 int r_idx;
1443#endif
9d5c8243
AK		 1444
1445 for (i = 0; i < adapter->num_tx_queues; i++) {
1446 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1447 if (err) {
1448 dev_err(&adapter->pdev->dev,
1449 "Allocation for Tx Queue %u failed\n", i);
1450 for (i--; i >= 0; i--)
3b644cf6 1451 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1452 break;
1453 }
1454 }
1455
661086df
PWJ		 1456#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1457 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1458 r_idx = i % adapter->num_tx_queues;
1459 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1460 }
1461#endif
9d5c8243
AK		 1462 return err;
1463}
1464
1465/**
1466 * igb_configure_tx - Configure transmit Unit after Reset
1467 * @adapter: board private structure
1468 *
1469 * Configure the Tx unit of the MAC after a reset.
1470 **/
1471static void igb_configure_tx(struct igb_adapter *adapter)
1472{
1473 u64 tdba, tdwba;
1474 struct e1000_hw *hw = &adapter->hw;
1475 u32 tctl;
1476 u32 txdctl, txctrl;
1477 int i;
1478
1479 for (i = 0; i < adapter->num_tx_queues; i++) {
1480 struct igb_ring *ring = &(adapter->tx_ring[i]);
1481
1482 wr32(E1000_TDLEN(i),
1483 ring->count * sizeof(struct e1000_tx_desc));
1484 tdba = ring->dma;
1485 wr32(E1000_TDBAL(i),
1486 tdba & 0x00000000ffffffffULL);
1487 wr32(E1000_TDBAH(i), tdba >> 32);
1488
1489 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1490 tdwba |= 1; /* enable head wb */
1491 wr32(E1000_TDWBAL(i),
1492 tdwba & 0x00000000ffffffffULL);
1493 wr32(E1000_TDWBAH(i), tdwba >> 32);
1494
1495 ring->head = E1000_TDH(i);
1496 ring->tail = E1000_TDT(i);
1497 writel(0, hw->hw_addr + ring->tail);
1498 writel(0, hw->hw_addr + ring->head);
1499 txdctl = rd32(E1000_TXDCTL(i));
1500 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1501 wr32(E1000_TXDCTL(i), txdctl);
1502
1503 /* Turn off Relaxed Ordering on head write-backs. The
1504 * writebacks MUST be delivered in order or it will
1505 * completely screw up our bookeeping.
1506 */
1507 txctrl = rd32(E1000_DCA_TXCTRL(i));
1508 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1509 wr32(E1000_DCA_TXCTRL(i), txctrl);
1510 }
1511
1512
1513
1514 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1515
1516 /* Program the Transmit Control Register */
1517
1518 tctl = rd32(E1000_TCTL);
1519 tctl &= ~E1000_TCTL_CT;
1520 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1521 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1522
1523 igb_config_collision_dist(hw);
1524
1525 /* Setup Transmit Descriptor Settings for eop descriptor */
1526 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1527
1528 /* Enable transmits */
1529 tctl |= E1000_TCTL_EN;
1530
1531 wr32(E1000_TCTL, tctl);
1532}
1533
1534/**
1535 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1536 * @adapter: board private structure
1537 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1538 *
1539 * Returns 0 on success, negative on failure
1540 **/
1541
1542int igb_setup_rx_resources(struct igb_adapter *adapter,
1543 struct igb_ring *rx_ring)
1544{
1545 struct pci_dev *pdev = adapter->pdev;
1546 int size, desc_len;
1547
1548 size = sizeof(struct igb_buffer) * rx_ring->count;
1549 rx_ring->buffer_info = vmalloc(size);
1550 if (!rx_ring->buffer_info)
1551 goto err;
1552 memset(rx_ring->buffer_info, 0, size);
1553
1554 desc_len = sizeof(union e1000_adv_rx_desc);
1555
1556 /* Round up to nearest 4K */
1557 rx_ring->size = rx_ring->count * desc_len;
1558 rx_ring->size = ALIGN(rx_ring->size, 4096);
1559
1560 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1561 &rx_ring->dma);
1562
1563 if (!rx_ring->desc)
1564 goto err;
1565
1566 rx_ring->next_to_clean = 0;
1567 rx_ring->next_to_use = 0;
1568 rx_ring->pending_skb = NULL;
1569
1570 rx_ring->adapter = adapter;
9d5c8243
AK		 1571
1572 return 0;
1573
1574err:
1575 vfree(rx_ring->buffer_info);
1576 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1577 "the receive descriptor ring\n");
1578 return -ENOMEM;
1579}
1580
1581/**
1582 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1583 * (Descriptors) for all queues
1584 * @adapter: board private structure
1585 *
1586 * Return 0 on success, negative on failure
1587 **/
1588static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1589{
1590 int i, err = 0;
1591
1592 for (i = 0; i < adapter->num_rx_queues; i++) {
1593 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1594 if (err) {
1595 dev_err(&adapter->pdev->dev,
1596 "Allocation for Rx Queue %u failed\n", i);
1597 for (i--; i >= 0; i--)
3b644cf6 1598 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1599 break;
1600 }
1601 }
1602
1603 return err;
1604}
1605
1606/**
1607 * igb_setup_rctl - configure the receive control registers
1608 * @adapter: Board private structure
1609 **/
1610static void igb_setup_rctl(struct igb_adapter *adapter)
1611{
1612 struct e1000_hw *hw = &adapter->hw;
1613 u32 rctl;
1614 u32 srrctl = 0;
1615 int i;
1616
1617 rctl = rd32(E1000_RCTL);
1618
1619 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1620
1621 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1622 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1623 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1624
1625 /* disable the stripping of CRC because it breaks
1626 * BMC firmware connected over SMBUS
1627 rctl |= E1000_RCTL_SECRC;
1628 */
1629
1630 rctl &= ~E1000_RCTL_SBP;
1631
1632 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1633 rctl &= ~E1000_RCTL_LPE;
1634 else
1635 rctl |= E1000_RCTL_LPE;
1636 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1637 /* Setup buffer sizes */
1638 rctl &= ~E1000_RCTL_SZ_4096;
1639 rctl |= E1000_RCTL_BSEX;
1640 switch (adapter->rx_buffer_len) {
1641 case IGB_RXBUFFER_256:
1642 rctl |= E1000_RCTL_SZ_256;
1643 rctl &= ~E1000_RCTL_BSEX;
1644 break;
1645 case IGB_RXBUFFER_512:
1646 rctl |= E1000_RCTL_SZ_512;
1647 rctl &= ~E1000_RCTL_BSEX;
1648 break;
1649 case IGB_RXBUFFER_1024:
1650 rctl |= E1000_RCTL_SZ_1024;
1651 rctl &= ~E1000_RCTL_BSEX;
1652 break;
1653 case IGB_RXBUFFER_2048:
1654 default:
1655 rctl |= E1000_RCTL_SZ_2048;
1656 rctl &= ~E1000_RCTL_BSEX;
1657 break;
1658 case IGB_RXBUFFER_4096:
1659 rctl |= E1000_RCTL_SZ_4096;
1660 break;
1661 case IGB_RXBUFFER_8192:
1662 rctl |= E1000_RCTL_SZ_8192;
1663 break;
1664 case IGB_RXBUFFER_16384:
1665 rctl |= E1000_RCTL_SZ_16384;
1666 break;
1667 }
1668 } else {
1669 rctl &= ~E1000_RCTL_BSEX;
1670 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1671 }
1672
1673 /* 82575 and greater support packet-split where the protocol
1674 * header is placed in skb->data and the packet data is
1675 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1676 * In the case of a non-split, skb->data is linearly filled,
1677 * followed by the page buffers. Therefore, skb->data is
1678 * sized to hold the largest protocol header.
1679 */
1680 /* allocations using alloc_page take too long for regular MTU
1681 * so only enable packet split for jumbo frames */
1682 if (rctl & E1000_RCTL_LPE) {
1683 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1684 srrctl = adapter->rx_ps_hdr_size <<
1685 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1686 /* buffer size is ALWAYS one page */
1687 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1688 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1689 } else {
1690 adapter->rx_ps_hdr_size = 0;
1691 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1692 }
1693
1694 for (i = 0; i < adapter->num_rx_queues; i++)
1695 wr32(E1000_SRRCTL(i), srrctl);
1696
1697 wr32(E1000_RCTL, rctl);
1698}
1699
1700/**
1701 * igb_configure_rx - Configure receive Unit after Reset
1702 * @adapter: board private structure
1703 *
1704 * Configure the Rx unit of the MAC after a reset.
1705 **/
1706static void igb_configure_rx(struct igb_adapter *adapter)
1707{
1708 u64 rdba;
1709 struct e1000_hw *hw = &adapter->hw;
1710 u32 rctl, rxcsum;
1711 u32 rxdctl;
1712 int i;
1713
1714 /* disable receives while setting up the descriptors */
1715 rctl = rd32(E1000_RCTL);
1716 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1717 wrfl();
1718 mdelay(10);
1719
1720 if (adapter->itr_setting > 3)
1721 wr32(E1000_ITR,
1722 1000000000 / (adapter->itr * 256));
1723
1724 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1725 * the Base and Length of the Rx Descriptor Ring */
1726 for (i = 0; i < adapter->num_rx_queues; i++) {
1727 struct igb_ring *ring = &(adapter->rx_ring[i]);
1728 rdba = ring->dma;
1729 wr32(E1000_RDBAL(i),
1730 rdba & 0x00000000ffffffffULL);
1731 wr32(E1000_RDBAH(i), rdba >> 32);
1732 wr32(E1000_RDLEN(i),
1733 ring->count * sizeof(union e1000_adv_rx_desc));
1734
1735 ring->head = E1000_RDH(i);
1736 ring->tail = E1000_RDT(i);
1737 writel(0, hw->hw_addr + ring->tail);
1738 writel(0, hw->hw_addr + ring->head);
1739
1740 rxdctl = rd32(E1000_RXDCTL(i));
1741 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1742 rxdctl &= 0xFFF00000;
1743 rxdctl |= IGB_RX_PTHRESH;
1744 rxdctl |= IGB_RX_HTHRESH << 8;
1745 rxdctl |= IGB_RX_WTHRESH << 16;
1746 wr32(E1000_RXDCTL(i), rxdctl);
1747 }
1748
1749 if (adapter->num_rx_queues > 1) {
1750 u32 random[10];
1751 u32 mrqc;
1752 u32 j, shift;
1753 union e1000_reta {
1754 u32 dword;
1755 u8 bytes[4];
1756 } reta;
1757
1758 get_random_bytes(&random[0], 40);
1759
1760 shift = 6;
1761 for (j = 0; j < (32 * 4); j++) {
1762 reta.bytes[j & 3] =
1763 (j % adapter->num_rx_queues) << shift;
1764 if ((j & 3) == 3)
1765 writel(reta.dword,
1766 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1767 }
1768 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1769
1770 /* Fill out hash function seeds */
1771 for (j = 0; j < 10; j++)
1772 array_wr32(E1000_RSSRK(0), j, random[j]);
1773
1774 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1775 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1776 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1777 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1778 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1779 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1780 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1781 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1782
1783
1784 wr32(E1000_MRQC, mrqc);
1785
1786 /* Multiqueue and raw packet checksumming are mutually
1787 * exclusive. Note that this not the same as TCP/IP
1788 * checksumming, which works fine. */
1789 rxcsum = rd32(E1000_RXCSUM);
1790 rxcsum |= E1000_RXCSUM_PCSD;
1791 wr32(E1000_RXCSUM, rxcsum);
1792 } else {
1793 /* Enable Receive Checksum Offload for TCP and UDP */
1794 rxcsum = rd32(E1000_RXCSUM);
1795 if (adapter->rx_csum) {
1796 rxcsum |= E1000_RXCSUM_TUOFL;
1797
1798 /* Enable IPv4 payload checksum for UDP fragments
1799 * Must be used in conjunction with packet-split. */
1800 if (adapter->rx_ps_hdr_size)
1801 rxcsum |= E1000_RXCSUM_IPPCSE;
1802 } else {
1803 rxcsum &= ~E1000_RXCSUM_TUOFL;
1804 /* don't need to clear IPPCSE as it defaults to 0 */
1805 }
1806 wr32(E1000_RXCSUM, rxcsum);
1807 }
1808
1809 if (adapter->vlgrp)
1810 wr32(E1000_RLPML,
1811 adapter->max_frame_size + VLAN_TAG_SIZE);
1812 else
1813 wr32(E1000_RLPML, adapter->max_frame_size);
1814
1815 /* Enable Receives */
1816 wr32(E1000_RCTL, rctl);
1817}
1818
1819/**
1820 * igb_free_tx_resources - Free Tx Resources per Queue
1821 * @adapter: board private structure
1822 * @tx_ring: Tx descriptor ring for a specific queue
1823 *
1824 * Free all transmit software resources
1825 **/
3b644cf6 1826static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1827{
3b644cf6 1828 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1829
3b644cf6 1830 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1831
1832 vfree(tx_ring->buffer_info);
1833 tx_ring->buffer_info = NULL;
1834
1835 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1836
1837 tx_ring->desc = NULL;
1838}
1839
1840/**
1841 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1842 * @adapter: board private structure
1843 *
1844 * Free all transmit software resources
1845 **/
1846static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1847{
1848 int i;
1849
1850 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1851 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1852}
1853
1854static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1855 struct igb_buffer *buffer_info)
1856{
1857 if (buffer_info->dma) {
1858 pci_unmap_page(adapter->pdev,
1859 buffer_info->dma,
1860 buffer_info->length,
1861 PCI_DMA_TODEVICE);
1862 buffer_info->dma = 0;
1863 }
1864 if (buffer_info->skb) {
1865 dev_kfree_skb_any(buffer_info->skb);
1866 buffer_info->skb = NULL;
1867 }
1868 buffer_info->time_stamp = 0;
1869 /* buffer_info must be completely set up in the transmit path */
1870}
1871
1872/**
1873 * igb_clean_tx_ring - Free Tx Buffers
1874 * @adapter: board private structure
1875 * @tx_ring: ring to be cleaned
1876 **/
3b644cf6 1877static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 1878{
3b644cf6 1879 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 1880 struct igb_buffer *buffer_info;
1881 unsigned long size;
1882 unsigned int i;
1883
1884 if (!tx_ring->buffer_info)
1885 return;
1886 /* Free all the Tx ring sk_buffs */
1887
1888 for (i = 0; i < tx_ring->count; i++) {
1889 buffer_info = &tx_ring->buffer_info[i];
1890 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1891 }
1892
1893 size = sizeof(struct igb_buffer) * tx_ring->count;
1894 memset(tx_ring->buffer_info, 0, size);
1895
1896 /* Zero out the descriptor ring */
1897
1898 memset(tx_ring->desc, 0, tx_ring->size);
1899
1900 tx_ring->next_to_use = 0;
1901 tx_ring->next_to_clean = 0;
1902
1903 writel(0, adapter->hw.hw_addr + tx_ring->head);
1904 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1905}
1906
1907/**
1908 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1909 * @adapter: board private structure
1910 **/
1911static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1912{
1913 int i;
1914
1915 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1916 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 1917}
1918
1919/**
1920 * igb_free_rx_resources - Free Rx Resources
1921 * @adapter: board private structure
1922 * @rx_ring: ring to clean the resources from
1923 *
1924 * Free all receive software resources
1925 **/
3b644cf6 1926static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 1927{
3b644cf6 1928 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 1929
3b644cf6 1930 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 1931
1932 vfree(rx_ring->buffer_info);
1933 rx_ring->buffer_info = NULL;
1934
1935 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1936
1937 rx_ring->desc = NULL;
1938}
1939
1940/**
1941 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1942 * @adapter: board private structure
1943 *
1944 * Free all receive software resources
1945 **/
1946static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1947{
1948 int i;
1949
1950 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 1951 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1952}
1953
1954/**
1955 * igb_clean_rx_ring - Free Rx Buffers per Queue
1956 * @adapter: board private structure
1957 * @rx_ring: ring to free buffers from
1958 **/
3b644cf6 1959static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 1960{
3b644cf6 1961 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 1962 struct igb_buffer *buffer_info;
1963 struct pci_dev *pdev = adapter->pdev;
1964 unsigned long size;
1965 unsigned int i;
1966
1967 if (!rx_ring->buffer_info)
1968 return;
1969 /* Free all the Rx ring sk_buffs */
1970 for (i = 0; i < rx_ring->count; i++) {
1971 buffer_info = &rx_ring->buffer_info[i];
1972 if (buffer_info->dma) {
1973 if (adapter->rx_ps_hdr_size)
1974 pci_unmap_single(pdev, buffer_info->dma,
1975 adapter->rx_ps_hdr_size,
1976 PCI_DMA_FROMDEVICE);
1977 else
1978 pci_unmap_single(pdev, buffer_info->dma,
1979 adapter->rx_buffer_len,
1980 PCI_DMA_FROMDEVICE);
1981 buffer_info->dma = 0;
1982 }
1983
1984 if (buffer_info->skb) {
1985 dev_kfree_skb(buffer_info->skb);
1986 buffer_info->skb = NULL;
1987 }
1988 if (buffer_info->page) {
1989 pci_unmap_page(pdev, buffer_info->page_dma,
1990 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1991 put_page(buffer_info->page);
1992 buffer_info->page = NULL;
1993 buffer_info->page_dma = 0;
1994 }
1995 }
1996
1997 /* there also may be some cached data from a chained receive */
1998 if (rx_ring->pending_skb) {
1999 dev_kfree_skb(rx_ring->pending_skb);
2000 rx_ring->pending_skb = NULL;
2001 }
2002
2003 size = sizeof(struct igb_buffer) * rx_ring->count;
2004 memset(rx_ring->buffer_info, 0, size);
2005
2006 /* Zero out the descriptor ring */
2007 memset(rx_ring->desc, 0, rx_ring->size);
2008
2009 rx_ring->next_to_clean = 0;
2010 rx_ring->next_to_use = 0;
2011
2012 writel(0, adapter->hw.hw_addr + rx_ring->head);
2013 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2014}
2015
2016/**
2017 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2018 * @adapter: board private structure
2019 **/
2020static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2021{
2022 int i;
2023
2024 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2025 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2026}
2027
2028/**
2029 * igb_set_mac - Change the Ethernet Address of the NIC
2030 * @netdev: network interface device structure
2031 * @p: pointer to an address structure
2032 *
2033 * Returns 0 on success, negative on failure
2034 **/
2035static int igb_set_mac(struct net_device *netdev, void *p)
2036{
2037 struct igb_adapter *adapter = netdev_priv(netdev);
2038 struct sockaddr *addr = p;
2039
2040 if (!is_valid_ether_addr(addr->sa_data))
2041 return -EADDRNOTAVAIL;
2042
2043 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2044 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2045
2046 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2047
2048 return 0;
2049}
2050
2051/**
2052 * igb_set_multi - Multicast and Promiscuous mode set
2053 * @netdev: network interface device structure
2054 *
2055 * The set_multi entry point is called whenever the multicast address
2056 * list or the network interface flags are updated. This routine is
2057 * responsible for configuring the hardware for proper multicast,
2058 * promiscuous mode, and all-multi behavior.
2059 **/
2060static void igb_set_multi(struct net_device *netdev)
2061{
2062 struct igb_adapter *adapter = netdev_priv(netdev);
2063 struct e1000_hw *hw = &adapter->hw;
2064 struct e1000_mac_info *mac = &hw->mac;
2065 struct dev_mc_list *mc_ptr;
2066 u8 *mta_list;
2067 u32 rctl;
2068 int i;
2069
2070 /* Check for Promiscuous and All Multicast modes */
2071
2072 rctl = rd32(E1000_RCTL);
2073
2074 if (netdev->flags & IFF_PROMISC)
2075 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2076 else if (netdev->flags & IFF_ALLMULTI) {
2077 rctl |= E1000_RCTL_MPE;
2078 rctl &= ~E1000_RCTL_UPE;
2079 } else
2080 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2081
2082 wr32(E1000_RCTL, rctl);
2083
2084 if (!netdev->mc_count) {
2085 /* nothing to program, so clear mc list */
2086 igb_update_mc_addr_list(hw, NULL, 0, 1,
2087 mac->rar_entry_count);
2088 return;
2089 }
2090
2091 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2092 if (!mta_list)
2093 return;
2094
2095 /* The shared function expects a packed array of only addresses. */
2096 mc_ptr = netdev->mc_list;
2097
2098 for (i = 0; i < netdev->mc_count; i++) {
2099 if (!mc_ptr)
2100 break;
2101 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2102 mc_ptr = mc_ptr->next;
2103 }
2104 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2105 kfree(mta_list);
2106}
2107
2108/* Need to wait a few seconds after link up to get diagnostic information from
2109 * the phy */
2110static void igb_update_phy_info(unsigned long data)
2111{
2112 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2113 if (adapter->hw.phy.ops.get_phy_info)
2114 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2115}
2116
2117/**
2118 * igb_watchdog - Timer Call-back
2119 * @data: pointer to adapter cast into an unsigned long
2120 **/
2121static void igb_watchdog(unsigned long data)
2122{
2123 struct igb_adapter *adapter = (struct igb_adapter *)data;
2124 /* Do the rest outside of interrupt context */
2125 schedule_work(&adapter->watchdog_task);
2126}
2127
2128static void igb_watchdog_task(struct work_struct *work)
2129{
2130 struct igb_adapter *adapter = container_of(work,
2131 struct igb_adapter, watchdog_task);
2132 struct e1000_hw *hw = &adapter->hw;
2133
2134 struct net_device *netdev = adapter->netdev;
2135 struct igb_ring *tx_ring = adapter->tx_ring;
2136 struct e1000_mac_info *mac = &adapter->hw.mac;
2137 u32 link;
2138 s32 ret_val;
661086df
PWJ		 2139#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2140 int i;
2141#endif
9d5c8243
AK		 2142
2143 if ((netif_carrier_ok(netdev)) &&
2144 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2145 goto link_up;
2146
2147 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2148 if ((ret_val == E1000_ERR_PHY) &&
2149 (hw->phy.type == e1000_phy_igp_3) &&
2150 (rd32(E1000_CTRL) &
2151 E1000_PHY_CTRL_GBE_DISABLE))
2152 dev_info(&adapter->pdev->dev,
2153 "Gigabit has been disabled, downgrading speed\n");
2154
2155 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2156 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2157 link = mac->serdes_has_link;
2158 else
2159 link = rd32(E1000_STATUS) &
2160 E1000_STATUS_LU;
2161
2162 if (link) {
2163 if (!netif_carrier_ok(netdev)) {
2164 u32 ctrl;
2165 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2166 &adapter->link_speed,
2167 &adapter->link_duplex);
2168
2169 ctrl = rd32(E1000_CTRL);
2170 dev_info(&adapter->pdev->dev,
2171 "NIC Link is Up %d Mbps %s, "
2172 "Flow Control: %s\n",
2173 adapter->link_speed,
2174 adapter->link_duplex == FULL_DUPLEX ?
2175 "Full Duplex" : "Half Duplex",
2176 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2177 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2178 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2179 E1000_CTRL_TFCE) ? "TX" : "None")));
2180
2181 /* tweak tx_queue_len according to speed/duplex and
2182 * adjust the timeout factor */
2183 netdev->tx_queue_len = adapter->tx_queue_len;
2184 adapter->tx_timeout_factor = 1;
2185 switch (adapter->link_speed) {
2186 case SPEED_10:
2187 netdev->tx_queue_len = 10;
2188 adapter->tx_timeout_factor = 14;
2189 break;
2190 case SPEED_100:
2191 netdev->tx_queue_len = 100;
2192 /* maybe add some timeout factor ? */
2193 break;
2194 }
2195
2196 netif_carrier_on(netdev);
2197 netif_wake_queue(netdev);
661086df
PWJ		 2198#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2199 for (i = 0; i < adapter->num_tx_queues; i++)
2200 netif_wake_subqueue(netdev, i);
2201#endif
9d5c8243
AK		 2202
2203 if (!test_bit(__IGB_DOWN, &adapter->state))
2204 mod_timer(&adapter->phy_info_timer,
2205 round_jiffies(jiffies + 2 * HZ));
2206 }
2207 } else {
2208 if (netif_carrier_ok(netdev)) {
2209 adapter->link_speed = 0;
2210 adapter->link_duplex = 0;
2211 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2212 netif_carrier_off(netdev);
2213 netif_stop_queue(netdev);
661086df
PWJ		 2214#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2215 for (i = 0; i < adapter->num_tx_queues; i++)
2216 netif_stop_subqueue(netdev, i);
2217#endif
9d5c8243
AK		 2218 if (!test_bit(__IGB_DOWN, &adapter->state))
2219 mod_timer(&adapter->phy_info_timer,
2220 round_jiffies(jiffies + 2 * HZ));
2221 }
2222 }
2223
2224link_up:
2225 igb_update_stats(adapter);
2226
2227 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2228 adapter->tpt_old = adapter->stats.tpt;
2229 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2230 adapter->colc_old = adapter->stats.colc;
2231
2232 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2233 adapter->gorc_old = adapter->stats.gorc;
2234 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2235 adapter->gotc_old = adapter->stats.gotc;
2236
2237 igb_update_adaptive(&adapter->hw);
2238
2239 if (!netif_carrier_ok(netdev)) {
2240 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2241 /* We've lost link, so the controller stops DMA,
2242 * but we've got queued Tx work that's never going
2243 * to get done, so reset controller to flush Tx.
2244 * (Do the reset outside of interrupt context). */
2245 adapter->tx_timeout_count++;
2246 schedule_work(&adapter->reset_task);
2247 }
2248 }
2249
2250 /* Cause software interrupt to ensure rx ring is cleaned */
2251 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2252
2253 /* Force detection of hung controller every watchdog period */
2254 tx_ring->detect_tx_hung = true;
2255
2256 /* Reset the timer */
2257 if (!test_bit(__IGB_DOWN, &adapter->state))
2258 mod_timer(&adapter->watchdog_timer,
2259 round_jiffies(jiffies + 2 * HZ));
2260}
2261
2262enum latency_range {
2263 lowest_latency = 0,
2264 low_latency = 1,
2265 bulk_latency = 2,
2266 latency_invalid = 255
2267};
2268
2269
2270static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2271 struct igb_ring *rx_ring)
2272{
2273 struct e1000_hw *hw = &adapter->hw;
2274 int new_val;
2275
2276 new_val = rx_ring->itr_val / 2;
2277 if (new_val < IGB_MIN_DYN_ITR)
2278 new_val = IGB_MIN_DYN_ITR;
2279
2280 if (new_val != rx_ring->itr_val) {
2281 rx_ring->itr_val = new_val;
2282 wr32(rx_ring->itr_register,
2283 1000000000 / (new_val * 256));
2284 }
2285}
2286
2287static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2288 struct igb_ring *rx_ring)
2289{
2290 struct e1000_hw *hw = &adapter->hw;
2291 int new_val;
2292
2293 new_val = rx_ring->itr_val * 2;
2294 if (new_val > IGB_MAX_DYN_ITR)
2295 new_val = IGB_MAX_DYN_ITR;
2296
2297 if (new_val != rx_ring->itr_val) {
2298 rx_ring->itr_val = new_val;
2299 wr32(rx_ring->itr_register,
2300 1000000000 / (new_val * 256));
2301 }
2302}
2303
2304/**
2305 * igb_update_itr - update the dynamic ITR value based on statistics
2306 * Stores a new ITR value based on packets and byte
2307 * counts during the last interrupt. The advantage of per interrupt
2308 * computation is faster updates and more accurate ITR for the current
2309 * traffic pattern. Constants in this function were computed
2310 * based on theoretical maximum wire speed and thresholds were set based
2311 * on testing data as well as attempting to minimize response time
2312 * while increasing bulk throughput.
2313 * this functionality is controlled by the InterruptThrottleRate module
2314 * parameter (see igb_param.c)
2315 * NOTE: These calculations are only valid when operating in a single-
2316 * queue environment.
2317 * @adapter: pointer to adapter
2318 * @itr_setting: current adapter->itr
2319 * @packets: the number of packets during this measurement interval
2320 * @bytes: the number of bytes during this measurement interval
2321 **/
2322static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2323 int packets, int bytes)
2324{
2325 unsigned int retval = itr_setting;
2326
2327 if (packets == 0)
2328 goto update_itr_done;
2329
2330 switch (itr_setting) {
2331 case lowest_latency:
2332 /* handle TSO and jumbo frames */
2333 if (bytes/packets > 8000)
2334 retval = bulk_latency;
2335 else if ((packets < 5) && (bytes > 512))
2336 retval = low_latency;
2337 break;
2338 case low_latency: /* 50 usec aka 20000 ints/s */
2339 if (bytes > 10000) {
2340 /* this if handles the TSO accounting */
2341 if (bytes/packets > 8000) {
2342 retval = bulk_latency;
2343 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2344 retval = bulk_latency;
2345 } else if ((packets > 35)) {
2346 retval = lowest_latency;
2347 }
2348 } else if (bytes/packets > 2000) {
2349 retval = bulk_latency;
2350 } else if (packets <= 2 && bytes < 512) {
2351 retval = lowest_latency;
2352 }
2353 break;
2354 case bulk_latency: /* 250 usec aka 4000 ints/s */
2355 if (bytes > 25000) {
2356 if (packets > 35)
2357 retval = low_latency;
2358 } else if (bytes < 6000) {
2359 retval = low_latency;
2360 }
2361 break;
2362 }
2363
2364update_itr_done:
2365 return retval;
2366}
2367
2368static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2369 int rx_only)
2370{
2371 u16 current_itr;
2372 u32 new_itr = adapter->itr;
2373
2374 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2375 if (adapter->link_speed != SPEED_1000) {
2376 current_itr = 0;
2377 new_itr = 4000;
2378 goto set_itr_now;
2379 }
2380
2381 adapter->rx_itr = igb_update_itr(adapter,
2382 adapter->rx_itr,
2383 adapter->rx_ring->total_packets,
2384 adapter->rx_ring->total_bytes);
2385 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2386 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2387 adapter->rx_itr = low_latency;
2388
2389 if (!rx_only) {
2390 adapter->tx_itr = igb_update_itr(adapter,
2391 adapter->tx_itr,
2392 adapter->tx_ring->total_packets,
2393 adapter->tx_ring->total_bytes);
2394 /* conservative mode (itr 3) eliminates the
2395 * lowest_latency setting */
2396 if (adapter->itr_setting == 3 &&
2397 adapter->tx_itr == lowest_latency)
2398 adapter->tx_itr = low_latency;
2399
2400 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2401 } else {
2402 current_itr = adapter->rx_itr;
2403 }
2404
2405 switch (current_itr) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency:
2408 new_itr = 70000;
2409 break;
2410 case low_latency:
2411 new_itr = 20000; /* aka hwitr = ~200 */
2412 break;
2413 case bulk_latency:
2414 new_itr = 4000;
2415 break;
2416 default:
2417 break;
2418 }
2419
2420set_itr_now:
2421 if (new_itr != adapter->itr) {
2422 /* this attempts to bias the interrupt rate towards Bulk
2423 * by adding intermediate steps when interrupt rate is
2424 * increasing */
2425 new_itr = new_itr > adapter->itr ?
2426 min(adapter->itr + (new_itr >> 2), new_itr) :
2427 new_itr;
2428 /* Don't write the value here; it resets the adapter's
2429 * internal timer, and causes us to delay far longer than
2430 * we should between interrupts. Instead, we write the ITR
2431 * value at the beginning of the next interrupt so the timing
2432 * ends up being correct.
2433 */
2434 adapter->itr = new_itr;
2435 adapter->set_itr = 1;
2436 }
2437
2438 return;
2439}
2440
2441
2442#define IGB_TX_FLAGS_CSUM 0x00000001
2443#define IGB_TX_FLAGS_VLAN 0x00000002
2444#define IGB_TX_FLAGS_TSO 0x00000004
2445#define IGB_TX_FLAGS_IPV4 0x00000008
2446#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2447#define IGB_TX_FLAGS_VLAN_SHIFT 16
2448
2449static inline int igb_tso_adv(struct igb_adapter *adapter,
2450 struct igb_ring *tx_ring,
2451 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2452{
2453 struct e1000_adv_tx_context_desc *context_desc;
2454 unsigned int i;
2455 int err;
2456 struct igb_buffer *buffer_info;
2457 u32 info = 0, tu_cmd = 0;
2458 u32 mss_l4len_idx, l4len;
2459 *hdr_len = 0;
2460
2461 if (skb_header_cloned(skb)) {
2462 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2463 if (err)
2464 return err;
2465 }
2466
2467 l4len = tcp_hdrlen(skb);
2468 *hdr_len += l4len;
2469
2470 if (skb->protocol == htons(ETH_P_IP)) {
2471 struct iphdr *iph = ip_hdr(skb);
2472 iph->tot_len = 0;
2473 iph->check = 0;
2474 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2475 iph->daddr, 0,
2476 IPPROTO_TCP,
2477 0);
2478 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2479 ipv6_hdr(skb)->payload_len = 0;
2480 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2481 &ipv6_hdr(skb)->daddr,
2482 0, IPPROTO_TCP, 0);
2483 }
2484
2485 i = tx_ring->next_to_use;
2486
2487 buffer_info = &tx_ring->buffer_info[i];
2488 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2489 /* VLAN MACLEN IPLEN */
2490 if (tx_flags & IGB_TX_FLAGS_VLAN)
2491 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2492 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2493 *hdr_len += skb_network_offset(skb);
2494 info |= skb_network_header_len(skb);
2495 *hdr_len += skb_network_header_len(skb);
2496 context_desc->vlan_macip_lens = cpu_to_le32(info);
2497
2498 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2499 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2500
2501 if (skb->protocol == htons(ETH_P_IP))
2502 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2503 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2504
2505 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2506
2507 /* MSS L4LEN IDX */
2508 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2509 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2510
2511 /* Context index must be unique per ring. Luckily, so is the interrupt
2512 * mask value. */
2513 mss_l4len_idx |= tx_ring->eims_value >> 4;
2514
2515 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2516 context_desc->seqnum_seed = 0;
2517
2518 buffer_info->time_stamp = jiffies;
2519 buffer_info->dma = 0;
2520 i++;
2521 if (i == tx_ring->count)
2522 i = 0;
2523
2524 tx_ring->next_to_use = i;
2525
2526 return true;
2527}
2528
2529static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2530 struct igb_ring *tx_ring,
2531 struct sk_buff *skb, u32 tx_flags)
2532{
2533 struct e1000_adv_tx_context_desc *context_desc;
2534 unsigned int i;
2535 struct igb_buffer *buffer_info;
2536 u32 info = 0, tu_cmd = 0;
2537
2538 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2539 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2540 i = tx_ring->next_to_use;
2541 buffer_info = &tx_ring->buffer_info[i];
2542 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2543
2544 if (tx_flags & IGB_TX_FLAGS_VLAN)
2545 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2546 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2547 if (skb->ip_summed == CHECKSUM_PARTIAL)
2548 info |= skb_network_header_len(skb);
2549
2550 context_desc->vlan_macip_lens = cpu_to_le32(info);
2551
2552 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2553
2554 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2555 switch (skb->protocol) {
2556 case __constant_htons(ETH_P_IP):
9d5c8243 2557 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2558 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2559 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2560 break;
2561 case __constant_htons(ETH_P_IPV6):
2562 /* XXX what about other V6 headers?? */
2563 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2564 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2565 break;
2566 default:
2567 if (unlikely(net_ratelimit()))
2568 dev_warn(&adapter->pdev->dev,
2569 "partial checksum but proto=%x!\n",
2570 skb->protocol);
2571 break;
2572 }
9d5c8243
AK		 2573 }
2574
2575 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2576 context_desc->seqnum_seed = 0;
2577 context_desc->mss_l4len_idx =
661086df 2578 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2579
2580 buffer_info->time_stamp = jiffies;
2581 buffer_info->dma = 0;
2582
2583 i++;
2584 if (i == tx_ring->count)
2585 i = 0;
2586 tx_ring->next_to_use = i;
2587
2588 return true;
2589 }
2590
2591
2592 return false;
2593}
2594
2595#define IGB_MAX_TXD_PWR 16
2596#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2597
2598static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2599 struct igb_ring *tx_ring,
2600 struct sk_buff *skb)
2601{
2602 struct igb_buffer *buffer_info;
2603 unsigned int len = skb_headlen(skb);
2604 unsigned int count = 0, i;
2605 unsigned int f;
2606
2607 i = tx_ring->next_to_use;
2608
2609 buffer_info = &tx_ring->buffer_info[i];
2610 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2611 buffer_info->length = len;
2612 /* set time_stamp *before* dma to help avoid a possible race */
2613 buffer_info->time_stamp = jiffies;
2614 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2615 PCI_DMA_TODEVICE);
2616 count++;
2617 i++;
2618 if (i == tx_ring->count)
2619 i = 0;
2620
2621 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2622 struct skb_frag_struct *frag;
2623
2624 frag = &skb_shinfo(skb)->frags[f];
2625 len = frag->size;
2626
2627 buffer_info = &tx_ring->buffer_info[i];
2628 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2629 buffer_info->length = len;
2630 buffer_info->time_stamp = jiffies;
2631 buffer_info->dma = pci_map_page(adapter->pdev,
2632 frag->page,
2633 frag->page_offset,
2634 len,
2635 PCI_DMA_TODEVICE);
2636
2637 count++;
2638 i++;
2639 if (i == tx_ring->count)
2640 i = 0;
2641 }
2642
2643 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2644 tx_ring->buffer_info[i].skb = skb;
2645
2646 return count;
2647}
2648
2649static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2650 struct igb_ring *tx_ring,
2651 int tx_flags, int count, u32 paylen,
2652 u8 hdr_len)
2653{
2654 union e1000_adv_tx_desc *tx_desc = NULL;
2655 struct igb_buffer *buffer_info;
2656 u32 olinfo_status = 0, cmd_type_len;
2657 unsigned int i;
2658
2659 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2660 E1000_ADVTXD_DCMD_DEXT);
2661
2662 if (tx_flags & IGB_TX_FLAGS_VLAN)
2663 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2664
2665 if (tx_flags & IGB_TX_FLAGS_TSO) {
2666 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2667
2668 /* insert tcp checksum */
2669 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2670
2671 /* insert ip checksum */
2672 if (tx_flags & IGB_TX_FLAGS_IPV4)
2673 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2674
2675 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2676 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2677 }
2678
2679 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2680 IGB_TX_FLAGS_VLAN))
661086df 2681 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2682
2683 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2684
2685 i = tx_ring->next_to_use;
2686 while (count--) {
2687 buffer_info = &tx_ring->buffer_info[i];
2688 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2689 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2690 tx_desc->read.cmd_type_len =
2691 cpu_to_le32(cmd_type_len | buffer_info->length);
2692 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2693 i++;
2694 if (i == tx_ring->count)
2695 i = 0;
2696 }
2697
2698 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2699 /* Force memory writes to complete before letting h/w
2700 * know there are new descriptors to fetch. (Only
2701 * applicable for weak-ordered memory model archs,
2702 * such as IA-64). */
2703 wmb();
2704
2705 tx_ring->next_to_use = i;
2706 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2707 /* we need this if more than one processor can write to our tail
2708 * at a time, it syncronizes IO on IA64/Altix systems */
2709 mmiowb();
2710}
2711
2712static int __igb_maybe_stop_tx(struct net_device *netdev,
2713 struct igb_ring *tx_ring, int size)
2714{
2715 struct igb_adapter *adapter = netdev_priv(netdev);
2716
661086df
PWJ		 2717#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2718 netif_stop_subqueue(netdev, tx_ring->queue_index);
2719#else
9d5c8243 2720 netif_stop_queue(netdev);
661086df
PWJ		 2721#endif
2722
9d5c8243
AK		 2723 /* Herbert's original patch had:
2724 * smp_mb__after_netif_stop_queue();
2725 * but since that doesn't exist yet, just open code it. */
2726 smp_mb();
2727
2728 /* We need to check again in a case another CPU has just
2729 * made room available. */
2730 if (IGB_DESC_UNUSED(tx_ring) < size)
2731 return -EBUSY;
2732
2733 /* A reprieve! */
661086df
PWJ		 2734#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2735 netif_wake_subqueue(netdev, tx_ring->queue_index);
2736#else
2737 netif_wake_queue(netdev);
2738#endif
9d5c8243
AK		 2739 ++adapter->restart_queue;
2740 return 0;
2741}
2742
2743static int igb_maybe_stop_tx(struct net_device *netdev,
2744 struct igb_ring *tx_ring, int size)
2745{
2746 if (IGB_DESC_UNUSED(tx_ring) >= size)
2747 return 0;
2748 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2749}
2750
2751#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2752
2753static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2754 struct net_device *netdev,
2755 struct igb_ring *tx_ring)
2756{
2757 struct igb_adapter *adapter = netdev_priv(netdev);
2758 unsigned int tx_flags = 0;
2759 unsigned int len;
9d5c8243
AK		 2760 u8 hdr_len = 0;
2761 int tso = 0;
2762
2763 len = skb_headlen(skb);
2764
2765 if (test_bit(__IGB_DOWN, &adapter->state)) {
2766 dev_kfree_skb_any(skb);
2767 return NETDEV_TX_OK;
2768 }
2769
2770 if (skb->len <= 0) {
2771 dev_kfree_skb_any(skb);
2772 return NETDEV_TX_OK;
2773 }
2774
9d5c8243
AK		 2775 /* need: 1 descriptor per page,
2776 * + 2 desc gap to keep tail from touching head,
2777 * + 1 desc for skb->data,
2778 * + 1 desc for context descriptor,
2779 * otherwise try next time */
2780 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2781 /* this is a hard error */
9d5c8243
AK		 2782 return NETDEV_TX_BUSY;
2783 }
2784
2785 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2786 tx_flags |= IGB_TX_FLAGS_VLAN;
2787 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2788 }
2789
661086df
PWJ		 2790 if (skb->protocol == htons(ETH_P_IP))
2791 tx_flags |= IGB_TX_FLAGS_IPV4;
2792
9d5c8243
AK		 2793 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2794 &hdr_len) : 0;
2795
2796 if (tso < 0) {
2797 dev_kfree_skb_any(skb);
9d5c8243
AK		 2798 return NETDEV_TX_OK;
2799 }
2800
2801 if (tso)
2802 tx_flags |= IGB_TX_FLAGS_TSO;
2803 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2804 if (skb->ip_summed == CHECKSUM_PARTIAL)
2805 tx_flags |= IGB_TX_FLAGS_CSUM;
2806
9d5c8243
AK		 2807 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2808 igb_tx_map_adv(adapter, tx_ring, skb),
2809 skb->len, hdr_len);
2810
2811 netdev->trans_start = jiffies;
2812
2813 /* Make sure there is space in the ring for the next send. */
2814 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2815
9d5c8243
AK		 2816 return NETDEV_TX_OK;
2817}
2818
2819static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2820{
2821 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 2822 struct igb_ring *tx_ring;
2823
2824#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2825 int r_idx = 0;
2826 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
2827 tx_ring = adapter->multi_tx_table[r_idx];
2828#else
2829 tx_ring = &adapter->tx_ring[0];
2830#endif
2831
9d5c8243
AK		 2832
2833 /* This goes back to the question of how to logically map a tx queue
2834 * to a flow. Right now, performance is impacted slightly negatively
2835 * if using multiple tx queues. If the stack breaks away from a
2836 * single qdisc implementation, we can look at this again. */
2837 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2838}
2839
2840/**
2841 * igb_tx_timeout - Respond to a Tx Hang
2842 * @netdev: network interface device structure
2843 **/
2844static void igb_tx_timeout(struct net_device *netdev)
2845{
2846 struct igb_adapter *adapter = netdev_priv(netdev);
2847 struct e1000_hw *hw = &adapter->hw;
2848
2849 /* Do the reset outside of interrupt context */
2850 adapter->tx_timeout_count++;
2851 schedule_work(&adapter->reset_task);
2852 wr32(E1000_EICS, adapter->eims_enable_mask &
2853 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2854}
2855
2856static void igb_reset_task(struct work_struct *work)
2857{
2858 struct igb_adapter *adapter;
2859 adapter = container_of(work, struct igb_adapter, reset_task);
2860
2861 igb_reinit_locked(adapter);
2862}
2863
2864/**
2865 * igb_get_stats - Get System Network Statistics
2866 * @netdev: network interface device structure
2867 *
2868 * Returns the address of the device statistics structure.
2869 * The statistics are actually updated from the timer callback.
2870 **/
2871static struct net_device_stats *
2872igb_get_stats(struct net_device *netdev)
2873{
2874 struct igb_adapter *adapter = netdev_priv(netdev);
2875
2876 /* only return the current stats */
2877 return &adapter->net_stats;
2878}
2879
2880/**
2881 * igb_change_mtu - Change the Maximum Transfer Unit
2882 * @netdev: network interface device structure
2883 * @new_mtu: new value for maximum frame size
2884 *
2885 * Returns 0 on success, negative on failure
2886 **/
2887static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2888{
2889 struct igb_adapter *adapter = netdev_priv(netdev);
2890 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2891
2892 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2893 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2894 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2895 return -EINVAL;
2896 }
2897
2898#define MAX_STD_JUMBO_FRAME_SIZE 9234
2899 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2900 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2901 return -EINVAL;
2902 }
2903
2904 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2905 msleep(1);
2906 /* igb_down has a dependency on max_frame_size */
2907 adapter->max_frame_size = max_frame;
2908 if (netif_running(netdev))
2909 igb_down(adapter);
2910
2911 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2912 * means we reserve 2 more, this pushes us to allocate from the next
2913 * larger slab size.
2914 * i.e. RXBUFFER_2048 --> size-4096 slab
2915 */
2916
2917 if (max_frame <= IGB_RXBUFFER_256)
2918 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2919 else if (max_frame <= IGB_RXBUFFER_512)
2920 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2921 else if (max_frame <= IGB_RXBUFFER_1024)
2922 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2923 else if (max_frame <= IGB_RXBUFFER_2048)
2924 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2925 else
2926 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2927 /* adjust allocation if LPE protects us, and we aren't using SBP */
2928 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2929 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2930 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2931
2932 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2933 netdev->mtu, new_mtu);
2934 netdev->mtu = new_mtu;
2935
2936 if (netif_running(netdev))
2937 igb_up(adapter);
2938 else
2939 igb_reset(adapter);
2940
2941 clear_bit(__IGB_RESETTING, &adapter->state);
2942
2943 return 0;
2944}
2945
2946/**
2947 * igb_update_stats - Update the board statistics counters
2948 * @adapter: board private structure
2949 **/
2950
2951void igb_update_stats(struct igb_adapter *adapter)
2952{
2953 struct e1000_hw *hw = &adapter->hw;
2954 struct pci_dev *pdev = adapter->pdev;
2955 u16 phy_tmp;
2956
2957#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2958
2959 /*
2960 * Prevent stats update while adapter is being reset, or if the pci
2961 * connection is down.
2962 */
2963 if (adapter->link_speed == 0)
2964 return;
2965 if (pci_channel_offline(pdev))
2966 return;
2967
2968 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2969 adapter->stats.gprc += rd32(E1000_GPRC);
2970 adapter->stats.gorc += rd32(E1000_GORCL);
2971 rd32(E1000_GORCH); /* clear GORCL */
2972 adapter->stats.bprc += rd32(E1000_BPRC);
2973 adapter->stats.mprc += rd32(E1000_MPRC);
2974 adapter->stats.roc += rd32(E1000_ROC);
2975
2976 adapter->stats.prc64 += rd32(E1000_PRC64);
2977 adapter->stats.prc127 += rd32(E1000_PRC127);
2978 adapter->stats.prc255 += rd32(E1000_PRC255);
2979 adapter->stats.prc511 += rd32(E1000_PRC511);
2980 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2981 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2982 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2983 adapter->stats.sec += rd32(E1000_SEC);
2984
2985 adapter->stats.mpc += rd32(E1000_MPC);
2986 adapter->stats.scc += rd32(E1000_SCC);
2987 adapter->stats.ecol += rd32(E1000_ECOL);
2988 adapter->stats.mcc += rd32(E1000_MCC);
2989 adapter->stats.latecol += rd32(E1000_LATECOL);
2990 adapter->stats.dc += rd32(E1000_DC);
2991 adapter->stats.rlec += rd32(E1000_RLEC);
2992 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2993 adapter->stats.xontxc += rd32(E1000_XONTXC);
2994 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2995 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2996 adapter->stats.fcruc += rd32(E1000_FCRUC);
2997 adapter->stats.gptc += rd32(E1000_GPTC);
2998 adapter->stats.gotc += rd32(E1000_GOTCL);
2999 rd32(E1000_GOTCH); /* clear GOTCL */
3000 adapter->stats.rnbc += rd32(E1000_RNBC);
3001 adapter->stats.ruc += rd32(E1000_RUC);
3002 adapter->stats.rfc += rd32(E1000_RFC);
3003 adapter->stats.rjc += rd32(E1000_RJC);
3004 adapter->stats.tor += rd32(E1000_TORH);
3005 adapter->stats.tot += rd32(E1000_TOTH);
3006 adapter->stats.tpr += rd32(E1000_TPR);
3007
3008 adapter->stats.ptc64 += rd32(E1000_PTC64);
3009 adapter->stats.ptc127 += rd32(E1000_PTC127);
3010 adapter->stats.ptc255 += rd32(E1000_PTC255);
3011 adapter->stats.ptc511 += rd32(E1000_PTC511);
3012 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3013 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3014
3015 adapter->stats.mptc += rd32(E1000_MPTC);
3016 adapter->stats.bptc += rd32(E1000_BPTC);
3017
3018 /* used for adaptive IFS */
3019
3020 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3021 adapter->stats.tpt += hw->mac.tx_packet_delta;
3022 hw->mac.collision_delta = rd32(E1000_COLC);
3023 adapter->stats.colc += hw->mac.collision_delta;
3024
3025 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3026 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3027 adapter->stats.tncrs += rd32(E1000_TNCRS);
3028 adapter->stats.tsctc += rd32(E1000_TSCTC);
3029 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3030
3031 adapter->stats.iac += rd32(E1000_IAC);
3032 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3033 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3034 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3035 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3036 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3037 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3038 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3039 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3040
3041 /* Fill out the OS statistics structure */
3042 adapter->net_stats.multicast = adapter->stats.mprc;
3043 adapter->net_stats.collisions = adapter->stats.colc;
3044
3045 /* Rx Errors */
3046
3047 /* RLEC on some newer hardware can be incorrect so build
3048 * our own version based on RUC and ROC */
3049 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3050 adapter->stats.crcerrs + adapter->stats.algnerrc +
3051 adapter->stats.ruc + adapter->stats.roc +
3052 adapter->stats.cexterr;
3053 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3054 adapter->stats.roc;
3055 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3056 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3057 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3058
3059 /* Tx Errors */
3060 adapter->net_stats.tx_errors = adapter->stats.ecol +
3061 adapter->stats.latecol;
3062 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3063 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3064 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3065
3066 /* Tx Dropped needs to be maintained elsewhere */
3067
3068 /* Phy Stats */
3069 if (hw->phy.media_type == e1000_media_type_copper) {
3070 if ((adapter->link_speed == SPEED_1000) &&
3071 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3072 &phy_tmp))) {
3073 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3074 adapter->phy_stats.idle_errors += phy_tmp;
3075 }
3076 }
3077
3078 /* Management Stats */
3079 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3080 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3081 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3082}
3083
3084
3085static irqreturn_t igb_msix_other(int irq, void *data)
3086{
3087 struct net_device *netdev = data;
3088 struct igb_adapter *adapter = netdev_priv(netdev);
3089 struct e1000_hw *hw = &adapter->hw;
844290e5 3090 u32 icr = rd32(E1000_ICR);
9d5c8243 3091
844290e5
PW		 3092 /* reading ICR causes bit 31 of EICR to be cleared */
3093 if (!(icr & E1000_ICR_LSC))
3094 goto no_link_interrupt;
3095 hw->mac.get_link_status = 1;
3096 /* guard against interrupt when we're going down */
3097 if (!test_bit(__IGB_DOWN, &adapter->state))
3098 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3099
9d5c8243
AK		 3100no_link_interrupt:
3101 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3102 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3103
3104 return IRQ_HANDLED;
3105}
3106
3107static irqreturn_t igb_msix_tx(int irq, void *data)
3108{
3109 struct igb_ring *tx_ring = data;
3110 struct igb_adapter *adapter = tx_ring->adapter;
3111 struct e1000_hw *hw = &adapter->hw;
3112
3113 if (!tx_ring->itr_val)
3114 wr32(E1000_EIMC, tx_ring->eims_value);
3115
3116 tx_ring->total_bytes = 0;
3117 tx_ring->total_packets = 0;
661086df
PWJ		 3118
3119 /* auto mask will automatically reenable the interrupt when we write
3120 * EICS */
3b644cf6 3121 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3122 /* Ring was not completely cleaned, so fire another interrupt */
3123 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3124 else
9d5c8243 3125 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3126
9d5c8243
AK		 3127 return IRQ_HANDLED;
3128}
3129
3130static irqreturn_t igb_msix_rx(int irq, void *data)
3131{
3132 struct igb_ring *rx_ring = data;
3133 struct igb_adapter *adapter = rx_ring->adapter;
3134 struct e1000_hw *hw = &adapter->hw;
3135
844290e5
PW		 3136 /* Write the ITR value calculated at the end of the
3137 * previous interrupt.
3138 */
9d5c8243 3139
844290e5
PW		 3140 if (adapter->set_itr) {
3141 wr32(rx_ring->itr_register,
3142 1000000000 / (rx_ring->itr_val * 256));
3143 adapter->set_itr = 0;
9d5c8243
AK		 3144 }
3145
844290e5
PW		 3146 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3147 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3148
9d5c8243
AK		 3149 return IRQ_HANDLED;
3150}
3151
3152
3153/**
3154 * igb_intr_msi - Interrupt Handler
3155 * @irq: interrupt number
3156 * @data: pointer to a network interface device structure
3157 **/
3158static irqreturn_t igb_intr_msi(int irq, void *data)
3159{
3160 struct net_device *netdev = data;
3161 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3162 struct e1000_hw *hw = &adapter->hw;
3163 /* read ICR disables interrupts using IAM */
3164 u32 icr = rd32(E1000_ICR);
3165
3166 /* Write the ITR value calculated at the end of the
3167 * previous interrupt.
3168 */
3169 if (adapter->set_itr) {
844290e5 3170 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3171 adapter->set_itr = 0;
3172 }
3173
9d5c8243
AK		 3174 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3175 hw->mac.get_link_status = 1;
3176 if (!test_bit(__IGB_DOWN, &adapter->state))
3177 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3178 }
3179
844290e5 3180 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3181
3182 return IRQ_HANDLED;
3183}
3184
3185/**
3186 * igb_intr - Interrupt Handler
3187 * @irq: interrupt number
3188 * @data: pointer to a network interface device structure
3189 **/
3190static irqreturn_t igb_intr(int irq, void *data)
3191{
3192 struct net_device *netdev = data;
3193 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3194 struct e1000_hw *hw = &adapter->hw;
3195 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3196 * need for the IMC write */
3197 u32 icr = rd32(E1000_ICR);
3198 u32 eicr = 0;
3199 if (!icr)
3200 return IRQ_NONE; /* Not our interrupt */
3201
3202 /* Write the ITR value calculated at the end of the
3203 * previous interrupt.
3204 */
3205 if (adapter->set_itr) {
844290e5 3206 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3207 adapter->set_itr = 0;
3208 }
3209
3210 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3211 * not set, then the adapter didn't send an interrupt */
3212 if (!(icr & E1000_ICR_INT_ASSERTED))
3213 return IRQ_NONE;
3214
3215 eicr = rd32(E1000_EICR);
3216
3217 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3218 hw->mac.get_link_status = 1;
3219 /* guard against interrupt when we're going down */
3220 if (!test_bit(__IGB_DOWN, &adapter->state))
3221 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3222 }
3223
844290e5 3224 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3225
3226 return IRQ_HANDLED;
3227}
3228
3229/**
661086df
PWJ		 3230 * igb_poll - NAPI Rx polling callback
3231 * @napi: napi polling structure
3232 * @budget: count of how many packets we should handle
9d5c8243 3233 **/
661086df 3234static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3235{
661086df
PWJ		 3236 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3237 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3238 struct net_device *netdev = adapter->netdev;
661086df 3239 int tx_clean_complete, work_done = 0;
9d5c8243 3240
661086df
PWJ		 3241 /* this poll routine only supports one tx and one rx queue */
3242 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3243 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3244
3245 /* If no Tx and not enough Rx work done, exit the polling mode */
3246 if ((tx_clean_complete && (work_done < budget)) ||
3247 !netif_running(netdev)) {
9d5c8243
AK		 3248 if (adapter->itr_setting & 3)
3249 igb_set_itr(adapter, E1000_ITR, false);
3250 netif_rx_complete(netdev, napi);
3251 if (!test_bit(__IGB_DOWN, &adapter->state))
3252 igb_irq_enable(adapter);
3253 return 0;
3254 }
3255
3256 return 1;
3257}
3258
3259static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3260{
3261 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3262 struct igb_adapter *adapter = rx_ring->adapter;
3263 struct e1000_hw *hw = &adapter->hw;
3264 struct net_device *netdev = adapter->netdev;
3265 int work_done = 0;
3266
3267 /* Keep link state information with original netdev */
3268 if (!netif_carrier_ok(netdev))
3269 goto quit_polling;
3270
3b644cf6 3271 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3272
3273
3274 /* If not enough Rx work done, exit the polling mode */
3275 if ((work_done == 0) || !netif_running(netdev)) {
3276quit_polling:
3277 netif_rx_complete(netdev, napi);
3278
3279 wr32(E1000_EIMS, rx_ring->eims_value);
3280 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3281 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3282 int mean_size = rx_ring->total_bytes /
3283 rx_ring->total_packets;
3284 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3285 igb_raise_rx_eitr(adapter, rx_ring);
3286 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3287 igb_lower_rx_eitr(adapter, rx_ring);
3288 }
844290e5
PW		 3289
3290 if (!test_bit(__IGB_DOWN, &adapter->state))
3291 wr32(E1000_EIMS, rx_ring->eims_value);
3292
9d5c8243
AK		 3293 return 0;
3294 }
3295
3296 return 1;
3297}
6d8126f9
AV		 3298
3299static inline u32 get_head(struct igb_ring *tx_ring)
3300{
3301 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3302 return le32_to_cpu(*(volatile __le32 *)end);
3303}
3304
9d5c8243
AK		 3305/**
3306 * igb_clean_tx_irq - Reclaim resources after transmit completes
3307 * @adapter: board private structure
3308 * returns true if ring is completely cleaned
3309 **/
3b644cf6 3310static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3311{
3b644cf6 3312 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3313 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3314 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3315 struct e1000_tx_desc *tx_desc;
3316 struct igb_buffer *buffer_info;
3317 struct sk_buff *skb;
3318 unsigned int i;
3319 u32 head, oldhead;
3320 unsigned int count = 0;
3321 bool cleaned = false;
3322 bool retval = true;
3323 unsigned int total_bytes = 0, total_packets = 0;
3324
3325 rmb();
6d8126f9 3326 head = get_head(tx_ring);
9d5c8243
AK		 3327 i = tx_ring->next_to_clean;
3328 while (1) {
3329 while (i != head) {
3330 cleaned = true;
3331 tx_desc = E1000_TX_DESC(*tx_ring, i);
3332 buffer_info = &tx_ring->buffer_info[i];
3333 skb = buffer_info->skb;
3334
3335 if (skb) {
3336 unsigned int segs, bytecount;
3337 /* gso_segs is currently only valid for tcp */
3338 segs = skb_shinfo(skb)->gso_segs ?: 1;
3339 /* multiply data chunks by size of headers */
3340 bytecount = ((segs - 1) * skb_headlen(skb)) +
3341 skb->len;
3342 total_packets += segs;
3343 total_bytes += bytecount;
3344 }
3345
3346 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3347 tx_desc->upper.data = 0;
3348
3349 i++;
3350 if (i == tx_ring->count)
3351 i = 0;
3352
3353 count++;
3354 if (count == IGB_MAX_TX_CLEAN) {
3355 retval = false;
3356 goto done_cleaning;
3357 }
3358 }
3359 oldhead = head;
3360 rmb();
6d8126f9 3361 head = get_head(tx_ring);
9d5c8243
AK		 3362 if (head == oldhead)
3363 goto done_cleaning;
3364 } /* while (1) */
3365
3366done_cleaning:
3367 tx_ring->next_to_clean = i;
3368
3369 if (unlikely(cleaned &&
3370 netif_carrier_ok(netdev) &&
3371 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3372 /* Make sure that anybody stopping the queue after this
3373 * sees the new next_to_clean.
3374 */
3375 smp_mb();
661086df
PWJ		 3376#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3377 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3378 !(test_bit(__IGB_DOWN, &adapter->state))) {
3379 netif_wake_subqueue(netdev, tx_ring->queue_index);
3380 ++adapter->restart_queue;
3381 }
3382#else
9d5c8243
AK		 3383 if (netif_queue_stopped(netdev) &&
3384 !(test_bit(__IGB_DOWN, &adapter->state))) {
3385 netif_wake_queue(netdev);
3386 ++adapter->restart_queue;
3387 }
661086df 3388#endif
9d5c8243
AK		 3389 }
3390
3391 if (tx_ring->detect_tx_hung) {
3392 /* Detect a transmit hang in hardware, this serializes the
3393 * check with the clearing of time_stamp and movement of i */
3394 tx_ring->detect_tx_hung = false;
3395 if (tx_ring->buffer_info[i].time_stamp &&
3396 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3397 (adapter->tx_timeout_factor * HZ))
3398 && !(rd32(E1000_STATUS) &
3399 E1000_STATUS_TXOFF)) {
3400
3401 tx_desc = E1000_TX_DESC(*tx_ring, i);
3402 /* detected Tx unit hang */
3403 dev_err(&adapter->pdev->dev,
3404 "Detected Tx Unit Hang\n"
3405 " Tx Queue <%lu>\n"
3406 " TDH <%x>\n"
3407 " TDT <%x>\n"
3408 " next_to_use <%x>\n"
3409 " next_to_clean <%x>\n"
3410 " head (WB) <%x>\n"
3411 "buffer_info[next_to_clean]\n"
3412 " time_stamp <%lx>\n"
3413 " jiffies <%lx>\n"
3414 " desc.status <%x>\n",
3415 (unsigned long)((tx_ring - adapter->tx_ring) /
3416 sizeof(struct igb_ring)),
3417 readl(adapter->hw.hw_addr + tx_ring->head),
3418 readl(adapter->hw.hw_addr + tx_ring->tail),
3419 tx_ring->next_to_use,
3420 tx_ring->next_to_clean,
3421 head,
3422 tx_ring->buffer_info[i].time_stamp,
3423 jiffies,
3424 tx_desc->upper.fields.status);
661086df
PWJ		 3425#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3426 netif_stop_subqueue(netdev, tx_ring->queue_index);
3427#else
9d5c8243 3428 netif_stop_queue(netdev);
661086df 3429#endif
9d5c8243
AK		 3430 }
3431 }
3432 tx_ring->total_bytes += total_bytes;
3433 tx_ring->total_packets += total_packets;
e21ed353
AD		 3434 tx_ring->tx_stats.bytes += total_bytes;
3435 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3436 adapter->net_stats.tx_bytes += total_bytes;
3437 adapter->net_stats.tx_packets += total_packets;
3438 return retval;
3439}
3440
3441
3442/**
3443 * igb_receive_skb - helper function to handle rx indications
3444 * @adapter: board private structure
3445 * @status: descriptor status field as written by hardware
3446 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3447 * @skb: pointer to sk_buff to be indicated to stack
3448 **/
6d8126f9 3449static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
9d5c8243
AK		 3450 struct sk_buff *skb)
3451{
3452 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3453 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
38b22195 3454 le16_to_cpu(vlan));
9d5c8243
AK		 3455 else
3456 netif_receive_skb(skb);
3457}
3458
3459
3460static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3461 u32 status_err, struct sk_buff *skb)
3462{
3463 skb->ip_summed = CHECKSUM_NONE;
3464
3465 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3466 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3467 return;
3468 /* TCP/UDP checksum error bit is set */
3469 if (status_err &
3470 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3471 /* let the stack verify checksum errors */
3472 adapter->hw_csum_err++;
3473 return;
3474 }
3475 /* It must be a TCP or UDP packet with a valid checksum */
3476 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3477 skb->ip_summed = CHECKSUM_UNNECESSARY;
3478
3479 adapter->hw_csum_good++;
3480}
3481
3b644cf6
MW		 3482static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3483 int *work_done, int budget)
9d5c8243 3484{
3b644cf6 3485 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3486 struct net_device *netdev = adapter->netdev;
3487 struct pci_dev *pdev = adapter->pdev;
3488 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3489 struct igb_buffer *buffer_info , *next_buffer;
3490 struct sk_buff *skb;
3491 unsigned int i, j;
3492 u32 length, hlen, staterr;
3493 bool cleaned = false;
3494 int cleaned_count = 0;
3495 unsigned int total_bytes = 0, total_packets = 0;
3496
3497 i = rx_ring->next_to_clean;
3498 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3499 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3500
3501 while (staterr & E1000_RXD_STAT_DD) {
3502 if (*work_done >= budget)
3503 break;
3504 (*work_done)++;
3505 buffer_info = &rx_ring->buffer_info[i];
3506
3507 /* HW will not DMA in data larger than the given buffer, even
3508 * if it parses the (NFS, of course) header to be larger. In
3509 * that case, it fills the header buffer and spills the rest
3510 * into the page.
3511 */
7deb07b1
AV		 3512 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3513 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3514 if (hlen > adapter->rx_ps_hdr_size)
3515 hlen = adapter->rx_ps_hdr_size;
3516
3517 length = le16_to_cpu(rx_desc->wb.upper.length);
3518 cleaned = true;
3519 cleaned_count++;
3520
3521 if (rx_ring->pending_skb != NULL) {
3522 skb = rx_ring->pending_skb;
3523 rx_ring->pending_skb = NULL;
3524 j = rx_ring->pending_skb_page;
3525 } else {
3526 skb = buffer_info->skb;
3527 prefetch(skb->data - NET_IP_ALIGN);
3528 buffer_info->skb = NULL;
3529 if (hlen) {
3530 pci_unmap_single(pdev, buffer_info->dma,
3531 adapter->rx_ps_hdr_size +
3532 NET_IP_ALIGN,
3533 PCI_DMA_FROMDEVICE);
3534 skb_put(skb, hlen);
3535 } else {
3536 pci_unmap_single(pdev, buffer_info->dma,
3537 adapter->rx_buffer_len +
3538 NET_IP_ALIGN,
3539 PCI_DMA_FROMDEVICE);
3540 skb_put(skb, length);
3541 goto send_up;
3542 }
3543 j = 0;
3544 }
3545
3546 while (length) {
3547 pci_unmap_page(pdev, buffer_info->page_dma,
3548 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3549 buffer_info->page_dma = 0;
3550 skb_fill_page_desc(skb, j, buffer_info->page,
3551 0, length);
3552 buffer_info->page = NULL;
3553
3554 skb->len += length;
3555 skb->data_len += length;
3556 skb->truesize += length;
3557 rx_desc->wb.upper.status_error = 0;
3558 if (staterr & E1000_RXD_STAT_EOP)
3559 break;
3560
3561 j++;
3562 cleaned_count++;
3563 i++;
3564 if (i == rx_ring->count)
3565 i = 0;
3566
3567 buffer_info = &rx_ring->buffer_info[i];
3568 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3569 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3570 length = le16_to_cpu(rx_desc->wb.upper.length);
3571 if (!(staterr & E1000_RXD_STAT_DD)) {
3572 rx_ring->pending_skb = skb;
3573 rx_ring->pending_skb_page = j;
3574 goto out;
3575 }
3576 }
3577send_up:
3578 pskb_trim(skb, skb->len - 4);
3579 i++;
3580 if (i == rx_ring->count)
3581 i = 0;
3582 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3583 prefetch(next_rxd);
3584 next_buffer = &rx_ring->buffer_info[i];
3585
3586 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3587 dev_kfree_skb_irq(skb);
3588 goto next_desc;
3589 }
3590 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3591
3592 total_bytes += skb->len;
3593 total_packets++;
3594
3595 igb_rx_checksum_adv(adapter, staterr, skb);
3596
3597 skb->protocol = eth_type_trans(skb, netdev);
3598
3599 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3600
3601 netdev->last_rx = jiffies;
3602
3603next_desc:
3604 rx_desc->wb.upper.status_error = 0;
3605
3606 /* return some buffers to hardware, one at a time is too slow */
3607 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3608 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3609 cleaned_count = 0;
3610 }
3611
3612 /* use prefetched values */
3613 rx_desc = next_rxd;
3614 buffer_info = next_buffer;
3615
3616 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3617 }
3618out:
3619 rx_ring->next_to_clean = i;
3620 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3621
3622 if (cleaned_count)
3b644cf6 3623 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3624
3625 rx_ring->total_packets += total_packets;
3626 rx_ring->total_bytes += total_bytes;
3627 rx_ring->rx_stats.packets += total_packets;
3628 rx_ring->rx_stats.bytes += total_bytes;
3629 adapter->net_stats.rx_bytes += total_bytes;
3630 adapter->net_stats.rx_packets += total_packets;
3631 return cleaned;
3632}
3633
3634
3635/**
3636 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3637 * @adapter: address of board private structure
3638 **/
3b644cf6 3639static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3640 int cleaned_count)
3641{
3b644cf6 3642 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3643 struct net_device *netdev = adapter->netdev;
3644 struct pci_dev *pdev = adapter->pdev;
3645 union e1000_adv_rx_desc *rx_desc;
3646 struct igb_buffer *buffer_info;
3647 struct sk_buff *skb;
3648 unsigned int i;
3649
3650 i = rx_ring->next_to_use;
3651 buffer_info = &rx_ring->buffer_info[i];
3652
3653 while (cleaned_count--) {
3654 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3655
3656 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3657 buffer_info->page = alloc_page(GFP_ATOMIC);
3658 if (!buffer_info->page) {
3659 adapter->alloc_rx_buff_failed++;
3660 goto no_buffers;
3661 }
3662 buffer_info->page_dma =
3663 pci_map_page(pdev,
3664 buffer_info->page,
3665 0, PAGE_SIZE,
3666 PCI_DMA_FROMDEVICE);
3667 }
3668
3669 if (!buffer_info->skb) {
3670 int bufsz;
3671
3672 if (adapter->rx_ps_hdr_size)
3673 bufsz = adapter->rx_ps_hdr_size;
3674 else
3675 bufsz = adapter->rx_buffer_len;
3676 bufsz += NET_IP_ALIGN;
3677 skb = netdev_alloc_skb(netdev, bufsz);
3678
3679 if (!skb) {
3680 adapter->alloc_rx_buff_failed++;
3681 goto no_buffers;
3682 }
3683
3684 /* Make buffer alignment 2 beyond a 16 byte boundary
3685 * this will result in a 16 byte aligned IP header after
3686 * the 14 byte MAC header is removed
3687 */
3688 skb_reserve(skb, NET_IP_ALIGN);
3689
3690 buffer_info->skb = skb;
3691 buffer_info->dma = pci_map_single(pdev, skb->data,
3692 bufsz,
3693 PCI_DMA_FROMDEVICE);
3694
3695 }
3696 /* Refresh the desc even if buffer_addrs didn't change because
3697 * each write-back erases this info. */
3698 if (adapter->rx_ps_hdr_size) {
3699 rx_desc->read.pkt_addr =
3700 cpu_to_le64(buffer_info->page_dma);
3701 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3702 } else {
3703 rx_desc->read.pkt_addr =
3704 cpu_to_le64(buffer_info->dma);
3705 rx_desc->read.hdr_addr = 0;
3706 }
3707
3708 i++;
3709 if (i == rx_ring->count)
3710 i = 0;
3711 buffer_info = &rx_ring->buffer_info[i];
3712 }
3713
3714no_buffers:
3715 if (rx_ring->next_to_use != i) {
3716 rx_ring->next_to_use = i;
3717 if (i == 0)
3718 i = (rx_ring->count - 1);
3719 else
3720 i--;
3721
3722 /* Force memory writes to complete before letting h/w
3723 * know there are new descriptors to fetch. (Only
3724 * applicable for weak-ordered memory model archs,
3725 * such as IA-64). */
3726 wmb();
3727 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3728 }
3729}
3730
3731/**
3732 * igb_mii_ioctl -
3733 * @netdev:
3734 * @ifreq:
3735 * @cmd:
3736 **/
3737static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3738{
3739 struct igb_adapter *adapter = netdev_priv(netdev);
3740 struct mii_ioctl_data *data = if_mii(ifr);
3741
3742 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3743 return -EOPNOTSUPP;
3744
3745 switch (cmd) {
3746 case SIOCGMIIPHY:
3747 data->phy_id = adapter->hw.phy.addr;
3748 break;
3749 case SIOCGMIIREG:
3750 if (!capable(CAP_NET_ADMIN))
3751 return -EPERM;
3752 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3753 data->reg_num
3754 & 0x1F, &data->val_out))
3755 return -EIO;
3756 break;
3757 case SIOCSMIIREG:
3758 default:
3759 return -EOPNOTSUPP;
3760 }
3761 return 0;
3762}
3763
3764/**
3765 * igb_ioctl -
3766 * @netdev:
3767 * @ifreq:
3768 * @cmd:
3769 **/
3770static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3771{
3772 switch (cmd) {
3773 case SIOCGMIIPHY:
3774 case SIOCGMIIREG:
3775 case SIOCSMIIREG:
3776 return igb_mii_ioctl(netdev, ifr, cmd);
3777 default:
3778 return -EOPNOTSUPP;
3779 }
3780}
3781
3782static void igb_vlan_rx_register(struct net_device *netdev,
3783 struct vlan_group *grp)
3784{
3785 struct igb_adapter *adapter = netdev_priv(netdev);
3786 struct e1000_hw *hw = &adapter->hw;
3787 u32 ctrl, rctl;
3788
3789 igb_irq_disable(adapter);
3790 adapter->vlgrp = grp;
3791
3792 if (grp) {
3793 /* enable VLAN tag insert/strip */
3794 ctrl = rd32(E1000_CTRL);
3795 ctrl |= E1000_CTRL_VME;
3796 wr32(E1000_CTRL, ctrl);
3797
3798 /* enable VLAN receive filtering */
3799 rctl = rd32(E1000_RCTL);
3800 rctl |= E1000_RCTL_VFE;
3801 rctl &= ~E1000_RCTL_CFIEN;
3802 wr32(E1000_RCTL, rctl);
3803 igb_update_mng_vlan(adapter);
3804 wr32(E1000_RLPML,
3805 adapter->max_frame_size + VLAN_TAG_SIZE);
3806 } else {
3807 /* disable VLAN tag insert/strip */
3808 ctrl = rd32(E1000_CTRL);
3809 ctrl &= ~E1000_CTRL_VME;
3810 wr32(E1000_CTRL, ctrl);
3811
3812 /* disable VLAN filtering */
3813 rctl = rd32(E1000_RCTL);
3814 rctl &= ~E1000_RCTL_VFE;
3815 wr32(E1000_RCTL, rctl);
3816 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3817 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3818 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3819 }
3820 wr32(E1000_RLPML,
3821 adapter->max_frame_size);
3822 }
3823
3824 if (!test_bit(__IGB_DOWN, &adapter->state))
3825 igb_irq_enable(adapter);
3826}
3827
3828static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3829{
3830 struct igb_adapter *adapter = netdev_priv(netdev);
3831 struct e1000_hw *hw = &adapter->hw;
3832 u32 vfta, index;
3833
3834 if ((adapter->hw.mng_cookie.status &
3835 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3836 (vid == adapter->mng_vlan_id))
3837 return;
3838 /* add VID to filter table */
3839 index = (vid >> 5) & 0x7F;
3840 vfta = array_rd32(E1000_VFTA, index);
3841 vfta |= (1 << (vid & 0x1F));
3842 igb_write_vfta(&adapter->hw, index, vfta);
3843}
3844
3845static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3846{
3847 struct igb_adapter *adapter = netdev_priv(netdev);
3848 struct e1000_hw *hw = &adapter->hw;
3849 u32 vfta, index;
3850
3851 igb_irq_disable(adapter);
3852 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3853
3854 if (!test_bit(__IGB_DOWN, &adapter->state))
3855 igb_irq_enable(adapter);
3856
3857 if ((adapter->hw.mng_cookie.status &
3858 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3859 (vid == adapter->mng_vlan_id)) {
3860 /* release control to f/w */
3861 igb_release_hw_control(adapter);
3862 return;
3863 }
3864
3865 /* remove VID from filter table */
3866 index = (vid >> 5) & 0x7F;
3867 vfta = array_rd32(E1000_VFTA, index);
3868 vfta &= ~(1 << (vid & 0x1F));
3869 igb_write_vfta(&adapter->hw, index, vfta);
3870}
3871
3872static void igb_restore_vlan(struct igb_adapter *adapter)
3873{
3874 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3875
3876 if (adapter->vlgrp) {
3877 u16 vid;
3878 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3879 if (!vlan_group_get_device(adapter->vlgrp, vid))
3880 continue;
3881 igb_vlan_rx_add_vid(adapter->netdev, vid);
3882 }
3883 }
3884}
3885
3886int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3887{
3888 struct e1000_mac_info *mac = &adapter->hw.mac;
3889
3890 mac->autoneg = 0;
3891
3892 /* Fiber NICs only allow 1000 gbps Full duplex */
3893 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3894 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3895 dev_err(&adapter->pdev->dev,
3896 "Unsupported Speed/Duplex configuration\n");
3897 return -EINVAL;
3898 }
3899
3900 switch (spddplx) {
3901 case SPEED_10 + DUPLEX_HALF:
3902 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3903 break;
3904 case SPEED_10 + DUPLEX_FULL:
3905 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3906 break;
3907 case SPEED_100 + DUPLEX_HALF:
3908 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3909 break;
3910 case SPEED_100 + DUPLEX_FULL:
3911 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3912 break;
3913 case SPEED_1000 + DUPLEX_FULL:
3914 mac->autoneg = 1;
3915 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3916 break;
3917 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3918 default:
3919 dev_err(&adapter->pdev->dev,
3920 "Unsupported Speed/Duplex configuration\n");
3921 return -EINVAL;
3922 }
3923 return 0;
3924}
3925
3926
3927static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3928{
3929 struct net_device *netdev = pci_get_drvdata(pdev);
3930 struct igb_adapter *adapter = netdev_priv(netdev);
3931 struct e1000_hw *hw = &adapter->hw;
3932 u32 ctrl, ctrl_ext, rctl, status;
3933 u32 wufc = adapter->wol;
3934#ifdef CONFIG_PM
3935 int retval = 0;
3936#endif
3937
3938 netif_device_detach(netdev);
3939
3940 if (netif_running(netdev)) {
3941 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3942 igb_down(adapter);
3943 igb_free_irq(adapter);
3944 }
3945
3946#ifdef CONFIG_PM
3947 retval = pci_save_state(pdev);
3948 if (retval)
3949 return retval;
3950#endif
3951
3952 status = rd32(E1000_STATUS);
3953 if (status & E1000_STATUS_LU)
3954 wufc &= ~E1000_WUFC_LNKC;
3955
3956 if (wufc) {
3957 igb_setup_rctl(adapter);
3958 igb_set_multi(netdev);
3959
3960 /* turn on all-multi mode if wake on multicast is enabled */
3961 if (wufc & E1000_WUFC_MC) {
3962 rctl = rd32(E1000_RCTL);
3963 rctl |= E1000_RCTL_MPE;
3964 wr32(E1000_RCTL, rctl);
3965 }
3966
3967 ctrl = rd32(E1000_CTRL);
3968 /* advertise wake from D3Cold */
3969 #define E1000_CTRL_ADVD3WUC 0x00100000
3970 /* phy power management enable */
3971 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3972 ctrl |= E1000_CTRL_ADVD3WUC;
3973 wr32(E1000_CTRL, ctrl);
3974
3975 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3976 adapter->hw.phy.media_type ==
3977 e1000_media_type_internal_serdes) {
3978 /* keep the laser running in D3 */
3979 ctrl_ext = rd32(E1000_CTRL_EXT);
3980 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3981 wr32(E1000_CTRL_EXT, ctrl_ext);
3982 }
3983
3984 /* Allow time for pending master requests to run */
3985 igb_disable_pcie_master(&adapter->hw);
3986
3987 wr32(E1000_WUC, E1000_WUC_PME_EN);
3988 wr32(E1000_WUFC, wufc);
3989 pci_enable_wake(pdev, PCI_D3hot, 1);
3990 pci_enable_wake(pdev, PCI_D3cold, 1);
3991 } else {
3992 wr32(E1000_WUC, 0);
3993 wr32(E1000_WUFC, 0);
3994 pci_enable_wake(pdev, PCI_D3hot, 0);
3995 pci_enable_wake(pdev, PCI_D3cold, 0);
3996 }
3997
9d5c8243
AK		 3998 /* make sure adapter isn't asleep if manageability is enabled */
3999 if (adapter->en_mng_pt) {
4000 pci_enable_wake(pdev, PCI_D3hot, 1);
4001 pci_enable_wake(pdev, PCI_D3cold, 1);
4002 }
4003
4004 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4005 * would have already happened in close and is redundant. */
4006 igb_release_hw_control(adapter);
4007
4008 pci_disable_device(pdev);
4009
4010 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4011
4012 return 0;
4013}
4014
4015#ifdef CONFIG_PM
4016static int igb_resume(struct pci_dev *pdev)
4017{
4018 struct net_device *netdev = pci_get_drvdata(pdev);
4019 struct igb_adapter *adapter = netdev_priv(netdev);
4020 struct e1000_hw *hw = &adapter->hw;
4021 u32 err;
4022
4023 pci_set_power_state(pdev, PCI_D0);
4024 pci_restore_state(pdev);
42bfd33a
TI		 4025
4026 if (adapter->need_ioport)
4027 err = pci_enable_device(pdev);
4028 else
4029 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4030 if (err) {
4031 dev_err(&pdev->dev,
4032 "igb: Cannot enable PCI device from suspend\n");
4033 return err;
4034 }
4035 pci_set_master(pdev);
4036
4037 pci_enable_wake(pdev, PCI_D3hot, 0);
4038 pci_enable_wake(pdev, PCI_D3cold, 0);
4039
4040 if (netif_running(netdev)) {
4041 err = igb_request_irq(adapter);
4042 if (err)
4043 return err;
4044 }
4045
4046 /* e1000_power_up_phy(adapter); */
4047
4048 igb_reset(adapter);
4049 wr32(E1000_WUS, ~0);
4050
4051 igb_init_manageability(adapter);
4052
4053 if (netif_running(netdev))
4054 igb_up(adapter);
4055
4056 netif_device_attach(netdev);
4057
4058 /* let the f/w know that the h/w is now under the control of the
4059 * driver. */
4060 igb_get_hw_control(adapter);
4061
4062 return 0;
4063}
4064#endif
4065
4066static void igb_shutdown(struct pci_dev *pdev)
4067{
4068 igb_suspend(pdev, PMSG_SUSPEND);
4069}
4070
4071#ifdef CONFIG_NET_POLL_CONTROLLER
4072/*
4073 * Polling 'interrupt' - used by things like netconsole to send skbs
4074 * without having to re-enable interrupts. It's not called while
4075 * the interrupt routine is executing.
4076 */
4077static void igb_netpoll(struct net_device *netdev)
4078{
4079 struct igb_adapter *adapter = netdev_priv(netdev);
4080 int i;
4081 int work_done = 0;
4082
4083 igb_irq_disable(adapter);
4084 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4085 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4086
4087 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4088 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4089 &work_done,
4090 adapter->rx_ring[i].napi.weight);
4091
4092 igb_irq_enable(adapter);
4093}
4094#endif /* CONFIG_NET_POLL_CONTROLLER */
4095
4096/**
4097 * igb_io_error_detected - called when PCI error is detected
4098 * @pdev: Pointer to PCI device
4099 * @state: The current pci connection state
4100 *
4101 * This function is called after a PCI bus error affecting
4102 * this device has been detected.
4103 */
4104static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4105 pci_channel_state_t state)
4106{
4107 struct net_device *netdev = pci_get_drvdata(pdev);
4108 struct igb_adapter *adapter = netdev_priv(netdev);
4109
4110 netif_device_detach(netdev);
4111
4112 if (netif_running(netdev))
4113 igb_down(adapter);
4114 pci_disable_device(pdev);
4115
4116 /* Request a slot slot reset. */
4117 return PCI_ERS_RESULT_NEED_RESET;
4118}
4119
4120/**
4121 * igb_io_slot_reset - called after the pci bus has been reset.
4122 * @pdev: Pointer to PCI device
4123 *
4124 * Restart the card from scratch, as if from a cold-boot. Implementation
4125 * resembles the first-half of the igb_resume routine.
4126 */
4127static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4128{
4129 struct net_device *netdev = pci_get_drvdata(pdev);
4130 struct igb_adapter *adapter = netdev_priv(netdev);
4131 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4132 int err;
9d5c8243 4133
42bfd33a
TI		 4134 if (adapter->need_ioport)
4135 err = pci_enable_device(pdev);
4136 else
4137 err = pci_enable_device_mem(pdev);
4138 if (err) {
9d5c8243
AK		 4139 dev_err(&pdev->dev,
4140 "Cannot re-enable PCI device after reset.\n");
4141 return PCI_ERS_RESULT_DISCONNECT;
4142 }
4143 pci_set_master(pdev);
c682fc23 4144 pci_restore_state(pdev);
9d5c8243
AK		 4145
4146 pci_enable_wake(pdev, PCI_D3hot, 0);
4147 pci_enable_wake(pdev, PCI_D3cold, 0);
4148
4149 igb_reset(adapter);
4150 wr32(E1000_WUS, ~0);
4151
4152 return PCI_ERS_RESULT_RECOVERED;
4153}
4154
4155/**
4156 * igb_io_resume - called when traffic can start flowing again.
4157 * @pdev: Pointer to PCI device
4158 *
4159 * This callback is called when the error recovery driver tells us that
4160 * its OK to resume normal operation. Implementation resembles the
4161 * second-half of the igb_resume routine.
4162 */
4163static void igb_io_resume(struct pci_dev *pdev)
4164{
4165 struct net_device *netdev = pci_get_drvdata(pdev);
4166 struct igb_adapter *adapter = netdev_priv(netdev);
4167
4168 igb_init_manageability(adapter);
4169
4170 if (netif_running(netdev)) {
4171 if (igb_up(adapter)) {
4172 dev_err(&pdev->dev, "igb_up failed after reset\n");
4173 return;
4174 }
4175 }
4176
4177 netif_device_attach(netdev);
4178
4179 /* let the f/w know that the h/w is now under the control of the
4180 * driver. */
4181 igb_get_hw_control(adapter);
4182
4183}
4184
4185/* igb_main.c */
Linux kernel - Deliverables
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