projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: ethtool -d reads EICR which is incorrect as it is read on clear
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
fe4506b6
JC		 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
9d5c8243
AK		 47#include "igb.h"
48
0024fd00 49#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 50char igb_driver_name[] = "igb";
51char igb_driver_version[] = DRV_VERSION;
52static const char igb_driver_string[] =
53 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 55
9d5c8243
AK		 56static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58};
59
60static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 79static void igb_free_tx_resources(struct igb_ring *);
80static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
fe4506b6
JC		 110#ifdef CONFIG_DCA
111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
114#endif /* CONFIG_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
9d5c8243
AK		 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
123static void igb_tx_timeout(struct net_device *);
124static void igb_reset_task(struct work_struct *);
125static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
126static void igb_vlan_rx_add_vid(struct net_device *, u16);
127static void igb_vlan_rx_kill_vid(struct net_device *, u16);
128static void igb_restore_vlan(struct igb_adapter *);
129
130static int igb_suspend(struct pci_dev *, pm_message_t);
131#ifdef CONFIG_PM
132static int igb_resume(struct pci_dev *);
133#endif
134static void igb_shutdown(struct pci_dev *);
fe4506b6
JC		 135#ifdef CONFIG_DCA
136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
9d5c8243
AK		 143
144#ifdef CONFIG_NET_POLL_CONTROLLER
145/* for netdump / net console */
146static void igb_netpoll(struct net_device *);
147#endif
148
149static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
150 pci_channel_state_t);
151static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
152static void igb_io_resume(struct pci_dev *);
153
154static struct pci_error_handlers igb_err_handler = {
155 .error_detected = igb_io_error_detected,
156 .slot_reset = igb_io_slot_reset,
157 .resume = igb_io_resume,
158};
159
160
161static struct pci_driver igb_driver = {
162 .name = igb_driver_name,
163 .id_table = igb_pci_tbl,
164 .probe = igb_probe,
165 .remove = __devexit_p(igb_remove),
166#ifdef CONFIG_PM
167 /* Power Managment Hooks */
168 .suspend = igb_suspend,
169 .resume = igb_resume,
170#endif
171 .shutdown = igb_shutdown,
172 .err_handler = &igb_err_handler
173};
174
7dfc16fa
AD		 175static int global_quad_port_a; /* global quad port a indication */
176
9d5c8243
AK		 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_VERSION);
181
182#ifdef DEBUG
183/**
184 * igb_get_hw_dev_name - return device name string
185 * used by hardware layer to print debugging information
186 **/
187char *igb_get_hw_dev_name(struct e1000_hw *hw)
188{
189 struct igb_adapter *adapter = hw->back;
190 return adapter->netdev->name;
191}
192#endif
193
194/**
195 * igb_init_module - Driver Registration Routine
196 *
197 * igb_init_module is the first routine called when the driver is
198 * loaded. All it does is register with the PCI subsystem.
199 **/
200static int __init igb_init_module(void)
201{
202 int ret;
203 printk(KERN_INFO "%s - version %s\n",
204 igb_driver_string, igb_driver_version);
205
206 printk(KERN_INFO "%s\n", igb_copyright);
207
7dfc16fa
AD		 208 global_quad_port_a = 0;
209
9d5c8243 210 ret = pci_register_driver(&igb_driver);
fe4506b6
JC		 211#ifdef CONFIG_DCA
212 dca_register_notify(&dca_notifier);
213#endif
9d5c8243
AK		 214 return ret;
215}
216
217module_init(igb_init_module);
218
219/**
220 * igb_exit_module - Driver Exit Cleanup Routine
221 *
222 * igb_exit_module is called just before the driver is removed
223 * from memory.
224 **/
225static void __exit igb_exit_module(void)
226{
fe4506b6
JC		 227#ifdef CONFIG_DCA
228 dca_unregister_notify(&dca_notifier);
229#endif
9d5c8243
AK		 230 pci_unregister_driver(&igb_driver);
231}
232
233module_exit(igb_exit_module);
234
235/**
236 * igb_alloc_queues - Allocate memory for all rings
237 * @adapter: board private structure to initialize
238 *
239 * We allocate one ring per queue at run-time since we don't know the
240 * number of queues at compile-time.
241 **/
242static int igb_alloc_queues(struct igb_adapter *adapter)
243{
244 int i;
245
246 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
247 sizeof(struct igb_ring), GFP_KERNEL);
248 if (!adapter->tx_ring)
249 return -ENOMEM;
250
251 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
252 sizeof(struct igb_ring), GFP_KERNEL);
253 if (!adapter->rx_ring) {
254 kfree(adapter->tx_ring);
255 return -ENOMEM;
256 }
257
6eb5a7f1
AD		 258 adapter->rx_ring->buddy = adapter->tx_ring;
259
661086df
PWJ		 260 for (i = 0; i < adapter->num_tx_queues; i++) {
261 struct igb_ring *ring = &(adapter->tx_ring[i]);
262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
9d5c8243
AK		 265 for (i = 0; i < adapter->num_rx_queues; i++) {
266 struct igb_ring *ring = &(adapter->rx_ring[i]);
267 ring->adapter = adapter;
844290e5 268 ring->queue_index = i;
9d5c8243
AK		 269 ring->itr_register = E1000_ITR;
270
844290e5 271 /* set a default napi handler for each rx_ring */
661086df 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 273 }
274 return 0;
275}
276
a88f10ec
AD		 277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
9d5c8243
AK		 288#define IGB_N0_QUEUE -1
289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
290 int tx_queue, int msix_vector)
291{
292 u32 msixbm = 0;
293 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
9d5c8243
AK		 298 /* The 82575 assigns vectors using a bitmask, which matches the
299 bitmask for the EICR/EIMS/EIMC registers. To assign one
300 or more queues to a vector, we write the appropriate bits
301 into the MSIXBM register for that vector. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
304 adapter->rx_ring[rx_queue].eims_value = msixbm;
305 }
306 if (tx_queue > IGB_N0_QUEUE) {
307 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
308 adapter->tx_ring[tx_queue].eims_value =
309 E1000_EICR_TX_QUEUE0 << tx_queue;
310 }
311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 312 break;
313 case e1000_82576:
106ef2fe 314 /* The 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
9d5c8243
AK		 353}
354
355/**
356 * igb_configure_msix - Configure MSI-X hardware
357 *
358 * igb_configure_msix sets up the hardware to properly
359 * generate MSI-X interrupts.
360 **/
361static void igb_configure_msix(struct igb_adapter *adapter)
362{
363 u32 tmp;
364 int i, vector = 0;
365 struct e1000_hw *hw = &adapter->hw;
366
367 adapter->eims_enable_mask = 0;
2d064c06
AD		 368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
9d5c8243
AK		 374
375 for (i = 0; i < adapter->num_tx_queues; i++) {
376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
378 adapter->eims_enable_mask |= tx_ring->eims_value;
379 if (tx_ring->itr_val)
6eb5a7f1 380 writel(tx_ring->itr_val,
9d5c8243
AK		 381 hw->hw_addr + tx_ring->itr_register);
382 else
383 writel(1, hw->hw_addr + tx_ring->itr_register);
384 }
385
386 for (i = 0; i < adapter->num_rx_queues; i++) {
387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 388 rx_ring->buddy = NULL;
9d5c8243
AK		 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
390 adapter->eims_enable_mask |= rx_ring->eims_value;
391 if (rx_ring->itr_val)
6eb5a7f1 392 writel(rx_ring->itr_val,
9d5c8243
AK		 393 hw->hw_addr + rx_ring->itr_register);
394 else
395 writel(1, hw->hw_addr + rx_ring->itr_register);
396 }
397
398
399 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 400 switch (hw->mac.type) {
401 case e1000_82575:
9d5c8243
AK		 402 array_wr32(E1000_MSIXBM(0), vector++,
403 E1000_EIMS_OTHER);
404
9d5c8243
AK		 405 tmp = rd32(E1000_CTRL_EXT);
406 /* enable MSI-X PBA support*/
407 tmp |= E1000_CTRL_EXT_PBA_CLR;
408
409 /* Auto-Mask interrupts upon ICR read. */
410 tmp |= E1000_CTRL_EXT_EIAME;
411 tmp |= E1000_CTRL_EXT_IRCA;
412
413 wr32(E1000_CTRL_EXT, tmp);
414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 415 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 416
2d064c06
AD		 417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
9d5c8243
AK		 430 wrfl();
431}
432
433/**
434 * igb_request_msix - Initialize MSI-X interrupts
435 *
436 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
437 * kernel.
438 **/
439static int igb_request_msix(struct igb_adapter *adapter)
440{
441 struct net_device *netdev = adapter->netdev;
442 int i, err = 0, vector = 0;
443
444 vector = 0;
445
446 for (i = 0; i < adapter->num_tx_queues; i++) {
447 struct igb_ring *ring = &(adapter->tx_ring[i]);
448 sprintf(ring->name, "%s-tx%d", netdev->name, i);
449 err = request_irq(adapter->msix_entries[vector].vector,
450 &igb_msix_tx, 0, ring->name,
451 &(adapter->tx_ring[i]));
452 if (err)
453 goto out;
454 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 455 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 456 vector++;
457 }
458 for (i = 0; i < adapter->num_rx_queues; i++) {
459 struct igb_ring *ring = &(adapter->rx_ring[i]);
460 if (strlen(netdev->name) < (IFNAMSIZ - 5))
461 sprintf(ring->name, "%s-rx%d", netdev->name, i);
462 else
463 memcpy(ring->name, netdev->name, IFNAMSIZ);
464 err = request_irq(adapter->msix_entries[vector].vector,
465 &igb_msix_rx, 0, ring->name,
466 &(adapter->rx_ring[i]));
467 if (err)
468 goto out;
469 ring->itr_register = E1000_EITR(0) + (vector << 2);
470 ring->itr_val = adapter->itr;
844290e5
PW		 471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 474 vector++;
475 }
476
477 err = request_irq(adapter->msix_entries[vector].vector,
478 &igb_msix_other, 0, netdev->name, netdev);
479 if (err)
480 goto out;
481
9d5c8243
AK		 482 igb_configure_msix(adapter);
483 return 0;
484out:
485 return err;
486}
487
488static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
489{
490 if (adapter->msix_entries) {
491 pci_disable_msix(adapter->pdev);
492 kfree(adapter->msix_entries);
493 adapter->msix_entries = NULL;
7dfc16fa 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 495 pci_disable_msi(adapter->pdev);
496 return;
497}
498
499
500/**
501 * igb_set_interrupt_capability - set MSI or MSI-X if supported
502 *
503 * Attempt to configure interrupts using the best available
504 * capabilities of the hardware and kernel.
505 **/
506static void igb_set_interrupt_capability(struct igb_adapter *adapter)
507{
508 int err;
509 int numvecs, i;
510
511 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
512 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
513 GFP_KERNEL);
514 if (!adapter->msix_entries)
515 goto msi_only;
516
517 for (i = 0; i < numvecs; i++)
518 adapter->msix_entries[i].entry = i;
519
520 err = pci_enable_msix(adapter->pdev,
521 adapter->msix_entries,
522 numvecs);
523 if (err == 0)
524 return;
525
526 igb_reset_interrupt_capability(adapter);
527
528 /* If we can't do MSI-X, try MSI */
529msi_only:
530 adapter->num_rx_queues = 1;
661086df 531 adapter->num_tx_queues = 1;
9d5c8243 532 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 533 adapter->flags |= IGB_FLAG_HAS_MSI;
661086df 534
661086df 535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 537 return;
538}
539
540/**
541 * igb_request_irq - initialize interrupts
542 *
543 * Attempts to configure interrupts using the best available
544 * capabilities of the hardware and kernel.
545 **/
546static int igb_request_irq(struct igb_adapter *adapter)
547{
548 struct net_device *netdev = adapter->netdev;
549 struct e1000_hw *hw = &adapter->hw;
550 int err = 0;
551
552 if (adapter->msix_entries) {
553 err = igb_request_msix(adapter);
844290e5 554 if (!err)
9d5c8243 555 goto request_done;
9d5c8243
AK		 556 /* fall back to MSI */
557 igb_reset_interrupt_capability(adapter);
558 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 559 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 560 igb_free_all_tx_resources(adapter);
561 igb_free_all_rx_resources(adapter);
562 adapter->num_rx_queues = 1;
563 igb_alloc_queues(adapter);
844290e5 564 } else {
2d064c06
AD		 565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
9d5c8243 576 }
844290e5 577
7dfc16fa 578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
580 netdev->name, netdev);
581 if (!err)
582 goto request_done;
583 /* fall back to legacy interrupts */
584 igb_reset_interrupt_capability(adapter);
7dfc16fa 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 586 }
587
588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
589 netdev->name, netdev);
590
6cb5e577 591 if (err)
9d5c8243
AK		 592 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
593 err);
9d5c8243
AK		 594
595request_done:
596 return err;
597}
598
599static void igb_free_irq(struct igb_adapter *adapter)
600{
601 struct net_device *netdev = adapter->netdev;
602
603 if (adapter->msix_entries) {
604 int vector = 0, i;
605
606 for (i = 0; i < adapter->num_tx_queues; i++)
607 free_irq(adapter->msix_entries[vector++].vector,
608 &(adapter->tx_ring[i]));
609 for (i = 0; i < adapter->num_rx_queues; i++)
610 free_irq(adapter->msix_entries[vector++].vector,
611 &(adapter->rx_ring[i]));
612
613 free_irq(adapter->msix_entries[vector++].vector, netdev);
614 return;
615 }
616
617 free_irq(adapter->pdev->irq, netdev);
618}
619
620/**
621 * igb_irq_disable - Mask off interrupt generation on the NIC
622 * @adapter: board private structure
623 **/
624static void igb_irq_disable(struct igb_adapter *adapter)
625{
626 struct e1000_hw *hw = &adapter->hw;
627
628 if (adapter->msix_entries) {
844290e5 629 wr32(E1000_EIAM, 0);
9d5c8243
AK		 630 wr32(E1000_EIMC, ~0);
631 wr32(E1000_EIAC, 0);
632 }
844290e5
PW		 633
634 wr32(E1000_IAM, 0);
9d5c8243
AK		 635 wr32(E1000_IMC, ~0);
636 wrfl();
637 synchronize_irq(adapter->pdev->irq);
638}
639
640/**
641 * igb_irq_enable - Enable default interrupt generation settings
642 * @adapter: board private structure
643 **/
644static void igb_irq_enable(struct igb_adapter *adapter)
645{
646 struct e1000_hw *hw = &adapter->hw;
647
648 if (adapter->msix_entries) {
844290e5
PW		 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
650 wr32(E1000_EIAM, adapter->eims_enable_mask);
651 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 652 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 653 } else {
654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
9d5c8243
AK		 657}
658
659static void igb_update_mng_vlan(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 u16 vid = adapter->hw.mng_cookie.vlan_id;
663 u16 old_vid = adapter->mng_vlan_id;
664 if (adapter->vlgrp) {
665 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
666 if (adapter->hw.mng_cookie.status &
667 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
668 igb_vlan_rx_add_vid(netdev, vid);
669 adapter->mng_vlan_id = vid;
670 } else
671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
672
673 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
674 (vid != old_vid) &&
675 !vlan_group_get_device(adapter->vlgrp, old_vid))
676 igb_vlan_rx_kill_vid(netdev, old_vid);
677 } else
678 adapter->mng_vlan_id = vid;
679 }
680}
681
682/**
683 * igb_release_hw_control - release control of the h/w to f/w
684 * @adapter: address of board private structure
685 *
686 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
687 * For ASF and Pass Through versions of f/w this means that the
688 * driver is no longer loaded.
689 *
690 **/
691static void igb_release_hw_control(struct igb_adapter *adapter)
692{
693 struct e1000_hw *hw = &adapter->hw;
694 u32 ctrl_ext;
695
696 /* Let firmware take over control of h/w */
697 ctrl_ext = rd32(E1000_CTRL_EXT);
698 wr32(E1000_CTRL_EXT,
699 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
700}
701
702
703/**
704 * igb_get_hw_control - get control of the h/w from f/w
705 * @adapter: address of board private structure
706 *
707 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
708 * For ASF and Pass Through versions of f/w this means that
709 * the driver is loaded.
710 *
711 **/
712static void igb_get_hw_control(struct igb_adapter *adapter)
713{
714 struct e1000_hw *hw = &adapter->hw;
715 u32 ctrl_ext;
716
717 /* Let firmware know the driver has taken over */
718 ctrl_ext = rd32(E1000_CTRL_EXT);
719 wr32(E1000_CTRL_EXT,
720 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
721}
722
9d5c8243
AK		 723/**
724 * igb_configure - configure the hardware for RX and TX
725 * @adapter: private board structure
726 **/
727static void igb_configure(struct igb_adapter *adapter)
728{
729 struct net_device *netdev = adapter->netdev;
730 int i;
731
732 igb_get_hw_control(adapter);
733 igb_set_multi(netdev);
734
735 igb_restore_vlan(adapter);
9d5c8243
AK		 736
737 igb_configure_tx(adapter);
738 igb_setup_rctl(adapter);
739 igb_configure_rx(adapter);
662d7205
AD		 740
741 igb_rx_fifo_flush_82575(&adapter->hw);
742
9d5c8243
AK		 743 /* call IGB_DESC_UNUSED which always leaves
744 * at least 1 descriptor unused to make sure
745 * next_to_use != next_to_clean */
746 for (i = 0; i < adapter->num_rx_queues; i++) {
747 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 748 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 749 }
750
751
752 adapter->tx_queue_len = netdev->tx_queue_len;
753}
754
755
756/**
757 * igb_up - Open the interface and prepare it to handle traffic
758 * @adapter: board private structure
759 **/
760
761int igb_up(struct igb_adapter *adapter)
762{
763 struct e1000_hw *hw = &adapter->hw;
764 int i;
765
766 /* hardware has been reset, we need to reload some things */
767 igb_configure(adapter);
768
769 clear_bit(__IGB_DOWN, &adapter->state);
770
844290e5
PW		 771 for (i = 0; i < adapter->num_rx_queues; i++)
772 napi_enable(&adapter->rx_ring[i].napi);
773 if (adapter->msix_entries)
9d5c8243 774 igb_configure_msix(adapter);
9d5c8243
AK		 775
776 /* Clear any pending interrupts. */
777 rd32(E1000_ICR);
778 igb_irq_enable(adapter);
779
780 /* Fire a link change interrupt to start the watchdog. */
781 wr32(E1000_ICS, E1000_ICS_LSC);
782 return 0;
783}
784
785void igb_down(struct igb_adapter *adapter)
786{
787 struct e1000_hw *hw = &adapter->hw;
788 struct net_device *netdev = adapter->netdev;
789 u32 tctl, rctl;
790 int i;
791
792 /* signal that we're down so the interrupt handler does not
793 * reschedule our watchdog timer */
794 set_bit(__IGB_DOWN, &adapter->state);
795
796 /* disable receives in the hardware */
797 rctl = rd32(E1000_RCTL);
798 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
799 /* flush and sleep below */
800
fd2ea0a7 801 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 802
803 /* disable transmits in the hardware */
804 tctl = rd32(E1000_TCTL);
805 tctl &= ~E1000_TCTL_EN;
806 wr32(E1000_TCTL, tctl);
807 /* flush both disables and wait for them to finish */
808 wrfl();
809 msleep(10);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 813
9d5c8243
AK		 814 igb_irq_disable(adapter);
815
816 del_timer_sync(&adapter->watchdog_timer);
817 del_timer_sync(&adapter->phy_info_timer);
818
819 netdev->tx_queue_len = adapter->tx_queue_len;
820 netif_carrier_off(netdev);
821 adapter->link_speed = 0;
822 adapter->link_duplex = 0;
823
3023682e
JK		 824 if (!pci_channel_offline(adapter->pdev))
825 igb_reset(adapter);
9d5c8243
AK		 826 igb_clean_all_tx_rings(adapter);
827 igb_clean_all_rx_rings(adapter);
828}
829
830void igb_reinit_locked(struct igb_adapter *adapter)
831{
832 WARN_ON(in_interrupt());
833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
834 msleep(1);
835 igb_down(adapter);
836 igb_up(adapter);
837 clear_bit(__IGB_RESETTING, &adapter->state);
838}
839
840void igb_reset(struct igb_adapter *adapter)
841{
842 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 843 struct e1000_mac_info *mac = &hw->mac;
844 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 845 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
846 u16 hwm;
847
848 /* Repartition Pba for greater than 9k mtu
849 * To take effect CTRL.RST is required.
850 */
2d064c06 851 if (mac->type != e1000_82576) {
9d5c8243 852 pba = E1000_PBA_34K;
2d064c06
AD		 853 }
854 else {
855 pba = E1000_PBA_64K;
856 }
9d5c8243 857
2d064c06
AD		 858 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
859 (mac->type < e1000_82576)) {
9d5c8243
AK		 860 /* adjust PBA for jumbo frames */
861 wr32(E1000_PBA, pba);
862
863 /* To maintain wire speed transmits, the Tx FIFO should be
864 * large enough to accommodate two full transmit packets,
865 * rounded up to the next 1KB and expressed in KB. Likewise,
866 * the Rx FIFO should be large enough to accommodate at least
867 * one full receive packet and is similarly rounded up and
868 * expressed in KB. */
869 pba = rd32(E1000_PBA);
870 /* upper 16 bits has Tx packet buffer allocation size in KB */
871 tx_space = pba >> 16;
872 /* lower 16 bits has Rx packet buffer allocation size in KB */
873 pba &= 0xffff;
874 /* the tx fifo also stores 16 bytes of information about the tx
875 * but don't include ethernet FCS because hardware appends it */
876 min_tx_space = (adapter->max_frame_size +
877 sizeof(struct e1000_tx_desc) -
878 ETH_FCS_LEN) * 2;
879 min_tx_space = ALIGN(min_tx_space, 1024);
880 min_tx_space >>= 10;
881 /* software strips receive CRC, so leave room for it */
882 min_rx_space = adapter->max_frame_size;
883 min_rx_space = ALIGN(min_rx_space, 1024);
884 min_rx_space >>= 10;
885
886 /* If current Tx allocation is less than the min Tx FIFO size,
887 * and the min Tx FIFO size is less than the current Rx FIFO
888 * allocation, take space away from current Rx allocation */
889 if (tx_space < min_tx_space &&
890 ((min_tx_space - tx_space) < pba)) {
891 pba = pba - (min_tx_space - tx_space);
892
893 /* if short on rx space, rx wins and must trump tx
894 * adjustment */
895 if (pba < min_rx_space)
896 pba = min_rx_space;
897 }
2d064c06 898 wr32(E1000_PBA, pba);
9d5c8243 899 }
9d5c8243
AK		 900
901 /* flow control settings */
902 /* The high water mark must be low enough to fit one full frame
903 * (or the size used for early receive) above it in the Rx FIFO.
904 * Set it to the lower of:
905 * - 90% of the Rx FIFO size, or
906 * - the full Rx FIFO size minus one full frame */
907 hwm = min(((pba << 10) * 9 / 10),
2d064c06 908 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 909
2d064c06
AD		 910 if (mac->type < e1000_82576) {
911 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
912 fc->low_water = fc->high_water - 8;
913 } else {
914 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
915 fc->low_water = fc->high_water - 16;
916 }
9d5c8243
AK		 917 fc->pause_time = 0xFFFF;
918 fc->send_xon = 1;
919 fc->type = fc->original_type;
920
921 /* Allow time for pending master requests to run */
922 adapter->hw.mac.ops.reset_hw(&adapter->hw);
923 wr32(E1000_WUC, 0);
924
925 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
926 dev_err(&adapter->pdev->dev, "Hardware Error\n");
927
928 igb_update_mng_vlan(adapter);
929
930 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
931 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
932
933 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 934 if (adapter->hw.phy.ops.get_phy_info)
935 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 936}
937
42bfd33a
TI		 938/**
939 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
940 * @pdev: PCI device information struct
941 *
942 * Returns true if an adapter needs ioport resources
943 **/
944static int igb_is_need_ioport(struct pci_dev *pdev)
945{
946 switch (pdev->device) {
947 /* Currently there are no adapters that need ioport resources */
948 default:
949 return false;
950 }
951}
952
9d5c8243
AK		 953/**
954 * igb_probe - Device Initialization Routine
955 * @pdev: PCI device information struct
956 * @ent: entry in igb_pci_tbl
957 *
958 * Returns 0 on success, negative on failure
959 *
960 * igb_probe initializes an adapter identified by a pci_dev structure.
961 * The OS initialization, configuring of the adapter private structure,
962 * and a hardware reset occur.
963 **/
964static int __devinit igb_probe(struct pci_dev *pdev,
965 const struct pci_device_id *ent)
966{
967 struct net_device *netdev;
968 struct igb_adapter *adapter;
969 struct e1000_hw *hw;
970 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
971 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 972 int i, err, pci_using_dac;
973 u16 eeprom_data = 0;
974 u16 eeprom_apme_mask = IGB_EEPROM_APME;
975 u32 part_num;
42bfd33a 976 int bars, need_ioport;
9d5c8243 977
42bfd33a
TI		 978 /* do not allocate ioport bars when not needed */
979 need_ioport = igb_is_need_ioport(pdev);
980 if (need_ioport) {
981 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
982 err = pci_enable_device(pdev);
983 } else {
984 bars = pci_select_bars(pdev, IORESOURCE_MEM);
985 err = pci_enable_device_mem(pdev);
986 }
9d5c8243
AK		 987 if (err)
988 return err;
989
990 pci_using_dac = 0;
991 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
992 if (!err) {
993 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
994 if (!err)
995 pci_using_dac = 1;
996 } else {
997 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
998 if (err) {
999 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1000 if (err) {
1001 dev_err(&pdev->dev, "No usable DMA "
1002 "configuration, aborting\n");
1003 goto err_dma;
1004 }
1005 }
1006 }
1007
42bfd33a 1008 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1009 if (err)
1010 goto err_pci_reg;
1011
1012 pci_set_master(pdev);
c682fc23 1013 pci_save_state(pdev);
9d5c8243
AK		 1014
1015 err = -ENOMEM;
661086df 1016 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1017 if (!netdev)
1018 goto err_alloc_etherdev;
1019
1020 SET_NETDEV_DEV(netdev, &pdev->dev);
1021
1022 pci_set_drvdata(pdev, netdev);
1023 adapter = netdev_priv(netdev);
1024 adapter->netdev = netdev;
1025 adapter->pdev = pdev;
1026 hw = &adapter->hw;
1027 hw->back = adapter;
1028 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1029 adapter->bars = bars;
1030 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1031
1032 mmio_start = pci_resource_start(pdev, 0);
1033 mmio_len = pci_resource_len(pdev, 0);
1034
1035 err = -EIO;
1036 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1037 if (!adapter->hw.hw_addr)
1038 goto err_ioremap;
1039
1040 netdev->open = &igb_open;
1041 netdev->stop = &igb_close;
1042 netdev->get_stats = &igb_get_stats;
1043 netdev->set_multicast_list = &igb_set_multi;
1044 netdev->set_mac_address = &igb_set_mac;
1045 netdev->change_mtu = &igb_change_mtu;
1046 netdev->do_ioctl = &igb_ioctl;
1047 igb_set_ethtool_ops(netdev);
1048 netdev->tx_timeout = &igb_tx_timeout;
1049 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1050 netdev->vlan_rx_register = igb_vlan_rx_register;
1051 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1052 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1053#ifdef CONFIG_NET_POLL_CONTROLLER
1054 netdev->poll_controller = igb_netpoll;
1055#endif
1056 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1057
1058 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1059
1060 netdev->mem_start = mmio_start;
1061 netdev->mem_end = mmio_start + mmio_len;
1062
9d5c8243
AK		 1063 /* PCI config space info */
1064 hw->vendor_id = pdev->vendor;
1065 hw->device_id = pdev->device;
1066 hw->revision_id = pdev->revision;
1067 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1068 hw->subsystem_device_id = pdev->subsystem_device;
1069
1070 /* setup the private structure */
1071 hw->back = adapter;
1072 /* Copy the default MAC, PHY and NVM function pointers */
1073 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1074 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1075 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1076 /* Initialize skew-specific constants */
1077 err = ei->get_invariants(hw);
1078 if (err)
1079 goto err_hw_init;
1080
1081 err = igb_sw_init(adapter);
1082 if (err)
1083 goto err_sw_init;
1084
1085 igb_get_bus_info_pcie(hw);
1086
7dfc16fa
AD		 1087 /* set flags */
1088 switch (hw->mac.type) {
1089 case e1000_82576:
1090 case e1000_82575:
1091 adapter->flags |= IGB_FLAG_HAS_DCA;
1092 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1093 break;
1094 default:
1095 break;
1096 }
1097
9d5c8243
AK		 1098 hw->phy.autoneg_wait_to_complete = false;
1099 hw->mac.adaptive_ifs = true;
1100
1101 /* Copper options */
1102 if (hw->phy.media_type == e1000_media_type_copper) {
1103 hw->phy.mdix = AUTO_ALL_MODES;
1104 hw->phy.disable_polarity_correction = false;
1105 hw->phy.ms_type = e1000_ms_hw_default;
1106 }
1107
1108 if (igb_check_reset_block(hw))
1109 dev_info(&pdev->dev,
1110 "PHY reset is blocked due to SOL/IDER session.\n");
1111
1112 netdev->features = NETIF_F_SG |
1113 NETIF_F_HW_CSUM |
1114 NETIF_F_HW_VLAN_TX |
1115 NETIF_F_HW_VLAN_RX |
1116 NETIF_F_HW_VLAN_FILTER;
1117
1118 netdev->features |= NETIF_F_TSO;
9d5c8243 1119 netdev->features |= NETIF_F_TSO6;
48f29ffc 1120
d3352520
AD		 1121#ifdef CONFIG_IGB_LRO
1122 netdev->features |= NETIF_F_LRO;
1123#endif
1124
48f29ffc
JK		 1125 netdev->vlan_features |= NETIF_F_TSO;
1126 netdev->vlan_features |= NETIF_F_TSO6;
1127 netdev->vlan_features |= NETIF_F_HW_CSUM;
1128 netdev->vlan_features |= NETIF_F_SG;
1129
9d5c8243
AK		 1130 if (pci_using_dac)
1131 netdev->features |= NETIF_F_HIGHDMA;
1132
1133 netdev->features |= NETIF_F_LLTX;
1134 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1135
1136 /* before reading the NVM, reset the controller to put the device in a
1137 * known good starting state */
1138 hw->mac.ops.reset_hw(hw);
1139
1140 /* make sure the NVM is good */
1141 if (igb_validate_nvm_checksum(hw) < 0) {
1142 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1143 err = -EIO;
1144 goto err_eeprom;
1145 }
1146
1147 /* copy the MAC address out of the NVM */
1148 if (hw->mac.ops.read_mac_addr(hw))
1149 dev_err(&pdev->dev, "NVM Read Error\n");
1150
1151 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1152 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1153
1154 if (!is_valid_ether_addr(netdev->perm_addr)) {
1155 dev_err(&pdev->dev, "Invalid MAC Address\n");
1156 err = -EIO;
1157 goto err_eeprom;
1158 }
1159
1160 init_timer(&adapter->watchdog_timer);
1161 adapter->watchdog_timer.function = &igb_watchdog;
1162 adapter->watchdog_timer.data = (unsigned long) adapter;
1163
1164 init_timer(&adapter->phy_info_timer);
1165 adapter->phy_info_timer.function = &igb_update_phy_info;
1166 adapter->phy_info_timer.data = (unsigned long) adapter;
1167
1168 INIT_WORK(&adapter->reset_task, igb_reset_task);
1169 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1170
1171 /* Initialize link & ring properties that are user-changeable */
1172 adapter->tx_ring->count = 256;
1173 for (i = 0; i < adapter->num_tx_queues; i++)
1174 adapter->tx_ring[i].count = adapter->tx_ring->count;
1175 adapter->rx_ring->count = 256;
1176 for (i = 0; i < adapter->num_rx_queues; i++)
1177 adapter->rx_ring[i].count = adapter->rx_ring->count;
1178
1179 adapter->fc_autoneg = true;
1180 hw->mac.autoneg = true;
1181 hw->phy.autoneg_advertised = 0x2f;
1182
1183 hw->fc.original_type = e1000_fc_default;
1184 hw->fc.type = e1000_fc_default;
1185
1186 adapter->itr_setting = 3;
1187 adapter->itr = IGB_START_ITR;
1188
1189 igb_validate_mdi_setting(hw);
1190
1191 adapter->rx_csum = 1;
1192
1193 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1194 * enable the ACPI Magic Packet filter
1195 */
1196
1197 if (hw->bus.func == 0 ||
1198 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1199 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1200 &eeprom_data);
1201
1202 if (eeprom_data & eeprom_apme_mask)
1203 adapter->eeprom_wol |= E1000_WUFC_MAG;
1204
1205 /* now that we have the eeprom settings, apply the special cases where
1206 * the eeprom may be wrong or the board simply won't support wake on
1207 * lan on a particular port */
1208 switch (pdev->device) {
1209 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1210 adapter->eeprom_wol = 0;
1211 break;
1212 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1213 case E1000_DEV_ID_82576_FIBER:
1214 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1215 /* Wake events only supported on port A for dual fiber
1216 * regardless of eeprom setting */
1217 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1218 adapter->eeprom_wol = 0;
1219 break;
7dfc16fa
AD		 1220 case E1000_DEV_ID_82576_QUAD_COPPER:
1221 /* if quad port adapter, disable WoL on all but port A */
1222 if (global_quad_port_a != 0)
1223 adapter->eeprom_wol = 0;
1224 else
1225 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1226 /* Reset for multiple quad port adapters */
1227 if (++global_quad_port_a == 4)
1228 global_quad_port_a = 0;
1229 break;
9d5c8243
AK		 1230 }
1231
1232 /* initialize the wol settings based on the eeprom settings */
1233 adapter->wol = adapter->eeprom_wol;
1234
1235 /* reset the hardware with the new settings */
1236 igb_reset(adapter);
1237
1238 /* let the f/w know that the h/w is now under the control of the
1239 * driver. */
1240 igb_get_hw_control(adapter);
1241
1242 /* tell the stack to leave us alone until igb_open() is called */
1243 netif_carrier_off(netdev);
fd2ea0a7 1244 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1245
1246 strcpy(netdev->name, "eth%d");
1247 err = register_netdev(netdev);
1248 if (err)
1249 goto err_register;
1250
fe4506b6 1251#ifdef CONFIG_DCA
7dfc16fa
AD		 1252 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1253 (dca_add_requester(&pdev->dev) == 0)) {
1254 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1255 dev_info(&pdev->dev, "DCA enabled\n");
1256 /* Always use CB2 mode, difference is masked
1257 * in the CB driver. */
1258 wr32(E1000_DCA_CTRL, 2);
1259 igb_setup_dca(adapter);
1260 }
1261#endif
1262
9d5c8243
AK		 1263 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1264 /* print bus type/speed/width info */
1265 dev_info(&pdev->dev,
1266 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1267 netdev->name,
1268 ((hw->bus.speed == e1000_bus_speed_2500)
1269 ? "2.5Gb/s" : "unknown"),
1270 ((hw->bus.width == e1000_bus_width_pcie_x4)
1271 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1272 ? "Width x1" : "unknown"),
1273 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1274 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1275
1276 igb_read_part_num(hw, &part_num);
1277 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1278 (part_num >> 8), (part_num & 0xff));
1279
1280 dev_info(&pdev->dev,
1281 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1282 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1283 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1284 adapter->num_rx_queues, adapter->num_tx_queues);
1285
9d5c8243
AK		 1286 return 0;
1287
1288err_register:
1289 igb_release_hw_control(adapter);
1290err_eeprom:
1291 if (!igb_check_reset_block(hw))
1292 hw->phy.ops.reset_phy(hw);
1293
1294 if (hw->flash_address)
1295 iounmap(hw->flash_address);
1296
1297 igb_remove_device(hw);
a88f10ec 1298 igb_free_queues(adapter);
9d5c8243
AK		 1299err_sw_init:
1300err_hw_init:
1301 iounmap(hw->hw_addr);
1302err_ioremap:
1303 free_netdev(netdev);
1304err_alloc_etherdev:
42bfd33a 1305 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1306err_pci_reg:
1307err_dma:
1308 pci_disable_device(pdev);
1309 return err;
1310}
1311
1312/**
1313 * igb_remove - Device Removal Routine
1314 * @pdev: PCI device information struct
1315 *
1316 * igb_remove is called by the PCI subsystem to alert the driver
1317 * that it should release a PCI device. The could be caused by a
1318 * Hot-Plug event, or because the driver is going to be removed from
1319 * memory.
1320 **/
1321static void __devexit igb_remove(struct pci_dev *pdev)
1322{
1323 struct net_device *netdev = pci_get_drvdata(pdev);
1324 struct igb_adapter *adapter = netdev_priv(netdev);
9280fa52 1325#ifdef CONFIG_DCA
fe4506b6 1326 struct e1000_hw *hw = &adapter->hw;
9280fa52 1327#endif
9d5c8243
AK		 1328
1329 /* flush_scheduled work may reschedule our watchdog task, so
1330 * explicitly disable watchdog tasks from being rescheduled */
1331 set_bit(__IGB_DOWN, &adapter->state);
1332 del_timer_sync(&adapter->watchdog_timer);
1333 del_timer_sync(&adapter->phy_info_timer);
1334
1335 flush_scheduled_work();
1336
fe4506b6 1337#ifdef CONFIG_DCA
7dfc16fa 1338 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1339 dev_info(&pdev->dev, "DCA disabled\n");
1340 dca_remove_requester(&pdev->dev);
7dfc16fa 1341 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1342 wr32(E1000_DCA_CTRL, 1);
1343 }
1344#endif
1345
9d5c8243
AK		 1346 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1347 * would have already happened in close and is redundant. */
1348 igb_release_hw_control(adapter);
1349
1350 unregister_netdev(netdev);
1351
c743a87e
AD		 1352 if (adapter->hw.phy.ops.reset_phy &&
1353 !igb_check_reset_block(&adapter->hw))
9d5c8243
AK		 1354 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1355
1356 igb_remove_device(&adapter->hw);
1357 igb_reset_interrupt_capability(adapter);
1358
a88f10ec 1359 igb_free_queues(adapter);
9d5c8243
AK		 1360
1361 iounmap(adapter->hw.hw_addr);
1362 if (adapter->hw.flash_address)
1363 iounmap(adapter->hw.flash_address);
42bfd33a 1364 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1365
1366 free_netdev(netdev);
1367
1368 pci_disable_device(pdev);
1369}
1370
1371/**
1372 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1373 * @adapter: board private structure to initialize
1374 *
1375 * igb_sw_init initializes the Adapter private data structure.
1376 * Fields are initialized based on PCI device information and
1377 * OS network device settings (MTU size).
1378 **/
1379static int __devinit igb_sw_init(struct igb_adapter *adapter)
1380{
1381 struct e1000_hw *hw = &adapter->hw;
1382 struct net_device *netdev = adapter->netdev;
1383 struct pci_dev *pdev = adapter->pdev;
1384
1385 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1386
1387 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1388 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1389 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1390 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1391
1392 /* Number of supported queues. */
1393 /* Having more queues than CPUs doesn't make sense. */
661086df 1394 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1395 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1396
661086df
PWJ		 1397 /* This call may decrease the number of queues depending on
1398 * interrupt mode. */
9d5c8243
AK		 1399 igb_set_interrupt_capability(adapter);
1400
1401 if (igb_alloc_queues(adapter)) {
1402 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1403 return -ENOMEM;
1404 }
1405
1406 /* Explicitly disable IRQ since the NIC can be in any state. */
1407 igb_irq_disable(adapter);
1408
1409 set_bit(__IGB_DOWN, &adapter->state);
1410 return 0;
1411}
1412
1413/**
1414 * igb_open - Called when a network interface is made active
1415 * @netdev: network interface device structure
1416 *
1417 * Returns 0 on success, negative value on failure
1418 *
1419 * The open entry point is called when a network interface is made
1420 * active by the system (IFF_UP). At this point all resources needed
1421 * for transmit and receive operations are allocated, the interrupt
1422 * handler is registered with the OS, the watchdog timer is started,
1423 * and the stack is notified that the interface is ready.
1424 **/
1425static int igb_open(struct net_device *netdev)
1426{
1427 struct igb_adapter *adapter = netdev_priv(netdev);
1428 struct e1000_hw *hw = &adapter->hw;
1429 int err;
1430 int i;
1431
1432 /* disallow open during test */
1433 if (test_bit(__IGB_TESTING, &adapter->state))
1434 return -EBUSY;
1435
1436 /* allocate transmit descriptors */
1437 err = igb_setup_all_tx_resources(adapter);
1438 if (err)
1439 goto err_setup_tx;
1440
1441 /* allocate receive descriptors */
1442 err = igb_setup_all_rx_resources(adapter);
1443 if (err)
1444 goto err_setup_rx;
1445
1446 /* e1000_power_up_phy(adapter); */
1447
1448 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1449 if ((adapter->hw.mng_cookie.status &
1450 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1451 igb_update_mng_vlan(adapter);
1452
1453 /* before we allocate an interrupt, we must be ready to handle it.
1454 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1455 * as soon as we call pci_request_irq, so we have to setup our
1456 * clean_rx handler before we do so. */
1457 igb_configure(adapter);
1458
1459 err = igb_request_irq(adapter);
1460 if (err)
1461 goto err_req_irq;
1462
1463 /* From here on the code is the same as igb_up() */
1464 clear_bit(__IGB_DOWN, &adapter->state);
1465
844290e5
PW		 1466 for (i = 0; i < adapter->num_rx_queues; i++)
1467 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1468
1469 /* Clear any pending interrupts. */
1470 rd32(E1000_ICR);
844290e5
PW		 1471
1472 igb_irq_enable(adapter);
1473
d55b53ff
JK		 1474 netif_tx_start_all_queues(netdev);
1475
9d5c8243
AK		 1476 /* Fire a link status change interrupt to start the watchdog. */
1477 wr32(E1000_ICS, E1000_ICS_LSC);
1478
1479 return 0;
1480
1481err_req_irq:
1482 igb_release_hw_control(adapter);
1483 /* e1000_power_down_phy(adapter); */
1484 igb_free_all_rx_resources(adapter);
1485err_setup_rx:
1486 igb_free_all_tx_resources(adapter);
1487err_setup_tx:
1488 igb_reset(adapter);
1489
1490 return err;
1491}
1492
1493/**
1494 * igb_close - Disables a network interface
1495 * @netdev: network interface device structure
1496 *
1497 * Returns 0, this is not allowed to fail
1498 *
1499 * The close entry point is called when an interface is de-activated
1500 * by the OS. The hardware is still under the driver's control, but
1501 * needs to be disabled. A global MAC reset is issued to stop the
1502 * hardware, and all transmit and receive resources are freed.
1503 **/
1504static int igb_close(struct net_device *netdev)
1505{
1506 struct igb_adapter *adapter = netdev_priv(netdev);
1507
1508 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1509 igb_down(adapter);
1510
1511 igb_free_irq(adapter);
1512
1513 igb_free_all_tx_resources(adapter);
1514 igb_free_all_rx_resources(adapter);
1515
1516 /* kill manageability vlan ID if supported, but not if a vlan with
1517 * the same ID is registered on the host OS (let 8021q kill it) */
1518 if ((adapter->hw.mng_cookie.status &
1519 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1520 !(adapter->vlgrp &&
1521 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1522 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1523
1524 return 0;
1525}
1526
1527/**
1528 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1529 * @adapter: board private structure
1530 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1531 *
1532 * Return 0 on success, negative on failure
1533 **/
1534
1535int igb_setup_tx_resources(struct igb_adapter *adapter,
1536 struct igb_ring *tx_ring)
1537{
1538 struct pci_dev *pdev = adapter->pdev;
1539 int size;
1540
1541 size = sizeof(struct igb_buffer) * tx_ring->count;
1542 tx_ring->buffer_info = vmalloc(size);
1543 if (!tx_ring->buffer_info)
1544 goto err;
1545 memset(tx_ring->buffer_info, 0, size);
1546
1547 /* round up to nearest 4K */
1548 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1549 + sizeof(u32);
1550 tx_ring->size = ALIGN(tx_ring->size, 4096);
1551
1552 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1553 &tx_ring->dma);
1554
1555 if (!tx_ring->desc)
1556 goto err;
1557
1558 tx_ring->adapter = adapter;
1559 tx_ring->next_to_use = 0;
1560 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1561 return 0;
1562
1563err:
1564 vfree(tx_ring->buffer_info);
1565 dev_err(&adapter->pdev->dev,
1566 "Unable to allocate memory for the transmit descriptor ring\n");
1567 return -ENOMEM;
1568}
1569
1570/**
1571 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1572 * (Descriptors) for all queues
1573 * @adapter: board private structure
1574 *
1575 * Return 0 on success, negative on failure
1576 **/
1577static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1578{
1579 int i, err = 0;
661086df 1580 int r_idx;
9d5c8243
AK		 1581
1582 for (i = 0; i < adapter->num_tx_queues; i++) {
1583 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1584 if (err) {
1585 dev_err(&adapter->pdev->dev,
1586 "Allocation for Tx Queue %u failed\n", i);
1587 for (i--; i >= 0; i--)
3b644cf6 1588 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1589 break;
1590 }
1591 }
1592
661086df
PWJ		 1593 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1594 r_idx = i % adapter->num_tx_queues;
1595 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1596 }
9d5c8243
AK		 1597 return err;
1598}
1599
1600/**
1601 * igb_configure_tx - Configure transmit Unit after Reset
1602 * @adapter: board private structure
1603 *
1604 * Configure the Tx unit of the MAC after a reset.
1605 **/
1606static void igb_configure_tx(struct igb_adapter *adapter)
1607{
1608 u64 tdba, tdwba;
1609 struct e1000_hw *hw = &adapter->hw;
1610 u32 tctl;
1611 u32 txdctl, txctrl;
1612 int i;
1613
1614 for (i = 0; i < adapter->num_tx_queues; i++) {
1615 struct igb_ring *ring = &(adapter->tx_ring[i]);
1616
1617 wr32(E1000_TDLEN(i),
1618 ring->count * sizeof(struct e1000_tx_desc));
1619 tdba = ring->dma;
1620 wr32(E1000_TDBAL(i),
1621 tdba & 0x00000000ffffffffULL);
1622 wr32(E1000_TDBAH(i), tdba >> 32);
1623
1624 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1625 tdwba |= 1; /* enable head wb */
1626 wr32(E1000_TDWBAL(i),
1627 tdwba & 0x00000000ffffffffULL);
1628 wr32(E1000_TDWBAH(i), tdwba >> 32);
1629
1630 ring->head = E1000_TDH(i);
1631 ring->tail = E1000_TDT(i);
1632 writel(0, hw->hw_addr + ring->tail);
1633 writel(0, hw->hw_addr + ring->head);
1634 txdctl = rd32(E1000_TXDCTL(i));
1635 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1636 wr32(E1000_TXDCTL(i), txdctl);
1637
1638 /* Turn off Relaxed Ordering on head write-backs. The
1639 * writebacks MUST be delivered in order or it will
1640 * completely screw up our bookeeping.
1641 */
1642 txctrl = rd32(E1000_DCA_TXCTRL(i));
1643 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1644 wr32(E1000_DCA_TXCTRL(i), txctrl);
1645 }
1646
1647
1648
1649 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1650
1651 /* Program the Transmit Control Register */
1652
1653 tctl = rd32(E1000_TCTL);
1654 tctl &= ~E1000_TCTL_CT;
1655 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1656 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1657
1658 igb_config_collision_dist(hw);
1659
1660 /* Setup Transmit Descriptor Settings for eop descriptor */
1661 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1662
1663 /* Enable transmits */
1664 tctl |= E1000_TCTL_EN;
1665
1666 wr32(E1000_TCTL, tctl);
1667}
1668
1669/**
1670 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1671 * @adapter: board private structure
1672 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1673 *
1674 * Returns 0 on success, negative on failure
1675 **/
1676
1677int igb_setup_rx_resources(struct igb_adapter *adapter,
1678 struct igb_ring *rx_ring)
1679{
1680 struct pci_dev *pdev = adapter->pdev;
1681 int size, desc_len;
1682
d3352520
AD		 1683#ifdef CONFIG_IGB_LRO
1684 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1685 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1686 if (!rx_ring->lro_mgr.lro_arr)
1687 goto err;
1688 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1689#endif
1690
9d5c8243
AK		 1691 size = sizeof(struct igb_buffer) * rx_ring->count;
1692 rx_ring->buffer_info = vmalloc(size);
1693 if (!rx_ring->buffer_info)
1694 goto err;
1695 memset(rx_ring->buffer_info, 0, size);
1696
1697 desc_len = sizeof(union e1000_adv_rx_desc);
1698
1699 /* Round up to nearest 4K */
1700 rx_ring->size = rx_ring->count * desc_len;
1701 rx_ring->size = ALIGN(rx_ring->size, 4096);
1702
1703 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1704 &rx_ring->dma);
1705
1706 if (!rx_ring->desc)
1707 goto err;
1708
1709 rx_ring->next_to_clean = 0;
1710 rx_ring->next_to_use = 0;
9d5c8243
AK		 1711
1712 rx_ring->adapter = adapter;
9d5c8243
AK		 1713
1714 return 0;
1715
1716err:
d3352520
AD		 1717#ifdef CONFIG_IGB_LRO
1718 vfree(rx_ring->lro_mgr.lro_arr);
1719 rx_ring->lro_mgr.lro_arr = NULL;
1720#endif
9d5c8243
AK		 1721 vfree(rx_ring->buffer_info);
1722 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1723 "the receive descriptor ring\n");
1724 return -ENOMEM;
1725}
1726
1727/**
1728 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1729 * (Descriptors) for all queues
1730 * @adapter: board private structure
1731 *
1732 * Return 0 on success, negative on failure
1733 **/
1734static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1735{
1736 int i, err = 0;
1737
1738 for (i = 0; i < adapter->num_rx_queues; i++) {
1739 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1740 if (err) {
1741 dev_err(&adapter->pdev->dev,
1742 "Allocation for Rx Queue %u failed\n", i);
1743 for (i--; i >= 0; i--)
3b644cf6 1744 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1745 break;
1746 }
1747 }
1748
1749 return err;
1750}
1751
1752/**
1753 * igb_setup_rctl - configure the receive control registers
1754 * @adapter: Board private structure
1755 **/
1756static void igb_setup_rctl(struct igb_adapter *adapter)
1757{
1758 struct e1000_hw *hw = &adapter->hw;
1759 u32 rctl;
1760 u32 srrctl = 0;
1761 int i;
1762
1763 rctl = rd32(E1000_RCTL);
1764
1765 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1766
1767 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1768 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1769 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1770
87cb7e8c
AK		 1771 /*
1772 * enable stripping of CRC. It's unlikely this will break BMC
1773 * redirection as it did with e1000. Newer features require
1774 * that the HW strips the CRC.
9d5c8243 1775 */
87cb7e8c 1776 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1777
1778 rctl &= ~E1000_RCTL_SBP;
1779
1780 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1781 rctl &= ~E1000_RCTL_LPE;
1782 else
1783 rctl |= E1000_RCTL_LPE;
1784 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1785 /* Setup buffer sizes */
1786 rctl &= ~E1000_RCTL_SZ_4096;
1787 rctl |= E1000_RCTL_BSEX;
1788 switch (adapter->rx_buffer_len) {
1789 case IGB_RXBUFFER_256:
1790 rctl |= E1000_RCTL_SZ_256;
1791 rctl &= ~E1000_RCTL_BSEX;
1792 break;
1793 case IGB_RXBUFFER_512:
1794 rctl |= E1000_RCTL_SZ_512;
1795 rctl &= ~E1000_RCTL_BSEX;
1796 break;
1797 case IGB_RXBUFFER_1024:
1798 rctl |= E1000_RCTL_SZ_1024;
1799 rctl &= ~E1000_RCTL_BSEX;
1800 break;
1801 case IGB_RXBUFFER_2048:
1802 default:
1803 rctl |= E1000_RCTL_SZ_2048;
1804 rctl &= ~E1000_RCTL_BSEX;
1805 break;
9d5c8243
AK		 1806 }
1807 } else {
1808 rctl &= ~E1000_RCTL_BSEX;
1809 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1810 }
1811
1812 /* 82575 and greater support packet-split where the protocol
1813 * header is placed in skb->data and the packet data is
1814 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1815 * In the case of a non-split, skb->data is linearly filled,
1816 * followed by the page buffers. Therefore, skb->data is
1817 * sized to hold the largest protocol header.
1818 */
1819 /* allocations using alloc_page take too long for regular MTU
1820 * so only enable packet split for jumbo frames */
1821 if (rctl & E1000_RCTL_LPE) {
1822 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1823 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1824 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1825 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1826 } else {
1827 adapter->rx_ps_hdr_size = 0;
1828 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1829 }
1830
1831 for (i = 0; i < adapter->num_rx_queues; i++)
1832 wr32(E1000_SRRCTL(i), srrctl);
1833
1834 wr32(E1000_RCTL, rctl);
1835}
1836
1837/**
1838 * igb_configure_rx - Configure receive Unit after Reset
1839 * @adapter: board private structure
1840 *
1841 * Configure the Rx unit of the MAC after a reset.
1842 **/
1843static void igb_configure_rx(struct igb_adapter *adapter)
1844{
1845 u64 rdba;
1846 struct e1000_hw *hw = &adapter->hw;
1847 u32 rctl, rxcsum;
1848 u32 rxdctl;
1849 int i;
1850
1851 /* disable receives while setting up the descriptors */
1852 rctl = rd32(E1000_RCTL);
1853 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1854 wrfl();
1855 mdelay(10);
1856
1857 if (adapter->itr_setting > 3)
6eb5a7f1 1858 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1859
1860 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1861 * the Base and Length of the Rx Descriptor Ring */
1862 for (i = 0; i < adapter->num_rx_queues; i++) {
1863 struct igb_ring *ring = &(adapter->rx_ring[i]);
1864 rdba = ring->dma;
1865 wr32(E1000_RDBAL(i),
1866 rdba & 0x00000000ffffffffULL);
1867 wr32(E1000_RDBAH(i), rdba >> 32);
1868 wr32(E1000_RDLEN(i),
1869 ring->count * sizeof(union e1000_adv_rx_desc));
1870
1871 ring->head = E1000_RDH(i);
1872 ring->tail = E1000_RDT(i);
1873 writel(0, hw->hw_addr + ring->tail);
1874 writel(0, hw->hw_addr + ring->head);
1875
1876 rxdctl = rd32(E1000_RXDCTL(i));
1877 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1878 rxdctl &= 0xFFF00000;
1879 rxdctl |= IGB_RX_PTHRESH;
1880 rxdctl |= IGB_RX_HTHRESH << 8;
1881 rxdctl |= IGB_RX_WTHRESH << 16;
1882 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1883#ifdef CONFIG_IGB_LRO
1884 /* Intitial LRO Settings */
1885 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1886 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1887 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1888 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1889 ring->lro_mgr.dev = adapter->netdev;
1890 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1891 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1892#endif
9d5c8243
AK		 1893 }
1894
1895 if (adapter->num_rx_queues > 1) {
1896 u32 random[10];
1897 u32 mrqc;
1898 u32 j, shift;
1899 union e1000_reta {
1900 u32 dword;
1901 u8 bytes[4];
1902 } reta;
1903
1904 get_random_bytes(&random[0], 40);
1905
2d064c06
AD		 1906 if (hw->mac.type >= e1000_82576)
1907 shift = 0;
1908 else
1909 shift = 6;
9d5c8243
AK		 1910 for (j = 0; j < (32 * 4); j++) {
1911 reta.bytes[j & 3] =
1912 (j % adapter->num_rx_queues) << shift;
1913 if ((j & 3) == 3)
1914 writel(reta.dword,
1915 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1916 }
1917 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1918
1919 /* Fill out hash function seeds */
1920 for (j = 0; j < 10; j++)
1921 array_wr32(E1000_RSSRK(0), j, random[j]);
1922
1923 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1924 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1925 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1926 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1927 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1928 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1929 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1930 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1931
1932
1933 wr32(E1000_MRQC, mrqc);
1934
1935 /* Multiqueue and raw packet checksumming are mutually
1936 * exclusive. Note that this not the same as TCP/IP
1937 * checksumming, which works fine. */
1938 rxcsum = rd32(E1000_RXCSUM);
1939 rxcsum |= E1000_RXCSUM_PCSD;
1940 wr32(E1000_RXCSUM, rxcsum);
1941 } else {
1942 /* Enable Receive Checksum Offload for TCP and UDP */
1943 rxcsum = rd32(E1000_RXCSUM);
1944 if (adapter->rx_csum) {
1945 rxcsum |= E1000_RXCSUM_TUOFL;
1946
1947 /* Enable IPv4 payload checksum for UDP fragments
1948 * Must be used in conjunction with packet-split. */
1949 if (adapter->rx_ps_hdr_size)
1950 rxcsum |= E1000_RXCSUM_IPPCSE;
1951 } else {
1952 rxcsum &= ~E1000_RXCSUM_TUOFL;
1953 /* don't need to clear IPPCSE as it defaults to 0 */
1954 }
1955 wr32(E1000_RXCSUM, rxcsum);
1956 }
1957
1958 if (adapter->vlgrp)
1959 wr32(E1000_RLPML,
1960 adapter->max_frame_size + VLAN_TAG_SIZE);
1961 else
1962 wr32(E1000_RLPML, adapter->max_frame_size);
1963
1964 /* Enable Receives */
1965 wr32(E1000_RCTL, rctl);
1966}
1967
1968/**
1969 * igb_free_tx_resources - Free Tx Resources per Queue
1970 * @adapter: board private structure
1971 * @tx_ring: Tx descriptor ring for a specific queue
1972 *
1973 * Free all transmit software resources
1974 **/
3b644cf6 1975static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1976{
3b644cf6 1977 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1978
3b644cf6 1979 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1980
1981 vfree(tx_ring->buffer_info);
1982 tx_ring->buffer_info = NULL;
1983
1984 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1985
1986 tx_ring->desc = NULL;
1987}
1988
1989/**
1990 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1991 * @adapter: board private structure
1992 *
1993 * Free all transmit software resources
1994 **/
1995static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1996{
1997 int i;
1998
1999 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2000 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2001}
2002
2003static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2004 struct igb_buffer *buffer_info)
2005{
2006 if (buffer_info->dma) {
2007 pci_unmap_page(adapter->pdev,
2008 buffer_info->dma,
2009 buffer_info->length,
2010 PCI_DMA_TODEVICE);
2011 buffer_info->dma = 0;
2012 }
2013 if (buffer_info->skb) {
2014 dev_kfree_skb_any(buffer_info->skb);
2015 buffer_info->skb = NULL;
2016 }
2017 buffer_info->time_stamp = 0;
2018 /* buffer_info must be completely set up in the transmit path */
2019}
2020
2021/**
2022 * igb_clean_tx_ring - Free Tx Buffers
2023 * @adapter: board private structure
2024 * @tx_ring: ring to be cleaned
2025 **/
3b644cf6 2026static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2027{
3b644cf6 2028 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2029 struct igb_buffer *buffer_info;
2030 unsigned long size;
2031 unsigned int i;
2032
2033 if (!tx_ring->buffer_info)
2034 return;
2035 /* Free all the Tx ring sk_buffs */
2036
2037 for (i = 0; i < tx_ring->count; i++) {
2038 buffer_info = &tx_ring->buffer_info[i];
2039 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2040 }
2041
2042 size = sizeof(struct igb_buffer) * tx_ring->count;
2043 memset(tx_ring->buffer_info, 0, size);
2044
2045 /* Zero out the descriptor ring */
2046
2047 memset(tx_ring->desc, 0, tx_ring->size);
2048
2049 tx_ring->next_to_use = 0;
2050 tx_ring->next_to_clean = 0;
2051
2052 writel(0, adapter->hw.hw_addr + tx_ring->head);
2053 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2054}
2055
2056/**
2057 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2058 * @adapter: board private structure
2059 **/
2060static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2061{
2062 int i;
2063
2064 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2065 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2066}
2067
2068/**
2069 * igb_free_rx_resources - Free Rx Resources
2070 * @adapter: board private structure
2071 * @rx_ring: ring to clean the resources from
2072 *
2073 * Free all receive software resources
2074 **/
3b644cf6 2075static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2076{
3b644cf6 2077 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2078
3b644cf6 2079 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2080
2081 vfree(rx_ring->buffer_info);
2082 rx_ring->buffer_info = NULL;
2083
d3352520
AD		 2084#ifdef CONFIG_IGB_LRO
2085 vfree(rx_ring->lro_mgr.lro_arr);
2086 rx_ring->lro_mgr.lro_arr = NULL;
2087#endif
2088
9d5c8243
AK		 2089 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2090
2091 rx_ring->desc = NULL;
2092}
2093
2094/**
2095 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2096 * @adapter: board private structure
2097 *
2098 * Free all receive software resources
2099 **/
2100static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2101{
2102 int i;
2103
2104 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2105 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2106}
2107
2108/**
2109 * igb_clean_rx_ring - Free Rx Buffers per Queue
2110 * @adapter: board private structure
2111 * @rx_ring: ring to free buffers from
2112 **/
3b644cf6 2113static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2114{
3b644cf6 2115 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2116 struct igb_buffer *buffer_info;
2117 struct pci_dev *pdev = adapter->pdev;
2118 unsigned long size;
2119 unsigned int i;
2120
2121 if (!rx_ring->buffer_info)
2122 return;
2123 /* Free all the Rx ring sk_buffs */
2124 for (i = 0; i < rx_ring->count; i++) {
2125 buffer_info = &rx_ring->buffer_info[i];
2126 if (buffer_info->dma) {
2127 if (adapter->rx_ps_hdr_size)
2128 pci_unmap_single(pdev, buffer_info->dma,
2129 adapter->rx_ps_hdr_size,
2130 PCI_DMA_FROMDEVICE);
2131 else
2132 pci_unmap_single(pdev, buffer_info->dma,
2133 adapter->rx_buffer_len,
2134 PCI_DMA_FROMDEVICE);
2135 buffer_info->dma = 0;
2136 }
2137
2138 if (buffer_info->skb) {
2139 dev_kfree_skb(buffer_info->skb);
2140 buffer_info->skb = NULL;
2141 }
2142 if (buffer_info->page) {
bf36c1a0
AD		 2143 if (buffer_info->page_dma)
2144 pci_unmap_page(pdev, buffer_info->page_dma,
2145 PAGE_SIZE / 2,
2146 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2147 put_page(buffer_info->page);
2148 buffer_info->page = NULL;
2149 buffer_info->page_dma = 0;
bf36c1a0 2150 buffer_info->page_offset = 0;
9d5c8243
AK		 2151 }
2152 }
2153
9d5c8243
AK		 2154 size = sizeof(struct igb_buffer) * rx_ring->count;
2155 memset(rx_ring->buffer_info, 0, size);
2156
2157 /* Zero out the descriptor ring */
2158 memset(rx_ring->desc, 0, rx_ring->size);
2159
2160 rx_ring->next_to_clean = 0;
2161 rx_ring->next_to_use = 0;
2162
2163 writel(0, adapter->hw.hw_addr + rx_ring->head);
2164 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2165}
2166
2167/**
2168 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2169 * @adapter: board private structure
2170 **/
2171static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2172{
2173 int i;
2174
2175 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2176 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2177}
2178
2179/**
2180 * igb_set_mac - Change the Ethernet Address of the NIC
2181 * @netdev: network interface device structure
2182 * @p: pointer to an address structure
2183 *
2184 * Returns 0 on success, negative on failure
2185 **/
2186static int igb_set_mac(struct net_device *netdev, void *p)
2187{
2188 struct igb_adapter *adapter = netdev_priv(netdev);
2189 struct sockaddr *addr = p;
2190
2191 if (!is_valid_ether_addr(addr->sa_data))
2192 return -EADDRNOTAVAIL;
2193
2194 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2195 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2196
2197 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2198
2199 return 0;
2200}
2201
2202/**
2203 * igb_set_multi - Multicast and Promiscuous mode set
2204 * @netdev: network interface device structure
2205 *
2206 * The set_multi entry point is called whenever the multicast address
2207 * list or the network interface flags are updated. This routine is
2208 * responsible for configuring the hardware for proper multicast,
2209 * promiscuous mode, and all-multi behavior.
2210 **/
2211static void igb_set_multi(struct net_device *netdev)
2212{
2213 struct igb_adapter *adapter = netdev_priv(netdev);
2214 struct e1000_hw *hw = &adapter->hw;
2215 struct e1000_mac_info *mac = &hw->mac;
2216 struct dev_mc_list *mc_ptr;
2217 u8 *mta_list;
2218 u32 rctl;
2219 int i;
2220
2221 /* Check for Promiscuous and All Multicast modes */
2222
2223 rctl = rd32(E1000_RCTL);
2224
746b9f02 2225 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2226 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2227 rctl &= ~E1000_RCTL_VFE;
2228 } else {
2229 if (netdev->flags & IFF_ALLMULTI) {
2230 rctl |= E1000_RCTL_MPE;
2231 rctl &= ~E1000_RCTL_UPE;
2232 } else
2233 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2234 rctl |= E1000_RCTL_VFE;
746b9f02 2235 }
9d5c8243
AK		 2236 wr32(E1000_RCTL, rctl);
2237
2238 if (!netdev->mc_count) {
2239 /* nothing to program, so clear mc list */
2d064c06 2240 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2241 mac->rar_entry_count);
2242 return;
2243 }
2244
2245 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2246 if (!mta_list)
2247 return;
2248
2249 /* The shared function expects a packed array of only addresses. */
2250 mc_ptr = netdev->mc_list;
2251
2252 for (i = 0; i < netdev->mc_count; i++) {
2253 if (!mc_ptr)
2254 break;
2255 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2256 mc_ptr = mc_ptr->next;
2257 }
2d064c06
AD		 2258 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2259 mac->rar_entry_count);
9d5c8243
AK		 2260 kfree(mta_list);
2261}
2262
2263/* Need to wait a few seconds after link up to get diagnostic information from
2264 * the phy */
2265static void igb_update_phy_info(unsigned long data)
2266{
2267 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2268 if (adapter->hw.phy.ops.get_phy_info)
2269 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2270}
2271
2272/**
2273 * igb_watchdog - Timer Call-back
2274 * @data: pointer to adapter cast into an unsigned long
2275 **/
2276static void igb_watchdog(unsigned long data)
2277{
2278 struct igb_adapter *adapter = (struct igb_adapter *)data;
2279 /* Do the rest outside of interrupt context */
2280 schedule_work(&adapter->watchdog_task);
2281}
2282
2283static void igb_watchdog_task(struct work_struct *work)
2284{
2285 struct igb_adapter *adapter = container_of(work,
2286 struct igb_adapter, watchdog_task);
2287 struct e1000_hw *hw = &adapter->hw;
2288
2289 struct net_device *netdev = adapter->netdev;
2290 struct igb_ring *tx_ring = adapter->tx_ring;
2291 struct e1000_mac_info *mac = &adapter->hw.mac;
2292 u32 link;
7a6ea550 2293 u32 eics = 0;
9d5c8243 2294 s32 ret_val;
7a6ea550 2295 int i;
9d5c8243
AK		 2296
2297 if ((netif_carrier_ok(netdev)) &&
2298 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2299 goto link_up;
2300
2301 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2302 if ((ret_val == E1000_ERR_PHY) &&
2303 (hw->phy.type == e1000_phy_igp_3) &&
2304 (rd32(E1000_CTRL) &
2305 E1000_PHY_CTRL_GBE_DISABLE))
2306 dev_info(&adapter->pdev->dev,
2307 "Gigabit has been disabled, downgrading speed\n");
2308
2309 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2310 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2311 link = mac->serdes_has_link;
2312 else
2313 link = rd32(E1000_STATUS) &
2314 E1000_STATUS_LU;
2315
2316 if (link) {
2317 if (!netif_carrier_ok(netdev)) {
2318 u32 ctrl;
2319 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2320 &adapter->link_speed,
2321 &adapter->link_duplex);
2322
2323 ctrl = rd32(E1000_CTRL);
2324 dev_info(&adapter->pdev->dev,
2325 "NIC Link is Up %d Mbps %s, "
2326 "Flow Control: %s\n",
2327 adapter->link_speed,
2328 adapter->link_duplex == FULL_DUPLEX ?
2329 "Full Duplex" : "Half Duplex",
2330 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2331 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2332 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2333 E1000_CTRL_TFCE) ? "TX" : "None")));
2334
2335 /* tweak tx_queue_len according to speed/duplex and
2336 * adjust the timeout factor */
2337 netdev->tx_queue_len = adapter->tx_queue_len;
2338 adapter->tx_timeout_factor = 1;
2339 switch (adapter->link_speed) {
2340 case SPEED_10:
2341 netdev->tx_queue_len = 10;
2342 adapter->tx_timeout_factor = 14;
2343 break;
2344 case SPEED_100:
2345 netdev->tx_queue_len = 100;
2346 /* maybe add some timeout factor ? */
2347 break;
2348 }
2349
2350 netif_carrier_on(netdev);
fd2ea0a7 2351 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2352
2353 if (!test_bit(__IGB_DOWN, &adapter->state))
2354 mod_timer(&adapter->phy_info_timer,
2355 round_jiffies(jiffies + 2 * HZ));
2356 }
2357 } else {
2358 if (netif_carrier_ok(netdev)) {
2359 adapter->link_speed = 0;
2360 adapter->link_duplex = 0;
2361 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2362 netif_carrier_off(netdev);
fd2ea0a7 2363 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2364 if (!test_bit(__IGB_DOWN, &adapter->state))
2365 mod_timer(&adapter->phy_info_timer,
2366 round_jiffies(jiffies + 2 * HZ));
2367 }
2368 }
2369
2370link_up:
2371 igb_update_stats(adapter);
2372
2373 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2374 adapter->tpt_old = adapter->stats.tpt;
2375 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2376 adapter->colc_old = adapter->stats.colc;
2377
2378 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2379 adapter->gorc_old = adapter->stats.gorc;
2380 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2381 adapter->gotc_old = adapter->stats.gotc;
2382
2383 igb_update_adaptive(&adapter->hw);
2384
2385 if (!netif_carrier_ok(netdev)) {
2386 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2387 /* We've lost link, so the controller stops DMA,
2388 * but we've got queued Tx work that's never going
2389 * to get done, so reset controller to flush Tx.
2390 * (Do the reset outside of interrupt context). */
2391 adapter->tx_timeout_count++;
2392 schedule_work(&adapter->reset_task);
2393 }
2394 }
2395
2396 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2397 if (adapter->msix_entries) {
2398 for (i = 0; i < adapter->num_rx_queues; i++)
2399 eics |= adapter->rx_ring[i].eims_value;
2400 wr32(E1000_EICS, eics);
2401 } else {
2402 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2403 }
9d5c8243
AK		 2404
2405 /* Force detection of hung controller every watchdog period */
2406 tx_ring->detect_tx_hung = true;
2407
2408 /* Reset the timer */
2409 if (!test_bit(__IGB_DOWN, &adapter->state))
2410 mod_timer(&adapter->watchdog_timer,
2411 round_jiffies(jiffies + 2 * HZ));
2412}
2413
2414enum latency_range {
2415 lowest_latency = 0,
2416 low_latency = 1,
2417 bulk_latency = 2,
2418 latency_invalid = 255
2419};
2420
2421
6eb5a7f1
AD		 2422/**
2423 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2424 *
2425 * Stores a new ITR value based on strictly on packet size. This
2426 * algorithm is less sophisticated than that used in igb_update_itr,
2427 * due to the difficulty of synchronizing statistics across multiple
2428 * receive rings. The divisors and thresholds used by this fuction
2429 * were determined based on theoretical maximum wire speed and testing
2430 * data, in order to minimize response time while increasing bulk
2431 * throughput.
2432 * This functionality is controlled by the InterruptThrottleRate module
2433 * parameter (see igb_param.c)
2434 * NOTE: This function is called only when operating in a multiqueue
2435 * receive environment.
2436 * @rx_ring: pointer to ring
2437 **/
2438static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2439{
6eb5a7f1
AD		 2440 int new_val = rx_ring->itr_val;
2441 int avg_wire_size = 0;
2442 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2443
6eb5a7f1
AD		 2444 if (!rx_ring->total_packets)
2445 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2446
6eb5a7f1
AD		 2447 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2448 * ints/sec - ITR timer value of 120 ticks.
2449 */
2450 if (adapter->link_speed != SPEED_1000) {
2451 new_val = 120;
2452 goto set_itr_val;
9d5c8243 2453 }
6eb5a7f1 2454 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2455
6eb5a7f1
AD		 2456 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2457 avg_wire_size += 24;
2458
2459 /* Don't starve jumbo frames */
2460 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2461
6eb5a7f1
AD		 2462 /* Give a little boost to mid-size frames */
2463 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2464 new_val = avg_wire_size / 3;
2465 else
2466 new_val = avg_wire_size / 2;
9d5c8243 2467
6eb5a7f1 2468set_itr_val:
9d5c8243
AK		 2469 if (new_val != rx_ring->itr_val) {
2470 rx_ring->itr_val = new_val;
6eb5a7f1 2471 rx_ring->set_itr = 1;
9d5c8243 2472 }
6eb5a7f1
AD		 2473clear_counts:
2474 rx_ring->total_bytes = 0;
2475 rx_ring->total_packets = 0;
9d5c8243
AK		 2476}
2477
2478/**
2479 * igb_update_itr - update the dynamic ITR value based on statistics
2480 * Stores a new ITR value based on packets and byte
2481 * counts during the last interrupt. The advantage of per interrupt
2482 * computation is faster updates and more accurate ITR for the current
2483 * traffic pattern. Constants in this function were computed
2484 * based on theoretical maximum wire speed and thresholds were set based
2485 * on testing data as well as attempting to minimize response time
2486 * while increasing bulk throughput.
2487 * this functionality is controlled by the InterruptThrottleRate module
2488 * parameter (see igb_param.c)
2489 * NOTE: These calculations are only valid when operating in a single-
2490 * queue environment.
2491 * @adapter: pointer to adapter
2492 * @itr_setting: current adapter->itr
2493 * @packets: the number of packets during this measurement interval
2494 * @bytes: the number of bytes during this measurement interval
2495 **/
2496static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2497 int packets, int bytes)
2498{
2499 unsigned int retval = itr_setting;
2500
2501 if (packets == 0)
2502 goto update_itr_done;
2503
2504 switch (itr_setting) {
2505 case lowest_latency:
2506 /* handle TSO and jumbo frames */
2507 if (bytes/packets > 8000)
2508 retval = bulk_latency;
2509 else if ((packets < 5) && (bytes > 512))
2510 retval = low_latency;
2511 break;
2512 case low_latency: /* 50 usec aka 20000 ints/s */
2513 if (bytes > 10000) {
2514 /* this if handles the TSO accounting */
2515 if (bytes/packets > 8000) {
2516 retval = bulk_latency;
2517 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2518 retval = bulk_latency;
2519 } else if ((packets > 35)) {
2520 retval = lowest_latency;
2521 }
2522 } else if (bytes/packets > 2000) {
2523 retval = bulk_latency;
2524 } else if (packets <= 2 && bytes < 512) {
2525 retval = lowest_latency;
2526 }
2527 break;
2528 case bulk_latency: /* 250 usec aka 4000 ints/s */
2529 if (bytes > 25000) {
2530 if (packets > 35)
2531 retval = low_latency;
2532 } else if (bytes < 6000) {
2533 retval = low_latency;
2534 }
2535 break;
2536 }
2537
2538update_itr_done:
2539 return retval;
2540}
2541
6eb5a7f1 2542static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2543{
2544 u16 current_itr;
2545 u32 new_itr = adapter->itr;
2546
2547 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2548 if (adapter->link_speed != SPEED_1000) {
2549 current_itr = 0;
2550 new_itr = 4000;
2551 goto set_itr_now;
2552 }
2553
2554 adapter->rx_itr = igb_update_itr(adapter,
2555 adapter->rx_itr,
2556 adapter->rx_ring->total_packets,
2557 adapter->rx_ring->total_bytes);
9d5c8243 2558
6eb5a7f1 2559 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2560 adapter->tx_itr = igb_update_itr(adapter,
2561 adapter->tx_itr,
2562 adapter->tx_ring->total_packets,
2563 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2564
2565 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2566 } else {
2567 current_itr = adapter->rx_itr;
2568 }
2569
6eb5a7f1
AD		 2570 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2571 if (adapter->itr_setting == 3 &&
2572 current_itr == lowest_latency)
2573 current_itr = low_latency;
2574
9d5c8243
AK		 2575 switch (current_itr) {
2576 /* counts and packets in update_itr are dependent on these numbers */
2577 case lowest_latency:
2578 new_itr = 70000;
2579 break;
2580 case low_latency:
2581 new_itr = 20000; /* aka hwitr = ~200 */
2582 break;
2583 case bulk_latency:
2584 new_itr = 4000;
2585 break;
2586 default:
2587 break;
2588 }
2589
2590set_itr_now:
6eb5a7f1
AD		 2591 adapter->rx_ring->total_bytes = 0;
2592 adapter->rx_ring->total_packets = 0;
2593 if (adapter->rx_ring->buddy) {
2594 adapter->rx_ring->buddy->total_bytes = 0;
2595 adapter->rx_ring->buddy->total_packets = 0;
2596 }
2597
9d5c8243
AK		 2598 if (new_itr != adapter->itr) {
2599 /* this attempts to bias the interrupt rate towards Bulk
2600 * by adding intermediate steps when interrupt rate is
2601 * increasing */
2602 new_itr = new_itr > adapter->itr ?
2603 min(adapter->itr + (new_itr >> 2), new_itr) :
2604 new_itr;
2605 /* Don't write the value here; it resets the adapter's
2606 * internal timer, and causes us to delay far longer than
2607 * we should between interrupts. Instead, we write the ITR
2608 * value at the beginning of the next interrupt so the timing
2609 * ends up being correct.
2610 */
2611 adapter->itr = new_itr;
6eb5a7f1
AD		 2612 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2613 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2614 }
2615
2616 return;
2617}
2618
2619
2620#define IGB_TX_FLAGS_CSUM 0x00000001
2621#define IGB_TX_FLAGS_VLAN 0x00000002
2622#define IGB_TX_FLAGS_TSO 0x00000004
2623#define IGB_TX_FLAGS_IPV4 0x00000008
2624#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2625#define IGB_TX_FLAGS_VLAN_SHIFT 16
2626
2627static inline int igb_tso_adv(struct igb_adapter *adapter,
2628 struct igb_ring *tx_ring,
2629 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2630{
2631 struct e1000_adv_tx_context_desc *context_desc;
2632 unsigned int i;
2633 int err;
2634 struct igb_buffer *buffer_info;
2635 u32 info = 0, tu_cmd = 0;
2636 u32 mss_l4len_idx, l4len;
2637 *hdr_len = 0;
2638
2639 if (skb_header_cloned(skb)) {
2640 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2641 if (err)
2642 return err;
2643 }
2644
2645 l4len = tcp_hdrlen(skb);
2646 *hdr_len += l4len;
2647
2648 if (skb->protocol == htons(ETH_P_IP)) {
2649 struct iphdr *iph = ip_hdr(skb);
2650 iph->tot_len = 0;
2651 iph->check = 0;
2652 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2653 iph->daddr, 0,
2654 IPPROTO_TCP,
2655 0);
2656 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2657 ipv6_hdr(skb)->payload_len = 0;
2658 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2659 &ipv6_hdr(skb)->daddr,
2660 0, IPPROTO_TCP, 0);
2661 }
2662
2663 i = tx_ring->next_to_use;
2664
2665 buffer_info = &tx_ring->buffer_info[i];
2666 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2667 /* VLAN MACLEN IPLEN */
2668 if (tx_flags & IGB_TX_FLAGS_VLAN)
2669 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2670 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2671 *hdr_len += skb_network_offset(skb);
2672 info |= skb_network_header_len(skb);
2673 *hdr_len += skb_network_header_len(skb);
2674 context_desc->vlan_macip_lens = cpu_to_le32(info);
2675
2676 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2677 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2678
2679 if (skb->protocol == htons(ETH_P_IP))
2680 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2681 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2682
2683 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2684
2685 /* MSS L4LEN IDX */
2686 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2687 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2688
7dfc16fa
AD		 2689 /* Context index must be unique per ring. */
2690 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2691 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2692
2693 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2694 context_desc->seqnum_seed = 0;
2695
2696 buffer_info->time_stamp = jiffies;
2697 buffer_info->dma = 0;
2698 i++;
2699 if (i == tx_ring->count)
2700 i = 0;
2701
2702 tx_ring->next_to_use = i;
2703
2704 return true;
2705}
2706
2707static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2708 struct igb_ring *tx_ring,
2709 struct sk_buff *skb, u32 tx_flags)
2710{
2711 struct e1000_adv_tx_context_desc *context_desc;
2712 unsigned int i;
2713 struct igb_buffer *buffer_info;
2714 u32 info = 0, tu_cmd = 0;
2715
2716 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2717 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2718 i = tx_ring->next_to_use;
2719 buffer_info = &tx_ring->buffer_info[i];
2720 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2721
2722 if (tx_flags & IGB_TX_FLAGS_VLAN)
2723 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2724 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2725 if (skb->ip_summed == CHECKSUM_PARTIAL)
2726 info |= skb_network_header_len(skb);
2727
2728 context_desc->vlan_macip_lens = cpu_to_le32(info);
2729
2730 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2731
2732 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2733 switch (skb->protocol) {
2734 case __constant_htons(ETH_P_IP):
9d5c8243 2735 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2736 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2737 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2738 break;
2739 case __constant_htons(ETH_P_IPV6):
2740 /* XXX what about other V6 headers?? */
2741 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2742 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2743 break;
2744 default:
2745 if (unlikely(net_ratelimit()))
2746 dev_warn(&adapter->pdev->dev,
2747 "partial checksum but proto=%x!\n",
2748 skb->protocol);
2749 break;
2750 }
9d5c8243
AK		 2751 }
2752
2753 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2754 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2755 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2756 context_desc->mss_l4len_idx =
2757 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2758
2759 buffer_info->time_stamp = jiffies;
2760 buffer_info->dma = 0;
2761
2762 i++;
2763 if (i == tx_ring->count)
2764 i = 0;
2765 tx_ring->next_to_use = i;
2766
2767 return true;
2768 }
2769
2770
2771 return false;
2772}
2773
2774#define IGB_MAX_TXD_PWR 16
2775#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2776
2777static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2778 struct igb_ring *tx_ring,
2779 struct sk_buff *skb)
2780{
2781 struct igb_buffer *buffer_info;
2782 unsigned int len = skb_headlen(skb);
2783 unsigned int count = 0, i;
2784 unsigned int f;
2785
2786 i = tx_ring->next_to_use;
2787
2788 buffer_info = &tx_ring->buffer_info[i];
2789 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2790 buffer_info->length = len;
2791 /* set time_stamp *before* dma to help avoid a possible race */
2792 buffer_info->time_stamp = jiffies;
2793 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2794 PCI_DMA_TODEVICE);
2795 count++;
2796 i++;
2797 if (i == tx_ring->count)
2798 i = 0;
2799
2800 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2801 struct skb_frag_struct *frag;
2802
2803 frag = &skb_shinfo(skb)->frags[f];
2804 len = frag->size;
2805
2806 buffer_info = &tx_ring->buffer_info[i];
2807 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2808 buffer_info->length = len;
2809 buffer_info->time_stamp = jiffies;
2810 buffer_info->dma = pci_map_page(adapter->pdev,
2811 frag->page,
2812 frag->page_offset,
2813 len,
2814 PCI_DMA_TODEVICE);
2815
2816 count++;
2817 i++;
2818 if (i == tx_ring->count)
2819 i = 0;
2820 }
2821
2822 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2823 tx_ring->buffer_info[i].skb = skb;
2824
2825 return count;
2826}
2827
2828static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2829 struct igb_ring *tx_ring,
2830 int tx_flags, int count, u32 paylen,
2831 u8 hdr_len)
2832{
2833 union e1000_adv_tx_desc *tx_desc = NULL;
2834 struct igb_buffer *buffer_info;
2835 u32 olinfo_status = 0, cmd_type_len;
2836 unsigned int i;
2837
2838 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2839 E1000_ADVTXD_DCMD_DEXT);
2840
2841 if (tx_flags & IGB_TX_FLAGS_VLAN)
2842 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2843
2844 if (tx_flags & IGB_TX_FLAGS_TSO) {
2845 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2846
2847 /* insert tcp checksum */
2848 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2849
2850 /* insert ip checksum */
2851 if (tx_flags & IGB_TX_FLAGS_IPV4)
2852 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2853
2854 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2855 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2856 }
2857
7dfc16fa
AD		 2858 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2859 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2860 IGB_TX_FLAGS_VLAN)))
661086df 2861 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2862
2863 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2864
2865 i = tx_ring->next_to_use;
2866 while (count--) {
2867 buffer_info = &tx_ring->buffer_info[i];
2868 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2869 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2870 tx_desc->read.cmd_type_len =
2871 cpu_to_le32(cmd_type_len | buffer_info->length);
2872 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2873 i++;
2874 if (i == tx_ring->count)
2875 i = 0;
2876 }
2877
2878 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2879 /* Force memory writes to complete before letting h/w
2880 * know there are new descriptors to fetch. (Only
2881 * applicable for weak-ordered memory model archs,
2882 * such as IA-64). */
2883 wmb();
2884
2885 tx_ring->next_to_use = i;
2886 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2887 /* we need this if more than one processor can write to our tail
2888 * at a time, it syncronizes IO on IA64/Altix systems */
2889 mmiowb();
2890}
2891
2892static int __igb_maybe_stop_tx(struct net_device *netdev,
2893 struct igb_ring *tx_ring, int size)
2894{
2895 struct igb_adapter *adapter = netdev_priv(netdev);
2896
661086df 2897 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2898
9d5c8243
AK		 2899 /* Herbert's original patch had:
2900 * smp_mb__after_netif_stop_queue();
2901 * but since that doesn't exist yet, just open code it. */
2902 smp_mb();
2903
2904 /* We need to check again in a case another CPU has just
2905 * made room available. */
2906 if (IGB_DESC_UNUSED(tx_ring) < size)
2907 return -EBUSY;
2908
2909 /* A reprieve! */
661086df 2910 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2911 ++adapter->restart_queue;
2912 return 0;
2913}
2914
2915static int igb_maybe_stop_tx(struct net_device *netdev,
2916 struct igb_ring *tx_ring, int size)
2917{
2918 if (IGB_DESC_UNUSED(tx_ring) >= size)
2919 return 0;
2920 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2921}
2922
2923#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2924
2925static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2926 struct net_device *netdev,
2927 struct igb_ring *tx_ring)
2928{
2929 struct igb_adapter *adapter = netdev_priv(netdev);
2930 unsigned int tx_flags = 0;
2931 unsigned int len;
9d5c8243
AK		 2932 u8 hdr_len = 0;
2933 int tso = 0;
2934
2935 len = skb_headlen(skb);
2936
2937 if (test_bit(__IGB_DOWN, &adapter->state)) {
2938 dev_kfree_skb_any(skb);
2939 return NETDEV_TX_OK;
2940 }
2941
2942 if (skb->len <= 0) {
2943 dev_kfree_skb_any(skb);
2944 return NETDEV_TX_OK;
2945 }
2946
9d5c8243
AK		 2947 /* need: 1 descriptor per page,
2948 * + 2 desc gap to keep tail from touching head,
2949 * + 1 desc for skb->data,
2950 * + 1 desc for context descriptor,
2951 * otherwise try next time */
2952 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2953 /* this is a hard error */
9d5c8243
AK		 2954 return NETDEV_TX_BUSY;
2955 }
6eb5a7f1 2956 skb_orphan(skb);
9d5c8243
AK		 2957
2958 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2959 tx_flags |= IGB_TX_FLAGS_VLAN;
2960 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2961 }
2962
661086df
PWJ		 2963 if (skb->protocol == htons(ETH_P_IP))
2964 tx_flags |= IGB_TX_FLAGS_IPV4;
2965
9d5c8243
AK		 2966 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2967 &hdr_len) : 0;
2968
2969 if (tso < 0) {
2970 dev_kfree_skb_any(skb);
9d5c8243
AK		 2971 return NETDEV_TX_OK;
2972 }
2973
2974 if (tso)
2975 tx_flags |= IGB_TX_FLAGS_TSO;
2976 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2977 if (skb->ip_summed == CHECKSUM_PARTIAL)
2978 tx_flags |= IGB_TX_FLAGS_CSUM;
2979
9d5c8243
AK		 2980 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2981 igb_tx_map_adv(adapter, tx_ring, skb),
2982 skb->len, hdr_len);
2983
2984 netdev->trans_start = jiffies;
2985
2986 /* Make sure there is space in the ring for the next send. */
2987 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2988
9d5c8243
AK		 2989 return NETDEV_TX_OK;
2990}
2991
2992static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2993{
2994 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 2995 struct igb_ring *tx_ring;
2996
661086df
PWJ		 2997 int r_idx = 0;
2998 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
2999 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3000
3001 /* This goes back to the question of how to logically map a tx queue
3002 * to a flow. Right now, performance is impacted slightly negatively
3003 * if using multiple tx queues. If the stack breaks away from a
3004 * single qdisc implementation, we can look at this again. */
3005 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3006}
3007
3008/**
3009 * igb_tx_timeout - Respond to a Tx Hang
3010 * @netdev: network interface device structure
3011 **/
3012static void igb_tx_timeout(struct net_device *netdev)
3013{
3014 struct igb_adapter *adapter = netdev_priv(netdev);
3015 struct e1000_hw *hw = &adapter->hw;
3016
3017 /* Do the reset outside of interrupt context */
3018 adapter->tx_timeout_count++;
3019 schedule_work(&adapter->reset_task);
3020 wr32(E1000_EICS, adapter->eims_enable_mask &
3021 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3022}
3023
3024static void igb_reset_task(struct work_struct *work)
3025{
3026 struct igb_adapter *adapter;
3027 adapter = container_of(work, struct igb_adapter, reset_task);
3028
3029 igb_reinit_locked(adapter);
3030}
3031
3032/**
3033 * igb_get_stats - Get System Network Statistics
3034 * @netdev: network interface device structure
3035 *
3036 * Returns the address of the device statistics structure.
3037 * The statistics are actually updated from the timer callback.
3038 **/
3039static struct net_device_stats *
3040igb_get_stats(struct net_device *netdev)
3041{
3042 struct igb_adapter *adapter = netdev_priv(netdev);
3043
3044 /* only return the current stats */
3045 return &adapter->net_stats;
3046}
3047
3048/**
3049 * igb_change_mtu - Change the Maximum Transfer Unit
3050 * @netdev: network interface device structure
3051 * @new_mtu: new value for maximum frame size
3052 *
3053 * Returns 0 on success, negative on failure
3054 **/
3055static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3056{
3057 struct igb_adapter *adapter = netdev_priv(netdev);
3058 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3059
3060 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3061 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3062 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3063 return -EINVAL;
3064 }
3065
3066#define MAX_STD_JUMBO_FRAME_SIZE 9234
3067 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3068 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3069 return -EINVAL;
3070 }
3071
3072 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3073 msleep(1);
3074 /* igb_down has a dependency on max_frame_size */
3075 adapter->max_frame_size = max_frame;
3076 if (netif_running(netdev))
3077 igb_down(adapter);
3078
3079 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3080 * means we reserve 2 more, this pushes us to allocate from the next
3081 * larger slab size.
3082 * i.e. RXBUFFER_2048 --> size-4096 slab
3083 */
3084
3085 if (max_frame <= IGB_RXBUFFER_256)
3086 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3087 else if (max_frame <= IGB_RXBUFFER_512)
3088 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3089 else if (max_frame <= IGB_RXBUFFER_1024)
3090 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3091 else if (max_frame <= IGB_RXBUFFER_2048)
3092 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3093 else
bf36c1a0
AD		 3094#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3095 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3096#else
3097 adapter->rx_buffer_len = PAGE_SIZE / 2;
3098#endif
9d5c8243
AK		 3099 /* adjust allocation if LPE protects us, and we aren't using SBP */
3100 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3101 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3102 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3103
3104 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3105 netdev->mtu, new_mtu);
3106 netdev->mtu = new_mtu;
3107
3108 if (netif_running(netdev))
3109 igb_up(adapter);
3110 else
3111 igb_reset(adapter);
3112
3113 clear_bit(__IGB_RESETTING, &adapter->state);
3114
3115 return 0;
3116}
3117
3118/**
3119 * igb_update_stats - Update the board statistics counters
3120 * @adapter: board private structure
3121 **/
3122
3123void igb_update_stats(struct igb_adapter *adapter)
3124{
3125 struct e1000_hw *hw = &adapter->hw;
3126 struct pci_dev *pdev = adapter->pdev;
3127 u16 phy_tmp;
3128
3129#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3130
3131 /*
3132 * Prevent stats update while adapter is being reset, or if the pci
3133 * connection is down.
3134 */
3135 if (adapter->link_speed == 0)
3136 return;
3137 if (pci_channel_offline(pdev))
3138 return;
3139
3140 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3141 adapter->stats.gprc += rd32(E1000_GPRC);
3142 adapter->stats.gorc += rd32(E1000_GORCL);
3143 rd32(E1000_GORCH); /* clear GORCL */
3144 adapter->stats.bprc += rd32(E1000_BPRC);
3145 adapter->stats.mprc += rd32(E1000_MPRC);
3146 adapter->stats.roc += rd32(E1000_ROC);
3147
3148 adapter->stats.prc64 += rd32(E1000_PRC64);
3149 adapter->stats.prc127 += rd32(E1000_PRC127);
3150 adapter->stats.prc255 += rd32(E1000_PRC255);
3151 adapter->stats.prc511 += rd32(E1000_PRC511);
3152 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3153 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3154 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3155 adapter->stats.sec += rd32(E1000_SEC);
3156
3157 adapter->stats.mpc += rd32(E1000_MPC);
3158 adapter->stats.scc += rd32(E1000_SCC);
3159 adapter->stats.ecol += rd32(E1000_ECOL);
3160 adapter->stats.mcc += rd32(E1000_MCC);
3161 adapter->stats.latecol += rd32(E1000_LATECOL);
3162 adapter->stats.dc += rd32(E1000_DC);
3163 adapter->stats.rlec += rd32(E1000_RLEC);
3164 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3165 adapter->stats.xontxc += rd32(E1000_XONTXC);
3166 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3167 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3168 adapter->stats.fcruc += rd32(E1000_FCRUC);
3169 adapter->stats.gptc += rd32(E1000_GPTC);
3170 adapter->stats.gotc += rd32(E1000_GOTCL);
3171 rd32(E1000_GOTCH); /* clear GOTCL */
3172 adapter->stats.rnbc += rd32(E1000_RNBC);
3173 adapter->stats.ruc += rd32(E1000_RUC);
3174 adapter->stats.rfc += rd32(E1000_RFC);
3175 adapter->stats.rjc += rd32(E1000_RJC);
3176 adapter->stats.tor += rd32(E1000_TORH);
3177 adapter->stats.tot += rd32(E1000_TOTH);
3178 adapter->stats.tpr += rd32(E1000_TPR);
3179
3180 adapter->stats.ptc64 += rd32(E1000_PTC64);
3181 adapter->stats.ptc127 += rd32(E1000_PTC127);
3182 adapter->stats.ptc255 += rd32(E1000_PTC255);
3183 adapter->stats.ptc511 += rd32(E1000_PTC511);
3184 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3185 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3186
3187 adapter->stats.mptc += rd32(E1000_MPTC);
3188 adapter->stats.bptc += rd32(E1000_BPTC);
3189
3190 /* used for adaptive IFS */
3191
3192 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3193 adapter->stats.tpt += hw->mac.tx_packet_delta;
3194 hw->mac.collision_delta = rd32(E1000_COLC);
3195 adapter->stats.colc += hw->mac.collision_delta;
3196
3197 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3198 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3199 adapter->stats.tncrs += rd32(E1000_TNCRS);
3200 adapter->stats.tsctc += rd32(E1000_TSCTC);
3201 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3202
3203 adapter->stats.iac += rd32(E1000_IAC);
3204 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3205 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3206 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3207 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3208 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3209 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3210 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3211 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3212
3213 /* Fill out the OS statistics structure */
3214 adapter->net_stats.multicast = adapter->stats.mprc;
3215 adapter->net_stats.collisions = adapter->stats.colc;
3216
3217 /* Rx Errors */
3218
3219 /* RLEC on some newer hardware can be incorrect so build
3220 * our own version based on RUC and ROC */
3221 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3222 adapter->stats.crcerrs + adapter->stats.algnerrc +
3223 adapter->stats.ruc + adapter->stats.roc +
3224 adapter->stats.cexterr;
3225 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3226 adapter->stats.roc;
3227 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3228 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3229 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3230
3231 /* Tx Errors */
3232 adapter->net_stats.tx_errors = adapter->stats.ecol +
3233 adapter->stats.latecol;
3234 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3235 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3236 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3237
3238 /* Tx Dropped needs to be maintained elsewhere */
3239
3240 /* Phy Stats */
3241 if (hw->phy.media_type == e1000_media_type_copper) {
3242 if ((adapter->link_speed == SPEED_1000) &&
3243 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3244 &phy_tmp))) {
3245 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3246 adapter->phy_stats.idle_errors += phy_tmp;
3247 }
3248 }
3249
3250 /* Management Stats */
3251 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3252 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3253 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3254}
3255
3256
3257static irqreturn_t igb_msix_other(int irq, void *data)
3258{
3259 struct net_device *netdev = data;
3260 struct igb_adapter *adapter = netdev_priv(netdev);
3261 struct e1000_hw *hw = &adapter->hw;
844290e5 3262 u32 icr = rd32(E1000_ICR);
9d5c8243 3263
844290e5
PW		 3264 /* reading ICR causes bit 31 of EICR to be cleared */
3265 if (!(icr & E1000_ICR_LSC))
3266 goto no_link_interrupt;
3267 hw->mac.get_link_status = 1;
3268 /* guard against interrupt when we're going down */
3269 if (!test_bit(__IGB_DOWN, &adapter->state))
3270 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3271
9d5c8243
AK		 3272no_link_interrupt:
3273 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3274 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3275
3276 return IRQ_HANDLED;
3277}
3278
3279static irqreturn_t igb_msix_tx(int irq, void *data)
3280{
3281 struct igb_ring *tx_ring = data;
3282 struct igb_adapter *adapter = tx_ring->adapter;
3283 struct e1000_hw *hw = &adapter->hw;
3284
fe4506b6 3285#ifdef CONFIG_DCA
7dfc16fa 3286 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3287 igb_update_tx_dca(tx_ring);
3288#endif
9d5c8243
AK		 3289 tx_ring->total_bytes = 0;
3290 tx_ring->total_packets = 0;
661086df
PWJ		 3291
3292 /* auto mask will automatically reenable the interrupt when we write
3293 * EICS */
3b644cf6 3294 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3295 /* Ring was not completely cleaned, so fire another interrupt */
3296 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3297 else
9d5c8243 3298 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3299
9d5c8243
AK		 3300 return IRQ_HANDLED;
3301}
3302
6eb5a7f1
AD		 3303static void igb_write_itr(struct igb_ring *ring)
3304{
3305 struct e1000_hw *hw = &ring->adapter->hw;
3306 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3307 switch (hw->mac.type) {
3308 case e1000_82576:
3309 wr32(ring->itr_register,
3310 ring->itr_val |
3311 0x80000000);
3312 break;
3313 default:
3314 wr32(ring->itr_register,
3315 ring->itr_val |
3316 (ring->itr_val << 16));
3317 break;
3318 }
3319 ring->set_itr = 0;
3320 }
3321}
3322
9d5c8243
AK		 3323static irqreturn_t igb_msix_rx(int irq, void *data)
3324{
3325 struct igb_ring *rx_ring = data;
3326 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3327
844290e5
PW		 3328 /* Write the ITR value calculated at the end of the
3329 * previous interrupt.
3330 */
9d5c8243 3331
6eb5a7f1 3332 igb_write_itr(rx_ring);
9d5c8243 3333
844290e5
PW		 3334 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3335 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3336
fe4506b6 3337#ifdef CONFIG_DCA
7dfc16fa 3338 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3339 igb_update_rx_dca(rx_ring);
3340#endif
3341 return IRQ_HANDLED;
3342}
3343
3344#ifdef CONFIG_DCA
3345static void igb_update_rx_dca(struct igb_ring *rx_ring)
3346{
3347 u32 dca_rxctrl;
3348 struct igb_adapter *adapter = rx_ring->adapter;
3349 struct e1000_hw *hw = &adapter->hw;
3350 int cpu = get_cpu();
3351 int q = rx_ring - adapter->rx_ring;
3352
3353 if (rx_ring->cpu != cpu) {
3354 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3355 if (hw->mac.type == e1000_82576) {
3356 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3357 dca_rxctrl |= dca_get_tag(cpu) <<
3358 E1000_DCA_RXCTRL_CPUID_SHIFT;
3359 } else {
3360 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3361 dca_rxctrl |= dca_get_tag(cpu);
3362 }
fe4506b6
JC		 3363 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3364 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3365 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3366 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3367 rx_ring->cpu = cpu;
3368 }
3369 put_cpu();
3370}
3371
3372static void igb_update_tx_dca(struct igb_ring *tx_ring)
3373{
3374 u32 dca_txctrl;
3375 struct igb_adapter *adapter = tx_ring->adapter;
3376 struct e1000_hw *hw = &adapter->hw;
3377 int cpu = get_cpu();
3378 int q = tx_ring - adapter->tx_ring;
3379
3380 if (tx_ring->cpu != cpu) {
3381 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3382 if (hw->mac.type == e1000_82576) {
3383 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3384 dca_txctrl |= dca_get_tag(cpu) <<
3385 E1000_DCA_TXCTRL_CPUID_SHIFT;
3386 } else {
3387 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3388 dca_txctrl |= dca_get_tag(cpu);
3389 }
fe4506b6
JC		 3390 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3391 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3392 tx_ring->cpu = cpu;
3393 }
3394 put_cpu();
3395}
3396
3397static void igb_setup_dca(struct igb_adapter *adapter)
3398{
3399 int i;
3400
7dfc16fa 3401 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3402 return;
3403
3404 for (i = 0; i < adapter->num_tx_queues; i++) {
3405 adapter->tx_ring[i].cpu = -1;
3406 igb_update_tx_dca(&adapter->tx_ring[i]);
3407 }
3408 for (i = 0; i < adapter->num_rx_queues; i++) {
3409 adapter->rx_ring[i].cpu = -1;
3410 igb_update_rx_dca(&adapter->rx_ring[i]);
3411 }
3412}
3413
3414static int __igb_notify_dca(struct device *dev, void *data)
3415{
3416 struct net_device *netdev = dev_get_drvdata(dev);
3417 struct igb_adapter *adapter = netdev_priv(netdev);
3418 struct e1000_hw *hw = &adapter->hw;
3419 unsigned long event = *(unsigned long *)data;
3420
7dfc16fa
AD		 3421 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3422 goto out;
3423
fe4506b6
JC		 3424 switch (event) {
3425 case DCA_PROVIDER_ADD:
3426 /* if already enabled, don't do it again */
7dfc16fa 3427 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3428 break;
7dfc16fa 3429 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3430 /* Always use CB2 mode, difference is masked
3431 * in the CB driver. */
3432 wr32(E1000_DCA_CTRL, 2);
3433 if (dca_add_requester(dev) == 0) {
3434 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3435 igb_setup_dca(adapter);
3436 break;
3437 }
3438 /* Fall Through since DCA is disabled. */
3439 case DCA_PROVIDER_REMOVE:
7dfc16fa 3440 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3441 /* without this a class_device is left
3442 * hanging around in the sysfs model */
3443 dca_remove_requester(dev);
3444 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3445 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3446 wr32(E1000_DCA_CTRL, 1);
3447 }
3448 break;
3449 }
7dfc16fa 3450out:
fe4506b6 3451 return 0;
9d5c8243
AK		 3452}
3453
fe4506b6
JC		 3454static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3455 void *p)
3456{
3457 int ret_val;
3458
3459 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3460 __igb_notify_dca);
3461
3462 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3463}
3464#endif /* CONFIG_DCA */
9d5c8243
AK		 3465
3466/**
3467 * igb_intr_msi - Interrupt Handler
3468 * @irq: interrupt number
3469 * @data: pointer to a network interface device structure
3470 **/
3471static irqreturn_t igb_intr_msi(int irq, void *data)
3472{
3473 struct net_device *netdev = data;
3474 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3475 struct e1000_hw *hw = &adapter->hw;
3476 /* read ICR disables interrupts using IAM */
3477 u32 icr = rd32(E1000_ICR);
3478
6eb5a7f1 3479 igb_write_itr(adapter->rx_ring);
9d5c8243 3480
9d5c8243
AK		 3481 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3482 hw->mac.get_link_status = 1;
3483 if (!test_bit(__IGB_DOWN, &adapter->state))
3484 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3485 }
3486
844290e5 3487 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3488
3489 return IRQ_HANDLED;
3490}
3491
3492/**
3493 * igb_intr - Interrupt Handler
3494 * @irq: interrupt number
3495 * @data: pointer to a network interface device structure
3496 **/
3497static irqreturn_t igb_intr(int irq, void *data)
3498{
3499 struct net_device *netdev = data;
3500 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3501 struct e1000_hw *hw = &adapter->hw;
3502 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3503 * need for the IMC write */
3504 u32 icr = rd32(E1000_ICR);
3505 u32 eicr = 0;
3506 if (!icr)
3507 return IRQ_NONE; /* Not our interrupt */
3508
6eb5a7f1 3509 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3510
3511 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3512 * not set, then the adapter didn't send an interrupt */
3513 if (!(icr & E1000_ICR_INT_ASSERTED))
3514 return IRQ_NONE;
3515
3516 eicr = rd32(E1000_EICR);
3517
3518 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3519 hw->mac.get_link_status = 1;
3520 /* guard against interrupt when we're going down */
3521 if (!test_bit(__IGB_DOWN, &adapter->state))
3522 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3523 }
3524
844290e5 3525 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3526
3527 return IRQ_HANDLED;
3528}
3529
3530/**
661086df
PWJ		 3531 * igb_poll - NAPI Rx polling callback
3532 * @napi: napi polling structure
3533 * @budget: count of how many packets we should handle
9d5c8243 3534 **/
661086df 3535static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3536{
661086df
PWJ		 3537 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3538 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3539 struct net_device *netdev = adapter->netdev;
661086df 3540 int tx_clean_complete, work_done = 0;
9d5c8243 3541
661086df 3542 /* this poll routine only supports one tx and one rx queue */
fe4506b6 3543#ifdef CONFIG_DCA
7dfc16fa 3544 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3545 igb_update_tx_dca(&adapter->tx_ring[0]);
3546#endif
661086df 3547 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6
JC		 3548
3549#ifdef CONFIG_DCA
7dfc16fa 3550 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3551 igb_update_rx_dca(&adapter->rx_ring[0]);
3552#endif
661086df 3553 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3554
3555 /* If no Tx and not enough Rx work done, exit the polling mode */
3556 if ((tx_clean_complete && (work_done < budget)) ||
3557 !netif_running(netdev)) {
9d5c8243 3558 if (adapter->itr_setting & 3)
6eb5a7f1 3559 igb_set_itr(adapter);
9d5c8243
AK		 3560 netif_rx_complete(netdev, napi);
3561 if (!test_bit(__IGB_DOWN, &adapter->state))
3562 igb_irq_enable(adapter);
3563 return 0;
3564 }
3565
3566 return 1;
3567}
3568
3569static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3570{
3571 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3572 struct igb_adapter *adapter = rx_ring->adapter;
3573 struct e1000_hw *hw = &adapter->hw;
3574 struct net_device *netdev = adapter->netdev;
3575 int work_done = 0;
3576
3577 /* Keep link state information with original netdev */
3578 if (!netif_carrier_ok(netdev))
3579 goto quit_polling;
3580
fe4506b6 3581#ifdef CONFIG_DCA
7dfc16fa 3582 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3583 igb_update_rx_dca(rx_ring);
3584#endif
3b644cf6 3585 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3586
3587
3588 /* If not enough Rx work done, exit the polling mode */
3589 if ((work_done == 0) || !netif_running(netdev)) {
3590quit_polling:
3591 netif_rx_complete(netdev, napi);
3592
6eb5a7f1
AD		 3593 if (adapter->itr_setting & 3) {
3594 if (adapter->num_rx_queues == 1)
3595 igb_set_itr(adapter);
3596 else
3597 igb_update_ring_itr(rx_ring);
9d5c8243 3598 }
844290e5
PW		 3599
3600 if (!test_bit(__IGB_DOWN, &adapter->state))
3601 wr32(E1000_EIMS, rx_ring->eims_value);
3602
9d5c8243
AK		 3603 return 0;
3604 }
3605
3606 return 1;
3607}
6d8126f9
AV		 3608
3609static inline u32 get_head(struct igb_ring *tx_ring)
3610{
3611 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3612 return le32_to_cpu(*(volatile __le32 *)end);
3613}
3614
9d5c8243
AK		 3615/**
3616 * igb_clean_tx_irq - Reclaim resources after transmit completes
3617 * @adapter: board private structure
3618 * returns true if ring is completely cleaned
3619 **/
3b644cf6 3620static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3621{
3b644cf6 3622 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3623 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3624 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3625 struct e1000_tx_desc *tx_desc;
3626 struct igb_buffer *buffer_info;
3627 struct sk_buff *skb;
3628 unsigned int i;
3629 u32 head, oldhead;
3630 unsigned int count = 0;
3631 bool cleaned = false;
3632 bool retval = true;
3633 unsigned int total_bytes = 0, total_packets = 0;
3634
3635 rmb();
6d8126f9 3636 head = get_head(tx_ring);
9d5c8243
AK		 3637 i = tx_ring->next_to_clean;
3638 while (1) {
3639 while (i != head) {
3640 cleaned = true;
3641 tx_desc = E1000_TX_DESC(*tx_ring, i);
3642 buffer_info = &tx_ring->buffer_info[i];
3643 skb = buffer_info->skb;
3644
3645 if (skb) {
3646 unsigned int segs, bytecount;
3647 /* gso_segs is currently only valid for tcp */
3648 segs = skb_shinfo(skb)->gso_segs ?: 1;
3649 /* multiply data chunks by size of headers */
3650 bytecount = ((segs - 1) * skb_headlen(skb)) +
3651 skb->len;
3652 total_packets += segs;
3653 total_bytes += bytecount;
3654 }
3655
3656 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3657 tx_desc->upper.data = 0;
3658
3659 i++;
3660 if (i == tx_ring->count)
3661 i = 0;
3662
3663 count++;
3664 if (count == IGB_MAX_TX_CLEAN) {
3665 retval = false;
3666 goto done_cleaning;
3667 }
3668 }
3669 oldhead = head;
3670 rmb();
6d8126f9 3671 head = get_head(tx_ring);
9d5c8243
AK		 3672 if (head == oldhead)
3673 goto done_cleaning;
3674 } /* while (1) */
3675
3676done_cleaning:
3677 tx_ring->next_to_clean = i;
3678
3679 if (unlikely(cleaned &&
3680 netif_carrier_ok(netdev) &&
3681 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3682 /* Make sure that anybody stopping the queue after this
3683 * sees the new next_to_clean.
3684 */
3685 smp_mb();
661086df
PWJ		 3686 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3687 !(test_bit(__IGB_DOWN, &adapter->state))) {
3688 netif_wake_subqueue(netdev, tx_ring->queue_index);
3689 ++adapter->restart_queue;
3690 }
9d5c8243
AK		 3691 }
3692
3693 if (tx_ring->detect_tx_hung) {
3694 /* Detect a transmit hang in hardware, this serializes the
3695 * check with the clearing of time_stamp and movement of i */
3696 tx_ring->detect_tx_hung = false;
3697 if (tx_ring->buffer_info[i].time_stamp &&
3698 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3699 (adapter->tx_timeout_factor * HZ))
3700 && !(rd32(E1000_STATUS) &
3701 E1000_STATUS_TXOFF)) {
3702
3703 tx_desc = E1000_TX_DESC(*tx_ring, i);
3704 /* detected Tx unit hang */
3705 dev_err(&adapter->pdev->dev,
3706 "Detected Tx Unit Hang\n"
2d064c06 3707 " Tx Queue <%d>\n"
9d5c8243
AK		 3708 " TDH <%x>\n"
3709 " TDT <%x>\n"
3710 " next_to_use <%x>\n"
3711 " next_to_clean <%x>\n"
3712 " head (WB) <%x>\n"
3713 "buffer_info[next_to_clean]\n"
3714 " time_stamp <%lx>\n"
3715 " jiffies <%lx>\n"
3716 " desc.status <%x>\n",
2d064c06 3717 tx_ring->queue_index,
9d5c8243
AK		 3718 readl(adapter->hw.hw_addr + tx_ring->head),
3719 readl(adapter->hw.hw_addr + tx_ring->tail),
3720 tx_ring->next_to_use,
3721 tx_ring->next_to_clean,
3722 head,
3723 tx_ring->buffer_info[i].time_stamp,
3724 jiffies,
3725 tx_desc->upper.fields.status);
661086df 3726 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3727 }
3728 }
3729 tx_ring->total_bytes += total_bytes;
3730 tx_ring->total_packets += total_packets;
e21ed353
AD		 3731 tx_ring->tx_stats.bytes += total_bytes;
3732 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3733 adapter->net_stats.tx_bytes += total_bytes;
3734 adapter->net_stats.tx_packets += total_packets;
3735 return retval;
3736}
3737
d3352520
AD		 3738#ifdef CONFIG_IGB_LRO
3739 /**
3740 * igb_get_skb_hdr - helper function for LRO header processing
3741 * @skb: pointer to sk_buff to be added to LRO packet
3742 * @iphdr: pointer to ip header structure
3743 * @tcph: pointer to tcp header structure
3744 * @hdr_flags: pointer to header flags
3745 * @priv: pointer to the receive descriptor for the current sk_buff
3746 **/
3747static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3748 u64 *hdr_flags, void *priv)
3749{
3750 union e1000_adv_rx_desc *rx_desc = priv;
3751 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3752 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3753
3754 /* Verify that this is a valid IPv4 TCP packet */
3755 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3756 E1000_RXDADV_PKTTYPE_TCP))
3757 return -1;
3758
3759 /* Set network headers */
3760 skb_reset_network_header(skb);
3761 skb_set_transport_header(skb, ip_hdrlen(skb));
3762 *iphdr = ip_hdr(skb);
3763 *tcph = tcp_hdr(skb);
3764 *hdr_flags = LRO_IPV4 | LRO_TCP;
3765
3766 return 0;
3767
3768}
3769#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3770
3771/**
3772 * igb_receive_skb - helper function to handle rx indications
d3352520 3773 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3774 * @status: descriptor status field as written by hardware
3775 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3776 * @skb: pointer to sk_buff to be indicated to stack
3777 **/
d3352520
AD		 3778static void igb_receive_skb(struct igb_ring *ring, u8 status,
3779 union e1000_adv_rx_desc * rx_desc,
3780 struct sk_buff *skb)
3781{
3782 struct igb_adapter * adapter = ring->adapter;
3783 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3784
3785#ifdef CONFIG_IGB_LRO
3786 if (adapter->netdev->features & NETIF_F_LRO &&
3787 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3788 if (vlan_extracted)
3789 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3790 adapter->vlgrp,
3791 le16_to_cpu(rx_desc->wb.upper.vlan),
3792 rx_desc);
3793 else
3794 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3795 ring->lro_used = 1;
3796 } else {
3797#endif
3798 if (vlan_extracted)
3799 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3800 le16_to_cpu(rx_desc->wb.upper.vlan));
3801 else
3802
3803 netif_receive_skb(skb);
3804#ifdef CONFIG_IGB_LRO
3805 }
3806#endif
9d5c8243
AK		 3807}
3808
3809
3810static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3811 u32 status_err, struct sk_buff *skb)
3812{
3813 skb->ip_summed = CHECKSUM_NONE;
3814
3815 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3816 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3817 return;
3818 /* TCP/UDP checksum error bit is set */
3819 if (status_err &
3820 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3821 /* let the stack verify checksum errors */
3822 adapter->hw_csum_err++;
3823 return;
3824 }
3825 /* It must be a TCP or UDP packet with a valid checksum */
3826 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3827 skb->ip_summed = CHECKSUM_UNNECESSARY;
3828
3829 adapter->hw_csum_good++;
3830}
3831
3b644cf6
MW		 3832static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3833 int *work_done, int budget)
9d5c8243 3834{
3b644cf6 3835 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3836 struct net_device *netdev = adapter->netdev;
3837 struct pci_dev *pdev = adapter->pdev;
3838 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3839 struct igb_buffer *buffer_info , *next_buffer;
3840 struct sk_buff *skb;
bf36c1a0 3841 unsigned int i;
9d5c8243
AK		 3842 u32 length, hlen, staterr;
3843 bool cleaned = false;
3844 int cleaned_count = 0;
3845 unsigned int total_bytes = 0, total_packets = 0;
3846
3847 i = rx_ring->next_to_clean;
3848 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3850
3851 while (staterr & E1000_RXD_STAT_DD) {
3852 if (*work_done >= budget)
3853 break;
3854 (*work_done)++;
3855 buffer_info = &rx_ring->buffer_info[i];
3856
3857 /* HW will not DMA in data larger than the given buffer, even
3858 * if it parses the (NFS, of course) header to be larger. In
3859 * that case, it fills the header buffer and spills the rest
3860 * into the page.
3861 */
7deb07b1
AV		 3862 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3863 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3864 if (hlen > adapter->rx_ps_hdr_size)
3865 hlen = adapter->rx_ps_hdr_size;
3866
3867 length = le16_to_cpu(rx_desc->wb.upper.length);
3868 cleaned = true;
3869 cleaned_count++;
3870
bf36c1a0
AD		 3871 skb = buffer_info->skb;
3872 prefetch(skb->data - NET_IP_ALIGN);
3873 buffer_info->skb = NULL;
3874 if (!adapter->rx_ps_hdr_size) {
3875 pci_unmap_single(pdev, buffer_info->dma,
3876 adapter->rx_buffer_len +
3877 NET_IP_ALIGN,
3878 PCI_DMA_FROMDEVICE);
3879 skb_put(skb, length);
3880 goto send_up;
9d5c8243
AK		 3881 }
3882
bf36c1a0
AD		 3883 if (!skb_shinfo(skb)->nr_frags) {
3884 pci_unmap_single(pdev, buffer_info->dma,
3885 adapter->rx_ps_hdr_size +
3886 NET_IP_ALIGN,
3887 PCI_DMA_FROMDEVICE);
3888 skb_put(skb, hlen);
3889 }
3890
3891 if (length) {
9d5c8243 3892 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3893 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3894 buffer_info->page_dma = 0;
bf36c1a0
AD		 3895
3896 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3897 buffer_info->page,
3898 buffer_info->page_offset,
3899 length);
3900
3901 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3902 (page_count(buffer_info->page) != 1))
3903 buffer_info->page = NULL;
3904 else
3905 get_page(buffer_info->page);
9d5c8243
AK		 3906
3907 skb->len += length;
3908 skb->data_len += length;
9d5c8243 3909
bf36c1a0 3910 skb->truesize += length;
9d5c8243
AK		 3911 }
3912send_up:
9d5c8243
AK		 3913 i++;
3914 if (i == rx_ring->count)
3915 i = 0;
3916 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3917 prefetch(next_rxd);
3918 next_buffer = &rx_ring->buffer_info[i];
3919
bf36c1a0
AD		 3920 if (!(staterr & E1000_RXD_STAT_EOP)) {
3921 buffer_info->skb = xchg(&next_buffer->skb, skb);
3922 buffer_info->dma = xchg(&next_buffer->dma, 0);
3923 goto next_desc;
3924 }
3925
9d5c8243
AK		 3926 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3927 dev_kfree_skb_irq(skb);
3928 goto next_desc;
3929 }
9d5c8243
AK		 3930
3931 total_bytes += skb->len;
3932 total_packets++;
3933
3934 igb_rx_checksum_adv(adapter, staterr, skb);
3935
3936 skb->protocol = eth_type_trans(skb, netdev);
3937
d3352520 3938 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243
AK		 3939
3940 netdev->last_rx = jiffies;
3941
3942next_desc:
3943 rx_desc->wb.upper.status_error = 0;
3944
3945 /* return some buffers to hardware, one at a time is too slow */
3946 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3947 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3948 cleaned_count = 0;
3949 }
3950
3951 /* use prefetched values */
3952 rx_desc = next_rxd;
3953 buffer_info = next_buffer;
3954
3955 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3956 }
bf36c1a0 3957
9d5c8243
AK		 3958 rx_ring->next_to_clean = i;
3959 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3960
d3352520
AD		 3961#ifdef CONFIG_IGB_LRO
3962 if (rx_ring->lro_used) {
3963 lro_flush_all(&rx_ring->lro_mgr);
3964 rx_ring->lro_used = 0;
3965 }
3966#endif
3967
9d5c8243 3968 if (cleaned_count)
3b644cf6 3969 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3970
3971 rx_ring->total_packets += total_packets;
3972 rx_ring->total_bytes += total_bytes;
3973 rx_ring->rx_stats.packets += total_packets;
3974 rx_ring->rx_stats.bytes += total_bytes;
3975 adapter->net_stats.rx_bytes += total_bytes;
3976 adapter->net_stats.rx_packets += total_packets;
3977 return cleaned;
3978}
3979
3980
3981/**
3982 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3983 * @adapter: address of board private structure
3984 **/
3b644cf6 3985static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3986 int cleaned_count)
3987{
3b644cf6 3988 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3989 struct net_device *netdev = adapter->netdev;
3990 struct pci_dev *pdev = adapter->pdev;
3991 union e1000_adv_rx_desc *rx_desc;
3992 struct igb_buffer *buffer_info;
3993 struct sk_buff *skb;
3994 unsigned int i;
3995
3996 i = rx_ring->next_to_use;
3997 buffer_info = &rx_ring->buffer_info[i];
3998
3999 while (cleaned_count--) {
4000 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4001
bf36c1a0 4002 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4003 if (!buffer_info->page) {
bf36c1a0
AD		 4004 buffer_info->page = alloc_page(GFP_ATOMIC);
4005 if (!buffer_info->page) {
4006 adapter->alloc_rx_buff_failed++;
4007 goto no_buffers;
4008 }
4009 buffer_info->page_offset = 0;
4010 } else {
4011 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4012 }
4013 buffer_info->page_dma =
4014 pci_map_page(pdev,
4015 buffer_info->page,
bf36c1a0
AD		 4016 buffer_info->page_offset,
4017 PAGE_SIZE / 2,
9d5c8243
AK		 4018 PCI_DMA_FROMDEVICE);
4019 }
4020
4021 if (!buffer_info->skb) {
4022 int bufsz;
4023
4024 if (adapter->rx_ps_hdr_size)
4025 bufsz = adapter->rx_ps_hdr_size;
4026 else
4027 bufsz = adapter->rx_buffer_len;
4028 bufsz += NET_IP_ALIGN;
4029 skb = netdev_alloc_skb(netdev, bufsz);
4030
4031 if (!skb) {
4032 adapter->alloc_rx_buff_failed++;
4033 goto no_buffers;
4034 }
4035
4036 /* Make buffer alignment 2 beyond a 16 byte boundary
4037 * this will result in a 16 byte aligned IP header after
4038 * the 14 byte MAC header is removed
4039 */
4040 skb_reserve(skb, NET_IP_ALIGN);
4041
4042 buffer_info->skb = skb;
4043 buffer_info->dma = pci_map_single(pdev, skb->data,
4044 bufsz,
4045 PCI_DMA_FROMDEVICE);
4046
4047 }
4048 /* Refresh the desc even if buffer_addrs didn't change because
4049 * each write-back erases this info. */
4050 if (adapter->rx_ps_hdr_size) {
4051 rx_desc->read.pkt_addr =
4052 cpu_to_le64(buffer_info->page_dma);
4053 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4054 } else {
4055 rx_desc->read.pkt_addr =
4056 cpu_to_le64(buffer_info->dma);
4057 rx_desc->read.hdr_addr = 0;
4058 }
4059
4060 i++;
4061 if (i == rx_ring->count)
4062 i = 0;
4063 buffer_info = &rx_ring->buffer_info[i];
4064 }
4065
4066no_buffers:
4067 if (rx_ring->next_to_use != i) {
4068 rx_ring->next_to_use = i;
4069 if (i == 0)
4070 i = (rx_ring->count - 1);
4071 else
4072 i--;
4073
4074 /* Force memory writes to complete before letting h/w
4075 * know there are new descriptors to fetch. (Only
4076 * applicable for weak-ordered memory model archs,
4077 * such as IA-64). */
4078 wmb();
4079 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4080 }
4081}
4082
4083/**
4084 * igb_mii_ioctl -
4085 * @netdev:
4086 * @ifreq:
4087 * @cmd:
4088 **/
4089static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4090{
4091 struct igb_adapter *adapter = netdev_priv(netdev);
4092 struct mii_ioctl_data *data = if_mii(ifr);
4093
4094 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4095 return -EOPNOTSUPP;
4096
4097 switch (cmd) {
4098 case SIOCGMIIPHY:
4099 data->phy_id = adapter->hw.phy.addr;
4100 break;
4101 case SIOCGMIIREG:
4102 if (!capable(CAP_NET_ADMIN))
4103 return -EPERM;
4104 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4105 data->reg_num
4106 & 0x1F, &data->val_out))
4107 return -EIO;
4108 break;
4109 case SIOCSMIIREG:
4110 default:
4111 return -EOPNOTSUPP;
4112 }
4113 return 0;
4114}
4115
4116/**
4117 * igb_ioctl -
4118 * @netdev:
4119 * @ifreq:
4120 * @cmd:
4121 **/
4122static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4123{
4124 switch (cmd) {
4125 case SIOCGMIIPHY:
4126 case SIOCGMIIREG:
4127 case SIOCSMIIREG:
4128 return igb_mii_ioctl(netdev, ifr, cmd);
4129 default:
4130 return -EOPNOTSUPP;
4131 }
4132}
4133
4134static void igb_vlan_rx_register(struct net_device *netdev,
4135 struct vlan_group *grp)
4136{
4137 struct igb_adapter *adapter = netdev_priv(netdev);
4138 struct e1000_hw *hw = &adapter->hw;
4139 u32 ctrl, rctl;
4140
4141 igb_irq_disable(adapter);
4142 adapter->vlgrp = grp;
4143
4144 if (grp) {
4145 /* enable VLAN tag insert/strip */
4146 ctrl = rd32(E1000_CTRL);
4147 ctrl |= E1000_CTRL_VME;
4148 wr32(E1000_CTRL, ctrl);
4149
4150 /* enable VLAN receive filtering */
4151 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4152 rctl &= ~E1000_RCTL_CFIEN;
4153 wr32(E1000_RCTL, rctl);
4154 igb_update_mng_vlan(adapter);
4155 wr32(E1000_RLPML,
4156 adapter->max_frame_size + VLAN_TAG_SIZE);
4157 } else {
4158 /* disable VLAN tag insert/strip */
4159 ctrl = rd32(E1000_CTRL);
4160 ctrl &= ~E1000_CTRL_VME;
4161 wr32(E1000_CTRL, ctrl);
4162
9d5c8243
AK		 4163 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4164 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4165 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4166 }
4167 wr32(E1000_RLPML,
4168 adapter->max_frame_size);
4169 }
4170
4171 if (!test_bit(__IGB_DOWN, &adapter->state))
4172 igb_irq_enable(adapter);
4173}
4174
4175static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4176{
4177 struct igb_adapter *adapter = netdev_priv(netdev);
4178 struct e1000_hw *hw = &adapter->hw;
4179 u32 vfta, index;
4180
4181 if ((adapter->hw.mng_cookie.status &
4182 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4183 (vid == adapter->mng_vlan_id))
4184 return;
4185 /* add VID to filter table */
4186 index = (vid >> 5) & 0x7F;
4187 vfta = array_rd32(E1000_VFTA, index);
4188 vfta |= (1 << (vid & 0x1F));
4189 igb_write_vfta(&adapter->hw, index, vfta);
4190}
4191
4192static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4193{
4194 struct igb_adapter *adapter = netdev_priv(netdev);
4195 struct e1000_hw *hw = &adapter->hw;
4196 u32 vfta, index;
4197
4198 igb_irq_disable(adapter);
4199 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4200
4201 if (!test_bit(__IGB_DOWN, &adapter->state))
4202 igb_irq_enable(adapter);
4203
4204 if ((adapter->hw.mng_cookie.status &
4205 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4206 (vid == adapter->mng_vlan_id)) {
4207 /* release control to f/w */
4208 igb_release_hw_control(adapter);
4209 return;
4210 }
4211
4212 /* remove VID from filter table */
4213 index = (vid >> 5) & 0x7F;
4214 vfta = array_rd32(E1000_VFTA, index);
4215 vfta &= ~(1 << (vid & 0x1F));
4216 igb_write_vfta(&adapter->hw, index, vfta);
4217}
4218
4219static void igb_restore_vlan(struct igb_adapter *adapter)
4220{
4221 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4222
4223 if (adapter->vlgrp) {
4224 u16 vid;
4225 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4226 if (!vlan_group_get_device(adapter->vlgrp, vid))
4227 continue;
4228 igb_vlan_rx_add_vid(adapter->netdev, vid);
4229 }
4230 }
4231}
4232
4233int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4234{
4235 struct e1000_mac_info *mac = &adapter->hw.mac;
4236
4237 mac->autoneg = 0;
4238
4239 /* Fiber NICs only allow 1000 gbps Full duplex */
4240 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4241 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4242 dev_err(&adapter->pdev->dev,
4243 "Unsupported Speed/Duplex configuration\n");
4244 return -EINVAL;
4245 }
4246
4247 switch (spddplx) {
4248 case SPEED_10 + DUPLEX_HALF:
4249 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4250 break;
4251 case SPEED_10 + DUPLEX_FULL:
4252 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4253 break;
4254 case SPEED_100 + DUPLEX_HALF:
4255 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4256 break;
4257 case SPEED_100 + DUPLEX_FULL:
4258 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4259 break;
4260 case SPEED_1000 + DUPLEX_FULL:
4261 mac->autoneg = 1;
4262 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4263 break;
4264 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4265 default:
4266 dev_err(&adapter->pdev->dev,
4267 "Unsupported Speed/Duplex configuration\n");
4268 return -EINVAL;
4269 }
4270 return 0;
4271}
4272
4273
4274static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4275{
4276 struct net_device *netdev = pci_get_drvdata(pdev);
4277 struct igb_adapter *adapter = netdev_priv(netdev);
4278 struct e1000_hw *hw = &adapter->hw;
2d064c06 4279 u32 ctrl, rctl, status;
9d5c8243
AK		 4280 u32 wufc = adapter->wol;
4281#ifdef CONFIG_PM
4282 int retval = 0;
4283#endif
4284
4285 netif_device_detach(netdev);
4286
a88f10ec
AD		 4287 if (netif_running(netdev))
4288 igb_close(netdev);
4289
4290 igb_reset_interrupt_capability(adapter);
4291
4292 igb_free_queues(adapter);
9d5c8243
AK		 4293
4294#ifdef CONFIG_PM
4295 retval = pci_save_state(pdev);
4296 if (retval)
4297 return retval;
4298#endif
4299
4300 status = rd32(E1000_STATUS);
4301 if (status & E1000_STATUS_LU)
4302 wufc &= ~E1000_WUFC_LNKC;
4303
4304 if (wufc) {
4305 igb_setup_rctl(adapter);
4306 igb_set_multi(netdev);
4307
4308 /* turn on all-multi mode if wake on multicast is enabled */
4309 if (wufc & E1000_WUFC_MC) {
4310 rctl = rd32(E1000_RCTL);
4311 rctl |= E1000_RCTL_MPE;
4312 wr32(E1000_RCTL, rctl);
4313 }
4314
4315 ctrl = rd32(E1000_CTRL);
4316 /* advertise wake from D3Cold */
4317 #define E1000_CTRL_ADVD3WUC 0x00100000
4318 /* phy power management enable */
4319 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4320 ctrl |= E1000_CTRL_ADVD3WUC;
4321 wr32(E1000_CTRL, ctrl);
4322
9d5c8243
AK		 4323 /* Allow time for pending master requests to run */
4324 igb_disable_pcie_master(&adapter->hw);
4325
4326 wr32(E1000_WUC, E1000_WUC_PME_EN);
4327 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4328 } else {
4329 wr32(E1000_WUC, 0);
4330 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4331 }
4332
2d064c06
AD		 4333 /* make sure adapter isn't asleep if manageability/wol is enabled */
4334 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4335 pci_enable_wake(pdev, PCI_D3hot, 1);
4336 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4337 } else {
4338 igb_shutdown_fiber_serdes_link_82575(hw);
4339 pci_enable_wake(pdev, PCI_D3hot, 0);
4340 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4341 }
4342
4343 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4344 * would have already happened in close and is redundant. */
4345 igb_release_hw_control(adapter);
4346
4347 pci_disable_device(pdev);
4348
4349 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4350
4351 return 0;
4352}
4353
4354#ifdef CONFIG_PM
4355static int igb_resume(struct pci_dev *pdev)
4356{
4357 struct net_device *netdev = pci_get_drvdata(pdev);
4358 struct igb_adapter *adapter = netdev_priv(netdev);
4359 struct e1000_hw *hw = &adapter->hw;
4360 u32 err;
4361
4362 pci_set_power_state(pdev, PCI_D0);
4363 pci_restore_state(pdev);
42bfd33a
TI		 4364
4365 if (adapter->need_ioport)
4366 err = pci_enable_device(pdev);
4367 else
4368 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4369 if (err) {
4370 dev_err(&pdev->dev,
4371 "igb: Cannot enable PCI device from suspend\n");
4372 return err;
4373 }
4374 pci_set_master(pdev);
4375
4376 pci_enable_wake(pdev, PCI_D3hot, 0);
4377 pci_enable_wake(pdev, PCI_D3cold, 0);
4378
a88f10ec
AD		 4379 igb_set_interrupt_capability(adapter);
4380
4381 if (igb_alloc_queues(adapter)) {
4382 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4383 return -ENOMEM;
9d5c8243
AK		 4384 }
4385
4386 /* e1000_power_up_phy(adapter); */
4387
4388 igb_reset(adapter);
4389 wr32(E1000_WUS, ~0);
4390
a88f10ec
AD		 4391 if (netif_running(netdev)) {
4392 err = igb_open(netdev);
4393 if (err)
4394 return err;
4395 }
9d5c8243
AK		 4396
4397 netif_device_attach(netdev);
4398
4399 /* let the f/w know that the h/w is now under the control of the
4400 * driver. */
4401 igb_get_hw_control(adapter);
4402
4403 return 0;
4404}
4405#endif
4406
4407static void igb_shutdown(struct pci_dev *pdev)
4408{
4409 igb_suspend(pdev, PMSG_SUSPEND);
4410}
4411
4412#ifdef CONFIG_NET_POLL_CONTROLLER
4413/*
4414 * Polling 'interrupt' - used by things like netconsole to send skbs
4415 * without having to re-enable interrupts. It's not called while
4416 * the interrupt routine is executing.
4417 */
4418static void igb_netpoll(struct net_device *netdev)
4419{
4420 struct igb_adapter *adapter = netdev_priv(netdev);
4421 int i;
4422 int work_done = 0;
4423
4424 igb_irq_disable(adapter);
7dfc16fa
AD		 4425 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4426
9d5c8243 4427 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4428 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4429
4430 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4431 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4432 &work_done,
4433 adapter->rx_ring[i].napi.weight);
4434
7dfc16fa 4435 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4436 igb_irq_enable(adapter);
4437}
4438#endif /* CONFIG_NET_POLL_CONTROLLER */
4439
4440/**
4441 * igb_io_error_detected - called when PCI error is detected
4442 * @pdev: Pointer to PCI device
4443 * @state: The current pci connection state
4444 *
4445 * This function is called after a PCI bus error affecting
4446 * this device has been detected.
4447 */
4448static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4449 pci_channel_state_t state)
4450{
4451 struct net_device *netdev = pci_get_drvdata(pdev);
4452 struct igb_adapter *adapter = netdev_priv(netdev);
4453
4454 netif_device_detach(netdev);
4455
4456 if (netif_running(netdev))
4457 igb_down(adapter);
4458 pci_disable_device(pdev);
4459
4460 /* Request a slot slot reset. */
4461 return PCI_ERS_RESULT_NEED_RESET;
4462}
4463
4464/**
4465 * igb_io_slot_reset - called after the pci bus has been reset.
4466 * @pdev: Pointer to PCI device
4467 *
4468 * Restart the card from scratch, as if from a cold-boot. Implementation
4469 * resembles the first-half of the igb_resume routine.
4470 */
4471static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4472{
4473 struct net_device *netdev = pci_get_drvdata(pdev);
4474 struct igb_adapter *adapter = netdev_priv(netdev);
4475 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4476 int err;
9d5c8243 4477
42bfd33a
TI		 4478 if (adapter->need_ioport)
4479 err = pci_enable_device(pdev);
4480 else
4481 err = pci_enable_device_mem(pdev);
4482 if (err) {
9d5c8243
AK		 4483 dev_err(&pdev->dev,
4484 "Cannot re-enable PCI device after reset.\n");
4485 return PCI_ERS_RESULT_DISCONNECT;
4486 }
4487 pci_set_master(pdev);
c682fc23 4488 pci_restore_state(pdev);
9d5c8243
AK		 4489
4490 pci_enable_wake(pdev, PCI_D3hot, 0);
4491 pci_enable_wake(pdev, PCI_D3cold, 0);
4492
4493 igb_reset(adapter);
4494 wr32(E1000_WUS, ~0);
4495
4496 return PCI_ERS_RESULT_RECOVERED;
4497}
4498
4499/**
4500 * igb_io_resume - called when traffic can start flowing again.
4501 * @pdev: Pointer to PCI device
4502 *
4503 * This callback is called when the error recovery driver tells us that
4504 * its OK to resume normal operation. Implementation resembles the
4505 * second-half of the igb_resume routine.
4506 */
4507static void igb_io_resume(struct pci_dev *pdev)
4508{
4509 struct net_device *netdev = pci_get_drvdata(pdev);
4510 struct igb_adapter *adapter = netdev_priv(netdev);
4511
9d5c8243
AK		 4512 if (netif_running(netdev)) {
4513 if (igb_up(adapter)) {
4514 dev_err(&pdev->dev, "igb_up failed after reset\n");
4515 return;
4516 }
4517 }
4518
4519 netif_device_attach(netdev);
4520
4521 /* let the f/w know that the h/w is now under the control of the
4522 * driver. */
4523 igb_get_hw_control(adapter);
4524
4525}
4526
4527/* igb_main.c */
Linux kernel - Deliverables
This page took 0.301967 seconds and 5 git commands to generate.