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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card. | |
7 | * | |
8 | * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle | |
9 | * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc. | |
10 | * | |
11 | * References: | |
12 | * o IOC3 ASIC specification 4.51, 1996-04-18 | |
13 | * o IEEE 802.3 specification, 2000 edition | |
14 | * o DP38840A Specification, National Semiconductor, March 1997 | |
15 | * | |
16 | * To do: | |
17 | * | |
18 | * o Handle allocation failures in ioc3_alloc_skb() more gracefully. | |
19 | * o Handle allocation failures in ioc3_init_rings(). | |
20 | * o Use prefetching for large packets. What is a good lower limit for | |
21 | * prefetching? | |
22 | * o We're probably allocating a bit too much memory. | |
23 | * o Use hardware checksums. | |
24 | * o Convert to using a IOC3 meta driver. | |
25 | * o Which PHYs might possibly be attached to the IOC3 in real live, | |
26 | * which workarounds are required for them? Do we ever have Lucent's? | |
27 | * o For the 2.5 branch kill the mii-tool ioctls. | |
28 | */ | |
29 | ||
30 | #define IOC3_NAME "ioc3-eth" | |
d5b20697 | 31 | #define IOC3_VERSION "2.6.3-4" |
1da177e4 | 32 | |
1da177e4 LT |
33 | #include <linux/init.h> |
34 | #include <linux/delay.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/mm.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/crc32.h> | |
41 | #include <linux/mii.h> | |
42 | #include <linux/in.h> | |
43 | #include <linux/ip.h> | |
44 | #include <linux/tcp.h> | |
45 | #include <linux/udp.h> | |
910638ae | 46 | #include <linux/dma-mapping.h> |
1da177e4 LT |
47 | |
48 | #ifdef CONFIG_SERIAL_8250 | |
15a93807 RB |
49 | #include <linux/serial_core.h> |
50 | #include <linux/serial_8250.h> | |
0491d1f3 | 51 | #include <linux/serial_reg.h> |
1da177e4 LT |
52 | #endif |
53 | ||
54 | #include <linux/netdevice.h> | |
55 | #include <linux/etherdevice.h> | |
56 | #include <linux/ethtool.h> | |
57 | #include <linux/skbuff.h> | |
58 | #include <net/ip.h> | |
59 | ||
60 | #include <asm/byteorder.h> | |
1da177e4 LT |
61 | #include <asm/io.h> |
62 | #include <asm/pgtable.h> | |
63 | #include <asm/uaccess.h> | |
64 | #include <asm/sn/types.h> | |
65 | #include <asm/sn/sn0/addrs.h> | |
66 | #include <asm/sn/sn0/hubni.h> | |
67 | #include <asm/sn/sn0/hubio.h> | |
68 | #include <asm/sn/klconfig.h> | |
69 | #include <asm/sn/ioc3.h> | |
70 | #include <asm/sn/sn0/ip27.h> | |
71 | #include <asm/pci/bridge.h> | |
72 | ||
73 | /* | |
74 | * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The | |
75 | * value must be a power of two. | |
76 | */ | |
77 | #define RX_BUFFS 64 | |
78 | ||
79 | #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21) | |
80 | #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21) | |
81 | ||
82 | /* Private per NIC data of the driver. */ | |
83 | struct ioc3_private { | |
84 | struct ioc3 *regs; | |
85 | unsigned long *rxr; /* pointer to receiver ring */ | |
86 | struct ioc3_etxd *txr; | |
87 | struct sk_buff *rx_skbs[512]; | |
88 | struct sk_buff *tx_skbs[128]; | |
89 | struct net_device_stats stats; | |
90 | int rx_ci; /* RX consumer index */ | |
91 | int rx_pi; /* RX producer index */ | |
92 | int tx_ci; /* TX consumer index */ | |
93 | int tx_pi; /* TX producer index */ | |
94 | int txqlen; | |
95 | u32 emcr, ehar_h, ehar_l; | |
96 | spinlock_t ioc3_lock; | |
97 | struct mii_if_info mii; | |
98 | struct pci_dev *pdev; | |
99 | ||
100 | /* Members used by autonegotiation */ | |
101 | struct timer_list ioc3_timer; | |
102 | }; | |
103 | ||
104 | static inline struct net_device *priv_netdev(struct ioc3_private *dev) | |
105 | { | |
106 | return (void *)dev - ((sizeof(struct net_device) + 31) & ~31); | |
107 | } | |
108 | ||
109 | static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
110 | static void ioc3_set_multicast_list(struct net_device *dev); | |
111 | static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
112 | static void ioc3_timeout(struct net_device *dev); | |
113 | static inline unsigned int ioc3_hash(const unsigned char *addr); | |
114 | static inline void ioc3_stop(struct ioc3_private *ip); | |
115 | static void ioc3_init(struct net_device *dev); | |
116 | ||
117 | static const char ioc3_str[] = "IOC3 Ethernet"; | |
7282d491 | 118 | static const struct ethtool_ops ioc3_ethtool_ops; |
1da177e4 LT |
119 | |
120 | /* We use this to acquire receive skb's that we can DMA directly into. */ | |
121 | ||
122 | #define IOC3_CACHELINE 128UL | |
123 | ||
124 | static inline unsigned long aligned_rx_skb_addr(unsigned long addr) | |
125 | { | |
126 | return (~addr + 1) & (IOC3_CACHELINE - 1UL); | |
127 | } | |
128 | ||
129 | static inline struct sk_buff * ioc3_alloc_skb(unsigned long length, | |
130 | unsigned int gfp_mask) | |
131 | { | |
132 | struct sk_buff *skb; | |
133 | ||
134 | skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask); | |
135 | if (likely(skb)) { | |
136 | int offset = aligned_rx_skb_addr((unsigned long) skb->data); | |
137 | if (offset) | |
138 | skb_reserve(skb, offset); | |
139 | } | |
140 | ||
141 | return skb; | |
142 | } | |
143 | ||
144 | static inline unsigned long ioc3_map(void *ptr, unsigned long vdev) | |
145 | { | |
146 | #ifdef CONFIG_SGI_IP27 | |
d955d90b | 147 | vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */ |
1da177e4 LT |
148 | |
149 | return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF | | |
150 | ((unsigned long)ptr & TO_PHYS_MASK); | |
151 | #else | |
152 | return virt_to_bus(ptr); | |
153 | #endif | |
154 | } | |
155 | ||
156 | /* BEWARE: The IOC3 documentation documents the size of rx buffers as | |
157 | 1644 while it's actually 1664. This one was nasty to track down ... */ | |
158 | #define RX_OFFSET 10 | |
159 | #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE) | |
160 | ||
161 | /* DMA barrier to separate cached and uncached accesses. */ | |
162 | #define BARRIER() \ | |
163 | __asm__("sync" ::: "memory") | |
164 | ||
165 | ||
166 | #define IOC3_SIZE 0x100000 | |
167 | ||
168 | /* | |
169 | * IOC3 is a big endian device | |
170 | * | |
171 | * Unorthodox but makes the users of these macros more readable - the pointer | |
172 | * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3 | |
173 | * in the environment. | |
174 | */ | |
175 | #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr) | |
176 | #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0) | |
177 | #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0) | |
178 | #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr) | |
179 | #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0) | |
180 | #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr) | |
181 | #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0) | |
182 | #define ioc3_r_eier() be32_to_cpu(ioc3->eier) | |
183 | #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0) | |
184 | #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr) | |
185 | #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0) | |
186 | #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h) | |
187 | #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0) | |
188 | #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l) | |
189 | #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0) | |
190 | #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar) | |
191 | #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0) | |
192 | #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir) | |
193 | #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0) | |
194 | #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir) | |
195 | #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0) | |
196 | #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr) | |
197 | #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0) | |
198 | #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr) | |
199 | #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0) | |
200 | #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr) | |
201 | #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0) | |
202 | #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc) | |
203 | #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0) | |
204 | #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir) | |
205 | #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0) | |
206 | #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h) | |
207 | #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0) | |
208 | #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l) | |
209 | #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0) | |
210 | #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir) | |
211 | #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0) | |
212 | #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir) | |
213 | #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0) | |
214 | #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h) | |
215 | #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0) | |
216 | #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l) | |
217 | #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0) | |
218 | #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h) | |
219 | #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0) | |
220 | #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l) | |
221 | #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0) | |
222 | #define ioc3_r_micr() be32_to_cpu(ioc3->micr) | |
223 | #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0) | |
224 | #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r) | |
225 | #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0) | |
226 | #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w) | |
227 | #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0) | |
228 | ||
229 | static inline u32 mcr_pack(u32 pulse, u32 sample) | |
230 | { | |
231 | return (pulse << 10) | (sample << 2); | |
232 | } | |
233 | ||
234 | static int nic_wait(struct ioc3 *ioc3) | |
235 | { | |
236 | u32 mcr; | |
237 | ||
238 | do { | |
239 | mcr = ioc3_r_mcr(); | |
240 | } while (!(mcr & 2)); | |
241 | ||
242 | return mcr & 1; | |
243 | } | |
244 | ||
245 | static int nic_reset(struct ioc3 *ioc3) | |
246 | { | |
247 | int presence; | |
248 | ||
249 | ioc3_w_mcr(mcr_pack(500, 65)); | |
250 | presence = nic_wait(ioc3); | |
251 | ||
252 | ioc3_w_mcr(mcr_pack(0, 500)); | |
253 | nic_wait(ioc3); | |
254 | ||
255 | return presence; | |
256 | } | |
257 | ||
258 | static inline int nic_read_bit(struct ioc3 *ioc3) | |
259 | { | |
260 | int result; | |
261 | ||
262 | ioc3_w_mcr(mcr_pack(6, 13)); | |
263 | result = nic_wait(ioc3); | |
264 | ioc3_w_mcr(mcr_pack(0, 100)); | |
265 | nic_wait(ioc3); | |
266 | ||
267 | return result; | |
268 | } | |
269 | ||
270 | static inline void nic_write_bit(struct ioc3 *ioc3, int bit) | |
271 | { | |
272 | if (bit) | |
273 | ioc3_w_mcr(mcr_pack(6, 110)); | |
274 | else | |
275 | ioc3_w_mcr(mcr_pack(80, 30)); | |
276 | ||
277 | nic_wait(ioc3); | |
278 | } | |
279 | ||
280 | /* | |
281 | * Read a byte from an iButton device | |
282 | */ | |
283 | static u32 nic_read_byte(struct ioc3 *ioc3) | |
284 | { | |
285 | u32 result = 0; | |
286 | int i; | |
287 | ||
288 | for (i = 0; i < 8; i++) | |
289 | result = (result >> 1) | (nic_read_bit(ioc3) << 7); | |
290 | ||
291 | return result; | |
292 | } | |
293 | ||
294 | /* | |
295 | * Write a byte to an iButton device | |
296 | */ | |
297 | static void nic_write_byte(struct ioc3 *ioc3, int byte) | |
298 | { | |
299 | int i, bit; | |
300 | ||
301 | for (i = 8; i; i--) { | |
302 | bit = byte & 1; | |
303 | byte >>= 1; | |
304 | ||
305 | nic_write_bit(ioc3, bit); | |
306 | } | |
307 | } | |
308 | ||
309 | static u64 nic_find(struct ioc3 *ioc3, int *last) | |
310 | { | |
311 | int a, b, index, disc; | |
312 | u64 address = 0; | |
313 | ||
314 | nic_reset(ioc3); | |
315 | /* Search ROM. */ | |
316 | nic_write_byte(ioc3, 0xf0); | |
317 | ||
318 | /* Algorithm from ``Book of iButton Standards''. */ | |
319 | for (index = 0, disc = 0; index < 64; index++) { | |
320 | a = nic_read_bit(ioc3); | |
321 | b = nic_read_bit(ioc3); | |
322 | ||
323 | if (a && b) { | |
324 | printk("NIC search failed (not fatal).\n"); | |
325 | *last = 0; | |
326 | return 0; | |
327 | } | |
328 | ||
329 | if (!a && !b) { | |
330 | if (index == *last) { | |
331 | address |= 1UL << index; | |
332 | } else if (index > *last) { | |
333 | address &= ~(1UL << index); | |
334 | disc = index; | |
335 | } else if ((address & (1UL << index)) == 0) | |
336 | disc = index; | |
337 | nic_write_bit(ioc3, address & (1UL << index)); | |
338 | continue; | |
339 | } else { | |
340 | if (a) | |
341 | address |= 1UL << index; | |
342 | else | |
343 | address &= ~(1UL << index); | |
344 | nic_write_bit(ioc3, a); | |
345 | continue; | |
346 | } | |
347 | } | |
348 | ||
349 | *last = disc; | |
350 | ||
351 | return address; | |
352 | } | |
353 | ||
354 | static int nic_init(struct ioc3 *ioc3) | |
355 | { | |
f49343a5 AC |
356 | const char *unknown = "unknown"; |
357 | const char *type = unknown; | |
1da177e4 LT |
358 | u8 crc; |
359 | u8 serial[6]; | |
360 | int save = 0, i; | |
361 | ||
1da177e4 LT |
362 | while (1) { |
363 | u64 reg; | |
364 | reg = nic_find(ioc3, &save); | |
365 | ||
366 | switch (reg & 0xff) { | |
367 | case 0x91: | |
368 | type = "DS1981U"; | |
369 | break; | |
370 | default: | |
371 | if (save == 0) { | |
372 | /* Let the caller try again. */ | |
373 | return -1; | |
374 | } | |
375 | continue; | |
376 | } | |
377 | ||
378 | nic_reset(ioc3); | |
379 | ||
380 | /* Match ROM. */ | |
381 | nic_write_byte(ioc3, 0x55); | |
382 | for (i = 0; i < 8; i++) | |
383 | nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff); | |
384 | ||
385 | reg >>= 8; /* Shift out type. */ | |
386 | for (i = 0; i < 6; i++) { | |
387 | serial[i] = reg & 0xff; | |
388 | reg >>= 8; | |
389 | } | |
390 | crc = reg & 0xff; | |
391 | break; | |
392 | } | |
393 | ||
394 | printk("Found %s NIC", type); | |
f49343a5 | 395 | if (type != unknown) { |
1da177e4 LT |
396 | printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x," |
397 | " CRC %02x", serial[0], serial[1], serial[2], | |
398 | serial[3], serial[4], serial[5], crc); | |
399 | } | |
400 | printk(".\n"); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | /* | |
406 | * Read the NIC (Number-In-a-Can) device used to store the MAC address on | |
407 | * SN0 / SN00 nodeboards and PCI cards. | |
408 | */ | |
409 | static void ioc3_get_eaddr_nic(struct ioc3_private *ip) | |
410 | { | |
411 | struct ioc3 *ioc3 = ip->regs; | |
412 | u8 nic[14]; | |
413 | int tries = 2; /* There may be some problem with the battery? */ | |
414 | int i; | |
415 | ||
416 | ioc3_w_gpcr_s(1 << 21); | |
417 | ||
418 | while (tries--) { | |
419 | if (!nic_init(ioc3)) | |
420 | break; | |
421 | udelay(500); | |
422 | } | |
423 | ||
424 | if (tries < 0) { | |
425 | printk("Failed to read MAC address\n"); | |
426 | return; | |
427 | } | |
428 | ||
429 | /* Read Memory. */ | |
430 | nic_write_byte(ioc3, 0xf0); | |
431 | nic_write_byte(ioc3, 0x00); | |
432 | nic_write_byte(ioc3, 0x00); | |
433 | ||
434 | for (i = 13; i >= 0; i--) | |
435 | nic[i] = nic_read_byte(ioc3); | |
436 | ||
437 | for (i = 2; i < 8; i++) | |
438 | priv_netdev(ip)->dev_addr[i - 2] = nic[i]; | |
439 | } | |
440 | ||
441 | /* | |
442 | * Ok, this is hosed by design. It's necessary to know what machine the | |
443 | * NIC is in in order to know how to read the NIC address. We also have | |
444 | * to know if it's a PCI card or a NIC in on the node board ... | |
445 | */ | |
446 | static void ioc3_get_eaddr(struct ioc3_private *ip) | |
447 | { | |
448 | int i; | |
449 | ||
450 | ||
451 | ioc3_get_eaddr_nic(ip); | |
452 | ||
453 | printk("Ethernet address is "); | |
454 | for (i = 0; i < 6; i++) { | |
455 | printk("%02x", priv_netdev(ip)->dev_addr[i]); | |
456 | if (i < 5) | |
457 | printk(":"); | |
458 | } | |
459 | printk(".\n"); | |
460 | } | |
461 | ||
462 | static void __ioc3_set_mac_address(struct net_device *dev) | |
463 | { | |
464 | struct ioc3_private *ip = netdev_priv(dev); | |
465 | struct ioc3 *ioc3 = ip->regs; | |
466 | ||
467 | ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]); | |
468 | ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | | |
469 | (dev->dev_addr[1] << 8) | dev->dev_addr[0]); | |
470 | } | |
471 | ||
472 | static int ioc3_set_mac_address(struct net_device *dev, void *addr) | |
473 | { | |
474 | struct ioc3_private *ip = netdev_priv(dev); | |
475 | struct sockaddr *sa = addr; | |
476 | ||
477 | memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); | |
478 | ||
479 | spin_lock_irq(&ip->ioc3_lock); | |
480 | __ioc3_set_mac_address(dev); | |
481 | spin_unlock_irq(&ip->ioc3_lock); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | /* | |
487 | * Caller must hold the ioc3_lock ever for MII readers. This is also | |
488 | * used to protect the transmitter side but it's low contention. | |
489 | */ | |
490 | static int ioc3_mdio_read(struct net_device *dev, int phy, int reg) | |
491 | { | |
492 | struct ioc3_private *ip = netdev_priv(dev); | |
493 | struct ioc3 *ioc3 = ip->regs; | |
494 | ||
495 | while (ioc3_r_micr() & MICR_BUSY); | |
496 | ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG); | |
497 | while (ioc3_r_micr() & MICR_BUSY); | |
498 | ||
852ea22a | 499 | return ioc3_r_midr_r() & MIDR_DATA_MASK; |
1da177e4 LT |
500 | } |
501 | ||
502 | static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) | |
503 | { | |
504 | struct ioc3_private *ip = netdev_priv(dev); | |
505 | struct ioc3 *ioc3 = ip->regs; | |
506 | ||
507 | while (ioc3_r_micr() & MICR_BUSY); | |
508 | ioc3_w_midr_w(data); | |
509 | ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg); | |
510 | while (ioc3_r_micr() & MICR_BUSY); | |
511 | } | |
512 | ||
513 | static int ioc3_mii_init(struct ioc3_private *ip); | |
514 | ||
515 | static struct net_device_stats *ioc3_get_stats(struct net_device *dev) | |
516 | { | |
517 | struct ioc3_private *ip = netdev_priv(dev); | |
518 | struct ioc3 *ioc3 = ip->regs; | |
519 | ||
520 | ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK); | |
521 | return &ip->stats; | |
522 | } | |
523 | ||
524 | #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM | |
525 | ||
526 | static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len) | |
527 | { | |
528 | struct ethhdr *eh = eth_hdr(skb); | |
529 | uint32_t csum, ehsum; | |
530 | unsigned int proto; | |
531 | struct iphdr *ih; | |
532 | uint16_t *ew; | |
533 | unsigned char *cp; | |
534 | ||
535 | /* | |
536 | * Did hardware handle the checksum at all? The cases we can handle | |
537 | * are: | |
538 | * | |
539 | * - TCP and UDP checksums of IPv4 only. | |
540 | * - IPv6 would be doable but we keep that for later ... | |
541 | * - Only unfragmented packets. Did somebody already tell you | |
542 | * fragmentation is evil? | |
543 | * - don't care about packet size. Worst case when processing a | |
544 | * malformed packet we'll try to access the packet at ip header + | |
545 | * 64 bytes which is still inside the skb. Even in the unlikely | |
546 | * case where the checksum is right the higher layers will still | |
547 | * drop the packet as appropriate. | |
548 | */ | |
549 | if (eh->h_proto != ntohs(ETH_P_IP)) | |
550 | return; | |
551 | ||
552 | ih = (struct iphdr *) ((char *)eh + ETH_HLEN); | |
553 | if (ih->frag_off & htons(IP_MF | IP_OFFSET)) | |
554 | return; | |
555 | ||
556 | proto = ih->protocol; | |
557 | if (proto != IPPROTO_TCP && proto != IPPROTO_UDP) | |
558 | return; | |
559 | ||
560 | /* Same as tx - compute csum of pseudo header */ | |
561 | csum = hwsum + | |
562 | (ih->tot_len - (ih->ihl << 2)) + | |
563 | htons((uint16_t)ih->protocol) + | |
564 | (ih->saddr >> 16) + (ih->saddr & 0xffff) + | |
565 | (ih->daddr >> 16) + (ih->daddr & 0xffff); | |
566 | ||
567 | /* Sum up ethernet dest addr, src addr and protocol */ | |
568 | ew = (uint16_t *) eh; | |
569 | ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6]; | |
570 | ||
571 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
572 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
573 | ||
574 | csum += 0xffff ^ ehsum; | |
575 | ||
576 | /* In the next step we also subtract the 1's complement | |
577 | checksum of the trailing ethernet CRC. */ | |
578 | cp = (char *)eh + len; /* points at trailing CRC */ | |
579 | if (len & 1) { | |
580 | csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]); | |
581 | csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]); | |
582 | } else { | |
583 | csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]); | |
584 | csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]); | |
585 | } | |
586 | ||
587 | csum = (csum & 0xffff) + (csum >> 16); | |
588 | csum = (csum & 0xffff) + (csum >> 16); | |
589 | ||
590 | if (csum == 0xffff) | |
591 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
592 | } | |
593 | #endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */ | |
594 | ||
595 | static inline void ioc3_rx(struct ioc3_private *ip) | |
596 | { | |
597 | struct sk_buff *skb, *new_skb; | |
598 | struct ioc3 *ioc3 = ip->regs; | |
599 | int rx_entry, n_entry, len; | |
600 | struct ioc3_erxbuf *rxb; | |
601 | unsigned long *rxr; | |
602 | u32 w0, err; | |
603 | ||
604 | rxr = (unsigned long *) ip->rxr; /* Ring base */ | |
605 | rx_entry = ip->rx_ci; /* RX consume index */ | |
606 | n_entry = ip->rx_pi; | |
607 | ||
608 | skb = ip->rx_skbs[rx_entry]; | |
609 | rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET); | |
610 | w0 = be32_to_cpu(rxb->w0); | |
611 | ||
612 | while (w0 & ERXBUF_V) { | |
613 | err = be32_to_cpu(rxb->err); /* It's valid ... */ | |
614 | if (err & ERXBUF_GOODPKT) { | |
615 | len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4; | |
616 | skb_trim(skb, len); | |
617 | skb->protocol = eth_type_trans(skb, priv_netdev(ip)); | |
618 | ||
619 | new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); | |
620 | if (!new_skb) { | |
621 | /* Ouch, drop packet and just recycle packet | |
622 | to keep the ring filled. */ | |
623 | ip->stats.rx_dropped++; | |
624 | new_skb = skb; | |
625 | goto next; | |
626 | } | |
627 | ||
628 | #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM | |
629 | ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len); | |
630 | #endif | |
631 | ||
632 | netif_rx(skb); | |
633 | ||
634 | ip->rx_skbs[rx_entry] = NULL; /* Poison */ | |
635 | ||
1da177e4 LT |
636 | /* Because we reserve afterwards. */ |
637 | skb_put(new_skb, (1664 + RX_OFFSET)); | |
638 | rxb = (struct ioc3_erxbuf *) new_skb->data; | |
639 | skb_reserve(new_skb, RX_OFFSET); | |
640 | ||
641 | priv_netdev(ip)->last_rx = jiffies; | |
642 | ip->stats.rx_packets++; /* Statistics */ | |
643 | ip->stats.rx_bytes += len; | |
644 | } else { | |
645 | /* The frame is invalid and the skb never | |
646 | reached the network layer so we can just | |
647 | recycle it. */ | |
648 | new_skb = skb; | |
649 | ip->stats.rx_errors++; | |
650 | } | |
651 | if (err & ERXBUF_CRCERR) /* Statistics */ | |
652 | ip->stats.rx_crc_errors++; | |
653 | if (err & ERXBUF_FRAMERR) | |
654 | ip->stats.rx_frame_errors++; | |
655 | next: | |
656 | ip->rx_skbs[n_entry] = new_skb; | |
657 | rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1)); | |
658 | rxb->w0 = 0; /* Clear valid flag */ | |
659 | n_entry = (n_entry + 1) & 511; /* Update erpir */ | |
660 | ||
661 | /* Now go on to the next ring entry. */ | |
662 | rx_entry = (rx_entry + 1) & 511; | |
663 | skb = ip->rx_skbs[rx_entry]; | |
664 | rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET); | |
665 | w0 = be32_to_cpu(rxb->w0); | |
666 | } | |
667 | ioc3_w_erpir((n_entry << 3) | ERPIR_ARM); | |
668 | ip->rx_pi = n_entry; | |
669 | ip->rx_ci = rx_entry; | |
670 | } | |
671 | ||
672 | static inline void ioc3_tx(struct ioc3_private *ip) | |
673 | { | |
674 | unsigned long packets, bytes; | |
675 | struct ioc3 *ioc3 = ip->regs; | |
676 | int tx_entry, o_entry; | |
677 | struct sk_buff *skb; | |
678 | u32 etcir; | |
679 | ||
680 | spin_lock(&ip->ioc3_lock); | |
681 | etcir = ioc3_r_etcir(); | |
682 | ||
683 | tx_entry = (etcir >> 7) & 127; | |
684 | o_entry = ip->tx_ci; | |
685 | packets = 0; | |
686 | bytes = 0; | |
687 | ||
688 | while (o_entry != tx_entry) { | |
689 | packets++; | |
690 | skb = ip->tx_skbs[o_entry]; | |
691 | bytes += skb->len; | |
692 | dev_kfree_skb_irq(skb); | |
693 | ip->tx_skbs[o_entry] = NULL; | |
694 | ||
695 | o_entry = (o_entry + 1) & 127; /* Next */ | |
696 | ||
697 | etcir = ioc3_r_etcir(); /* More pkts sent? */ | |
698 | tx_entry = (etcir >> 7) & 127; | |
699 | } | |
700 | ||
701 | ip->stats.tx_packets += packets; | |
702 | ip->stats.tx_bytes += bytes; | |
703 | ip->txqlen -= packets; | |
704 | ||
705 | if (ip->txqlen < 128) | |
706 | netif_wake_queue(priv_netdev(ip)); | |
707 | ||
708 | ip->tx_ci = o_entry; | |
709 | spin_unlock(&ip->ioc3_lock); | |
710 | } | |
711 | ||
712 | /* | |
713 | * Deal with fatal IOC3 errors. This condition might be caused by a hard or | |
714 | * software problems, so we should try to recover | |
715 | * more gracefully if this ever happens. In theory we might be flooded | |
716 | * with such error interrupts if something really goes wrong, so we might | |
717 | * also consider to take the interface down. | |
718 | */ | |
719 | static void ioc3_error(struct ioc3_private *ip, u32 eisr) | |
720 | { | |
721 | struct net_device *dev = priv_netdev(ip); | |
722 | unsigned char *iface = dev->name; | |
723 | ||
724 | spin_lock(&ip->ioc3_lock); | |
725 | ||
726 | if (eisr & EISR_RXOFLO) | |
727 | printk(KERN_ERR "%s: RX overflow.\n", iface); | |
728 | if (eisr & EISR_RXBUFOFLO) | |
729 | printk(KERN_ERR "%s: RX buffer overflow.\n", iface); | |
730 | if (eisr & EISR_RXMEMERR) | |
731 | printk(KERN_ERR "%s: RX PCI error.\n", iface); | |
732 | if (eisr & EISR_RXPARERR) | |
733 | printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface); | |
734 | if (eisr & EISR_TXBUFUFLO) | |
735 | printk(KERN_ERR "%s: TX buffer underflow.\n", iface); | |
736 | if (eisr & EISR_TXMEMERR) | |
737 | printk(KERN_ERR "%s: TX PCI error.\n", iface); | |
738 | ||
739 | ioc3_stop(ip); | |
740 | ioc3_init(dev); | |
741 | ioc3_mii_init(ip); | |
742 | ||
743 | netif_wake_queue(dev); | |
744 | ||
745 | spin_unlock(&ip->ioc3_lock); | |
746 | } | |
747 | ||
748 | /* The interrupt handler does all of the Rx thread work and cleans up | |
749 | after the Tx thread. */ | |
7d12e780 | 750 | static irqreturn_t ioc3_interrupt(int irq, void *_dev) |
1da177e4 LT |
751 | { |
752 | struct net_device *dev = (struct net_device *)_dev; | |
753 | struct ioc3_private *ip = netdev_priv(dev); | |
754 | struct ioc3 *ioc3 = ip->regs; | |
755 | const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | | |
756 | EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | | |
757 | EISR_TXEXPLICIT | EISR_TXMEMERR; | |
758 | u32 eisr; | |
759 | ||
760 | eisr = ioc3_r_eisr() & enabled; | |
761 | ||
762 | ioc3_w_eisr(eisr); | |
763 | (void) ioc3_r_eisr(); /* Flush */ | |
764 | ||
765 | if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR | | |
766 | EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR)) | |
767 | ioc3_error(ip, eisr); | |
768 | if (eisr & EISR_RXTIMERINT) | |
769 | ioc3_rx(ip); | |
770 | if (eisr & EISR_TXEXPLICIT) | |
771 | ioc3_tx(ip); | |
772 | ||
773 | return IRQ_HANDLED; | |
774 | } | |
775 | ||
776 | static inline void ioc3_setup_duplex(struct ioc3_private *ip) | |
777 | { | |
778 | struct ioc3 *ioc3 = ip->regs; | |
779 | ||
780 | if (ip->mii.full_duplex) { | |
781 | ioc3_w_etcsr(ETCSR_FD); | |
782 | ip->emcr |= EMCR_DUPLEX; | |
783 | } else { | |
784 | ioc3_w_etcsr(ETCSR_HD); | |
785 | ip->emcr &= ~EMCR_DUPLEX; | |
786 | } | |
787 | ioc3_w_emcr(ip->emcr); | |
788 | } | |
789 | ||
790 | static void ioc3_timer(unsigned long data) | |
791 | { | |
792 | struct ioc3_private *ip = (struct ioc3_private *) data; | |
793 | ||
794 | /* Print the link status if it has changed */ | |
795 | mii_check_media(&ip->mii, 1, 0); | |
796 | ioc3_setup_duplex(ip); | |
797 | ||
798 | ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */ | |
799 | add_timer(&ip->ioc3_timer); | |
800 | } | |
801 | ||
802 | /* | |
803 | * Try to find a PHY. There is no apparent relation between the MII addresses | |
804 | * in the SGI documentation and what we find in reality, so we simply probe | |
805 | * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my | |
806 | * onboard IOC3s has the special oddity that probing doesn't seem to find it | |
807 | * yet the interface seems to work fine, so if probing fails we for now will | |
808 | * simply default to PHY 31 instead of bailing out. | |
809 | */ | |
810 | static int ioc3_mii_init(struct ioc3_private *ip) | |
811 | { | |
812 | struct net_device *dev = priv_netdev(ip); | |
813 | int i, found = 0, res = 0; | |
814 | int ioc3_phy_workaround = 1; | |
815 | u16 word; | |
816 | ||
817 | for (i = 0; i < 32; i++) { | |
818 | word = ioc3_mdio_read(dev, i, MII_PHYSID1); | |
819 | ||
820 | if (word != 0xffff && word != 0x0000) { | |
821 | found = 1; | |
822 | break; /* Found a PHY */ | |
823 | } | |
824 | } | |
825 | ||
826 | if (!found) { | |
827 | if (ioc3_phy_workaround) | |
828 | i = 31; | |
829 | else { | |
830 | ip->mii.phy_id = -1; | |
831 | res = -ENODEV; | |
832 | goto out; | |
833 | } | |
834 | } | |
835 | ||
836 | ip->mii.phy_id = i; | |
f0ba7358 RB |
837 | |
838 | out: | |
839 | return res; | |
840 | } | |
841 | ||
842 | static void ioc3_mii_start(struct ioc3_private *ip) | |
843 | { | |
1da177e4 LT |
844 | ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */ |
845 | ip->ioc3_timer.data = (unsigned long) ip; | |
846 | ip->ioc3_timer.function = &ioc3_timer; | |
847 | add_timer(&ip->ioc3_timer); | |
1da177e4 LT |
848 | } |
849 | ||
850 | static inline void ioc3_clean_rx_ring(struct ioc3_private *ip) | |
851 | { | |
852 | struct sk_buff *skb; | |
853 | int i; | |
854 | ||
855 | for (i = ip->rx_ci; i & 15; i++) { | |
856 | ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci]; | |
857 | ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++]; | |
858 | } | |
859 | ip->rx_pi &= 511; | |
860 | ip->rx_ci &= 511; | |
861 | ||
862 | for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) { | |
863 | struct ioc3_erxbuf *rxb; | |
864 | skb = ip->rx_skbs[i]; | |
865 | rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET); | |
866 | rxb->w0 = 0; | |
867 | } | |
868 | } | |
869 | ||
870 | static inline void ioc3_clean_tx_ring(struct ioc3_private *ip) | |
871 | { | |
872 | struct sk_buff *skb; | |
873 | int i; | |
874 | ||
875 | for (i=0; i < 128; i++) { | |
876 | skb = ip->tx_skbs[i]; | |
877 | if (skb) { | |
878 | ip->tx_skbs[i] = NULL; | |
879 | dev_kfree_skb_any(skb); | |
880 | } | |
881 | ip->txr[i].cmd = 0; | |
882 | } | |
883 | ip->tx_pi = 0; | |
884 | ip->tx_ci = 0; | |
885 | } | |
886 | ||
887 | static void ioc3_free_rings(struct ioc3_private *ip) | |
888 | { | |
889 | struct sk_buff *skb; | |
890 | int rx_entry, n_entry; | |
891 | ||
892 | if (ip->txr) { | |
893 | ioc3_clean_tx_ring(ip); | |
894 | free_pages((unsigned long)ip->txr, 2); | |
895 | ip->txr = NULL; | |
896 | } | |
897 | ||
898 | if (ip->rxr) { | |
899 | n_entry = ip->rx_ci; | |
900 | rx_entry = ip->rx_pi; | |
901 | ||
902 | while (n_entry != rx_entry) { | |
903 | skb = ip->rx_skbs[n_entry]; | |
904 | if (skb) | |
905 | dev_kfree_skb_any(skb); | |
906 | ||
907 | n_entry = (n_entry + 1) & 511; | |
908 | } | |
909 | free_page((unsigned long)ip->rxr); | |
910 | ip->rxr = NULL; | |
911 | } | |
912 | } | |
913 | ||
914 | static void ioc3_alloc_rings(struct net_device *dev) | |
915 | { | |
916 | struct ioc3_private *ip = netdev_priv(dev); | |
917 | struct ioc3_erxbuf *rxb; | |
918 | unsigned long *rxr; | |
919 | int i; | |
920 | ||
921 | if (ip->rxr == NULL) { | |
922 | /* Allocate and initialize rx ring. 4kb = 512 entries */ | |
923 | ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC); | |
924 | rxr = (unsigned long *) ip->rxr; | |
925 | if (!rxr) | |
926 | printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n"); | |
927 | ||
928 | /* Now the rx buffers. The RX ring may be larger but | |
929 | we only allocate 16 buffers for now. Need to tune | |
930 | this for performance and memory later. */ | |
931 | for (i = 0; i < RX_BUFFS; i++) { | |
932 | struct sk_buff *skb; | |
933 | ||
934 | skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); | |
935 | if (!skb) { | |
936 | show_free_areas(); | |
937 | continue; | |
938 | } | |
939 | ||
940 | ip->rx_skbs[i] = skb; | |
1da177e4 LT |
941 | |
942 | /* Because we reserve afterwards. */ | |
943 | skb_put(skb, (1664 + RX_OFFSET)); | |
944 | rxb = (struct ioc3_erxbuf *) skb->data; | |
945 | rxr[i] = cpu_to_be64(ioc3_map(rxb, 1)); | |
946 | skb_reserve(skb, RX_OFFSET); | |
947 | } | |
948 | ip->rx_ci = 0; | |
949 | ip->rx_pi = RX_BUFFS; | |
950 | } | |
951 | ||
952 | if (ip->txr == NULL) { | |
953 | /* Allocate and initialize tx rings. 16kb = 128 bufs. */ | |
954 | ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2); | |
955 | if (!ip->txr) | |
956 | printk("ioc3_alloc_rings(): __get_free_pages() failed!\n"); | |
957 | ip->tx_pi = 0; | |
958 | ip->tx_ci = 0; | |
959 | } | |
960 | } | |
961 | ||
962 | static void ioc3_init_rings(struct net_device *dev) | |
963 | { | |
964 | struct ioc3_private *ip = netdev_priv(dev); | |
965 | struct ioc3 *ioc3 = ip->regs; | |
966 | unsigned long ring; | |
967 | ||
968 | ioc3_free_rings(ip); | |
969 | ioc3_alloc_rings(dev); | |
970 | ||
971 | ioc3_clean_rx_ring(ip); | |
972 | ioc3_clean_tx_ring(ip); | |
973 | ||
974 | /* Now the rx ring base, consume & produce registers. */ | |
975 | ring = ioc3_map(ip->rxr, 0); | |
976 | ioc3_w_erbr_h(ring >> 32); | |
977 | ioc3_w_erbr_l(ring & 0xffffffff); | |
978 | ioc3_w_ercir(ip->rx_ci << 3); | |
979 | ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM); | |
980 | ||
981 | ring = ioc3_map(ip->txr, 0); | |
982 | ||
983 | ip->txqlen = 0; /* nothing queued */ | |
984 | ||
985 | /* Now the tx ring base, consume & produce registers. */ | |
986 | ioc3_w_etbr_h(ring >> 32); | |
987 | ioc3_w_etbr_l(ring & 0xffffffff); | |
988 | ioc3_w_etpir(ip->tx_pi << 7); | |
989 | ioc3_w_etcir(ip->tx_ci << 7); | |
990 | (void) ioc3_r_etcir(); /* Flush */ | |
991 | } | |
992 | ||
993 | static inline void ioc3_ssram_disc(struct ioc3_private *ip) | |
994 | { | |
995 | struct ioc3 *ioc3 = ip->regs; | |
996 | volatile u32 *ssram0 = &ioc3->ssram[0x0000]; | |
997 | volatile u32 *ssram1 = &ioc3->ssram[0x4000]; | |
998 | unsigned int pattern = 0x5555; | |
999 | ||
1000 | /* Assume the larger size SSRAM and enable parity checking */ | |
1001 | ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR)); | |
1002 | ||
1003 | *ssram0 = pattern; | |
1004 | *ssram1 = ~pattern & IOC3_SSRAM_DM; | |
1005 | ||
1006 | if ((*ssram0 & IOC3_SSRAM_DM) != pattern || | |
1007 | (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) { | |
1008 | /* set ssram size to 64 KB */ | |
1009 | ip->emcr = EMCR_RAMPAR; | |
1010 | ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ); | |
1011 | } else | |
1012 | ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR; | |
1013 | } | |
1014 | ||
1015 | static void ioc3_init(struct net_device *dev) | |
1016 | { | |
1017 | struct ioc3_private *ip = netdev_priv(dev); | |
1018 | struct ioc3 *ioc3 = ip->regs; | |
1019 | ||
cfadbd29 | 1020 | del_timer_sync(&ip->ioc3_timer); /* Kill if running */ |
1da177e4 LT |
1021 | |
1022 | ioc3_w_emcr(EMCR_RST); /* Reset */ | |
1023 | (void) ioc3_r_emcr(); /* Flush WB */ | |
1024 | udelay(4); /* Give it time ... */ | |
1025 | ioc3_w_emcr(0); | |
1026 | (void) ioc3_r_emcr(); | |
1027 | ||
1028 | /* Misc registers */ | |
1029 | #ifdef CONFIG_SGI_IP27 | |
1030 | ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */ | |
1031 | #else | |
1032 | ioc3_w_erbar(0); /* Let PCI API get it right */ | |
1033 | #endif | |
1034 | (void) ioc3_r_etcdc(); /* Clear on read */ | |
1035 | ioc3_w_ercsr(15); /* RX low watermark */ | |
1036 | ioc3_w_ertr(0); /* Interrupt immediately */ | |
1037 | __ioc3_set_mac_address(dev); | |
1038 | ioc3_w_ehar_h(ip->ehar_h); | |
1039 | ioc3_w_ehar_l(ip->ehar_l); | |
1040 | ioc3_w_ersr(42); /* XXX should be random */ | |
1041 | ||
1042 | ioc3_init_rings(dev); | |
1043 | ||
1044 | ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN | | |
1045 | EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN; | |
1046 | ioc3_w_emcr(ip->emcr); | |
1047 | ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | | |
1048 | EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | | |
1049 | EISR_TXEXPLICIT | EISR_TXMEMERR); | |
1050 | (void) ioc3_r_eier(); | |
1051 | } | |
1052 | ||
1053 | static inline void ioc3_stop(struct ioc3_private *ip) | |
1054 | { | |
1055 | struct ioc3 *ioc3 = ip->regs; | |
1056 | ||
1057 | ioc3_w_emcr(0); /* Shutup */ | |
1058 | ioc3_w_eier(0); /* Disable interrupts */ | |
1059 | (void) ioc3_r_eier(); /* Flush */ | |
1060 | } | |
1061 | ||
1062 | static int ioc3_open(struct net_device *dev) | |
1063 | { | |
1064 | struct ioc3_private *ip = netdev_priv(dev); | |
1065 | ||
1fb9df5d | 1066 | if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) { |
1da177e4 LT |
1067 | printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq); |
1068 | ||
1069 | return -EAGAIN; | |
1070 | } | |
1071 | ||
1072 | ip->ehar_h = 0; | |
1073 | ip->ehar_l = 0; | |
1074 | ioc3_init(dev); | |
f0ba7358 | 1075 | ioc3_mii_start(ip); |
1da177e4 LT |
1076 | |
1077 | netif_start_queue(dev); | |
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | static int ioc3_close(struct net_device *dev) | |
1082 | { | |
1083 | struct ioc3_private *ip = netdev_priv(dev); | |
1084 | ||
cfadbd29 | 1085 | del_timer_sync(&ip->ioc3_timer); |
1da177e4 LT |
1086 | |
1087 | netif_stop_queue(dev); | |
1088 | ||
1089 | ioc3_stop(ip); | |
1090 | free_irq(dev->irq, dev); | |
1091 | ||
1092 | ioc3_free_rings(ip); | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | /* | |
1097 | * MENET cards have four IOC3 chips, which are attached to two sets of | |
1098 | * PCI slot resources each: the primary connections are on slots | |
1099 | * 0..3 and the secondaries are on 4..7 | |
1100 | * | |
1101 | * All four ethernets are brought out to connectors; six serial ports | |
1102 | * (a pair from each of the first three IOC3s) are brought out to | |
1103 | * MiniDINs; all other subdevices are left swinging in the wind, leave | |
1104 | * them disabled. | |
1105 | */ | |
f49343a5 AC |
1106 | |
1107 | static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot) | |
1108 | { | |
1109 | struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0)); | |
1110 | int ret = 0; | |
1111 | ||
1112 | if (dev) { | |
1113 | if (dev->vendor == PCI_VENDOR_ID_SGI && | |
1114 | dev->device == PCI_DEVICE_ID_SGI_IOC3) | |
1115 | ret = 1; | |
1116 | pci_dev_put(dev); | |
1117 | } | |
1118 | ||
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | static int ioc3_is_menet(struct pci_dev *pdev) | |
1da177e4 | 1123 | { |
f49343a5 AC |
1124 | return pdev->bus->parent == NULL && |
1125 | ioc3_adjacent_is_ioc3(pdev, 0) && | |
1126 | ioc3_adjacent_is_ioc3(pdev, 1) && | |
1127 | ioc3_adjacent_is_ioc3(pdev, 2); | |
1da177e4 LT |
1128 | } |
1129 | ||
1130 | #ifdef CONFIG_SERIAL_8250 | |
1131 | /* | |
1132 | * Note about serial ports and consoles: | |
1133 | * For console output, everyone uses the IOC3 UARTA (offset 0x178) | |
1134 | * connected to the master node (look in ip27_setup_console() and | |
1135 | * ip27prom_console_write()). | |
1136 | * | |
1137 | * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port | |
1138 | * addresses on a partitioned machine. Since we currently use the ioc3 | |
1139 | * serial ports, we use dynamic serial port discovery that the serial.c | |
1140 | * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 | |
1141 | * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater | |
1142 | * than UARTB's, although UARTA on o200s has traditionally been known as | |
1143 | * port 0. So, we just use one serial port from each ioc3 (since the | |
1144 | * serial driver adds addresses to get to higher ports). | |
1145 | * | |
1146 | * The first one to do a register_console becomes the preferred console | |
1147 | * (if there is no kernel command line console= directive). /dev/console | |
1148 | * (ie 5, 1) is then "aliased" into the device number returned by the | |
1149 | * "device" routine referred to in this console structure | |
1150 | * (ip27prom_console_dev). | |
1151 | * | |
1152 | * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working | |
1153 | * around ioc3 oddities in this respect. | |
1154 | * | |
0491d1f3 RB |
1155 | * The IOC3 serials use a 22MHz clock rate with an additional divider which |
1156 | * can be programmed in the SCR register if the DLAB bit is set. | |
1157 | * | |
1158 | * Register to interrupt zero because we share the interrupt with | |
1159 | * the serial driver which we don't properly support yet. | |
1160 | * | |
1161 | * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been | |
1162 | * registered. | |
1da177e4 | 1163 | */ |
0491d1f3 RB |
1164 | static void __devinit ioc3_8250_register(struct ioc3_uartregs __iomem *uart) |
1165 | { | |
1166 | #define COSMISC_CONSTANT 6 | |
1167 | ||
1168 | struct uart_port port = { | |
1169 | .irq = 0, | |
1170 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | |
1171 | .iotype = UPIO_MEM, | |
1172 | .regshift = 0, | |
1173 | .uartclk = (22000000 << 1) / COSMISC_CONSTANT, | |
1174 | ||
1175 | .membase = (unsigned char __iomem *) uart, | |
1176 | .mapbase = (unsigned long) uart, | |
1177 | }; | |
1178 | unsigned char lcr; | |
1179 | ||
1180 | lcr = uart->iu_lcr; | |
1181 | uart->iu_lcr = lcr | UART_LCR_DLAB; | |
1182 | uart->iu_scr = COSMISC_CONSTANT, | |
1183 | uart->iu_lcr = lcr; | |
1184 | uart->iu_lcr; | |
1185 | serial8250_register_port(&port); | |
1186 | } | |
1da177e4 LT |
1187 | |
1188 | static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3) | |
1189 | { | |
1da177e4 LT |
1190 | /* |
1191 | * We need to recognice and treat the fourth MENET serial as it | |
1192 | * does not have an SuperIO chip attached to it, therefore attempting | |
1193 | * to access it will result in bus errors. We call something an | |
1194 | * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3 | |
1195 | * in it. This is paranoid but we want to avoid blowing up on a | |
1196 | * showhorn PCI box that happens to have 4 IOC3 cards in it so it's | |
1197 | * not paranoid enough ... | |
1198 | */ | |
1199 | if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3) | |
1200 | return; | |
1201 | ||
15a93807 | 1202 | /* |
0491d1f3 RB |
1203 | * Switch IOC3 to PIO mode. It probably already was but let's be |
1204 | * paranoid | |
15a93807 | 1205 | */ |
0491d1f3 RB |
1206 | ioc3->gpcr_s = GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL; |
1207 | ioc3->gpcr_s; | |
1208 | ioc3->gppr_6 = 0; | |
1209 | ioc3->gppr_6; | |
1210 | ioc3->gppr_7 = 0; | |
1211 | ioc3->gppr_7; | |
1212 | ioc3->sscr_a = ioc3->sscr_a & ~SSCR_DMA_EN; | |
1213 | ioc3->sscr_a; | |
1214 | ioc3->sscr_b = ioc3->sscr_b & ~SSCR_DMA_EN; | |
1215 | ioc3->sscr_b; | |
1216 | /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */ | |
1217 | ioc3->sio_iec &= ~ (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | | |
1218 | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | | |
1219 | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | | |
1220 | SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR); | |
1221 | ioc3->sio_iec |= SIO_IR_SA_INT; | |
1222 | ioc3->sscr_a = 0; | |
1223 | ioc3->sio_iec &= ~ (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | | |
1224 | SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | | |
1225 | SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | | |
1226 | SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR); | |
1227 | ioc3->sio_iec |= SIO_IR_SB_INT; | |
1228 | ioc3->sscr_b = 0; | |
1229 | ||
1230 | ioc3_8250_register(&ioc3->sregs.uarta); | |
1231 | ioc3_8250_register(&ioc3->sregs.uartb); | |
1da177e4 LT |
1232 | } |
1233 | #endif | |
1234 | ||
1235 | static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1236 | { | |
1237 | unsigned int sw_physid1, sw_physid2; | |
1238 | struct net_device *dev = NULL; | |
1239 | struct ioc3_private *ip; | |
1240 | struct ioc3 *ioc3; | |
1241 | unsigned long ioc3_base, ioc3_size; | |
1242 | u32 vendor, model, rev; | |
1243 | int err, pci_using_dac; | |
1244 | ||
1245 | /* Configure DMA attributes. */ | |
910638ae | 1246 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); |
1da177e4 LT |
1247 | if (!err) { |
1248 | pci_using_dac = 1; | |
910638ae | 1249 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
1da177e4 LT |
1250 | if (err < 0) { |
1251 | printk(KERN_ERR "%s: Unable to obtain 64 bit DMA " | |
1252 | "for consistent allocations\n", pci_name(pdev)); | |
1253 | goto out; | |
1254 | } | |
1255 | } else { | |
910638ae | 1256 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
1da177e4 LT |
1257 | if (err) { |
1258 | printk(KERN_ERR "%s: No usable DMA configuration, " | |
1259 | "aborting.\n", pci_name(pdev)); | |
1260 | goto out; | |
1261 | } | |
1262 | pci_using_dac = 0; | |
1263 | } | |
1264 | ||
1265 | if (pci_enable_device(pdev)) | |
1266 | return -ENODEV; | |
1267 | ||
1268 | dev = alloc_etherdev(sizeof(struct ioc3_private)); | |
1269 | if (!dev) { | |
1270 | err = -ENOMEM; | |
1271 | goto out_disable; | |
1272 | } | |
1273 | ||
1274 | if (pci_using_dac) | |
1275 | dev->features |= NETIF_F_HIGHDMA; | |
1276 | ||
1277 | err = pci_request_regions(pdev, "ioc3"); | |
1278 | if (err) | |
1279 | goto out_free; | |
1280 | ||
1281 | SET_MODULE_OWNER(dev); | |
1282 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1283 | ||
1284 | ip = netdev_priv(dev); | |
1285 | ||
1286 | dev->irq = pdev->irq; | |
1287 | ||
1288 | ioc3_base = pci_resource_start(pdev, 0); | |
1289 | ioc3_size = pci_resource_len(pdev, 0); | |
1290 | ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size); | |
1291 | if (!ioc3) { | |
1292 | printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n", | |
1293 | pci_name(pdev)); | |
1294 | err = -ENOMEM; | |
1295 | goto out_res; | |
1296 | } | |
1297 | ip->regs = ioc3; | |
1298 | ||
1299 | #ifdef CONFIG_SERIAL_8250 | |
1300 | ioc3_serial_probe(pdev, ioc3); | |
1301 | #endif | |
1302 | ||
1303 | spin_lock_init(&ip->ioc3_lock); | |
1304 | init_timer(&ip->ioc3_timer); | |
1305 | ||
1306 | ioc3_stop(ip); | |
1307 | ioc3_init(dev); | |
1308 | ||
1309 | ip->pdev = pdev; | |
1310 | ||
1311 | ip->mii.phy_id_mask = 0x1f; | |
1312 | ip->mii.reg_num_mask = 0x1f; | |
1313 | ip->mii.dev = dev; | |
1314 | ip->mii.mdio_read = ioc3_mdio_read; | |
1315 | ip->mii.mdio_write = ioc3_mdio_write; | |
1316 | ||
1317 | ioc3_mii_init(ip); | |
1318 | ||
1319 | if (ip->mii.phy_id == -1) { | |
1320 | printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n", | |
1321 | pci_name(pdev)); | |
1322 | err = -ENODEV; | |
1323 | goto out_stop; | |
1324 | } | |
1325 | ||
f0ba7358 | 1326 | ioc3_mii_start(ip); |
1da177e4 LT |
1327 | ioc3_ssram_disc(ip); |
1328 | ioc3_get_eaddr(ip); | |
1329 | ||
1330 | /* The IOC3-specific entries in the device structure. */ | |
1331 | dev->open = ioc3_open; | |
1332 | dev->hard_start_xmit = ioc3_start_xmit; | |
1333 | dev->tx_timeout = ioc3_timeout; | |
1334 | dev->watchdog_timeo = 5 * HZ; | |
1335 | dev->stop = ioc3_close; | |
1336 | dev->get_stats = ioc3_get_stats; | |
1337 | dev->do_ioctl = ioc3_ioctl; | |
1338 | dev->set_multicast_list = ioc3_set_multicast_list; | |
1339 | dev->set_mac_address = ioc3_set_mac_address; | |
1340 | dev->ethtool_ops = &ioc3_ethtool_ops; | |
1341 | #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM | |
1342 | dev->features = NETIF_F_IP_CSUM; | |
1343 | #endif | |
1344 | ||
1da177e4 LT |
1345 | sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); |
1346 | sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2); | |
1347 | ||
1348 | err = register_netdev(dev); | |
1349 | if (err) | |
1350 | goto out_stop; | |
1351 | ||
1352 | mii_check_media(&ip->mii, 1, 1); | |
852ea22a | 1353 | ioc3_setup_duplex(ip); |
1da177e4 LT |
1354 | |
1355 | vendor = (sw_physid1 << 12) | (sw_physid2 >> 4); | |
1356 | model = (sw_physid2 >> 4) & 0x3f; | |
1357 | rev = sw_physid2 & 0xf; | |
1358 | printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, " | |
1359 | "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev); | |
1360 | printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name, | |
1361 | ip->emcr & EMCR_BUFSIZ ? 128 : 64); | |
1362 | ||
1363 | return 0; | |
1364 | ||
1365 | out_stop: | |
1366 | ioc3_stop(ip); | |
f0ba7358 | 1367 | del_timer_sync(&ip->ioc3_timer); |
1da177e4 LT |
1368 | ioc3_free_rings(ip); |
1369 | out_res: | |
1370 | pci_release_regions(pdev); | |
1371 | out_free: | |
1372 | free_netdev(dev); | |
1373 | out_disable: | |
1374 | /* | |
1375 | * We should call pci_disable_device(pdev); here if the IOC3 wasn't | |
1376 | * such a weird device ... | |
1377 | */ | |
1378 | out: | |
1379 | return err; | |
1380 | } | |
1381 | ||
1382 | static void __devexit ioc3_remove_one (struct pci_dev *pdev) | |
1383 | { | |
1384 | struct net_device *dev = pci_get_drvdata(pdev); | |
1385 | struct ioc3_private *ip = netdev_priv(dev); | |
1386 | struct ioc3 *ioc3 = ip->regs; | |
1387 | ||
1388 | unregister_netdev(dev); | |
f0ba7358 RB |
1389 | del_timer_sync(&ip->ioc3_timer); |
1390 | ||
1da177e4 LT |
1391 | iounmap(ioc3); |
1392 | pci_release_regions(pdev); | |
1393 | free_netdev(dev); | |
1394 | /* | |
1395 | * We should call pci_disable_device(pdev); here if the IOC3 wasn't | |
1396 | * such a weird device ... | |
1397 | */ | |
1398 | } | |
1399 | ||
1400 | static struct pci_device_id ioc3_pci_tbl[] = { | |
1401 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID }, | |
1402 | { 0 } | |
1403 | }; | |
1404 | MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl); | |
1405 | ||
1406 | static struct pci_driver ioc3_driver = { | |
1407 | .name = "ioc3-eth", | |
1408 | .id_table = ioc3_pci_tbl, | |
1409 | .probe = ioc3_probe, | |
1410 | .remove = __devexit_p(ioc3_remove_one), | |
1411 | }; | |
1412 | ||
1413 | static int __init ioc3_init_module(void) | |
1414 | { | |
70f1e002 | 1415 | return pci_register_driver(&ioc3_driver); |
1da177e4 LT |
1416 | } |
1417 | ||
1418 | static void __exit ioc3_cleanup_module(void) | |
1419 | { | |
1420 | pci_unregister_driver(&ioc3_driver); | |
1421 | } | |
1422 | ||
1423 | static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1424 | { | |
1425 | unsigned long data; | |
1426 | struct ioc3_private *ip = netdev_priv(dev); | |
1427 | struct ioc3 *ioc3 = ip->regs; | |
1428 | unsigned int len; | |
1429 | struct ioc3_etxd *desc; | |
1430 | uint32_t w0 = 0; | |
1431 | int produce; | |
1432 | ||
1433 | #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM | |
1434 | /* | |
1435 | * IOC3 has a fairly simple minded checksumming hardware which simply | |
1436 | * adds up the 1's complement checksum for the entire packet and | |
1437 | * inserts it at an offset which can be specified in the descriptor | |
1438 | * into the transmit packet. This means we have to compensate for the | |
1439 | * MAC header which should not be summed and the TCP/UDP pseudo headers | |
1440 | * manually. | |
1441 | */ | |
84fa7933 | 1442 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 ACM |
1443 | const struct iphdr *ih = ip_hdr(skb); |
1444 | const int proto = ntohs(ih->protocol); | |
1da177e4 | 1445 | unsigned int csoff; |
1da177e4 LT |
1446 | uint32_t csum, ehsum; |
1447 | uint16_t *eh; | |
1448 | ||
1449 | /* The MAC header. skb->mac seem the logic approach | |
1450 | to find the MAC header - except it's a NULL pointer ... */ | |
1451 | eh = (uint16_t *) skb->data; | |
1452 | ||
1453 | /* Sum up dest addr, src addr and protocol */ | |
1454 | ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6]; | |
1455 | ||
1456 | /* Fold ehsum. can't use csum_fold which negates also ... */ | |
1457 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
1458 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
1459 | ||
1460 | /* Skip IP header; it's sum is always zero and was | |
1461 | already filled in by ip_output.c */ | |
1462 | csum = csum_tcpudp_nofold(ih->saddr, ih->daddr, | |
1463 | ih->tot_len - (ih->ihl << 2), | |
1464 | proto, 0xffff ^ ehsum); | |
1465 | ||
1466 | csum = (csum & 0xffff) + (csum >> 16); /* Fold again */ | |
1467 | csum = (csum & 0xffff) + (csum >> 16); | |
1468 | ||
1469 | csoff = ETH_HLEN + (ih->ihl << 2); | |
1470 | if (proto == IPPROTO_UDP) { | |
1471 | csoff += offsetof(struct udphdr, check); | |
4bedb452 | 1472 | udp_hdr(skb)->check = csum; |
1da177e4 LT |
1473 | } |
1474 | if (proto == IPPROTO_TCP) { | |
1475 | csoff += offsetof(struct tcphdr, check); | |
aa8223c7 | 1476 | tcp_hdr(skb)->check = csum; |
1da177e4 LT |
1477 | } |
1478 | ||
1479 | w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT); | |
1480 | } | |
1481 | #endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */ | |
1482 | ||
1483 | spin_lock_irq(&ip->ioc3_lock); | |
1484 | ||
1485 | data = (unsigned long) skb->data; | |
1486 | len = skb->len; | |
1487 | ||
1488 | produce = ip->tx_pi; | |
1489 | desc = &ip->txr[produce]; | |
1490 | ||
1491 | if (len <= 104) { | |
1492 | /* Short packet, let's copy it directly into the ring. */ | |
d626f62b | 1493 | skb_copy_from_linear_data(skb, desc->data, skb->len); |
1da177e4 LT |
1494 | if (len < ETH_ZLEN) { |
1495 | /* Very short packet, pad with zeros at the end. */ | |
1496 | memset(desc->data + len, 0, ETH_ZLEN - len); | |
1497 | len = ETH_ZLEN; | |
1498 | } | |
1499 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0); | |
1500 | desc->bufcnt = cpu_to_be32(len); | |
1501 | } else if ((data ^ (data + len - 1)) & 0x4000) { | |
1502 | unsigned long b2 = (data | 0x3fffUL) + 1UL; | |
1503 | unsigned long s1 = b2 - data; | |
1504 | unsigned long s2 = data + len - b2; | |
1505 | ||
1506 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | | |
1507 | ETXD_B1V | ETXD_B2V | w0); | |
1508 | desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) | | |
1509 | (s2 << ETXD_B2CNT_SHIFT)); | |
1510 | desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1)); | |
1511 | desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1)); | |
1512 | } else { | |
1513 | /* Normal sized packet that doesn't cross a page boundary. */ | |
1514 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0); | |
1515 | desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT); | |
1516 | desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1)); | |
1517 | } | |
1518 | ||
1519 | BARRIER(); | |
1520 | ||
1521 | dev->trans_start = jiffies; | |
1522 | ip->tx_skbs[produce] = skb; /* Remember skb */ | |
1523 | produce = (produce + 1) & 127; | |
1524 | ip->tx_pi = produce; | |
1525 | ioc3_w_etpir(produce << 7); /* Fire ... */ | |
1526 | ||
1527 | ip->txqlen++; | |
1528 | ||
1529 | if (ip->txqlen >= 127) | |
1530 | netif_stop_queue(dev); | |
1531 | ||
1532 | spin_unlock_irq(&ip->ioc3_lock); | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | static void ioc3_timeout(struct net_device *dev) | |
1538 | { | |
1539 | struct ioc3_private *ip = netdev_priv(dev); | |
1540 | ||
1541 | printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); | |
1542 | ||
1543 | spin_lock_irq(&ip->ioc3_lock); | |
1544 | ||
1545 | ioc3_stop(ip); | |
1546 | ioc3_init(dev); | |
1547 | ioc3_mii_init(ip); | |
f0ba7358 | 1548 | ioc3_mii_start(ip); |
1da177e4 LT |
1549 | |
1550 | spin_unlock_irq(&ip->ioc3_lock); | |
1551 | ||
1552 | netif_wake_queue(dev); | |
1553 | } | |
1554 | ||
1555 | /* | |
1556 | * Given a multicast ethernet address, this routine calculates the | |
1557 | * address's bit index in the logical address filter mask | |
1558 | */ | |
1559 | ||
1560 | static inline unsigned int ioc3_hash(const unsigned char *addr) | |
1561 | { | |
1562 | unsigned int temp = 0; | |
1563 | u32 crc; | |
1564 | int bits; | |
1565 | ||
1566 | crc = ether_crc_le(ETH_ALEN, addr); | |
1567 | ||
1568 | crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */ | |
1569 | for (bits = 6; --bits >= 0; ) { | |
1570 | temp <<= 1; | |
1571 | temp |= (crc & 0x1); | |
1572 | crc >>= 1; | |
1573 | } | |
1574 | ||
1575 | return temp; | |
1576 | } | |
1577 | ||
1578 | static void ioc3_get_drvinfo (struct net_device *dev, | |
1579 | struct ethtool_drvinfo *info) | |
1580 | { | |
1581 | struct ioc3_private *ip = netdev_priv(dev); | |
852ea22a | 1582 | |
1da177e4 LT |
1583 | strcpy (info->driver, IOC3_NAME); |
1584 | strcpy (info->version, IOC3_VERSION); | |
1585 | strcpy (info->bus_info, pci_name(ip->pdev)); | |
1586 | } | |
1587 | ||
1588 | static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1589 | { | |
1590 | struct ioc3_private *ip = netdev_priv(dev); | |
1591 | int rc; | |
1592 | ||
1593 | spin_lock_irq(&ip->ioc3_lock); | |
1594 | rc = mii_ethtool_gset(&ip->mii, cmd); | |
1595 | spin_unlock_irq(&ip->ioc3_lock); | |
1596 | ||
1597 | return rc; | |
1598 | } | |
1599 | ||
1600 | static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1601 | { | |
1602 | struct ioc3_private *ip = netdev_priv(dev); | |
1603 | int rc; | |
1604 | ||
1605 | spin_lock_irq(&ip->ioc3_lock); | |
1606 | rc = mii_ethtool_sset(&ip->mii, cmd); | |
1607 | spin_unlock_irq(&ip->ioc3_lock); | |
852ea22a | 1608 | |
1da177e4 LT |
1609 | return rc; |
1610 | } | |
1611 | ||
1612 | static int ioc3_nway_reset(struct net_device *dev) | |
1613 | { | |
1614 | struct ioc3_private *ip = netdev_priv(dev); | |
1615 | int rc; | |
1616 | ||
1617 | spin_lock_irq(&ip->ioc3_lock); | |
1618 | rc = mii_nway_restart(&ip->mii); | |
1619 | spin_unlock_irq(&ip->ioc3_lock); | |
1620 | ||
1621 | return rc; | |
1622 | } | |
1623 | ||
1624 | static u32 ioc3_get_link(struct net_device *dev) | |
1625 | { | |
1626 | struct ioc3_private *ip = netdev_priv(dev); | |
1627 | int rc; | |
1628 | ||
1629 | spin_lock_irq(&ip->ioc3_lock); | |
1630 | rc = mii_link_ok(&ip->mii); | |
1631 | spin_unlock_irq(&ip->ioc3_lock); | |
1632 | ||
1633 | return rc; | |
1634 | } | |
1635 | ||
7282d491 | 1636 | static const struct ethtool_ops ioc3_ethtool_ops = { |
1da177e4 LT |
1637 | .get_drvinfo = ioc3_get_drvinfo, |
1638 | .get_settings = ioc3_get_settings, | |
1639 | .set_settings = ioc3_set_settings, | |
1640 | .nway_reset = ioc3_nway_reset, | |
1641 | .get_link = ioc3_get_link, | |
1642 | }; | |
1643 | ||
1644 | static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1645 | { | |
1646 | struct ioc3_private *ip = netdev_priv(dev); | |
1647 | int rc; | |
1648 | ||
1649 | spin_lock_irq(&ip->ioc3_lock); | |
1650 | rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL); | |
1651 | spin_unlock_irq(&ip->ioc3_lock); | |
1652 | ||
1653 | return rc; | |
1654 | } | |
1655 | ||
1656 | static void ioc3_set_multicast_list(struct net_device *dev) | |
1657 | { | |
1658 | struct dev_mc_list *dmi = dev->mc_list; | |
1659 | struct ioc3_private *ip = netdev_priv(dev); | |
1660 | struct ioc3 *ioc3 = ip->regs; | |
1661 | u64 ehar = 0; | |
1662 | int i; | |
1663 | ||
1664 | netif_stop_queue(dev); /* Lock out others. */ | |
1665 | ||
1666 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 LT |
1667 | ip->emcr |= EMCR_PROMISC; |
1668 | ioc3_w_emcr(ip->emcr); | |
1669 | (void) ioc3_r_emcr(); | |
1670 | } else { | |
1671 | ip->emcr &= ~EMCR_PROMISC; | |
1672 | ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */ | |
1673 | (void) ioc3_r_emcr(); | |
1674 | ||
1675 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) { | |
1676 | /* Too many for hashing to make sense or we want all | |
1677 | multicast packets anyway, so skip computing all the | |
1678 | hashes and just accept all packets. */ | |
1679 | ip->ehar_h = 0xffffffff; | |
1680 | ip->ehar_l = 0xffffffff; | |
1681 | } else { | |
1682 | for (i = 0; i < dev->mc_count; i++) { | |
1683 | char *addr = dmi->dmi_addr; | |
1684 | dmi = dmi->next; | |
1685 | ||
1686 | if (!(*addr & 1)) | |
1687 | continue; | |
1688 | ||
1689 | ehar |= (1UL << ioc3_hash(addr)); | |
1690 | } | |
1691 | ip->ehar_h = ehar >> 32; | |
1692 | ip->ehar_l = ehar & 0xffffffff; | |
1693 | } | |
1694 | ioc3_w_ehar_h(ip->ehar_h); | |
1695 | ioc3_w_ehar_l(ip->ehar_l); | |
1696 | } | |
1697 | ||
1698 | netif_wake_queue(dev); /* Let us get going again. */ | |
1699 | } | |
1700 | ||
1701 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | |
1702 | MODULE_DESCRIPTION("SGI IOC3 Ethernet driver"); | |
1703 | MODULE_LICENSE("GPL"); | |
1704 | ||
1705 | module_init(ioc3_init_module); | |
1706 | module_exit(ioc3_cleanup_module); |