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ipg: remove commented out code
[deliverable/linux.git] / drivers / net / ipg.c
CommitLineData
1202d6ff
FR		 1/*
2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3 *
4 * Copyright (C) 2003, 2007 IC Plus Corp
5 *
6 * Original Author:
7 *
8 * Craig Rich
9 * Sundance Technology, Inc.
10 * www.sundanceti.com
11 * craig_rich@sundanceti.com
12 *
13 * Current Maintainer:
14 *
15 * Sorbica Shieh.
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
18 *
19 * Jesse Huang
20 * http://www.icplus.com.tw
21 * jesse@icplus.com.tw
22 */
23#include <linux/crc32.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/mutex.h>
27
1dad939d 28#include <asm/div64.h>
29
1202d6ff
FR		 30#define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31#define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32#define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35 IPG_AC_AUTO_INIT)
36
37#define ipg_w32(val32,reg) iowrite32((val32), ioaddr + (reg))
38#define ipg_w16(val16,reg) iowrite16((val16), ioaddr + (reg))
39#define ipg_w8(val8,reg) iowrite8((val8), ioaddr + (reg))
40
41#define ipg_r32(reg) ioread32(ioaddr + (reg))
42#define ipg_r16(reg) ioread16(ioaddr + (reg))
43#define ipg_r8(reg) ioread8(ioaddr + (reg))
44
45#define JUMBO_FRAME_4k_ONLY
46enum {
47 netdev_io_size = 128
48};
49
50#include "ipg.h"
51#define DRV_NAME "ipg"
52
53MODULE_AUTHOR("IC Plus Corp. 2003");
1662e4b7 54MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
1202d6ff
FR		 55MODULE_LICENSE("GPL");
56
96fd74b2
AB		 57//variable record -- index by leading revision/length
58//Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
59static unsigned short DefaultPhyParam[] = {
60 // 11/12/03 IP1000A v1-3 rev=0x40
61 /*--------------------------------------------------------------------------
62 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
63 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
64 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
65 --------------------------------------------------------------------------*/
66 // 12/17/03 IP1000A v1-4 rev=0x40
67 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
68 0x0000,
69 30, 0x005e, 9, 0x0700,
70 // 01/09/04 IP1000A v1-5 rev=0x41
71 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
72 0x0000,
73 30, 0x005e, 9, 0x0700,
74 0x0000
75};
76
1202d6ff
FR		 77static const char *ipg_brand_name[] = {
78 "IC PLUS IP1000 1000/100/10 based NIC",
79 "Sundance Technology ST2021 based NIC",
80 "Tamarack Microelectronics TC9020/9021 based NIC",
81 "Tamarack Microelectronics TC9020/9021 based NIC",
82 "D-Link NIC",
83 "D-Link NIC IP1000A"
84};
85
86static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
87 { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
88 { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
89 { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
90 { PCI_VDEVICE(DLINK, 0x9021), 3 },
91 { PCI_VDEVICE(DLINK, 0x4000), 4 },
92 { PCI_VDEVICE(DLINK, 0x4020), 5 },
93 { 0, }
94};
95
96MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
97
98static inline void __iomem *ipg_ioaddr(struct net_device *dev)
99{
100 struct ipg_nic_private *sp = netdev_priv(dev);
101 return sp->ioaddr;
102}
103
104#ifdef IPG_DEBUG
105static void ipg_dump_rfdlist(struct net_device *dev)
106{
107 struct ipg_nic_private *sp = netdev_priv(dev);
108 void __iomem *ioaddr = sp->ioaddr;
109 unsigned int i;
110 u32 offset;
111
112 IPG_DEBUG_MSG("_dump_rfdlist\n");
113
114 printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
115 printk(KERN_INFO "rx_dirty = %2.2x\n", sp->rx_dirty);
116 printk(KERN_INFO "RFDList start address = %16.16lx\n",
117 (unsigned long) sp->rxd_map);
118 printk(KERN_INFO "RFDListPtr register = %8.8x%8.8x\n",
119 ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
120
121 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
122 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
123 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
124 offset, (unsigned long) sp->rxd[i].next_desc);
125 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
126 printk(KERN_INFO "%2.2x %4.4x RFS = %16.16lx\n", i,
127 offset, (unsigned long) sp->rxd[i].rfs);
128 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
129 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
130 offset, (unsigned long) sp->rxd[i].frag_info);
131 }
132}
133
134static void ipg_dump_tfdlist(struct net_device *dev)
135{
136 struct ipg_nic_private *sp = netdev_priv(dev);
137 void __iomem *ioaddr = sp->ioaddr;
138 unsigned int i;
139 u32 offset;
140
141 IPG_DEBUG_MSG("_dump_tfdlist\n");
142
143 printk(KERN_INFO "tx_current = %2.2x\n", sp->tx_current);
144 printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
145 printk(KERN_INFO "TFDList start address = %16.16lx\n",
146 (unsigned long) sp->txd_map);
147 printk(KERN_INFO "TFDListPtr register = %8.8x%8.8x\n",
148 ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
149
150 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
151 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
152 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
153 offset, (unsigned long) sp->txd[i].next_desc);
154
155 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
156 printk(KERN_INFO "%2.2x %4.4x TFC = %16.16lx\n", i,
157 offset, (unsigned long) sp->txd[i].tfc);
158 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
159 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
160 offset, (unsigned long) sp->txd[i].frag_info);
161 }
162}
163#endif
164
165static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
166{
167 ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
168 ndelay(IPG_PC_PHYCTRLWAIT_NS);
169}
170
171static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
172{
173 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
174 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
175}
176
177static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
178{
179 phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
180
181 ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
182}
183
184static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
185{
186 ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
187 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
188}
189
190static u16 read_phy_bit(void __iomem * ioaddr, u8 phyctrlpolarity)
191{
192 u16 bit_data;
193
194 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
195
196 bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
197
198 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
199
200 return bit_data;
201}
202
203/*
204 * Read a register from the Physical Layer device located
205 * on the IPG NIC, using the IPG PHYCTRL register.
206 */
207static int mdio_read(struct net_device * dev, int phy_id, int phy_reg)
208{
209 void __iomem *ioaddr = ipg_ioaddr(dev);
210 /*
211 * The GMII mangement frame structure for a read is as follows:
212 *
213 * |Preamble|st|op|phyad|regad|ta| data |idle|
214 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
215 *
216 * <32 1s> = 32 consecutive logic 1 values
217 * A = bit of Physical Layer device address (MSB first)
218 * R = bit of register address (MSB first)
219 * z = High impedance state
220 * D = bit of read data (MSB first)
221 *
222 * Transmission order is 'Preamble' field first, bits transmitted
223 * left to right (first to last).
224 */
225 struct {
226 u32 field;
227 unsigned int len;
228 } p[] = {
229 { GMII_PREAMBLE, 32 }, /* Preamble */
230 { GMII_ST, 2 }, /* ST */
231 { GMII_READ, 2 }, /* OP */
232 { phy_id, 5 }, /* PHYAD */
233 { phy_reg, 5 }, /* REGAD */
234 { 0x0000, 2 }, /* TA */
235 { 0x0000, 16 }, /* DATA */
236 { 0x0000, 1 } /* IDLE */
237 };
238 unsigned int i, j;
239 u8 polarity, data;
240
241 polarity = ipg_r8(PHY_CTRL);
242 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
243
244 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
245 for (j = 0; j < 5; j++) {
246 for (i = 0; i < p[j].len; i++) {
247 /* For each variable length field, the MSB must be
248 * transmitted first. Rotate through the field bits,
249 * starting with the MSB, and move each bit into the
250 * the 1st (2^1) bit position (this is the bit position
251 * corresponding to the MgmtData bit of the PhyCtrl
252 * register for the IPG).
253 *
254 * Example: ST = 01;
255 *
256 * First write a '0' to bit 1 of the PhyCtrl
257 * register, then write a '1' to bit 1 of the
258 * PhyCtrl register.
259 *
260 * To do this, right shift the MSB of ST by the value:
261 * [field length - 1 - #ST bits already written]
262 * then left shift this result by 1.
263 */
264 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
265 data &= IPG_PC_MGMTDATA;
266 data |= polarity | IPG_PC_MGMTDIR;
267
268 ipg_drive_phy_ctl_low_high(ioaddr, data);
269 }
270 }
271
272 send_three_state(ioaddr, polarity);
273
274 read_phy_bit(ioaddr, polarity);
275
276 /*
277 * For a read cycle, the bits for the next two fields (TA and
278 * DATA) are driven by the PHY (the IPG reads these bits).
279 */
280 for (i = 0; i < p[6].len; i++) {
281 p[6].field |=
282 (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
283 }
284
285 send_three_state(ioaddr, polarity);
286 send_three_state(ioaddr, polarity);
287 send_three_state(ioaddr, polarity);
288 send_end(ioaddr, polarity);
289
290 /* Return the value of the DATA field. */
291 return p[6].field;
292}
293
294/*
295 * Write to a register from the Physical Layer device located
296 * on the IPG NIC, using the IPG PHYCTRL register.
297 */
298static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
299{
300 void __iomem *ioaddr = ipg_ioaddr(dev);
301 /*
302 * The GMII mangement frame structure for a read is as follows:
303 *
304 * |Preamble|st|op|phyad|regad|ta| data |idle|
305 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
306 *
307 * <32 1s> = 32 consecutive logic 1 values
308 * A = bit of Physical Layer device address (MSB first)
309 * R = bit of register address (MSB first)
310 * z = High impedance state
311 * D = bit of write data (MSB first)
312 *
313 * Transmission order is 'Preamble' field first, bits transmitted
314 * left to right (first to last).
315 */
316 struct {
317 u32 field;
318 unsigned int len;
319 } p[] = {
320 { GMII_PREAMBLE, 32 }, /* Preamble */
321 { GMII_ST, 2 }, /* ST */
322 { GMII_WRITE, 2 }, /* OP */
323 { phy_id, 5 }, /* PHYAD */
324 { phy_reg, 5 }, /* REGAD */
325 { 0x0002, 2 }, /* TA */
326 { val & 0xffff, 16 }, /* DATA */
327 { 0x0000, 1 } /* IDLE */
328 };
329 unsigned int i, j;
330 u8 polarity, data;
331
332 polarity = ipg_r8(PHY_CTRL);
333 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
334
335 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
336 for (j = 0; j < 7; j++) {
337 for (i = 0; i < p[j].len; i++) {
338 /* For each variable length field, the MSB must be
339 * transmitted first. Rotate through the field bits,
340 * starting with the MSB, and move each bit into the
341 * the 1st (2^1) bit position (this is the bit position
342 * corresponding to the MgmtData bit of the PhyCtrl
343 * register for the IPG).
344 *
345 * Example: ST = 01;
346 *
347 * First write a '0' to bit 1 of the PhyCtrl
348 * register, then write a '1' to bit 1 of the
349 * PhyCtrl register.
350 *
351 * To do this, right shift the MSB of ST by the value:
352 * [field length - 1 - #ST bits already written]
353 * then left shift this result by 1.
354 */
355 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
356 data &= IPG_PC_MGMTDATA;
357 data |= polarity | IPG_PC_MGMTDIR;
358
359 ipg_drive_phy_ctl_low_high(ioaddr, data);
360 }
361 }
362
363 /* The last cycle is a tri-state, so read from the PHY. */
364 for (j = 7; j < 8; j++) {
365 for (i = 0; i < p[j].len; i++) {
366 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
367
368 p[j].field |= ((ipg_r8(PHY_CTRL) &
369 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
370
371 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
372 }
373 }
374}
375
376/* Set LED_Mode JES20040127EEPROM */
377static void ipg_set_led_mode(struct net_device *dev)
378{
379 struct ipg_nic_private *sp = netdev_priv(dev);
380 void __iomem *ioaddr = sp->ioaddr;
381 u32 mode;
382
383 mode = ipg_r32(ASIC_CTRL);
384 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
385
386 if ((sp->LED_Mode & 0x03) > 1)
387 mode |= IPG_AC_LED_MODE_BIT_1; /* Write Asic Control Bit 29 */
388
389 if ((sp->LED_Mode & 0x01) == 1)
390 mode |= IPG_AC_LED_MODE; /* Write Asic Control Bit 14 */
391
392 if ((sp->LED_Mode & 0x08) == 8)
393 mode |= IPG_AC_LED_SPEED; /* Write Asic Control Bit 27 */
394
395 ipg_w32(mode, ASIC_CTRL);
396}
397
398/* Set PHYSet JES20040127EEPROM */
399static void ipg_set_phy_set(struct net_device *dev)
400{
401 struct ipg_nic_private *sp = netdev_priv(dev);
402 void __iomem *ioaddr = sp->ioaddr;
403 int physet;
404
405 physet = ipg_r8(PHY_SET);
406 physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
407 physet |= ((sp->LED_Mode & 0x70) >> 4);
408 ipg_w8(physet, PHY_SET);
409}
410
411static int ipg_reset(struct net_device *dev, u32 resetflags)
412{
413 /* Assert functional resets via the IPG AsicCtrl
414 * register as specified by the 'resetflags' input
415 * parameter.
416 */
417 void __iomem *ioaddr = ipg_ioaddr(dev); //JES20040127EEPROM:
418 unsigned int timeout_count = 0;
419
420 IPG_DEBUG_MSG("_reset\n");
421
422 ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
423
424 /* Delay added to account for problem with 10Mbps reset. */
425 mdelay(IPG_AC_RESETWAIT);
426
427 while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
428 mdelay(IPG_AC_RESETWAIT);
429 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
430 return -ETIME;
431 }
432 /* Set LED Mode in Asic Control JES20040127EEPROM */
433 ipg_set_led_mode(dev);
434
435 /* Set PHYSet Register Value JES20040127EEPROM */
436 ipg_set_phy_set(dev);
437 return 0;
438}
439
440/* Find the GMII PHY address. */
441static int ipg_find_phyaddr(struct net_device *dev)
442{
443 unsigned int phyaddr, i;
444
445 for (i = 0; i < 32; i++) {
446 u32 status;
447
448 /* Search for the correct PHY address among 32 possible. */
449 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
450
451 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
452 GMII_PHY_ID1
453 */
454
455 status = mdio_read(dev, phyaddr, MII_BMSR);
456
457 if ((status != 0xFFFF) && (status != 0))
458 return phyaddr;
459 }
460
461 return 0x1f;
462}
463
464/*
465 * Configure IPG based on result of IEEE 802.3 PHY
466 * auto-negotiation.
467 */
468static int ipg_config_autoneg(struct net_device *dev)
469{
470 struct ipg_nic_private *sp = netdev_priv(dev);
471 void __iomem *ioaddr = sp->ioaddr;
472 unsigned int txflowcontrol;
473 unsigned int rxflowcontrol;
474 unsigned int fullduplex;
475 unsigned int gig;
476 u32 mac_ctrl_val;
477 u32 asicctrl;
478 u8 phyctrl;
479
480 IPG_DEBUG_MSG("_config_autoneg\n");
481
482 asicctrl = ipg_r32(ASIC_CTRL);
483 phyctrl = ipg_r8(PHY_CTRL);
484 mac_ctrl_val = ipg_r32(MAC_CTRL);
485
486 /* Set flags for use in resolving auto-negotation, assuming
487 * non-1000Mbps, half duplex, no flow control.
488 */
489 fullduplex = 0;
490 txflowcontrol = 0;
491 rxflowcontrol = 0;
492 gig = 0;
493
494 /* To accomodate a problem in 10Mbps operation,
495 * set a global flag if PHY running in 10Mbps mode.
496 */
497 sp->tenmbpsmode = 0;
498
499 printk(KERN_INFO "%s: Link speed = ", dev->name);
500
501 /* Determine actual speed of operation. */
502 switch (phyctrl & IPG_PC_LINK_SPEED) {
503 case IPG_PC_LINK_SPEED_10MBPS:
504 printk("10Mbps.\n");
505 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
506 dev->name);
507 sp->tenmbpsmode = 1;
508 break;
509 case IPG_PC_LINK_SPEED_100MBPS:
510 printk("100Mbps.\n");
511 break;
512 case IPG_PC_LINK_SPEED_1000MBPS:
513 printk("1000Mbps.\n");
514 gig = 1;
515 break;
516 default:
517 printk("undefined!\n");
518 return 0;
519 }
520
521 if (phyctrl & IPG_PC_DUPLEX_STATUS) {
522 fullduplex = 1;
523 txflowcontrol = 1;
524 rxflowcontrol = 1;
525 }
526
527 /* Configure full duplex, and flow control. */
528 if (fullduplex == 1) {
529 /* Configure IPG for full duplex operation. */
530 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
531
532 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
533
534 if (txflowcontrol == 1) {
535 printk("TX flow control");
536 mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
537 } else {
538 printk("no TX flow control");
539 mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
540 }
541
542 if (rxflowcontrol == 1) {
543 printk(", RX flow control.");
544 mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
545 } else {
546 printk(", no RX flow control.");
547 mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
548 }
549
550 printk("\n");
551 } else {
552 /* Configure IPG for half duplex operation. */
553 printk(KERN_INFO "%s: setting half duplex, "
554 "no TX flow control, no RX flow control.\n", dev->name);
555
556 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
557 ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
558 ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
559 }
560 ipg_w32(mac_ctrl_val, MAC_CTRL);
561 return 0;
562}
563
564/* Determine and configure multicast operation and set
565 * receive mode for IPG.
566 */
567static void ipg_nic_set_multicast_list(struct net_device *dev)
568{
569 void __iomem *ioaddr = ipg_ioaddr(dev);
570 struct dev_mc_list *mc_list_ptr;
571 unsigned int hashindex;
572 u32 hashtable[2];
573 u8 receivemode;
574
575 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
576
577 receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
578
579 if (dev->flags & IFF_PROMISC) {
580 /* NIC to be configured in promiscuous mode. */
581 receivemode = IPG_RM_RECEIVEALLFRAMES;
582 } else if ((dev->flags & IFF_ALLMULTI) ||
583 (dev->flags & IFF_MULTICAST &
584 (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
585 /* NIC to be configured to receive all multicast
586 * frames. */
587 receivemode |= IPG_RM_RECEIVEMULTICAST;
588 } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
589 /* NIC to be configured to receive selected
590 * multicast addresses. */
591 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
592 }
593
594 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
595 * The IPG applies a cyclic-redundancy-check (the same CRC
596 * used to calculate the frame data FCS) to the destination
597 * address all incoming multicast frames whose destination
598 * address has the multicast bit set. The least significant
599 * 6 bits of the CRC result are used as an addressing index
600 * into the hash table. If the value of the bit addressed by
601 * this index is a 1, the frame is passed to the host system.
602 */
603
604 /* Clear hashtable. */
605 hashtable[0] = 0x00000000;
606 hashtable[1] = 0x00000000;
607
608 /* Cycle through all multicast addresses to filter. */
609 for (mc_list_ptr = dev->mc_list;
610 mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
611 /* Calculate CRC result for each multicast address. */
612 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
613 ETH_ALEN);
614
615 /* Use only the least significant 6 bits. */
616 hashindex = hashindex & 0x3F;
617
618 /* Within "hashtable", set bit number "hashindex"
619 * to a logic 1.
620 */
621 set_bit(hashindex, (void *)hashtable);
622 }
623
624 /* Write the value of the hashtable, to the 4, 16 bit
625 * HASHTABLE IPG registers.
626 */
627 ipg_w32(hashtable[0], HASHTABLE_0);
628 ipg_w32(hashtable[1], HASHTABLE_1);
629
630 ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
631
632 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
633}
634
635static int ipg_io_config(struct net_device *dev)
636{
637 void __iomem *ioaddr = ipg_ioaddr(dev);
638 u32 origmacctrl;
639 u32 restoremacctrl;
640
641 IPG_DEBUG_MSG("_io_config\n");
642
643 origmacctrl = ipg_r32(MAC_CTRL);
644
645 restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
646
647 /* Based on compilation option, determine if FCS is to be
648 * stripped on receive frames by IPG.
649 */
650 if (!IPG_STRIP_FCS_ON_RX)
651 restoremacctrl |= IPG_MC_RCV_FCS;
652
653 /* Determine if transmitter and/or receiver are
654 * enabled so we may restore MACCTRL correctly.
655 */
656 if (origmacctrl & IPG_MC_TX_ENABLED)
657 restoremacctrl |= IPG_MC_TX_ENABLE;
658
659 if (origmacctrl & IPG_MC_RX_ENABLED)
660 restoremacctrl |= IPG_MC_RX_ENABLE;
661
662 /* Transmitter and receiver must be disabled before setting
663 * IFSSelect.
664 */
665 ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
666 IPG_MC_RSVD_MASK, MAC_CTRL);
667
668 /* Now that transmitter and receiver are disabled, write
669 * to IFSSelect.
670 */
671 ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
672
673 /* Set RECEIVEMODE register. */
674 ipg_nic_set_multicast_list(dev);
675
676 ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
677
678 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
679 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
680 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE, RX_DMA_BURST_THRESH);
681 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE, TX_DMA_POLL_PERIOD);
682 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
683 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE, TX_DMA_BURST_THRESH);
684 ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
685 IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
686 IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
687 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
688 ipg_w16(IPG_FLOWONTHRESH_VALUE, FLOW_ON_THRESH);
689 ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
690
691 /* IPG multi-frag frame bug workaround.
692 * Per silicon revision B3 eratta.
693 */
694 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
695
696 /* IPG TX poll now bug workaround.
697 * Per silicon revision B3 eratta.
698 */
699 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
700
701 /* IPG RX poll now bug workaround.
702 * Per silicon revision B3 eratta.
703 */
704 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
705
706 /* Now restore MACCTRL to original setting. */
707 ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
708
709 /* Disable unused RMON statistics. */
710 ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
711
712 /* Disable unused MIB statistics. */
713 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
714 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
715 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
716 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
717 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
718 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
719
720 return 0;
721}
722
723/*
724 * Create a receive buffer within system memory and update
725 * NIC private structure appropriately.
726 */
727static int ipg_get_rxbuff(struct net_device *dev, int entry)
728{
729 struct ipg_nic_private *sp = netdev_priv(dev);
730 struct ipg_rx *rxfd = sp->rxd + entry;
731 struct sk_buff *skb;
732 u64 rxfragsize;
733
734 IPG_DEBUG_MSG("_get_rxbuff\n");
735
736 skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
737 if (!skb) {
738 sp->RxBuff[entry] = NULL;
739 return -ENOMEM;
740 }
741
742 /* Adjust the data start location within the buffer to
743 * align IP address field to a 16 byte boundary.
744 */
745 skb_reserve(skb, NET_IP_ALIGN);
746
747 /* Associate the receive buffer with the IPG NIC. */
748 skb->dev = dev;
749
750 /* Save the address of the sk_buff structure. */
751 sp->RxBuff[entry] = skb;
752
753 rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
754 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
755
756 /* Set the RFD fragment length. */
757 rxfragsize = IPG_RXFRAG_SIZE;
758 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
759
760 return 0;
761}
762
763static int init_rfdlist(struct net_device *dev)
764{
765 struct ipg_nic_private *sp = netdev_priv(dev);
766 void __iomem *ioaddr = sp->ioaddr;
767 unsigned int i;
768
769 IPG_DEBUG_MSG("_init_rfdlist\n");
770
771 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
772 struct ipg_rx *rxfd = sp->rxd + i;
773
774 if (sp->RxBuff[i]) {
775 pci_unmap_single(sp->pdev,
325a8071 776 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 777 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
85d68a58 778 dev_kfree_skb_irq(sp->RxBuff[i]);
1202d6ff
FR		 779 sp->RxBuff[i] = NULL;
780 }
781
782 /* Clear out the RFS field. */
783 rxfd->rfs = 0x0000000000000000;
784
785 if (ipg_get_rxbuff(dev, i) < 0) {
786 /*
787 * A receive buffer was not ready, break the
788 * RFD list here.
789 */
790 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
791
792 /* Just in case we cannot allocate a single RFD.
793 * Should not occur.
794 */
795 if (i == 0) {
796 printk(KERN_ERR "%s: No memory available"
797 " for RFD list.\n", dev->name);
798 return -ENOMEM;
799 }
800 }
801
802 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
803 sizeof(struct ipg_rx)*(i + 1));
804 }
805 sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
806
807 sp->rx_current = 0;
808 sp->rx_dirty = 0;
809
810 /* Write the location of the RFDList to the IPG. */
811 ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
812 ipg_w32(0x00000000, RFD_LIST_PTR_1);
813
814 return 0;
815}
816
817static void init_tfdlist(struct net_device *dev)
818{
819 struct ipg_nic_private *sp = netdev_priv(dev);
820 void __iomem *ioaddr = sp->ioaddr;
821 unsigned int i;
822
823 IPG_DEBUG_MSG("_init_tfdlist\n");
824
825 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
826 struct ipg_tx *txfd = sp->txd + i;
827
828 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
829
830 if (sp->TxBuff[i]) {
85d68a58 831 dev_kfree_skb_irq(sp->TxBuff[i]);
1202d6ff
FR		 832 sp->TxBuff[i] = NULL;
833 }
834
835 txfd->next_desc = cpu_to_le64(sp->txd_map +
836 sizeof(struct ipg_tx)*(i + 1));
837 }
838 sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
839
840 sp->tx_current = 0;
841 sp->tx_dirty = 0;
842
843 /* Write the location of the TFDList to the IPG. */
844 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
845 (u32) sp->txd_map);
846 ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
847 ipg_w32(0x00000000, TFD_LIST_PTR_1);
848
849 sp->ResetCurrentTFD = 1;
850}
851
852/*
853 * Free all transmit buffers which have already been transfered
854 * via DMA to the IPG.
855 */
856static void ipg_nic_txfree(struct net_device *dev)
857{
858 struct ipg_nic_private *sp = netdev_priv(dev);
0da1b995 859 unsigned int released, pending, dirty;
1dad939d 860
1202d6ff
FR		 861 IPG_DEBUG_MSG("_nic_txfree\n");
862
863 pending = sp->tx_current - sp->tx_dirty;
0da1b995 864 dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
1202d6ff
FR		 865
866 for (released = 0; released < pending; released++) {
1202d6ff
FR		 867 struct sk_buff *skb = sp->TxBuff[dirty];
868 struct ipg_tx *txfd = sp->txd + dirty;
869
870 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
871
872 /* Look at each TFD's TFC field beginning
873 * at the last freed TFD up to the current TFD.
874 * If the TFDDone bit is set, free the associated
875 * buffer.
876 */
0da1b995
FR		 877 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
878 break;
1202d6ff
FR		 879
880 /* Free the transmit buffer. */
881 if (skb) {
882 pci_unmap_single(sp->pdev,
325a8071 883 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1202d6ff
FR		 884 skb->len, PCI_DMA_TODEVICE);
885
85d68a58 886 dev_kfree_skb_irq(skb);
1202d6ff
FR		 887
888 sp->TxBuff[dirty] = NULL;
889 }
0da1b995 890 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
1202d6ff
FR		 891 }
892
893 sp->tx_dirty += released;
894
895 if (netif_queue_stopped(dev) &&
896 (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
897 netif_wake_queue(dev);
898 }
899}
900
901static void ipg_tx_timeout(struct net_device *dev)
902{
903 struct ipg_nic_private *sp = netdev_priv(dev);
904 void __iomem *ioaddr = sp->ioaddr;
905
906 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
907 IPG_AC_FIFO);
908
909 spin_lock_irq(&sp->lock);
910
911 /* Re-configure after DMA reset. */
912 if (ipg_io_config(dev) < 0) {
913 printk(KERN_INFO "%s: Error during re-configuration.\n",
914 dev->name);
915 }
916
917 init_tfdlist(dev);
918
919 spin_unlock_irq(&sp->lock);
920
921 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
922 MAC_CTRL);
923}
924
925/*
926 * For TxComplete interrupts, free all transmit
927 * buffers which have already been transfered via DMA
928 * to the IPG.
929 */
930static void ipg_nic_txcleanup(struct net_device *dev)
931{
932 struct ipg_nic_private *sp = netdev_priv(dev);
933 void __iomem *ioaddr = sp->ioaddr;
934 unsigned int i;
935
936 IPG_DEBUG_MSG("_nic_txcleanup\n");
937
938 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
939 /* Reading the TXSTATUS register clears the
940 * TX_COMPLETE interrupt.
941 */
942 u32 txstatusdword = ipg_r32(TX_STATUS);
943
944 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
945
946 /* Check for Transmit errors. Error bits only valid if
947 * TX_COMPLETE bit in the TXSTATUS register is a 1.
948 */
949 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
950 break;
951
952 /* If in 10Mbps mode, indicate transmit is ready. */
953 if (sp->tenmbpsmode) {
954 netif_wake_queue(dev);
955 }
956
957 /* Transmit error, increment stat counters. */
958 if (txstatusdword & IPG_TS_TX_ERROR) {
959 IPG_DEBUG_MSG("Transmit error.\n");
960 sp->stats.tx_errors++;
961 }
962
963 /* Late collision, re-enable transmitter. */
964 if (txstatusdword & IPG_TS_LATE_COLLISION) {
965 IPG_DEBUG_MSG("Late collision on transmit.\n");
966 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
967 IPG_MC_RSVD_MASK, MAC_CTRL);
968 }
969
970 /* Maximum collisions, re-enable transmitter. */
971 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
972 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
973 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
974 IPG_MC_RSVD_MASK, MAC_CTRL);
975 }
976
977 /* Transmit underrun, reset and re-enable
978 * transmitter.
979 */
980 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
981 IPG_DEBUG_MSG("Transmitter underrun.\n");
982 sp->stats.tx_fifo_errors++;
983 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
984 IPG_AC_NETWORK | IPG_AC_FIFO);
985
986 /* Re-configure after DMA reset. */
987 if (ipg_io_config(dev) < 0) {
988 printk(KERN_INFO
989 "%s: Error during re-configuration.\n",
990 dev->name);
991 }
992 init_tfdlist(dev);
993
994 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
995 IPG_MC_RSVD_MASK, MAC_CTRL);
996 }
997 }
998
999 ipg_nic_txfree(dev);
1000}
1001
1002/* Provides statistical information about the IPG NIC. */
96fd74b2 1003static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1202d6ff
FR		 1004{
1005 struct ipg_nic_private *sp = netdev_priv(dev);
1006 void __iomem *ioaddr = sp->ioaddr;
1007 u16 temp1;
1008 u16 temp2;
1009
1010 IPG_DEBUG_MSG("_nic_get_stats\n");
1011
1012 /* Check to see if the NIC has been initialized via nic_open,
1013 * before trying to read statistic registers.
1014 */
1015 if (!test_bit(__LINK_STATE_START, &dev->state))
1016 return &sp->stats;
1017
1018 sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1019 sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1020 sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1021 sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1022 temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1023 sp->stats.rx_errors += temp1;
1024 sp->stats.rx_missed_errors += temp1;
1025 temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1026 ipg_r32(IPG_LATECOLLISIONS);
1027 temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1028 sp->stats.collisions += temp1;
1029 sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1030 sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1031 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1032 sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1033
1034 /* detailed tx_errors */
1035 sp->stats.tx_carrier_errors += temp2;
1036
1037 /* detailed rx_errors */
1038 sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1039 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1040 sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1041
1042 /* Unutilized IPG statistic registers. */
1043 ipg_r32(IPG_MCSTFRAMESRCVDOK);
1044
1045 return &sp->stats;
1046}
1047
1048/* Restore used receive buffers. */
1049static int ipg_nic_rxrestore(struct net_device *dev)
1050{
1051 struct ipg_nic_private *sp = netdev_priv(dev);
1052 const unsigned int curr = sp->rx_current;
1053 unsigned int dirty = sp->rx_dirty;
1054
1055 IPG_DEBUG_MSG("_nic_rxrestore\n");
1056
1057 for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1058 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1059
1060 /* rx_copybreak may poke hole here and there. */
1061 if (sp->RxBuff[entry])
1062 continue;
1063
1064 /* Generate a new receive buffer to replace the
1065 * current buffer (which will be released by the
1066 * Linux system).
1067 */
1068 if (ipg_get_rxbuff(dev, entry) < 0) {
1069 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1070
1071 break;
1072 }
1073
1074 /* Reset the RFS field. */
1075 sp->rxd[entry].rfs = 0x0000000000000000;
1076 }
1077 sp->rx_dirty = dirty;
1078
1079 return 0;
1080}
1081
1082#ifdef JUMBO_FRAME
1083
1084/* use jumboindex and jumbosize to control jumbo frame status
1085 initial status is jumboindex=-1 and jumbosize=0
1086 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1087 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1088 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1089 previous receiving and need to continue dumping the current one
1090*/
1091enum {
1092 NormalPacket,
1093 ErrorPacket
1094};
1095
1096enum {
1097 Frame_NoStart_NoEnd = 0,
1098 Frame_WithStart = 1,
1099 Frame_WithEnd = 10,
1100 Frame_WithStart_WithEnd = 11
1101};
1102
1103inline void ipg_nic_rx_free_skb(struct net_device *dev)
1104{
1105 struct ipg_nic_private *sp = netdev_priv(dev);
1106 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1107
1108 if (sp->RxBuff[entry]) {
1109 struct ipg_rx *rxfd = sp->rxd + entry;
1110
1111 pci_unmap_single(sp->pdev,
1112 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1113 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
85d68a58 1114 dev_kfree_skb_irq(sp->RxBuff[entry]);
1202d6ff
FR		 1115 sp->RxBuff[entry] = NULL;
1116 }
1117}
1118
1119inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1120{
1121 struct ipg_nic_private *sp = netdev_priv(dev);
1122 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1123 int type = Frame_NoStart_NoEnd;
1124
1125 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1126 type += Frame_WithStart;
1127 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1128 type += Frame_WithEnd;
1129 return type;
1130}
1131
1132inline int ipg_nic_rx_check_error(struct net_device *dev)
1133{
1134 struct ipg_nic_private *sp = netdev_priv(dev);
1135 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1136 struct ipg_rx *rxfd = sp->rxd + entry;
1137
1138 if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1139 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1140 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1141 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1142 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1143 (unsigned long) rxfd->rfs);
1144
1145 /* Increment general receive error statistic. */
1146 sp->stats.rx_errors++;
1147
1148 /* Increment detailed receive error statistics. */
1149 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1150 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1151
1152 sp->stats.rx_fifo_errors++;
1153 }
1154
1155 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1156 IPG_DEBUG_MSG("RX runt occured.\n");
1157 sp->stats.rx_length_errors++;
1158 }
1159
1160 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1161 * error count handled by a IPG statistic register.
1162 */
1163
1164 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1165 IPG_DEBUG_MSG("RX alignment error occured.\n");
1166 sp->stats.rx_frame_errors++;
1167 }
1168
1169 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1170 * handled by a IPG statistic register.
1171 */
1172
1173 /* Free the memory associated with the RX
1174 * buffer since it is erroneous and we will
1175 * not pass it to higher layer processes.
1176 */
1177 if (sp->RxBuff[entry]) {
1178 pci_unmap_single(sp->pdev,
1179 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1180 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1181
85d68a58 1182 dev_kfree_skb_irq(sp->RxBuff[entry]);
1202d6ff
FR		 1183 sp->RxBuff[entry] = NULL;
1184 }
1185 return ErrorPacket;
1186 }
1187 return NormalPacket;
1188}
1189
1190static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1191 struct ipg_nic_private *sp,
1192 struct ipg_rx *rxfd, unsigned entry)
1193{
1194 struct SJumbo *jumbo = &sp->Jumbo;
1195 struct sk_buff *skb;
1196 int framelen;
1197
1198 if (jumbo->FoundStart) {
85d68a58 1199 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1200 jumbo->FoundStart = 0;
1201 jumbo->CurrentSize = 0;
1202 jumbo->skb = NULL;
1203 }
1204
1205 // 1: found error, 0 no error
1206 if (ipg_nic_rx_check_error(dev) != NormalPacket)
1207 return;
1208
1209 skb = sp->RxBuff[entry];
1210 if (!skb)
1211 return;
1212
1213 // accept this frame and send to upper layer
1214 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1215 if (framelen > IPG_RXFRAG_SIZE)
1216 framelen = IPG_RXFRAG_SIZE;
1217
1218 skb_put(skb, framelen);
1219 skb->protocol = eth_type_trans(skb, dev);
1220 skb->ip_summed = CHECKSUM_NONE;
1221 netif_rx(skb);
1222 dev->last_rx = jiffies;
1223 sp->RxBuff[entry] = NULL;
1224}
1225
1226static void ipg_nic_rx_with_start(struct net_device *dev,
1227 struct ipg_nic_private *sp,
1228 struct ipg_rx *rxfd, unsigned entry)
1229{
1230 struct SJumbo *jumbo = &sp->Jumbo;
1231 struct pci_dev *pdev = sp->pdev;
1232 struct sk_buff *skb;
1233
1234 // 1: found error, 0 no error
1235 if (ipg_nic_rx_check_error(dev) != NormalPacket)
1236 return;
1237
1238 // accept this frame and send to upper layer
1239 skb = sp->RxBuff[entry];
1240 if (!skb)
1241 return;
1242
1243 if (jumbo->FoundStart)
85d68a58 1244 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1245
1246 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1247 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1248
1249 skb_put(skb, IPG_RXFRAG_SIZE);
1250
1251 jumbo->FoundStart = 1;
1252 jumbo->CurrentSize = IPG_RXFRAG_SIZE;
1253 jumbo->skb = skb;
1254
1255 sp->RxBuff[entry] = NULL;
1256 dev->last_rx = jiffies;
1257}
1258
1259static void ipg_nic_rx_with_end(struct net_device *dev,
1260 struct ipg_nic_private *sp,
1261 struct ipg_rx *rxfd, unsigned entry)
1262{
1263 struct SJumbo *jumbo = &sp->Jumbo;
1264
1265 //1: found error, 0 no error
1266 if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1267 struct sk_buff *skb = sp->RxBuff[entry];
1268
1269 if (!skb)
1270 return;
1271
1272 if (jumbo->FoundStart) {
1273 int framelen, endframelen;
1274
1275 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1276
1277 endframeLen = framelen - jumbo->CurrentSize;
1278 /*
1279 if (framelen > IPG_RXFRAG_SIZE)
1280 framelen=IPG_RXFRAG_SIZE;
1281 */
1282 if (framelen > IPG_RXSUPPORT_SIZE)
85d68a58 1283 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1284 else {
1285 memcpy(skb_put(jumbo->skb, endframeLen),
1286 skb->data, endframeLen);
1287
1288 jumbo->skb->protocol =
1289 eth_type_trans(jumbo->skb, dev);
1290
1291 jumbo->skb->ip_summed = CHECKSUM_NONE;
1292 netif_rx(jumbo->skb);
1293 }
1294 }
1295
1296 dev->last_rx = jiffies;
1297 jumbo->FoundStart = 0;
1298 jumbo->CurrentSize = 0;
1299 jumbo->skb = NULL;
1300
1301 ipg_nic_rx_free_skb(dev);
1302 } else {
85d68a58 1303 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1304 jumbo->FoundStart = 0;
1305 jumbo->CurrentSize = 0;
1306 jumbo->skb = NULL;
1307 }
1308}
1309
1310static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1311 struct ipg_nic_private *sp,
1312 struct ipg_rx *rxfd, unsigned entry)
1313{
1314 struct SJumbo *jumbo = &sp->Jumbo;
1315
1316 //1: found error, 0 no error
1317 if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1318 struct sk_buff *skb = sp->RxBuff[entry];
1319
1320 if (skb) {
1321 if (jumbo->FoundStart) {
1322 jumbo->CurrentSize += IPG_RXFRAG_SIZE;
1323 if (jumbo->CurrentSize <= IPG_RXSUPPORT_SIZE) {
1324 memcpy(skb_put(jumbo->skb,
1325 IPG_RXFRAG_SIZE),
1326 skb->data, IPG_RXFRAG_SIZE);
1327 }
1328 }
1329 dev->last_rx = jiffies;
1330 ipg_nic_rx_free_skb(dev);
1331 }
1332 } else {
85d68a58 1333 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1334 jumbo->FoundStart = 0;
1335 jumbo->CurrentSize = 0;
1336 jumbo->skb = NULL;
1337 }
1338}
1339
1340static int ipg_nic_rx(struct net_device *dev)
1341{
1342 struct ipg_nic_private *sp = netdev_priv(dev);
1343 unsigned int curr = sp->rx_current;
1344 void __iomem *ioaddr = sp->ioaddr;
1345 unsigned int i;
1346
1347 IPG_DEBUG_MSG("_nic_rx\n");
1348
1349 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1350 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1351 struct ipg_rx *rxfd = sp->rxd + entry;
1352
1353 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1354 break;
1355
1356 switch (ipg_nic_rx_check_frame_type(dev)) {
1357 case Frame_WithStart_WithEnd:
1358 ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1359 break;
1360 case Frame_WithStart:
1361 ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1362 break;
1363 case Frame_WithEnd:
1364 ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1365 break;
1366 case Frame_NoStart_NoEnd:
1367 ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1368 break;
1369 }
1370 }
1371
1372 sp->rx_current = curr;
1373
1374 if (i == IPG_MAXRFDPROCESS_COUNT) {
1375 /* There are more RFDs to process, however the
1376 * allocated amount of RFD processing time has
1377 * expired. Assert Interrupt Requested to make
1378 * sure we come back to process the remaining RFDs.
1379 */
1380 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1381 }
1382
1383 ipg_nic_rxrestore(dev);
1384
1385 return 0;
1386}
1387
1388#else
1389static int ipg_nic_rx(struct net_device *dev)
1390{
1391 /* Transfer received Ethernet frames to higher network layers. */
1392 struct ipg_nic_private *sp = netdev_priv(dev);
1393 unsigned int curr = sp->rx_current;
1394 void __iomem *ioaddr = sp->ioaddr;
1395 struct ipg_rx *rxfd;
1396 unsigned int i;
1397
1398 IPG_DEBUG_MSG("_nic_rx\n");
1399
1400#define __RFS_MASK \
1401 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1402
1403 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1404 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1405 struct sk_buff *skb = sp->RxBuff[entry];
1406 unsigned int framelen;
1407
1408 rxfd = sp->rxd + entry;
1409
1410 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1411 break;
1412
1413 /* Get received frame length. */
1414 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1415
1416 /* Check for jumbo frame arrival with too small
1417 * RXFRAG_SIZE.
1418 */
1419 if (framelen > IPG_RXFRAG_SIZE) {
1420 IPG_DEBUG_MSG
1421 ("RFS FrameLen > allocated fragment size.\n");
1422
1423 framelen = IPG_RXFRAG_SIZE;
1424 }
1425
325a8071 1426 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1202d6ff
FR		 1427 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1428 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
325a8071 1429 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1202d6ff
FR		 1430
1431 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1432 (unsigned long int) rxfd->rfs);
1433
1434 /* Increment general receive error statistic. */
1435 sp->stats.rx_errors++;
1436
1437 /* Increment detailed receive error statistics. */
325a8071 1438 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1202d6ff
FR		 1439 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1440 sp->stats.rx_fifo_errors++;
1441 }
1442
325a8071 1443 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1202d6ff
FR		 1444 IPG_DEBUG_MSG("RX runt occured.\n");
1445 sp->stats.rx_length_errors++;
1446 }
1447
325a8071 1448 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1202d6ff
FR		 1449 /* Do nothing, error count handled by a IPG
1450 * statistic register.
1451 */
1452
325a8071 1453 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1202d6ff
FR		 1454 IPG_DEBUG_MSG("RX alignment error occured.\n");
1455 sp->stats.rx_frame_errors++;
1456 }
1457
325a8071 1458 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1202d6ff
FR		 1459 /* Do nothing, error count handled by a IPG
1460 * statistic register.
1461 */
1462
1463 /* Free the memory associated with the RX
1464 * buffer since it is erroneous and we will
1465 * not pass it to higher layer processes.
1466 */
1467 if (skb) {
325a8071 1468 __le64 info = rxfd->frag_info;
1202d6ff
FR		 1469
1470 pci_unmap_single(sp->pdev,
325a8071 1471 le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1472 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1473
85d68a58 1474 dev_kfree_skb_irq(skb);
1202d6ff
FR		 1475 }
1476 } else {
1477
1478 /* Adjust the new buffer length to accomodate the size
1479 * of the received frame.
1480 */
1481 skb_put(skb, framelen);
1482
1483 /* Set the buffer's protocol field to Ethernet. */
1484 skb->protocol = eth_type_trans(skb, dev);
1485
6d3b2cb9
PE		 1486 /* The IPG encountered an error with (or
1487 * there were no) IP/TCP/UDP checksums.
1488 * This may or may not indicate an invalid
1489 * IP/TCP/UDP frame was received. Let the
1490 * upper layer decide.
1202d6ff 1491 */
6d3b2cb9 1492 skb->ip_summed = CHECKSUM_NONE;
1202d6ff
FR		 1493
1494 /* Hand off frame for higher layer processing.
1495 * The function netif_rx() releases the sk_buff
1496 * when processing completes.
1497 */
1498 netif_rx(skb);
1499
1500 /* Record frame receive time (jiffies = Linux
1501 * kernel current time stamp).
1502 */
1503 dev->last_rx = jiffies;
1504 }
1505
1506 /* Assure RX buffer is not reused by IPG. */
1507 sp->RxBuff[entry] = NULL;
1508 }
1509
1510 /*
1511 * If there are more RFDs to proces and the allocated amount of RFD
1512 * processing time has expired, assert Interrupt Requested to make
1513 * sure we come back to process the remaining RFDs.
1514 */
1515 if (i == IPG_MAXRFDPROCESS_COUNT)
1516 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1517
1518#ifdef IPG_DEBUG
1519 /* Check if the RFD list contained no receive frame data. */
1520 if (!i)
1521 sp->EmptyRFDListCount++;
1522#endif
325a8071
AV		 1523 while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1524 !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1525 (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1202d6ff
FR		 1526 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1527
1528 rxfd = sp->rxd + entry;
1529
1530 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1531
1532 /* An unexpected event, additional code needed to handle
1533 * properly. So for the time being, just disregard the
1534 * frame.
1535 */
1536
1537 /* Free the memory associated with the RX
1538 * buffer since it is erroneous and we will
1539 * not pass it to higher layer processes.
1540 */
1541 if (sp->RxBuff[entry]) {
1542 pci_unmap_single(sp->pdev,
325a8071 1543 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 1544 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
85d68a58 1545 dev_kfree_skb_irq(sp->RxBuff[entry]);
1202d6ff
FR		 1546 }
1547
1548 /* Assure RX buffer is not reused by IPG. */
1549 sp->RxBuff[entry] = NULL;
1550 }
1551
1552 sp->rx_current = curr;
1553
1554 /* Check to see if there are a minimum number of used
1555 * RFDs before restoring any (should improve performance.)
1556 */
1557 if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1558 ipg_nic_rxrestore(dev);
1559
1560 return 0;
1561}
1562#endif
1563
1564static void ipg_reset_after_host_error(struct work_struct *work)
1565{
1566 struct ipg_nic_private *sp =
1567 container_of(work, struct ipg_nic_private, task.work);
1568 struct net_device *dev = sp->dev;
1569
1570 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1571
1572 /*
1573 * Acknowledge HostError interrupt by resetting
1574 * IPG DMA and HOST.
1575 */
1576 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1577
1578 init_rfdlist(dev);
1579 init_tfdlist(dev);
1580
1581 if (ipg_io_config(dev) < 0) {
1582 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1583 dev->name);
1584 schedule_delayed_work(&sp->task, HZ);
1585 }
1586}
1587
1588static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1589{
1590 struct net_device *dev = dev_inst;
1591 struct ipg_nic_private *sp = netdev_priv(dev);
1592 void __iomem *ioaddr = sp->ioaddr;
1593 unsigned int handled = 0;
1594 u16 status;
1595
1596 IPG_DEBUG_MSG("_interrupt_handler\n");
1597
1598#ifdef JUMBO_FRAME
1599 ipg_nic_rxrestore(dev);
1600#endif
227bc24d
FR		 1601 spin_lock(&sp->lock);
1602
1202d6ff
FR		 1603 /* Get interrupt source information, and acknowledge
1604 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1605 * IntRequested, MacControlFrame, LinkEvent) interrupts
1606 * if issued. Also, all IPG interrupts are disabled by
1607 * reading IntStatusAck.
1608 */
1609 status = ipg_r16(INT_STATUS_ACK);
1610
1611 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1612
1613 /* Shared IRQ of remove event. */
1614 if (!(status & IPG_IS_RSVD_MASK))
1615 goto out_enable;
1616
1617 handled = 1;
1618
1619 if (unlikely(!netif_running(dev)))
227bc24d 1620 goto out_unlock;
1202d6ff
FR		 1621
1622 /* If RFDListEnd interrupt, restore all used RFDs. */
1623 if (status & IPG_IS_RFD_LIST_END) {
1624 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1625
1626 /* The RFD list end indicates an RFD was encountered
1627 * with a 0 NextPtr, or with an RFDDone bit set to 1
1628 * (indicating the RFD is not read for use by the
1629 * IPG.) Try to restore all RFDs.
1630 */
1631 ipg_nic_rxrestore(dev);
1632
1633#ifdef IPG_DEBUG
1634 /* Increment the RFDlistendCount counter. */
1635 sp->RFDlistendCount++;
1636#endif
1637 }
1638
1639 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1640 * IntRequested interrupt, process received frames. */
1641 if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1642 (status & IPG_IS_RFD_LIST_END) ||
1643 (status & IPG_IS_RX_DMA_COMPLETE) ||
1644 (status & IPG_IS_INT_REQUESTED)) {
1645#ifdef IPG_DEBUG
1646 /* Increment the RFD list checked counter if interrupted
1647 * only to check the RFD list. */
1648 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1649 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1650 (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1651 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1652 IPG_IS_UPDATE_STATS)))
1653 sp->RFDListCheckedCount++;
1654#endif
1655
1656 ipg_nic_rx(dev);
1657 }
1658
1659 /* If TxDMAComplete interrupt, free used TFDs. */
1660 if (status & IPG_IS_TX_DMA_COMPLETE)
1661 ipg_nic_txfree(dev);
1662
1663 /* TxComplete interrupts indicate one of numerous actions.
1664 * Determine what action to take based on TXSTATUS register.
1665 */
1666 if (status & IPG_IS_TX_COMPLETE)
1667 ipg_nic_txcleanup(dev);
1668
1669 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1670 if (status & IPG_IS_UPDATE_STATS)
1671 ipg_nic_get_stats(dev);
1672
1673 /* If HostError interrupt, reset IPG. */
1674 if (status & IPG_IS_HOST_ERROR) {
1675 IPG_DDEBUG_MSG("HostError Interrupt\n");
1676
1677 schedule_delayed_work(&sp->task, 0);
1678 }
1679
1680 /* If LinkEvent interrupt, resolve autonegotiation. */
1681 if (status & IPG_IS_LINK_EVENT) {
1682 if (ipg_config_autoneg(dev) < 0)
1683 printk(KERN_INFO "%s: Auto-negotiation error.\n",
1684 dev->name);
1685 }
1686
1687 /* If MACCtrlFrame interrupt, do nothing. */
1688 if (status & IPG_IS_MAC_CTRL_FRAME)
1689 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1690
1691 /* If RxComplete interrupt, do nothing. */
1692 if (status & IPG_IS_RX_COMPLETE)
1693 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1694
1695 /* If RxEarly interrupt, do nothing. */
1696 if (status & IPG_IS_RX_EARLY)
1697 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1698
1699out_enable:
1700 /* Re-enable IPG interrupts. */
1701 ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1702 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1703 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
227bc24d 1704out_unlock:
1202d6ff 1705 spin_unlock(&sp->lock);
227bc24d 1706
1202d6ff
FR		 1707 return IRQ_RETVAL(handled);
1708}
1709
1710static void ipg_rx_clear(struct ipg_nic_private *sp)
1711{
1712 unsigned int i;
1713
1714 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1715 if (sp->RxBuff[i]) {
1716 struct ipg_rx *rxfd = sp->rxd + i;
1717
85d68a58 1718 dev_kfree_skb_irq(sp->RxBuff[i]);
1202d6ff
FR		 1719 sp->RxBuff[i] = NULL;
1720 pci_unmap_single(sp->pdev,
325a8071 1721 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1722 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1723 }
1724 }
1725}
1726
1727static void ipg_tx_clear(struct ipg_nic_private *sp)
1728{
1729 unsigned int i;
1730
1731 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1732 if (sp->TxBuff[i]) {
1733 struct ipg_tx *txfd = sp->txd + i;
1734
1735 pci_unmap_single(sp->pdev,
325a8071 1736 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1202d6ff
FR		 1737 sp->TxBuff[i]->len, PCI_DMA_TODEVICE);
1738
85d68a58 1739 dev_kfree_skb_irq(sp->TxBuff[i]);
1202d6ff
FR		 1740
1741 sp->TxBuff[i] = NULL;
1742 }
1743 }
1744}
1745
1746static int ipg_nic_open(struct net_device *dev)
1747{
1748 struct ipg_nic_private *sp = netdev_priv(dev);
1749 void __iomem *ioaddr = sp->ioaddr;
1750 struct pci_dev *pdev = sp->pdev;
1751 int rc;
1752
1753 IPG_DEBUG_MSG("_nic_open\n");
1754
1755 sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1756
1757 /* Check for interrupt line conflicts, and request interrupt
1758 * line for IPG.
1759 *
1760 * IMPORTANT: Disable IPG interrupts prior to registering
1761 * IRQ.
1762 */
1763 ipg_w16(0x0000, INT_ENABLE);
1764
1765 /* Register the interrupt line to be used by the IPG within
1766 * the Linux system.
1767 */
1768 rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1769 dev->name, dev);
1770 if (rc < 0) {
1771 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1772 dev->name);
1773 goto out;
1774 }
1775
1776 dev->irq = pdev->irq;
1777
1778 rc = -ENOMEM;
1779
1780 sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1781 &sp->rxd_map, GFP_KERNEL);
1782 if (!sp->rxd)
1783 goto err_free_irq_0;
1784
1785 sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1786 &sp->txd_map, GFP_KERNEL);
1787 if (!sp->txd)
1788 goto err_free_rx_1;
1789
1790 rc = init_rfdlist(dev);
1791 if (rc < 0) {
1792 printk(KERN_INFO "%s: Error during configuration.\n",
1793 dev->name);
1794 goto err_free_tx_2;
1795 }
1796
1797 init_tfdlist(dev);
1798
1799 rc = ipg_io_config(dev);
1800 if (rc < 0) {
1801 printk(KERN_INFO "%s: Error during configuration.\n",
1802 dev->name);
1803 goto err_release_tfdlist_3;
1804 }
1805
1806 /* Resolve autonegotiation. */
1807 if (ipg_config_autoneg(dev) < 0)
1808 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1809
1810#ifdef JUMBO_FRAME
1811 /* initialize JUMBO Frame control variable */
1812 sp->Jumbo.FoundStart = 0;
1813 sp->Jumbo.CurrentSize = 0;
1814 sp->Jumbo.skb = 0;
1815 dev->mtu = IPG_TXFRAG_SIZE;
1816#endif
1817
1818 /* Enable transmit and receive operation of the IPG. */
1819 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1820 IPG_MC_RSVD_MASK, MAC_CTRL);
1821
1822 netif_start_queue(dev);
1823out:
1824 return rc;
1825
1826err_release_tfdlist_3:
1827 ipg_tx_clear(sp);
1828 ipg_rx_clear(sp);
1829err_free_tx_2:
1830 dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1831err_free_rx_1:
1832 dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1833err_free_irq_0:
1834 free_irq(pdev->irq, dev);
1835 goto out;
1836}
1837
1838static int ipg_nic_stop(struct net_device *dev)
1839{
1840 struct ipg_nic_private *sp = netdev_priv(dev);
1841 void __iomem *ioaddr = sp->ioaddr;
1842 struct pci_dev *pdev = sp->pdev;
1843
1844 IPG_DEBUG_MSG("_nic_stop\n");
1845
1846 netif_stop_queue(dev);
1847
1848 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1849 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1850 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1851 IPG_DUMPTFDLIST(dev);
1852
1853 do {
1854 (void) ipg_r16(INT_STATUS_ACK);
1855
1856 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1857
1858 synchronize_irq(pdev->irq);
1859 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1860
1861 ipg_rx_clear(sp);
1862
1863 ipg_tx_clear(sp);
1864
1865 pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1866 pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1867
1868 free_irq(pdev->irq, dev);
1869
1870 return 0;
1871}
1872
1873static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1874{
1875 struct ipg_nic_private *sp = netdev_priv(dev);
1876 void __iomem *ioaddr = sp->ioaddr;
1877 unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1878 unsigned long flags;
1879 struct ipg_tx *txfd;
1880
1881 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1882
1883 /* If in 10Mbps mode, stop the transmit queue so
1884 * no more transmit frames are accepted.
1885 */
1886 if (sp->tenmbpsmode)
1887 netif_stop_queue(dev);
1888
1889 if (sp->ResetCurrentTFD) {
1890 sp->ResetCurrentTFD = 0;
1891 entry = 0;
1892 }
1893
1894 txfd = sp->txd + entry;
1895
1896 sp->TxBuff[entry] = skb;
1897
1898 /* Clear all TFC fields, except TFDDONE. */
1899 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1900
1901 /* Specify the TFC field within the TFD. */
1902 txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1903 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1904 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1905
1906 /* Request TxComplete interrupts at an interval defined
1907 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1908 * Request TxComplete interrupt for every frame
1909 * if in 10Mbps mode to accomodate problem with 10Mbps
1910 * processing.
1911 */
1912 if (sp->tenmbpsmode)
1913 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
47cccd7d 1914 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1202d6ff
FR		 1915 /* Based on compilation option, determine if FCS is to be
1916 * appended to transmit frame by IPG.
1917 */
1918 if (!(IPG_APPEND_FCS_ON_TX))
1919 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1920
1921 /* Based on compilation option, determine if IP, TCP and/or
1922 * UDP checksums are to be added to transmit frame by IPG.
1923 */
1924 if (IPG_ADD_IPCHECKSUM_ON_TX)
1925 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1926
1927 if (IPG_ADD_TCPCHECKSUM_ON_TX)
1928 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1929
1930 if (IPG_ADD_UDPCHECKSUM_ON_TX)
1931 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1932
1933 /* Based on compilation option, determine if VLAN tag info is to be
1934 * inserted into transmit frame by IPG.
1935 */
1936 if (IPG_INSERT_MANUAL_VLAN_TAG) {
1937 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1938 ((u64) IPG_MANUAL_VLAN_VID << 32) |
1939 ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1940 ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1941 }
1942
1943 /* The fragment start location within system memory is defined
1944 * by the sk_buff structure's data field. The physical address
1945 * of this location within the system's virtual memory space
1946 * is determined using the IPG_HOST2BUS_MAP function.
1947 */
1948 txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1949 skb->len, PCI_DMA_TODEVICE));
1950
1951 /* The length of the fragment within system memory is defined by
1952 * the sk_buff structure's len field.
1953 */
1954 txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1955 ((u64) (skb->len & 0xffff) << 48));
1956
1957 /* Clear the TFDDone bit last to indicate the TFD is ready
1958 * for transfer to the IPG.
1959 */
1960 txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1961
1962 spin_lock_irqsave(&sp->lock, flags);
1963
1964 sp->tx_current++;
1965
1966 mmiowb();
1967
1968 ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1969
1970 if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
dafdec74 1971 netif_stop_queue(dev);
1202d6ff
FR		 1972
1973 spin_unlock_irqrestore(&sp->lock, flags);
1974
1975 return NETDEV_TX_OK;
1976}
1977
1978static void ipg_set_phy_default_param(unsigned char rev,
1979 struct net_device *dev, int phy_address)
1980{
1981 unsigned short length;
1982 unsigned char revision;
1983 unsigned short *phy_param;
1984 unsigned short address, value;
1985
1986 phy_param = &DefaultPhyParam[0];
1987 length = *phy_param & 0x00FF;
1988 revision = (unsigned char)((*phy_param) >> 8);
1989 phy_param++;
1990 while (length != 0) {
1991 if (rev == revision) {
1992 while (length > 1) {
1993 address = *phy_param;
1994 value = *(phy_param + 1);
1995 phy_param += 2;
1996 mdio_write(dev, phy_address, address, value);
1997 length -= 4;
1998 }
1999 break;
2000 } else {
2001 phy_param += length / 2;
2002 length = *phy_param & 0x00FF;
2003 revision = (unsigned char)((*phy_param) >> 8);
2004 phy_param++;
2005 }
2006 }
2007}
2008
2009/* JES20040127EEPROM */
2010static int read_eeprom(struct net_device *dev, int eep_addr)
2011{
2012 void __iomem *ioaddr = ipg_ioaddr(dev);
2013 unsigned int i;
2014 int ret = 0;
2015 u16 value;
2016
2017 value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2018 ipg_w16(value, EEPROM_CTRL);
2019
2020 for (i = 0; i < 1000; i++) {
2021 u16 data;
2022
2023 mdelay(10);
2024 data = ipg_r16(EEPROM_CTRL);
2025 if (!(data & IPG_EC_EEPROM_BUSY)) {
2026 ret = ipg_r16(EEPROM_DATA);
2027 break;
2028 }
2029 }
2030 return ret;
2031}
2032
2033static void ipg_init_mii(struct net_device *dev)
2034{
2035 struct ipg_nic_private *sp = netdev_priv(dev);
2036 struct mii_if_info *mii_if = &sp->mii_if;
2037 int phyaddr;
2038
2039 mii_if->dev = dev;
2040 mii_if->mdio_read = mdio_read;
2041 mii_if->mdio_write = mdio_write;
2042 mii_if->phy_id_mask = 0x1f;
2043 mii_if->reg_num_mask = 0x1f;
2044
2045 mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2046
2047 if (phyaddr != 0x1f) {
2048 u16 mii_phyctrl, mii_1000cr;
2049 u8 revisionid = 0;
2050
2051 mii_1000cr = mdio_read(dev, phyaddr, MII_CTRL1000);
2052 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2053 GMII_PHY_1000BASETCONTROL_PreferMaster;
2054 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2055
2056 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2057
2058 /* Set default phyparam */
2059 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2060 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2061
2062 /* Reset PHY */
2063 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2064 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2065
2066 }
2067}
2068
2069static int ipg_hw_init(struct net_device *dev)
2070{
2071 struct ipg_nic_private *sp = netdev_priv(dev);
2072 void __iomem *ioaddr = sp->ioaddr;
2073 unsigned int i;
2074 int rc;
2075
2076 /* Read/Write and Reset EEPROM Value Jesse20040128EEPROM_VALUE */
2077 /* Read LED Mode Configuration from EEPROM */
2078 sp->LED_Mode = read_eeprom(dev, 6);
2079
2080 /* Reset all functions within the IPG. Do not assert
2081 * RST_OUT as not compatible with some PHYs.
2082 */
2083 rc = ipg_reset(dev, IPG_RESET_MASK);
2084 if (rc < 0)
2085 goto out;
2086
2087 ipg_init_mii(dev);
2088
2089 /* Read MAC Address from EEPROM */
2090 for (i = 0; i < 3; i++)
2091 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2092
2093 for (i = 0; i < 3; i++)
2094 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2095
2096 /* Set station address in ethernet_device structure. */
2097 dev->dev_addr[0] = ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2098 dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2099 dev->dev_addr[2] = ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2100 dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2101 dev->dev_addr[4] = ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2102 dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2103out:
2104 return rc;
2105}
2106
2107static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2108{
2109 struct ipg_nic_private *sp = netdev_priv(dev);
2110 int rc;
2111
2112 mutex_lock(&sp->mii_mutex);
2113 rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2114 mutex_unlock(&sp->mii_mutex);
2115
2116 return rc;
2117}
2118
2119static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2120{
2121 /* Function to accomodate changes to Maximum Transfer Unit
2122 * (or MTU) of IPG NIC. Cannot use default function since
2123 * the default will not allow for MTU > 1500 bytes.
2124 */
2125
2126 IPG_DEBUG_MSG("_nic_change_mtu\n");
2127
2128 /* Check that the new MTU value is between 68 (14 byte header, 46
2129 * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2130 * corresponds to the MAXFRAMESIZE register in the IPG.
2131 */
2132 if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2133 return -EINVAL;
2134
2135 dev->mtu = new_mtu;
2136
2137 return 0;
2138}
2139
2140static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2141{
2142 struct ipg_nic_private *sp = netdev_priv(dev);
2143 int rc;
2144
2145 mutex_lock(&sp->mii_mutex);
2146 rc = mii_ethtool_gset(&sp->mii_if, cmd);
2147 mutex_unlock(&sp->mii_mutex);
2148
2149 return rc;
2150}
2151
2152static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2153{
2154 struct ipg_nic_private *sp = netdev_priv(dev);
2155 int rc;
2156
2157 mutex_lock(&sp->mii_mutex);
2158 rc = mii_ethtool_sset(&sp->mii_if, cmd);
2159 mutex_unlock(&sp->mii_mutex);
2160
2161 return rc;
2162}
2163
2164static int ipg_nway_reset(struct net_device *dev)
2165{
2166 struct ipg_nic_private *sp = netdev_priv(dev);
2167 int rc;
2168
2169 mutex_lock(&sp->mii_mutex);
2170 rc = mii_nway_restart(&sp->mii_if);
2171 mutex_unlock(&sp->mii_mutex);
2172
2173 return rc;
2174}
2175
2176static struct ethtool_ops ipg_ethtool_ops = {
2177 .get_settings = ipg_get_settings,
2178 .set_settings = ipg_set_settings,
2179 .nway_reset = ipg_nway_reset,
2180};
2181
2182static void ipg_remove(struct pci_dev *pdev)
2183{
2184 struct net_device *dev = pci_get_drvdata(pdev);
2185 struct ipg_nic_private *sp = netdev_priv(dev);
2186
2187 IPG_DEBUG_MSG("_remove\n");
2188
2189 /* Un-register Ethernet device. */
2190 unregister_netdev(dev);
2191
2192 pci_iounmap(pdev, sp->ioaddr);
2193
2194 pci_release_regions(pdev);
2195
2196 free_netdev(dev);
2197 pci_disable_device(pdev);
2198 pci_set_drvdata(pdev, NULL);
2199}
2200
2201static int __devinit ipg_probe(struct pci_dev *pdev,
2202 const struct pci_device_id *id)
2203{
2204 unsigned int i = id->driver_data;
2205 struct ipg_nic_private *sp;
2206 struct net_device *dev;
2207 void __iomem *ioaddr;
2208 int rc;
2209
2210 rc = pci_enable_device(pdev);
2211 if (rc < 0)
2212 goto out;
2213
2214 printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2215
2216 pci_set_master(pdev);
2217
2218 rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2219 if (rc < 0) {
2220 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2221 if (rc < 0) {
2222 printk(KERN_ERR "%s: DMA config failed.\n",
2223 pci_name(pdev));
2224 goto err_disable_0;
2225 }
2226 }
2227
2228 /*
2229 * Initialize net device.
2230 */
2231 dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2232 if (!dev) {
2233 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2234 rc = -ENOMEM;
2235 goto err_disable_0;
2236 }
2237
2238 sp = netdev_priv(dev);
2239 spin_lock_init(&sp->lock);
2240 mutex_init(&sp->mii_mutex);
2241
2242 /* Declare IPG NIC functions for Ethernet device methods.
2243 */
2244 dev->open = &ipg_nic_open;
2245 dev->stop = &ipg_nic_stop;
2246 dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2247 dev->get_stats = &ipg_nic_get_stats;
2248 dev->set_multicast_list = &ipg_nic_set_multicast_list;
2249 dev->do_ioctl = ipg_ioctl;
2250 dev->tx_timeout = ipg_tx_timeout;
2251 dev->change_mtu = &ipg_nic_change_mtu;
2252
2253 SET_NETDEV_DEV(dev, &pdev->dev);
2254 SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2255
2256 rc = pci_request_regions(pdev, DRV_NAME);
2257 if (rc)
2258 goto err_free_dev_1;
2259
2260 ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2261 if (!ioaddr) {
2262 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2263 rc = -EIO;
2264 goto err_release_regions_2;
2265 }
2266
2267 /* Save the pointer to the PCI device information. */
2268 sp->ioaddr = ioaddr;
2269 sp->pdev = pdev;
2270 sp->dev = dev;
2271
2272 INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2273
2274 pci_set_drvdata(pdev, dev);
2275
2276 rc = ipg_hw_init(dev);
2277 if (rc < 0)
2278 goto err_unmap_3;
2279
2280 rc = register_netdev(dev);
2281 if (rc < 0)
2282 goto err_unmap_3;
2283
2284 printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2285out:
2286 return rc;
2287
2288err_unmap_3:
2289 pci_iounmap(pdev, ioaddr);
2290err_release_regions_2:
2291 pci_release_regions(pdev);
2292err_free_dev_1:
2293 free_netdev(dev);
2294err_disable_0:
2295 pci_disable_device(pdev);
2296 goto out;
2297}
2298
2299static struct pci_driver ipg_pci_driver = {
2300 .name = IPG_DRIVER_NAME,
2301 .id_table = ipg_pci_tbl,
2302 .probe = ipg_probe,
2303 .remove = __devexit_p(ipg_remove),
2304};
2305
2306static int __init ipg_init_module(void)
2307{
2308 return pci_register_driver(&ipg_pci_driver);
2309}
2310
2311static void __exit ipg_exit_module(void)
2312{
2313 pci_unregister_driver(&ipg_pci_driver);
2314}
2315
2316module_init(ipg_init_module);
2317module_exit(ipg_exit_module);
Linux kernel - Deliverables
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