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irda: via-ircc proper dma freeing
[deliverable/linux.git] / drivers / net / irda / nsc-ircc.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 *
3 * Filename: nsc-ircc.c
4 * Version: 1.0
5 * Description: Driver for the NSC PC'108 and PC'338 IrDA chipsets
6 * Status: Stable.
7 * Author: Dag Brattli <dagb@cs.uit.no>
8 * Created at: Sat Nov 7 21:43:15 1998
9 * Modified at: Wed Mar 1 11:29:34 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
11 *
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
14 * Copyright (c) 1998 Actisys Corp., www.actisys.com
ec4f32d5 15 * Copyright (c) 2000-2004 Jean Tourrilhes <jt@hpl.hp.com>
1da177e4
LT		 16 * All Rights Reserved
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
96de0e25 23 * Neither Dag Brattli nor University of Tromsø admit liability nor
1da177e4
LT		 24 * provide warranty for any of this software. This material is
25 * provided "AS-IS" and at no charge.
26 *
27 * Notice that all functions that needs to access the chip in _any_
28 * way, must save BSR register on entry, and restore it on exit.
29 * It is _very_ important to follow this policy!
30 *
31 * __u8 bank;
32 *
33 * bank = inb(iobase+BSR);
34 *
35 * do_your_stuff_here();
36 *
37 * outb(bank, iobase+BSR);
38 *
39 * If you find bugs in this file, its very likely that the same bug
40 * will also be in w83977af_ir.c since the implementations are quite
41 * similar.
42 *
43 ********************************************************************/
44
45#include <linux/module.h>
46
47#include <linux/kernel.h>
48#include <linux/types.h>
49#include <linux/skbuff.h>
50#include <linux/netdevice.h>
51#include <linux/ioport.h>
52#include <linux/delay.h>
53#include <linux/slab.h>
54#include <linux/init.h>
55#include <linux/rtnetlink.h>
56#include <linux/dma-mapping.h>
ec4f32d5 57#include <linux/pnp.h>
3b99b93b 58#include <linux/platform_device.h>
1da177e4
LT		 59
60#include <asm/io.h>
61#include <asm/dma.h>
62#include <asm/byteorder.h>
63
1da177e4
LT		 64#include <net/irda/wrapper.h>
65#include <net/irda/irda.h>
66#include <net/irda/irda_device.h>
67
68#include "nsc-ircc.h"
69
70#define CHIP_IO_EXTENT 8
71#define BROKEN_DONGLE_ID
72
73static char *driver_name = "nsc-ircc";
74
3b99b93b
DT		 75/* Power Management */
76#define NSC_IRCC_DRIVER_NAME "nsc-ircc"
77static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
78static int nsc_ircc_resume(struct platform_device *dev);
79
80static struct platform_driver nsc_ircc_driver = {
81 .suspend = nsc_ircc_suspend,
82 .resume = nsc_ircc_resume,
83 .driver = {
84 .name = NSC_IRCC_DRIVER_NAME,
85 },
86};
87
1da177e4
LT		 88/* Module parameters */
89static int qos_mtt_bits = 0x07; /* 1 ms or more */
90static int dongle_id;
91
92/* Use BIOS settions by default, but user may supply module parameters */
0ed79c9b
JT		 93static unsigned int io[] = { ~0, ~0, ~0, ~0, ~0 };
94static unsigned int irq[] = { 0, 0, 0, 0, 0 };
95static unsigned int dma[] = { 0, 0, 0, 0, 0 };
1da177e4
LT		 96
97static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info);
98static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info);
99static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info);
100static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info);
101static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info);
102static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info);
c17f888f 103#ifdef CONFIG_PNP
ec4f32d5 104static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id);
c17f888f 105#endif
1da177e4
LT		 106
107/* These are the known NSC chips */
108static nsc_chip_t chips[] = {
109/* Name, {cfg registers}, chip id index reg, chip id expected value, revision mask */
110 { "PC87108", { 0x150, 0x398, 0xea }, 0x05, 0x10, 0xf0,
111 nsc_ircc_probe_108, nsc_ircc_init_108 },
112 { "PC87338", { 0x398, 0x15c, 0x2e }, 0x08, 0xb0, 0xf8,
113 nsc_ircc_probe_338, nsc_ircc_init_338 },
114 /* Contributed by Steffen Pingel - IBM X40 */
2fd19a68 115 { "PC8738x", { 0x164e, 0x4e, 0x2e }, 0x20, 0xf4, 0xff,
1da177e4
LT		 116 nsc_ircc_probe_39x, nsc_ircc_init_39x },
117 /* Contributed by Jan Frey - IBM A30/A31 */
118 { "PC8739x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xea, 0xff,
119 nsc_ircc_probe_39x, nsc_ircc_init_39x },
d83561a4
BC		 120 /* IBM ThinkPads using PC8738x (T60/X60/Z60) */
121 { "IBM-PC8738x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf4, 0xff,
122 nsc_ircc_probe_39x, nsc_ircc_init_39x },
123 /* IBM ThinkPads using PC8394T (T43/R52/?) */
124 { "IBM-PC8394T", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf9, 0xff,
125 nsc_ircc_probe_39x, nsc_ircc_init_39x },
1da177e4
LT		 126 { NULL }
127};
128
0ed79c9b 129static struct nsc_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL, NULL };
1da177e4
LT		 130
131static char *dongle_types[] = {
132 "Differential serial interface",
133 "Differential serial interface",
134 "Reserved",
135 "Reserved",
136 "Sharp RY5HD01",
137 "Reserved",
138 "Single-ended serial interface",
139 "Consumer-IR only",
140 "HP HSDL-2300, HP HSDL-3600/HSDL-3610",
141 "IBM31T1100 or Temic TFDS6000/TFDS6500",
142 "Reserved",
143 "Reserved",
144 "HP HSDL-1100/HSDL-2100",
145 "HP HSDL-1100/HSDL-2100",
146 "Supports SIR Mode only",
147 "No dongle connected",
148};
149
ec4f32d5
JT		 150/* PNP probing */
151static chipio_t pnp_info;
152static const struct pnp_device_id nsc_ircc_pnp_table[] = {
153 { .id = "NSC6001", .driver_data = 0 },
154 { .id = "IBM0071", .driver_data = 0 },
155 { }
156};
157
158MODULE_DEVICE_TABLE(pnp, nsc_ircc_pnp_table);
159
160static struct pnp_driver nsc_ircc_pnp_driver = {
c17f888f 161#ifdef CONFIG_PNP
ec4f32d5
JT		 162 .name = "nsc-ircc",
163 .id_table = nsc_ircc_pnp_table,
164 .probe = nsc_ircc_pnp_probe,
c17f888f 165#endif
ec4f32d5
JT		 166};
167
1da177e4 168/* Some prototypes */
ec4f32d5 169static int nsc_ircc_open(chipio_t *info);
1da177e4
LT		 170static int nsc_ircc_close(struct nsc_ircc_cb *self);
171static int nsc_ircc_setup(chipio_t *info);
172static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self);
173static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self);
174static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase);
175static int nsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
176static int nsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
177static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
178static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase);
179static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 baud);
180static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self);
181static int nsc_ircc_read_dongle_id (int iobase);
182static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id);
183
184static int nsc_ircc_net_open(struct net_device *dev);
185static int nsc_ircc_net_close(struct net_device *dev);
186static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
187static struct net_device_stats *nsc_ircc_net_get_stats(struct net_device *dev);
1da177e4 188
ec4f32d5
JT		 189/* Globals */
190static int pnp_registered;
191static int pnp_succeeded;
192
1da177e4
LT		 193/*
194 * Function nsc_ircc_init ()
195 *
196 * Initialize chip. Just try to find out how many chips we are dealing with
197 * and where they are
198 */
199static int __init nsc_ircc_init(void)
200{
201 chipio_t info;
202 nsc_chip_t *chip;
ec4f32d5 203 int ret;
1da177e4
LT		 204 int cfg_base;
205 int cfg, id;
206 int reg;
207 int i = 0;
208
3b99b93b
DT		 209 ret = platform_driver_register(&nsc_ircc_driver);
210 if (ret) {
211 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
212 return ret;
213 }
214
ec4f32d5
JT		 215 /* Register with PnP subsystem to detect disable ports */
216 ret = pnp_register_driver(&nsc_ircc_pnp_driver);
217
803d0abb 218 if (!ret)
ec4f32d5
JT		 219 pnp_registered = 1;
220
221 ret = -ENODEV;
222
1da177e4 223 /* Probe for all the NSC chipsets we know about */
ec4f32d5 224 for (chip = chips; chip->name ; chip++) {
1da177e4
LT		 225 IRDA_DEBUG(2, "%s(), Probing for %s ...\n", __FUNCTION__,
226 chip->name);
227
228 /* Try all config registers for this chip */
ec4f32d5 229 for (cfg = 0; cfg < ARRAY_SIZE(chip->cfg); cfg++) {
1da177e4
LT		 230 cfg_base = chip->cfg[cfg];
231 if (!cfg_base)
232 continue;
1da177e4
LT		 233
234 /* Read index register */
235 reg = inb(cfg_base);
236 if (reg == 0xff) {
237 IRDA_DEBUG(2, "%s() no chip at 0x%03x\n", __FUNCTION__, cfg_base);
238 continue;
239 }
240
241 /* Read chip identification register */
242 outb(chip->cid_index, cfg_base);
243 id = inb(cfg_base+1);
244 if ((id & chip->cid_mask) == chip->cid_value) {
245 IRDA_DEBUG(2, "%s() Found %s chip, revision=%d\n",
246 __FUNCTION__, chip->name, id & ~chip->cid_mask);
ec4f32d5
JT		 247
248 /*
249 * If we found a correct PnP setting,
250 * we first try it.
251 */
252 if (pnp_succeeded) {
253 memset(&info, 0, sizeof(chipio_t));
254 info.cfg_base = cfg_base;
255 info.fir_base = pnp_info.fir_base;
256 info.dma = pnp_info.dma;
257 info.irq = pnp_info.irq;
258
259 if (info.fir_base < 0x2000) {
260 IRDA_MESSAGE("%s, chip->init\n", driver_name);
261 chip->init(chip, &info);
262 } else
263 chip->probe(chip, &info);
264
265 if (nsc_ircc_open(&info) >= 0)
266 ret = 0;
267 }
268
269 /*
270 * Opening based on PnP values failed.
271 * Let's fallback to user values, or probe
272 * the chip.
273 */
274 if (ret) {
275 IRDA_DEBUG(2, "%s, PnP init failed\n", driver_name);
276 memset(&info, 0, sizeof(chipio_t));
277 info.cfg_base = cfg_base;
278 info.fir_base = io[i];
279 info.dma = dma[i];
280 info.irq = irq[i];
281
282 /*
283 * If the user supplies the base address, then
284 * we init the chip, if not we probe the values
285 * set by the BIOS
286 */
287 if (io[i] < 0x2000) {
288 chip->init(chip, &info);
289 } else
290 chip->probe(chip, &info);
291
292 if (nsc_ircc_open(&info) >= 0)
293 ret = 0;
294 }
1da177e4
LT		 295 i++;
296 } else {
297 IRDA_DEBUG(2, "%s(), Wrong chip id=0x%02x\n", __FUNCTION__, id);
298 }
299 }
ec4f32d5
JT		 300 }
301
302 if (ret) {
3b99b93b 303 platform_driver_unregister(&nsc_ircc_driver);
ec4f32d5
JT		 304 pnp_unregister_driver(&nsc_ircc_pnp_driver);
305 pnp_registered = 0;
1da177e4
LT		 306 }
307
308 return ret;
309}
310
311/*
312 * Function nsc_ircc_cleanup ()
313 *
314 * Close all configured chips
315 *
316 */
317static void __exit nsc_ircc_cleanup(void)
318{
319 int i;
320
ec4f32d5 321 for (i = 0; i < ARRAY_SIZE(dev_self); i++) {
1da177e4
LT		 322 if (dev_self[i])
323 nsc_ircc_close(dev_self[i]);
324 }
ec4f32d5 325
3b99b93b
DT		 326 platform_driver_unregister(&nsc_ircc_driver);
327
ec4f32d5
JT		 328 if (pnp_registered)
329 pnp_unregister_driver(&nsc_ircc_pnp_driver);
330
331 pnp_registered = 0;
1da177e4
LT		 332}
333
334/*
335 * Function nsc_ircc_open (iobase, irq)
336 *
337 * Open driver instance
338 *
339 */
ec4f32d5 340static int __init nsc_ircc_open(chipio_t *info)
1da177e4
LT		 341{
342 struct net_device *dev;
343 struct nsc_ircc_cb *self;
1da177e4 344 void *ret;
ec4f32d5 345 int err, chip_index;
1da177e4
LT		 346
347 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
348
ec4f32d5
JT		 349
350 for (chip_index = 0; chip_index < ARRAY_SIZE(dev_self); chip_index++) {
351 if (!dev_self[chip_index])
352 break;
353 }
354
355 if (chip_index == ARRAY_SIZE(dev_self)) {
356 IRDA_ERROR("%s(), maximum number of supported chips reached!\n", __FUNCTION__);
357 return -ENOMEM;
358 }
359
1da177e4
LT		 360 IRDA_MESSAGE("%s, Found chip at base=0x%03x\n", driver_name,
361 info->cfg_base);
362
363 if ((nsc_ircc_setup(info)) == -1)
364 return -1;
365
366 IRDA_MESSAGE("%s, driver loaded (Dag Brattli)\n", driver_name);
367
368 dev = alloc_irdadev(sizeof(struct nsc_ircc_cb));
369 if (dev == NULL) {
370 IRDA_ERROR("%s(), can't allocate memory for "
371 "control block!\n", __FUNCTION__);
372 return -ENOMEM;
373 }
374
375 self = dev->priv;
376 self->netdev = dev;
377 spin_lock_init(&self->lock);
378
379 /* Need to store self somewhere */
ec4f32d5
JT		 380 dev_self[chip_index] = self;
381 self->index = chip_index;
1da177e4
LT		 382
383 /* Initialize IO */
384 self->io.cfg_base = info->cfg_base;
385 self->io.fir_base = info->fir_base;
386 self->io.irq = info->irq;
387 self->io.fir_ext = CHIP_IO_EXTENT;
388 self->io.dma = info->dma;
389 self->io.fifo_size = 32;
390
391 /* Reserve the ioports that we need */
392 ret = request_region(self->io.fir_base, self->io.fir_ext, driver_name);
393 if (!ret) {
394 IRDA_WARNING("%s(), can't get iobase of 0x%03x\n",
395 __FUNCTION__, self->io.fir_base);
396 err = -ENODEV;
397 goto out1;
398 }
399
400 /* Initialize QoS for this device */
401 irda_init_max_qos_capabilies(&self->qos);
402
403 /* The only value we must override it the baudrate */
404 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
405 IR_115200|IR_576000|IR_1152000 |(IR_4000000 << 8);
406
407 self->qos.min_turn_time.bits = qos_mtt_bits;
408 irda_qos_bits_to_value(&self->qos);
409
410 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
411 self->rx_buff.truesize = 14384;
412 self->tx_buff.truesize = 14384;
413
414 /* Allocate memory if needed */
415 self->rx_buff.head =
416 dma_alloc_coherent(NULL, self->rx_buff.truesize,
417 &self->rx_buff_dma, GFP_KERNEL);
418 if (self->rx_buff.head == NULL) {
419 err = -ENOMEM;
420 goto out2;
421
422 }
423 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
424
425 self->tx_buff.head =
426 dma_alloc_coherent(NULL, self->tx_buff.truesize,
427 &self->tx_buff_dma, GFP_KERNEL);
428 if (self->tx_buff.head == NULL) {
429 err = -ENOMEM;
430 goto out3;
431 }
432 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
433
434 self->rx_buff.in_frame = FALSE;
435 self->rx_buff.state = OUTSIDE_FRAME;
436 self->tx_buff.data = self->tx_buff.head;
437 self->rx_buff.data = self->rx_buff.head;
438
439 /* Reset Tx queue info */
440 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
441 self->tx_fifo.tail = self->tx_buff.head;
442
443 /* Override the network functions we need to use */
1da177e4
LT		 444 dev->hard_start_xmit = nsc_ircc_hard_xmit_sir;
445 dev->open = nsc_ircc_net_open;
446 dev->stop = nsc_ircc_net_close;
447 dev->do_ioctl = nsc_ircc_net_ioctl;
448 dev->get_stats = nsc_ircc_net_get_stats;
449
450 err = register_netdev(dev);
451 if (err) {
452 IRDA_ERROR("%s(), register_netdev() failed!\n", __FUNCTION__);
453 goto out4;
454 }
455 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
456
457 /* Check if user has supplied a valid dongle id or not */
458 if ((dongle_id <= 0) ||
ec4f32d5 459 (dongle_id >= ARRAY_SIZE(dongle_types))) {
1da177e4
LT		 460 dongle_id = nsc_ircc_read_dongle_id(self->io.fir_base);
461
462 IRDA_MESSAGE("%s, Found dongle: %s\n", driver_name,
463 dongle_types[dongle_id]);
464 } else {
465 IRDA_MESSAGE("%s, Using dongle: %s\n", driver_name,
466 dongle_types[dongle_id]);
467 }
468
469 self->io.dongle_id = dongle_id;
470 nsc_ircc_init_dongle_interface(self->io.fir_base, dongle_id);
471
3b99b93b
DT		 472 self->pldev = platform_device_register_simple(NSC_IRCC_DRIVER_NAME,
473 self->index, NULL, 0);
474 if (IS_ERR(self->pldev)) {
475 err = PTR_ERR(self->pldev);
476 goto out5;
477 }
478 platform_set_drvdata(self->pldev, self);
1da177e4 479
ec4f32d5 480 return chip_index;
3b99b93b
DT		 481
482 out5:
483 unregister_netdev(dev);
1da177e4
LT		 484 out4:
485 dma_free_coherent(NULL, self->tx_buff.truesize,
486 self->tx_buff.head, self->tx_buff_dma);
487 out3:
488 dma_free_coherent(NULL, self->rx_buff.truesize,
489 self->rx_buff.head, self->rx_buff_dma);
490 out2:
491 release_region(self->io.fir_base, self->io.fir_ext);
492 out1:
493 free_netdev(dev);
ec4f32d5 494 dev_self[chip_index] = NULL;
1da177e4
LT		 495 return err;
496}
497
498/*
499 * Function nsc_ircc_close (self)
500 *
501 * Close driver instance
502 *
503 */
504static int __exit nsc_ircc_close(struct nsc_ircc_cb *self)
505{
506 int iobase;
507
508 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
509
510 IRDA_ASSERT(self != NULL, return -1;);
511
512 iobase = self->io.fir_base;
513
3b99b93b
DT		 514 platform_device_unregister(self->pldev);
515
1da177e4
LT		 516 /* Remove netdevice */
517 unregister_netdev(self->netdev);
518
519 /* Release the PORT that this driver is using */
520 IRDA_DEBUG(4, "%s(), Releasing Region %03x\n",
521 __FUNCTION__, self->io.fir_base);
522 release_region(self->io.fir_base, self->io.fir_ext);
523
524 if (self->tx_buff.head)
525 dma_free_coherent(NULL, self->tx_buff.truesize,
526 self->tx_buff.head, self->tx_buff_dma);
527
528 if (self->rx_buff.head)
529 dma_free_coherent(NULL, self->rx_buff.truesize,
530 self->rx_buff.head, self->rx_buff_dma);
531
532 dev_self[self->index] = NULL;
533 free_netdev(self->netdev);
534
535 return 0;
536}
537
538/*
539 * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma)
540 *
541 * Initialize the NSC '108 chip
542 *
543 */
544static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info)
545{
546 int cfg_base = info->cfg_base;
547 __u8 temp=0;
548
549 outb(2, cfg_base); /* Mode Control Register (MCTL) */
550 outb(0x00, cfg_base+1); /* Disable device */
551
552 /* Base Address and Interrupt Control Register (BAIC) */
553 outb(CFG_108_BAIC, cfg_base);
554 switch (info->fir_base) {
555 case 0x3e8: outb(0x14, cfg_base+1); break;
556 case 0x2e8: outb(0x15, cfg_base+1); break;
557 case 0x3f8: outb(0x16, cfg_base+1); break;
558 case 0x2f8: outb(0x17, cfg_base+1); break;
559 default: IRDA_ERROR("%s(), invalid base_address", __FUNCTION__);
560 }
561
562 /* Control Signal Routing Register (CSRT) */
563 switch (info->irq) {
564 case 3: temp = 0x01; break;
565 case 4: temp = 0x02; break;
566 case 5: temp = 0x03; break;
567 case 7: temp = 0x04; break;
568 case 9: temp = 0x05; break;
569 case 11: temp = 0x06; break;
570 case 15: temp = 0x07; break;
571 default: IRDA_ERROR("%s(), invalid irq", __FUNCTION__);
572 }
573 outb(CFG_108_CSRT, cfg_base);
574
575 switch (info->dma) {
576 case 0: outb(0x08+temp, cfg_base+1); break;
577 case 1: outb(0x10+temp, cfg_base+1); break;
578 case 3: outb(0x18+temp, cfg_base+1); break;
579 default: IRDA_ERROR("%s(), invalid dma", __FUNCTION__);
580 }
581
582 outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */
583 outb(0x03, cfg_base+1); /* Enable device */
584
585 return 0;
586}
587
588/*
589 * Function nsc_ircc_probe_108 (chip, info)
590 *
591 *
592 *
593 */
594static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info)
595{
596 int cfg_base = info->cfg_base;
597 int reg;
598
599 /* Read address and interrupt control register (BAIC) */
600 outb(CFG_108_BAIC, cfg_base);
601 reg = inb(cfg_base+1);
602
603 switch (reg & 0x03) {
604 case 0:
605 info->fir_base = 0x3e8;
606 break;
607 case 1:
608 info->fir_base = 0x2e8;
609 break;
610 case 2:
611 info->fir_base = 0x3f8;
612 break;
613 case 3:
614 info->fir_base = 0x2f8;
615 break;
616 }
617 info->sir_base = info->fir_base;
618 IRDA_DEBUG(2, "%s(), probing fir_base=0x%03x\n", __FUNCTION__,
619 info->fir_base);
620
621 /* Read control signals routing register (CSRT) */
622 outb(CFG_108_CSRT, cfg_base);
623 reg = inb(cfg_base+1);
624
625 switch (reg & 0x07) {
626 case 0:
627 info->irq = -1;
628 break;
629 case 1:
630 info->irq = 3;
631 break;
632 case 2:
633 info->irq = 4;
634 break;
635 case 3:
636 info->irq = 5;
637 break;
638 case 4:
639 info->irq = 7;
640 break;
641 case 5:
642 info->irq = 9;
643 break;
644 case 6:
645 info->irq = 11;
646 break;
647 case 7:
648 info->irq = 15;
649 break;
650 }
651 IRDA_DEBUG(2, "%s(), probing irq=%d\n", __FUNCTION__, info->irq);
652
653 /* Currently we only read Rx DMA but it will also be used for Tx */
654 switch ((reg >> 3) & 0x03) {
655 case 0:
656 info->dma = -1;
657 break;
658 case 1:
659 info->dma = 0;
660 break;
661 case 2:
662 info->dma = 1;
663 break;
664 case 3:
665 info->dma = 3;
666 break;
667 }
668 IRDA_DEBUG(2, "%s(), probing dma=%d\n", __FUNCTION__, info->dma);
669
670 /* Read mode control register (MCTL) */
671 outb(CFG_108_MCTL, cfg_base);
672 reg = inb(cfg_base+1);
673
674 info->enabled = reg & 0x01;
675 info->suspended = !((reg >> 1) & 0x01);
676
677 return 0;
678}
679
680/*
681 * Function nsc_ircc_init_338 (chip, info)
682 *
683 * Initialize the NSC '338 chip. Remember that the 87338 needs two
684 * consecutive writes to the data registers while CPU interrupts are
685 * disabled. The 97338 does not require this, but shouldn't be any
686 * harm if we do it anyway.
687 */
688static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info)
689{
690 /* No init yet */
691
692 return 0;
693}
694
695/*
696 * Function nsc_ircc_probe_338 (chip, info)
697 *
698 *
699 *
700 */
701static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info)
702{
703 int cfg_base = info->cfg_base;
704 int reg, com = 0;
705 int pnp;
706
707 /* Read funtion enable register (FER) */
708 outb(CFG_338_FER, cfg_base);
709 reg = inb(cfg_base+1);
710
711 info->enabled = (reg >> 2) & 0x01;
712
713 /* Check if we are in Legacy or PnP mode */
714 outb(CFG_338_PNP0, cfg_base);
715 reg = inb(cfg_base+1);
716
717 pnp = (reg >> 3) & 0x01;
718 if (pnp) {
719 IRDA_DEBUG(2, "(), Chip is in PnP mode\n");
720 outb(0x46, cfg_base);
721 reg = (inb(cfg_base+1) & 0xfe) << 2;
722
723 outb(0x47, cfg_base);
724 reg |= ((inb(cfg_base+1) & 0xfc) << 8);
725
726 info->fir_base = reg;
727 } else {
728 /* Read function address register (FAR) */
729 outb(CFG_338_FAR, cfg_base);
730 reg = inb(cfg_base+1);
731
732 switch ((reg >> 4) & 0x03) {
733 case 0:
734 info->fir_base = 0x3f8;
735 break;
736 case 1:
737 info->fir_base = 0x2f8;
738 break;
739 case 2:
740 com = 3;
741 break;
742 case 3:
743 com = 4;
744 break;
745 }
746
747 if (com) {
748 switch ((reg >> 6) & 0x03) {
749 case 0:
750 if (com == 3)
751 info->fir_base = 0x3e8;
752 else
753 info->fir_base = 0x2e8;
754 break;
755 case 1:
756 if (com == 3)
757 info->fir_base = 0x338;
758 else
759 info->fir_base = 0x238;
760 break;
761 case 2:
762 if (com == 3)
763 info->fir_base = 0x2e8;
764 else
765 info->fir_base = 0x2e0;
766 break;
767 case 3:
768 if (com == 3)
769 info->fir_base = 0x220;
770 else
771 info->fir_base = 0x228;
772 break;
773 }
774 }
775 }
776 info->sir_base = info->fir_base;
777
778 /* Read PnP register 1 (PNP1) */
779 outb(CFG_338_PNP1, cfg_base);
780 reg = inb(cfg_base+1);
781
782 info->irq = reg >> 4;
783
784 /* Read PnP register 3 (PNP3) */
785 outb(CFG_338_PNP3, cfg_base);
786 reg = inb(cfg_base+1);
787
788 info->dma = (reg & 0x07) - 1;
789
790 /* Read power and test register (PTR) */
791 outb(CFG_338_PTR, cfg_base);
792 reg = inb(cfg_base+1);
793
794 info->suspended = reg & 0x01;
795
796 return 0;
797}
798
799
800/*
801 * Function nsc_ircc_init_39x (chip, info)
802 *
803 * Now that we know it's a '39x (see probe below), we need to
804 * configure it so we can use it.
805 *
806 * The NSC '338 chip is a Super I/O chip with a "bank" architecture,
807 * the configuration of the different functionality (serial, parallel,
808 * floppy...) are each in a different bank (Logical Device Number).
809 * The base address, irq and dma configuration registers are common
810 * to all functionalities (index 0x30 to 0x7F).
811 * There is only one configuration register specific to the
812 * serial port, CFG_39X_SPC.
813 * JeanII
814 *
815 * Note : this code was written by Jan Frey <janfrey@web.de>
816 */
817static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info)
818{
819 int cfg_base = info->cfg_base;
820 int enabled;
821
7f927fcc 822 /* User is sure about his config... accept it. */
1da177e4
LT		 823 IRDA_DEBUG(2, "%s(): nsc_ircc_init_39x (user settings): "
824 "io=0x%04x, irq=%d, dma=%d\n",
825 __FUNCTION__, info->fir_base, info->irq, info->dma);
826
827 /* Access bank for SP2 */
828 outb(CFG_39X_LDN, cfg_base);
829 outb(0x02, cfg_base+1);
830
831 /* Configure SP2 */
832
833 /* We want to enable the device if not enabled */
834 outb(CFG_39X_ACT, cfg_base);
835 enabled = inb(cfg_base+1) & 0x01;
836
837 if (!enabled) {
838 /* Enable the device */
839 outb(CFG_39X_SIOCF1, cfg_base);
840 outb(0x01, cfg_base+1);
841 /* May want to update info->enabled. Jean II */
842 }
843
844 /* Enable UART bank switching (bit 7) ; Sets the chip to normal
845 * power mode (wake up from sleep mode) (bit 1) */
846 outb(CFG_39X_SPC, cfg_base);
847 outb(0x82, cfg_base+1);
848
849 return 0;
850}
851
852/*
853 * Function nsc_ircc_probe_39x (chip, info)
854 *
855 * Test if we really have a '39x chip at the given address
856 *
857 * Note : this code was written by Jan Frey <janfrey@web.de>
858 */
859static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info)
860{
861 int cfg_base = info->cfg_base;
862 int reg1, reg2, irq, irqt, dma1, dma2;
863 int enabled, susp;
864
865 IRDA_DEBUG(2, "%s(), nsc_ircc_probe_39x, base=%d\n",
866 __FUNCTION__, cfg_base);
867
868 /* This function should be executed with irq off to avoid
869 * another driver messing with the Super I/O bank - Jean II */
870
871 /* Access bank for SP2 */
872 outb(CFG_39X_LDN, cfg_base);
873 outb(0x02, cfg_base+1);
874
875 /* Read infos about SP2 ; store in info struct */
876 outb(CFG_39X_BASEH, cfg_base);
877 reg1 = inb(cfg_base+1);
878 outb(CFG_39X_BASEL, cfg_base);
879 reg2 = inb(cfg_base+1);
880 info->fir_base = (reg1 << 8) | reg2;
881
882 outb(CFG_39X_IRQNUM, cfg_base);
883 irq = inb(cfg_base+1);
884 outb(CFG_39X_IRQSEL, cfg_base);
885 irqt = inb(cfg_base+1);
886 info->irq = irq;
887
888 outb(CFG_39X_DMA0, cfg_base);
889 dma1 = inb(cfg_base+1);
890 outb(CFG_39X_DMA1, cfg_base);
891 dma2 = inb(cfg_base+1);
892 info->dma = dma1 -1;
893
894 outb(CFG_39X_ACT, cfg_base);
895 info->enabled = enabled = inb(cfg_base+1) & 0x01;
896
897 outb(CFG_39X_SPC, cfg_base);
898 susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1);
899
900 IRDA_DEBUG(2, "%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n", __FUNCTION__, reg1,reg2,irq,irqt,dma1,dma2,enabled,susp);
901
902 /* Configure SP2 */
903
904 /* We want to enable the device if not enabled */
905 outb(CFG_39X_ACT, cfg_base);
906 enabled = inb(cfg_base+1) & 0x01;
907
908 if (!enabled) {
909 /* Enable the device */
910 outb(CFG_39X_SIOCF1, cfg_base);
911 outb(0x01, cfg_base+1);
912 /* May want to update info->enabled. Jean II */
913 }
914
915 /* Enable UART bank switching (bit 7) ; Sets the chip to normal
916 * power mode (wake up from sleep mode) (bit 1) */
917 outb(CFG_39X_SPC, cfg_base);
918 outb(0x82, cfg_base+1);
919
920 return 0;
921}
922
c17f888f 923#ifdef CONFIG_PNP
ec4f32d5
JT		 924/* PNP probing */
925static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
926{
927 memset(&pnp_info, 0, sizeof(chipio_t));
928 pnp_info.irq = -1;
929 pnp_info.dma = -1;
930 pnp_succeeded = 1;
931
932 /* There don't seem to be any way to get the cfg_base.
933 * On my box, cfg_base is in the PnP descriptor of the
934 * motherboard. Oh well... Jean II */
935
936 if (pnp_port_valid(dev, 0) &&
937 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED))
938 pnp_info.fir_base = pnp_port_start(dev, 0);
939
940 if (pnp_irq_valid(dev, 0) &&
941 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED))
942 pnp_info.irq = pnp_irq(dev, 0);
943
944 if (pnp_dma_valid(dev, 0) &&
945 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED))
946 pnp_info.dma = pnp_dma(dev, 0);
947
948 IRDA_DEBUG(0, "%s() : From PnP, found firbase 0x%03X ; irq %d ; dma %d.\n",
949 __FUNCTION__, pnp_info.fir_base, pnp_info.irq, pnp_info.dma);
950
951 if((pnp_info.fir_base == 0) ||
952 (pnp_info.irq == -1) || (pnp_info.dma == -1)) {
953 /* Returning an error will disable the device. Yuck ! */
954 //return -EINVAL;
955 pnp_succeeded = 0;
956 }
957
958 return 0;
959}
c17f888f 960#endif
ec4f32d5 961
1da177e4
LT		 962/*
963 * Function nsc_ircc_setup (info)
964 *
965 * Returns non-negative on success.
966 *
967 */
968static int nsc_ircc_setup(chipio_t *info)
969{
970 int version;
971 int iobase = info->fir_base;
972
973 /* Read the Module ID */
974 switch_bank(iobase, BANK3);
975 version = inb(iobase+MID);
976
977 IRDA_DEBUG(2, "%s() Driver %s Found chip version %02x\n",
978 __FUNCTION__, driver_name, version);
979
980 /* Should be 0x2? */
981 if (0x20 != (version & 0xf0)) {
982 IRDA_ERROR("%s, Wrong chip version %02x\n",
983 driver_name, version);
984 return -1;
985 }
986
987 /* Switch to advanced mode */
988 switch_bank(iobase, BANK2);
989 outb(ECR1_EXT_SL, iobase+ECR1);
990 switch_bank(iobase, BANK0);
991
992 /* Set FIFO threshold to TX17, RX16, reset and enable FIFO's */
993 switch_bank(iobase, BANK0);
994 outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
995
996 outb(0x03, iobase+LCR); /* 8 bit word length */
997 outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/
998
999 /* Set FIFO size to 32 */
1000 switch_bank(iobase, BANK2);
1001 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
1002
1003 /* IRCR2: FEND_MD is not set */
1004 switch_bank(iobase, BANK5);
1005 outb(0x02, iobase+4);
1006
1007 /* Make sure that some defaults are OK */
1008 switch_bank(iobase, BANK6);
1009 outb(0x20, iobase+0); /* Set 32 bits FIR CRC */
1010 outb(0x0a, iobase+1); /* Set MIR pulse width */
1011 outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */
1012 outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */
1013
1014 /* Enable receive interrupts */
1015 switch_bank(iobase, BANK0);
1016 outb(IER_RXHDL_IE, iobase+IER);
1017
1018 return 0;
1019}
1020
1021/*
1022 * Function nsc_ircc_read_dongle_id (void)
1023 *
1024 * Try to read dongle indentification. This procedure needs to be executed
1025 * once after power-on/reset. It also needs to be used whenever you suspect
1026 * that the user may have plugged/unplugged the IrDA Dongle.
1027 */
1028static int nsc_ircc_read_dongle_id (int iobase)
1029{
1030 int dongle_id;
1031 __u8 bank;
1032
1033 bank = inb(iobase+BSR);
1034
1035 /* Select Bank 7 */
1036 switch_bank(iobase, BANK7);
1037
1038 /* IRCFG4: IRSL0_DS and IRSL21_DS are cleared */
1039 outb(0x00, iobase+7);
1040
1041 /* ID0, 1, and 2 are pulled up/down very slowly */
1042 udelay(50);
1043
1044 /* IRCFG1: read the ID bits */
1045 dongle_id = inb(iobase+4) & 0x0f;
1046
1047#ifdef BROKEN_DONGLE_ID
1048 if (dongle_id == 0x0a)
1049 dongle_id = 0x09;
1050#endif
1051 /* Go back to bank 0 before returning */
1052 switch_bank(iobase, BANK0);
1053
1054 outb(bank, iobase+BSR);
1055
1056 return dongle_id;
1057}
1058
1059/*
1060 * Function nsc_ircc_init_dongle_interface (iobase, dongle_id)
1061 *
1062 * This function initializes the dongle for the transceiver that is
1063 * used. This procedure needs to be executed once after
1064 * power-on/reset. It also needs to be used whenever you suspect that
1065 * the dongle is changed.
1066 */
1067static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id)
1068{
1069 int bank;
1070
1071 /* Save current bank */
1072 bank = inb(iobase+BSR);
1073
1074 /* Select Bank 7 */
1075 switch_bank(iobase, BANK7);
1076
1077 /* IRCFG4: set according to dongle_id */
1078 switch (dongle_id) {
1079 case 0x00: /* same as */
1080 case 0x01: /* Differential serial interface */
1081 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1082 __FUNCTION__, dongle_types[dongle_id]);
1083 break;
1084 case 0x02: /* same as */
1085 case 0x03: /* Reserved */
1086 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1087 __FUNCTION__, dongle_types[dongle_id]);
1088 break;
1089 case 0x04: /* Sharp RY5HD01 */
1090 break;
1091 case 0x05: /* Reserved, but this is what the Thinkpad reports */
1092 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1093 __FUNCTION__, dongle_types[dongle_id]);
1094 break;
1095 case 0x06: /* Single-ended serial interface */
1096 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1097 __FUNCTION__, dongle_types[dongle_id]);
1098 break;
1099 case 0x07: /* Consumer-IR only */
1100 IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
1101 __FUNCTION__, dongle_types[dongle_id]);
1102 break;
1103 case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
1104 IRDA_DEBUG(0, "%s(), %s\n",
1105 __FUNCTION__, dongle_types[dongle_id]);
1106 break;
1107 case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
1108 outb(0x28, iobase+7); /* Set irsl[0-2] as output */
1109 break;
1110 case 0x0A: /* same as */
1111 case 0x0B: /* Reserved */
1112 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1113 __FUNCTION__, dongle_types[dongle_id]);
1114 break;
1115 case 0x0C: /* same as */
1116 case 0x0D: /* HP HSDL-1100/HSDL-2100 */
1117 /*
1118 * Set irsl0 as input, irsl[1-2] as output, and separate
1119 * inputs are used for SIR and MIR/FIR
1120 */
1121 outb(0x48, iobase+7);
1122 break;
1123 case 0x0E: /* Supports SIR Mode only */
1124 outb(0x28, iobase+7); /* Set irsl[0-2] as output */
1125 break;
1126 case 0x0F: /* No dongle connected */
1127 IRDA_DEBUG(0, "%s(), %s\n",
1128 __FUNCTION__, dongle_types[dongle_id]);
1129
1130 switch_bank(iobase, BANK0);
1131 outb(0x62, iobase+MCR);
1132 break;
1133 default:
1134 IRDA_DEBUG(0, "%s(), invalid dongle_id %#x",
1135 __FUNCTION__, dongle_id);
1136 }
1137
1138 /* IRCFG1: IRSL1 and 2 are set to IrDA mode */
1139 outb(0x00, iobase+4);
1140
1141 /* Restore bank register */
1142 outb(bank, iobase+BSR);
1143
1144} /* set_up_dongle_interface */
1145
1146/*
1147 * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id)
1148 *
1149 * Change speed of the attach dongle
1150 *
1151 */
1152static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id)
1153{
1154 __u8 bank;
1155
1156 /* Save current bank */
1157 bank = inb(iobase+BSR);
1158
1159 /* Select Bank 7 */
1160 switch_bank(iobase, BANK7);
1161
1162 /* IRCFG1: set according to dongle_id */
1163 switch (dongle_id) {
1164 case 0x00: /* same as */
1165 case 0x01: /* Differential serial interface */
1166 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1167 __FUNCTION__, dongle_types[dongle_id]);
1168 break;
1169 case 0x02: /* same as */
1170 case 0x03: /* Reserved */
1171 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1172 __FUNCTION__, dongle_types[dongle_id]);
1173 break;
1174 case 0x04: /* Sharp RY5HD01 */
1175 break;
1176 case 0x05: /* Reserved */
1177 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1178 __FUNCTION__, dongle_types[dongle_id]);
1179 break;
1180 case 0x06: /* Single-ended serial interface */
1181 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1182 __FUNCTION__, dongle_types[dongle_id]);
1183 break;
1184 case 0x07: /* Consumer-IR only */
1185 IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
1186 __FUNCTION__, dongle_types[dongle_id]);
1187 break;
1188 case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
1189 IRDA_DEBUG(0, "%s(), %s\n",
1190 __FUNCTION__, dongle_types[dongle_id]);
1191 outb(0x00, iobase+4);
1192 if (speed > 115200)
1193 outb(0x01, iobase+4);
1194 break;
1195 case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
1196 outb(0x01, iobase+4);
1197
1198 if (speed == 4000000) {
1199 /* There was a cli() there, but we now are already
1200 * under spin_lock_irqsave() - JeanII */
1201 outb(0x81, iobase+4);
1202 outb(0x80, iobase+4);
1203 } else
1204 outb(0x00, iobase+4);
1205 break;
1206 case 0x0A: /* same as */
1207 case 0x0B: /* Reserved */
1208 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1209 __FUNCTION__, dongle_types[dongle_id]);
1210 break;
1211 case 0x0C: /* same as */
1212 case 0x0D: /* HP HSDL-1100/HSDL-2100 */
1213 break;
1214 case 0x0E: /* Supports SIR Mode only */
1215 break;
1216 case 0x0F: /* No dongle connected */
1217 IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
1218 __FUNCTION__, dongle_types[dongle_id]);
1219
1220 switch_bank(iobase, BANK0);
1221 outb(0x62, iobase+MCR);
1222 break;
1223 default:
1224 IRDA_DEBUG(0, "%s(), invalid data_rate\n", __FUNCTION__);
1225 }
1226 /* Restore bank register */
1227 outb(bank, iobase+BSR);
1228}
1229
1230/*
1231 * Function nsc_ircc_change_speed (self, baud)
1232 *
1233 * Change the speed of the device
1234 *
1235 * This function *must* be called with irq off and spin-lock.
1236 */
1237static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 speed)
1238{
1239 struct net_device *dev = self->netdev;
1240 __u8 mcr = MCR_SIR;
1241 int iobase;
1242 __u8 bank;
1243 __u8 ier; /* Interrupt enable register */
1244
1245 IRDA_DEBUG(2, "%s(), speed=%d\n", __FUNCTION__, speed);
1246
1247 IRDA_ASSERT(self != NULL, return 0;);
1248
1249 iobase = self->io.fir_base;
1250
1251 /* Update accounting for new speed */
1252 self->io.speed = speed;
1253
1254 /* Save current bank */
1255 bank = inb(iobase+BSR);
1256
1257 /* Disable interrupts */
1258 switch_bank(iobase, BANK0);
1259 outb(0, iobase+IER);
1260
1261 /* Select Bank 2 */
1262 switch_bank(iobase, BANK2);
1263
1264 outb(0x00, iobase+BGDH);
1265 switch (speed) {
1266 case 9600: outb(0x0c, iobase+BGDL); break;
1267 case 19200: outb(0x06, iobase+BGDL); break;
1268 case 38400: outb(0x03, iobase+BGDL); break;
1269 case 57600: outb(0x02, iobase+BGDL); break;
1270 case 115200: outb(0x01, iobase+BGDL); break;
1271 case 576000:
1272 switch_bank(iobase, BANK5);
1273
1274 /* IRCR2: MDRS is set */
1275 outb(inb(iobase+4) | 0x04, iobase+4);
1276
1277 mcr = MCR_MIR;
1278 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
1279 break;
1280 case 1152000:
1281 mcr = MCR_MIR;
1282 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __FUNCTION__);
1283 break;
1284 case 4000000:
1285 mcr = MCR_FIR;
1286 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __FUNCTION__);
1287 break;
1288 default:
1289 mcr = MCR_FIR;
1290 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n",
1291 __FUNCTION__, speed);
1292 break;
1293 }
1294
1295 /* Set appropriate speed mode */
1296 switch_bank(iobase, BANK0);
1297 outb(mcr | MCR_TX_DFR, iobase+MCR);
1298
1299 /* Give some hits to the transceiver */
1300 nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
1301
1302 /* Set FIFO threshold to TX17, RX16 */
1303 switch_bank(iobase, BANK0);
1304 outb(0x00, iobase+FCR);
1305 outb(FCR_FIFO_EN, iobase+FCR);
1306 outb(FCR_RXTH| /* Set Rx FIFO threshold */
1307 FCR_TXTH| /* Set Tx FIFO threshold */
1308 FCR_TXSR| /* Reset Tx FIFO */
1309 FCR_RXSR| /* Reset Rx FIFO */
1310 FCR_FIFO_EN, /* Enable FIFOs */
1311 iobase+FCR);
1312
1313 /* Set FIFO size to 32 */
1314 switch_bank(iobase, BANK2);
1315 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
1316
1317 /* Enable some interrupts so we can receive frames */
1318 switch_bank(iobase, BANK0);
1319 if (speed > 115200) {
1320 /* Install FIR xmit handler */
1321 dev->hard_start_xmit = nsc_ircc_hard_xmit_fir;
1322 ier = IER_SFIF_IE;
1323 nsc_ircc_dma_receive(self);
1324 } else {
1325 /* Install SIR xmit handler */
1326 dev->hard_start_xmit = nsc_ircc_hard_xmit_sir;
1327 ier = IER_RXHDL_IE;
1328 }
1329 /* Set our current interrupt mask */
1330 outb(ier, iobase+IER);
1331
1332 /* Restore BSR */
1333 outb(bank, iobase+BSR);
1334
1335 /* Make sure interrupt handlers keep the proper interrupt mask */
1336 return(ier);
1337}
1338
1339/*
1340 * Function nsc_ircc_hard_xmit (skb, dev)
1341 *
1342 * Transmit the frame!
1343 *
1344 */
1345static int nsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
1346{
1347 struct nsc_ircc_cb *self;
1348 unsigned long flags;
1349 int iobase;
1350 __s32 speed;
1351 __u8 bank;
1352
1353 self = (struct nsc_ircc_cb *) dev->priv;
1354
1355 IRDA_ASSERT(self != NULL, return 0;);
1356
1357 iobase = self->io.fir_base;
1358
1359 netif_stop_queue(dev);
1360
1361 /* Make sure tests *& speed change are atomic */
1362 spin_lock_irqsave(&self->lock, flags);
1363
1364 /* Check if we need to change the speed */
1365 speed = irda_get_next_speed(skb);
1366 if ((speed != self->io.speed) && (speed != -1)) {
1367 /* Check for empty frame. */
1368 if (!skb->len) {
1369 /* If we just sent a frame, we get called before
1370 * the last bytes get out (because of the SIR FIFO).
1371 * If this is the case, let interrupt handler change
1372 * the speed itself... Jean II */
1373 if (self->io.direction == IO_RECV) {
1374 nsc_ircc_change_speed(self, speed);
1375 /* TODO : For SIR->SIR, the next packet
1376 * may get corrupted - Jean II */
1377 netif_wake_queue(dev);
1378 } else {
1379 self->new_speed = speed;
1380 /* Queue will be restarted after speed change
1381 * to make sure packets gets through the
1382 * proper xmit handler - Jean II */
1383 }
1384 dev->trans_start = jiffies;
1385 spin_unlock_irqrestore(&self->lock, flags);
1386 dev_kfree_skb(skb);
1387 return 0;
1388 } else
1389 self->new_speed = speed;
1390 }
1391
1392 /* Save current bank */
1393 bank = inb(iobase+BSR);
1394
1395 self->tx_buff.data = self->tx_buff.head;
1396
1397 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1398 self->tx_buff.truesize);
1399
1400 self->stats.tx_bytes += self->tx_buff.len;
1401
1402 /* Add interrupt on tx low level (will fire immediately) */
1403 switch_bank(iobase, BANK0);
1404 outb(IER_TXLDL_IE, iobase+IER);
1405
1406 /* Restore bank register */
1407 outb(bank, iobase+BSR);
1408
1409 dev->trans_start = jiffies;
1410 spin_unlock_irqrestore(&self->lock, flags);
1411
1412 dev_kfree_skb(skb);
1413
1414 return 0;
1415}
1416
1417static int nsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1418{
1419 struct nsc_ircc_cb *self;
1420 unsigned long flags;
1421 int iobase;
1422 __s32 speed;
1423 __u8 bank;
1424 int mtt, diff;
1425
1426 self = (struct nsc_ircc_cb *) dev->priv;
1427 iobase = self->io.fir_base;
1428
1429 netif_stop_queue(dev);
1430
1431 /* Make sure tests *& speed change are atomic */
1432 spin_lock_irqsave(&self->lock, flags);
1433
1434 /* Check if we need to change the speed */
1435 speed = irda_get_next_speed(skb);
1436 if ((speed != self->io.speed) && (speed != -1)) {
1437 /* Check for empty frame. */
1438 if (!skb->len) {
1439 /* If we are currently transmitting, defer to
1440 * interrupt handler. - Jean II */
1441 if(self->tx_fifo.len == 0) {
1442 nsc_ircc_change_speed(self, speed);
1443 netif_wake_queue(dev);
1444 } else {
1445 self->new_speed = speed;
1446 /* Keep queue stopped :
1447 * the speed change operation may change the
1448 * xmit handler, and we want to make sure
1449 * the next packet get through the proper
1450 * Tx path, so block the Tx queue until
1451 * the speed change has been done.
1452 * Jean II */
1453 }
1454 dev->trans_start = jiffies;
1455 spin_unlock_irqrestore(&self->lock, flags);
1456 dev_kfree_skb(skb);
1457 return 0;
1458 } else {
1459 /* Change speed after current frame */
1460 self->new_speed = speed;
1461 }
1462 }
1463
1464 /* Save current bank */
1465 bank = inb(iobase+BSR);
1466
1467 /* Register and copy this frame to DMA memory */
1468 self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
1469 self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
1470 self->tx_fifo.tail += skb->len;
1471
1472 self->stats.tx_bytes += skb->len;
1473
d626f62b
ACM		 1474 skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start,
1475 skb->len);
1da177e4
LT		 1476 self->tx_fifo.len++;
1477 self->tx_fifo.free++;
1478
1479 /* Start transmit only if there is currently no transmit going on */
1480 if (self->tx_fifo.len == 1) {
1481 /* Check if we must wait the min turn time or not */
1482 mtt = irda_get_mtt(skb);
1483 if (mtt) {
1484 /* Check how much time we have used already */
1485 do_gettimeofday(&self->now);
1486 diff = self->now.tv_usec - self->stamp.tv_usec;
1487 if (diff < 0)
1488 diff += 1000000;
1489
1490 /* Check if the mtt is larger than the time we have
1491 * already used by all the protocol processing
1492 */
1493 if (mtt > diff) {
1494 mtt -= diff;
1495
1496 /*
1497 * Use timer if delay larger than 125 us, and
1498 * use udelay for smaller values which should
1499 * be acceptable
1500 */
1501 if (mtt > 125) {
1502 /* Adjust for timer resolution */
1503 mtt = mtt / 125;
1504
1505 /* Setup timer */
1506 switch_bank(iobase, BANK4);
1507 outb(mtt & 0xff, iobase+TMRL);
1508 outb((mtt >> 8) & 0x0f, iobase+TMRH);
1509
1510 /* Start timer */
1511 outb(IRCR1_TMR_EN, iobase+IRCR1);
1512 self->io.direction = IO_XMIT;
1513
1514 /* Enable timer interrupt */
1515 switch_bank(iobase, BANK0);
1516 outb(IER_TMR_IE, iobase+IER);
1517
1518 /* Timer will take care of the rest */
1519 goto out;
1520 } else
1521 udelay(mtt);
1522 }
1523 }
1524 /* Enable DMA interrupt */
1525 switch_bank(iobase, BANK0);
1526 outb(IER_DMA_IE, iobase+IER);
1527
1528 /* Transmit frame */
1529 nsc_ircc_dma_xmit(self, iobase);
1530 }
1531 out:
1532 /* Not busy transmitting anymore if window is not full,
1533 * and if we don't need to change speed */
1534 if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0))
1535 netif_wake_queue(self->netdev);
1536
1537 /* Restore bank register */
1538 outb(bank, iobase+BSR);
1539
1540 dev->trans_start = jiffies;
1541 spin_unlock_irqrestore(&self->lock, flags);
1542 dev_kfree_skb(skb);
1543
1544 return 0;
1545}
1546
1547/*
1548 * Function nsc_ircc_dma_xmit (self, iobase)
1549 *
1550 * Transmit data using DMA
1551 *
1552 */
1553static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase)
1554{
1555 int bsr;
1556
1557 /* Save current bank */
1558 bsr = inb(iobase+BSR);
1559
1560 /* Disable DMA */
1561 switch_bank(iobase, BANK0);
1562 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1563
1564 self->io.direction = IO_XMIT;
1565
1566 /* Choose transmit DMA channel */
1567 switch_bank(iobase, BANK2);
1568 outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1569
1570 irda_setup_dma(self->io.dma,
1571 ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
1572 self->tx_buff.head) + self->tx_buff_dma,
1573 self->tx_fifo.queue[self->tx_fifo.ptr].len,
1574 DMA_TX_MODE);
1575
1576 /* Enable DMA and SIR interaction pulse */
1577 switch_bank(iobase, BANK0);
1578 outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR);
1579
1580 /* Restore bank register */
1581 outb(bsr, iobase+BSR);
1582}
1583
1584/*
1585 * Function nsc_ircc_pio_xmit (self, iobase)
1586 *
1587 * Transmit data using PIO. Returns the number of bytes that actually
1588 * got transferred
1589 *
1590 */
1591static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
1592{
1593 int actual = 0;
1594 __u8 bank;
1595
1596 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
1597
1598 /* Save current bank */
1599 bank = inb(iobase+BSR);
1600
1601 switch_bank(iobase, BANK0);
1602 if (!(inb_p(iobase+LSR) & LSR_TXEMP)) {
1603 IRDA_DEBUG(4, "%s(), warning, FIFO not empty yet!\n",
1604 __FUNCTION__);
1605
1606 /* FIFO may still be filled to the Tx interrupt threshold */
1607 fifo_size -= 17;
1608 }
1609
1610 /* Fill FIFO with current frame */
1611 while ((fifo_size-- > 0) && (actual < len)) {
1612 /* Transmit next byte */
1613 outb(buf[actual++], iobase+TXD);
1614 }
1615
1616 IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
1617 __FUNCTION__, fifo_size, actual, len);
1618
1619 /* Restore bank */
1620 outb(bank, iobase+BSR);
1621
1622 return actual;
1623}
1624
1625/*
1626 * Function nsc_ircc_dma_xmit_complete (self)
1627 *
1628 * The transfer of a frame in finished. This function will only be called
1629 * by the interrupt handler
1630 *
1631 */
1632static int nsc_ircc_dma_xmit_complete(struct nsc_ircc_cb *self)
1633{
1634 int iobase;
1635 __u8 bank;
1636 int ret = TRUE;
1637
1638 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
1639
1640 iobase = self->io.fir_base;
1641
1642 /* Save current bank */
1643 bank = inb(iobase+BSR);
1644
1645 /* Disable DMA */
1646 switch_bank(iobase, BANK0);
1647 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1648
1649 /* Check for underrrun! */
1650 if (inb(iobase+ASCR) & ASCR_TXUR) {
1651 self->stats.tx_errors++;
1652 self->stats.tx_fifo_errors++;
1653
1654 /* Clear bit, by writing 1 into it */
1655 outb(ASCR_TXUR, iobase+ASCR);
1656 } else {
1657 self->stats.tx_packets++;
1658 }
1659
1660 /* Finished with this frame, so prepare for next */
1661 self->tx_fifo.ptr++;
1662 self->tx_fifo.len--;
1663
1664 /* Any frames to be sent back-to-back? */
1665 if (self->tx_fifo.len) {
1666 nsc_ircc_dma_xmit(self, iobase);
1667
1668 /* Not finished yet! */
1669 ret = FALSE;
1670 } else {
1671 /* Reset Tx FIFO info */
1672 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1673 self->tx_fifo.tail = self->tx_buff.head;
1674 }
1675
1676 /* Make sure we have room for more frames and
1677 * that we don't need to change speed */
1678 if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) {
1679 /* Not busy transmitting anymore */
1680 /* Tell the network layer, that we can accept more frames */
1681 netif_wake_queue(self->netdev);
1682 }
1683
1684 /* Restore bank */
1685 outb(bank, iobase+BSR);
1686
1687 return ret;
1688}
1689
1690/*
1691 * Function nsc_ircc_dma_receive (self)
1692 *
1693 * Get ready for receiving a frame. The device will initiate a DMA
1694 * if it starts to receive a frame.
1695 *
1696 */
1697static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self)
1698{
1699 int iobase;
1700 __u8 bsr;
1701
1702 iobase = self->io.fir_base;
1703
1704 /* Reset Tx FIFO info */
1705 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1706 self->tx_fifo.tail = self->tx_buff.head;
1707
1708 /* Save current bank */
1709 bsr = inb(iobase+BSR);
1710
1711 /* Disable DMA */
1712 switch_bank(iobase, BANK0);
1713 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1714
1715 /* Choose DMA Rx, DMA Fairness, and Advanced mode */
1716 switch_bank(iobase, BANK2);
1717 outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1718
1719 self->io.direction = IO_RECV;
1720 self->rx_buff.data = self->rx_buff.head;
1721
1722 /* Reset Rx FIFO. This will also flush the ST_FIFO */
1723 switch_bank(iobase, BANK0);
1724 outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
1725
1726 self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1727 self->st_fifo.tail = self->st_fifo.head = 0;
1728
1729 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1730 DMA_RX_MODE);
1731
1732 /* Enable DMA */
1733 switch_bank(iobase, BANK0);
1734 outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR);
1735
1736 /* Restore bank register */
1737 outb(bsr, iobase+BSR);
1738
1739 return 0;
1740}
1741
1742/*
1743 * Function nsc_ircc_dma_receive_complete (self)
1744 *
1745 * Finished with receiving frames
1746 *
1747 *
1748 */
1749static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase)
1750{
1751 struct st_fifo *st_fifo;
1752 struct sk_buff *skb;
1753 __u8 status;
1754 __u8 bank;
1755 int len;
1756
1757 st_fifo = &self->st_fifo;
1758
1759 /* Save current bank */
1760 bank = inb(iobase+BSR);
1761
1762 /* Read all entries in status FIFO */
1763 switch_bank(iobase, BANK5);
1764 while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) {
1765 /* We must empty the status FIFO no matter what */
1766 len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8);
1767
1768 if (st_fifo->tail >= MAX_RX_WINDOW) {
1769 IRDA_DEBUG(0, "%s(), window is full!\n", __FUNCTION__);
1770 continue;
1771 }
1772
1773 st_fifo->entries[st_fifo->tail].status = status;
1774 st_fifo->entries[st_fifo->tail].len = len;
1775 st_fifo->pending_bytes += len;
1776 st_fifo->tail++;
1777 st_fifo->len++;
1778 }
1779 /* Try to process all entries in status FIFO */
1780 while (st_fifo->len > 0) {
1781 /* Get first entry */
1782 status = st_fifo->entries[st_fifo->head].status;
1783 len = st_fifo->entries[st_fifo->head].len;
1784 st_fifo->pending_bytes -= len;
1785 st_fifo->head++;
1786 st_fifo->len--;
1787
1788 /* Check for errors */
1789 if (status & FRM_ST_ERR_MSK) {
1790 if (status & FRM_ST_LOST_FR) {
1791 /* Add number of lost frames to stats */
1792 self->stats.rx_errors += len;
1793 } else {
1794 /* Skip frame */
1795 self->stats.rx_errors++;
1796
1797 self->rx_buff.data += len;
1798
1799 if (status & FRM_ST_MAX_LEN)
1800 self->stats.rx_length_errors++;
1801
1802 if (status & FRM_ST_PHY_ERR)
1803 self->stats.rx_frame_errors++;
1804
1805 if (status & FRM_ST_BAD_CRC)
1806 self->stats.rx_crc_errors++;
1807 }
1808 /* The errors below can be reported in both cases */
1809 if (status & FRM_ST_OVR1)
1810 self->stats.rx_fifo_errors++;
1811
1812 if (status & FRM_ST_OVR2)
1813 self->stats.rx_fifo_errors++;
1814 } else {
1815 /*
1816 * First we must make sure that the frame we
1817 * want to deliver is all in main memory. If we
1818 * cannot tell, then we check if the Rx FIFO is
1819 * empty. If not then we will have to take a nap
1820 * and try again later.
1821 */
1822 if (st_fifo->pending_bytes < self->io.fifo_size) {
1823 switch_bank(iobase, BANK0);
1824 if (inb(iobase+LSR) & LSR_RXDA) {
1825 /* Put this entry back in fifo */
1826 st_fifo->head--;
1827 st_fifo->len++;
1828 st_fifo->pending_bytes += len;
1829 st_fifo->entries[st_fifo->head].status = status;
1830 st_fifo->entries[st_fifo->head].len = len;
1831 /*
1832 * DMA not finished yet, so try again
1833 * later, set timer value, resolution
1834 * 125 us
1835 */
1836 switch_bank(iobase, BANK4);
1837 outb(0x02, iobase+TMRL); /* x 125 us */
1838 outb(0x00, iobase+TMRH);
1839
1840 /* Start timer */
1841 outb(IRCR1_TMR_EN, iobase+IRCR1);
1842
1843 /* Restore bank register */
1844 outb(bank, iobase+BSR);
1845
1846 return FALSE; /* I'll be back! */
1847 }
1848 }
1849
1850 /*
1851 * Remember the time we received this frame, so we can
1852 * reduce the min turn time a bit since we will know
1853 * how much time we have used for protocol processing
1854 */
1855 do_gettimeofday(&self->stamp);
1856
1857 skb = dev_alloc_skb(len+1);
1858 if (skb == NULL) {
1859 IRDA_WARNING("%s(), memory squeeze, "
1860 "dropping frame.\n",
1861 __FUNCTION__);
1862 self->stats.rx_dropped++;
1863
1864 /* Restore bank register */
1865 outb(bank, iobase+BSR);
1866
1867 return FALSE;
1868 }
1869
1870 /* Make sure IP header gets aligned */
1871 skb_reserve(skb, 1);
1872
1873 /* Copy frame without CRC */
1874 if (self->io.speed < 4000000) {
1875 skb_put(skb, len-2);
27d7ff46
ACM		 1876 skb_copy_to_linear_data(skb,
1877 self->rx_buff.data,
1878 len - 2);
1da177e4
LT		 1879 } else {
1880 skb_put(skb, len-4);
27d7ff46
ACM		 1881 skb_copy_to_linear_data(skb,
1882 self->rx_buff.data,
1883 len - 4);
1da177e4
LT		 1884 }
1885
1886 /* Move to next frame */
1887 self->rx_buff.data += len;
1888 self->stats.rx_bytes += len;
1889 self->stats.rx_packets++;
1890
1891 skb->dev = self->netdev;
459a98ed 1892 skb_reset_mac_header(skb);
1da177e4
LT		 1893 skb->protocol = htons(ETH_P_IRDA);
1894 netif_rx(skb);
1895 self->netdev->last_rx = jiffies;
1896 }
1897 }
1898 /* Restore bank register */
1899 outb(bank, iobase+BSR);
1900
1901 return TRUE;
1902}
1903
1904/*
1905 * Function nsc_ircc_pio_receive (self)
1906 *
1907 * Receive all data in receiver FIFO
1908 *
1909 */
1910static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self)
1911{
1912 __u8 byte;
1913 int iobase;
1914
1915 iobase = self->io.fir_base;
1916
1917 /* Receive all characters in Rx FIFO */
1918 do {
1919 byte = inb(iobase+RXD);
1920 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1921 byte);
1922 } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */
1923}
1924
1925/*
1926 * Function nsc_ircc_sir_interrupt (self, eir)
1927 *
1928 * Handle SIR interrupt
1929 *
1930 */
1931static void nsc_ircc_sir_interrupt(struct nsc_ircc_cb *self, int eir)
1932{
1933 int actual;
1934
1935 /* Check if transmit FIFO is low on data */
1936 if (eir & EIR_TXLDL_EV) {
1937 /* Write data left in transmit buffer */
1938 actual = nsc_ircc_pio_write(self->io.fir_base,
1939 self->tx_buff.data,
1940 self->tx_buff.len,
1941 self->io.fifo_size);
1942 self->tx_buff.data += actual;
1943 self->tx_buff.len -= actual;
1944
1945 self->io.direction = IO_XMIT;
1946
1947 /* Check if finished */
1948 if (self->tx_buff.len > 0)
1949 self->ier = IER_TXLDL_IE;
1950 else {
1951
1952 self->stats.tx_packets++;
1953 netif_wake_queue(self->netdev);
1954 self->ier = IER_TXEMP_IE;
1955 }
1956
1957 }
1958 /* Check if transmission has completed */
1959 if (eir & EIR_TXEMP_EV) {
1960 /* Turn around and get ready to receive some data */
1961 self->io.direction = IO_RECV;
1962 self->ier = IER_RXHDL_IE;
1963 /* Check if we need to change the speed?
1964 * Need to be after self->io.direction to avoid race with
1965 * nsc_ircc_hard_xmit_sir() - Jean II */
1966 if (self->new_speed) {
1967 IRDA_DEBUG(2, "%s(), Changing speed!\n", __FUNCTION__);
1968 self->ier = nsc_ircc_change_speed(self,
1969 self->new_speed);
1970 self->new_speed = 0;
1971 netif_wake_queue(self->netdev);
1972
1973 /* Check if we are going to FIR */
1974 if (self->io.speed > 115200) {
1975 /* No need to do anymore SIR stuff */
1976 return;
1977 }
1978 }
1979 }
1980
1981 /* Rx FIFO threshold or timeout */
1982 if (eir & EIR_RXHDL_EV) {
1983 nsc_ircc_pio_receive(self);
1984
1985 /* Keep receiving */
1986 self->ier = IER_RXHDL_IE;
1987 }
1988}
1989
1990/*
1991 * Function nsc_ircc_fir_interrupt (self, eir)
1992 *
1993 * Handle MIR/FIR interrupt
1994 *
1995 */
1996static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase,
1997 int eir)
1998{
1999 __u8 bank;
2000
2001 bank = inb(iobase+BSR);
2002
2003 /* Status FIFO event*/
2004 if (eir & EIR_SFIF_EV) {
2005 /* Check if DMA has finished */
2006 if (nsc_ircc_dma_receive_complete(self, iobase)) {
2007 /* Wait for next status FIFO interrupt */
2008 self->ier = IER_SFIF_IE;
2009 } else {
2010 self->ier = IER_SFIF_IE | IER_TMR_IE;
2011 }
2012 } else if (eir & EIR_TMR_EV) { /* Timer finished */
2013 /* Disable timer */
2014 switch_bank(iobase, BANK4);
2015 outb(0, iobase+IRCR1);
2016
2017 /* Clear timer event */
2018 switch_bank(iobase, BANK0);
2019 outb(ASCR_CTE, iobase+ASCR);
2020
2021 /* Check if this is a Tx timer interrupt */
2022 if (self->io.direction == IO_XMIT) {
2023 nsc_ircc_dma_xmit(self, iobase);
2024
2025 /* Interrupt on DMA */
2026 self->ier = IER_DMA_IE;
2027 } else {
2028 /* Check (again) if DMA has finished */
2029 if (nsc_ircc_dma_receive_complete(self, iobase)) {
2030 self->ier = IER_SFIF_IE;
2031 } else {
2032 self->ier = IER_SFIF_IE | IER_TMR_IE;
2033 }
2034 }
2035 } else if (eir & EIR_DMA_EV) {
2036 /* Finished with all transmissions? */
2037 if (nsc_ircc_dma_xmit_complete(self)) {
2038 if(self->new_speed != 0) {
2039 /* As we stop the Tx queue, the speed change
2040 * need to be done when the Tx fifo is
2041 * empty. Ask for a Tx done interrupt */
2042 self->ier = IER_TXEMP_IE;
2043 } else {
2044 /* Check if there are more frames to be
2045 * transmitted */
2046 if (irda_device_txqueue_empty(self->netdev)) {
2047 /* Prepare for receive */
2048 nsc_ircc_dma_receive(self);
2049 self->ier = IER_SFIF_IE;
2050 } else
2051 IRDA_WARNING("%s(), potential "
2052 "Tx queue lockup !\n",
2053 __FUNCTION__);
2054 }
2055 } else {
2056 /* Not finished yet, so interrupt on DMA again */
2057 self->ier = IER_DMA_IE;
2058 }
2059 } else if (eir & EIR_TXEMP_EV) {
2060 /* The Tx FIFO has totally drained out, so now we can change
2061 * the speed... - Jean II */
2062 self->ier = nsc_ircc_change_speed(self, self->new_speed);
2063 self->new_speed = 0;
2064 netif_wake_queue(self->netdev);
2065 /* Note : nsc_ircc_change_speed() restarted Rx fifo */
2066 }
2067
2068 outb(bank, iobase+BSR);
2069}
2070
2071/*
2072 * Function nsc_ircc_interrupt (irq, dev_id, regs)
2073 *
2074 * An interrupt from the chip has arrived. Time to do some work
2075 *
2076 */
7d12e780 2077static irqreturn_t nsc_ircc_interrupt(int irq, void *dev_id)
1da177e4 2078{
c31f28e7 2079 struct net_device *dev = dev_id;
1da177e4
LT		 2080 struct nsc_ircc_cb *self;
2081 __u8 bsr, eir;
2082 int iobase;
2083
c31f28e7 2084 self = dev->priv;
1da177e4
LT		 2085
2086 spin_lock(&self->lock);
2087
2088 iobase = self->io.fir_base;
2089
2090 bsr = inb(iobase+BSR); /* Save current bank */
2091
2092 switch_bank(iobase, BANK0);
2093 self->ier = inb(iobase+IER);
2094 eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */
2095
2096 outb(0, iobase+IER); /* Disable interrupts */
2097
2098 if (eir) {
2099 /* Dispatch interrupt handler for the current speed */
2100 if (self->io.speed > 115200)
2101 nsc_ircc_fir_interrupt(self, iobase, eir);
2102 else
2103 nsc_ircc_sir_interrupt(self, eir);
2104 }
2105
2106 outb(self->ier, iobase+IER); /* Restore interrupts */
2107 outb(bsr, iobase+BSR); /* Restore bank register */
2108
2109 spin_unlock(&self->lock);
2110 return IRQ_RETVAL(eir);
2111}
2112
2113/*
2114 * Function nsc_ircc_is_receiving (self)
2115 *
2116 * Return TRUE is we are currently receiving a frame
2117 *
2118 */
2119static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self)
2120{
2121 unsigned long flags;
2122 int status = FALSE;
2123 int iobase;
2124 __u8 bank;
2125
2126 IRDA_ASSERT(self != NULL, return FALSE;);
2127
2128 spin_lock_irqsave(&self->lock, flags);
2129
2130 if (self->io.speed > 115200) {
2131 iobase = self->io.fir_base;
2132
2133 /* Check if rx FIFO is not empty */
2134 bank = inb(iobase+BSR);
2135 switch_bank(iobase, BANK2);
2136 if ((inb(iobase+RXFLV) & 0x3f) != 0) {
2137 /* We are receiving something */
2138 status = TRUE;
2139 }
2140 outb(bank, iobase+BSR);
2141 } else
2142 status = (self->rx_buff.state != OUTSIDE_FRAME);
2143
2144 spin_unlock_irqrestore(&self->lock, flags);
2145
2146 return status;
2147}
2148
2149/*
2150 * Function nsc_ircc_net_open (dev)
2151 *
2152 * Start the device
2153 *
2154 */
2155static int nsc_ircc_net_open(struct net_device *dev)
2156{
2157 struct nsc_ircc_cb *self;
2158 int iobase;
2159 char hwname[32];
2160 __u8 bank;
2161
2162 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
2163
2164 IRDA_ASSERT(dev != NULL, return -1;);
2165 self = (struct nsc_ircc_cb *) dev->priv;
2166
2167 IRDA_ASSERT(self != NULL, return 0;);
2168
2169 iobase = self->io.fir_base;
2170
2171 if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, dev->name, dev)) {
2172 IRDA_WARNING("%s, unable to allocate irq=%d\n",
2173 driver_name, self->io.irq);
2174 return -EAGAIN;
2175 }
2176 /*
2177 * Always allocate the DMA channel after the IRQ, and clean up on
2178 * failure.
2179 */
2180 if (request_dma(self->io.dma, dev->name)) {
2181 IRDA_WARNING("%s, unable to allocate dma=%d\n",
2182 driver_name, self->io.dma);
2183 free_irq(self->io.irq, dev);
2184 return -EAGAIN;
2185 }
2186
2187 /* Save current bank */
2188 bank = inb(iobase+BSR);
2189
2190 /* turn on interrupts */
2191 switch_bank(iobase, BANK0);
2192 outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER);
2193
2194 /* Restore bank register */
2195 outb(bank, iobase+BSR);
2196
2197 /* Ready to play! */
2198 netif_start_queue(dev);
2199
2200 /* Give self a hardware name */
2201 sprintf(hwname, "NSC-FIR @ 0x%03x", self->io.fir_base);
2202
2203 /*
2204 * Open new IrLAP layer instance, now that everything should be
2205 * initialized properly
2206 */
2207 self->irlap = irlap_open(dev, &self->qos, hwname);
2208
2209 return 0;
2210}
2211
2212/*
2213 * Function nsc_ircc_net_close (dev)
2214 *
2215 * Stop the device
2216 *
2217 */
2218static int nsc_ircc_net_close(struct net_device *dev)
2219{
2220 struct nsc_ircc_cb *self;
2221 int iobase;
2222 __u8 bank;
2223
2224 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
2225
2226 IRDA_ASSERT(dev != NULL, return -1;);
2227
2228 self = (struct nsc_ircc_cb *) dev->priv;
2229 IRDA_ASSERT(self != NULL, return 0;);
2230
2231 /* Stop device */
2232 netif_stop_queue(dev);
2233
2234 /* Stop and remove instance of IrLAP */
2235 if (self->irlap)
2236 irlap_close(self->irlap);
2237 self->irlap = NULL;
2238
2239 iobase = self->io.fir_base;
2240
2241 disable_dma(self->io.dma);
2242
2243 /* Save current bank */
2244 bank = inb(iobase+BSR);
2245
2246 /* Disable interrupts */
2247 switch_bank(iobase, BANK0);
2248 outb(0, iobase+IER);
2249
2250 free_irq(self->io.irq, dev);
2251 free_dma(self->io.dma);
2252
2253 /* Restore bank register */
2254 outb(bank, iobase+BSR);
2255
2256 return 0;
2257}
2258
2259/*
2260 * Function nsc_ircc_net_ioctl (dev, rq, cmd)
2261 *
2262 * Process IOCTL commands for this device
2263 *
2264 */
2265static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2266{
2267 struct if_irda_req *irq = (struct if_irda_req *) rq;
2268 struct nsc_ircc_cb *self;
2269 unsigned long flags;
2270 int ret = 0;
2271
2272 IRDA_ASSERT(dev != NULL, return -1;);
2273
2274 self = dev->priv;
2275
2276 IRDA_ASSERT(self != NULL, return -1;);
2277
2278 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
2279
2280 switch (cmd) {
2281 case SIOCSBANDWIDTH: /* Set bandwidth */
2282 if (!capable(CAP_NET_ADMIN)) {
2283 ret = -EPERM;
2284 break;
2285 }
2286 spin_lock_irqsave(&self->lock, flags);
2287 nsc_ircc_change_speed(self, irq->ifr_baudrate);
2288 spin_unlock_irqrestore(&self->lock, flags);
2289 break;
2290 case SIOCSMEDIABUSY: /* Set media busy */
2291 if (!capable(CAP_NET_ADMIN)) {
2292 ret = -EPERM;
2293 break;
2294 }
2295 irda_device_set_media_busy(self->netdev, TRUE);
2296 break;
2297 case SIOCGRECEIVING: /* Check if we are receiving right now */
2298 /* This is already protected */
2299 irq->ifr_receiving = nsc_ircc_is_receiving(self);
2300 break;
2301 default:
2302 ret = -EOPNOTSUPP;
2303 }
2304 return ret;
2305}
2306
2307static struct net_device_stats *nsc_ircc_net_get_stats(struct net_device *dev)
2308{
2309 struct nsc_ircc_cb *self = (struct nsc_ircc_cb *) dev->priv;
2310
2311 return &self->stats;
2312}
2313
3b99b93b 2314static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 2315{
3b99b93b
DT		 2316 struct nsc_ircc_cb *self = platform_get_drvdata(dev);
2317 int bank;
2318 unsigned long flags;
2319 int iobase = self->io.fir_base;
1da177e4
LT		 2320
2321 if (self->io.suspended)
3b99b93b 2322 return 0;
1da177e4 2323
3b99b93b 2324 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1da177e4 2325
3b99b93b
DT		 2326 rtnl_lock();
2327 if (netif_running(self->netdev)) {
2328 netif_device_detach(self->netdev);
2329 spin_lock_irqsave(&self->lock, flags);
2330 /* Save current bank */
2331 bank = inb(iobase+BSR);
2332
2333 /* Disable interrupts */
2334 switch_bank(iobase, BANK0);
2335 outb(0, iobase+IER);
2336
2337 /* Restore bank register */
2338 outb(bank, iobase+BSR);
2339
2340 spin_unlock_irqrestore(&self->lock, flags);
2341 free_irq(self->io.irq, self->netdev);
2342 disable_dma(self->io.dma);
2343 }
1da177e4 2344 self->io.suspended = 1;
3b99b93b
DT		 2345 rtnl_unlock();
2346
2347 return 0;
1da177e4
LT		 2348}
2349
3b99b93b 2350static int nsc_ircc_resume(struct platform_device *dev)
1da177e4 2351{
3b99b93b
DT		 2352 struct nsc_ircc_cb *self = platform_get_drvdata(dev);
2353 unsigned long flags;
2354
1da177e4 2355 if (!self->io.suspended)
3b99b93b 2356 return 0;
1da177e4 2357
3b99b93b
DT		 2358 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
2359
2360 rtnl_lock();
1da177e4 2361 nsc_ircc_setup(&self->io);
3b99b93b 2362 nsc_ircc_init_dongle_interface(self->io.fir_base, self->io.dongle_id);
1da177e4 2363
3b99b93b
DT		 2364 if (netif_running(self->netdev)) {
2365 if (request_irq(self->io.irq, nsc_ircc_interrupt, 0,
2366 self->netdev->name, self->netdev)) {
2367 IRDA_WARNING("%s, unable to allocate irq=%d\n",
2368 driver_name, self->io.irq);
2369
2370 /*
2371 * Don't fail resume process, just kill this
2372 * network interface
2373 */
2374 unregister_netdevice(self->netdev);
2375 } else {
2376 spin_lock_irqsave(&self->lock, flags);
2377 nsc_ircc_change_speed(self, self->io.speed);
2378 spin_unlock_irqrestore(&self->lock, flags);
2379 netif_device_attach(self->netdev);
2380 }
2381
2382 } else {
2383 spin_lock_irqsave(&self->lock, flags);
2384 nsc_ircc_change_speed(self, 9600);
2385 spin_unlock_irqrestore(&self->lock, flags);
2386 }
1da177e4 2387 self->io.suspended = 0;
3b99b93b 2388 rtnl_unlock();
1da177e4 2389
3b99b93b 2390 return 0;
1da177e4
LT		 2391}
2392
2393MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
2394MODULE_DESCRIPTION("NSC IrDA Device Driver");
2395MODULE_LICENSE("GPL");
2396
2397
2398module_param(qos_mtt_bits, int, 0);
2399MODULE_PARM_DESC(qos_mtt_bits, "Minimum Turn Time");
2400module_param_array(io, int, NULL, 0);
2401MODULE_PARM_DESC(io, "Base I/O addresses");
2402module_param_array(irq, int, NULL, 0);
2403MODULE_PARM_DESC(irq, "IRQ lines");
2404module_param_array(dma, int, NULL, 0);
2405MODULE_PARM_DESC(dma, "DMA channels");
2406module_param(dongle_id, int, 0);
2407MODULE_PARM_DESC(dongle_id, "Type-id of used dongle");
2408
2409module_init(nsc_ircc_init);
2410module_exit(nsc_ircc_cleanup);
2411
Linux kernel - Deliverables
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