Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /********************************************************************* |
1da177e4 LT |
2 | * |
3 | * Description: Driver for the SMC Infrared Communications Controller | |
4 | * Status: Experimental. | |
5 | * Author: Daniele Peri (peri@csai.unipa.it) | |
527b6af4 DT |
6 | * Created at: |
7 | * Modified at: | |
8 | * Modified by: | |
9 | * | |
1da177e4 LT |
10 | * Copyright (c) 2002 Daniele Peri |
11 | * All Rights Reserved. | |
12 | * Copyright (c) 2002 Jean Tourrilhes | |
c1e14a6e | 13 | * Copyright (c) 2006 Linus Walleij |
1da177e4 LT |
14 | * |
15 | * | |
16 | * Based on smc-ircc.c: | |
17 | * | |
18 | * Copyright (c) 2001 Stefani Seibold | |
19 | * Copyright (c) 1999-2001 Dag Brattli | |
527b6af4 | 20 | * Copyright (c) 1998-1999 Thomas Davis, |
1da177e4 LT |
21 | * |
22 | * and irport.c: | |
23 | * | |
24 | * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved. | |
25 | * | |
527b6af4 DT |
26 | * |
27 | * This program is free software; you can redistribute it and/or | |
28 | * modify it under the terms of the GNU General Public License as | |
29 | * published by the Free Software Foundation; either version 2 of | |
1da177e4 | 30 | * the License, or (at your option) any later version. |
527b6af4 | 31 | * |
1da177e4 LT |
32 | * This program is distributed in the hope that it will be useful, |
33 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
34 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
35 | * GNU General Public License for more details. | |
527b6af4 DT |
36 | * |
37 | * You should have received a copy of the GNU General Public License | |
38 | * along with this program; if not, write to the Free Software | |
39 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
1da177e4 LT |
40 | * MA 02111-1307 USA |
41 | * | |
42 | ********************************************************************/ | |
43 | ||
44 | #include <linux/module.h> | |
45 | #include <linux/kernel.h> | |
46 | #include <linux/types.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/netdevice.h> | |
49 | #include <linux/ioport.h> | |
50 | #include <linux/delay.h> | |
51 | #include <linux/slab.h> | |
52 | #include <linux/init.h> | |
53 | #include <linux/rtnetlink.h> | |
54 | #include <linux/serial_reg.h> | |
55 | #include <linux/dma-mapping.h> | |
d94c77b9 | 56 | #include <linux/pnp.h> |
d052d1be | 57 | #include <linux/platform_device.h> |
1da177e4 LT |
58 | |
59 | #include <asm/io.h> | |
60 | #include <asm/dma.h> | |
61 | #include <asm/byteorder.h> | |
62 | ||
63 | #include <linux/spinlock.h> | |
64 | #include <linux/pm.h> | |
c1e14a6e LW |
65 | #ifdef CONFIG_PCI |
66 | #include <linux/pci.h> | |
67 | #endif | |
1da177e4 LT |
68 | |
69 | #include <net/irda/wrapper.h> | |
70 | #include <net/irda/irda.h> | |
71 | #include <net/irda/irda_device.h> | |
72 | ||
73 | #include "smsc-ircc2.h" | |
74 | #include "smsc-sio.h" | |
75 | ||
98b77773 DT |
76 | |
77 | MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); | |
78 | MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); | |
79 | MODULE_LICENSE("GPL"); | |
80 | ||
cbcdd772 | 81 | static int smsc_nopnp = 1; |
d0d4f69b | 82 | module_param_named(nopnp, smsc_nopnp, bool, 0); |
32db9276 | 83 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true"); |
d0d4f69b | 84 | |
916f11c7 BH |
85 | #define DMA_INVAL 255 |
86 | static int ircc_dma = DMA_INVAL; | |
98b77773 DT |
87 | module_param(ircc_dma, int, 0); |
88 | MODULE_PARM_DESC(ircc_dma, "DMA channel"); | |
89 | ||
916f11c7 BH |
90 | #define IRQ_INVAL 255 |
91 | static int ircc_irq = IRQ_INVAL; | |
98b77773 DT |
92 | module_param(ircc_irq, int, 0); |
93 | MODULE_PARM_DESC(ircc_irq, "IRQ line"); | |
94 | ||
95 | static int ircc_fir; | |
96 | module_param(ircc_fir, int, 0); | |
97 | MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); | |
98 | ||
99 | static int ircc_sir; | |
100 | module_param(ircc_sir, int, 0); | |
101 | MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); | |
102 | ||
103 | static int ircc_cfg; | |
104 | module_param(ircc_cfg, int, 0); | |
105 | MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); | |
106 | ||
107 | static int ircc_transceiver; | |
108 | module_param(ircc_transceiver, int, 0); | |
109 | MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); | |
110 | ||
1da177e4 LT |
111 | /* Types */ |
112 | ||
c1e14a6e LW |
113 | #ifdef CONFIG_PCI |
114 | struct smsc_ircc_subsystem_configuration { | |
115 | unsigned short vendor; /* PCI vendor ID */ | |
116 | unsigned short device; /* PCI vendor ID */ | |
117 | unsigned short subvendor; /* PCI subsystem vendor ID */ | |
118 | unsigned short subdevice; /* PCI sybsystem device ID */ | |
119 | unsigned short sir_io; /* I/O port for SIR */ | |
120 | unsigned short fir_io; /* I/O port for FIR */ | |
121 | unsigned char fir_irq; /* FIR IRQ */ | |
122 | unsigned char fir_dma; /* FIR DMA */ | |
123 | unsigned short cfg_base; /* I/O port for chip configuration */ | |
124 | int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */ | |
125 | const char *name; /* name shown as info */ | |
126 | }; | |
127 | #endif | |
128 | ||
1da177e4 LT |
129 | struct smsc_transceiver { |
130 | char *name; | |
527b6af4 | 131 | void (*set_for_speed)(int fir_base, u32 speed); |
1da177e4 LT |
132 | int (*probe)(int fir_base); |
133 | }; | |
1da177e4 LT |
134 | |
135 | struct smsc_chip { | |
136 | char *name; | |
137 | #if 0 | |
138 | u8 type; | |
139 | #endif | |
140 | u16 flags; | |
141 | u8 devid; | |
142 | u8 rev; | |
143 | }; | |
1da177e4 LT |
144 | |
145 | struct smsc_chip_address { | |
146 | unsigned int cfg_base; | |
147 | unsigned int type; | |
148 | }; | |
1da177e4 LT |
149 | |
150 | /* Private data for each instance */ | |
151 | struct smsc_ircc_cb { | |
152 | struct net_device *netdev; /* Yes! we are some kind of netdevice */ | |
1da177e4 | 153 | struct irlap_cb *irlap; /* The link layer we are binded to */ |
527b6af4 | 154 | |
1da177e4 LT |
155 | chipio_t io; /* IrDA controller information */ |
156 | iobuff_t tx_buff; /* Transmit buffer */ | |
157 | iobuff_t rx_buff; /* Receive buffer */ | |
158 | dma_addr_t tx_buff_dma; | |
159 | dma_addr_t rx_buff_dma; | |
160 | ||
161 | struct qos_info qos; /* QoS capabilities for this device */ | |
162 | ||
163 | spinlock_t lock; /* For serializing operations */ | |
527b6af4 | 164 | |
1da177e4 LT |
165 | __u32 new_speed; |
166 | __u32 flags; /* Interface flags */ | |
167 | ||
168 | int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ | |
169 | int tx_len; /* Number of frames in tx_buff */ | |
170 | ||
171 | int transceiver; | |
6bb3b2cd | 172 | struct platform_device *pldev; |
1da177e4 LT |
173 | }; |
174 | ||
175 | /* Constants */ | |
176 | ||
6bb3b2cd DT |
177 | #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2" |
178 | ||
1da177e4 LT |
179 | #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 |
180 | #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 | |
98b77773 | 181 | #define SMSC_IRCC2_C_NET_TIMEOUT 0 |
1da177e4 LT |
182 | #define SMSC_IRCC2_C_SIR_STOP 0 |
183 | ||
6bb3b2cd DT |
184 | static const char *driver_name = SMSC_IRCC2_DRIVER_NAME; |
185 | ||
1da177e4 LT |
186 | /* Prototypes */ |
187 | ||
188 | static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq); | |
189 | static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base); | |
190 | static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq); | |
191 | static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self); | |
192 | static void smsc_ircc_init_chip(struct smsc_ircc_cb *self); | |
193 | static int __exit smsc_ircc_close(struct smsc_ircc_cb *self); | |
80a90589 DT |
194 | static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self); |
195 | static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self); | |
1da177e4 LT |
196 | static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self); |
197 | static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev); | |
198 | static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev); | |
80a90589 DT |
199 | static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs); |
200 | static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self); | |
0fa2f491 DT |
201 | static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed); |
202 | static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed); | |
7d12e780 | 203 | static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id); |
1da177e4 LT |
204 | static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev); |
205 | static void smsc_ircc_sir_start(struct smsc_ircc_cb *self); | |
206 | #if SMSC_IRCC2_C_SIR_STOP | |
207 | static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self); | |
208 | #endif | |
209 | static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self); | |
210 | static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len); | |
211 | static int smsc_ircc_net_open(struct net_device *dev); | |
212 | static int smsc_ircc_net_close(struct net_device *dev); | |
213 | static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
214 | #if SMSC_IRCC2_C_NET_TIMEOUT | |
215 | static void smsc_ircc_timeout(struct net_device *dev); | |
216 | #endif | |
1da177e4 LT |
217 | static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self); |
218 | static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self); | |
219 | static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed); | |
220 | static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); | |
221 | ||
222 | /* Probing */ | |
223 | static int __init smsc_ircc_look_for_chips(void); | |
b6158d23 DT |
224 | static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type); |
225 | static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type); | |
226 | static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type); | |
1da177e4 LT |
227 | static int __init smsc_superio_fdc(unsigned short cfg_base); |
228 | static int __init smsc_superio_lpc(unsigned short cfg_base); | |
c1e14a6e LW |
229 | #ifdef CONFIG_PCI |
230 | static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf); | |
231 | static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); | |
08d09997 LW |
232 | static void __init preconfigure_ali_port(struct pci_dev *dev, |
233 | unsigned short port); | |
c1e14a6e LW |
234 | static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); |
235 | static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, | |
236 | unsigned short ircc_fir, | |
237 | unsigned short ircc_sir, | |
238 | unsigned char ircc_dma, | |
239 | unsigned char ircc_irq); | |
240 | #endif | |
1da177e4 LT |
241 | |
242 | /* Transceivers specific functions */ | |
243 | ||
244 | static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed); | |
245 | static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base); | |
246 | static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed); | |
247 | static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base); | |
248 | static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed); | |
249 | static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base); | |
250 | ||
251 | /* Power Management */ | |
252 | ||
3ae5eaec RK |
253 | static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state); |
254 | static int smsc_ircc_resume(struct platform_device *dev); | |
1da177e4 | 255 | |
3ae5eaec | 256 | static struct platform_driver smsc_ircc_driver = { |
6bb3b2cd DT |
257 | .suspend = smsc_ircc_suspend, |
258 | .resume = smsc_ircc_resume, | |
3ae5eaec RK |
259 | .driver = { |
260 | .name = SMSC_IRCC2_DRIVER_NAME, | |
261 | }, | |
6bb3b2cd | 262 | }; |
1da177e4 LT |
263 | |
264 | /* Transceivers for SMSC-ircc */ | |
265 | ||
b6158d23 | 266 | static struct smsc_transceiver smsc_transceivers[] = |
1da177e4 | 267 | { |
98b77773 DT |
268 | { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, |
269 | { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, | |
270 | { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, | |
271 | { NULL, NULL } | |
1da177e4 | 272 | }; |
a956f4ca | 273 | #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1) |
1da177e4 LT |
274 | |
275 | /* SMC SuperIO chipsets definitions */ | |
276 | ||
277 | #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */ | |
278 | #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */ | |
279 | #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */ | |
280 | #define SIR 0 /* SuperIO Chip has only slow IRDA */ | |
281 | #define FIR 4 /* SuperIO Chip has fast IRDA */ | |
282 | #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ | |
283 | ||
b6158d23 | 284 | static struct smsc_chip __initdata fdc_chips_flat[] = |
1da177e4 LT |
285 | { |
286 | /* Base address 0x3f0 or 0x370 */ | |
287 | { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ | |
288 | { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 }, | |
289 | { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 }, | |
290 | { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 }, | |
291 | { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */ | |
292 | { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 }, | |
293 | { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 }, | |
294 | { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 }, | |
295 | { NULL } | |
296 | }; | |
297 | ||
b6158d23 | 298 | static struct smsc_chip __initdata fdc_chips_paged[] = |
1da177e4 LT |
299 | { |
300 | /* Base address 0x3f0 or 0x370 */ | |
301 | { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, | |
302 | { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 }, | |
303 | { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 }, | |
304 | { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 }, | |
305 | { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 }, | |
306 | { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 }, | |
307 | { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 }, | |
308 | { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 }, | |
309 | { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 }, | |
310 | { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 }, | |
311 | { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 }, | |
312 | { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 }, | |
313 | { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 }, | |
314 | { NULL } | |
315 | }; | |
316 | ||
b6158d23 | 317 | static struct smsc_chip __initdata lpc_chips_flat[] = |
1da177e4 LT |
318 | { |
319 | /* Base address 0x2E or 0x4E */ | |
320 | { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, | |
afdf27c9 | 321 | { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 }, |
1da177e4 LT |
322 | { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 }, |
323 | { NULL } | |
324 | }; | |
325 | ||
b6158d23 | 326 | static struct smsc_chip __initdata lpc_chips_paged[] = |
1da177e4 LT |
327 | { |
328 | /* Base address 0x2E or 0x4E */ | |
329 | { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, | |
330 | { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 }, | |
331 | { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, | |
332 | { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 }, | |
333 | { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, | |
334 | { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 }, | |
335 | { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 }, | |
336 | { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 }, | |
337 | { NULL } | |
338 | }; | |
339 | ||
340 | #define SMSCSIO_TYPE_FDC 1 | |
341 | #define SMSCSIO_TYPE_LPC 2 | |
342 | #define SMSCSIO_TYPE_FLAT 4 | |
343 | #define SMSCSIO_TYPE_PAGED 8 | |
344 | ||
b6158d23 | 345 | static struct smsc_chip_address __initdata possible_addresses[] = |
1da177e4 | 346 | { |
98b77773 DT |
347 | { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
348 | { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
349 | { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
350 | { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
351 | { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
352 | { 0, 0 } | |
1da177e4 LT |
353 | }; |
354 | ||
355 | /* Globals */ | |
356 | ||
98b77773 DT |
357 | static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; |
358 | static unsigned short dev_count; | |
1da177e4 LT |
359 | |
360 | static inline void register_bank(int iobase, int bank) | |
361 | { | |
98b77773 DT |
362 | outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), |
363 | iobase + IRCC_MASTER); | |
1da177e4 LT |
364 | } |
365 | ||
d94c77b9 DB |
366 | /* PNP hotplug support */ |
367 | static const struct pnp_device_id smsc_ircc_pnp_table[] = { | |
368 | { .id = "SMCf010", .driver_data = 0 }, | |
369 | /* and presumably others */ | |
370 | { } | |
371 | }; | |
372 | MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table); | |
d0d4f69b BH |
373 | |
374 | static int pnp_driver_registered; | |
375 | ||
7a1aa309 | 376 | #ifdef CONFIG_PNP |
d0d4f69b BH |
377 | static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev, |
378 | const struct pnp_device_id *dev_id) | |
379 | { | |
380 | unsigned int firbase, sirbase; | |
381 | u8 dma, irq; | |
382 | ||
383 | if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) && | |
384 | pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0))) | |
385 | return -EINVAL; | |
386 | ||
387 | sirbase = pnp_port_start(dev, 0); | |
388 | firbase = pnp_port_start(dev, 1); | |
389 | dma = pnp_dma(dev, 0); | |
390 | irq = pnp_irq(dev, 0); | |
391 | ||
392 | if (smsc_ircc_open(firbase, sirbase, dma, irq)) | |
393 | return -ENODEV; | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | static struct pnp_driver smsc_ircc_pnp_driver = { | |
399 | .name = "smsc-ircc2", | |
400 | .id_table = smsc_ircc_pnp_table, | |
401 | .probe = smsc_ircc_pnp_probe, | |
402 | }; | |
7a1aa309 IM |
403 | #else /* CONFIG_PNP */ |
404 | static struct pnp_driver smsc_ircc_pnp_driver; | |
405 | #endif | |
1da177e4 LT |
406 | |
407 | /******************************************************************************* | |
408 | * | |
409 | * | |
410 | * SMSC-ircc stuff | |
411 | * | |
412 | * | |
413 | *******************************************************************************/ | |
414 | ||
d0d4f69b BH |
415 | static int __init smsc_ircc_legacy_probe(void) |
416 | { | |
417 | int ret = 0; | |
418 | ||
7c31d2f5 BH |
419 | #ifdef CONFIG_PCI |
420 | if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) { | |
421 | /* Ignore errors from preconfiguration */ | |
422 | IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name); | |
423 | } | |
424 | #endif | |
425 | ||
d0d4f69b BH |
426 | if (ircc_fir > 0 && ircc_sir > 0) { |
427 | IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); | |
428 | IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); | |
429 | ||
430 | if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq)) | |
431 | ret = -ENODEV; | |
432 | } else { | |
433 | ret = -ENODEV; | |
434 | ||
435 | /* try user provided configuration register base address */ | |
436 | if (ircc_cfg > 0) { | |
437 | IRDA_MESSAGE(" Overriding configuration address " | |
438 | "0x%04x\n", ircc_cfg); | |
439 | if (!smsc_superio_fdc(ircc_cfg)) | |
440 | ret = 0; | |
441 | if (!smsc_superio_lpc(ircc_cfg)) | |
442 | ret = 0; | |
443 | } | |
444 | ||
445 | if (smsc_ircc_look_for_chips() > 0) | |
446 | ret = 0; | |
447 | } | |
448 | return ret; | |
449 | } | |
450 | ||
1da177e4 LT |
451 | /* |
452 | * Function smsc_ircc_init () | |
453 | * | |
454 | * Initialize chip. Just try to find out how many chips we are dealing with | |
455 | * and where they are | |
456 | */ | |
457 | static int __init smsc_ircc_init(void) | |
458 | { | |
6bb3b2cd | 459 | int ret; |
1da177e4 | 460 | |
a97a6f10 | 461 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 | 462 | |
3ae5eaec | 463 | ret = platform_driver_register(&smsc_ircc_driver); |
6bb3b2cd DT |
464 | if (ret) { |
465 | IRDA_ERROR("%s, Can't register driver!\n", driver_name); | |
466 | return ret; | |
467 | } | |
468 | ||
98b77773 | 469 | dev_count = 0; |
527b6af4 | 470 | |
d0d4f69b BH |
471 | if (smsc_nopnp || !pnp_platform_devices || |
472 | ircc_cfg || ircc_fir || ircc_sir || | |
473 | ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) { | |
474 | ret = smsc_ircc_legacy_probe(); | |
6bb3b2cd | 475 | } else { |
d0d4f69b BH |
476 | if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0) |
477 | pnp_driver_registered = 1; | |
1da177e4 | 478 | } |
527b6af4 | 479 | |
d0d4f69b BH |
480 | if (ret) { |
481 | if (pnp_driver_registered) | |
482 | pnp_unregister_driver(&smsc_ircc_pnp_driver); | |
3ae5eaec | 483 | platform_driver_unregister(&smsc_ircc_driver); |
d0d4f69b | 484 | } |
527b6af4 | 485 | |
1da177e4 LT |
486 | return ret; |
487 | } | |
488 | ||
489 | /* | |
490 | * Function smsc_ircc_open (firbase, sirbase, dma, irq) | |
491 | * | |
492 | * Try to open driver instance | |
493 | * | |
494 | */ | |
495 | static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq) | |
496 | { | |
497 | struct smsc_ircc_cb *self; | |
498 | struct net_device *dev; | |
499 | int err; | |
527b6af4 | 500 | |
a97a6f10 | 501 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
502 | |
503 | err = smsc_ircc_present(fir_base, sir_base); | |
98b77773 | 504 | if (err) |
1da177e4 | 505 | goto err_out; |
527b6af4 | 506 | |
1da177e4 | 507 | err = -ENOMEM; |
a956f4ca | 508 | if (dev_count >= ARRAY_SIZE(dev_self)) { |
a97a6f10 | 509 | IRDA_WARNING("%s(), too many devices!\n", __func__); |
1da177e4 LT |
510 | goto err_out1; |
511 | } | |
512 | ||
513 | /* | |
514 | * Allocate new instance of the driver | |
515 | */ | |
516 | dev = alloc_irdadev(sizeof(struct smsc_ircc_cb)); | |
517 | if (!dev) { | |
a97a6f10 | 518 | IRDA_WARNING("%s() can't allocate net device\n", __func__); |
1da177e4 LT |
519 | goto err_out1; |
520 | } | |
521 | ||
1da177e4 LT |
522 | dev->hard_start_xmit = smsc_ircc_hard_xmit_sir; |
523 | #if SMSC_IRCC2_C_NET_TIMEOUT | |
524 | dev->tx_timeout = smsc_ircc_timeout; | |
98b77773 | 525 | dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ |
1da177e4 LT |
526 | #endif |
527 | dev->open = smsc_ircc_net_open; | |
528 | dev->stop = smsc_ircc_net_close; | |
529 | dev->do_ioctl = smsc_ircc_net_ioctl; | |
527b6af4 | 530 | |
da0841a0 | 531 | self = netdev_priv(dev); |
1da177e4 LT |
532 | self->netdev = dev; |
533 | ||
534 | /* Make ifconfig display some details */ | |
535 | dev->base_addr = self->io.fir_base = fir_base; | |
536 | dev->irq = self->io.irq = irq; | |
537 | ||
538 | /* Need to store self somewhere */ | |
6bb3b2cd | 539 | dev_self[dev_count] = self; |
1da177e4 LT |
540 | spin_lock_init(&self->lock); |
541 | ||
527b6af4 | 542 | self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE; |
1da177e4 LT |
543 | self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE; |
544 | ||
545 | self->rx_buff.head = | |
546 | dma_alloc_coherent(NULL, self->rx_buff.truesize, | |
547 | &self->rx_buff_dma, GFP_KERNEL); | |
548 | if (self->rx_buff.head == NULL) { | |
549 | IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n", | |
550 | driver_name); | |
551 | goto err_out2; | |
552 | } | |
553 | ||
554 | self->tx_buff.head = | |
555 | dma_alloc_coherent(NULL, self->tx_buff.truesize, | |
556 | &self->tx_buff_dma, GFP_KERNEL); | |
557 | if (self->tx_buff.head == NULL) { | |
558 | IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n", | |
559 | driver_name); | |
560 | goto err_out3; | |
561 | } | |
562 | ||
563 | memset(self->rx_buff.head, 0, self->rx_buff.truesize); | |
564 | memset(self->tx_buff.head, 0, self->tx_buff.truesize); | |
565 | ||
566 | self->rx_buff.in_frame = FALSE; | |
567 | self->rx_buff.state = OUTSIDE_FRAME; | |
568 | self->tx_buff.data = self->tx_buff.head; | |
569 | self->rx_buff.data = self->rx_buff.head; | |
527b6af4 | 570 | |
1da177e4 | 571 | smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); |
1da177e4 | 572 | smsc_ircc_setup_qos(self); |
1da177e4 | 573 | smsc_ircc_init_chip(self); |
527b6af4 | 574 | |
98b77773 DT |
575 | if (ircc_transceiver > 0 && |
576 | ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) | |
1da177e4 LT |
577 | self->transceiver = ircc_transceiver; |
578 | else | |
579 | smsc_ircc_probe_transceiver(self); | |
580 | ||
581 | err = register_netdev(self->netdev); | |
98b77773 | 582 | if (err) { |
1da177e4 LT |
583 | IRDA_ERROR("%s, Network device registration failed!\n", |
584 | driver_name); | |
585 | goto err_out4; | |
586 | } | |
587 | ||
6bb3b2cd DT |
588 | self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME, |
589 | dev_count, NULL, 0); | |
590 | if (IS_ERR(self->pldev)) { | |
591 | err = PTR_ERR(self->pldev); | |
592 | goto err_out5; | |
593 | } | |
3ae5eaec | 594 | platform_set_drvdata(self->pldev, self); |
1da177e4 LT |
595 | |
596 | IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); | |
6bb3b2cd | 597 | dev_count++; |
1da177e4 LT |
598 | |
599 | return 0; | |
98b77773 | 600 | |
6bb3b2cd DT |
601 | err_out5: |
602 | unregister_netdev(self->netdev); | |
603 | ||
1da177e4 LT |
604 | err_out4: |
605 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
606 | self->tx_buff.head, self->tx_buff_dma); | |
607 | err_out3: | |
608 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
609 | self->rx_buff.head, self->rx_buff_dma); | |
610 | err_out2: | |
611 | free_netdev(self->netdev); | |
6bb3b2cd | 612 | dev_self[dev_count] = NULL; |
1da177e4 LT |
613 | err_out1: |
614 | release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); | |
615 | release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); | |
616 | err_out: | |
617 | return err; | |
618 | } | |
619 | ||
620 | /* | |
621 | * Function smsc_ircc_present(fir_base, sir_base) | |
622 | * | |
623 | * Check the smsc-ircc chip presence | |
624 | * | |
625 | */ | |
626 | static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) | |
627 | { | |
628 | unsigned char low, high, chip, config, dma, irq, version; | |
629 | ||
630 | if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT, | |
631 | driver_name)) { | |
632 | IRDA_WARNING("%s: can't get fir_base of 0x%03x\n", | |
a97a6f10 | 633 | __func__, fir_base); |
1da177e4 LT |
634 | goto out1; |
635 | } | |
636 | ||
637 | if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT, | |
638 | driver_name)) { | |
639 | IRDA_WARNING("%s: can't get sir_base of 0x%03x\n", | |
a97a6f10 | 640 | __func__, sir_base); |
1da177e4 LT |
641 | goto out2; |
642 | } | |
643 | ||
644 | register_bank(fir_base, 3); | |
645 | ||
98b77773 DT |
646 | high = inb(fir_base + IRCC_ID_HIGH); |
647 | low = inb(fir_base + IRCC_ID_LOW); | |
648 | chip = inb(fir_base + IRCC_CHIP_ID); | |
649 | version = inb(fir_base + IRCC_VERSION); | |
650 | config = inb(fir_base + IRCC_INTERFACE); | |
1da177e4 LT |
651 | dma = config & IRCC_INTERFACE_DMA_MASK; |
652 | irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; | |
653 | ||
527b6af4 | 654 | if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { |
98b77773 | 655 | IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", |
a97a6f10 | 656 | __func__, fir_base); |
1da177e4 LT |
657 | goto out3; |
658 | } | |
659 | IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, " | |
660 | "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n", | |
661 | chip & 0x0f, version, fir_base, sir_base, dma, irq); | |
662 | ||
663 | return 0; | |
98b77773 | 664 | |
1da177e4 LT |
665 | out3: |
666 | release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); | |
667 | out2: | |
668 | release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); | |
669 | out1: | |
670 | return -ENODEV; | |
671 | } | |
672 | ||
673 | /* | |
674 | * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq) | |
675 | * | |
676 | * Setup I/O | |
677 | * | |
678 | */ | |
527b6af4 DT |
679 | static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, |
680 | unsigned int fir_base, unsigned int sir_base, | |
1da177e4 LT |
681 | u8 dma, u8 irq) |
682 | { | |
683 | unsigned char config, chip_dma, chip_irq; | |
684 | ||
685 | register_bank(fir_base, 3); | |
98b77773 DT |
686 | config = inb(fir_base + IRCC_INTERFACE); |
687 | chip_dma = config & IRCC_INTERFACE_DMA_MASK; | |
688 | chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; | |
1da177e4 LT |
689 | |
690 | self->io.fir_base = fir_base; | |
691 | self->io.sir_base = sir_base; | |
692 | self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT; | |
693 | self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT; | |
694 | self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE; | |
695 | self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED; | |
696 | ||
916f11c7 | 697 | if (irq != IRQ_INVAL) { |
1da177e4 LT |
698 | if (irq != chip_irq) |
699 | IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", | |
700 | driver_name, chip_irq, irq); | |
701 | self->io.irq = irq; | |
98b77773 | 702 | } else |
1da177e4 | 703 | self->io.irq = chip_irq; |
527b6af4 | 704 | |
916f11c7 | 705 | if (dma != DMA_INVAL) { |
1da177e4 LT |
706 | if (dma != chip_dma) |
707 | IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", | |
708 | driver_name, chip_dma, dma); | |
709 | self->io.dma = dma; | |
98b77773 | 710 | } else |
1da177e4 LT |
711 | self->io.dma = chip_dma; |
712 | ||
713 | } | |
714 | ||
715 | /* | |
716 | * Function smsc_ircc_setup_qos(self) | |
717 | * | |
718 | * Setup qos | |
719 | * | |
720 | */ | |
721 | static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self) | |
722 | { | |
723 | /* Initialize QoS for this device */ | |
724 | irda_init_max_qos_capabilies(&self->qos); | |
527b6af4 | 725 | |
1da177e4 LT |
726 | self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| |
727 | IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); | |
728 | ||
729 | self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME; | |
730 | self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE; | |
731 | irda_qos_bits_to_value(&self->qos); | |
732 | } | |
733 | ||
734 | /* | |
735 | * Function smsc_ircc_init_chip(self) | |
736 | * | |
737 | * Init chip | |
738 | * | |
739 | */ | |
740 | static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) | |
741 | { | |
e812cb52 | 742 | int iobase = self->io.fir_base; |
1da177e4 LT |
743 | |
744 | register_bank(iobase, 0); | |
98b77773 DT |
745 | outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); |
746 | outb(0x00, iobase + IRCC_MASTER); | |
1da177e4 LT |
747 | |
748 | register_bank(iobase, 1); | |
e812cb52 | 749 | outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), |
98b77773 | 750 | iobase + IRCC_SCE_CFGA); |
1da177e4 LT |
751 | |
752 | #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ | |
98b77773 DT |
753 | outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), |
754 | iobase + IRCC_SCE_CFGB); | |
527b6af4 | 755 | #else |
98b77773 DT |
756 | outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), |
757 | iobase + IRCC_SCE_CFGB); | |
527b6af4 | 758 | #endif |
98b77773 DT |
759 | (void) inb(iobase + IRCC_FIFO_THRESHOLD); |
760 | outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); | |
527b6af4 | 761 | |
1da177e4 | 762 | register_bank(iobase, 4); |
e812cb52 | 763 | outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); |
527b6af4 | 764 | |
1da177e4 | 765 | register_bank(iobase, 0); |
e812cb52 | 766 | outb(0, iobase + IRCC_LCR_A); |
1da177e4 LT |
767 | |
768 | smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); | |
527b6af4 | 769 | |
1da177e4 | 770 | /* Power on device */ |
98b77773 | 771 | outb(0x00, iobase + IRCC_MASTER); |
1da177e4 LT |
772 | } |
773 | ||
774 | /* | |
775 | * Function smsc_ircc_net_ioctl (dev, rq, cmd) | |
776 | * | |
777 | * Process IOCTL commands for this device | |
778 | * | |
779 | */ | |
780 | static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
781 | { | |
782 | struct if_irda_req *irq = (struct if_irda_req *) rq; | |
783 | struct smsc_ircc_cb *self; | |
784 | unsigned long flags; | |
785 | int ret = 0; | |
786 | ||
787 | IRDA_ASSERT(dev != NULL, return -1;); | |
788 | ||
da0841a0 | 789 | self = netdev_priv(dev); |
1da177e4 LT |
790 | |
791 | IRDA_ASSERT(self != NULL, return -1;); | |
792 | ||
a97a6f10 | 793 | IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd); |
527b6af4 | 794 | |
1da177e4 LT |
795 | switch (cmd) { |
796 | case SIOCSBANDWIDTH: /* Set bandwidth */ | |
797 | if (!capable(CAP_NET_ADMIN)) | |
798 | ret = -EPERM; | |
799 | else { | |
800 | /* Make sure we are the only one touching | |
801 | * self->io.speed and the hardware - Jean II */ | |
802 | spin_lock_irqsave(&self->lock, flags); | |
803 | smsc_ircc_change_speed(self, irq->ifr_baudrate); | |
804 | spin_unlock_irqrestore(&self->lock, flags); | |
805 | } | |
806 | break; | |
807 | case SIOCSMEDIABUSY: /* Set media busy */ | |
808 | if (!capable(CAP_NET_ADMIN)) { | |
809 | ret = -EPERM; | |
810 | break; | |
811 | } | |
812 | ||
813 | irda_device_set_media_busy(self->netdev, TRUE); | |
814 | break; | |
815 | case SIOCGRECEIVING: /* Check if we are receiving right now */ | |
816 | irq->ifr_receiving = smsc_ircc_is_receiving(self); | |
817 | break; | |
818 | #if 0 | |
819 | case SIOCSDTRRTS: | |
820 | if (!capable(CAP_NET_ADMIN)) { | |
821 | ret = -EPERM; | |
822 | break; | |
823 | } | |
824 | smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts); | |
825 | break; | |
826 | #endif | |
827 | default: | |
828 | ret = -EOPNOTSUPP; | |
829 | } | |
527b6af4 | 830 | |
1da177e4 LT |
831 | return ret; |
832 | } | |
833 | ||
1da177e4 LT |
834 | #if SMSC_IRCC2_C_NET_TIMEOUT |
835 | /* | |
836 | * Function smsc_ircc_timeout (struct net_device *dev) | |
837 | * | |
838 | * The networking timeout management. | |
839 | * | |
840 | */ | |
841 | ||
842 | static void smsc_ircc_timeout(struct net_device *dev) | |
843 | { | |
da0841a0 | 844 | struct smsc_ircc_cb *self = netdev_priv(dev); |
1da177e4 LT |
845 | unsigned long flags; |
846 | ||
1da177e4 LT |
847 | IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n", |
848 | dev->name, self->io.speed); | |
849 | spin_lock_irqsave(&self->lock, flags); | |
850 | smsc_ircc_sir_start(self); | |
851 | smsc_ircc_change_speed(self, self->io.speed); | |
852 | dev->trans_start = jiffies; | |
853 | netif_wake_queue(dev); | |
854 | spin_unlock_irqrestore(&self->lock, flags); | |
855 | } | |
856 | #endif | |
857 | ||
858 | /* | |
859 | * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev) | |
860 | * | |
861 | * Transmits the current frame until FIFO is full, then | |
862 | * waits until the next transmit interrupt, and continues until the | |
863 | * frame is transmitted. | |
864 | */ | |
0e49e645 | 865 | static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
866 | { |
867 | struct smsc_ircc_cb *self; | |
868 | unsigned long flags; | |
1da177e4 LT |
869 | s32 speed; |
870 | ||
a97a6f10 | 871 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
872 | |
873 | IRDA_ASSERT(dev != NULL, return 0;); | |
527b6af4 | 874 | |
da0841a0 | 875 | self = netdev_priv(dev); |
1da177e4 LT |
876 | IRDA_ASSERT(self != NULL, return 0;); |
877 | ||
1da177e4 | 878 | netif_stop_queue(dev); |
527b6af4 | 879 | |
1da177e4 LT |
880 | /* Make sure test of self->io.speed & speed change are atomic */ |
881 | spin_lock_irqsave(&self->lock, flags); | |
882 | ||
883 | /* Check if we need to change the speed */ | |
884 | speed = irda_get_next_speed(skb); | |
98b77773 | 885 | if (speed != self->io.speed && speed != -1) { |
1da177e4 LT |
886 | /* Check for empty frame */ |
887 | if (!skb->len) { | |
888 | /* | |
889 | * We send frames one by one in SIR mode (no | |
890 | * pipelining), so at this point, if we were sending | |
891 | * a previous frame, we just received the interrupt | |
892 | * telling us it is finished (UART_IIR_THRI). | |
893 | * Therefore, waiting for the transmitter to really | |
894 | * finish draining the fifo won't take too long. | |
895 | * And the interrupt handler is not expected to run. | |
896 | * - Jean II */ | |
897 | smsc_ircc_sir_wait_hw_transmitter_finish(self); | |
898 | smsc_ircc_change_speed(self, speed); | |
899 | spin_unlock_irqrestore(&self->lock, flags); | |
900 | dev_kfree_skb(skb); | |
901 | return 0; | |
1da177e4 | 902 | } |
98b77773 | 903 | self->new_speed = speed; |
1da177e4 LT |
904 | } |
905 | ||
906 | /* Init tx buffer */ | |
907 | self->tx_buff.data = self->tx_buff.head; | |
908 | ||
909 | /* Copy skb to tx_buff while wrapping, stuffing and making CRC */ | |
527b6af4 | 910 | self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, |
1da177e4 | 911 | self->tx_buff.truesize); |
527b6af4 | 912 | |
af049081 | 913 | dev->stats.tx_bytes += self->tx_buff.len; |
1da177e4 LT |
914 | |
915 | /* Turn on transmit finished interrupt. Will fire immediately! */ | |
80a90589 | 916 | outb(UART_IER_THRI, self->io.sir_base + UART_IER); |
1da177e4 LT |
917 | |
918 | spin_unlock_irqrestore(&self->lock, flags); | |
919 | ||
920 | dev_kfree_skb(skb); | |
527b6af4 | 921 | |
1da177e4 LT |
922 | return 0; |
923 | } | |
924 | ||
925 | /* | |
926 | * Function smsc_ircc_set_fir_speed (self, baud) | |
927 | * | |
928 | * Change the speed of the device | |
929 | * | |
930 | */ | |
931 | static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) | |
932 | { | |
933 | int fir_base, ir_mode, ctrl, fast; | |
934 | ||
935 | IRDA_ASSERT(self != NULL, return;); | |
936 | fir_base = self->io.fir_base; | |
937 | ||
938 | self->io.speed = speed; | |
939 | ||
98b77773 | 940 | switch (speed) { |
1da177e4 | 941 | default: |
527b6af4 | 942 | case 576000: |
1da177e4 LT |
943 | ir_mode = IRCC_CFGA_IRDA_HDLC; |
944 | ctrl = IRCC_CRC; | |
945 | fast = 0; | |
a97a6f10 | 946 | IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__); |
1da177e4 LT |
947 | break; |
948 | case 1152000: | |
949 | ir_mode = IRCC_CFGA_IRDA_HDLC; | |
950 | ctrl = IRCC_1152 | IRCC_CRC; | |
951 | fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA; | |
952 | IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", | |
a97a6f10 | 953 | __func__); |
1da177e4 LT |
954 | break; |
955 | case 4000000: | |
956 | ir_mode = IRCC_CFGA_IRDA_4PPM; | |
957 | ctrl = IRCC_CRC; | |
958 | fast = IRCC_LCR_A_FAST; | |
959 | IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", | |
a97a6f10 | 960 | __func__); |
1da177e4 LT |
961 | break; |
962 | } | |
963 | #if 0 | |
964 | Now in tranceiver! | |
965 | /* This causes an interrupt */ | |
966 | register_bank(fir_base, 0); | |
98b77773 | 967 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); |
1da177e4 | 968 | #endif |
527b6af4 | 969 | |
1da177e4 | 970 | register_bank(fir_base, 1); |
98b77773 | 971 | outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); |
527b6af4 | 972 | |
1da177e4 | 973 | register_bank(fir_base, 4); |
98b77773 | 974 | outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); |
1da177e4 LT |
975 | } |
976 | ||
977 | /* | |
978 | * Function smsc_ircc_fir_start(self) | |
979 | * | |
980 | * Change the speed of the device | |
981 | * | |
982 | */ | |
983 | static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) | |
984 | { | |
985 | struct net_device *dev; | |
986 | int fir_base; | |
987 | ||
a97a6f10 | 988 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
989 | |
990 | IRDA_ASSERT(self != NULL, return;); | |
991 | dev = self->netdev; | |
992 | IRDA_ASSERT(dev != NULL, return;); | |
993 | ||
994 | fir_base = self->io.fir_base; | |
995 | ||
996 | /* Reset everything */ | |
997 | ||
998 | /* Install FIR transmit handler */ | |
527b6af4 | 999 | dev->hard_start_xmit = smsc_ircc_hard_xmit_fir; |
1da177e4 LT |
1000 | |
1001 | /* Clear FIFO */ | |
98b77773 | 1002 | outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); |
1da177e4 LT |
1003 | |
1004 | /* Enable interrupt */ | |
98b77773 | 1005 | /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ |
1da177e4 LT |
1006 | |
1007 | register_bank(fir_base, 1); | |
1008 | ||
527b6af4 | 1009 | /* Select the TX/RX interface */ |
1da177e4 | 1010 | #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ |
98b77773 DT |
1011 | outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), |
1012 | fir_base + IRCC_SCE_CFGB); | |
527b6af4 | 1013 | #else |
98b77773 DT |
1014 | outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), |
1015 | fir_base + IRCC_SCE_CFGB); | |
527b6af4 | 1016 | #endif |
98b77773 | 1017 | (void) inb(fir_base + IRCC_FIFO_THRESHOLD); |
1da177e4 LT |
1018 | |
1019 | /* Enable SCE interrupts */ | |
98b77773 | 1020 | outb(0, fir_base + IRCC_MASTER); |
1da177e4 | 1021 | register_bank(fir_base, 0); |
98b77773 DT |
1022 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); |
1023 | outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); | |
1da177e4 LT |
1024 | } |
1025 | ||
1026 | /* | |
1027 | * Function smsc_ircc_fir_stop(self, baud) | |
1028 | * | |
1029 | * Change the speed of the device | |
1030 | * | |
1031 | */ | |
1032 | static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) | |
1033 | { | |
1034 | int fir_base; | |
1035 | ||
a97a6f10 | 1036 | IRDA_DEBUG(1, "%s\n", __func__); |
527b6af4 | 1037 | |
1da177e4 LT |
1038 | IRDA_ASSERT(self != NULL, return;); |
1039 | ||
1040 | fir_base = self->io.fir_base; | |
1041 | register_bank(fir_base, 0); | |
98b77773 DT |
1042 | /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ |
1043 | outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); | |
1da177e4 LT |
1044 | } |
1045 | ||
1046 | ||
1047 | /* | |
1048 | * Function smsc_ircc_change_speed(self, baud) | |
1049 | * | |
1050 | * Change the speed of the device | |
1051 | * | |
1052 | * This function *must* be called with spinlock held, because it may | |
1053 | * be called from the irq handler. - Jean II | |
1054 | */ | |
0fa2f491 | 1055 | static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed) |
1da177e4 | 1056 | { |
1da177e4 | 1057 | struct net_device *dev; |
1da177e4 | 1058 | int last_speed_was_sir; |
527b6af4 | 1059 | |
a97a6f10 | 1060 | IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed); |
1da177e4 LT |
1061 | |
1062 | IRDA_ASSERT(self != NULL, return;); | |
1063 | dev = self->netdev; | |
1da177e4 LT |
1064 | |
1065 | last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED; | |
1066 | ||
1067 | #if 0 | |
1068 | /* Temp Hack */ | |
1069 | speed= 1152000; | |
1070 | self->io.speed = speed; | |
1071 | last_speed_was_sir = 0; | |
527b6af4 | 1072 | smsc_ircc_fir_start(self); |
1da177e4 | 1073 | #endif |
527b6af4 | 1074 | |
98b77773 | 1075 | if (self->io.speed == 0) |
1da177e4 LT |
1076 | smsc_ircc_sir_start(self); |
1077 | ||
1078 | #if 0 | |
98b77773 | 1079 | if (!last_speed_was_sir) speed = self->io.speed; |
1da177e4 LT |
1080 | #endif |
1081 | ||
98b77773 DT |
1082 | if (self->io.speed != speed) |
1083 | smsc_ircc_set_transceiver_for_speed(self, speed); | |
1da177e4 LT |
1084 | |
1085 | self->io.speed = speed; | |
527b6af4 | 1086 | |
98b77773 DT |
1087 | if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { |
1088 | if (!last_speed_was_sir) { | |
1da177e4 LT |
1089 | smsc_ircc_fir_stop(self); |
1090 | smsc_ircc_sir_start(self); | |
1091 | } | |
527b6af4 | 1092 | smsc_ircc_set_sir_speed(self, speed); |
98b77773 DT |
1093 | } else { |
1094 | if (last_speed_was_sir) { | |
527b6af4 | 1095 | #if SMSC_IRCC2_C_SIR_STOP |
1da177e4 LT |
1096 | smsc_ircc_sir_stop(self); |
1097 | #endif | |
1098 | smsc_ircc_fir_start(self); | |
1099 | } | |
1100 | smsc_ircc_set_fir_speed(self, speed); | |
1101 | ||
1102 | #if 0 | |
1103 | self->tx_buff.len = 10; | |
1104 | self->tx_buff.data = self->tx_buff.head; | |
527b6af4 | 1105 | |
80a90589 | 1106 | smsc_ircc_dma_xmit(self, 4000); |
1da177e4 LT |
1107 | #endif |
1108 | /* Be ready for incoming frames */ | |
80a90589 | 1109 | smsc_ircc_dma_receive(self); |
1da177e4 | 1110 | } |
527b6af4 | 1111 | |
1da177e4 LT |
1112 | netif_wake_queue(dev); |
1113 | } | |
1114 | ||
1115 | /* | |
1116 | * Function smsc_ircc_set_sir_speed (self, speed) | |
1117 | * | |
1118 | * Set speed of IrDA port to specified baudrate | |
1119 | * | |
1120 | */ | |
0e49e645 | 1121 | static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed) |
1da177e4 | 1122 | { |
527b6af4 | 1123 | int iobase; |
1da177e4 LT |
1124 | int fcr; /* FIFO control reg */ |
1125 | int lcr; /* Line control reg */ | |
1126 | int divisor; | |
1127 | ||
a97a6f10 | 1128 | IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed); |
1da177e4 LT |
1129 | |
1130 | IRDA_ASSERT(self != NULL, return;); | |
1131 | iobase = self->io.sir_base; | |
527b6af4 | 1132 | |
1da177e4 LT |
1133 | /* Update accounting for new speed */ |
1134 | self->io.speed = speed; | |
1135 | ||
1136 | /* Turn off interrupts */ | |
98b77773 | 1137 | outb(0, iobase + UART_IER); |
1da177e4 | 1138 | |
98b77773 | 1139 | divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; |
527b6af4 | 1140 | |
1da177e4 LT |
1141 | fcr = UART_FCR_ENABLE_FIFO; |
1142 | ||
527b6af4 | 1143 | /* |
1da177e4 LT |
1144 | * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and |
1145 | * almost 1,7 ms at 19200 bps. At speeds above that we can just forget | |
527b6af4 | 1146 | * about this timeout since it will always be fast enough. |
1da177e4 | 1147 | */ |
98b77773 DT |
1148 | fcr |= self->io.speed < 38400 ? |
1149 | UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; | |
527b6af4 | 1150 | |
1da177e4 LT |
1151 | /* IrDA ports use 8N1 */ |
1152 | lcr = UART_LCR_WLEN8; | |
527b6af4 | 1153 | |
98b77773 DT |
1154 | outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ |
1155 | outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ | |
1156 | outb(divisor >> 8, iobase + UART_DLM); | |
1157 | outb(lcr, iobase + UART_LCR); /* Set 8N1 */ | |
1158 | outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ | |
1da177e4 LT |
1159 | |
1160 | /* Turn on interrups */ | |
98b77773 | 1161 | outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); |
1da177e4 | 1162 | |
a97a6f10 | 1163 | IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed); |
1da177e4 LT |
1164 | } |
1165 | ||
1166 | ||
1167 | /* | |
1168 | * Function smsc_ircc_hard_xmit_fir (skb, dev) | |
1169 | * | |
1170 | * Transmit the frame! | |
1171 | * | |
1172 | */ | |
1173 | static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) | |
1174 | { | |
1175 | struct smsc_ircc_cb *self; | |
1176 | unsigned long flags; | |
1177 | s32 speed; | |
1da177e4 LT |
1178 | int mtt; |
1179 | ||
1180 | IRDA_ASSERT(dev != NULL, return 0;); | |
da0841a0 | 1181 | self = netdev_priv(dev); |
1da177e4 LT |
1182 | IRDA_ASSERT(self != NULL, return 0;); |
1183 | ||
1da177e4 LT |
1184 | netif_stop_queue(dev); |
1185 | ||
1186 | /* Make sure test of self->io.speed & speed change are atomic */ | |
1187 | spin_lock_irqsave(&self->lock, flags); | |
1188 | ||
1189 | /* Check if we need to change the speed after this frame */ | |
1190 | speed = irda_get_next_speed(skb); | |
98b77773 | 1191 | if (speed != self->io.speed && speed != -1) { |
1da177e4 LT |
1192 | /* Check for empty frame */ |
1193 | if (!skb->len) { | |
1194 | /* Note : you should make sure that speed changes | |
1195 | * are not going to corrupt any outgoing frame. | |
1196 | * Look at nsc-ircc for the gory details - Jean II */ | |
527b6af4 | 1197 | smsc_ircc_change_speed(self, speed); |
1da177e4 LT |
1198 | spin_unlock_irqrestore(&self->lock, flags); |
1199 | dev_kfree_skb(skb); | |
1200 | return 0; | |
98b77773 DT |
1201 | } |
1202 | ||
1203 | self->new_speed = speed; | |
1da177e4 | 1204 | } |
527b6af4 | 1205 | |
d626f62b | 1206 | skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len); |
1da177e4 LT |
1207 | |
1208 | self->tx_buff.len = skb->len; | |
1209 | self->tx_buff.data = self->tx_buff.head; | |
527b6af4 DT |
1210 | |
1211 | mtt = irda_get_mtt(skb); | |
1da177e4 LT |
1212 | if (mtt) { |
1213 | int bofs; | |
1214 | ||
527b6af4 | 1215 | /* |
1da177e4 LT |
1216 | * Compute how many BOFs (STA or PA's) we need to waste the |
1217 | * min turn time given the speed of the link. | |
1218 | */ | |
1219 | bofs = mtt * (self->io.speed / 1000) / 8000; | |
1220 | if (bofs > 4095) | |
1221 | bofs = 4095; | |
1222 | ||
80a90589 | 1223 | smsc_ircc_dma_xmit(self, bofs); |
1da177e4 LT |
1224 | } else { |
1225 | /* Transmit frame */ | |
80a90589 | 1226 | smsc_ircc_dma_xmit(self, 0); |
1da177e4 | 1227 | } |
98b77773 | 1228 | |
1da177e4 LT |
1229 | spin_unlock_irqrestore(&self->lock, flags); |
1230 | dev_kfree_skb(skb); | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | /* | |
80a90589 | 1236 | * Function smsc_ircc_dma_xmit (self, bofs) |
1da177e4 LT |
1237 | * |
1238 | * Transmit data using DMA | |
1239 | * | |
1240 | */ | |
80a90589 | 1241 | static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs) |
1da177e4 | 1242 | { |
80a90589 | 1243 | int iobase = self->io.fir_base; |
1da177e4 LT |
1244 | u8 ctrl; |
1245 | ||
a97a6f10 | 1246 | IRDA_DEBUG(3, "%s\n", __func__); |
1da177e4 LT |
1247 | #if 1 |
1248 | /* Disable Rx */ | |
1249 | register_bank(iobase, 0); | |
98b77773 | 1250 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 LT |
1251 | #endif |
1252 | register_bank(iobase, 1); | |
98b77773 DT |
1253 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1254 | iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1255 | |
1256 | self->io.direction = IO_XMIT; | |
1257 | ||
1258 | /* Set BOF additional count for generating the min turn time */ | |
1259 | register_bank(iobase, 4); | |
98b77773 DT |
1260 | outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); |
1261 | ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; | |
1262 | outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); | |
1da177e4 LT |
1263 | |
1264 | /* Set max Tx frame size */ | |
98b77773 DT |
1265 | outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); |
1266 | outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); | |
1da177e4 LT |
1267 | |
1268 | /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ | |
527b6af4 | 1269 | |
1da177e4 LT |
1270 | /* Enable burst mode chip Tx DMA */ |
1271 | register_bank(iobase, 1); | |
98b77773 DT |
1272 | outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | |
1273 | IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1274 | |
1275 | /* Setup DMA controller (must be done after enabling chip DMA) */ | |
1276 | irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, | |
1277 | DMA_TX_MODE); | |
1278 | ||
1279 | /* Enable interrupt */ | |
1280 | ||
1281 | register_bank(iobase, 0); | |
98b77773 DT |
1282 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1283 | outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); | |
527b6af4 | 1284 | |
1da177e4 | 1285 | /* Enable transmit */ |
98b77773 | 1286 | outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); |
1da177e4 LT |
1287 | } |
1288 | ||
1289 | /* | |
1290 | * Function smsc_ircc_dma_xmit_complete (self) | |
1291 | * | |
527b6af4 | 1292 | * The transfer of a frame in finished. This function will only be called |
1da177e4 LT |
1293 | * by the interrupt handler |
1294 | * | |
1295 | */ | |
80a90589 | 1296 | static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self) |
1da177e4 | 1297 | { |
80a90589 DT |
1298 | int iobase = self->io.fir_base; |
1299 | ||
a97a6f10 | 1300 | IRDA_DEBUG(3, "%s\n", __func__); |
1da177e4 LT |
1301 | #if 0 |
1302 | /* Disable Tx */ | |
1303 | register_bank(iobase, 0); | |
98b77773 | 1304 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 | 1305 | #endif |
80a90589 DT |
1306 | register_bank(iobase, 1); |
1307 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, | |
1308 | iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1309 | |
1310 | /* Check for underrun! */ | |
1311 | register_bank(iobase, 0); | |
98b77773 | 1312 | if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { |
af049081 SH |
1313 | self->netdev->stats.tx_errors++; |
1314 | self->netdev->stats.tx_fifo_errors++; | |
1da177e4 LT |
1315 | |
1316 | /* Reset error condition */ | |
1317 | register_bank(iobase, 0); | |
98b77773 DT |
1318 | outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); |
1319 | outb(0x00, iobase + IRCC_MASTER); | |
1da177e4 | 1320 | } else { |
af049081 SH |
1321 | self->netdev->stats.tx_packets++; |
1322 | self->netdev->stats.tx_bytes += self->tx_buff.len; | |
1da177e4 LT |
1323 | } |
1324 | ||
1325 | /* Check if it's time to change the speed */ | |
1326 | if (self->new_speed) { | |
527b6af4 | 1327 | smsc_ircc_change_speed(self, self->new_speed); |
1da177e4 LT |
1328 | self->new_speed = 0; |
1329 | } | |
1330 | ||
1331 | netif_wake_queue(self->netdev); | |
1332 | } | |
1333 | ||
1334 | /* | |
1335 | * Function smsc_ircc_dma_receive(self) | |
1336 | * | |
1337 | * Get ready for receiving a frame. The device will initiate a DMA | |
1338 | * if it starts to receive a frame. | |
1339 | * | |
1340 | */ | |
80a90589 | 1341 | static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self) |
1da177e4 | 1342 | { |
80a90589 | 1343 | int iobase = self->io.fir_base; |
1da177e4 LT |
1344 | #if 0 |
1345 | /* Turn off chip DMA */ | |
1346 | register_bank(iobase, 1); | |
98b77773 DT |
1347 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1348 | iobase + IRCC_SCE_CFGB); | |
1da177e4 | 1349 | #endif |
527b6af4 | 1350 | |
1da177e4 LT |
1351 | /* Disable Tx */ |
1352 | register_bank(iobase, 0); | |
98b77773 | 1353 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 LT |
1354 | |
1355 | /* Turn off chip DMA */ | |
1356 | register_bank(iobase, 1); | |
98b77773 DT |
1357 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1358 | iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1359 | |
1360 | self->io.direction = IO_RECV; | |
1361 | self->rx_buff.data = self->rx_buff.head; | |
1362 | ||
1363 | /* Set max Rx frame size */ | |
1364 | register_bank(iobase, 4); | |
98b77773 DT |
1365 | outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); |
1366 | outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); | |
1da177e4 LT |
1367 | |
1368 | /* Setup DMA controller */ | |
1369 | irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, | |
1370 | DMA_RX_MODE); | |
1371 | ||
1372 | /* Enable burst mode chip Rx DMA */ | |
1373 | register_bank(iobase, 1); | |
98b77773 DT |
1374 | outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | |
1375 | IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1376 | |
1377 | /* Enable interrupt */ | |
1378 | register_bank(iobase, 0); | |
98b77773 DT |
1379 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1380 | outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); | |
1da177e4 LT |
1381 | |
1382 | /* Enable receiver */ | |
1383 | register_bank(iobase, 0); | |
527b6af4 | 1384 | outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, |
98b77773 | 1385 | iobase + IRCC_LCR_B); |
527b6af4 | 1386 | |
1da177e4 LT |
1387 | return 0; |
1388 | } | |
1389 | ||
1390 | /* | |
80a90589 | 1391 | * Function smsc_ircc_dma_receive_complete(self) |
1da177e4 LT |
1392 | * |
1393 | * Finished with receiving frames | |
1394 | * | |
1395 | */ | |
80a90589 | 1396 | static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self) |
1da177e4 LT |
1397 | { |
1398 | struct sk_buff *skb; | |
1399 | int len, msgcnt, lsr; | |
80a90589 | 1400 | int iobase = self->io.fir_base; |
527b6af4 | 1401 | |
1da177e4 | 1402 | register_bank(iobase, 0); |
527b6af4 | 1403 | |
a97a6f10 | 1404 | IRDA_DEBUG(3, "%s\n", __func__); |
1da177e4 LT |
1405 | #if 0 |
1406 | /* Disable Rx */ | |
1407 | register_bank(iobase, 0); | |
98b77773 | 1408 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 LT |
1409 | #endif |
1410 | register_bank(iobase, 0); | |
98b77773 DT |
1411 | outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); |
1412 | lsr= inb(iobase + IRCC_LSR); | |
1413 | msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; | |
1da177e4 | 1414 | |
a97a6f10 | 1415 | IRDA_DEBUG(2, "%s: dma count = %d\n", __func__, |
1da177e4 LT |
1416 | get_dma_residue(self->io.dma)); |
1417 | ||
1418 | len = self->rx_buff.truesize - get_dma_residue(self->io.dma); | |
1419 | ||
98b77773 DT |
1420 | /* Look for errors */ |
1421 | if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { | |
af049081 | 1422 | self->netdev->stats.rx_errors++; |
98b77773 | 1423 | if (lsr & IRCC_LSR_FRAME_ERROR) |
af049081 | 1424 | self->netdev->stats.rx_frame_errors++; |
98b77773 | 1425 | if (lsr & IRCC_LSR_CRC_ERROR) |
af049081 | 1426 | self->netdev->stats.rx_crc_errors++; |
98b77773 | 1427 | if (lsr & IRCC_LSR_SIZE_ERROR) |
af049081 | 1428 | self->netdev->stats.rx_length_errors++; |
98b77773 | 1429 | if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) |
af049081 | 1430 | self->netdev->stats.rx_length_errors++; |
1da177e4 LT |
1431 | return; |
1432 | } | |
98b77773 | 1433 | |
1da177e4 | 1434 | /* Remove CRC */ |
98b77773 | 1435 | len -= self->io.speed < 4000000 ? 2 : 4; |
1da177e4 | 1436 | |
98b77773 | 1437 | if (len < 2 || len > 2050) { |
a97a6f10 | 1438 | IRDA_WARNING("%s(), bogus len=%d\n", __func__, len); |
1da177e4 LT |
1439 | return; |
1440 | } | |
a97a6f10 | 1441 | IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len); |
1da177e4 | 1442 | |
98b77773 DT |
1443 | skb = dev_alloc_skb(len + 1); |
1444 | if (!skb) { | |
1da177e4 | 1445 | IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", |
a97a6f10 | 1446 | __func__); |
1da177e4 | 1447 | return; |
527b6af4 | 1448 | } |
1da177e4 | 1449 | /* Make sure IP header gets aligned */ |
527b6af4 | 1450 | skb_reserve(skb, 1); |
1da177e4 LT |
1451 | |
1452 | memcpy(skb_put(skb, len), self->rx_buff.data, len); | |
af049081 SH |
1453 | self->netdev->stats.rx_packets++; |
1454 | self->netdev->stats.rx_bytes += len; | |
1da177e4 LT |
1455 | |
1456 | skb->dev = self->netdev; | |
459a98ed | 1457 | skb_reset_mac_header(skb); |
1da177e4 LT |
1458 | skb->protocol = htons(ETH_P_IRDA); |
1459 | netif_rx(skb); | |
1460 | } | |
1461 | ||
1462 | /* | |
1463 | * Function smsc_ircc_sir_receive (self) | |
1464 | * | |
1465 | * Receive one frame from the infrared port | |
1466 | * | |
1467 | */ | |
527b6af4 | 1468 | static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) |
1da177e4 LT |
1469 | { |
1470 | int boguscount = 0; | |
1471 | int iobase; | |
1472 | ||
1473 | IRDA_ASSERT(self != NULL, return;); | |
1474 | ||
1475 | iobase = self->io.sir_base; | |
1476 | ||
527b6af4 DT |
1477 | /* |
1478 | * Receive all characters in Rx FIFO, unwrap and unstuff them. | |
1479 | * async_unwrap_char will deliver all found frames | |
1da177e4 LT |
1480 | */ |
1481 | do { | |
af049081 | 1482 | async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff, |
98b77773 | 1483 | inb(iobase + UART_RX)); |
1da177e4 LT |
1484 | |
1485 | /* Make sure we don't stay here to long */ | |
1486 | if (boguscount++ > 32) { | |
a97a6f10 | 1487 | IRDA_DEBUG(2, "%s(), breaking!\n", __func__); |
1da177e4 LT |
1488 | break; |
1489 | } | |
98b77773 | 1490 | } while (inb(iobase + UART_LSR) & UART_LSR_DR); |
1da177e4 LT |
1491 | } |
1492 | ||
1493 | ||
1494 | /* | |
1495 | * Function smsc_ircc_interrupt (irq, dev_id, regs) | |
1496 | * | |
1497 | * An interrupt from the chip has arrived. Time to do some work | |
1498 | * | |
1499 | */ | |
28fc1f5a | 1500 | static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id) |
1da177e4 | 1501 | { |
28fc1f5a JG |
1502 | struct net_device *dev = dev_id; |
1503 | struct smsc_ircc_cb *self = netdev_priv(dev); | |
1da177e4 LT |
1504 | int iobase, iir, lcra, lsr; |
1505 | irqreturn_t ret = IRQ_NONE; | |
1506 | ||
1da177e4 | 1507 | /* Serialise the interrupt handler in various CPUs, stop Tx path */ |
527b6af4 | 1508 | spin_lock(&self->lock); |
1da177e4 LT |
1509 | |
1510 | /* Check if we should use the SIR interrupt handler */ | |
98b77773 | 1511 | if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { |
1da177e4 LT |
1512 | ret = smsc_ircc_interrupt_sir(dev); |
1513 | goto irq_ret_unlock; | |
1514 | } | |
1515 | ||
1516 | iobase = self->io.fir_base; | |
1517 | ||
1518 | register_bank(iobase, 0); | |
98b77773 | 1519 | iir = inb(iobase + IRCC_IIR); |
527b6af4 | 1520 | if (iir == 0) |
1da177e4 LT |
1521 | goto irq_ret_unlock; |
1522 | ret = IRQ_HANDLED; | |
1523 | ||
1524 | /* Disable interrupts */ | |
98b77773 DT |
1525 | outb(0, iobase + IRCC_IER); |
1526 | lcra = inb(iobase + IRCC_LCR_A); | |
1527 | lsr = inb(iobase + IRCC_LSR); | |
527b6af4 | 1528 | |
a97a6f10 | 1529 | IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir); |
1da177e4 LT |
1530 | |
1531 | if (iir & IRCC_IIR_EOM) { | |
1532 | if (self->io.direction == IO_RECV) | |
80a90589 | 1533 | smsc_ircc_dma_receive_complete(self); |
1da177e4 | 1534 | else |
80a90589 | 1535 | smsc_ircc_dma_xmit_complete(self); |
527b6af4 | 1536 | |
80a90589 | 1537 | smsc_ircc_dma_receive(self); |
1da177e4 LT |
1538 | } |
1539 | ||
1540 | if (iir & IRCC_IIR_ACTIVE_FRAME) { | |
a97a6f10 | 1541 | /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/ |
1da177e4 LT |
1542 | } |
1543 | ||
1544 | /* Enable interrupts again */ | |
1545 | ||
1546 | register_bank(iobase, 0); | |
98b77773 | 1547 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1da177e4 LT |
1548 | |
1549 | irq_ret_unlock: | |
1550 | spin_unlock(&self->lock); | |
28fc1f5a | 1551 | |
1da177e4 LT |
1552 | return ret; |
1553 | } | |
1554 | ||
1555 | /* | |
7d12e780 | 1556 | * Function irport_interrupt_sir (irq, dev_id) |
1da177e4 LT |
1557 | * |
1558 | * Interrupt handler for SIR modes | |
1559 | */ | |
1560 | static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) | |
1561 | { | |
da0841a0 | 1562 | struct smsc_ircc_cb *self = netdev_priv(dev); |
1da177e4 LT |
1563 | int boguscount = 0; |
1564 | int iobase; | |
1565 | int iir, lsr; | |
1566 | ||
1567 | /* Already locked comming here in smsc_ircc_interrupt() */ | |
1568 | /*spin_lock(&self->lock);*/ | |
1569 | ||
1570 | iobase = self->io.sir_base; | |
1571 | ||
98b77773 | 1572 | iir = inb(iobase + UART_IIR) & UART_IIR_ID; |
1da177e4 LT |
1573 | if (iir == 0) |
1574 | return IRQ_NONE; | |
1575 | while (iir) { | |
1576 | /* Clear interrupt */ | |
98b77773 | 1577 | lsr = inb(iobase + UART_LSR); |
1da177e4 | 1578 | |
527b6af4 | 1579 | IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", |
a97a6f10 | 1580 | __func__, iir, lsr, iobase); |
1da177e4 LT |
1581 | |
1582 | switch (iir) { | |
1583 | case UART_IIR_RLSI: | |
a97a6f10 | 1584 | IRDA_DEBUG(2, "%s(), RLSI\n", __func__); |
1da177e4 LT |
1585 | break; |
1586 | case UART_IIR_RDI: | |
1587 | /* Receive interrupt */ | |
1588 | smsc_ircc_sir_receive(self); | |
1589 | break; | |
1590 | case UART_IIR_THRI: | |
1591 | if (lsr & UART_LSR_THRE) | |
1592 | /* Transmitter ready for data */ | |
1593 | smsc_ircc_sir_write_wakeup(self); | |
1594 | break; | |
1595 | default: | |
1596 | IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n", | |
a97a6f10 | 1597 | __func__, iir); |
1da177e4 | 1598 | break; |
527b6af4 DT |
1599 | } |
1600 | ||
1da177e4 LT |
1601 | /* Make sure we don't stay here to long */ |
1602 | if (boguscount++ > 100) | |
1603 | break; | |
1604 | ||
527b6af4 | 1605 | iir = inb(iobase + UART_IIR) & UART_IIR_ID; |
1da177e4 LT |
1606 | } |
1607 | /*spin_unlock(&self->lock);*/ | |
1608 | return IRQ_HANDLED; | |
1609 | } | |
1610 | ||
1611 | ||
1612 | #if 0 /* unused */ | |
1613 | /* | |
1614 | * Function ircc_is_receiving (self) | |
1615 | * | |
1616 | * Return TRUE is we are currently receiving a frame | |
1617 | * | |
1618 | */ | |
1619 | static int ircc_is_receiving(struct smsc_ircc_cb *self) | |
1620 | { | |
1621 | int status = FALSE; | |
1622 | /* int iobase; */ | |
1623 | ||
a97a6f10 | 1624 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
1625 | |
1626 | IRDA_ASSERT(self != NULL, return FALSE;); | |
1627 | ||
a97a6f10 | 1628 | IRDA_DEBUG(0, "%s: dma count = %d\n", __func__, |
1da177e4 LT |
1629 | get_dma_residue(self->io.dma)); |
1630 | ||
1631 | status = (self->rx_buff.state != OUTSIDE_FRAME); | |
527b6af4 | 1632 | |
1da177e4 LT |
1633 | return status; |
1634 | } | |
1635 | #endif /* unused */ | |
1636 | ||
e812cb52 DT |
1637 | static int smsc_ircc_request_irq(struct smsc_ircc_cb *self) |
1638 | { | |
1639 | int error; | |
1640 | ||
1641 | error = request_irq(self->io.irq, smsc_ircc_interrupt, 0, | |
1642 | self->netdev->name, self->netdev); | |
1643 | if (error) | |
1644 | IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n", | |
a97a6f10 | 1645 | __func__, self->io.irq, error); |
e812cb52 DT |
1646 | |
1647 | return error; | |
1648 | } | |
1649 | ||
1650 | static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self) | |
1651 | { | |
1652 | unsigned long flags; | |
1653 | ||
1654 | spin_lock_irqsave(&self->lock, flags); | |
1655 | ||
1656 | self->io.speed = 0; | |
1657 | smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); | |
1658 | ||
1659 | spin_unlock_irqrestore(&self->lock, flags); | |
1660 | } | |
1661 | ||
1662 | static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self) | |
1663 | { | |
1664 | int iobase = self->io.fir_base; | |
1665 | unsigned long flags; | |
1666 | ||
1667 | spin_lock_irqsave(&self->lock, flags); | |
1668 | ||
1669 | register_bank(iobase, 0); | |
1670 | outb(0, iobase + IRCC_IER); | |
1671 | outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); | |
1672 | outb(0x00, iobase + IRCC_MASTER); | |
1673 | ||
1674 | spin_unlock_irqrestore(&self->lock, flags); | |
1675 | } | |
1676 | ||
1da177e4 LT |
1677 | |
1678 | /* | |
1679 | * Function smsc_ircc_net_open (dev) | |
1680 | * | |
1681 | * Start the device | |
1682 | * | |
1683 | */ | |
1684 | static int smsc_ircc_net_open(struct net_device *dev) | |
1685 | { | |
1686 | struct smsc_ircc_cb *self; | |
1da177e4 | 1687 | char hwname[16]; |
1da177e4 | 1688 | |
a97a6f10 | 1689 | IRDA_DEBUG(1, "%s\n", __func__); |
527b6af4 | 1690 | |
1da177e4 | 1691 | IRDA_ASSERT(dev != NULL, return -1;); |
da0841a0 | 1692 | self = netdev_priv(dev); |
1da177e4 | 1693 | IRDA_ASSERT(self != NULL, return 0;); |
527b6af4 | 1694 | |
e812cb52 | 1695 | if (self->io.suspended) { |
a97a6f10 | 1696 | IRDA_DEBUG(0, "%s(), device is suspended\n", __func__); |
e812cb52 DT |
1697 | return -EAGAIN; |
1698 | } | |
1699 | ||
527b6af4 | 1700 | if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name, |
1da177e4 LT |
1701 | (void *) dev)) { |
1702 | IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n", | |
a97a6f10 | 1703 | __func__, self->io.irq); |
1da177e4 LT |
1704 | return -EAGAIN; |
1705 | } | |
1706 | ||
e812cb52 | 1707 | smsc_ircc_start_interrupts(self); |
527b6af4 | 1708 | |
1da177e4 LT |
1709 | /* Give self a hardware name */ |
1710 | /* It would be cool to offer the chip revision here - Jean II */ | |
1711 | sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base); | |
1712 | ||
527b6af4 | 1713 | /* |
1da177e4 | 1714 | * Open new IrLAP layer instance, now that everything should be |
527b6af4 | 1715 | * initialized properly |
1da177e4 LT |
1716 | */ |
1717 | self->irlap = irlap_open(dev, &self->qos, hwname); | |
1718 | ||
1719 | /* | |
1720 | * Always allocate the DMA channel after the IRQ, | |
1721 | * and clean up on failure. | |
1722 | */ | |
1723 | if (request_dma(self->io.dma, dev->name)) { | |
1724 | smsc_ircc_net_close(dev); | |
1725 | ||
1726 | IRDA_WARNING("%s(), unable to allocate DMA=%d\n", | |
a97a6f10 | 1727 | __func__, self->io.dma); |
1da177e4 LT |
1728 | return -EAGAIN; |
1729 | } | |
527b6af4 | 1730 | |
1da177e4 LT |
1731 | netif_start_queue(dev); |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | /* | |
1737 | * Function smsc_ircc_net_close (dev) | |
1738 | * | |
1739 | * Stop the device | |
1740 | * | |
1741 | */ | |
1742 | static int smsc_ircc_net_close(struct net_device *dev) | |
1743 | { | |
1744 | struct smsc_ircc_cb *self; | |
1da177e4 | 1745 | |
a97a6f10 | 1746 | IRDA_DEBUG(1, "%s\n", __func__); |
527b6af4 | 1747 | |
1da177e4 | 1748 | IRDA_ASSERT(dev != NULL, return -1;); |
da0841a0 | 1749 | self = netdev_priv(dev); |
1da177e4 | 1750 | IRDA_ASSERT(self != NULL, return 0;); |
527b6af4 | 1751 | |
1da177e4 LT |
1752 | /* Stop device */ |
1753 | netif_stop_queue(dev); | |
527b6af4 | 1754 | |
1da177e4 LT |
1755 | /* Stop and remove instance of IrLAP */ |
1756 | if (self->irlap) | |
1757 | irlap_close(self->irlap); | |
1758 | self->irlap = NULL; | |
1759 | ||
e812cb52 DT |
1760 | smsc_ircc_stop_interrupts(self); |
1761 | ||
1762 | /* if we are called from smsc_ircc_resume we don't have IRQ reserved */ | |
1763 | if (!self->io.suspended) | |
1764 | free_irq(self->io.irq, dev); | |
1765 | ||
1da177e4 | 1766 | disable_dma(self->io.dma); |
1da177e4 LT |
1767 | free_dma(self->io.dma); |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
3ae5eaec | 1772 | static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1773 | { |
3ae5eaec | 1774 | struct smsc_ircc_cb *self = platform_get_drvdata(dev); |
6bb3b2cd | 1775 | |
9480e307 | 1776 | if (!self->io.suspended) { |
e812cb52 DT |
1777 | IRDA_DEBUG(1, "%s, Suspending\n", driver_name); |
1778 | ||
1779 | rtnl_lock(); | |
1780 | if (netif_running(self->netdev)) { | |
1781 | netif_device_detach(self->netdev); | |
1782 | smsc_ircc_stop_interrupts(self); | |
1783 | free_irq(self->io.irq, self->netdev); | |
1784 | disable_dma(self->io.dma); | |
1785 | } | |
98b77773 | 1786 | self->io.suspended = 1; |
e812cb52 | 1787 | rtnl_unlock(); |
98b77773 | 1788 | } |
6bb3b2cd DT |
1789 | |
1790 | return 0; | |
1da177e4 LT |
1791 | } |
1792 | ||
3ae5eaec | 1793 | static int smsc_ircc_resume(struct platform_device *dev) |
1da177e4 | 1794 | { |
3ae5eaec | 1795 | struct smsc_ircc_cb *self = platform_get_drvdata(dev); |
1da177e4 | 1796 | |
9480e307 | 1797 | if (self->io.suspended) { |
e812cb52 DT |
1798 | IRDA_DEBUG(1, "%s, Waking up\n", driver_name); |
1799 | ||
1800 | rtnl_lock(); | |
1801 | smsc_ircc_init_chip(self); | |
1802 | if (netif_running(self->netdev)) { | |
1803 | if (smsc_ircc_request_irq(self)) { | |
1804 | /* | |
1805 | * Don't fail resume process, just kill this | |
1806 | * network interface | |
1807 | */ | |
1808 | unregister_netdevice(self->netdev); | |
1809 | } else { | |
1810 | enable_dma(self->io.dma); | |
1811 | smsc_ircc_start_interrupts(self); | |
1812 | netif_device_attach(self->netdev); | |
1813 | } | |
1814 | } | |
6bb3b2cd | 1815 | self->io.suspended = 0; |
e812cb52 | 1816 | rtnl_unlock(); |
6bb3b2cd | 1817 | } |
1da177e4 LT |
1818 | return 0; |
1819 | } | |
1820 | ||
1821 | /* | |
1822 | * Function smsc_ircc_close (self) | |
1823 | * | |
1824 | * Close driver instance | |
1825 | * | |
1826 | */ | |
1827 | static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) | |
1828 | { | |
a97a6f10 | 1829 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
1830 | |
1831 | IRDA_ASSERT(self != NULL, return -1;); | |
1832 | ||
6bb3b2cd | 1833 | platform_device_unregister(self->pldev); |
1da177e4 LT |
1834 | |
1835 | /* Remove netdevice */ | |
1836 | unregister_netdev(self->netdev); | |
1837 | ||
e812cb52 | 1838 | smsc_ircc_stop_interrupts(self); |
1da177e4 LT |
1839 | |
1840 | /* Release the PORTS that this driver is using */ | |
a97a6f10 | 1841 | IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__, |
1da177e4 LT |
1842 | self->io.fir_base); |
1843 | ||
1844 | release_region(self->io.fir_base, self->io.fir_ext); | |
1845 | ||
a97a6f10 | 1846 | IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__, |
1da177e4 LT |
1847 | self->io.sir_base); |
1848 | ||
1849 | release_region(self->io.sir_base, self->io.sir_ext); | |
1850 | ||
1851 | if (self->tx_buff.head) | |
1852 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
1853 | self->tx_buff.head, self->tx_buff_dma); | |
527b6af4 | 1854 | |
1da177e4 LT |
1855 | if (self->rx_buff.head) |
1856 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
1857 | self->rx_buff.head, self->rx_buff_dma); | |
1858 | ||
1859 | free_netdev(self->netdev); | |
1860 | ||
1861 | return 0; | |
1862 | } | |
1863 | ||
1864 | static void __exit smsc_ircc_cleanup(void) | |
1865 | { | |
1866 | int i; | |
1867 | ||
a97a6f10 | 1868 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 | 1869 | |
98b77773 | 1870 | for (i = 0; i < 2; i++) { |
1da177e4 LT |
1871 | if (dev_self[i]) |
1872 | smsc_ircc_close(dev_self[i]); | |
1873 | } | |
6bb3b2cd | 1874 | |
d0d4f69b BH |
1875 | if (pnp_driver_registered) |
1876 | pnp_unregister_driver(&smsc_ircc_pnp_driver); | |
1877 | ||
3ae5eaec | 1878 | platform_driver_unregister(&smsc_ircc_driver); |
1da177e4 LT |
1879 | } |
1880 | ||
1881 | /* | |
1882 | * Start SIR operations | |
1883 | * | |
1884 | * This function *must* be called with spinlock held, because it may | |
1885 | * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II | |
1886 | */ | |
0e49e645 | 1887 | static void smsc_ircc_sir_start(struct smsc_ircc_cb *self) |
1da177e4 LT |
1888 | { |
1889 | struct net_device *dev; | |
1890 | int fir_base, sir_base; | |
1891 | ||
a97a6f10 | 1892 | IRDA_DEBUG(3, "%s\n", __func__); |
1da177e4 | 1893 | |
527b6af4 | 1894 | IRDA_ASSERT(self != NULL, return;); |
98b77773 | 1895 | dev = self->netdev; |
527b6af4 | 1896 | IRDA_ASSERT(dev != NULL, return;); |
1da177e4 LT |
1897 | dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir; |
1898 | ||
1899 | fir_base = self->io.fir_base; | |
1900 | sir_base = self->io.sir_base; | |
1901 | ||
1902 | /* Reset everything */ | |
98b77773 | 1903 | outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); |
1da177e4 LT |
1904 | |
1905 | #if SMSC_IRCC2_C_SIR_STOP | |
1906 | /*smsc_ircc_sir_stop(self);*/ | |
1907 | #endif | |
1908 | ||
1909 | register_bank(fir_base, 1); | |
98b77773 | 1910 | outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); |
1da177e4 LT |
1911 | |
1912 | /* Initialize UART */ | |
98b77773 DT |
1913 | outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ |
1914 | outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); | |
527b6af4 | 1915 | |
1da177e4 | 1916 | /* Turn on interrups */ |
98b77773 | 1917 | outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); |
1da177e4 | 1918 | |
a97a6f10 | 1919 | IRDA_DEBUG(3, "%s() - exit\n", __func__); |
1da177e4 | 1920 | |
98b77773 | 1921 | outb(0x00, fir_base + IRCC_MASTER); |
1da177e4 LT |
1922 | } |
1923 | ||
1924 | #if SMSC_IRCC2_C_SIR_STOP | |
1925 | void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) | |
1926 | { | |
1927 | int iobase; | |
1928 | ||
a97a6f10 | 1929 | IRDA_DEBUG(3, "%s\n", __func__); |
1da177e4 LT |
1930 | iobase = self->io.sir_base; |
1931 | ||
1932 | /* Reset UART */ | |
98b77773 | 1933 | outb(0, iobase + UART_MCR); |
527b6af4 | 1934 | |
1da177e4 | 1935 | /* Turn off interrupts */ |
98b77773 | 1936 | outb(0, iobase + UART_IER); |
1da177e4 LT |
1937 | } |
1938 | #endif | |
1939 | ||
1940 | /* | |
1941 | * Function smsc_sir_write_wakeup (self) | |
1942 | * | |
1943 | * Called by the SIR interrupt handler when there's room for more data. | |
1944 | * If we have more packets to send, we send them here. | |
1945 | * | |
1946 | */ | |
1947 | static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) | |
1948 | { | |
1949 | int actual = 0; | |
1950 | int iobase; | |
1951 | int fcr; | |
1952 | ||
1953 | IRDA_ASSERT(self != NULL, return;); | |
1954 | ||
a97a6f10 | 1955 | IRDA_DEBUG(4, "%s\n", __func__); |
1da177e4 LT |
1956 | |
1957 | iobase = self->io.sir_base; | |
1958 | ||
1959 | /* Finished with frame? */ | |
1960 | if (self->tx_buff.len > 0) { | |
1961 | /* Write data left in transmit buffer */ | |
527b6af4 | 1962 | actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, |
1da177e4 LT |
1963 | self->tx_buff.data, self->tx_buff.len); |
1964 | self->tx_buff.data += actual; | |
1965 | self->tx_buff.len -= actual; | |
1966 | } else { | |
527b6af4 | 1967 | |
1da177e4 | 1968 | /*if (self->tx_buff.len ==0) {*/ |
527b6af4 DT |
1969 | |
1970 | /* | |
1971 | * Now serial buffer is almost free & we can start | |
1da177e4 LT |
1972 | * transmission of another packet. But first we must check |
1973 | * if we need to change the speed of the hardware | |
1974 | */ | |
1975 | if (self->new_speed) { | |
1976 | IRDA_DEBUG(5, "%s(), Changing speed to %d.\n", | |
a97a6f10 | 1977 | __func__, self->new_speed); |
1da177e4 LT |
1978 | smsc_ircc_sir_wait_hw_transmitter_finish(self); |
1979 | smsc_ircc_change_speed(self, self->new_speed); | |
1980 | self->new_speed = 0; | |
1981 | } else { | |
1982 | /* Tell network layer that we want more frames */ | |
1983 | netif_wake_queue(self->netdev); | |
1984 | } | |
af049081 | 1985 | self->netdev->stats.tx_packets++; |
1da177e4 | 1986 | |
98b77773 DT |
1987 | if (self->io.speed <= 115200) { |
1988 | /* | |
1989 | * Reset Rx FIFO to make sure that all reflected transmit data | |
1990 | * is discarded. This is needed for half duplex operation | |
1991 | */ | |
1992 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; | |
1993 | fcr |= self->io.speed < 38400 ? | |
1994 | UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; | |
1da177e4 | 1995 | |
98b77773 | 1996 | outb(fcr, iobase + UART_FCR); |
1da177e4 | 1997 | |
98b77773 DT |
1998 | /* Turn on receive interrupts */ |
1999 | outb(UART_IER_RDI, iobase + UART_IER); | |
1da177e4 LT |
2000 | } |
2001 | } | |
2002 | } | |
2003 | ||
2004 | /* | |
2005 | * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len) | |
2006 | * | |
2007 | * Fill Tx FIFO with transmit data | |
2008 | * | |
2009 | */ | |
2010 | static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) | |
2011 | { | |
2012 | int actual = 0; | |
527b6af4 | 2013 | |
1da177e4 | 2014 | /* Tx FIFO should be empty! */ |
98b77773 | 2015 | if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { |
a97a6f10 | 2016 | IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__); |
1da177e4 LT |
2017 | return 0; |
2018 | } | |
527b6af4 | 2019 | |
1da177e4 | 2020 | /* Fill FIFO with current frame */ |
98b77773 | 2021 | while (fifo_size-- > 0 && actual < len) { |
1da177e4 | 2022 | /* Transmit next byte */ |
98b77773 | 2023 | outb(buf[actual], iobase + UART_TX); |
1da177e4 LT |
2024 | actual++; |
2025 | } | |
2026 | return actual; | |
2027 | } | |
2028 | ||
2029 | /* | |
2030 | * Function smsc_ircc_is_receiving (self) | |
2031 | * | |
2032 | * Returns true is we are currently receiving data | |
2033 | * | |
2034 | */ | |
2035 | static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self) | |
2036 | { | |
2037 | return (self->rx_buff.state != OUTSIDE_FRAME); | |
2038 | } | |
2039 | ||
2040 | ||
2041 | /* | |
2042 | * Function smsc_ircc_probe_transceiver(self) | |
2043 | * | |
2044 | * Tries to find the used Transceiver | |
2045 | * | |
2046 | */ | |
2047 | static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) | |
2048 | { | |
2049 | unsigned int i; | |
527b6af4 | 2050 | |
1da177e4 | 2051 | IRDA_ASSERT(self != NULL, return;); |
527b6af4 | 2052 | |
98b77773 DT |
2053 | for (i = 0; smsc_transceivers[i].name != NULL; i++) |
2054 | if (smsc_transceivers[i].probe(self->io.fir_base)) { | |
1da177e4 LT |
2055 | IRDA_MESSAGE(" %s transceiver found\n", |
2056 | smsc_transceivers[i].name); | |
98b77773 | 2057 | self->transceiver= i + 1; |
1da177e4 LT |
2058 | return; |
2059 | } | |
98b77773 | 2060 | |
1da177e4 LT |
2061 | IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", |
2062 | smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); | |
527b6af4 | 2063 | |
98b77773 | 2064 | self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; |
1da177e4 LT |
2065 | } |
2066 | ||
2067 | ||
2068 | /* | |
2069 | * Function smsc_ircc_set_transceiver_for_speed(self, speed) | |
2070 | * | |
2071 | * Set the transceiver according to the speed | |
2072 | * | |
2073 | */ | |
2074 | static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed) | |
2075 | { | |
2076 | unsigned int trx; | |
527b6af4 | 2077 | |
1da177e4 | 2078 | trx = self->transceiver; |
98b77773 DT |
2079 | if (trx > 0) |
2080 | smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); | |
1da177e4 LT |
2081 | } |
2082 | ||
2083 | /* | |
2084 | * Function smsc_ircc_wait_hw_transmitter_finish () | |
2085 | * | |
2086 | * Wait for the real end of HW transmission | |
2087 | * | |
2088 | * The UART is a strict FIFO, and we get called only when we have finished | |
2089 | * pushing data to the FIFO, so the maximum amount of time we must wait | |
2090 | * is only for the FIFO to drain out. | |
2091 | * | |
2092 | * We use a simple calibrated loop. We may need to adjust the loop | |
2093 | * delay (udelay) to balance I/O traffic and latency. And we also need to | |
2094 | * adjust the maximum timeout. | |
2095 | * It would probably be better to wait for the proper interrupt, | |
2096 | * but it doesn't seem to be available. | |
2097 | * | |
2098 | * We can't use jiffies or kernel timers because : | |
2099 | * 1) We are called from the interrupt handler, which disable softirqs, | |
2100 | * so jiffies won't be increased | |
2101 | * 2) Jiffies granularity is usually very coarse (10ms), and we don't | |
2102 | * want to wait that long to detect stuck hardware. | |
2103 | * Jean II | |
2104 | */ | |
2105 | ||
2106 | static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) | |
2107 | { | |
98b77773 | 2108 | int iobase = self->io.sir_base; |
1da177e4 | 2109 | int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; |
527b6af4 | 2110 | |
1da177e4 | 2111 | /* Calibrated busy loop */ |
98b77773 | 2112 | while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) |
1da177e4 LT |
2113 | udelay(1); |
2114 | ||
98b77773 | 2115 | if (count == 0) |
a97a6f10 | 2116 | IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__); |
1da177e4 LT |
2117 | } |
2118 | ||
2119 | ||
2120 | /* PROBING | |
2121 | * | |
d94c77b9 DB |
2122 | * REVISIT we can be told about the device by PNP, and should use that info |
2123 | * instead of probing hardware and creating a platform_device ... | |
1da177e4 LT |
2124 | */ |
2125 | ||
2126 | static int __init smsc_ircc_look_for_chips(void) | |
2127 | { | |
b6158d23 | 2128 | struct smsc_chip_address *address; |
98b77773 | 2129 | char *type; |
1da177e4 | 2130 | unsigned int cfg_base, found; |
527b6af4 | 2131 | |
1da177e4 LT |
2132 | found = 0; |
2133 | address = possible_addresses; | |
527b6af4 | 2134 | |
98b77773 | 2135 | while (address->cfg_base) { |
1da177e4 | 2136 | cfg_base = address->cfg_base; |
527b6af4 | 2137 | |
a97a6f10 | 2138 | /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/ |
527b6af4 | 2139 | |
98b77773 | 2140 | if (address->type & SMSCSIO_TYPE_FDC) { |
1da177e4 | 2141 | type = "FDC"; |
98b77773 DT |
2142 | if (address->type & SMSCSIO_TYPE_FLAT) |
2143 | if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) | |
2144 | found++; | |
2145 | ||
2146 | if (address->type & SMSCSIO_TYPE_PAGED) | |
2147 | if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) | |
2148 | found++; | |
1da177e4 | 2149 | } |
98b77773 | 2150 | if (address->type & SMSCSIO_TYPE_LPC) { |
1da177e4 | 2151 | type = "LPC"; |
98b77773 DT |
2152 | if (address->type & SMSCSIO_TYPE_FLAT) |
2153 | if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) | |
2154 | found++; | |
2155 | ||
2156 | if (address->type & SMSCSIO_TYPE_PAGED) | |
2157 | if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) | |
2158 | found++; | |
1da177e4 LT |
2159 | } |
2160 | address++; | |
2161 | } | |
2162 | return found; | |
527b6af4 | 2163 | } |
1da177e4 LT |
2164 | |
2165 | /* | |
2166 | * Function smsc_superio_flat (chip, base, type) | |
2167 | * | |
2168 | * Try to get configuration of a smc SuperIO chip with flat register model | |
2169 | * | |
2170 | */ | |
b6158d23 | 2171 | static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type) |
1da177e4 LT |
2172 | { |
2173 | unsigned short firbase, sirbase; | |
2174 | u8 mode, dma, irq; | |
2175 | int ret = -ENODEV; | |
2176 | ||
a97a6f10 | 2177 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 | 2178 | |
98b77773 | 2179 | if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) |
1da177e4 LT |
2180 | return ret; |
2181 | ||
2182 | outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); | |
98b77773 | 2183 | mode = inb(cfgbase + 1); |
527b6af4 | 2184 | |
a97a6f10 | 2185 | /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/ |
527b6af4 | 2186 | |
98b77773 | 2187 | if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) |
a97a6f10 | 2188 | IRDA_WARNING("%s(): IrDA not enabled\n", __func__); |
1da177e4 LT |
2189 | |
2190 | outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); | |
98b77773 | 2191 | sirbase = inb(cfgbase + 1) << 2; |
1da177e4 | 2192 | |
527b6af4 | 2193 | /* FIR iobase */ |
1da177e4 | 2194 | outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); |
98b77773 | 2195 | firbase = inb(cfgbase + 1) << 3; |
1da177e4 LT |
2196 | |
2197 | /* DMA */ | |
2198 | outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); | |
98b77773 | 2199 | dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; |
527b6af4 | 2200 | |
1da177e4 LT |
2201 | /* IRQ */ |
2202 | outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); | |
98b77773 | 2203 | irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; |
1da177e4 | 2204 | |
a97a6f10 | 2205 | IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode); |
1da177e4 | 2206 | |
98b77773 DT |
2207 | if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) |
2208 | ret = 0; | |
527b6af4 | 2209 | |
1da177e4 LT |
2210 | /* Exit configuration */ |
2211 | outb(SMSCSIO_CFGEXITKEY, cfgbase); | |
2212 | ||
2213 | return ret; | |
2214 | } | |
2215 | ||
2216 | /* | |
2217 | * Function smsc_superio_paged (chip, base, type) | |
2218 | * | |
2219 | * Try to get configuration of a smc SuperIO chip with paged register model | |
2220 | * | |
2221 | */ | |
b6158d23 | 2222 | static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type) |
1da177e4 LT |
2223 | { |
2224 | unsigned short fir_io, sir_io; | |
2225 | int ret = -ENODEV; | |
527b6af4 | 2226 | |
a97a6f10 | 2227 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 | 2228 | |
98b77773 | 2229 | if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) |
1da177e4 | 2230 | return ret; |
527b6af4 | 2231 | |
1da177e4 LT |
2232 | /* Select logical device (UART2) */ |
2233 | outb(0x07, cfg_base); | |
2234 | outb(0x05, cfg_base + 1); | |
527b6af4 | 2235 | |
1da177e4 LT |
2236 | /* SIR iobase */ |
2237 | outb(0x60, cfg_base); | |
98b77773 | 2238 | sir_io = inb(cfg_base + 1) << 8; |
1da177e4 LT |
2239 | outb(0x61, cfg_base); |
2240 | sir_io |= inb(cfg_base + 1); | |
527b6af4 | 2241 | |
1da177e4 LT |
2242 | /* Read FIR base */ |
2243 | outb(0x62, cfg_base); | |
2244 | fir_io = inb(cfg_base + 1) << 8; | |
2245 | outb(0x63, cfg_base); | |
2246 | fir_io |= inb(cfg_base + 1); | |
2247 | outb(0x2b, cfg_base); /* ??? */ | |
2248 | ||
98b77773 DT |
2249 | if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) |
2250 | ret = 0; | |
527b6af4 | 2251 | |
1da177e4 LT |
2252 | /* Exit configuration */ |
2253 | outb(SMSCSIO_CFGEXITKEY, cfg_base); | |
2254 | ||
2255 | return ret; | |
2256 | } | |
2257 | ||
2258 | ||
98b77773 | 2259 | static int __init smsc_access(unsigned short cfg_base, unsigned char reg) |
1da177e4 | 2260 | { |
a97a6f10 | 2261 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
2262 | |
2263 | outb(reg, cfg_base); | |
98b77773 | 2264 | return inb(cfg_base) != reg ? -1 : 0; |
1da177e4 LT |
2265 | } |
2266 | ||
b6158d23 | 2267 | static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type) |
1da177e4 | 2268 | { |
98b77773 | 2269 | u8 devid, xdevid, rev; |
1da177e4 | 2270 | |
a97a6f10 | 2271 | IRDA_DEBUG(1, "%s\n", __func__); |
1da177e4 LT |
2272 | |
2273 | /* Leave configuration */ | |
2274 | ||
2275 | outb(SMSCSIO_CFGEXITKEY, cfg_base); | |
2276 | ||
2277 | if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ | |
2278 | return NULL; | |
2279 | ||
2280 | outb(reg, cfg_base); | |
2281 | ||
98b77773 | 2282 | xdevid = inb(cfg_base + 1); |
1da177e4 LT |
2283 | |
2284 | /* Enter configuration */ | |
2285 | ||
2286 | outb(SMSCSIO_CFGACCESSKEY, cfg_base); | |
2287 | ||
2288 | #if 0 | |
2289 | if (smsc_access(cfg_base,0x55)) /* send second key and check */ | |
2290 | return NULL; | |
2291 | #endif | |
527b6af4 | 2292 | |
1da177e4 LT |
2293 | /* probe device ID */ |
2294 | ||
98b77773 | 2295 | if (smsc_access(cfg_base, reg)) |
1da177e4 LT |
2296 | return NULL; |
2297 | ||
98b77773 | 2298 | devid = inb(cfg_base + 1); |
527b6af4 | 2299 | |
98b77773 | 2300 | if (devid == 0 || devid == 0xff) /* typical values for unused port */ |
1da177e4 LT |
2301 | return NULL; |
2302 | ||
2303 | /* probe revision ID */ | |
2304 | ||
98b77773 | 2305 | if (smsc_access(cfg_base, reg + 1)) |
1da177e4 LT |
2306 | return NULL; |
2307 | ||
98b77773 | 2308 | rev = inb(cfg_base + 1); |
1da177e4 | 2309 | |
98b77773 | 2310 | if (rev >= 128) /* i think this will make no sense */ |
1da177e4 LT |
2311 | return NULL; |
2312 | ||
98b77773 | 2313 | if (devid == xdevid) /* protection against false positives */ |
1da177e4 LT |
2314 | return NULL; |
2315 | ||
2316 | /* Check for expected device ID; are there others? */ | |
2317 | ||
98b77773 | 2318 | while (chip->devid != devid) { |
1da177e4 LT |
2319 | |
2320 | chip++; | |
2321 | ||
98b77773 | 2322 | if (chip->name == NULL) |
1da177e4 LT |
2323 | return NULL; |
2324 | } | |
2325 | ||
98b77773 DT |
2326 | IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", |
2327 | devid, rev, cfg_base, type, chip->name); | |
1da177e4 | 2328 | |
98b77773 | 2329 | if (chip->rev > rev) { |
527b6af4 | 2330 | IRDA_MESSAGE("Revision higher than expected\n"); |
1da177e4 LT |
2331 | return NULL; |
2332 | } | |
527b6af4 | 2333 | |
98b77773 | 2334 | if (chip->flags & NoIRDA) |
1da177e4 LT |
2335 | IRDA_MESSAGE("chipset does not support IRDA\n"); |
2336 | ||
2337 | return chip; | |
2338 | } | |
2339 | ||
2340 | static int __init smsc_superio_fdc(unsigned short cfg_base) | |
2341 | { | |
2342 | int ret = -1; | |
2343 | ||
2344 | if (!request_region(cfg_base, 2, driver_name)) { | |
2345 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", | |
a97a6f10 | 2346 | __func__, cfg_base); |
1da177e4 | 2347 | } else { |
98b77773 DT |
2348 | if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || |
2349 | !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) | |
1da177e4 LT |
2350 | ret = 0; |
2351 | ||
2352 | release_region(cfg_base, 2); | |
2353 | } | |
2354 | ||
2355 | return ret; | |
2356 | } | |
2357 | ||
2358 | static int __init smsc_superio_lpc(unsigned short cfg_base) | |
2359 | { | |
2360 | int ret = -1; | |
2361 | ||
2362 | if (!request_region(cfg_base, 2, driver_name)) { | |
2363 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", | |
a97a6f10 | 2364 | __func__, cfg_base); |
1da177e4 | 2365 | } else { |
98b77773 DT |
2366 | if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || |
2367 | !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) | |
1da177e4 | 2368 | ret = 0; |
98b77773 | 2369 | |
1da177e4 LT |
2370 | release_region(cfg_base, 2); |
2371 | } | |
2372 | return ret; | |
2373 | } | |
2374 | ||
c1e14a6e LW |
2375 | /* |
2376 | * Look for some specific subsystem setups that need | |
2377 | * pre-configuration not properly done by the BIOS (especially laptops) | |
2378 | * This code is based in part on smcinit.c, tosh1800-smcinit.c | |
2379 | * and tosh2450-smcinit.c. The table lists the device entries | |
08d09997 LW |
2380 | * for ISA bridges with an LPC (Low Pin Count) controller which |
2381 | * handles the communication with the SMSC device. After the LPC | |
2382 | * controller is initialized through PCI, the SMSC device is initialized | |
2383 | * through a dedicated port in the ISA port-mapped I/O area, this latter | |
2384 | * area is used to configure the SMSC device with default | |
2385 | * SIR and FIR I/O ports, DMA and IRQ. Different vendors have | |
2386 | * used different sets of parameters and different control port | |
2387 | * addresses making a subsystem device table necessary. | |
c1e14a6e LW |
2388 | */ |
2389 | #ifdef CONFIG_PCI | |
2390 | #define PCIID_VENDOR_INTEL 0x8086 | |
2391 | #define PCIID_VENDOR_ALI 0x10b9 | |
c5d965ca | 2392 | static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { |
895de090 LWLE |
2393 | /* |
2394 | * Subsystems needing entries: | |
2395 | * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family | |
2396 | * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family | |
2397 | * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family | |
2398 | */ | |
2399 | { | |
2400 | /* Guessed entry */ | |
2401 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2402 | .device = 0x24cc, | |
2403 | .subvendor = 0x103c, | |
2404 | .subdevice = 0x08bc, | |
2405 | .sir_io = 0x02f8, | |
2406 | .fir_io = 0x0130, | |
2407 | .fir_irq = 0x05, | |
2408 | .fir_dma = 0x03, | |
2409 | .cfg_base = 0x004e, | |
2410 | .preconfigure = preconfigure_through_82801, | |
2411 | .name = "HP nx5000 family", | |
2412 | }, | |
c1e14a6e LW |
2413 | { |
2414 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2415 | .device = 0x24cc, | |
2416 | .subvendor = 0x103c, | |
2417 | .subdevice = 0x088c, | |
08d09997 LW |
2418 | /* Quite certain these are the same for nc8000 as for nc6000 */ |
2419 | .sir_io = 0x02f8, | |
c1e14a6e | 2420 | .fir_io = 0x0130, |
08d09997 | 2421 | .fir_irq = 0x05, |
c1e14a6e LW |
2422 | .fir_dma = 0x03, |
2423 | .cfg_base = 0x004e, | |
2424 | .preconfigure = preconfigure_through_82801, | |
895de090 | 2425 | .name = "HP nc8000 family", |
c1e14a6e LW |
2426 | }, |
2427 | { | |
2428 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2429 | .device = 0x24cc, | |
2430 | .subvendor = 0x103c, | |
2431 | .subdevice = 0x0890, | |
2432 | .sir_io = 0x02f8, | |
2433 | .fir_io = 0x0130, | |
08d09997 | 2434 | .fir_irq = 0x05, |
c1e14a6e LW |
2435 | .fir_dma = 0x03, |
2436 | .cfg_base = 0x004e, | |
2437 | .preconfigure = preconfigure_through_82801, | |
895de090 LWLE |
2438 | .name = "HP nc6000 family", |
2439 | }, | |
2440 | { | |
2441 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2442 | .device = 0x24cc, | |
2443 | .subvendor = 0x0e11, | |
2444 | .subdevice = 0x0860, | |
2445 | /* I assume these are the same for x1000 as for the others */ | |
2446 | .sir_io = 0x02e8, | |
2447 | .fir_io = 0x02f8, | |
2448 | .fir_irq = 0x07, | |
2449 | .fir_dma = 0x03, | |
2450 | .cfg_base = 0x002e, | |
2451 | .preconfigure = preconfigure_through_82801, | |
2452 | .name = "Compaq x1000 family", | |
c1e14a6e LW |
2453 | }, |
2454 | { | |
08d09997 LW |
2455 | /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ |
2456 | .vendor = PCIID_VENDOR_INTEL, | |
c1e14a6e LW |
2457 | .device = 0x24c0, |
2458 | .subvendor = 0x1179, | |
08d09997 | 2459 | .subdevice = 0xffff, /* 0xffff is "any" */ |
c1e14a6e LW |
2460 | .sir_io = 0x03f8, |
2461 | .fir_io = 0x0130, | |
2462 | .fir_irq = 0x07, | |
2463 | .fir_dma = 0x01, | |
2464 | .cfg_base = 0x002e, | |
2465 | .preconfigure = preconfigure_through_82801, | |
08d09997 | 2466 | .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", |
c1e14a6e LW |
2467 | }, |
2468 | { | |
2469 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */ | |
08d09997 | 2470 | .device = 0x248c, |
c1e14a6e | 2471 | .subvendor = 0x1179, |
08d09997 | 2472 | .subdevice = 0xffff, /* 0xffff is "any" */ |
c1e14a6e LW |
2473 | .sir_io = 0x03f8, |
2474 | .fir_io = 0x0130, | |
2475 | .fir_irq = 0x03, | |
2476 | .fir_dma = 0x03, | |
2477 | .cfg_base = 0x002e, | |
2478 | .preconfigure = preconfigure_through_82801, | |
08d09997 | 2479 | .name = "Toshiba laptop with Intel 82801CAM ISA bridge", |
c1e14a6e LW |
2480 | }, |
2481 | { | |
08d09997 LW |
2482 | /* 82801DBM (ICH4-M) LPC Interface Bridge */ |
2483 | .vendor = PCIID_VENDOR_INTEL, | |
2484 | .device = 0x24cc, | |
2485 | .subvendor = 0x1179, | |
2486 | .subdevice = 0xffff, /* 0xffff is "any" */ | |
2487 | .sir_io = 0x03f8, | |
2488 | .fir_io = 0x0130, | |
2489 | .fir_irq = 0x03, | |
2490 | .fir_dma = 0x03, | |
2491 | .cfg_base = 0x002e, | |
2492 | .preconfigure = preconfigure_through_82801, | |
2493 | .name = "Toshiba laptop with Intel 8281DBM LPC bridge", | |
2494 | }, | |
2495 | { | |
2496 | /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ | |
2497 | .vendor = PCIID_VENDOR_ALI, | |
c1e14a6e LW |
2498 | .device = 0x1533, |
2499 | .subvendor = 0x1179, | |
08d09997 | 2500 | .subdevice = 0xffff, /* 0xffff is "any" */ |
c1e14a6e LW |
2501 | .sir_io = 0x02e8, |
2502 | .fir_io = 0x02f8, | |
2503 | .fir_irq = 0x07, | |
2504 | .fir_dma = 0x03, | |
2505 | .cfg_base = 0x002e, | |
2506 | .preconfigure = preconfigure_through_ali, | |
08d09997 | 2507 | .name = "Toshiba laptop with ALi ISA bridge", |
c1e14a6e LW |
2508 | }, |
2509 | { } // Terminator | |
2510 | }; | |
2511 | ||
2512 | ||
2513 | /* | |
08d09997 LW |
2514 | * This sets up the basic SMSC parameters |
2515 | * (FIR port, SIR port, FIR DMA, FIR IRQ) | |
c1e14a6e LW |
2516 | * through the chip configuration port. |
2517 | */ | |
08d09997 LW |
2518 | static int __init preconfigure_smsc_chip(struct |
2519 | smsc_ircc_subsystem_configuration | |
2520 | *conf) | |
c1e14a6e LW |
2521 | { |
2522 | unsigned short iobase = conf->cfg_base; | |
2523 | unsigned char tmpbyte; | |
2524 | ||
2525 | outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state | |
2526 | outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID | |
2527 | tmpbyte = inb(iobase +1); // Read device ID | |
08d09997 LW |
2528 | IRDA_DEBUG(0, |
2529 | "Detected Chip id: 0x%02x, setting up registers...\n", | |
2530 | tmpbyte); | |
c1e14a6e LW |
2531 | |
2532 | /* Disable UART1 and set up SIR I/O port */ | |
2533 | outb(0x24, iobase); // select CR24 - UART1 base addr | |
2534 | outb(0x00, iobase + 1); // disable UART1 | |
2535 | outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr | |
2536 | outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 | |
2537 | tmpbyte = inb(iobase + 1); | |
2538 | if (tmpbyte != (conf->sir_io >> 2) ) { | |
2539 | IRDA_WARNING("ERROR: could not configure SIR ioport.\n"); | |
08d09997 | 2540 | IRDA_WARNING("Try to supply ircc_cfg argument.\n"); |
c1e14a6e LW |
2541 | return -ENXIO; |
2542 | } | |
2543 | ||
2544 | /* Set up FIR IRQ channel for UART2 */ | |
2545 | outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select | |
2546 | tmpbyte = inb(iobase + 1); | |
2547 | tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion | |
2548 | tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK); | |
2549 | outb(tmpbyte, iobase + 1); | |
2550 | tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; | |
2551 | if (tmpbyte != conf->fir_irq) { | |
2552 | IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n"); | |
2553 | return -ENXIO; | |
2554 | } | |
2555 | ||
2556 | /* Set up FIR I/O port */ | |
2557 | outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr | |
2558 | outb((conf->fir_io >> 3), iobase + 1); | |
2559 | tmpbyte = inb(iobase + 1); | |
2560 | if (tmpbyte != (conf->fir_io >> 3) ) { | |
2561 | IRDA_WARNING("ERROR: could not configure FIR I/O port.\n"); | |
2562 | return -ENXIO; | |
2563 | } | |
2564 | ||
2565 | /* Set up FIR DMA channel */ | |
2566 | outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select | |
2567 | outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA | |
2568 | tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; | |
2569 | if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) { | |
2570 | IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n"); | |
2571 | return -ENXIO; | |
2572 | } | |
2573 | ||
2574 | outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode | |
2575 | tmpbyte = inb(iobase + 1); | |
08d09997 LW |
2576 | tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | |
2577 | SMSCSIOFLAT_UART2MODE_VAL_IRDA; | |
c1e14a6e LW |
2578 | outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed |
2579 | ||
2580 | outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel | |
2581 | tmpbyte = inb(iobase + 1); | |
2582 | outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down | |
2583 | ||
2584 | /* This one was not part of tosh1800 */ | |
2585 | outb(0x0a, iobase); // CR0a - ecp fifo / ir mux | |
2586 | tmpbyte = inb(iobase + 1); | |
2587 | outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port | |
2588 | ||
2589 | outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power | |
2590 | tmpbyte = inb(iobase + 1); | |
2591 | outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down | |
2592 | ||
2593 | outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle | |
2594 | tmpbyte = inb(iobase + 1); | |
2595 | outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done | |
2596 | ||
2597 | outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration | |
2598 | ||
2599 | return 0; | |
2600 | } | |
2601 | ||
08d09997 | 2602 | /* 82801CAM generic registers */ |
c1e14a6e LW |
2603 | #define VID 0x00 |
2604 | #define DID 0x02 | |
08d09997 LW |
2605 | #define PIRQ_A_D_ROUT 0x60 |
2606 | #define SIRQ_CNTL 0x64 | |
2607 | #define PIRQ_E_H_ROUT 0x68 | |
c1e14a6e | 2608 | #define PCI_DMA_C 0x90 |
08d09997 | 2609 | /* LPC-specific registers */ |
c1e14a6e | 2610 | #define COM_DEC 0xe0 |
08d09997 | 2611 | #define GEN1_DEC 0xe4 |
c1e14a6e LW |
2612 | #define LPC_EN 0xe6 |
2613 | #define GEN2_DEC 0xec | |
2614 | /* | |
08d09997 LW |
2615 | * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge |
2616 | * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. | |
2617 | * They all work the same way! | |
c1e14a6e LW |
2618 | */ |
2619 | static int __init preconfigure_through_82801(struct pci_dev *dev, | |
08d09997 LW |
2620 | struct |
2621 | smsc_ircc_subsystem_configuration | |
2622 | *conf) | |
c1e14a6e LW |
2623 | { |
2624 | unsigned short tmpword; | |
08d09997 | 2625 | unsigned char tmpbyte; |
c1e14a6e | 2626 | |
08d09997 LW |
2627 | IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n"); |
2628 | /* | |
2629 | * Select the range for the COMA COM port (SIR) | |
2630 | * Register COM_DEC: | |
2631 | * Bit 7: reserved | |
2632 | * Bit 6-4, COMB decode range | |
2633 | * Bit 3: reserved | |
2634 | * Bit 2-0, COMA decode range | |
2635 | * | |
2636 | * Decode ranges: | |
2637 | * 000 = 0x3f8-0x3ff (COM1) | |
2638 | * 001 = 0x2f8-0x2ff (COM2) | |
2639 | * 010 = 0x220-0x227 | |
2640 | * 011 = 0x228-0x22f | |
2641 | * 100 = 0x238-0x23f | |
2642 | * 101 = 0x2e8-0x2ef (COM4) | |
2643 | * 110 = 0x338-0x33f | |
2644 | * 111 = 0x3e8-0x3ef (COM3) | |
2645 | */ | |
2646 | pci_read_config_byte(dev, COM_DEC, &tmpbyte); | |
2647 | tmpbyte &= 0xf8; /* mask COMA bits */ | |
2648 | switch(conf->sir_io) { | |
2649 | case 0x3f8: | |
2650 | tmpbyte |= 0x00; | |
2651 | break; | |
2652 | case 0x2f8: | |
2653 | tmpbyte |= 0x01; | |
2654 | break; | |
2655 | case 0x220: | |
2656 | tmpbyte |= 0x02; | |
2657 | break; | |
2658 | case 0x228: | |
2659 | tmpbyte |= 0x03; | |
2660 | break; | |
2661 | case 0x238: | |
2662 | tmpbyte |= 0x04; | |
2663 | break; | |
2664 | case 0x2e8: | |
2665 | tmpbyte |= 0x05; | |
2666 | break; | |
2667 | case 0x338: | |
2668 | tmpbyte |= 0x06; | |
2669 | break; | |
2670 | case 0x3e8: | |
2671 | tmpbyte |= 0x07; | |
2672 | break; | |
2673 | default: | |
2674 | tmpbyte |= 0x01; /* COM2 default */ | |
2675 | } | |
2676 | IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte); | |
2677 | pci_write_config_byte(dev, COM_DEC, tmpbyte); | |
c1e14a6e | 2678 | |
08d09997 LW |
2679 | /* Enable Low Pin Count interface */ |
2680 | pci_read_config_word(dev, LPC_EN, &tmpword); | |
2681 | /* These seem to be set up at all times, | |
2682 | * just make sure it is properly set. | |
2683 | */ | |
2684 | switch(conf->cfg_base) { | |
2685 | case 0x04e: | |
2686 | tmpword |= 0x2000; | |
2687 | break; | |
2688 | case 0x02e: | |
2689 | tmpword |= 0x1000; | |
2690 | break; | |
2691 | case 0x062: | |
2692 | tmpword |= 0x0800; | |
2693 | break; | |
2694 | case 0x060: | |
2695 | tmpword |= 0x0400; | |
2696 | break; | |
2697 | default: | |
2698 | IRDA_WARNING("Uncommon I/O base address: 0x%04x\n", | |
2699 | conf->cfg_base); | |
2700 | break; | |
2701 | } | |
2702 | tmpword &= 0xfffd; /* disable LPC COMB */ | |
2703 | tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ | |
2704 | IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword); | |
c1e14a6e LW |
2705 | pci_write_config_word(dev, LPC_EN, tmpword); |
2706 | ||
08d09997 LW |
2707 | /* |
2708 | * Configure LPC DMA channel | |
2709 | * PCI_DMA_C bits: | |
2710 | * Bit 15-14: DMA channel 7 select | |
2711 | * Bit 13-12: DMA channel 6 select | |
2712 | * Bit 11-10: DMA channel 5 select | |
2713 | * Bit 9-8: Reserved | |
2714 | * Bit 7-6: DMA channel 3 select | |
2715 | * Bit 5-4: DMA channel 2 select | |
2716 | * Bit 3-2: DMA channel 1 select | |
2717 | * Bit 1-0: DMA channel 0 select | |
2718 | * 00 = Reserved value | |
2719 | * 01 = PC/PCI DMA | |
2720 | * 10 = Reserved value | |
2721 | * 11 = LPC I/F DMA | |
2722 | */ | |
2723 | pci_read_config_word(dev, PCI_DMA_C, &tmpword); | |
2724 | switch(conf->fir_dma) { | |
2725 | case 0x07: | |
2726 | tmpword |= 0xc000; | |
2727 | break; | |
2728 | case 0x06: | |
2729 | tmpword |= 0x3000; | |
2730 | break; | |
2731 | case 0x05: | |
2732 | tmpword |= 0x0c00; | |
2733 | break; | |
2734 | case 0x03: | |
2735 | tmpword |= 0x00c0; | |
2736 | break; | |
2737 | case 0x02: | |
2738 | tmpword |= 0x0030; | |
2739 | break; | |
2740 | case 0x01: | |
2741 | tmpword |= 0x000c; | |
2742 | break; | |
2743 | case 0x00: | |
2744 | tmpword |= 0x0003; | |
2745 | break; | |
2746 | default: | |
2747 | break; /* do not change settings */ | |
2748 | } | |
2749 | IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword); | |
2750 | pci_write_config_word(dev, PCI_DMA_C, tmpword); | |
2751 | ||
2752 | /* | |
2753 | * GEN2_DEC bits: | |
2754 | * Bit 15-4: Generic I/O range | |
2755 | * Bit 3-1: reserved (read as 0) | |
2756 | * Bit 0: enable GEN2 range on LPC I/F | |
2757 | */ | |
2758 | tmpword = conf->fir_io & 0xfff8; | |
2759 | tmpword |= 0x0001; | |
2760 | IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword); | |
2761 | pci_write_config_word(dev, GEN2_DEC, tmpword); | |
c1e14a6e LW |
2762 | |
2763 | /* Pre-configure chip */ | |
08d09997 LW |
2764 | return preconfigure_smsc_chip(conf); |
2765 | } | |
c1e14a6e | 2766 | |
08d09997 LW |
2767 | /* |
2768 | * Pre-configure a certain port on the ALi 1533 bridge. | |
2769 | * This is based on reverse-engineering since ALi does not | |
2770 | * provide any data sheet for the 1533 chip. | |
2771 | */ | |
2772 | static void __init preconfigure_ali_port(struct pci_dev *dev, | |
2773 | unsigned short port) | |
2774 | { | |
2775 | unsigned char reg; | |
2776 | /* These bits obviously control the different ports */ | |
2777 | unsigned char mask; | |
2778 | unsigned char tmpbyte; | |
2779 | ||
2780 | switch(port) { | |
2781 | case 0x0130: | |
2782 | case 0x0178: | |
2783 | reg = 0xb0; | |
2784 | mask = 0x80; | |
2785 | break; | |
2786 | case 0x03f8: | |
2787 | reg = 0xb4; | |
2788 | mask = 0x80; | |
2789 | break; | |
2790 | case 0x02f8: | |
2791 | reg = 0xb4; | |
2792 | mask = 0x30; | |
2793 | break; | |
2794 | case 0x02e8: | |
2795 | reg = 0xb4; | |
2796 | mask = 0x08; | |
2797 | break; | |
2798 | default: | |
2799 | IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port); | |
2800 | return; | |
2801 | } | |
2802 | ||
2803 | pci_read_config_byte(dev, reg, &tmpbyte); | |
2804 | /* Turn on the right bits */ | |
2805 | tmpbyte |= mask; | |
2806 | pci_write_config_byte(dev, reg, tmpbyte); | |
2807 | IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port); | |
2808 | return; | |
c1e14a6e LW |
2809 | } |
2810 | ||
2811 | static int __init preconfigure_through_ali(struct pci_dev *dev, | |
08d09997 LW |
2812 | struct |
2813 | smsc_ircc_subsystem_configuration | |
2814 | *conf) | |
c1e14a6e | 2815 | { |
08d09997 LW |
2816 | /* Configure the two ports on the ALi 1533 */ |
2817 | preconfigure_ali_port(dev, conf->sir_io); | |
2818 | preconfigure_ali_port(dev, conf->fir_io); | |
2819 | ||
2820 | /* Pre-configure chip */ | |
2821 | return preconfigure_smsc_chip(conf); | |
c1e14a6e LW |
2822 | } |
2823 | ||
2824 | static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, | |
2825 | unsigned short ircc_fir, | |
2826 | unsigned short ircc_sir, | |
2827 | unsigned char ircc_dma, | |
2828 | unsigned char ircc_irq) | |
2829 | { | |
2830 | struct pci_dev *dev = NULL; | |
2831 | unsigned short ss_vendor = 0x0000; | |
2832 | unsigned short ss_device = 0x0000; | |
2833 | int ret = 0; | |
2834 | ||
2835 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
2836 | ||
2837 | while (dev != NULL) { | |
2838 | struct smsc_ircc_subsystem_configuration *conf; | |
2839 | ||
2840 | /* | |
08d09997 LW |
2841 | * Cache the subsystem vendor/device: |
2842 | * some manufacturers fail to set this for all components, | |
2843 | * so we save it in case there is just 0x0000 0x0000 on the | |
2844 | * device we want to check. | |
c1e14a6e LW |
2845 | */ |
2846 | if (dev->subsystem_vendor != 0x0000U) { | |
2847 | ss_vendor = dev->subsystem_vendor; | |
2848 | ss_device = dev->subsystem_device; | |
2849 | } | |
2850 | conf = subsystem_configurations; | |
2851 | for( ; conf->subvendor; conf++) { | |
2852 | if(conf->vendor == dev->vendor && | |
2853 | conf->device == dev->device && | |
08d09997 LW |
2854 | conf->subvendor == ss_vendor && |
2855 | /* Sometimes these are cached values */ | |
2856 | (conf->subdevice == ss_device || | |
2857 | conf->subdevice == 0xffff)) { | |
2858 | struct smsc_ircc_subsystem_configuration | |
2859 | tmpconf; | |
c1e14a6e | 2860 | |
08d09997 LW |
2861 | memcpy(&tmpconf, conf, |
2862 | sizeof(struct smsc_ircc_subsystem_configuration)); | |
c1e14a6e | 2863 | |
08d09997 LW |
2864 | /* |
2865 | * Override the default values with anything | |
2866 | * passed in as parameter | |
2867 | */ | |
c1e14a6e LW |
2868 | if (ircc_cfg != 0) |
2869 | tmpconf.cfg_base = ircc_cfg; | |
2870 | if (ircc_fir != 0) | |
2871 | tmpconf.fir_io = ircc_fir; | |
2872 | if (ircc_sir != 0) | |
2873 | tmpconf.sir_io = ircc_sir; | |
916f11c7 | 2874 | if (ircc_dma != DMA_INVAL) |
c1e14a6e | 2875 | tmpconf.fir_dma = ircc_dma; |
916f11c7 | 2876 | if (ircc_irq != IRQ_INVAL) |
c1e14a6e LW |
2877 | tmpconf.fir_irq = ircc_irq; |
2878 | ||
2879 | IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name); | |
2880 | if (conf->preconfigure) | |
2881 | ret = conf->preconfigure(dev, &tmpconf); | |
2882 | else | |
2883 | ret = -ENODEV; | |
2884 | } | |
2885 | } | |
2886 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
2887 | } | |
2888 | ||
2889 | return ret; | |
2890 | } | |
2891 | #endif // CONFIG_PCI | |
2892 | ||
1da177e4 LT |
2893 | /************************************************ |
2894 | * | |
2895 | * Transceivers specific functions | |
2896 | * | |
2897 | ************************************************/ | |
2898 | ||
2899 | ||
2900 | /* | |
2901 | * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed) | |
2902 | * | |
2903 | * Program transceiver through smsc-ircc ATC circuitry | |
2904 | * | |
2905 | */ | |
2906 | ||
2907 | static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) | |
2908 | { | |
2909 | unsigned long jiffies_now, jiffies_timeout; | |
98b77773 | 2910 | u8 val; |
527b6af4 | 2911 | |
98b77773 DT |
2912 | jiffies_now = jiffies; |
2913 | jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; | |
527b6af4 | 2914 | |
1da177e4 LT |
2915 | /* ATC */ |
2916 | register_bank(fir_base, 4); | |
98b77773 DT |
2917 | outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, |
2918 | fir_base + IRCC_ATC); | |
2919 | ||
2920 | while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && | |
2921 | !time_after(jiffies, jiffies_timeout)) | |
2922 | /* empty */; | |
2923 | ||
2924 | if (val) | |
a97a6f10 | 2925 | IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__, |
98b77773 | 2926 | inb(fir_base + IRCC_ATC)); |
1da177e4 LT |
2927 | } |
2928 | ||
2929 | /* | |
2930 | * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base) | |
2931 | * | |
2932 | * Probe transceiver smsc-ircc ATC circuitry | |
2933 | * | |
2934 | */ | |
2935 | ||
2936 | static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) | |
2937 | { | |
2938 | return 0; | |
2939 | } | |
2940 | ||
2941 | /* | |
2942 | * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed) | |
2943 | * | |
527b6af4 | 2944 | * Set transceiver |
1da177e4 LT |
2945 | * |
2946 | */ | |
2947 | ||
2948 | static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) | |
2949 | { | |
98b77773 | 2950 | u8 fast_mode; |
527b6af4 | 2951 | |
98b77773 DT |
2952 | switch (speed) { |
2953 | default: | |
2954 | case 576000 : | |
527b6af4 | 2955 | fast_mode = 0; |
1da177e4 | 2956 | break; |
98b77773 DT |
2957 | case 1152000 : |
2958 | case 4000000 : | |
1da177e4 LT |
2959 | fast_mode = IRCC_LCR_A_FAST; |
2960 | break; | |
1da177e4 LT |
2961 | } |
2962 | register_bank(fir_base, 0); | |
98b77773 | 2963 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); |
1da177e4 LT |
2964 | } |
2965 | ||
2966 | /* | |
2967 | * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base) | |
2968 | * | |
527b6af4 | 2969 | * Probe transceiver |
1da177e4 LT |
2970 | * |
2971 | */ | |
2972 | ||
2973 | static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) | |
2974 | { | |
2975 | return 0; | |
2976 | } | |
2977 | ||
2978 | /* | |
2979 | * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed) | |
2980 | * | |
527b6af4 | 2981 | * Set transceiver |
1da177e4 LT |
2982 | * |
2983 | */ | |
2984 | ||
2985 | static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) | |
2986 | { | |
98b77773 | 2987 | u8 fast_mode; |
527b6af4 | 2988 | |
98b77773 DT |
2989 | switch (speed) { |
2990 | default: | |
2991 | case 576000 : | |
527b6af4 | 2992 | fast_mode = 0; |
1da177e4 | 2993 | break; |
98b77773 DT |
2994 | case 1152000 : |
2995 | case 4000000 : | |
1da177e4 LT |
2996 | fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; |
2997 | break; | |
527b6af4 | 2998 | |
1da177e4 LT |
2999 | } |
3000 | /* This causes an interrupt */ | |
3001 | register_bank(fir_base, 0); | |
98b77773 | 3002 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); |
1da177e4 LT |
3003 | } |
3004 | ||
3005 | /* | |
3006 | * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base) | |
3007 | * | |
527b6af4 | 3008 | * Probe transceiver |
1da177e4 LT |
3009 | * |
3010 | */ | |
3011 | ||
3012 | static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) | |
3013 | { | |
3014 | return 0; | |
3015 | } | |
3016 | ||
3017 | ||
3018 | module_init(smsc_ircc_init); | |
3019 | module_exit(smsc_ircc_cleanup); |