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[IRDA]: smsc-ircc2, smcinit support for ALi ISA bridges
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
1da177e4
LT		 11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 14 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 15 *
16 *
17 * Based on smc-ircc.c:
18 *
19 * Copyright (c) 2001 Stefani Seibold
20 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 21 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 22 *
23 * and irport.c:
24 *
25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
26 *
527b6af4
DT		 27 *
28 * This program is free software; you can redistribute it and/or
29 * modify it under the terms of the GNU General Public License as
30 * published by the Free Software Foundation; either version 2 of
1da177e4 31 * the License, or (at your option) any later version.
527b6af4 32 *
1da177e4
LT		 33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
527b6af4
DT		 37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 41 * MA 02111-1307 USA
42 *
43 ********************************************************************/
44
45#include <linux/module.h>
46#include <linux/kernel.h>
47#include <linux/types.h>
48#include <linux/skbuff.h>
49#include <linux/netdevice.h>
50#include <linux/ioport.h>
51#include <linux/delay.h>
52#include <linux/slab.h>
53#include <linux/init.h>
54#include <linux/rtnetlink.h>
55#include <linux/serial_reg.h>
56#include <linux/dma-mapping.h>
d052d1be 57#include <linux/platform_device.h>
1da177e4
LT		 58
59#include <asm/io.h>
60#include <asm/dma.h>
61#include <asm/byteorder.h>
62
63#include <linux/spinlock.h>
64#include <linux/pm.h>
c1e14a6e
LW		 65#ifdef CONFIG_PCI
66#include <linux/pci.h>
67#endif
1da177e4
LT		 68
69#include <net/irda/wrapper.h>
70#include <net/irda/irda.h>
71#include <net/irda/irda_device.h>
72
73#include "smsc-ircc2.h"
74#include "smsc-sio.h"
75
98b77773
DT		 76
77MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79MODULE_LICENSE("GPL");
80
98b77773
DT		 81static int ircc_dma = 255;
82module_param(ircc_dma, int, 0);
83MODULE_PARM_DESC(ircc_dma, "DMA channel");
84
85static int ircc_irq = 255;
86module_param(ircc_irq, int, 0);
87MODULE_PARM_DESC(ircc_irq, "IRQ line");
88
89static int ircc_fir;
90module_param(ircc_fir, int, 0);
91MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
92
93static int ircc_sir;
94module_param(ircc_sir, int, 0);
95MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
96
97static int ircc_cfg;
98module_param(ircc_cfg, int, 0);
99MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
100
101static int ircc_transceiver;
102module_param(ircc_transceiver, int, 0);
103MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
104
1da177e4
LT		 105/* Types */
106
c1e14a6e
LW		 107#ifdef CONFIG_PCI
108struct smsc_ircc_subsystem_configuration {
109 unsigned short vendor; /* PCI vendor ID */
110 unsigned short device; /* PCI vendor ID */
111 unsigned short subvendor; /* PCI subsystem vendor ID */
112 unsigned short subdevice; /* PCI sybsystem device ID */
113 unsigned short sir_io; /* I/O port for SIR */
114 unsigned short fir_io; /* I/O port for FIR */
115 unsigned char fir_irq; /* FIR IRQ */
116 unsigned char fir_dma; /* FIR DMA */
117 unsigned short cfg_base; /* I/O port for chip configuration */
118 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
119 const char *name; /* name shown as info */
120};
121#endif
122
1da177e4
LT		 123struct smsc_transceiver {
124 char *name;
527b6af4 125 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 126 int (*probe)(int fir_base);
127};
1da177e4
LT		 128
129struct smsc_chip {
130 char *name;
131 #if 0
132 u8 type;
133 #endif
134 u16 flags;
135 u8 devid;
136 u8 rev;
137};
1da177e4
LT		 138
139struct smsc_chip_address {
140 unsigned int cfg_base;
141 unsigned int type;
142};
1da177e4
LT		 143
144/* Private data for each instance */
145struct smsc_ircc_cb {
146 struct net_device *netdev; /* Yes! we are some kind of netdevice */
147 struct net_device_stats stats;
148 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 149
1da177e4
LT		 150 chipio_t io; /* IrDA controller information */
151 iobuff_t tx_buff; /* Transmit buffer */
152 iobuff_t rx_buff; /* Receive buffer */
153 dma_addr_t tx_buff_dma;
154 dma_addr_t rx_buff_dma;
155
156 struct qos_info qos; /* QoS capabilities for this device */
157
158 spinlock_t lock; /* For serializing operations */
527b6af4 159
1da177e4
LT		 160 __u32 new_speed;
161 __u32 flags; /* Interface flags */
162
163 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
164 int tx_len; /* Number of frames in tx_buff */
165
166 int transceiver;
6bb3b2cd 167 struct platform_device *pldev;
1da177e4
LT		 168};
169
170/* Constants */
171
6bb3b2cd
DT		 172#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
173
1da177e4
LT		 174#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
175#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 176#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 177#define SMSC_IRCC2_C_SIR_STOP 0
178
6bb3b2cd
DT		 179static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
180
1da177e4
LT		 181/* Prototypes */
182
183static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
184static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
185static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
186static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
187static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
188static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 189static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
190static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4
LT		 191static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
192static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
193static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
80a90589
DT		 194static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
195static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 196static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
197static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
1da177e4
LT		 198static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
199static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
200static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
201#if SMSC_IRCC2_C_SIR_STOP
202static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
203#endif
204static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
205static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
206static int smsc_ircc_net_open(struct net_device *dev);
207static int smsc_ircc_net_close(struct net_device *dev);
208static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
209#if SMSC_IRCC2_C_NET_TIMEOUT
210static void smsc_ircc_timeout(struct net_device *dev);
211#endif
212static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
1da177e4
LT		 213static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
214static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
215static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
216static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
217
218/* Probing */
219static int __init smsc_ircc_look_for_chips(void);
b6158d23
DT		 220static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
221static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
222static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
1da177e4
LT		 223static int __init smsc_superio_fdc(unsigned short cfg_base);
224static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e
LW		 225#ifdef CONFIG_PCI
226static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
227static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
08d09997
LW		 228static void __init preconfigure_ali_port(struct pci_dev *dev,
229 unsigned short port);
c1e14a6e
LW		 230static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
231static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
232 unsigned short ircc_fir,
233 unsigned short ircc_sir,
234 unsigned char ircc_dma,
235 unsigned char ircc_irq);
236#endif
1da177e4
LT		 237
238/* Transceivers specific functions */
239
240static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
241static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
242static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
243static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
244static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
245static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
246
247/* Power Management */
248
3ae5eaec
RK		 249static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
250static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 251
3ae5eaec 252static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 253 .suspend = smsc_ircc_suspend,
254 .resume = smsc_ircc_resume,
3ae5eaec
RK		 255 .driver = {
256 .name = SMSC_IRCC2_DRIVER_NAME,
257 },
6bb3b2cd 258};
1da177e4
LT		 259
260/* Transceivers for SMSC-ircc */
261
b6158d23 262static struct smsc_transceiver smsc_transceivers[] =
1da177e4 263{
98b77773
DT		 264 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
265 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
266 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
267 { NULL, NULL }
1da177e4 268};
a956f4ca 269#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 270
271/* SMC SuperIO chipsets definitions */
272
273#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
274#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
275#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
276#define SIR 0 /* SuperIO Chip has only slow IRDA */
277#define FIR 4 /* SuperIO Chip has fast IRDA */
278#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
279
b6158d23 280static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 281{
282 /* Base address 0x3f0 or 0x370 */
283 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
284 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
285 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
286 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
287 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
288 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
289 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
290 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
291 { NULL }
292};
293
b6158d23 294static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 295{
296 /* Base address 0x3f0 or 0x370 */
297 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
298 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
299 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
300 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
301 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
302 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
303 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
304 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
305 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
306 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
307 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
308 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
309 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
310 { NULL }
311};
312
b6158d23 313static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 314{
315 /* Base address 0x2E or 0x4E */
316 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
317 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
318 { NULL }
319};
320
b6158d23 321static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 322{
323 /* Base address 0x2E or 0x4E */
324 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
325 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
326 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
327 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
328 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
329 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
330 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
331 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
332 { NULL }
333};
334
335#define SMSCSIO_TYPE_FDC 1
336#define SMSCSIO_TYPE_LPC 2
337#define SMSCSIO_TYPE_FLAT 4
338#define SMSCSIO_TYPE_PAGED 8
339
b6158d23 340static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 341{
98b77773
DT		 342 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
343 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
344 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
345 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
346 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
347 { 0, 0 }
1da177e4
LT		 348};
349
350/* Globals */
351
98b77773
DT		 352static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
353static unsigned short dev_count;
1da177e4
LT		 354
355static inline void register_bank(int iobase, int bank)
356{
98b77773
DT		 357 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
358 iobase + IRCC_MASTER);
1da177e4
LT		 359}
360
361
362/*******************************************************************************
363 *
364 *
365 * SMSC-ircc stuff
366 *
367 *
368 *******************************************************************************/
369
370/*
371 * Function smsc_ircc_init ()
372 *
373 * Initialize chip. Just try to find out how many chips we are dealing with
374 * and where they are
375 */
376static int __init smsc_ircc_init(void)
377{
6bb3b2cd 378 int ret;
1da177e4
LT		 379
380 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
381
3ae5eaec 382 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd
DT		 383 if (ret) {
384 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
385 return ret;
386 }
387
c1e14a6e
LW		 388#ifdef CONFIG_PCI
389 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
390 /* Ignore errors from preconfiguration */
391 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
392 }
393#endif
394
98b77773 395 dev_count = 0;
527b6af4 396
98b77773 397 if (ircc_fir > 0 && ircc_sir > 0) {
1da177e4
LT		 398 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
399 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
400
6bb3b2cd
DT		 401 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
402 ret = -ENODEV;
403 } else {
505db036 404 ret = -ENODEV;
1da177e4 405
6bb3b2cd
DT		 406 /* try user provided configuration register base address */
407 if (ircc_cfg > 0) {
408 IRDA_MESSAGE(" Overriding configuration address "
409 "0x%04x\n", ircc_cfg);
410 if (!smsc_superio_fdc(ircc_cfg))
411 ret = 0;
412 if (!smsc_superio_lpc(ircc_cfg))
413 ret = 0;
414 }
1da177e4 415
6bb3b2cd 416 if (smsc_ircc_look_for_chips() > 0)
1da177e4
LT		 417 ret = 0;
418 }
527b6af4 419
6bb3b2cd 420 if (ret)
3ae5eaec 421 platform_driver_unregister(&smsc_ircc_driver);
527b6af4 422
1da177e4
LT		 423 return ret;
424}
425
426/*
427 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
428 *
429 * Try to open driver instance
430 *
431 */
432static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
433{
434 struct smsc_ircc_cb *self;
435 struct net_device *dev;
436 int err;
527b6af4 437
1da177e4
LT		 438 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
439
440 err = smsc_ircc_present(fir_base, sir_base);
98b77773 441 if (err)
1da177e4 442 goto err_out;
527b6af4 443
1da177e4 444 err = -ENOMEM;
a956f4ca 445 if (dev_count >= ARRAY_SIZE(dev_self)) {
1da177e4
LT		 446 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
447 goto err_out1;
448 }
449
450 /*
451 * Allocate new instance of the driver
452 */
453 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
454 if (!dev) {
455 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
456 goto err_out1;
457 }
458
459 SET_MODULE_OWNER(dev);
460
461 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
462#if SMSC_IRCC2_C_NET_TIMEOUT
463 dev->tx_timeout = smsc_ircc_timeout;
98b77773 464 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4
LT		 465#endif
466 dev->open = smsc_ircc_net_open;
467 dev->stop = smsc_ircc_net_close;
468 dev->do_ioctl = smsc_ircc_net_ioctl;
469 dev->get_stats = smsc_ircc_net_get_stats;
527b6af4 470
da0841a0 471 self = netdev_priv(dev);
1da177e4
LT		 472 self->netdev = dev;
473
474 /* Make ifconfig display some details */
475 dev->base_addr = self->io.fir_base = fir_base;
476 dev->irq = self->io.irq = irq;
477
478 /* Need to store self somewhere */
6bb3b2cd 479 dev_self[dev_count] = self;
1da177e4
LT		 480 spin_lock_init(&self->lock);
481
527b6af4 482 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 483 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
484
485 self->rx_buff.head =
486 dma_alloc_coherent(NULL, self->rx_buff.truesize,
487 &self->rx_buff_dma, GFP_KERNEL);
488 if (self->rx_buff.head == NULL) {
489 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
490 driver_name);
491 goto err_out2;
492 }
493
494 self->tx_buff.head =
495 dma_alloc_coherent(NULL, self->tx_buff.truesize,
496 &self->tx_buff_dma, GFP_KERNEL);
497 if (self->tx_buff.head == NULL) {
498 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
499 driver_name);
500 goto err_out3;
501 }
502
503 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
504 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
505
506 self->rx_buff.in_frame = FALSE;
507 self->rx_buff.state = OUTSIDE_FRAME;
508 self->tx_buff.data = self->tx_buff.head;
509 self->rx_buff.data = self->rx_buff.head;
527b6af4 510
1da177e4 511 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 512 smsc_ircc_setup_qos(self);
1da177e4 513 smsc_ircc_init_chip(self);
527b6af4 514
98b77773
DT		 515 if (ircc_transceiver > 0 &&
516 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 517 self->transceiver = ircc_transceiver;
518 else
519 smsc_ircc_probe_transceiver(self);
520
521 err = register_netdev(self->netdev);
98b77773 522 if (err) {
1da177e4
LT		 523 IRDA_ERROR("%s, Network device registration failed!\n",
524 driver_name);
525 goto err_out4;
526 }
527
6bb3b2cd
DT		 528 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
529 dev_count, NULL, 0);
530 if (IS_ERR(self->pldev)) {
531 err = PTR_ERR(self->pldev);
532 goto err_out5;
533 }
3ae5eaec 534 platform_set_drvdata(self->pldev, self);
1da177e4
LT		 535
536 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 537 dev_count++;
1da177e4
LT		 538
539 return 0;
98b77773 540
6bb3b2cd
DT		 541 err_out5:
542 unregister_netdev(self->netdev);
543
1da177e4
LT		 544 err_out4:
545 dma_free_coherent(NULL, self->tx_buff.truesize,
546 self->tx_buff.head, self->tx_buff_dma);
547 err_out3:
548 dma_free_coherent(NULL, self->rx_buff.truesize,
549 self->rx_buff.head, self->rx_buff_dma);
550 err_out2:
551 free_netdev(self->netdev);
6bb3b2cd 552 dev_self[dev_count] = NULL;
1da177e4
LT		 553 err_out1:
554 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
555 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
556 err_out:
557 return err;
558}
559
560/*
561 * Function smsc_ircc_present(fir_base, sir_base)
562 *
563 * Check the smsc-ircc chip presence
564 *
565 */
566static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
567{
568 unsigned char low, high, chip, config, dma, irq, version;
569
570 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
571 driver_name)) {
572 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
573 __FUNCTION__, fir_base);
574 goto out1;
575 }
576
577 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
578 driver_name)) {
579 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
580 __FUNCTION__, sir_base);
581 goto out2;
582 }
583
584 register_bank(fir_base, 3);
585
98b77773
DT		 586 high = inb(fir_base + IRCC_ID_HIGH);
587 low = inb(fir_base + IRCC_ID_LOW);
588 chip = inb(fir_base + IRCC_CHIP_ID);
589 version = inb(fir_base + IRCC_VERSION);
590 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 591 dma = config & IRCC_INTERFACE_DMA_MASK;
592 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
593
527b6af4 594 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 595 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
1da177e4
LT		 596 __FUNCTION__, fir_base);
597 goto out3;
598 }
599 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
600 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
601 chip & 0x0f, version, fir_base, sir_base, dma, irq);
602
603 return 0;
98b77773 604
1da177e4
LT		 605 out3:
606 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
607 out2:
608 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
609 out1:
610 return -ENODEV;
611}
612
613/*
614 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
615 *
616 * Setup I/O
617 *
618 */
527b6af4
DT		 619static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
620 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 621 u8 dma, u8 irq)
622{
623 unsigned char config, chip_dma, chip_irq;
624
625 register_bank(fir_base, 3);
98b77773
DT		 626 config = inb(fir_base + IRCC_INTERFACE);
627 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
628 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 629
630 self->io.fir_base = fir_base;
631 self->io.sir_base = sir_base;
632 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
633 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
634 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
635 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
636
637 if (irq < 255) {
638 if (irq != chip_irq)
639 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
640 driver_name, chip_irq, irq);
641 self->io.irq = irq;
98b77773 642 } else
1da177e4 643 self->io.irq = chip_irq;
527b6af4 644
1da177e4
LT		 645 if (dma < 255) {
646 if (dma != chip_dma)
647 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
648 driver_name, chip_dma, dma);
649 self->io.dma = dma;
98b77773 650 } else
1da177e4
LT		 651 self->io.dma = chip_dma;
652
653}
654
655/*
656 * Function smsc_ircc_setup_qos(self)
657 *
658 * Setup qos
659 *
660 */
661static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
662{
663 /* Initialize QoS for this device */
664 irda_init_max_qos_capabilies(&self->qos);
527b6af4 665
1da177e4
LT		 666 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
667 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
668
669 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
670 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
671 irda_qos_bits_to_value(&self->qos);
672}
673
674/*
675 * Function smsc_ircc_init_chip(self)
676 *
677 * Init chip
678 *
679 */
680static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
681{
e812cb52 682 int iobase = self->io.fir_base;
1da177e4
LT		 683
684 register_bank(iobase, 0);
98b77773
DT		 685 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
686 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 687
688 register_bank(iobase, 1);
e812cb52 689 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 690 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 691
692#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 693 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
694 iobase + IRCC_SCE_CFGB);
527b6af4 695#else
98b77773
DT		 696 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
697 iobase + IRCC_SCE_CFGB);
527b6af4 698#endif
98b77773
DT		 699 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
700 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 701
1da177e4 702 register_bank(iobase, 4);
e812cb52 703 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 704
1da177e4 705 register_bank(iobase, 0);
e812cb52 706 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 707
708 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 709
1da177e4 710 /* Power on device */
98b77773 711 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 712}
713
714/*
715 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
716 *
717 * Process IOCTL commands for this device
718 *
719 */
720static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
721{
722 struct if_irda_req *irq = (struct if_irda_req *) rq;
723 struct smsc_ircc_cb *self;
724 unsigned long flags;
725 int ret = 0;
726
727 IRDA_ASSERT(dev != NULL, return -1;);
728
da0841a0 729 self = netdev_priv(dev);
1da177e4
LT		 730
731 IRDA_ASSERT(self != NULL, return -1;);
732
733 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
527b6af4 734
1da177e4
LT		 735 switch (cmd) {
736 case SIOCSBANDWIDTH: /* Set bandwidth */
737 if (!capable(CAP_NET_ADMIN))
738 ret = -EPERM;
739 else {
740 /* Make sure we are the only one touching
741 * self->io.speed and the hardware - Jean II */
742 spin_lock_irqsave(&self->lock, flags);
743 smsc_ircc_change_speed(self, irq->ifr_baudrate);
744 spin_unlock_irqrestore(&self->lock, flags);
745 }
746 break;
747 case SIOCSMEDIABUSY: /* Set media busy */
748 if (!capable(CAP_NET_ADMIN)) {
749 ret = -EPERM;
750 break;
751 }
752
753 irda_device_set_media_busy(self->netdev, TRUE);
754 break;
755 case SIOCGRECEIVING: /* Check if we are receiving right now */
756 irq->ifr_receiving = smsc_ircc_is_receiving(self);
757 break;
758 #if 0
759 case SIOCSDTRRTS:
760 if (!capable(CAP_NET_ADMIN)) {
761 ret = -EPERM;
762 break;
763 }
764 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
765 break;
766 #endif
767 default:
768 ret = -EOPNOTSUPP;
769 }
527b6af4 770
1da177e4
LT		 771 return ret;
772}
773
774static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
775{
da0841a0 776 struct smsc_ircc_cb *self = netdev_priv(dev);
527b6af4 777
1da177e4
LT		 778 return &self->stats;
779}
780
781#if SMSC_IRCC2_C_NET_TIMEOUT
782/*
783 * Function smsc_ircc_timeout (struct net_device *dev)
784 *
785 * The networking timeout management.
786 *
787 */
788
789static void smsc_ircc_timeout(struct net_device *dev)
790{
da0841a0 791 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 792 unsigned long flags;
793
1da177e4
LT		 794 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
795 dev->name, self->io.speed);
796 spin_lock_irqsave(&self->lock, flags);
797 smsc_ircc_sir_start(self);
798 smsc_ircc_change_speed(self, self->io.speed);
799 dev->trans_start = jiffies;
800 netif_wake_queue(dev);
801 spin_unlock_irqrestore(&self->lock, flags);
802}
803#endif
804
805/*
806 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
807 *
808 * Transmits the current frame until FIFO is full, then
809 * waits until the next transmit interrupt, and continues until the
810 * frame is transmitted.
811 */
812int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
813{
814 struct smsc_ircc_cb *self;
815 unsigned long flags;
1da177e4
LT		 816 s32 speed;
817
818 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
819
820 IRDA_ASSERT(dev != NULL, return 0;);
527b6af4 821
da0841a0 822 self = netdev_priv(dev);
1da177e4
LT		 823 IRDA_ASSERT(self != NULL, return 0;);
824
1da177e4 825 netif_stop_queue(dev);
527b6af4 826
1da177e4
LT		 827 /* Make sure test of self->io.speed & speed change are atomic */
828 spin_lock_irqsave(&self->lock, flags);
829
830 /* Check if we need to change the speed */
831 speed = irda_get_next_speed(skb);
98b77773 832 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 833 /* Check for empty frame */
834 if (!skb->len) {
835 /*
836 * We send frames one by one in SIR mode (no
837 * pipelining), so at this point, if we were sending
838 * a previous frame, we just received the interrupt
839 * telling us it is finished (UART_IIR_THRI).
840 * Therefore, waiting for the transmitter to really
841 * finish draining the fifo won't take too long.
842 * And the interrupt handler is not expected to run.
843 * - Jean II */
844 smsc_ircc_sir_wait_hw_transmitter_finish(self);
845 smsc_ircc_change_speed(self, speed);
846 spin_unlock_irqrestore(&self->lock, flags);
847 dev_kfree_skb(skb);
848 return 0;
1da177e4 849 }
98b77773 850 self->new_speed = speed;
1da177e4
LT		 851 }
852
853 /* Init tx buffer */
854 self->tx_buff.data = self->tx_buff.head;
855
856 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 857 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 858 self->tx_buff.truesize);
527b6af4 859
1da177e4
LT		 860 self->stats.tx_bytes += self->tx_buff.len;
861
862 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 863 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 864
865 spin_unlock_irqrestore(&self->lock, flags);
866
867 dev_kfree_skb(skb);
527b6af4 868
1da177e4
LT		 869 return 0;
870}
871
872/*
873 * Function smsc_ircc_set_fir_speed (self, baud)
874 *
875 * Change the speed of the device
876 *
877 */
878static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
879{
880 int fir_base, ir_mode, ctrl, fast;
881
882 IRDA_ASSERT(self != NULL, return;);
883 fir_base = self->io.fir_base;
884
885 self->io.speed = speed;
886
98b77773 887 switch (speed) {
1da177e4 888 default:
527b6af4 889 case 576000:
1da177e4
LT		 890 ir_mode = IRCC_CFGA_IRDA_HDLC;
891 ctrl = IRCC_CRC;
892 fast = 0;
893 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
894 break;
895 case 1152000:
896 ir_mode = IRCC_CFGA_IRDA_HDLC;
897 ctrl = IRCC_1152 | IRCC_CRC;
898 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
899 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
900 __FUNCTION__);
901 break;
902 case 4000000:
903 ir_mode = IRCC_CFGA_IRDA_4PPM;
904 ctrl = IRCC_CRC;
905 fast = IRCC_LCR_A_FAST;
906 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
907 __FUNCTION__);
908 break;
909 }
910 #if 0
911 Now in tranceiver!
912 /* This causes an interrupt */
913 register_bank(fir_base, 0);
98b77773 914 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 915 #endif
527b6af4 916
1da177e4 917 register_bank(fir_base, 1);
98b77773 918 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 919
1da177e4 920 register_bank(fir_base, 4);
98b77773 921 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 922}
923
924/*
925 * Function smsc_ircc_fir_start(self)
926 *
927 * Change the speed of the device
928 *
929 */
930static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
931{
932 struct net_device *dev;
933 int fir_base;
934
935 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
936
937 IRDA_ASSERT(self != NULL, return;);
938 dev = self->netdev;
939 IRDA_ASSERT(dev != NULL, return;);
940
941 fir_base = self->io.fir_base;
942
943 /* Reset everything */
944
945 /* Install FIR transmit handler */
527b6af4 946 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1da177e4
LT		 947
948 /* Clear FIFO */
98b77773 949 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 950
951 /* Enable interrupt */
98b77773 952 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 953
954 register_bank(fir_base, 1);
955
527b6af4 956 /* Select the TX/RX interface */
1da177e4 957#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 958 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
959 fir_base + IRCC_SCE_CFGB);
527b6af4 960#else
98b77773
DT		 961 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
962 fir_base + IRCC_SCE_CFGB);
527b6af4 963#endif
98b77773 964 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 965
966 /* Enable SCE interrupts */
98b77773 967 outb(0, fir_base + IRCC_MASTER);
1da177e4 968 register_bank(fir_base, 0);
98b77773
DT		 969 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
970 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 971}
972
973/*
974 * Function smsc_ircc_fir_stop(self, baud)
975 *
976 * Change the speed of the device
977 *
978 */
979static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
980{
981 int fir_base;
982
983 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 984
1da177e4
LT		 985 IRDA_ASSERT(self != NULL, return;);
986
987 fir_base = self->io.fir_base;
988 register_bank(fir_base, 0);
98b77773
DT		 989 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
990 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 991}
992
993
994/*
995 * Function smsc_ircc_change_speed(self, baud)
996 *
997 * Change the speed of the device
998 *
999 * This function *must* be called with spinlock held, because it may
1000 * be called from the irq handler. - Jean II
1001 */
0fa2f491 1002static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1003{
1da177e4 1004 struct net_device *dev;
1da177e4 1005 int last_speed_was_sir;
527b6af4 1006
1da177e4
LT		 1007 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1008
1009 IRDA_ASSERT(self != NULL, return;);
1010 dev = self->netdev;
1da177e4
LT		 1011
1012 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1013
1014 #if 0
1015 /* Temp Hack */
1016 speed= 1152000;
1017 self->io.speed = speed;
1018 last_speed_was_sir = 0;
527b6af4 1019 smsc_ircc_fir_start(self);
1da177e4 1020 #endif
527b6af4 1021
98b77773 1022 if (self->io.speed == 0)
1da177e4
LT		 1023 smsc_ircc_sir_start(self);
1024
1025 #if 0
98b77773 1026 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1027 #endif
1028
98b77773
DT		 1029 if (self->io.speed != speed)
1030 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1031
1032 self->io.speed = speed;
527b6af4 1033
98b77773
DT		 1034 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1035 if (!last_speed_was_sir) {
1da177e4
LT		 1036 smsc_ircc_fir_stop(self);
1037 smsc_ircc_sir_start(self);
1038 }
527b6af4 1039 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1040 } else {
1041 if (last_speed_was_sir) {
527b6af4 1042 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1043 smsc_ircc_sir_stop(self);
1044 #endif
1045 smsc_ircc_fir_start(self);
1046 }
1047 smsc_ircc_set_fir_speed(self, speed);
1048
1049 #if 0
1050 self->tx_buff.len = 10;
1051 self->tx_buff.data = self->tx_buff.head;
527b6af4 1052
80a90589 1053 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1054 #endif
1055 /* Be ready for incoming frames */
80a90589 1056 smsc_ircc_dma_receive(self);
1da177e4 1057 }
527b6af4 1058
1da177e4
LT		 1059 netif_wake_queue(dev);
1060}
1061
1062/*
1063 * Function smsc_ircc_set_sir_speed (self, speed)
1064 *
1065 * Set speed of IrDA port to specified baudrate
1066 *
1067 */
0fa2f491 1068void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1069{
527b6af4 1070 int iobase;
1da177e4
LT		 1071 int fcr; /* FIFO control reg */
1072 int lcr; /* Line control reg */
1073 int divisor;
1074
1075 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1076
1077 IRDA_ASSERT(self != NULL, return;);
1078 iobase = self->io.sir_base;
527b6af4 1079
1da177e4
LT		 1080 /* Update accounting for new speed */
1081 self->io.speed = speed;
1082
1083 /* Turn off interrupts */
98b77773 1084 outb(0, iobase + UART_IER);
1da177e4 1085
98b77773 1086 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1087
1da177e4
LT		 1088 fcr = UART_FCR_ENABLE_FIFO;
1089
527b6af4 1090 /*
1da177e4
LT		 1091 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1092 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1093 * about this timeout since it will always be fast enough.
1da177e4 1094 */
98b77773
DT		 1095 fcr |= self->io.speed < 38400 ?
1096 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1097
1da177e4
LT		 1098 /* IrDA ports use 8N1 */
1099 lcr = UART_LCR_WLEN8;
527b6af4 1100
98b77773
DT		 1101 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1102 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1103 outb(divisor >> 8, iobase + UART_DLM);
1104 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1105 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1106
1107 /* Turn on interrups */
98b77773 1108 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 1109
1110 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1111}
1112
1113
1114/*
1115 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1116 *
1117 * Transmit the frame!
1118 *
1119 */
1120static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1121{
1122 struct smsc_ircc_cb *self;
1123 unsigned long flags;
1124 s32 speed;
1da177e4
LT		 1125 int mtt;
1126
1127 IRDA_ASSERT(dev != NULL, return 0;);
da0841a0 1128 self = netdev_priv(dev);
1da177e4
LT		 1129 IRDA_ASSERT(self != NULL, return 0;);
1130
1da177e4
LT		 1131 netif_stop_queue(dev);
1132
1133 /* Make sure test of self->io.speed & speed change are atomic */
1134 spin_lock_irqsave(&self->lock, flags);
1135
1136 /* Check if we need to change the speed after this frame */
1137 speed = irda_get_next_speed(skb);
98b77773 1138 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1139 /* Check for empty frame */
1140 if (!skb->len) {
1141 /* Note : you should make sure that speed changes
1142 * are not going to corrupt any outgoing frame.
1143 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1144 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1145 spin_unlock_irqrestore(&self->lock, flags);
1146 dev_kfree_skb(skb);
1147 return 0;
98b77773
DT		 1148 }
1149
1150 self->new_speed = speed;
1da177e4 1151 }
527b6af4 1152
1da177e4
LT		 1153 memcpy(self->tx_buff.head, skb->data, skb->len);
1154
1155 self->tx_buff.len = skb->len;
1156 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1157
1158 mtt = irda_get_mtt(skb);
1da177e4
LT		 1159 if (mtt) {
1160 int bofs;
1161
527b6af4 1162 /*
1da177e4
LT		 1163 * Compute how many BOFs (STA or PA's) we need to waste the
1164 * min turn time given the speed of the link.
1165 */
1166 bofs = mtt * (self->io.speed / 1000) / 8000;
1167 if (bofs > 4095)
1168 bofs = 4095;
1169
80a90589 1170 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1171 } else {
1172 /* Transmit frame */
80a90589 1173 smsc_ircc_dma_xmit(self, 0);
1da177e4 1174 }
98b77773 1175
1da177e4
LT		 1176 spin_unlock_irqrestore(&self->lock, flags);
1177 dev_kfree_skb(skb);
1178
1179 return 0;
1180}
1181
1182/*
80a90589 1183 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1184 *
1185 * Transmit data using DMA
1186 *
1187 */
80a90589 1188static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1189{
80a90589 1190 int iobase = self->io.fir_base;
1da177e4
LT		 1191 u8 ctrl;
1192
1193 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1194#if 1
1195 /* Disable Rx */
1196 register_bank(iobase, 0);
98b77773 1197 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1198#endif
1199 register_bank(iobase, 1);
98b77773
DT		 1200 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1201 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1202
1203 self->io.direction = IO_XMIT;
1204
1205 /* Set BOF additional count for generating the min turn time */
1206 register_bank(iobase, 4);
98b77773
DT		 1207 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1208 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1209 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1210
1211 /* Set max Tx frame size */
98b77773
DT		 1212 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1213 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1214
1215 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1216
1da177e4
LT		 1217 /* Enable burst mode chip Tx DMA */
1218 register_bank(iobase, 1);
98b77773
DT		 1219 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1220 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1221
1222 /* Setup DMA controller (must be done after enabling chip DMA) */
1223 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1224 DMA_TX_MODE);
1225
1226 /* Enable interrupt */
1227
1228 register_bank(iobase, 0);
98b77773
DT		 1229 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1230 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1231
1da177e4 1232 /* Enable transmit */
98b77773 1233 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1234}
1235
1236/*
1237 * Function smsc_ircc_dma_xmit_complete (self)
1238 *
527b6af4 1239 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1240 * by the interrupt handler
1241 *
1242 */
80a90589 1243static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1244{
80a90589
DT		 1245 int iobase = self->io.fir_base;
1246
1da177e4
LT		 1247 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1248#if 0
1249 /* Disable Tx */
1250 register_bank(iobase, 0);
98b77773 1251 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1252#endif
80a90589
DT		 1253 register_bank(iobase, 1);
1254 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1255 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1256
1257 /* Check for underrun! */
1258 register_bank(iobase, 0);
98b77773 1259 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1da177e4
LT		 1260 self->stats.tx_errors++;
1261 self->stats.tx_fifo_errors++;
1262
1263 /* Reset error condition */
1264 register_bank(iobase, 0);
98b77773
DT		 1265 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1266 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1267 } else {
1268 self->stats.tx_packets++;
98b77773 1269 self->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1270 }
1271
1272 /* Check if it's time to change the speed */
1273 if (self->new_speed) {
527b6af4 1274 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1275 self->new_speed = 0;
1276 }
1277
1278 netif_wake_queue(self->netdev);
1279}
1280
1281/*
1282 * Function smsc_ircc_dma_receive(self)
1283 *
1284 * Get ready for receiving a frame. The device will initiate a DMA
1285 * if it starts to receive a frame.
1286 *
1287 */
80a90589 1288static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1289{
80a90589 1290 int iobase = self->io.fir_base;
1da177e4
LT		 1291#if 0
1292 /* Turn off chip DMA */
1293 register_bank(iobase, 1);
98b77773
DT		 1294 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1295 iobase + IRCC_SCE_CFGB);
1da177e4 1296#endif
527b6af4 1297
1da177e4
LT		 1298 /* Disable Tx */
1299 register_bank(iobase, 0);
98b77773 1300 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1301
1302 /* Turn off chip DMA */
1303 register_bank(iobase, 1);
98b77773
DT		 1304 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1305 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1306
1307 self->io.direction = IO_RECV;
1308 self->rx_buff.data = self->rx_buff.head;
1309
1310 /* Set max Rx frame size */
1311 register_bank(iobase, 4);
98b77773
DT		 1312 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1313 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1314
1315 /* Setup DMA controller */
1316 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1317 DMA_RX_MODE);
1318
1319 /* Enable burst mode chip Rx DMA */
1320 register_bank(iobase, 1);
98b77773
DT		 1321 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1322 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1323
1324 /* Enable interrupt */
1325 register_bank(iobase, 0);
98b77773
DT		 1326 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1327 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1328
1329 /* Enable receiver */
1330 register_bank(iobase, 0);
527b6af4 1331 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1332 iobase + IRCC_LCR_B);
527b6af4 1333
1da177e4
LT		 1334 return 0;
1335}
1336
1337/*
80a90589 1338 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1339 *
1340 * Finished with receiving frames
1341 *
1342 */
80a90589 1343static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1344{
1345 struct sk_buff *skb;
1346 int len, msgcnt, lsr;
80a90589 1347 int iobase = self->io.fir_base;
527b6af4 1348
1da177e4 1349 register_bank(iobase, 0);
527b6af4 1350
1da177e4
LT		 1351 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1352#if 0
1353 /* Disable Rx */
1354 register_bank(iobase, 0);
98b77773 1355 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1356#endif
1357 register_bank(iobase, 0);
98b77773
DT		 1358 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1359 lsr= inb(iobase + IRCC_LSR);
1360 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4
LT		 1361
1362 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1363 get_dma_residue(self->io.dma));
1364
1365 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1366
98b77773
DT		 1367 /* Look for errors */
1368 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1da177e4 1369 self->stats.rx_errors++;
98b77773
DT		 1370 if (lsr & IRCC_LSR_FRAME_ERROR)
1371 self->stats.rx_frame_errors++;
1372 if (lsr & IRCC_LSR_CRC_ERROR)
1373 self->stats.rx_crc_errors++;
1374 if (lsr & IRCC_LSR_SIZE_ERROR)
1375 self->stats.rx_length_errors++;
1376 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1377 self->stats.rx_length_errors++;
1da177e4
LT		 1378 return;
1379 }
98b77773 1380
1da177e4 1381 /* Remove CRC */
98b77773 1382 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1383
98b77773 1384 if (len < 2 || len > 2050) {
1da177e4
LT		 1385 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1386 return;
1387 }
1388 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1389
98b77773
DT		 1390 skb = dev_alloc_skb(len + 1);
1391 if (!skb) {
1da177e4
LT		 1392 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1393 __FUNCTION__);
1394 return;
527b6af4 1395 }
1da177e4 1396 /* Make sure IP header gets aligned */
527b6af4 1397 skb_reserve(skb, 1);
1da177e4
LT		 1398
1399 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1400 self->stats.rx_packets++;
1401 self->stats.rx_bytes += len;
1402
1403 skb->dev = self->netdev;
1404 skb->mac.raw = skb->data;
1405 skb->protocol = htons(ETH_P_IRDA);
1406 netif_rx(skb);
1407}
1408
1409/*
1410 * Function smsc_ircc_sir_receive (self)
1411 *
1412 * Receive one frame from the infrared port
1413 *
1414 */
527b6af4 1415static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1416{
1417 int boguscount = 0;
1418 int iobase;
1419
1420 IRDA_ASSERT(self != NULL, return;);
1421
1422 iobase = self->io.sir_base;
1423
527b6af4
DT		 1424 /*
1425 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1426 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1427 */
1428 do {
527b6af4 1429 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
98b77773 1430 inb(iobase + UART_RX));
1da177e4
LT		 1431
1432 /* Make sure we don't stay here to long */
1433 if (boguscount++ > 32) {
1434 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1435 break;
1436 }
98b77773 1437 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1438}
1439
1440
1441/*
1442 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1443 *
1444 * An interrupt from the chip has arrived. Time to do some work
1445 *
1446 */
1447static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1448{
1449 struct net_device *dev = (struct net_device *) dev_id;
1450 struct smsc_ircc_cb *self;
1451 int iobase, iir, lcra, lsr;
1452 irqreturn_t ret = IRQ_NONE;
1453
1454 if (dev == NULL) {
527b6af4 1455 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1da177e4
LT		 1456 driver_name, irq);
1457 goto irq_ret;
1458 }
da0841a0
DT		 1459
1460 self = netdev_priv(dev);
1da177e4
LT		 1461 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1462
1463 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1464 spin_lock(&self->lock);
1da177e4
LT		 1465
1466 /* Check if we should use the SIR interrupt handler */
98b77773 1467 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1468 ret = smsc_ircc_interrupt_sir(dev);
1469 goto irq_ret_unlock;
1470 }
1471
1472 iobase = self->io.fir_base;
1473
1474 register_bank(iobase, 0);
98b77773 1475 iir = inb(iobase + IRCC_IIR);
527b6af4 1476 if (iir == 0)
1da177e4
LT		 1477 goto irq_ret_unlock;
1478 ret = IRQ_HANDLED;
1479
1480 /* Disable interrupts */
98b77773
DT		 1481 outb(0, iobase + IRCC_IER);
1482 lcra = inb(iobase + IRCC_LCR_A);
1483 lsr = inb(iobase + IRCC_LSR);
527b6af4 1484
1da177e4
LT		 1485 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1486
1487 if (iir & IRCC_IIR_EOM) {
1488 if (self->io.direction == IO_RECV)
80a90589 1489 smsc_ircc_dma_receive_complete(self);
1da177e4 1490 else
80a90589 1491 smsc_ircc_dma_xmit_complete(self);
527b6af4 1492
80a90589 1493 smsc_ircc_dma_receive(self);
1da177e4
LT		 1494 }
1495
1496 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1497 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1498 }
1499
1500 /* Enable interrupts again */
1501
1502 register_bank(iobase, 0);
98b77773 1503 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1504
1505 irq_ret_unlock:
1506 spin_unlock(&self->lock);
1507 irq_ret:
1508 return ret;
1509}
1510
1511/*
1512 * Function irport_interrupt_sir (irq, dev_id, regs)
1513 *
1514 * Interrupt handler for SIR modes
1515 */
1516static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1517{
da0841a0 1518 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1519 int boguscount = 0;
1520 int iobase;
1521 int iir, lsr;
1522
1523 /* Already locked comming here in smsc_ircc_interrupt() */
1524 /*spin_lock(&self->lock);*/
1525
1526 iobase = self->io.sir_base;
1527
98b77773 1528 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1529 if (iir == 0)
1530 return IRQ_NONE;
1531 while (iir) {
1532 /* Clear interrupt */
98b77773 1533 lsr = inb(iobase + UART_LSR);
1da177e4 1534
527b6af4 1535 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1da177e4
LT		 1536 __FUNCTION__, iir, lsr, iobase);
1537
1538 switch (iir) {
1539 case UART_IIR_RLSI:
1540 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1541 break;
1542 case UART_IIR_RDI:
1543 /* Receive interrupt */
1544 smsc_ircc_sir_receive(self);
1545 break;
1546 case UART_IIR_THRI:
1547 if (lsr & UART_LSR_THRE)
1548 /* Transmitter ready for data */
1549 smsc_ircc_sir_write_wakeup(self);
1550 break;
1551 default:
1552 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1553 __FUNCTION__, iir);
1554 break;
527b6af4
DT		 1555 }
1556
1da177e4
LT		 1557 /* Make sure we don't stay here to long */
1558 if (boguscount++ > 100)
1559 break;
1560
527b6af4 1561 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1562 }
1563 /*spin_unlock(&self->lock);*/
1564 return IRQ_HANDLED;
1565}
1566
1567
1568#if 0 /* unused */
1569/*
1570 * Function ircc_is_receiving (self)
1571 *
1572 * Return TRUE is we are currently receiving a frame
1573 *
1574 */
1575static int ircc_is_receiving(struct smsc_ircc_cb *self)
1576{
1577 int status = FALSE;
1578 /* int iobase; */
1579
1580 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1581
1582 IRDA_ASSERT(self != NULL, return FALSE;);
1583
1584 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1585 get_dma_residue(self->io.dma));
1586
1587 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1588
1da177e4
LT		 1589 return status;
1590}
1591#endif /* unused */
1592
e812cb52
DT		 1593static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1594{
1595 int error;
1596
1597 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1598 self->netdev->name, self->netdev);
1599 if (error)
1600 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1601 __FUNCTION__, self->io.irq, error);
1602
1603 return error;
1604}
1605
1606static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1607{
1608 unsigned long flags;
1609
1610 spin_lock_irqsave(&self->lock, flags);
1611
1612 self->io.speed = 0;
1613 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1614
1615 spin_unlock_irqrestore(&self->lock, flags);
1616}
1617
1618static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1619{
1620 int iobase = self->io.fir_base;
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(&self->lock, flags);
1624
1625 register_bank(iobase, 0);
1626 outb(0, iobase + IRCC_IER);
1627 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1628 outb(0x00, iobase + IRCC_MASTER);
1629
1630 spin_unlock_irqrestore(&self->lock, flags);
1631}
1632
1da177e4
LT		 1633
1634/*
1635 * Function smsc_ircc_net_open (dev)
1636 *
1637 * Start the device
1638 *
1639 */
1640static int smsc_ircc_net_open(struct net_device *dev)
1641{
1642 struct smsc_ircc_cb *self;
1da177e4 1643 char hwname[16];
1da177e4
LT		 1644
1645 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1646
1da177e4 1647 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1648 self = netdev_priv(dev);
1da177e4 1649 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1650
e812cb52
DT		 1651 if (self->io.suspended) {
1652 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1653 return -EAGAIN;
1654 }
1655
527b6af4 1656 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1657 (void *) dev)) {
1658 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1659 __FUNCTION__, self->io.irq);
1660 return -EAGAIN;
1661 }
1662
e812cb52 1663 smsc_ircc_start_interrupts(self);
527b6af4 1664
1da177e4
LT		 1665 /* Give self a hardware name */
1666 /* It would be cool to offer the chip revision here - Jean II */
1667 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1668
527b6af4 1669 /*
1da177e4 1670 * Open new IrLAP layer instance, now that everything should be
527b6af4 1671 * initialized properly
1da177e4
LT		 1672 */
1673 self->irlap = irlap_open(dev, &self->qos, hwname);
1674
1675 /*
1676 * Always allocate the DMA channel after the IRQ,
1677 * and clean up on failure.
1678 */
1679 if (request_dma(self->io.dma, dev->name)) {
1680 smsc_ircc_net_close(dev);
1681
1682 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1683 __FUNCTION__, self->io.dma);
1684 return -EAGAIN;
1685 }
527b6af4 1686
1da177e4
LT		 1687 netif_start_queue(dev);
1688
1689 return 0;
1690}
1691
1692/*
1693 * Function smsc_ircc_net_close (dev)
1694 *
1695 * Stop the device
1696 *
1697 */
1698static int smsc_ircc_net_close(struct net_device *dev)
1699{
1700 struct smsc_ircc_cb *self;
1da177e4
LT		 1701
1702 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1703
1da177e4 1704 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1705 self = netdev_priv(dev);
1da177e4 1706 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1707
1da177e4
LT		 1708 /* Stop device */
1709 netif_stop_queue(dev);
527b6af4 1710
1da177e4
LT		 1711 /* Stop and remove instance of IrLAP */
1712 if (self->irlap)
1713 irlap_close(self->irlap);
1714 self->irlap = NULL;
1715
e812cb52
DT		 1716 smsc_ircc_stop_interrupts(self);
1717
1718 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1719 if (!self->io.suspended)
1720 free_irq(self->io.irq, dev);
1721
1da177e4 1722 disable_dma(self->io.dma);
1da177e4
LT		 1723 free_dma(self->io.dma);
1724
1725 return 0;
1726}
1727
3ae5eaec 1728static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1729{
3ae5eaec 1730 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1731
9480e307 1732 if (!self->io.suspended) {
e812cb52
DT		 1733 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1734
1735 rtnl_lock();
1736 if (netif_running(self->netdev)) {
1737 netif_device_detach(self->netdev);
1738 smsc_ircc_stop_interrupts(self);
1739 free_irq(self->io.irq, self->netdev);
1740 disable_dma(self->io.dma);
1741 }
98b77773 1742 self->io.suspended = 1;
e812cb52 1743 rtnl_unlock();
98b77773 1744 }
6bb3b2cd
DT		 1745
1746 return 0;
1da177e4
LT		 1747}
1748
3ae5eaec 1749static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1750{
3ae5eaec 1751 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1752
9480e307 1753 if (self->io.suspended) {
e812cb52
DT		 1754 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1755
1756 rtnl_lock();
1757 smsc_ircc_init_chip(self);
1758 if (netif_running(self->netdev)) {
1759 if (smsc_ircc_request_irq(self)) {
1760 /*
1761 * Don't fail resume process, just kill this
1762 * network interface
1763 */
1764 unregister_netdevice(self->netdev);
1765 } else {
1766 enable_dma(self->io.dma);
1767 smsc_ircc_start_interrupts(self);
1768 netif_device_attach(self->netdev);
1769 }
1770 }
6bb3b2cd 1771 self->io.suspended = 0;
e812cb52 1772 rtnl_unlock();
6bb3b2cd 1773 }
1da177e4
LT		 1774 return 0;
1775}
1776
1777/*
1778 * Function smsc_ircc_close (self)
1779 *
1780 * Close driver instance
1781 *
1782 */
1783static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1784{
1da177e4
LT		 1785 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1786
1787 IRDA_ASSERT(self != NULL, return -1;);
1788
6bb3b2cd 1789 platform_device_unregister(self->pldev);
1da177e4
LT		 1790
1791 /* Remove netdevice */
1792 unregister_netdev(self->netdev);
1793
e812cb52 1794 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1795
1796 /* Release the PORTS that this driver is using */
1797 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1798 self->io.fir_base);
1799
1800 release_region(self->io.fir_base, self->io.fir_ext);
1801
527b6af4 1802 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1da177e4
LT		 1803 self->io.sir_base);
1804
1805 release_region(self->io.sir_base, self->io.sir_ext);
1806
1807 if (self->tx_buff.head)
1808 dma_free_coherent(NULL, self->tx_buff.truesize,
1809 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1810
1da177e4
LT		 1811 if (self->rx_buff.head)
1812 dma_free_coherent(NULL, self->rx_buff.truesize,
1813 self->rx_buff.head, self->rx_buff_dma);
1814
1815 free_netdev(self->netdev);
1816
1817 return 0;
1818}
1819
1820static void __exit smsc_ircc_cleanup(void)
1821{
1822 int i;
1823
1824 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1825
98b77773 1826 for (i = 0; i < 2; i++) {
1da177e4
LT		 1827 if (dev_self[i])
1828 smsc_ircc_close(dev_self[i]);
1829 }
6bb3b2cd 1830
3ae5eaec 1831 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1832}
1833
1834/*
1835 * Start SIR operations
1836 *
1837 * This function *must* be called with spinlock held, because it may
1838 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1839 */
1840void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1841{
1842 struct net_device *dev;
1843 int fir_base, sir_base;
1844
1845 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1846
527b6af4 1847 IRDA_ASSERT(self != NULL, return;);
98b77773 1848 dev = self->netdev;
527b6af4 1849 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1850 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1851
1852 fir_base = self->io.fir_base;
1853 sir_base = self->io.sir_base;
1854
1855 /* Reset everything */
98b77773 1856 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1857
1858 #if SMSC_IRCC2_C_SIR_STOP
1859 /*smsc_ircc_sir_stop(self);*/
1860 #endif
1861
1862 register_bank(fir_base, 1);
98b77773 1863 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1864
1865 /* Initialize UART */
98b77773
DT		 1866 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1867 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1868
1da177e4 1869 /* Turn on interrups */
98b77773 1870 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4
LT		 1871
1872 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1873
98b77773 1874 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1875}
1876
1877#if SMSC_IRCC2_C_SIR_STOP
1878void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1879{
1880 int iobase;
1881
1882 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1883 iobase = self->io.sir_base;
1884
1885 /* Reset UART */
98b77773 1886 outb(0, iobase + UART_MCR);
527b6af4 1887
1da177e4 1888 /* Turn off interrupts */
98b77773 1889 outb(0, iobase + UART_IER);
1da177e4
LT		 1890}
1891#endif
1892
1893/*
1894 * Function smsc_sir_write_wakeup (self)
1895 *
1896 * Called by the SIR interrupt handler when there's room for more data.
1897 * If we have more packets to send, we send them here.
1898 *
1899 */
1900static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1901{
1902 int actual = 0;
1903 int iobase;
1904 int fcr;
1905
1906 IRDA_ASSERT(self != NULL, return;);
1907
1908 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1909
1910 iobase = self->io.sir_base;
1911
1912 /* Finished with frame? */
1913 if (self->tx_buff.len > 0) {
1914 /* Write data left in transmit buffer */
527b6af4 1915 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1916 self->tx_buff.data, self->tx_buff.len);
1917 self->tx_buff.data += actual;
1918 self->tx_buff.len -= actual;
1919 } else {
527b6af4 1920
1da177e4 1921 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1922
1923 /*
1924 * Now serial buffer is almost free & we can start
1da177e4
LT		 1925 * transmission of another packet. But first we must check
1926 * if we need to change the speed of the hardware
1927 */
1928 if (self->new_speed) {
1929 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1930 __FUNCTION__, self->new_speed);
1931 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1932 smsc_ircc_change_speed(self, self->new_speed);
1933 self->new_speed = 0;
1934 } else {
1935 /* Tell network layer that we want more frames */
1936 netif_wake_queue(self->netdev);
1937 }
1938 self->stats.tx_packets++;
1939
98b77773
DT		 1940 if (self->io.speed <= 115200) {
1941 /*
1942 * Reset Rx FIFO to make sure that all reflected transmit data
1943 * is discarded. This is needed for half duplex operation
1944 */
1945 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1946 fcr |= self->io.speed < 38400 ?
1947 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 1948
98b77773 1949 outb(fcr, iobase + UART_FCR);
1da177e4 1950
98b77773
DT		 1951 /* Turn on receive interrupts */
1952 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 1953 }
1954 }
1955}
1956
1957/*
1958 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1959 *
1960 * Fill Tx FIFO with transmit data
1961 *
1962 */
1963static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1964{
1965 int actual = 0;
527b6af4 1966
1da177e4 1967 /* Tx FIFO should be empty! */
98b77773 1968 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1da177e4
LT		 1969 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1970 return 0;
1971 }
527b6af4 1972
1da177e4 1973 /* Fill FIFO with current frame */
98b77773 1974 while (fifo_size-- > 0 && actual < len) {
1da177e4 1975 /* Transmit next byte */
98b77773 1976 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 1977 actual++;
1978 }
1979 return actual;
1980}
1981
1982/*
1983 * Function smsc_ircc_is_receiving (self)
1984 *
1985 * Returns true is we are currently receiving data
1986 *
1987 */
1988static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1989{
1990 return (self->rx_buff.state != OUTSIDE_FRAME);
1991}
1992
1993
1994/*
1995 * Function smsc_ircc_probe_transceiver(self)
1996 *
1997 * Tries to find the used Transceiver
1998 *
1999 */
2000static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2001{
2002 unsigned int i;
527b6af4 2003
1da177e4 2004 IRDA_ASSERT(self != NULL, return;);
527b6af4 2005
98b77773
DT		 2006 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2007 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 2008 IRDA_MESSAGE(" %s transceiver found\n",
2009 smsc_transceivers[i].name);
98b77773 2010 self->transceiver= i + 1;
1da177e4
LT		 2011 return;
2012 }
98b77773 2013
1da177e4
LT		 2014 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2015 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2016
98b77773 2017 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2018}
2019
2020
2021/*
2022 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2023 *
2024 * Set the transceiver according to the speed
2025 *
2026 */
2027static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2028{
2029 unsigned int trx;
527b6af4 2030
1da177e4 2031 trx = self->transceiver;
98b77773
DT		 2032 if (trx > 0)
2033 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2034}
2035
2036/*
2037 * Function smsc_ircc_wait_hw_transmitter_finish ()
2038 *
2039 * Wait for the real end of HW transmission
2040 *
2041 * The UART is a strict FIFO, and we get called only when we have finished
2042 * pushing data to the FIFO, so the maximum amount of time we must wait
2043 * is only for the FIFO to drain out.
2044 *
2045 * We use a simple calibrated loop. We may need to adjust the loop
2046 * delay (udelay) to balance I/O traffic and latency. And we also need to
2047 * adjust the maximum timeout.
2048 * It would probably be better to wait for the proper interrupt,
2049 * but it doesn't seem to be available.
2050 *
2051 * We can't use jiffies or kernel timers because :
2052 * 1) We are called from the interrupt handler, which disable softirqs,
2053 * so jiffies won't be increased
2054 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2055 * want to wait that long to detect stuck hardware.
2056 * Jean II
2057 */
2058
2059static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2060{
98b77773 2061 int iobase = self->io.sir_base;
1da177e4 2062 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2063
1da177e4 2064 /* Calibrated busy loop */
98b77773 2065 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2066 udelay(1);
2067
98b77773 2068 if (count == 0)
1da177e4
LT		 2069 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2070}
2071
2072
2073/* PROBING
2074 *
2075 *
2076 */
2077
2078static int __init smsc_ircc_look_for_chips(void)
2079{
b6158d23 2080 struct smsc_chip_address *address;
98b77773 2081 char *type;
1da177e4 2082 unsigned int cfg_base, found;
527b6af4 2083
1da177e4
LT		 2084 found = 0;
2085 address = possible_addresses;
527b6af4 2086
98b77773 2087 while (address->cfg_base) {
1da177e4 2088 cfg_base = address->cfg_base;
527b6af4 2089
1da177e4 2090 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
527b6af4 2091
98b77773 2092 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2093 type = "FDC";
98b77773
DT		 2094 if (address->type & SMSCSIO_TYPE_FLAT)
2095 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2096 found++;
2097
2098 if (address->type & SMSCSIO_TYPE_PAGED)
2099 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2100 found++;
1da177e4 2101 }
98b77773 2102 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2103 type = "LPC";
98b77773
DT		 2104 if (address->type & SMSCSIO_TYPE_FLAT)
2105 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2106 found++;
2107
2108 if (address->type & SMSCSIO_TYPE_PAGED)
2109 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2110 found++;
1da177e4
LT		 2111 }
2112 address++;
2113 }
2114 return found;
527b6af4 2115}
1da177e4
LT		 2116
2117/*
2118 * Function smsc_superio_flat (chip, base, type)
2119 *
2120 * Try to get configuration of a smc SuperIO chip with flat register model
2121 *
2122 */
b6158d23 2123static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2124{
2125 unsigned short firbase, sirbase;
2126 u8 mode, dma, irq;
2127 int ret = -ENODEV;
2128
2129 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2130
98b77773 2131 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2132 return ret;
2133
2134 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2135 mode = inb(cfgbase + 1);
527b6af4 2136
1da177e4 2137 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
527b6af4 2138
98b77773 2139 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
1da177e4
LT		 2140 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2141
2142 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2143 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2144
527b6af4 2145 /* FIR iobase */
1da177e4 2146 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2147 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2148
2149 /* DMA */
2150 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2151 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2152
1da177e4
LT		 2153 /* IRQ */
2154 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2155 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4
LT		 2156
2157 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2158
98b77773
DT		 2159 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2160 ret = 0;
527b6af4 2161
1da177e4
LT		 2162 /* Exit configuration */
2163 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2164
2165 return ret;
2166}
2167
2168/*
2169 * Function smsc_superio_paged (chip, base, type)
2170 *
2171 * Try to get configuration of a smc SuperIO chip with paged register model
2172 *
2173 */
b6158d23 2174static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2175{
2176 unsigned short fir_io, sir_io;
2177 int ret = -ENODEV;
527b6af4 2178
1da177e4
LT		 2179 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2180
98b77773 2181 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2182 return ret;
527b6af4 2183
1da177e4
LT		 2184 /* Select logical device (UART2) */
2185 outb(0x07, cfg_base);
2186 outb(0x05, cfg_base + 1);
527b6af4 2187
1da177e4
LT		 2188 /* SIR iobase */
2189 outb(0x60, cfg_base);
98b77773 2190 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2191 outb(0x61, cfg_base);
2192 sir_io |= inb(cfg_base + 1);
527b6af4 2193
1da177e4
LT		 2194 /* Read FIR base */
2195 outb(0x62, cfg_base);
2196 fir_io = inb(cfg_base + 1) << 8;
2197 outb(0x63, cfg_base);
2198 fir_io |= inb(cfg_base + 1);
2199 outb(0x2b, cfg_base); /* ??? */
2200
98b77773
DT		 2201 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2202 ret = 0;
527b6af4 2203
1da177e4
LT		 2204 /* Exit configuration */
2205 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2206
2207 return ret;
2208}
2209
2210
98b77773 2211static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4
LT		 2212{
2213 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2214
2215 outb(reg, cfg_base);
98b77773 2216 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2217}
2218
b6158d23 2219static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2220{
98b77773 2221 u8 devid, xdevid, rev;
1da177e4
LT		 2222
2223 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2224
2225 /* Leave configuration */
2226
2227 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2228
2229 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2230 return NULL;
2231
2232 outb(reg, cfg_base);
2233
98b77773 2234 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2235
2236 /* Enter configuration */
2237
2238 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2239
2240 #if 0
2241 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2242 return NULL;
2243 #endif
527b6af4 2244
1da177e4
LT		 2245 /* probe device ID */
2246
98b77773 2247 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2248 return NULL;
2249
98b77773 2250 devid = inb(cfg_base + 1);
527b6af4 2251
98b77773 2252 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2253 return NULL;
2254
2255 /* probe revision ID */
2256
98b77773 2257 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2258 return NULL;
2259
98b77773 2260 rev = inb(cfg_base + 1);
1da177e4 2261
98b77773 2262 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2263 return NULL;
2264
98b77773 2265 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2266 return NULL;
2267
2268 /* Check for expected device ID; are there others? */
2269
98b77773 2270 while (chip->devid != devid) {
1da177e4
LT		 2271
2272 chip++;
2273
98b77773 2274 if (chip->name == NULL)
1da177e4
LT		 2275 return NULL;
2276 }
2277
98b77773
DT		 2278 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2279 devid, rev, cfg_base, type, chip->name);
1da177e4 2280
98b77773 2281 if (chip->rev > rev) {
527b6af4 2282 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2283 return NULL;
2284 }
527b6af4 2285
98b77773 2286 if (chip->flags & NoIRDA)
1da177e4
LT		 2287 IRDA_MESSAGE("chipset does not support IRDA\n");
2288
2289 return chip;
2290}
2291
2292static int __init smsc_superio_fdc(unsigned short cfg_base)
2293{
2294 int ret = -1;
2295
2296 if (!request_region(cfg_base, 2, driver_name)) {
2297 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2298 __FUNCTION__, cfg_base);
2299 } else {
98b77773
DT		 2300 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2301 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2302 ret = 0;
2303
2304 release_region(cfg_base, 2);
2305 }
2306
2307 return ret;
2308}
2309
2310static int __init smsc_superio_lpc(unsigned short cfg_base)
2311{
2312 int ret = -1;
2313
2314 if (!request_region(cfg_base, 2, driver_name)) {
2315 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2316 __FUNCTION__, cfg_base);
2317 } else {
98b77773
DT		 2318 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2319 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2320 ret = 0;
98b77773 2321
1da177e4
LT		 2322 release_region(cfg_base, 2);
2323 }
2324 return ret;
2325}
2326
c1e14a6e
LW		 2327/*
2328 * Look for some specific subsystem setups that need
2329 * pre-configuration not properly done by the BIOS (especially laptops)
2330 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2331 * and tosh2450-smcinit.c. The table lists the device entries
08d09997
LW		 2332 * for ISA bridges with an LPC (Low Pin Count) controller which
2333 * handles the communication with the SMSC device. After the LPC
2334 * controller is initialized through PCI, the SMSC device is initialized
2335 * through a dedicated port in the ISA port-mapped I/O area, this latter
2336 * area is used to configure the SMSC device with default
2337 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2338 * used different sets of parameters and different control port
2339 * addresses making a subsystem device table necessary.
c1e14a6e
LW		 2340 */
2341#ifdef CONFIG_PCI
2342#define PCIID_VENDOR_INTEL 0x8086
2343#define PCIID_VENDOR_ALI 0x10b9
2344static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __devinitdata = {
2345 {
2346 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2347 .device = 0x24cc,
2348 .subvendor = 0x103c,
2349 .subdevice = 0x088c,
08d09997
LW		 2350 /* Quite certain these are the same for nc8000 as for nc6000 */
2351 .sir_io = 0x02f8,
c1e14a6e 2352 .fir_io = 0x0130,
08d09997 2353 .fir_irq = 0x05,
c1e14a6e
LW		 2354 .fir_dma = 0x03,
2355 .cfg_base = 0x004e,
2356 .preconfigure = preconfigure_through_82801,
2357 .name = "HP nc8000",
2358 },
2359 {
2360 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2361 .device = 0x24cc,
2362 .subvendor = 0x103c,
2363 .subdevice = 0x0890,
2364 .sir_io = 0x02f8,
2365 .fir_io = 0x0130,
08d09997 2366 .fir_irq = 0x05,
c1e14a6e
LW		 2367 .fir_dma = 0x03,
2368 .cfg_base = 0x004e,
2369 .preconfigure = preconfigure_through_82801,
2370 .name = "HP nc6000",
2371 },
2372 {
08d09997
LW		 2373 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2374 .vendor = PCIID_VENDOR_INTEL,
c1e14a6e
LW		 2375 .device = 0x24c0,
2376 .subvendor = 0x1179,
08d09997 2377 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2378 .sir_io = 0x03f8,
2379 .fir_io = 0x0130,
2380 .fir_irq = 0x07,
2381 .fir_dma = 0x01,
2382 .cfg_base = 0x002e,
2383 .preconfigure = preconfigure_through_82801,
08d09997 2384 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
c1e14a6e
LW		 2385 },
2386 {
2387 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
08d09997 2388 .device = 0x248c,
c1e14a6e 2389 .subvendor = 0x1179,
08d09997 2390 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2391 .sir_io = 0x03f8,
2392 .fir_io = 0x0130,
2393 .fir_irq = 0x03,
2394 .fir_dma = 0x03,
2395 .cfg_base = 0x002e,
2396 .preconfigure = preconfigure_through_82801,
08d09997 2397 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
c1e14a6e
LW		 2398 },
2399 {
08d09997
LW		 2400 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2401 .vendor = PCIID_VENDOR_INTEL,
2402 .device = 0x24cc,
2403 .subvendor = 0x1179,
2404 .subdevice = 0xffff, /* 0xffff is "any" */
2405 .sir_io = 0x03f8,
2406 .fir_io = 0x0130,
2407 .fir_irq = 0x03,
2408 .fir_dma = 0x03,
2409 .cfg_base = 0x002e,
2410 .preconfigure = preconfigure_through_82801,
2411 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2412 },
2413 {
2414 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2415 .vendor = PCIID_VENDOR_ALI,
c1e14a6e
LW		 2416 .device = 0x1533,
2417 .subvendor = 0x1179,
08d09997 2418 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2419 .sir_io = 0x02e8,
2420 .fir_io = 0x02f8,
2421 .fir_irq = 0x07,
2422 .fir_dma = 0x03,
2423 .cfg_base = 0x002e,
2424 .preconfigure = preconfigure_through_ali,
08d09997 2425 .name = "Toshiba laptop with ALi ISA bridge",
c1e14a6e
LW		 2426 },
2427 { } // Terminator
2428};
2429
2430
2431/*
08d09997
LW		 2432 * This sets up the basic SMSC parameters
2433 * (FIR port, SIR port, FIR DMA, FIR IRQ)
c1e14a6e
LW		 2434 * through the chip configuration port.
2435 */
08d09997
LW		 2436static int __init preconfigure_smsc_chip(struct
2437 smsc_ircc_subsystem_configuration
2438 *conf)
c1e14a6e
LW		 2439{
2440 unsigned short iobase = conf->cfg_base;
2441 unsigned char tmpbyte;
2442
2443 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2444 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2445 tmpbyte = inb(iobase +1); // Read device ID
08d09997
LW		 2446 IRDA_DEBUG(0,
2447 "Detected Chip id: 0x%02x, setting up registers...\n",
2448 tmpbyte);
c1e14a6e
LW		 2449
2450 /* Disable UART1 and set up SIR I/O port */
2451 outb(0x24, iobase); // select CR24 - UART1 base addr
2452 outb(0x00, iobase + 1); // disable UART1
2453 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2454 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2455 tmpbyte = inb(iobase + 1);
2456 if (tmpbyte != (conf->sir_io >> 2) ) {
2457 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
08d09997 2458 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
c1e14a6e
LW		 2459 return -ENXIO;
2460 }
2461
2462 /* Set up FIR IRQ channel for UART2 */
2463 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2464 tmpbyte = inb(iobase + 1);
2465 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2466 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2467 outb(tmpbyte, iobase + 1);
2468 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2469 if (tmpbyte != conf->fir_irq) {
2470 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2471 return -ENXIO;
2472 }
2473
2474 /* Set up FIR I/O port */
2475 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2476 outb((conf->fir_io >> 3), iobase + 1);
2477 tmpbyte = inb(iobase + 1);
2478 if (tmpbyte != (conf->fir_io >> 3) ) {
2479 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2480 return -ENXIO;
2481 }
2482
2483 /* Set up FIR DMA channel */
2484 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2485 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2486 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2487 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2488 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2489 return -ENXIO;
2490 }
2491
2492 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2493 tmpbyte = inb(iobase + 1);
08d09997
LW		 2494 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2495 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
c1e14a6e
LW		 2496 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2497
2498 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2499 tmpbyte = inb(iobase + 1);
2500 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2501
2502 /* This one was not part of tosh1800 */
2503 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2504 tmpbyte = inb(iobase + 1);
2505 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2506
2507 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2508 tmpbyte = inb(iobase + 1);
2509 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2510
2511 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2512 tmpbyte = inb(iobase + 1);
2513 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2514
2515 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2516
2517 return 0;
2518}
2519
08d09997 2520/* 82801CAM generic registers */
c1e14a6e
LW		 2521#define VID 0x00
2522#define DID 0x02
08d09997
LW		 2523#define PIRQ_A_D_ROUT 0x60
2524#define SIRQ_CNTL 0x64
2525#define PIRQ_E_H_ROUT 0x68
c1e14a6e 2526#define PCI_DMA_C 0x90
08d09997 2527/* LPC-specific registers */
c1e14a6e 2528#define COM_DEC 0xe0
08d09997 2529#define GEN1_DEC 0xe4
c1e14a6e
LW		 2530#define LPC_EN 0xe6
2531#define GEN2_DEC 0xec
2532/*
08d09997
LW		 2533 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2534 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2535 * They all work the same way!
c1e14a6e
LW		 2536 */
2537static int __init preconfigure_through_82801(struct pci_dev *dev,
08d09997
LW		 2538 struct
2539 smsc_ircc_subsystem_configuration
2540 *conf)
c1e14a6e
LW		 2541{
2542 unsigned short tmpword;
08d09997 2543 unsigned char tmpbyte;
c1e14a6e 2544
08d09997
LW		 2545 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2546 /*
2547 * Select the range for the COMA COM port (SIR)
2548 * Register COM_DEC:
2549 * Bit 7: reserved
2550 * Bit 6-4, COMB decode range
2551 * Bit 3: reserved
2552 * Bit 2-0, COMA decode range
2553 *
2554 * Decode ranges:
2555 * 000 = 0x3f8-0x3ff (COM1)
2556 * 001 = 0x2f8-0x2ff (COM2)
2557 * 010 = 0x220-0x227
2558 * 011 = 0x228-0x22f
2559 * 100 = 0x238-0x23f
2560 * 101 = 0x2e8-0x2ef (COM4)
2561 * 110 = 0x338-0x33f
2562 * 111 = 0x3e8-0x3ef (COM3)
2563 */
2564 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2565 tmpbyte &= 0xf8; /* mask COMA bits */
2566 switch(conf->sir_io) {
2567 case 0x3f8:
2568 tmpbyte |= 0x00;
2569 break;
2570 case 0x2f8:
2571 tmpbyte |= 0x01;
2572 break;
2573 case 0x220:
2574 tmpbyte |= 0x02;
2575 break;
2576 case 0x228:
2577 tmpbyte |= 0x03;
2578 break;
2579 case 0x238:
2580 tmpbyte |= 0x04;
2581 break;
2582 case 0x2e8:
2583 tmpbyte |= 0x05;
2584 break;
2585 case 0x338:
2586 tmpbyte |= 0x06;
2587 break;
2588 case 0x3e8:
2589 tmpbyte |= 0x07;
2590 break;
2591 default:
2592 tmpbyte |= 0x01; /* COM2 default */
2593 }
2594 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2595 pci_write_config_byte(dev, COM_DEC, tmpbyte);
c1e14a6e 2596
08d09997
LW		 2597 /* Enable Low Pin Count interface */
2598 pci_read_config_word(dev, LPC_EN, &tmpword);
2599 /* These seem to be set up at all times,
2600 * just make sure it is properly set.
2601 */
2602 switch(conf->cfg_base) {
2603 case 0x04e:
2604 tmpword |= 0x2000;
2605 break;
2606 case 0x02e:
2607 tmpword |= 0x1000;
2608 break;
2609 case 0x062:
2610 tmpword |= 0x0800;
2611 break;
2612 case 0x060:
2613 tmpword |= 0x0400;
2614 break;
2615 default:
2616 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2617 conf->cfg_base);
2618 break;
2619 }
2620 tmpword &= 0xfffd; /* disable LPC COMB */
2621 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2622 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
c1e14a6e
LW		 2623 pci_write_config_word(dev, LPC_EN, tmpword);
2624
08d09997
LW		 2625 /*
2626 * Configure LPC DMA channel
2627 * PCI_DMA_C bits:
2628 * Bit 15-14: DMA channel 7 select
2629 * Bit 13-12: DMA channel 6 select
2630 * Bit 11-10: DMA channel 5 select
2631 * Bit 9-8: Reserved
2632 * Bit 7-6: DMA channel 3 select
2633 * Bit 5-4: DMA channel 2 select
2634 * Bit 3-2: DMA channel 1 select
2635 * Bit 1-0: DMA channel 0 select
2636 * 00 = Reserved value
2637 * 01 = PC/PCI DMA
2638 * 10 = Reserved value
2639 * 11 = LPC I/F DMA
2640 */
2641 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2642 switch(conf->fir_dma) {
2643 case 0x07:
2644 tmpword |= 0xc000;
2645 break;
2646 case 0x06:
2647 tmpword |= 0x3000;
2648 break;
2649 case 0x05:
2650 tmpword |= 0x0c00;
2651 break;
2652 case 0x03:
2653 tmpword |= 0x00c0;
2654 break;
2655 case 0x02:
2656 tmpword |= 0x0030;
2657 break;
2658 case 0x01:
2659 tmpword |= 0x000c;
2660 break;
2661 case 0x00:
2662 tmpword |= 0x0003;
2663 break;
2664 default:
2665 break; /* do not change settings */
2666 }
2667 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2668 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2669
2670 /*
2671 * GEN2_DEC bits:
2672 * Bit 15-4: Generic I/O range
2673 * Bit 3-1: reserved (read as 0)
2674 * Bit 0: enable GEN2 range on LPC I/F
2675 */
2676 tmpword = conf->fir_io & 0xfff8;
2677 tmpword |= 0x0001;
2678 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2679 pci_write_config_word(dev, GEN2_DEC, tmpword);
c1e14a6e
LW		 2680
2681 /* Pre-configure chip */
08d09997
LW		 2682 return preconfigure_smsc_chip(conf);
2683}
c1e14a6e 2684
08d09997
LW		 2685/*
2686 * Pre-configure a certain port on the ALi 1533 bridge.
2687 * This is based on reverse-engineering since ALi does not
2688 * provide any data sheet for the 1533 chip.
2689 */
2690static void __init preconfigure_ali_port(struct pci_dev *dev,
2691 unsigned short port)
2692{
2693 unsigned char reg;
2694 /* These bits obviously control the different ports */
2695 unsigned char mask;
2696 unsigned char tmpbyte;
2697
2698 switch(port) {
2699 case 0x0130:
2700 case 0x0178:
2701 reg = 0xb0;
2702 mask = 0x80;
2703 break;
2704 case 0x03f8:
2705 reg = 0xb4;
2706 mask = 0x80;
2707 break;
2708 case 0x02f8:
2709 reg = 0xb4;
2710 mask = 0x30;
2711 break;
2712 case 0x02e8:
2713 reg = 0xb4;
2714 mask = 0x08;
2715 break;
2716 default:
2717 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2718 return;
2719 }
2720
2721 pci_read_config_byte(dev, reg, &tmpbyte);
2722 /* Turn on the right bits */
2723 tmpbyte |= mask;
2724 pci_write_config_byte(dev, reg, tmpbyte);
2725 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2726 return;
c1e14a6e
LW		 2727}
2728
2729static int __init preconfigure_through_ali(struct pci_dev *dev,
08d09997
LW		 2730 struct
2731 smsc_ircc_subsystem_configuration
2732 *conf)
c1e14a6e 2733{
08d09997
LW		 2734 /* Configure the two ports on the ALi 1533 */
2735 preconfigure_ali_port(dev, conf->sir_io);
2736 preconfigure_ali_port(dev, conf->fir_io);
2737
2738 /* Pre-configure chip */
2739 return preconfigure_smsc_chip(conf);
c1e14a6e
LW		 2740}
2741
2742static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2743 unsigned short ircc_fir,
2744 unsigned short ircc_sir,
2745 unsigned char ircc_dma,
2746 unsigned char ircc_irq)
2747{
2748 struct pci_dev *dev = NULL;
2749 unsigned short ss_vendor = 0x0000;
2750 unsigned short ss_device = 0x0000;
2751 int ret = 0;
2752
2753 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2754
2755 while (dev != NULL) {
2756 struct smsc_ircc_subsystem_configuration *conf;
2757
2758 /*
08d09997
LW		 2759 * Cache the subsystem vendor/device:
2760 * some manufacturers fail to set this for all components,
2761 * so we save it in case there is just 0x0000 0x0000 on the
2762 * device we want to check.
c1e14a6e
LW		 2763 */
2764 if (dev->subsystem_vendor != 0x0000U) {
2765 ss_vendor = dev->subsystem_vendor;
2766 ss_device = dev->subsystem_device;
2767 }
2768 conf = subsystem_configurations;
2769 for( ; conf->subvendor; conf++) {
2770 if(conf->vendor == dev->vendor &&
2771 conf->device == dev->device &&
08d09997
LW		 2772 conf->subvendor == ss_vendor &&
2773 /* Sometimes these are cached values */
2774 (conf->subdevice == ss_device ||
2775 conf->subdevice == 0xffff)) {
2776 struct smsc_ircc_subsystem_configuration
2777 tmpconf;
c1e14a6e 2778
08d09997
LW		 2779 memcpy(&tmpconf, conf,
2780 sizeof(struct smsc_ircc_subsystem_configuration));
c1e14a6e 2781
08d09997
LW		 2782 /*
2783 * Override the default values with anything
2784 * passed in as parameter
2785 */
c1e14a6e
LW		 2786 if (ircc_cfg != 0)
2787 tmpconf.cfg_base = ircc_cfg;
2788 if (ircc_fir != 0)
2789 tmpconf.fir_io = ircc_fir;
2790 if (ircc_sir != 0)
2791 tmpconf.sir_io = ircc_sir;
2792 if (ircc_dma != 0xff)
2793 tmpconf.fir_dma = ircc_dma;
2794 if (ircc_irq != 0xff)
2795 tmpconf.fir_irq = ircc_irq;
2796
2797 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2798 if (conf->preconfigure)
2799 ret = conf->preconfigure(dev, &tmpconf);
2800 else
2801 ret = -ENODEV;
2802 }
2803 }
2804 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2805 }
2806
2807 return ret;
2808}
2809#endif // CONFIG_PCI
2810
1da177e4
LT		 2811/************************************************
2812 *
2813 * Transceivers specific functions
2814 *
2815 ************************************************/
2816
2817
2818/*
2819 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2820 *
2821 * Program transceiver through smsc-ircc ATC circuitry
2822 *
2823 */
2824
2825static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2826{
2827 unsigned long jiffies_now, jiffies_timeout;
98b77773 2828 u8 val;
527b6af4 2829
98b77773
DT		 2830 jiffies_now = jiffies;
2831 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2832
1da177e4
LT		 2833 /* ATC */
2834 register_bank(fir_base, 4);
98b77773
DT		 2835 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2836 fir_base + IRCC_ATC);
2837
2838 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2839 !time_after(jiffies, jiffies_timeout))
2840 /* empty */;
2841
2842 if (val)
1da177e4 2843 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
98b77773 2844 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2845}
2846
2847/*
2848 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2849 *
2850 * Probe transceiver smsc-ircc ATC circuitry
2851 *
2852 */
2853
2854static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2855{
2856 return 0;
2857}
2858
2859/*
2860 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2861 *
527b6af4 2862 * Set transceiver
1da177e4
LT		 2863 *
2864 */
2865
2866static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2867{
98b77773 2868 u8 fast_mode;
527b6af4 2869
98b77773
DT		 2870 switch (speed) {
2871 default:
2872 case 576000 :
527b6af4 2873 fast_mode = 0;
1da177e4 2874 break;
98b77773
DT		 2875 case 1152000 :
2876 case 4000000 :
1da177e4
LT		 2877 fast_mode = IRCC_LCR_A_FAST;
2878 break;
1da177e4
LT		 2879 }
2880 register_bank(fir_base, 0);
98b77773 2881 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2882}
2883
2884/*
2885 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2886 *
527b6af4 2887 * Probe transceiver
1da177e4
LT		 2888 *
2889 */
2890
2891static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2892{
2893 return 0;
2894}
2895
2896/*
2897 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2898 *
527b6af4 2899 * Set transceiver
1da177e4
LT		 2900 *
2901 */
2902
2903static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2904{
98b77773 2905 u8 fast_mode;
527b6af4 2906
98b77773
DT		 2907 switch (speed) {
2908 default:
2909 case 576000 :
527b6af4 2910 fast_mode = 0;
1da177e4 2911 break;
98b77773
DT		 2912 case 1152000 :
2913 case 4000000 :
1da177e4
LT		 2914 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2915 break;
527b6af4 2916
1da177e4
LT		 2917 }
2918 /* This causes an interrupt */
2919 register_bank(fir_base, 0);
98b77773 2920 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2921}
2922
2923/*
2924 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2925 *
527b6af4 2926 * Probe transceiver
1da177e4
LT		 2927 *
2928 */
2929
2930static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2931{
2932 return 0;
2933}
2934
2935
2936module_init(smsc_ircc_init);
2937module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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